HCGD16589EB_技术文档

10 Gbit/s

Transmitter MUX

with Re-timing

GD16585/GD16589

(FEC)

an Intel company

Preliminary

General Description

Features

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GD16585 and GD16589 are transmitter

chips used in SDH STM-64 and SONET

OC-192 optical communication systems.

data stream is re-timed by the high-

speed clock from the VCO.

PLL based CMU with on-chip 10 GHz

or 10.66 GHz VCO.

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The parallel input interface features

GIGA’s unique self-synchronizing dy-

namic phase alignment scheme that al-

lows both:

16:1 Multiplexer with a last stage

re-timing.

The device is available in two versions:

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GD16585 for 9.5328 Gbit/s.

GD16589 for 10.66 Gbit/s with

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OIF99.102.5 compliant timing .

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Forward Error Correction (FEC).

Except the different operating bit rate the

two versions are functional identical.

Source synchronous counter clocking

for OIF99.102.5 interfaces.

Forward clocking with phase nulling

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LVDS compatible parallel data and

clock inputs

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and jitter clean-up of the clock.

These schemes enable the serializer to

absorb output delay variations from the

upstream System ASIC without use of

initialization or reset.

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The transmitter integrates the main func-

tions of the serializer which are:

CML compatible serial data output.

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u

Clock Multiply Unit (CMU)

16:1 Multiplexer in a single monolithic

IC.

155 MHz or 622 MHz reference clock

input (selectable).

u

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The data and clock inputs to the MUX

are LVDS and the output data is CML

compatible.

Divide by 16 clock output.

The CMU consists of Phase Locked

Loop (PLL) controlled from an external

reference clock. The PLL characteristics

are controlled by an external loop filter al-

lowing the user to optimize the jitter

perfomance of the device.

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PLL out of lock detector.

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The device operates from a dual -5.2 V

and +3.3 V power supply. The power dis-

sipation is 2.2 W, typical.

Dual supply operation: -5.2 V and

+3.3 V

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Low power dissipation: 2.2 W (typ.).

The 16:1 Multiplexer accepts 16 parallel

input bits at 622.88 Mbit/s (or 666 Mbit/s)

that are serialized into a 9.9538 Gbit/s (or

10.66 Gbit/s) data stream. The serialized

The device is manufactured in a Silicon

Bipolar process and packaged in an 132

balls 13 × 13 mm Ceramic/Plastic Ball

Grid Array (CBGA).

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Available in three package versions:

–

EB: 132 ball (16 mill) Ceramic

BGA 13 × 13 mm

EF: 132 ball (20 mill) Ceramic

BGA 13 × 13 mm

FB: 132 ball (20 mill) Plastic

BGA 13 × 13 mm

DI0

DIN0

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VCUR

FF

16:1

OUT

OUTN

Parallel

Input Data

Available in two versions:

Multiplexer

–

GD16585 for 10 Gbit/s

GD16589 for 10.66 Gbit/s

DI15

DIN15

VCO

VCTL

Timing

Control

SEL1

SEL2

Phase

Applications

Selector

Phase

CKOUT

CKOUTN

PCTL

Frequency

Detector

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Telecommunication systems:

(PHIGH)

(PLOW)

–

SDH STM-64

CKI

CKIN

PFCX

SONET OC-192

Optical Transport Networking

(OTN)

NLDET

–

FEC applications

TCK

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Fibre optic test equipment.

PCTLX

SGNX

SEL3

REFCK/N VCC VDD VDDO VDDA VEE

Data Sheet Rev.: 13

Functional Details

The main function of GD16585/GD16589

is as transmitter in STM-64 /OC-192 and

OTN optical communication systems.

The timing relation is OIF99.102.5 com-

plaint with SEL1,2 = 1,1 (0 V).

The PCB layout of the loop filter and the

connecting lines between PCTL and

VCTL are critical for the jitter perfor-

mance of the device. The external com-

ponents and the artwork should be

placed very close to the pins at

GD16585.

The select inputs (SEL1-3 and SGNX)

are low-speed ECL compatible inputs,

which can be connected directly to the

negative supply rails (0 / -5.2 V).

It integrates:

u

Voltage Controlled Oscillator (VCO)

Phase and Frequency Detector (PFD)

u

16:1 Multiplexer

Re-timing of output data.

u

If the PHIGH and PLOW outputs are not

used they must be shorted to VDD (0 V),

please refer to Figure 1.

u

Phase nulling circuit for interfacing in-

put data and clock.

Bit Order

The parallel data input is multiplexed with

DI0 as the first sent bit, DI1 as the sec-

ond sent bit and with DI15 as the last

sent bit in a 16 bit frame.

VCO

The Outputs

Note:

This bit naming covention is

opposite to OIF99.102.5

The VCO is an LC-type differential oscil-

lator controlled by pin VCTL and with a

tuning range of ±5 %. The VCO and the

clock divider circuit generate the clock

signals and load pulses needed for

multiplexing and timing control.

The output of the MUX stage is retimed

by the 10 GHz (or 10.66 GHz) clock and

the output driver is a Current Mode Logic

(CML) output with internal 50 W termina-

tion resistors.

For OIF interfaces the data pins should

be connected as shown in the following

table.

The serial output driver is internally termi-

nated with 50 W resistors to 0 V. The out-

put should be terminated externally with

50 W at the receive end and should be

used differential. Both OUT and OUTN

are best terminated with the same load

resistor e.g. 50 W, an asymmetric loading

will decrease the performance of the out-

put due to reflections.

Input Pin:

OIF:

With the VCTL voltage at -3 V the VCO

frequency is fixed at 9.953 GHz (for

GD16585) and by changing the voltage

from 0 to –5.2 V the frequency is con-

trolled from 9 GHz to 10.2 GHz. The

modulation bandwidth of VCTL is

90 MHz.

DI0/DIN0

TXDATA15_P/N

(MSB)

DI1/DIN1

TXDATA14_P/N

TXDATA13_P/N

TXDATA12_P/N

TXDATA11_P/N

TXDATA10_P/N

TXDATA9_P/N

TXDATA8_P/N

TXDATA7_P/N

TXDATA6_P/N

TXDATA5_P/N

TXDATA4_P/N

TXDATA3_P/N

TXDATA2_P/N

TXDATA1_P/N

DI2/DIN2

DI3/DIN3

DI4/DIN4

Both outputs OUT/OUTN are not ESD

protected and extra precautions should

be taken when handling the outputs (the

internal 50 W resistor provides some

ESD hardness making the ouput low

impedance).

The Reference Clock

DI5/DIN5

DI6/DIN6

The PFD is made with digital set/reset

cells giving it a true phase and frequency

characteristic. The reference clock

(REFCK/REFCKN) to the PFD is 155 or

622 MHz selectable by SEL3.

DI7/DIN7

DI8/DIN8

A divide by 16 clock output from the

CMU is available at CKOUT/N for jitter

measurement and test purpose. These

outputs are differential open collector

with a 8 mA output current. They are ter-

minated externally with resistors and can

be terminated to the positive 3.3 V

DI9/DIN9

The reference clock input is a CML input

with 50 W internal termination resistors.

The reference clock should be used dif-

ferential for obtaining lowest clock jitter.

DI10/DIN10

DI11/DIN11

DI12/DIN12

DI13/DIN13

DI14/DIN14

DI15/DIN15

The PLL synchronizes the VCO to the

external reference clock. Spectral noise

from the reference clock, within the PLL

bandwidth, will be multiplied and added

to the serial output by the divider ratio

between the VCO and reference clock

i.e. N = 16 or in terms of phase noise as

20Log(16) = 24 dB (or 36 dB at N = 64).

A low noise reference clock with low

clock jitter is required in order to fulfill the

ITU-T jitter requirements.

supply. The clock outputs should be ter-

minated even though they are not used.

PLL out of lock detect signal (NLDET) is

provided as a status signal of the PLL. It

compares the VCO clock with the refer-

ence clock and is low whenever the VCO

is locked to the reference clock. The

NLDET is an open collector output and

must be terminated by an external resis-

tor.

TXDATA0_P/N

(LSB

CKI

TXCLK_P

TXCLK_N

CKIN

Loop Filter for the CMU

Inputs

The Output Voltage Control

An external passive loop filter is used,

consisting of a resistor and a capacitor

driven from the PCTL pin, which outputs

the phase and frequency information

from the PFD. The values of the external

components determines the

characterisitcs of the PLL e.g. bandwidth

and transfer function. For recommended

loop filter values see Figure 1.

The parallel data (DIx/DINx) and clock

(CKI/CKIN) inputs are LVDS compatible

with internal differential 100 W resistors.

The serial output voltage swing at

OUT/OUTN is controlled by VCUR in the

range from 0.1 V to 0.8 V. The voltage

swing is increased by increasing the

VCUR voltage and the output is off at

voltages below VEE +2 V.

The set-up and hold time between input

clock and data is selectable in four set-

tings by SEL1-2.

Data Sheet Rev.: 13

GD16585/GD16589

Page 2 of 17

If no adjustement is needed the VCUR

can be lefted open.

Thermal Condition

With AC coupled outputs the VCUR pin

must not be directly connected to 0 V

which may cause the output stage to

saturate deteriorating the eye-diagram.

The component dissipates 2.2 W with a

–5.2 V and +3.3 V voltage supply.

The die is mounted in a cavity on a metal

pad directly connected to the center balls

(E4-9, F4-9, G4-9, and H4-9).

Refer to Figure 1 for the recommended

set-up of VCUR.

It is important to have a good thermal

connection from the center balls of the

package to the ambient environment to

ensure the best thermal conditions.

Timing to the System ASIC

The component supports source

synchronouse clocking for OIF99.102.5

interface (311 MHz clock mode is not

supported) and forward clocking with

phase nulling and jitter clean-up of the

reference clock. With a OIF interface a

phase adjusted source clock is feed back

to the System ASIC and data and clock

are feed forward to the high-speed MUX.

Note:

To obtain T_CASE< 70°C,

the PGBA (compared to the

CBGA) requires additional

cooling on the case,

For details, please refer to

Application Note “ PBGA -

Thermal data....”.

The phase difference between the for-

ward clock (CKI/CKIN) and the internal

load pulse is detected by the Phase and

Frequency Detector (PFCX) and the

Phase Information (PCTLX) are use to

control the phase and frequency of the

external VCXO (622 MHz). The phase

adjusted output clock of the VCXO can

be used either as a source (counter)

clock to the System ASIC (OIF99.102.5

in 622 MHz clock mode) or as a jitter

clean reference clock (REFCK/N) to the

on-chip CMU.

10.66 Gbit/s Application

A version of the transmitter with a bit rate

of 10.66 Gbit/s for Optical Transport Net-

working (OTN) and Forward Error Cor-

rection (FEC) application is available.

The part number is GD16589.

The functionality and the pin-out are

identically to the GD16585.

The center frequency of the VCO

(10.66 GHz) is the only difference to the

GD16585.

The phase information at PCTLX is fil-

tered in an external low pass filter con-

sisting of a capacitor and a resistor. For

recommended component values, please

refer to Figure 1.

Package

GD16585 and GD16589 are packaged in

an 132 ball Ceramic/Plastic BGA

(13×13 mm). For the package outline,

please refer to Figure 14 and 15.

In ceramic packages following pin pairs

are individually shorted inside the pack-

age and mainly used as power pins:

C3/D3, C4/D4, C5/D5, C8/D8, C9/D9,

C10/D10, J3/K3, J4/K4, J5/K5, J8/K8,

J9/K9, and J10/K10, please refer to

“Package Pinout” Figure 8 on page 8.

Data Sheet Rev.: 13

GD16585/GD16589

Page 3 of 17

Application

0V

+3.3V

VCC

Framer

VDD/VDDA

(VDDO)

16

DI0..15

DIN0..15

16

OUT

OUTN

10Gbit/s

Output

CKI

CKIN

0V

VCO

PCTLX

1kW

-5.2V

10nF

10kW

VCUR

REFCK

4.7kW

REFCKN

500W

-5.2V

VCC

50W

CKOUT

100nF

330W

NLDET

CKOUTN

+

-

Out of

Lock

VCC

0V

VDD

SEL1

SEL2

PHIGH

PLOW

622MHz

155MHz

0V

SEL3

2.2kW 33nF

-5.2V

0V

VCTL

PCTL

VDDA

SGNX

-5.2V

VEE

-5.2V

Figure 1. Application Information, OIF interface to the Framer.

For all VDD pins refer to Pin List

Pin D1 Pin D2

VDD

Pin J8 Pin K8

C

10mF

VEE

Pin C2

A7

K5

Pin D11

C

Pin M3

VDDO

VEE

VDDA

10mF

VCC

VDD

C

10mF

C is 10nF parallel with 100pF.

VEE, VCC, VDDA pins refer to Pin List

Figure 2. De-coupling of the Power Supply

Data Sheet Rev.: 13

GD16585/GD16589

Page 4 of 17

10 Gbit/s Output Interface

GD16585/GD16589

0V

Driver

50W

OUT

50W MSL

OUTN

VCUR

-5.2V

Figure 3. 10 Gbit/s outputs (OUT/OUTN), DC coupled.

GD16585/GD16589

0V

Driver

50W

OUT

100nF

OUTN

50W MSL

VCUR

-5.2V

Figure 4. 10 Gbit/s outputs (OUT/OUTN), AC coupled.

Note:

With AC coupled outputs VCUR must not be connected directly to 0 V.

Data Sheet Rev.: 13

GD16585/GD16589

Page 5 of 17

622 Mbit/s Output Interface

(0V or 3.3V)

GD16585

50W

50W MSL

8mA

-5.2V

Figure 5. Open collector output.

Open collector outputs should always be terminated at the receiver end, by preferably 50 W.

622 Mbit/s Input Interface

GD16584 or

GD16585

VCC (+3.3V)

LVDS Output

50W MSL

100W

VEE (-5.2V)

Figure 6. LVDS compatible input.

Reference Clock Input

GD16585

0V

50W

-5.2V

500W

REFCK

100nF

REFCKN

500W

-5.2V

Figure 7. Reference Clock Input (REFCK/REFCKN), Differential AC Coupled.

Data Sheet Rev.: 13

GD16585/GD16589

Page 6 of 17

Pin List

Mnemonic:

Pin No.:

Pin Type:

Description:

DI0,

DI1,

DI2,

DI3,

DI4,

DI5,

DI6,

DI7,

DI8,

DI9,

DIN0

C7, D7

A8, B8

LVDS In

Data input, differential 622 Mbit/s. Multiplexed to serial output

starting with DI0, DI1...DI15.

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

DIN8

DIN9

A9, B9

Note:

The bit naming convention is opposite to OIF99.102.5:

DI0 is MSB. Please refer to item “Bit Order” on page 2.

B10, A11

C11, C12

D12, E12

G11, H12

J12, J11

L9, M9

L8, M8

DI10, DIN10

DI11, DIN11

DI12, DIN12

DI13, DIN13

DI14, DIN14

DI15, DIN15

L6, K6

M5, L5

M4, L4

L3, M2

K3, L2

L1, K2

REFCK, REFCKN

SEL1, SEL2

B5, A6

A3, B4

CML In

ECL In

Reference clock input, differential 155 MHz or 622 MHz.

Select the set-up and hold time beetwen the data and clock inputs

in four settings. For setting, please refer to Figure 13 and table on

page 14.

When left open, the inputs are pulled to “1” (VDD).

SEL3

A4

ECL In

Select the reference clock frequency.

0

1

155 MHz

622 MHz

When left open, the input is pulled to “1” (VDD).

CKI, CKIN

B6, B7

H1, E1

LVDS In

CML Out

Data clock input.

OUT, OUTN

Data output, differential 10 Gbit/s. No internal ESD output pro-

tection.

CKOUT, CKOUTN

L12, L11

Open Collector

Clock output, differential 622 MHz. Always terminate by 50 W to

VDD.

PCTL

C3

A1

Analogue Out

Open Collector

Analogue In

Open Collector

ECL In

Charge pump output for CMU PLL.

PCTLX

(PHIGH, PLOW)

VCTL

Charge pump output from PFCX to external VCXO.

Not used. Always terminate to VDD.

B3, C4

B1

VCO input voltage control.

VCUR

K1

Output voltage control.

NLDET

SGNX

C6

No Lock DETect output. Always terminate with a resistor to VDD.

Selects between positive and negative VCXO constant.

K12

0

1

Positive VCXO constant

Negative VCXO constant

When left open, the input is pulled to “1” (VDD).

Used for test purpose. Connect to VDD.

Digital Ground 0 V.

TCK

VDD

C1

ECL In

PWR

A2, A5, D1-2, D6,

E4-9, F1-2, F4-9,

F11, G1-2, G4-9,

H4-9, J1-2, J6, J8,

K8

VDDA

VDDO

A7, C5 (D5),

J5 (K5)

PWR

PLL Ground 0 V.

C2

VCO Ground 0 V. For test purpose connect to VEE.

Data Sheet Rev.: 13

GD16585/GD16589

Page 7 of 17

Mnemonic:

Pin No.:

Pin Type:

Description:

VEE

B2, C8, C10, D8,

D10, J4, J9, K4, K9

PWR

-5.2 V Digital supply voltage.

VCC

NC

D11, J7, J10 (K10),

M3

PWR

+3.3 V supply voltage for LVDS I/O.

A10, A12, B11-12,

C9, D9, F12, G12,

K7, K11, L7, L10,

M1, M6, M7,

Not Connected. Reserved for future use.

M10-12

NC

D3-4, J3

DO NOT CONNECT.

Package Pinout

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

1

2

3

4

5

6

7

8

9

10

11

12

(empty) = VDD

= Internally shorted in the package

Figure 8. Packages EB and EF Pinout. Top view seen through the package.

Data Sheet Rev.: 13

GD16585/GD16589

Page 8 of 17

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

1

2

3

4

5

6

7

8

9

10

11

12

(empty) = VDD

= Internally shorted in the package

Figure 9. Package FB Pinout. Top view seen through the package.

Data Sheet Rev.: 13

GD16585/GD16589

Page 9 of 17

Maximum Ratings

These are the limits beyond which the component may be damaged.

All voltages in table are referred to VDD/VDDA.

All currents are defined positive out of the pin.

VDD is 0 V or GND

Symbol:

V_EE

Characteristic:

Conditions:

MIN.:

TYP.:

MAX.:

UNIT:

V

Negative Supply

-6

V_CC

Positive Supply

+4

V_CC+0.5

24

V

V_ILVDS

I_ILVDS, CML

V_ICML

V_OCML

V ESD

LVDS Input Voltage

LVDS and CML Output Current

CML Input Voltage

CML Output Voltage

Static Discharge Voltage

0

V

Note 1

-24

mA

V

V_EE+3

0.5

V

HBM, Note 3

CDM, Note 4

Note 2

500

V

50

V

T_J

Junction Temperature

Storage Temperature

-55

-65

+125

^oC

T_S

Note 1: Nominal supply voltages.

Note 2: The maximum temperature equals a maximum case temperature of 105 °C (top side) with the device mounted on the

GD90584/585 Evaluation Board.

Note 3: Human Body Model: MIL 883D 3015.7 standard.

Note 4: Charge Device Model.: JESD2-C101 standard.

Data Sheet Rev.: 13

GD16585/GD16589

Page 10 of 17

DC Characteristics

T_CASE* = 0 °C to 70 °C. VEE = -5.2 V. VCC = +3.3 V. VDD is 0 V or GND.

All voltages in table are referred to VDD.

All currents are defined positive out of pin.

Symbol:

V_EE

Characteristic:

Conditions:

MIN.:

-5.46

TYP.:

-5.2

+3.3

400

MAX.:

-4.94

3.465

500

UNIT:

V

Negative Supply Voltage

V_CC

Positive Supply for LVDS I/O

Negative Supply Current

+3.135

V

I_EE

mA

mV

V

I_CC

Positive Supply Current

-21

-17

V_IHLVDS

V_ILLVDS

V_IVRLVDS

R_INLVDS

V_OHOC

V_OLOC

I_OHOC

I_OLOC

V_OHOUT

V_OLOUT

LVDS Input Voltage High, (differential)

LVDS Input Voltage Low, (differential)

LVDS Input Voltage Range

LVDS Input Resistor Termination

Open Collector Output Voltage High

Open Collector Output Voltage Low

Open Output Current High

Open Output Current Low

100

-100

2.4

0.8

80

DC

100

0

120

W

Note 1

-0.05

-0.5

-0.1

-9

+0.05

-0.3

+0.1

-7

V

Note 1

-0.4

0

V

Note 1

mA

V

Note 1

-8

OUT/OUTN Voltage High

Note 1, 10 MHz

-0.1

-0.05

-0.7

+0.05

-0.5

OUT/OUTN Voltage Low

-0.8

Note 3

V

I_OHOUT

I_OLOUT

OUT/OUTN Current High

OUT/OUTN Current Low

Note 1

Note 2

0

mA

V

-14

V_IHSEL1-3,SGNX SEL1-3, SGNX Input Voltage High

V_ILSEL1-3, SGNX SEL1-3, SGNX Input Voltage Low

0

V_EE+ 2

V_EE+ 0.8

V_EE

V

Note 1: Output externally terminated by 50 W to 0 V.

Note 2: SEL1-3 and SGNX can be connected directly to VDD or VEE.

Note 3: V_OLOUT MIN. may require VCUR adjustment, VCUR > -1 V.

*:

T_CASEmeasured at the center of the top.

Data Sheet Rev.: 13

GD16585/GD16589

Page 11 of 17

AC Characteristics, General

T_CASE*= 0 °C to 70 °C, VEE = -5.2 V. VCC = +3.3 V.

Symbol:

Characteristic:

Conditions:

MIN.:

TYP.:

MAX.:

UNIT:

J_TRF

Jitter transfer

f < 8 MHz

Note 1

0.0

0.1

dB

J_GEN

V_OUT

Jitter generation

12 kHz < f < 80 MHz

Note 1

0.1

UI_PP

10 Gbit/s output voltage

Note 3, VCUR open

-0.5 V < VCUR < 0 V

550

800

650

-10

mV_PP

G OUT

OUT/OUTN output reflection coefficient Note 2

Reference clock jitter REFCK/REFCKN,

f < 10 MHz

dB

F REFCK

+5

ps_PP

D _CYCLE,CKOUT/N CKOUT/CKOUTN duty cycle

Differential

45

40

55

60

%

D _CYCLE,REFCK

F _MAX,REFCK

REFCK duty cycle

Maximum REFCK/N frequency

GD16585

GD16589

635

680

MHz

Note 1: With the recommended loop filter.

Note 2: From DC to 6 GHz, measured on the GD90584/585 Evaluation Board.

Note 3: The output voltage is adjustable by pin VCUR.

*:

T_CASEmeasured at the center of the top.

Data Sheet Rev.: 13

GD16585/GD16589

Page 12 of 17

AC Characterisitcs, Source Synchronous Clocking - OIF99.102.5

T_CASE* = 0 °C to 70 °C, VEE = -5.2 V.

Framer

GD16585

OIF99.102.5

TXDATA

32

DI0..15

DIN0..15

TXCLK

2

CKI

CKIN

VCXO

2

TXCLK_SRC

PCTLX

-5.2 V

155/622 MHz

2

REFCK

REFCKN

SEL1

SEL2

Figure 10. OIF interface.

CKI

DI0-15

t

H

t

S

Figure 11. Timing relation between input data and clock.

Symbol:

Characteristic:

DI0-15 setup

DI0-15 hold

Conditions:

MIN.:

TYP.:

MAX.:

125

UNIT:

ps

t_S

t_H

SEL1 = SEL2 = “1”

175

ps

Note:

*:

The setup and hold time is defined from the rising edge of CKI. The setup time is positive before the edge and the hold

time is positive after the edge.

T_CASEmeasured at the center of the top.

Data Sheet Rev.: 13

GD16585/GD16589

Page 13 of 17

AC Characteristics, Forward Clocking to System ASIC

T_CASE*= 0 °C to 70 °C, VEE = -5.2 V.

System ASIC

GD16585

TXDATA

TXCLK

32

DI0..15

DIN0..15

2

CKI

CKIN

REFCK

REFCKN

VCXO

PCTLX

-5.2 V

Figure 12. Forward clocking with phase nulling circuit.

CKI

CKOUT

t

D

DI0-15

t

H

t

0,1

t

1,0

t

0,0

t

S

1,1

H

S

H

S

H

Figure 13. Timing relation between input data and clock.

Symbol:

t_S,11

t_H,11

t_S,00

t_H,00

t_S,10

t_H,10

t_S,01

t_H,01

t_D

Characteristic:

Conditions:

MIN.:

TYP.:

MAX.:

125

UNIT:

ps

DI0-15 setup time

DI0-15 hold time

(SEL1,SEL2) = (1,1)

(SEL1,SEL2) = (0,0)

(SEL1,SEL2) = (1,0)

(SEL1,SEL2) = (0,1)

175

ps

DI0-15 setup time

DI0-15 hold time

560

ps

-260

930

ps

DI0-15 setup time

DI0-15 hold time

ps

-630

1350

-1050

TBD

ps

DI0-15 setup time

DI0-15 hold time

ps

Delay between CKI and CKOUT

ps

Note:

*:

The setup and hold time is defined from the rising edge of CKI. The setup time is positive before the edge and the hold

time is positive after the edge.

SEL3 = “0”

T_CASEmeasured at the center of the top.

Data Sheet Rev.: 13

GD16585/GD16589

Page 14 of 17

Package Outline

EF - Package

Figure 14. Package 132 ball Ceramic BGA (EB and EF package).

Data Sheet Rev.: 13

GD16585/GD16589

Page 15 of 17

Figure 15. Package 132 ball Plastic BGA (FB package).

Data Sheet Rev.: 13

GD16585/GD16589

Page 16 of 17

Device Marking

GD16585-<XX>

GD16589-<XX>

Figure 16. Device marking. Top view.

Ordering Information

To order, please specify as shown below:

Product Name:

GD16585-EB

GD16585-EF

GD16585-FB

GD16589-EB

GD16589-EF

GD16589-FB

Version:

Package Type:

Intel Order Number: Case Temperature

Range:

10 Gbit/s

132 ball (16 mil) Ceramic BGA HCGD16585EB

MM# 835479

0...70 °C

10 Gbit/s

132 ball (20 mil) Ceramic BGA HCGD16585EF

MM# 837348

10 Gbit/s

132 ball (20 mil) Plastic BGA

RCGD16585FC

MM# TBD

10.66 Gbit/s

132 ball (16 mil) Ceramic BGA HCGD16589EB

MM# 835481

132 ball (20 mil) Ceramic BGA HCGD16589EF

MM# 837350

132 ball (20 mil) Plastic BGA

RCGD16589FC

MM# TBD

GD16585/GD16589, Data Sheet Rev.: 13 - Date: 14 November 2001

an Intel company

Mileparken 22, DK-2740 Skovlunde

Denmark

Phone : +45 7010 1062

Distributor:

The information herein is assumed to be

reliable. GIGA assumes no responsibility

for the use of this information, and all such

information shall be at the users own risk.

Prices and specifications are subject to

change without notice. No patent rights or

licenses to any of the circuits described

herein are implied or granted to any third

party. GIGA does not authorise or warrant

any GIGA Product for use in life support

devices and/or systems.

Fax : +45 7010 1063

E-mail : sales@giga.dk

Web site : http://www.intel.com/ixa

An Intel company

Please check our Internet web site

for latest version of this data sheet.


型号：	HCGD16589EB
厂家：	INTEL
描述：	Mux/Demux, 1-Func, Bipolar, CBGA132, 13 X 13 MM, CERAMIC, BGA-132 ATM 异步传输模式电信电信集成电路
文件：	总17页 (文件大小：183K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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