IMC002FLSCSBXXXXX [INTEL]
Flash Card, 128KX16, 100ns, PC CARD-68;
| 型号： | IMC002FLSCSBXXXXX |
| 厂家： | 
INTEL |
| 描述： | Flash Card, 128KX16, 100ns, PC CARD-68 PC |
| 文件： | 总29页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
E
5 VOLT VALUE SERIES 100
FLASH MEMORY CARD
iMC002FLSC, iMC004FLSC, iMC008FLSC, iMC016FLSC
Low-Cost Linear Flash Card
Automated Program and Erase
Algorithms
28F008SA Command Set
Single Supply: 5 Volt Operation
FAST Read Performance
100 ns Maximum Access Time
(2-, 4-, 8-Mbytes)
State-of-the-Art 0.4 µm ETOX™ V Flash
Technology
150 ns Maximum Access Time
(16-Mbytes)
100,000 Erase Cycles per Block
64-Kword Blocks
x16 Data Interface
PC Card Standard Type 1 Form Factor
High-Performance Random Writes
8 µs Typical Word Write
The Intel® Value Series 100 card offers a low cost removable solid-state storage solution for code and data
storage, high-performance disk emulation, and applications in mobile PCs and dedicated embedded
applications. Manufactured with Intel® FlashFile™ memory, this card takes advantage of a revolutionary
architecture that provides innovative capabilities, automated program/erase algorithms, reliable operation and
very high read/write performance.
The flash memory card provides one of the lowest cost, highest performance nonvolatile read/write solutions
for solid-state storage applications. These applications are enhanced further with this product’s
symmetrically-blocked architecture, extended MTBF, and 5 Volt operation.
The flash memory card can be used as a simple x16 linear array of flash devices. The PC Card form factor
offers an industry-standard pinout, removable linear flash memory, and the ability to upgrade system memory
software without changing the board layout.
NOTE: This document formerly known as Value Series 100 Flash Memory Card 2-, 4-, 8-, 16 Megabytes.
May 1999
Order Number: 290546-006
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The iMC002FLSC, iMC004FLSC, iMC008FLSC, iMC016FLSC may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-4725
or call 1-800-879-4683
or visit Intel’s website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1997, 1998, 1999
CG-041493
*Other brands and names are the property of their respective owners
E
iMC002/004/008/016FLSC
CONTENTS
PAGE
PAGE
1.0 SCOPE OF DOCUMENT.................................5
6.0 PC CARD INFORMATION STRUCTURE..... 16
2.0 PRODUCT OVERVIEW ...................................5
7.0 SYSTEM DESIGN CONSIDERATIONS........ 19
7.1 Power Supply Decoupling.......................... 19
7.2 Power-Up/Down Protection........................ 19
3.0 VALUE SERIES 100 CARD ARCHITECTURE
OVERVIEW.....................................................5
7.3 RDY/BSY# and Program/Block Erase
Polling ...................................................... 19
3.1 Card Pinout and Pin Description...................5
4.0 CARD CONTROL LOGIC..............................10
4.1 Bus Operations ..........................................10
4.1.1 Read....................................................10
4.1.2 Output Disable.....................................10
4.1.3 Standby ...............................................10
4.1.4 Intelligent Identifier Operation..............10
4.1.5 Write....................................................10
4.2 Address Decode Logic ...............................11
4.3 Data Control...............................................11
7.4 VCC, VPP, RESET Transitions and the
Command/Status Registers...................... 19
8.0 ELECTRICAL SPECIFICATIONS................. 20
8.1 Absolute Maximum Ratings....................... 20
8.2 Operating Conditions................................. 20
8.3 Capacitance .............................................. 20
8.4 DC Characteristics..................................... 21
8.5 AC Characteristics..................................... 22
8.5.1 Read Operations: Common Memory... 22
8.5.2 Write Operations: Common Memory... 24
8.5.2 Power-Up/Power-Down....................... 26
8.6 Erase and Data Write Performance ........... 27
5.0 COMMAND DEFINITIONS ............................12
5.1 Read Array Command (FFFFH) .................12
5.2 Intelligent Identifier Command (9090H) ......12
5.3 Read Status Register Command (7070H) ..13
5.4 Clear Status Register Command (5050H) ..13
9.0 PACKAGING ................................................ 28
10.0 ORDERING INFORMATION....................... 29
11.0 ADDITIONAL INFORMATION .................... 29
5.5 Erase Setup/Erase Confirm Commands
(2020H, D0D0H)........................................14
5.6 Erase Suspend/Erase Resume Commands
(B0B0H, D0D0H).......................................15
5.7 Program Commands (4040H or 1010H).....15
5.8 Word Write Suspend Command.................15
5.9 Set Block Lock-Bit Command.....................15
5.10 Clear Block Lock-Bits Command..............16
3
PRELIMINARY
iMC002/004/008/016FLSC
E
REVISION HISTORY
Date of
Revision
Version
Description
02/29/96
01/23/97
-001
-002
Original version
Added Specifications for 16-Mbyte Card
Added 16-Mbyte Tuples
Added I
for 16-Mbyte Card
CCSL
Changed A from N.C. to Active
24
Changed Interface to CMOS only–removed Table 9.3 TTL Interfacing
Changed DC specification and text to reflect conversion to the 28F0xxS5 family
06/15/97
12/01/97
-003
-004
Changed timing specifications for 16-Mbyte card
Added 24- and 32-Mbyte cards—they use the 28F016S5 component
Changed components used in 4-, 8- and 16-Mbyte densities to 28F016S5
Changed components used in 2-Mbyte density to 28F008S5
Increased ICCMAX
Decreased ICCS
Added Block Locking and Program Suspend
Removed 24- and 32-Mbyte cards
Changed title bullet to identify TWO speed versions (100 & 150 ns) for FAST
read performance based on memory density
Corrected Revision -003 Revision History by changing component references
In Section 2.0, added a reference to Figure 1
Clarified Section 3.0 wording relating to concurrent operations with multiple
components
Altered Figure 1 to show A22 as the least significant card address signal to the
Card Control Logic
In Table 7.0 at location 74H of CIS memory changed the value from 33H to 32H
for the 32-MB card
In Section 8.1 (Absolute Maximum Ratings) changed the lower limit of the
supply voltage range from –0.5 V to –0.2 V
In note 2 of Section 8.1 (Absolute Maximum Ratings) removed 20 ns overshoot
and undershoot specifications
Altered note references and added note 4 to the DC Characteristics table of
Section 8.4
Changed the specified VCC Standby Current and VCC Sleep Current values in
the DC Characteristics table of Section 8.4
Added a specification for tPHWL (Power-Down Recovery to WE# Going Low) to
the common memory write timing table of Section 8.5.2
Removed the “Write Protect” switch item and details from the figure in Section
9.0
As a non-material change, clarified or corrected various defective or ambiguous
wording
12/01/98
05/06/99
-005
-006
Changed name of document from Value Series 100 Flash Memory Card 2-, 4-,
8-, 16 Megabytes
Changed references of RESET pin to RST pin.
4
PRELIMINARY
E
iMC002/004/008/016FLSC
Typical flash memory components only support a
single operation at a time. Only one block in a
28F0XXS5 can be erased, or only one location
programmed, at a time. Since a Value Series 100
contains multiple devices, it is possible to perform
1.0 SCOPE OF DOCUMENT
This datasheet provides
a card architecture
overview, all AC and DC characteristics and
command definitions.
multiple concurrent operations in the card.
A
location in one component can be read while a
location in another component is being
programmed. (However, all DC characteristics
presented herein assume that only one operation
is being performed at a time, and that all other
components on the card are in stand-by.)
2.0 PRODUCT OVERVIEW
The 2-Mbyte card consist of two 28F008S5 flash
memories. The 4-, 8-, or 16-Mbyte cards consist of
two, four, or eight 28F016S5 flash memories.
Figure 1 provides a functional block diagram of the
16-Mbyte card. All 28F008S5 and 28F016S5
memory components (referred to herein by the
generic 28F0XXS5 part number) are made up of
64-Kbyte, individually erasable blocks. Therefore,
the 2-, 4-, 8-, or 16-Mbyte cards contain 32, 64,
128 or 256 independently-erasable, 64-Kbyte
blocks.
A user algorithm which would rely on a memory
array based on a specific memory component
capacity would be incompatible among all card
types and component selections. In the future, the
Value Series may use higher capacity memory
devices. Therefore, algorithms that are based on a
particular organization may not be compatible with
these newer, more cost-effective cards.
When accessed as 16-bit words, the blocks
appear to be 128 Kbytes. The high byte is in one
64-Kbyte block, the low byte in another. In this
mode, the 2-, 4-, 8-, or 16-Mbyte cards contain 16,
32, 64, or 128, independent 128-Kbyte blocks.
The Card information Structure (CIS) for the Value
Series 100 card is stored in Block 0 of the flash
memory to reduce the attribute memory cost
overhead of an EEPROM or ASIC. In embedded
applications, a CIS may not be required by the
system and the entire memory array can be used
by the system.
At the device level, internal algorithm automation
allows execution of program and erase operations
using a two-program command sequence. The
automated program/erase algorithms ensure that
data is reliably written in the least amount of time.
3.1
Card Pinout and Pin
Description
The memory card interface supports the PC Card
Standard, supported by Personal Computer
Memory Card Industry Association (PCMCIA) and
Japanese Electronics Industry Development
Association (JEIDA) 68-pin card format. The Value
Series 100 card meets all PCMCIA/JEIDA Type 1
mechanical specifications.
The 68-pin PC Card format provides the system
interface for the Value Series 100 card (see
Tables 1 and 2). The detailed specifications for
this interface are described in the PC Card
Standard Specification. The Value Series 100 card
product family
conforms
to
the
pinout
requirements of PCMCIA Versions Release 1.0,
Release 2.0 and Release 2.01 as well as the PC
Card Standard.
3.0 VALUE SERIES 100 CARD
ARCHITECTURE OVERVIEW
A Value Series 100 card is an array of flash
memory devices in a PC Card form factor. Pairs of
28F008S5 or 28F016S5 (28F0XXS5) devices,
connected in parallel, provide lower and upper
bytes of a 16-bit access.
5
PRELIMINARY
iMC002/004/008/016FLSC
E
D<15:8>
D<7:0>
D<15:0>
A<21:1>
A<20:0>
ZWE#
A<25:A22>
ZOE#
Card Control
Logic
CE1#
CE2#
ZCE#<7:0>
ZRY/ZBY#
ZRP#
WE#
OE#
RST
WAIT#
D<7:0>
A<20:0>
WE#
D<7:0>
28F016S5
Device 7
28F016S5
Device 6
CE#
CE#
A<20:0>
WE#
RY/BY#
RP#
RY/BY#
RP#
RDY/BSY#
BVD1
OE#
OE#
VCC VPP VSS
VCC VPP VSS
BVD2
WP
D<7:0>
A<20:0>
WE#
D<7:0>
A<20:0>
WE#
28F016S5
Device 4
28F016S5
Device 5
CE#
CE#
CD1#
RY/BY#
RP#
RY/BY#
RP#
CD2#
OE#
OE#
VCC VPP VSS
VCC VPP VSS
VSS VCC
D<7:0>
A<20:0>
WE#
D<7:0>
A<20:0>
WE#
28F016S5
Device 2
28F016S5
Device 3
CE#
CE#
RY/BY#
RP#
RY/BY#
RP#
OE#
OE#
VCC VPP VSS
VCC VPP VSS
D<7:0>
A<20:0>
WE#
D<7:0>
A<20:0>
WE#
28F016S5
Device 0
28F016S5
Device 1
CE#
CE#
RY/BY#
RP#
RY/BY#
RP#
OE#
OE#
VCC VPP VSS
VCC VPP VSS
VCC
VSS
VPP2
VPP1
VS1
VS2
OPEN
0491_01
Figure 1. 16-Mbyte Flash Memory Card Block Diagram Showing Major Functional Elements
6
PRELIMINARY
E
iMC002/004/008/016FLSC
Table 1. Value Series 100 Card Signals
Pin
1
Signal
GND
I/O
Function
Ground
Active
Pin
Signal
I/O
Function
Address Bit 2
Address Bit 1
Address Bit 0
Active
27 A2
I
I
I
2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
I/O Data Bit 3
I/O Data Bit 4
I/O Data Bit 5
I/O Data Bit 6
I/O Data Bit 7
28 A1
3
29 A0
4
30 DQ0
31 DQ1
32 DQ2
33 WP
34 GND
35 GND
36 CD1#
37 DQ11
38 DQ12
39 DQ13
40 DQ14
41 DQ15
42 CE2#
43 VS1
44 RFU
45 RFU
46 A17
47 A18
48 A19
49 A20
50 A21
51 VCC
52 VPP2
I/O Data Bit 0
I/O Data Bit 1
I/O Data Bit 2
5
6
7
I
I
Card Enable 1
LOW
LOW
O
Write Protect
Ground
HIGH
LOW
8
Address Bit 10
Output Enable
Address Bit 11
Address Bit 9
Address Bit 8
Address Bit 13
Address Bit 14
Write Enable
Ready/Busy
9
OE#
I
Ground
10 A11
11 A9
I
O
Card Detect 1
I
I/O Data Bit 11
I/O Data Bit 12
I/O Data Bit 13
I/O Data Bit 14
I/O Data Bit 15
12 A8
I
13 A13
14 A14
15 WE#
16 RDY/BSY#
17 VCC
18 VPP1
19 A16
20 A15
21 A12
22 A7
I
I
I
LOW
LOW
O
I
Card Enable 2
Voltage Sense 1
Reserved
LOW
N.C.
Supply Voltage
Supply Voltage
Address Bit 16
Address Bit 15
Address Bit 12
Address Bit 7
Address Bit 6
Address Bit 5
Address Bit 4
Address Bit 3
O
N.C.
I
I
I
I
I
I
I
I
Reserved
I
I
I
I
I
Address Bit 17
Address Bit 18
Address Bit 19
Address Bit 20
Address Bit 21
Supply Voltage
Supply Voltage
23 A6
24 A5
25 A4
26 A3
N.C.
7
PRELIMINARY
iMC002/004/008/016FLSC
E
Table 1. Value Series 100 Card Signals (Continued)
Pin
Signal
I/O
Function
Active
Pin
Signal
I/O
Function
Active
53 A22
I
Address Bit 22
61 REG#
62 BVD2
63 BVD1
I
Attribute
Memory Select
54
55
A
I
Address Bit 23
Address Bit 24
O
O
Battery Voltage
Detect 2
3
2
A24
I
Battery Voltage
Detect 1
56 A25
I
Address Bit 25
Voltage Sense 2
Reset
N.C.
N.C.
64 DQ8
65 DQ9
66 DQ10
67 CD2#
I/O Data Bit 8
I/O Data Bit 9
I/O Data Bit 10
57 VS2
58 RST
59 WAIT#
O
I
HIGH
LOW
O
Extend Bus
Cycle
O
Card Detect 2
LOW
60 RFU
Reserved
68 GND
Ground
8
PRELIMINARY
E
iMC002/004/008/016FLSC
Table 2. Value Series 100 Card Signal Description
Symbol
Type
Name and Function
A0–A25
INPUT
ADDRESS INPUTS: A0 through A25 enable direct addressing of up to 64 MB
of memory on the card. Signal A0 is not decoded since the card is x16 only.
The memory will wrap at the card density boundary. The system should not
try to access memory beyond the card’s density, since the upper addresses
are not decoded.
DQ0–DQ15
CE1#, CE2#
OE#
INPUT/
OUTPUT
DATA INPUT/OUTPUT: DQ0 through DQ15 constitute the bi-directional data
bus. DQ15 is the most significant bit.
INPUT
CARD ENABLE 1 & 2: CE1# enables EVEN byte accesses on D0–7, CE2#
enables ODD byte accesses on D8–15. Cannot access Odd Bytes on D0–7
.
INPUT
OUTPUT ENABLE: Active low signal enabling read data from the memory
card.
WE#
INPUT
WRITE ENABLE: Active low signal gating write data to the memory card.
RDY/BSY#
OUTPUT
READY/BUSY OUTPUT: Indicates status of internally timed erase or program
activities. A high output indicates the memory card is ready to accept
accesses.
CD1#,
CD2#
OUTPUT
CARD DETECT 1 & 2: These signals provide for card insertion detection. The
signals are connected to ground internally on the memory card, and will be
forced low whenever a card is placed in the socket. The host socket interface
circuitry shall supply 10K or larger pull-up resistors on these signal pins.
WP
OUTPUT
N.C.
WRITE PROTECT: This signal is pulled LOW for PC Card Standard
compatibility. The flash memory card has no WP signal functionality.
VPP1,VPP2
PROGRAM/ERASE POWER SUPPLY: These power signals are not
connected for the 5 V-only card.
VCC
CARD POWER SUPPLY: 5.0 V for all internal circuitry.
GROUND for all internal circuitry.
GND
REG#
INPUT
INPUT
REGISTER SELECT: The memory card has no separate attribute memory.
The CIS is located in common memory. REG# is unconnected on the card.
RST
RESET: The card is placed in Power-On Default State when RST is low.
RST high is the POWER-DOWN signal for the memory array.
WAIT#
OUTPUT
OUTPUT
WAIT: (Extended Bus Cycle) This signal is pulled high for compatibility.
BVD1,
BVD2
BATTERY VOLTAGE DETECT: These signals are pulled high to maintain
SRAM card compatibility.
VS1, VS2
OUTPUT
VOLTAGE SENSE: Notifies the host socket of the card’s VCC requirements.
VS1 and VS2 are OPEN to indicate a 5 V, 16-bit card has been inserted.
RFU
N.C.
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD pin may be driven or left floating.
9
PRELIMINARY
iMC002/004/008/016FLSC
E
4.1.4
INTELLIGENT IDENTIFIER
OPERATION
4.0 CARD CONTROL LOGIC
The intelligent identifier operation outputs the
manufacturer code, 89H, and the device code: A2H,
A6H or AAH. The table below lists the device and
capacity for each device code.
4.1
Bus Operations
Flash memory reads, erases and programs are
performed using bus cycles to or from the flash
memory that conform to standard microprocessor
bus cycles.
Device Code
Device Type
Component
Capacity
A2H
A6H
AAH
28F008SA
28F008S5
28F016S5
1 MB
1 MB
2 MB
4.1.1
READ
The components on the Value Series 100 card
have three read modes: read memory array, read
intelligent identifier or read status register; they are
enabled by writing the appropriate read mode
command to the Command User Interface (CUI).
The 28F0XXS5 automatically resets to read array
mode upon initial device power-up, or after reset.
A system should recognize all three codes in order
to support current cards, based on the 28F008SA
and newer cards based on the 28F0XXS5 family.
The manufacturer and device codes are read via
the CUI. Following a write of 9090H to the CUI, a
read from address location 0000H outputs the
manufacturer code (8989H). A read from address
0002H outputs the device code: A2A2H, A6A6H, or
AAAAH.
The 28F0XXS5 has four control pins, two of which
must be logically active to obtain data at the
outputs. Chip Enables (CE1,2#) are the device
selection control, and, when active, enable the
selected memory device. Output Enable (OE#) is
the data input/output (DQ0–DQ15) direction control,
and, when active, drives data from the selected
memory onto the I/O bus. WE# must be driven to
Future cards may incorporate devices that
implement the Common Flash Interface (CFI). This
V
IH during a read access.
4.1.2 OUTPUT DISABLE
With OE# and WE# at a logic-high level (VIH), the
standard
supports
forward
and
backward
compatibility between flash memories. New
algorithms should first determine if the card is CFI
compliant, and if it is not, then read the intelligent
identifiers.
device outputs are disabled. Output (DQ0–DQ15
are placed in a high-impedance state.
)
4.1.5
WRITE
Writes to the CUI enable reading of device data and
intelligent identifiers. They also control inspection
and clearing of the status register. The contents of
the interface register serves as input to the internal
state machine on each component.
4.1.3
STANDBY
CE1,2# at a logic-high level (VIH) places the card in
standby mode. Standby operation disables much of
the card’s circuitry and substantially reduces device
power consumption. The outputs (DQ0–DQ15) are
placed in a high-impedance state independent of
the status of OE#. If the card is de-selected during
program or block erase, the card will continue
functioning and consuming normal active power
until the operation completes.
The CUI itself does not occupy an addressable
memory location. The interface register is a latch
used to store the command, address and data
information needed to execute the command. Erase
Setup and Erase Confirm commands require both
appropriate command data and an address within
the block to be erased. The Program Setup
command requires both appropriate command data
and the address of the location to be written, while
the Program command consists of the data to be
written and the address of the location to be written.
10
PRELIMINARY
E
iMC002/004/008/016FLSC
Data Control
The CUI is written by bringing WE# to a logic-low
level (VIL) while CE# is low. Addresses and data
are latched on the rising edge of WE#. Standard
microprocessor write timings are used.
4.3
As shown in Table 3, data paths and directions are
selected by the Data Control logic using WE#, OE#,
CE1#, and CE2# as logic inputs. The Data Control
logic selects any of the PCMCIA word-wide, even-
byte and odd-byte modes for either reads or writes
to common memory.
4.2
Address Decode Logic
The address decode logic selects which
components device pair is enabled during a read or
write access. Unused upper addresses for the
Value Series 100 card will not be decoded. The
address decoding will wrap around at the card’s
density.
NOTE:
This card has a x16 interface. The odd byte
cannot be accessed on the lower data path
(D0–7). A0 is not decoded.
The Value Series 100 card does not have a
separate attribute memory space and REG# is not
included in the address decode logic. REG#
accesses will result in a read/write to the common
memory flash array.
Table 3. Data Access Mode Truth Table
Mode
Even Byte-Read
Odd Byte-Read
Word-Read
RESET CE2# CE1# OE# WE# A1
VPP
X
D8–15
High-Z
Odd
D0–7
Even
High-Z
Even
Even
XXX
Notes
1,2
1,2
1,2
3
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIL
VIL
VIL
VIL
VIH
X
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIL
VIH
X
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
X
VIH
VIH
VIH
VIL
VIL
VIL
VIH
VIH
X
X
X
X
X
X
Odd
Even Byte-Write
Odd Byte-Write
Word-Write
X
X
XXX
Odd
X
X
3
X
X
Odd
Even
89H
3
Manufacturer ID
Device ID
VIL
VIH
X
X
89H
X
A6H
A6H
4
Standby
X
High-Z High-Z
High-Z High-Z
High-Z High-Z
Output Disable
VIH
X
VIH
X
X
X
Power-Down
X
X
X
X
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and address.
3. Refer to Table 4 for valid DIN during a program operation.
4. The device code can be A6H or AAH. Software should check for all three cases for compatibility with future cards.
11
PRELIMINARY
iMC002/004/008/016FLSC
E
a byte program or block erase operation, the device
will not recognize the Read Array command until
the WSM has completed its operation.
5.0 COMMAND DEFINITIONS
Device operations are selected by writing specific
commands into the Command User Interface.
Table 4 defines the 28F0XXS5 commands.
5.2
Intelligent Identifier Command
(9090H)
5.1
Read Array Command (FFFFH)
The 28F0XXS5 contains an intelligent identifier
operation, initiated by writing 9090H into the CUI.
Following the command write, a ready cycle from
address 00000H retrieves the manufacturer code of
8989H. A read cycle from address 00002H returns
the device code of A2A2H, A6A6H, or AAAAH. To
terminate the operation, it is necessary to write
another valid command into the register.
Upon initial device power-up, and after reset, the
28F0XXS5 defaults to read array mode. This
operation is also initiated by writing FFFFH into the
CUI on the component. Microprocessor read cycles
retrieve array data. The device remains enabled for
reads until the CUI contents are altered by issuing a
valid command. Once the internal WSM has started
Table 4. 28F008SA-Compatible Mode Command Bus Definitions
First Bus Cycle Second Bus Cycle
Command
Read Array
R/W
W
Addr
DA
DA
DA
DA
PA
PA
BA
DA
DA
Data
R/W
R
Addr
DA
IA
Data
FFFFH
9090H
7070H
5050H
4040H
1010H
2020H
B0B0H
D0D0H
AD
ID
Intelligent Identifier
Read Status Register
Clear Status Register
Program
W
R
W
R
DA
SRD
W
W
W
W
W
PA
PA
BA
PD
PD
Program (Alternate)
Block Erase/Confirm
Erase or Program Suspend
Erase or Program Resume
W
W
D0D0H
W
W
ADDRESSES:
DATA:
DA
BA
IA
Device Address
Block Address
Identifier Address
Program Address
AD
SRD
ID
Array Data
Status Reg. Data
Identifier Data
Program Data
PA
PD
12
PRELIMINARY
E
iMC002/004/008/016FLSC
Table 5. New Commands
Command
Bus
Cycles
Req’d.
First Bus Cycle
Second Bus Cycle
R/W
W
Addr
X
Data
R/W
W
Addr
BA
X
Data
0101H
D0D0H
Set Block Lock-Bit
2
2
6060H
6060H
Clear Block Lock-Bits
W
X
W
5.3
Read Status Register
Command (7070H)
5.4
Clear Status Register
Command (5050H)
The 28F0XXS5 components on the Value Series
100 card each contain a status register which may
be read to determine when a program or block
erase operation is complete, and whether that
operation completed successfully. The status
register may be read at any time by writing the
Read Status Register command (7070H) to the
CUI. After writing this command, all subsequent
read operations output data from the status register,
until another valid command is written to the CUI.
The contents of the status register are latched on
the falling edge of OE# or CE#, whichever occurs
first. OE# or CE# must be toggled to VIH before
further reads to update the status register latch.
The Erase Status and Program Status bits are set
to “1”s by the WSM and can only be reset by the
Clear Status Register command. These bits
indicate various failure conditions (see Table 5). By
allowing system software to control the resetting of
these bits, several operations may be performed
(such as cumulatively writing several bytes or
erasing multiple blocks in sequence). The status
register may then be polled to determine if an error
occurred during that sequence. This status register
functionality adds flexibility to the way the device
may be used.
Additionally, the VPP Status bit (SR.3) must be
reset by system software before further writes or
block erases are attempted. To clear the status
register, the Clear Status Register command (50H)
is written to the CUI.
NOTE:
Two 28F0XXS5 devices are used in parallel
to form a x16 operation. Both status registers
need to be checked when determining the
status of a x16 erase/program operation.
13
PRELIMINARY
iMC002/004/008/016FLSC
E
Table 6. Status Register Definition
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
R
2
R
1
R
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
RDY/BSY# or the Write State Machine Status bit
must first be checked to determine byte write or
block erase completion, before the Byte Write or
Erase Status bit are checked for success.
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
0 = Erase in Progress/Completed
If the Program and Erase Status bits are set to “1”s
during a block erase attempt, an improper command
sequence was entered. Attempt the operation again.
SR.5 = ERASE STATUS
1 = Error in Block Erasure
0 =
Successful Block Erase
If VPP low status is detected, the status register
must be cleared before another program or block
erase operation is attempted.
SR.4 = PROGRAM STATUS
1 = Error in Program
0 = Successful Program
The VPP Status bit, unlike an A/D converter, does
not provide continuous indication of VPP level. The
WSM interrogates the VPP level only after the
Program or Block Erase command sequence have
been entered and informs the system if VPP has not
been switched on.
SR.3 = VPP STATUS
1 =
0 =
V
V
PP Low Detect, Operation Abort
PP OK
SR.2 = BYTE WRITE SUSPEND STATUS
1 = Byte Write Suspended
0 = Byte Write in Progress/Completed
SR.1 does not provide a continuous indication of
master and block lock-bit values. The WSM
interrogates the master lock-bit, block lock-bit, and
RST only after Block Erase, Byte Write, or Lock-Bit
configuration command sequences. It informs the
system, depending on the attempted operation, if
the block lock-bit is set. Reading the block lock and
master lock configuration codes after writing the
Read Identifier Codes command indicates master
and block lock-bit status.
SR.1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit
Detected, Operation Abort
0 = Unlock
SR.0 is reserved for future use and should be
masked out when polling the status register
invisible to the system. After the two-command
erase sequence is written to it, the 28F0XXS5
automatically outputs status register data when
read. The CPU can detect the completion of the
erase event by analyzing the output data of the
RDY/BSY# pin, or the WSM Status bit of the status
register. When erase is completed, the Erase
Status bit should be checked. If erase error is
detected the status register should be cleared. The
CUI remains in read status register mode until
further commands are issued to it.
5.5
Erase Setup/Erase Confirm
Commands (2020H, D0D0H)
Erase is executed one block at a time, initiated by
the two-cycle command sequence. An Erase Setup
command (2020H) is first written to the CUI,
followed by the Erase Confirm command (D0D0H).
These commands require both appropriate
sequencing and an address within the block to be
erased to FFFFH. Block preconditioning, erase and
verify are all handled internally by the WSM,
14
PRELIMINARY
E
iMC002/004/008/016FLSC
successfully program to “0”s. The CUI remains in
read status register mode until further commands
are issued to it.
5.6
Erase Suspend/Erase Resume
Commands (B0B0H, D0D0H)
The Erase Suspend command allows block erase
interruption in order to read data from another block
of memory. Once the erase process starts, writing
the Erase Suspend command (B0B0H) to the CUI
requests that the WSM suspend the erase
sequences at a predetermined point in the erase
algorithm. The 28F0XXS5 continues to output
status register data when read, after the Erase
Suspend command is written to it. Polling the WSM
Status and Erase Suspend Status bits will
determine when the erase operation has been
suspended (both will be set to “1”). RDY/BSY# will
5.8
Word Write Suspend Command
The conversion to the 28F0XXS5 family adds the
capability to suspend a programming or word-write
operation. Once
a
word write operation is
suspended, the card can be read, even if the data
is located on the same component as was being
programmed.
The
command
to
suspend
programming is the same as the Erase suspend
command, B0B0H. The program operation can be
resumed by issueing the Program resume
command, D0D0H.
also transition to VOH
.
At this point, a Read Array command can be written
to the CUI to read data from blocks other than that
which is suspended. The only other valid
commands, at this time, are Read Status Register
(7070H) and Erase Resume (D0D0H), at which time
the WSM will continue with the erase process. The
Erase Suspend Status and WSM Status bits of the
status register will automatically cleared and the
RDY/BSY# will return to VOL. After the Erase
Resume command is written to it, the 28F0XXS5
automatically outputs status register data when
read.
Once the word write process starts, writing the
Word Write Suspend command requests that the
WSM suspend the word write sequence at
a
predetermined point in the algorithm. After the host
writes the Word Write Suspend command, it should
write the Read Status Register command. Polling
status register bits SR.7 and SR.2 can determine
when the WSM suspends the byte write operation
(both will be set to “1”). BUSY# will also transition to
VOH. Specification tWHRH1 defines the word write
suspend latency. It is also possible that the word
write completes before the device has an
opportunity to suspend. The host should also check
for this condition.
5.7
Program Commands (4040H or
1010H)
After the word write has been suspended, the host
can write the Read Array command to read data
from any location except the suspended location.
The only other valid commands while word write is
suspended are Read Status Register and Word
Write Resume. After the host writes a Word Write
Resume to the CUI, the WSM will continue the word
write process. Status register bits SR.2 and SR.7
will automatically clear and BUSY# will return to
The Program command is executed by a two-
command sequence. The Program Setup command
(4040H or 1010H) is written to the CUI, followed by
a second write specifying the address and data
(latched on the rising edge of WE#) to be
programmed. The WSM then takes over, controlling
the program and program verify algorithms
internally. After the two-command write sequence is
written to it, the 28F0XXS5 automatically outputs
status register data when read. The CPU can detect
the completion of the program event by analyzing
the output of the RDY/BSY# pin, or the WSM
Status bit of the status register. Only the Read
Status Register command is valid while program is
active.
V
OL. After the host writes the Word Write Resume
command, the device automatically outputs status
register data when read.
5.9
Set Block Lock-Bit Command
The host can enable a flexible block locking and
unlocking scheme using the Set Block Lock-Bit
command. This command enables the host to lock
individual blocks within the flash array. The block
lock-bits gate program and erase operations.
When program is complete, the Program Status bit
should be checked. If program error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for “1”s that do not
15
PRELIMINARY
iMC002/004/008/016FLSC
E
The host sets the block lock-bit using a two-cycle
command sequence. The host writes the set block
lock-bit setup command along with the appropriate
block or device address. This command is followed
by the set block lock-bit confirm command (and an
address within the block to be locked). The WSM
controls the set lock-bit algorithm. After the host
completes the command sequence, the card
automatically outputs status register data when
read. The CPU can detect the completion of the set
lock-bit event by analyzing the BUSY# pin output or
status register bit SR.7.
This two-step sequence of set-up followed by
execution ensures that the host does not
accidentally clear block lock-bits. An invalid Clear
Block Lock-Bits command sequence will result in
the WSM setting status register bits SR.4 and SR.5
to “1.”
If a clear block lock-bits operation is aborted due to
VCC transitioning out of valid range or RST active
transition, block lock-bit values are left in an
undetermined state. The host must repeat the clear
block lock-bits command to initialize block lock-bit
contents to known values.
When the WSM completes the set lock-bit
operation, the host should check status register bit
SR.4. If the host detects an error it should clear the
status register. The CUI will remain in read status
6.0 PC CARD INFORMATION
STRUCTURE
register mode until the host issues
command.
a new
The Card Information Structure (CIS) begins at
address 00000000H of the card’s Common Memory
Plane and resides sequentially in memory locations
with even byte memory addresses. It contains a
variable length chain of data blocks (tuples) that
conform to a basic format (Table 6). The CIS of the
Value Series 100 card is found in Table 7.
This two-step sequence of set-up followed by
execution ensures that the host does not
accidentally set the lock-bits. An invalid Set Block
Lock-Bit command will result in the WSM setting
status register bits SR.4 and SR.5 to “1.”
CAUTION:
5.10 Clear Block Lock-Bits
Command
The CIS data in Block
0 is not write
protected and should not be erased by the
system software if the CIS is needed for card
recognition.
The host clears all set block lock-bits in parallel
using the Clear Block Lock-Bits command. The host
is free to clear block lock-bits using the Clear Block
Lock-Bits command
Table 7. PC Card Tuple Format
Bytes
Data
The host executes the clear block lock-bits
operation using a two-cycle command sequence.
The host must first issue a Clear Block Lock-Bits
setup command. This command is followed by a
confirm command. After the host completes the
two-cycle command sequence, the device
automatically outputs status register data when
read. The CPU can detect completion of the clear
block lock-bits event by analyzing the BUSY# pin
output or status register bit SR.7.
0
Tuple Code: CISTPL_xxx. The tuple
code 0FFH indicates no more tuples in
the list.
1
Tuple Link: TPL_LINK. Link to the next
tuple in the list. This can be viewed as
the number of additional bytes in tuple,
excluding this byte. A link field of zero
indicates an empty tuple body. A link
field containing 0FFH indicates the last
tuple in the list.
When the WSM completes the operation, the host
should check status register bit SR.5. If the host
detects a clear block lock-bit error, the host should
clear the status register. The CUI will remain in read
status register mode until the host issues another
command.
2-n
Bytes specific to this tuple.
16
PRELIMINARY
E
iMC002/004/008/016FLSC
Table 8. Value Series 100 Card Tuples
Address
2EH
30H
Value
Description
CISTPL_LONGLINK_C
TPL_LINK
Address
00H
Value
01H
Description
CISTPL_DEVICE
TPL_LINK
12H
04H
00H
00H
02H
00H
15H
40H
05H
00H
69H
02H
03H
32H
LOWEST BYTE
TYPE/SPEED
04H
54H
54H
54H
53H
2 MB: FLASH/100 ns
4 MB: FLASH/100 ns
8 MB: FLASH/100 ns
16 MB: FLASH/150 ns
34H
36H
38H
HIGHEST BYTE
CISTPL_VERS1
TPL_LINK
CARD SIZE:
2 MB
06H
06H
0EH
1EH
3EH
3AH
3CH
3EH
40H
4 MB
8 MB
16 MB
TPLLV1_MAJOR
TPLLV1_MINOR
08H
0AH
0CH
0EH
10H
12H
14H
16H
18H
FFH
1EH
06H
02H
11H
01H
01H
03H
01H
END OF DEVICE
CISTPL DEVICEGEO
TPL_LINK
42H
TPLLV1_INFO
i
44H
46H
48H
4AH
4CH
4EH
50H
52H
54H
56H
58H
5AH
5CH
5EH
60H
62H
64H
66H
68H
6EH
74H
65H
6CH
00H
56H
41H
4CH
55H
45H
20H
53H
45H
52H
49H
45H
53H
20H
31H
n
DGTPL_BUS
t
DGTPL_EBS
e
DGTPL_RBS
l
DGTPL_WBS
END TEXT
DGTPL_PART = 1
V
FLASH DEVICE
INTERLEAVE
A
1AH
1CH
1EH
20H
22H
20H
04H
89H
00H
CISTPL_MANFID
TPL_LINK (04H)
L
U
TPLMID_MANF: LSB
TPLMID_MANF: MSB
E
SPACE
03H
13H
23H
32H
2 MB - 100 ns
4 MB - 100 ns
8 MB - 100 ns
16 MB - 150 ns
S
E
R
24H
26H
28H
2AH
85H
21H
02H
01H
TPLMID_CARD MSB
CISTPL_FUNCID
TPL_LINK
I
E
S
TPLFID_FUNCTION :
Memory
SPACE
2CH
00H
TPLFID_SYSINIT
1
17
PRELIMINARY
iMC002/004/008/016FLSC
E
Address
A0H
A2H
A4H
A6H
A8H
AAH
ACH
AEH
B0H
B2H
B4H
B6H
B8H
BAH
BCH
BEH
C0H
C2H
C4H
Value
50H
4FH
52H
41H
54H
49H
4FH
4EH
20H
31H
39H
39H
35H
00H
FFH
18H
02H
89H
A6
Description
Address
6AH
Value
30H
30H
20H
00H
Description
P
0
0
O
6CH
R
6EH
SPACE
END TEXT
A
70H
T
72H
30H
30H
30H
31H
2 MB
4 MB
8 MB
16 MB
I
O
N
74H
32H
34H
38H
36H
2 MB
4 MB
8 MB
16 MB
SPACE
1
76H
78H
7AH
7CH
7EH
80H
82H
84H
86H
88H
8AH
8CH
8EH
90H
92H
94H
96H
98H
9AH
9CH
9EH
20H
00H
43H
4FH
50H
59H
52H
49H
47H
48H
54H
20H
49H
4EH
54H
45H
4CH
20H
43H
4FH
52H
SPACE
9
9
END TEXT
C
5
O
END TEXT
END OF LIST
CISTPL_JEDEC_C
TPL_LINK
P
Y
R
I
MANUFACTURER ID
2 MB (28F008S5)
G
H
AA
4, 8, or 16 MB
(28F016S5)
T
C6H
C8H
FFH
00H
CISTPL_END
SPACE
INVALID ADDRESS
I
N
T
E
L
SPACE
C
O
R
18
PRELIMINARY
E
Flash memory power-switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues: standby, active and transient current peaks
which are produced by rising and falling edges of
CE1# and CE2#. The capacitive and inductive loads
on the card and internal flash memory device pairs
determine the magnitudes of these peaks.
iMC002/004/008/016FLSC
7.0 SYSTEM DESIGN
CONSIDERATIONS
7.3
RDY/BSY# and Program/Block
Erase Polling
RDY/BSY# is a full CMOS output that provides a
hardware method of detecting program and block
erase completion. It transitions low time tWHRL after
a Program or Erase command sequence is written
to a 28F0XXS5, and returns to VOH when all the
WSM has finished executing the internal algorithm.
7.1
Power Supply Decoupling
RDY/BSY# can be connected to the interrupt input
of the system CPU or controller. It is active at all
times. RDY/BSY# is also VOH when the device is in
erase suspend or deep power-down modes.
Three-line control and proper decoupling capacitor
selection suppress transient voltage peaks. The
Value Series 100 cards contain on-card ceramic
decoupling capacitors connected between VCC and
GND.
7.4
V
, V , RESET Transitions
CC PP
and the Command/Status
Registers
Program and block erase completion are not
guaranteed if the internally generated VPP drops
below VPPH. If the VPP Status bit of the status
register (SR.3) is set to “1,” a Clear Status Register
command must be issued before further
program/block erase attempts are allowed by the
WSM. Otherwise, the Program (SR.4) or Erase
Status (SR.5) bits of the status register will be set
to “1”s, if error is detected. RESET transitions to VIH
during program and block erase also abort the
operations. Data is partially altered in either case,
and the command sequence must be repeated after
normal operation is restored. Device power-off, or
RESET transitions to VIH, clear the status register
to initial value 10000XXX for the upper eight bits.
The card connector should also have a 4.7 µF
electrolytic capacitor between VCC and GND. The
bulk capacitors overcome voltage slumps caused
by printed-circuit-board trace inductance, and
supply charge to the smaller capacitors as needed.
7.2
Power-Up/Down Protection
The PCMCIA/JEIDA-specified socket properly
sequences the power supplies to the flash memory
card via shorter and longer pins.
Each device in the memory card is designed to
offer protection against accidental erasure or
writing, caused by spurious system-level signals
that may exist during power transitions. The card
will power-up into the read state.
The CUI latches commands, as issued by system
software, and is not altered by CE# transitions, or
WSM actions. Its state upon power-up, after exit
from deep power-down or after VCC transitions
below VLKO, is read array mode.
A system designer must guard against active writes
for VCC voltages above VLKO (2.0 V). Since both
WE# and CE1# must be low for a command write,
driving either to VIH will inhibit writes. With its
control register architecture, alteration of device
contents only occurs after successful completion of
the two-step command sequences.
After program or block erase is complete, the CUI
must be reset to read array mode via the Read
Array command, if access to the memory array is
desired.
19
PRELIMINARY
iMC002/004/008/016FLSC
E
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.
NOTICE: This datasheet contains preliminary information on
new products in production. The specifications are subject
to change without notice. Verify with your local Intel Sales
office that you have the latest datasheet before finalizing a
design.
8.0 ELECTRICAL SPECIFICATIONS
8.1 Absolute Maximum Ratings*
Operating Temperature
During Read............................0 °C to +70 °C(1)
During Write............................0 °C to +70 °C(1)
Storage Temperature................... –30 °C to +80 °C
Voltage on Any Pin with
Respect to Ground........–2.0 V to VCC +2.0 V(2)
VCC Supply Voltage with
Respect to Ground.................. –0.2 V to +7.0 V
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is –0.5 V; Maximum DC voltage on output pins is VCC +0.5 V.
8.2
Operating Conditions
Temperature and VCC Operating Conditions
Symbol
Parameter
Supply Voltage
Min
Max
Units
VCC
4.75
5.25
V
(1)
8.3
Capacitance
TA = +25 °C, f = 1 MHz
Symbol
Parameter
Typ
25
3
Max
Unit
Condition
CIN
CIN
Address/Control
50
5
pF
µF
pF
VCC Supply Voltage
Output Capacitance
COUT
NOTE:
25
50
1. Sampled, not 100% tested.
4.0V
Input
0.0
1.5
Test Points
1.5 Output
0546_02
Figure 2. Transient Input/Output Reference Waveform for Standard Test Configuration
20
PRELIMINARY
E
iMC002/004/008/016FLSC
8.4
DC Characteristics
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions
ILI
Input Leakage Current
1,2
± 20
µA
VCC = VCC Max
V
IN = VCC or GND
VCC = VCC Max
OUT =VCC or GND
ILO
Output Leakage Current
1
± 20
µA
V
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1
1
1
1
1
0
0.8
VCC + 0.5
0.4
V
V
V
V
V
VIH
3.85
VOL
VOH
VLKO
IOL = 3.2 mA
VCC – 0.4
VCC
IOH = –2.0 mA
VCC Erase/Program
Lock Voltage
2.0
NOTES:
1. Values are the same for byte and word wide modes for all card densities.
2. Exceptions: With VIN = GND, the leakage current on CE1#, CE2#, OE#, and WE# will be < 500 µA due to internal pull-up
resistors. With VIN = VCC, RST leakage current will be < 150 µA due to internal pull-down resistors.
8.4
DC Characteristics (Continued)
Sym
Parameter
Density
(Mbytes)
ALL
Notes
x16 Mode
Units
Test Conditions
Typ
Max
VCC = VCC Max
CYCLE = 100 ns
ICCR VCC Read Current
1, 3
75
mA
t
ICCW VCC Program Current
ICCE VCC Erase Current
ICCSL VCC Sleep Current
ALL
ALL
2, 4
8
1, 3
1, 3
150
100
170
200
mA
mA
1, 2, 4
1, 2, 4
30
30
µA VCC = VCC Max
µA RESET, Control Signals =
VIH
16
2, 4
8
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
30
80
300
370
600
µA
ICCS VCC Standby Current
µA VCC = VCC Max
µA Control Signals = VCC
135
16
245 1,100 µA
CMOS Test Conditions: VIL = GND ± 0.2 V, VIH = VCC ± 0.2 V
NOTES:
1. All currents are RMS values unless otherwise specified. Typical conditions: VCC = 5 V, T = +25 °C.
2. Control Signals: CE1#, CE2#, OE#, WE#.
3. Characteristics assume only one pair of components are active and the remaining pairs are in standby.
4. Inputs are either VCC ± 0.2 V or GND ± 0.2 V.
21
PRELIMINARY
iMC002/004/008/016FLSC
8.5 AC Characteristics
E
AC timing diagrams and characteristics are
guaranteed to meet or exceed PCMCIA 2.1
specifications. No delay occurs when switching
between the common and attribute memory planes.
8.5.1
READ OPERATIONS—COMMON MEMORY
Symbol Parameter
2, 4, 8 MB
16 MB
Unit
JEDEC
PCMCIA
tRC
Min
Max
Min
Max
tAVAV
tAVQV
tELQV
tGLQV
tEHQX
tGHQZ
tELQX
tGLQX
tPHQV
Read Cycle Time
100
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta (A)
Address Access Time
100
100
50
150
150
75
ta (CE)
ta (OE)
tdis (CE)
tdis (OE)
ten (CE)
ten (OE)
Card Enable Access Time
Output Enable Access Time
Output Disable Time from CE#
Output Disable Time from OE#
Output Enable Time from CE#
Output Enable Time from OE#
50
75
50
75
5
5
5
5
Power-Down Recovery to Output
Delay. VCC = 5 V
530
530
22
PRELIMINARY
E
iMC002/004/008/016FLSC
Power-
down
Device and
Outputs
Data
Valid
Power-up Standby
Address Selection Enabled
V
StandbyV
VIH
VIL
Address Stable
Addresses(A)
tAVAV
VIH
VIL
CE#(C)
Note 1
Note 1
Note 1
tEHQZ
VIH
VIL
OE#(G)
WE#(W)
Note 1
tGHQZ
VIH
VIL
tGLQV
tGLQX
tELQV
tELQX
tAXQX
VOH
VOL
High Z
High Z
Data(D/Q)
Valid Output
tAVQV
Note 1: The filled area may be either high or low
A4533-01
049102
Figure 3. AC Waveforms for Read Operations
23
PRELIMINARY
iMC002/004/008/016FLSC
8.5.2
WRITE OPERATIONS—COMMON MEMORY(1)
E
Symbol
PCMCIA
Parameter
2, 4, 8 MB
16 MB
Unit
JEDEC
Min
100
60
Max
Min
150
80
Max
tAVAV
tWLWH
tAVWL
tAVWH
tELWH
tDVWH
tWHDX
tWHAX
tWHRL
tWHGL
tPHWL
tcW
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tw (WE)
tsu (A)
Write Pulse Width
Address Setup Time
10
20
tsu (A-WEH)
Address Setup Time for WE#
70
100
100
50
tsu (CEWEH) Card Enable Setup Time for WE#
70
tsu (D-WEH)
th (D)
Data Setup Time for WE#
Data Hold Time
40
15
20
trec (WE)
Write Recovery Time
15
20
WE# High to RDY/BSY#
Output Enable Hold from WE#
th (OE-WE)
10
10
Power-Down Recovery to WE#
Going Low
1
1
NOTE:
1. Read timing characteristics during erase and data program operations are the same as during read-only operations. Refer
to AC Characteristics, Read Operations—Common Memory.
24
PRELIMINARY
E
iMC002/004/008/016FLSC
1
2
3
4
5
6
VIH
ADDRESSES (A)
VIL
AIN
AIN
tAVAV
tAVWL
tAVWH
tWHAX
VIH
CE# (E)
VIL
tWHGL
VIH
OE# (G)
VIL
tELWH
tWHQV1,2
VIH
WE# (W)
VIL
tWLWH
tDVWH
tWHDX
VIH
DATA (D/Q)
VIL
High Z
tPHWL
Valid
SRD
D
D
D
IN
IN
IN
t WHRL
VOH
RDY/BSY# (R)
VOL
VIH
RP#
VIL
tQVVL
tVPWH
VPPH
VPPL
VPP(V)
VIH
VIL
0491_03
NOTES:
1. VCC Power-Up and Standby
2. Write Program or Erase Setup Command
3. Write Valid Address and Program or Erase Confirm Command
4. Automated Program or Erase Delay
5. Read Status Register Data
6. Write Read Array Command
Figure 4. AC Waveforms for Write Operations
25
PRELIMINARY
iMC002/004/008/016FLSC
8.5.3 POWER-UP/POWER-DOWN
E
Symbol
PCMCIA
Vi (CE)
Parameter
Notes
Min
Max
Units
CE# Signal Level (0.0V < VCC < 2.0V)
CE# Signal Level (2.0V < VCC < VIH)
1
1
1
0
VCC – 0.1
VIH
20
ViMAX
ViMAX
ViMAX
V
V
CE# Signal Level (VIH < VCC
)
V
tsu (VCC
)
CE# Setup Time
ms
ms
µs
ms
ms
µs
ms
ms
tsu (RESET)
CE# Setup Time
20
trec (VCC
)
CE# Recover Time
VCC Rising Time
1.0
0.1
3.0
10
tpr
tpf
2
2
300
300
VCC Falling Time
RESET Width
tw (RESET)
th (Hi-Z RESET) RESET Width
1
ts (Hi-Z RESET) RESET Width
0
NOTES:
1. ViMAX means Absolute Maximum Voltage for input in the period of 0.0 V < VCC < 2.0 V, Vi (CE#) is only 0.00 V ~ ViMAX.
2. The tpr and tpf are defined as “linear waveforms” in the period of 10% to 90%, or vice-versa. Even if the waveform is not a
“linear waveform,” its rising and falling time must meet this specification.
049105
Figure 5. Power-Up/Down Timing for Systems Supporting RESET
26
PRELIMINARY
E
iMC002/004/008/016FLSC
(1,3)
8.6
Erase and Data Write Performance
VCC = 5 V ± 0.5 V, TA = 0 °C to +70 °C
Sym
Parameter
Notes
Min
Typ(1)
Max
Units
Test Conditions
tWHQV1
tEHQV1
tWHQV2
tEHQV2
Word/Byte Program Time
2,4
8 µs
3 ms
Block Program Time
2
0.4
2.1
10
sec
Word Program Mode
Block Erase Time
2
2
0.6
sec
sec
Full Chip Erase Time
38.4
NOTES:
1. +25 °C, and normal voltages.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. To maximize system performance, the RDY/BSY# signal should be polled instead of using the maximum byte/word
program time as a delay timer.
The maximum word/byte program time is the absolute maximum time it takes the write algorithm to complete. The over-
whelming majority of the bits program in the typical value specified.
27
PRELIMINARY
iMC002/004/008/016FLSC
9.0 PACKAGING
E
Surface A
L
Substrate Area
1
C
Interconnect Area
P
Connector
W
2x T
2x S
X
X
X
Surface A
Surface B
#1
#34
#35
#68
Y
C Min
L ± 0.008 P Min
1
S Min
T
2
W ± 0.004 X ± 0.002 Y ± 0.002
0.394
(10.0)
3.370
(85.60)
0.394
(10.0)
0.118
(3.0)
0.065
(1.65)
2.126
(54.0)
0.039
(1.00)
0.063
(1.60)
1
2
Polarization key length
Interconnect area tolerance = ±0.002
Substrate area tolerance = ±0.004
3
Millimeters are in parenthesis ()
A6887-01
28
PRELIMINARY
E
iMC002/004/008/016FLSC
10.0 ORDERING INFORMATION
iMC008FLSC, SBXXXXX
Where:
i
= INTEL
MC
= MEMORY CARD
008
= DENSITY IN MEGABYTES (002, 004,008, 016 AVAILABLE)
= FLASH TECHNOLOGY
= BLOCKED ARCHITECTURE
= REVISION
FL
S
C
SBXXXXX
= CUSTOMER IDENTIFIER
11.0 ADDITIONAL INFORMATION
Order Number
Document
290597
292177
292204
Note 3
5 Volt FlashFile™ Memory Family; 28F004S5, 28F008S5, 28F016S5 datasheet
AP-622 Value Series 100 Card Design
AP-646 Common Flash Interface (CFI) and Command Sets
AP-606 Interchangeability of Series 1, Series 2, and Series 2+ Flash Memory Cards
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.
3. These documents can be located at the Intel World Wide Web support site,http://www.intel.com/support/flash/memory
29
PRELIMINARY
相关型号：
©2020 ICPDF网 联系我们和版权申明