JL82572EI/SL8V3 [INTEL]
Micro Peripheral IC;
| 型号： | JL82572EI/SL8V3 |
| 厂家： | 
INTEL |
| 描述： | Micro Peripheral IC |
| 文件： | 总50页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Intel 82571 & 82572 Gigabit Ethernet
Controller
Datasheet
Revision 2.0
December 2006
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COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
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product to deviate from published specifications. Current characterized errata are available on request.
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*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation, 2003 - 2006
ii
Datasheet—82571/82572 Ethernet Controller
Revision History
Date
Revision
Notes
Oct 2002
0.15
Initial Release
Revised ballout, added package drawing, added visual pin descriptions,
changed some ball names to “EXP” ball naming convention.
Feb 2003
0.5
•
•
•
•
Updated power specifications.
Changed names to “PE” naming convention
Revised signal descriptions, pinout information tables, and ballout grid.
Modified LAN disable ballout to cover A-0 (DEV_DIS_N) and B-0
(DEV_OFF_N).
Aug 2003
0.6
•
Removed integrated Baseboard Management Controller.
•
•
•
•
•
•
•
•
•
•
Updated operating temperature
Changed DEV_DIS_N pin (A Stepping) to RSVD_NC
Corrected LED descriptions in signal descriptions in signal descriptions
Added Absolute Maximum Ratings
Added General Operating Conditions
Added Power Specifications
Added voltage Ramp and Sequencing Recommendations
Added DC I/O Specifications
Added Timing Specifications
Oct 2003
May 2004
0.75
Edited Thermal Characteristics
•
Section 4.4, Figure 2; Section 4.5.1.1;Section 4.5.1.2, Figure 5; Section
4.5.2, Figure 6; Section 5.1, Figure 7; Section 5.1, Figure 8; Section 5.4,
Figure 9, ball T6 changed to PERST_N.
0.85
0.90
•
•
•
Included 82572EI information
Updated signal names
Updated power numbers
January
2005
May 2005
Nov 2005
0.92
1.0
•
•
Corrected 1.1 V Operating Range in Table 2
Changed document status to “Intel Confidential,” updated power values,
made minor corrections to text
•
•
Corrected pinlists
Pin A7 DEVICE_DIS_N has been moved to Reserved and No Connect
Signals; this pin is now Reserved. Refer to 82571EB/82571EI Design Guide
for guidance on proper connection.
March
2006
1.1
•
Pin R4 LAN_PWR_GOOD has been moved to Reserved and No Connect
Signals; this pin is now Reserved. Refer to 82571EB/82571EI Design Guide
for guidance on proper connection.
August
2006
1.2
2.0
•
•
Corrected signal names; minor text edits
Changed signal names PERST# to PE_RST_N and PE_WAKEn to
PE_WAKE_N; SMBCLK1 and SMBD1 are now reserved--Do not use these
pins--connect them to 3.3 V through a 100K ohms resistor; updated
schematics.
December
2006
iii
82571/82572 Ethernet Controller—Datasheet
Contents
1.0 Introduction ............................................................................................................. 1
1.1
1.2
1.3
Document Scope ................................................................................................ 1
Reference Documents.......................................................................................... 1
Block Diagram.................................................................................................... 3
2.0 Features of the 82571/82572 Gigabit Ethernet Controller......................................... 5
2.1
2.2
2.3
2.4
2.5
2.6
2.7
PCI Express Features .......................................................................................... 5
MAC-Specific Features......................................................................................... 5
PHY Specific Features.......................................................................................... 6
Host Offloading Features...................................................................................... 6
Manageability Features........................................................................................ 7
Additional Device Features................................................................................... 7
Technology Features ........................................................................................... 8
3.0 Signal Descriptions ................................................................................................... 9
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Signal Type Definitions........................................................................................ 9
PCI Express Interface.......................................................................................... 9
Power Management Signals.................................................................................10
SMB and Fast Management Link Bus Signals..........................................................11
EEPROM and Serial FLASH Interface Signals ..........................................................12
LED Signals ......................................................................................................12
Other Signals ....................................................................................................13
Crystal Signals ..................................................................................................13
PHY Analog Signals ............................................................................................13
3.9.1 Port 0 ...................................................................................................13
3.9.2 Port 1 (82571 Only)................................................................................14
3.10 Serializer / Deserializer Signals............................................................................15
3.11 Test Interface Signals.........................................................................................15
3.12 Power Supply Connections ..................................................................................16
3.12.1 Digital and Analog Supplies......................................................................16
3.12.2 Grounds, Reserved Pins and No Connects...................................................16
4.0 Voltage, Temperature, and Timing Specifications.....................................................17
4.1
4.2
Targeted Absolute Maximum Ratings....................................................................17
Targeted Recommended Operating Conditions.......................................................17
4.2.1 General Operating Conditions...................................................................17
4.2.2 Voltage Ramps.......................................................................................18
4.2.3 Voltage Power Sequencing Options............................................................19
DC Specifications...............................................................................................19
4.3.1 Power Specifications--82571EB.................................................................19
4.3.2 Power Specifications--82572EI .................................................................21
4.3.3 I/O Characteristics..................................................................................22
Targeted AC Characteristics ................................................................................23
Targeted Timing Specifications ............................................................................24
4.5.1 PCI Express Interface..............................................................................25
4.5.2 EEPROM Interface...................................................................................28
4.5.3 FLASH Interface .....................................................................................29
4.3
4.4
4.5
5.0 Package and Pinout Information..............................................................................31
5.1
5.2
5.3
5.4
Package Information ..........................................................................................31
Thermal Specification.........................................................................................33
Pinout Information.............................................................................................33
Visual Pin Assignments.......................................................................................44
iv
Datasheet—82571/82572 Gigabit Ethernet Controller
1.0
Introduction
The Intel® 82571EB Gigabit Ethernet Controller is a single, compact component with
two full-integrated Gigabit Ethernet Media Access Control (MAC) and physical layer
(PHY) ports. The Intel 82571/82572 Gigabit Ethernet Controller is a single-port version
of the controller in the same package. These devices use the PCI Express* architecture
(Rev. 1.0a). The Intel 82571/82572 Gigabit Ethernet Controller enables dual- or single-
port gigabit ethernet implementation in a very small area--ideal for both server and
workstation network designs that have critical space constraints.
The Intel 82571/82572 Gigabit Ethernet Controller provides a standard IEEE 802.3
Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3,
802.3u, and 802.3ab). Ports also contain a Serializer-Deserializer (SERDES) to support
1000Base-SX/LX (optical fiber) and Gigabit backplane applications. In addition to
managing MAC and PHY Ethernet layer functions, the controller manages PCI Express
packet traffic across its transaction, link, and physical/logical layers.
The Intel 82572EI Gigabit Ethernet Controller’s on-board System Management Bus
(SMB) ports enable network manageability implementations required by information
technology personnel for remote control and alerting via the LAN. With SMB,
management packets can be routed to or from a management processor. The SMB
ports enable industry standards, such as Alert Standard Format (ASF) 2.0, to be
implemented using the 82571/82572 Gigabit Ethernet Controller. In addition, on-chip
ASF 2.0 circuitry provides alerting and remote control capabilities with standardized
interfaces. Enhanced pass-through capabilities also allow system remote control over
standardized interfaces.
The 82571/82572 Gigabit Ethernet Controller with PCIe* architecture is designed for
high performance and low memory latency. The device is optimized to connect to a
system Memory Control Hub (MCH) using four PCI Express lanes. Alternatively, the
82571/82572 Gigabit Ethernet Controller controller can connect to an I/O Control Hub
(ICH6 & 7) that has a PCI Express interface.
Wide internal data paths eliminate performance bottlenecks by efficiently handling
large address and data words. Combining a parallel and pipe-lined logic architecture
optimized for gigabit ethernet and independent transmit and receive queues, the
82571/82572 Gigabit Ethernet Controller efficiently handles packets with minimum
latency. The 82571/82572 Gigabit Ethernet Controller includes advanced interrupt
handling features. The 82571/82572 Gigabit Ethernet Controller uses efficient ring
buffer descriptor data structures, with up to 64 packet descriptors cached on-chip. A
large 48 KByte per port on-chip packet buffer maintains superior performance. In
addition, using hardware acceleration, the controller offloads tasks from the host, such
as TCP/UDP/IP checksum calculations and TCP segmentation.
The 82571/82572 Gigabit Ethernet Controller is packaged in a 17 mm x 17 mm, 256-
ball grid array.
1.1
1.2
Document Scope
This document contains targeted datasheet specifications for the 82571/82572 Gigabit
Ethernet Controller, including signal descriptions, DC and AC parameters, packaging
data, and pinout information.
Reference Documents
This application assumes that the designer is acquainted with high-speed design and
board layout techniques. The following documents provide additional information:
• 82571/82572 Gigabit Ethernet Controller Design Guide. Intel Corporation.
1
82571/82572 Gigabit Ethernet Controller—Datasheet
• Intel Ethernet Controllers Timing Device Selection Guide, AP-419. Intel
Corporation.
• PCI Express Base Specification, Revision 1.0a. PCI Special Interest Group.
• PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special
Interest Group.
• PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special
Interest Group.
• IEEE Standard 802.3, 2000 Edition. Institute of Electrical and Electronics Engineers
(IEEE). This version incorporates various IEEE standards previously published
separately.
2
Datasheet—82571/82572 Gigabit Ethernet Controller
1.3
Block Diagram
Figure 1.
82571/82572 Gigabit Ethernet Controller Block Diagram (Single Port Shown)
3
82571/82572 Gigabit Ethernet Controller—Datasheet
Note:
This page is intentionally left blank.
4
Datasheet—82571/82572 Gigabit Ethernet Controller
2.0
Features of the 82571/82572 Gigabit Ethernet
Controller
2.1
PCI Express Features
Features
Benefits
Bus sharing not required
Uses x4 PCI Express interface on MCH device
Low latency path to memory
Relieves congestion for IO devices
Peak bandwidth 2 GB/s in each direction per PCI
Express lane
Supports Gigabit Ethernet at full wire speed
Compatible extensions to PCI power management
and ACPI
PE_WAKE_n available for wakeup event
PCI Express Power Management
High bandwidth density per pin
Less congested board routing
2.2
MAC-Specific Features
Features
Benefits
•
•
Network packets handled without waiting or
buffer overflow.
Optimized transmit and receive queues
Control over the transmissions of pause frames
through software or hardware triggering
Frame loss reduced from receive overruns
Efficient use of PCI Express bandwidth
Efficient packet prioritization
IEEE 802.3x compliant flow control support with
software controllable pause times and threshold
values
•
•
•
Caches up to 64 packet descriptors (per queue)
Separate transmit queue per port
Programmable host memory receive buffers (256
Bytes to 16 KBytes) and cache line size (64 Bytes to
128 Bytes)
•
Efficient use of PCI Express bandwidth
•
•
Low latency data handling
Superior DMA transfer rate performance
Wide, pipelined internal data path architecture
•
•
No external FIFO memory requirements
FIFO size adjustable to application
Dual 48 KByte configurable Transmit and Receive
FIFO buffers
Descriptor ring management hardware for transmit
and receive
•
•
Simple software programming model
Optimized descriptor fetching and write-back
mechanisms
Efficient system memory and use of PCI Express
bandwidth
Mechanism available for reducing interrupts
generated by transmit and receive operations
•
•
Maximizes system performance and throughput
Enables jumbo frames
Supports transmission and reception of packets up to
9 kB
5
82571/82572 Gigabit Ethernet Controller—Datasheet
2.3
PHY Specific Features
Features
Benefits
•
•
•
Smaller footprint and lower power dissipation
compared to multi-chip MAC and PHY solutions
Integrated PHY for 10/100/1000 Mbps operation
Automatic link configuration including speed,
duplex, and flow control
IEEE 802.3ab Auto-Negotiation support
Robust operation over the installed base of
Category-5 (CAT-5) twisted pair cabling
IEEE 802.3ab PHY compliance and compatibility
•
•
Robust performance in noisy environments
Tolerance of common electrical signal
impairments
State-of-the-art DSP architecture implements digital
adaptive equalization, echo cancellation, and cross-
talk cancellation
•
•
Improved end-user troubleshooting
Tolerance of common wiring faults
PHY cable correction and diagnostics
•
•
•
Low-Power Link-Up (LPLU)
Smart Speed
Smart Power-Down
•
•
Enables link in low-power mode
Reacts to various link speeds
2.4
Host Offloading Features
Features
Benefits
Transmit and receive IP, TCP and UDP checksum off-
loading capabilities
•
Lower CPU utilization
•
•
Increased throughput and lower CPU utilization
Large send offload feature (in Microsoft*
Windows* XP) compatible
Transmit TCP segmentation
IPv6 Offloading
•
Checksum and segmentation capability extended
to new standard packet type
•
•
•
16 exact matched packets (unicast or multicast)
4096-bit hash filter for multicast frames
Promiscuous (unicast and multicast) transfer
mode support
Advanced packet filtering
•
•
•
Optional filtering of invalid frames
IEEE 802.1q VLAN support with VLAN tag insertion,
stripping and packet filtering for up to 4096 VLAN
tags
Ability to create multiple virtual LAN segments
Optimized fetching and write-back mechanisms
for efficient system memory and PCI bandwidth
usage
Descriptor ring management hardware for transmit
and receive
•
High throughput for large data transfers on
networks supporting jumbo frames
9 kB jumbo frame support
6
Datasheet—82571/82572 Gigabit Ethernet Controller
2.5
Manageability Features
Features
Benefits
Manageability features:
•
•
•
Alerting and control via standardized interfaces
Network management flexibility
Manageability data transfers up to 8 Mb/s peak
rate
•
One SMBus port with Fast Management Link
Capability
•
•
Alerting Standards Format 1.0 and 2.0
Advanced Power Management (Wake on LAN)
•
•
•
Enables effective ASF 2.0 implementations
Promotes customized designs
Allows packets routing to and from either LAN
port and a server management processor
On-board microcontroller
•
•
Supports serial text and keyboard redirection
Supports remote floppy/CD
Preboot eXecution Environment (PXE) Flash interface
support (32-bit nd 64-bit)
•
Local Flash interface for PXE image
Compliance with PCI Power Management 1.1 and
ACPI 2.0 register set compliant including:
•
PCI power management capability requirements
for PC and embedded applications
•
•
D0 and D3 power states
Network Device Class Power Management
Specification 1.1
•
•
•
Easy system monitoring with industry standard
consoles
SNMP and RMON statistic counters
SDG 3.0, WfM 3.0, and PC2001 compliance
Wake on LAN support
Remote network management capabilities
through DMI 2.0 and SNMP software
Packet recognition and wake-up for NIC and LOM
applications without software configuration
2.6
Additional Device Features
Features
Benefits
•
•
•
Inherent dual port teaming ability
High availability using one port for failover
Higher throughput than single Gigabit Ethernet
port
82571EB: Two complete Gigabit Ethernet connections
in a single device
•
Lower latency due to one electrical load on the
bus
•
•
Saves critical board space
Reduced multi-port Gigabit Ethernet costs
•
•
•
Supports backplane and fiber applications as well
as copper-based Gigabit
Integrated SERDES
Four activity and link indication outputs (per port)
that directly drive LEDs
Link and activity indications (10, 100, and 1000
Mbps) on each port
Software definable function (speed, link, and
activity) and blinking allowing flexible LED
implementations
Programmable LED functionality
Internal PLL for clock generation can use a 25 MHz
crystal
•
Lower component count and system cost
Simplified testing using boundary scan
JTAG (IEEE 1149.1) Test Access Port built in silicon
Four software definable pins per port
Provides loopback capabilities
•
•
Additional flexibility for LEDs or other low speed
I/O devices
•
Validates silicon integrity
7
82571/82572 Gigabit Ethernet Controller—Datasheet
2.7
Technology Features
Features
Benefits
•
•
17 mm X 17 mm component
occupies only 28% more board
space than a single port device
256-pin Flip-Chip Ball Grid Array (FC-BGA) package
Offers lowest geometry to minimize
power and size while maintaining
Intel quality and reliability standards
Implemented in 90 nm CMOS process
Operating temperature:
1000BASE-T, 0° C to 55° C (with thermal management)
1000BASE-T, 0° C to 70° C (with increased thermal
•
•
Simple thermal design
management)
1000BASE-SX/LX (or SERDES backplane), 0°C to 70° C
Storage temperature 65° C to 140° C
Typical targeted power dissipation:
~3.50 W @ D0 1000 Mbps
~0.78mW @ D3 100 Mbps (wakeup enabled)
~0.36mW @ D3 wakeup disabled
Minimizes impact of incorporating
Gigabit instead of Fast Ethernet.
8
Datasheet—82571/82572 Ethernet Controller
3.0
Signal Descriptions
Note:
The targeted signal names are subject to change without notice. Verify with your local
Intel sales office that you have the latest information before finalizing a design.
3.1
Signal Type Definitions
The signals of the controller are electrically defined as follows:
Name
Definition
Input
I
Standard input only digital signal.
Output
O
Standard output only digital signal.
Tri-state
TS
Bi-directional three-state digital input/output signal.
Open Drain
Wired-OR with other agents.
OD
The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a
weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully
restore the signal to the de-asserted state.
Analog
A
A(I)
A(O)
P
PCIe*, SERDES, or, PHY analog signal.
Analog-Input
Standard input only analog signal.
Analog-Output
Standard output only analog signal.
Power
Power connection, voltage reference, or other reference connection.
3.2
PCI Express Interface
Symbol
Type
Name and Function
High Speed Serial Receive Data
These signals connect to corresponding PETn and PETp signals on a system
motherboard or a PCI Express connector. Series AC coupling capacitors are
required at the transmitter end. The PCI Express differential inputs are clocked at
2.5 Gb/s.
PERn[3:0]
PERp[3:0]
A(I)
High Speed Serial Transmit Data
These signals connect to corresponding PERn and PERp signals on a system
motherboard or a PCI Express connector. Series AC coupling capacitors are
required at the 82571EB/82572EI controller end. The PCI Express differential
outputs are clocked at 2.5 Gb/s.
PETn[3:0]
PETp[3:0]
A(O)
9
82571/82572 Ethernet Controller—Datasheet
Symbol
Type
Name and Function
High Speed Serial Impedance Compensation
Connect the recommended resistor value across these balls. Refer to the
82571EB/82572EI Design Guide for the recommended value.
PE_RCOMPp
PE_RCOMPn
P
100 MHz Differential Clock for the PCI Express Interface
The reference clock is furnished by the system and has a 300 ppm frequency
tolerance.
PE_CLKp
PE_CLKn
I
I
PCI Express Reset
When the signal is low, all PCI Express functions are held in reset. When the
signal is high, it denotes that main power is available to the 82571EB/82572EI
controller and the reference clock is running.
PE_RST_N
In systems with a PCI Express add-in card, this signal routes to the connector.
3.3
Power Management Signals
Symbol
Type
Name and Function
Auxiliary Power Present.
AUX_PWR
I
If the Auxiliary Power signal is high, then auxiliary power is present and the
82571EB/82572EI device should support the D3
power state.
cold
LAN Disables 0 or 1
LAN0_DIS_N
LAN1_DIS_N/
RSVD_B8
Disables individual Ethernet ports. State is latched upon a rising edge of
PERST_N or a PCI Express reset event. This pin has an internal pull-up resistor.
I
I
Note: Both ports cannot be disabled at the same time.
Device Off
DEV_OFF_N
PE_WAKE_N
Asynchronously disables Ethernet controller, including voltage regulator control
outputs if selected in CTRL_EXT. This pin has an internal pull-up resistor.
Wake
The device drives this signal low when it receives a wake-up event and either
the PME Enable bit in the Power Management Control/Status Register or the
Advanced Power Management Enable (APME) bit of the Wake-up Control
Register (WUC) is 1b.
OD
10
Datasheet—82571/82572 Ethernet Controller
3.4
SMB and Fast Management Link Bus Signals
Symbol
Type
Name and Function
SMB Clock
The SMB Clock signals are open drain signals for the serial SMB interface
(Ports A and B). Alternatively, when SMB Port A is configured for a Fast
Management Link Bus, SMB Clock A becomes the Fast Management Link Bus
Master Clock. The Fast Management Link Bus can be clocked up to 6.5 MHz.
SMBCLK0/FLBMCK
I/O
Note: Only SMBus 0 is supported; use only SMBCLK0. SMBCLK1 (pin P13) is
reserved. Do not use this pin. Connect it to 3.3 V through a 100K ohm
resistor.
SMB Data
The SMB Data signals are open drain signals for the serial SMB interface
(Ports A and B). Alternatively, when SMB Port A is configured for a Fast
Management Link Bus, SMB Data A becomes Fast Management Link Bus
Master Data.
SMBD0/FLBMD
I/O
Note: Only SMBus 0 is supported; use only SMBD0. SMBD1 (pin P12) is
reserved. Do not use this pin. Connect it to 3.3 V through a 100K ohm
resistor.
SMB Alert
SMBALRT_N/
The SMB Alert signal is an open drain signal for serial SMB Port A. In ASF
mode, this signal acts as a power good input. It acts as an alert input in
82559 compatible mode.
I/O
O
PCI_PWR_GOOD
Fast Management Link Bus Slave Data.
When SMB Port A is configured for a Fast Management Link Bus, this signal
becomes the serial data path for slave data from the 82571EB/82572EI
controller.
FLBSD
Fast Management Link Bus Interrupt Extension
Driven by the 82571EB/82572EI controller as a slave to alert the master to
read data. Alternatively, it signals the master to extend the low phase of the
clock.
FLBINTEX
O
11
82571/82572 Ethernet Controller—Datasheet
3.5
EEPROM and Serial FLASH Interface Signals
Symbol
Type
Name and Function
EEPROM Data Input
The EEPROM Data Input pin is used for output to the SPI EEPROM memory device.
EE_DI
O
EEPROM Data Output
EE_DO
EE_CS_N
EE_SK
I
The EEPROM Data Output pin is used for input from the SPI EEPROM memory
device. The EE_DO includes an internal pull-up resistor.
EEPROM Chip Select
The EEPROM Chip Select signal is used to enable the device.
O
O
EEPROM Serial Clock
The EEPROM Shift Clock provides the clock rate for the SPI EEPROM interface, which
is approximately 2 MHz.
FLASH Chip Enable Output.
Used to enable FLASH device.
FLSH_CE_N
FLSH_SCK
FLSH_SI
O
O
O
I
FLASH Serial Clock Output.
Inout from the memory device.
FLASH Serial Data Input.
This pin is an output to the memory device.
FLASH Serial Data Output
This pin is an input from the memory device.
FLSH_SO
3.6
LED Signals
Symbol
Type
Name and Function
LED0_0.
LED0_0
O
O
O
O
O
O
O
O
Programmable LED output for Port A. As the Link LED, it indicates link connectivity
on Port A.
LED0_1.
LED0_1
LED0_2
LED0_3
Programmable LED output for Port A. As the Activity LED, it flashes to indicate
receive activity on Port A for packets destined for this node.
LED0_2
Programmable LED output for Port A. As the Link 100 LED, it indicates link at 100
Mbps for Port A.
LED0_3.
Programmable LED output for Port A. As the Link 1000 LED, it indicates link at 1000
Mbps for Port A.
LEDB0_N.
LED1_0/
RSVD_P8
Programmable LED output for Port B. As the Link LED, it indicates link connectivity
on Port B. (82571 only.)
LED1_1.
LED1_1/
RSVD_R8
Programmable LED output for Port B. As the Activity LED, it flashes to indicate
receive activity on Port B for packets destined for this node. (82571 EB only.)
LED1_2.
LED1_2/
RSVD_T8
Programmable LED output for Port B. As the Link 100 LED, it indicates link at 100
Mbps for Port B. (82571 EB only.)
LED1_3.
LED1_3/
RSVD_P9
Programmable LED output for Port B. As the Link 1000 LED, it indicates link at 1000
Mbps for Port B. (82571 EB only.)
12
Datasheet—82571/82572 Ethernet Controller
3.7
Other Signals
Symbol
Type
Name and Function
SDP0_1
SDP0_2
Software Defined Pin
SDP0_3
The Software Defined Pins are programmable with respect to input and output
capability. SDP0_3 and SDP1_3 may optionally be configured as interrupt inputs.
SDP signals default to inputs upon power-up, but may be configured differently
by the EEPROM.
SDP0_4
TS
SDP1_1/RSVD_P6
SDP1_2/RSVD_B6
SDP1_3/RSVD_C6
SDP1_4/RSVD_R6
3.8
Crystal Signals
Symbol
Type
Name and Function
Crystal One
The Crystal One pin is a 25 MHz input signal. It should be connected to a parallel
resonant crystal with a frequency tolerance of 30 ppm or better. The other end of the
crystal should be connected to XTAL2. Optionally, an oscillator can be connected to
XTAL 1. See the design guide for more information..
XTAL1
I
Crystal Two
XTAL2
O
Crystal Two is the output of an internal oscillator circuit used to drive a crystal into
oscillation.
3.9
PHY Analog Signals
Port 0
3.9.1
Symbol
Type
Name and Function
Bias Resistors
These are the reference connections for the Media Dependent Interface. The
recommended resistor value should be connected across the positive/negative pair, even if
the MDI interface is not used. Refer to the 82571EB/82572EI Design Guide for the
recommended value.
RBIAS0p
RBIAS0n
P
Media Dependent Interface [0]
1000BASE-T: In MDI configuration, these correspond to BI_DA+/-, and in MDI-X
configuration, they correspond to BI_DB+/-.
100BASE-TX: In MDI configuration, these are used for the transmit pair, and in MDI-X
configuration, they are used for the receive pair.
MDI_PLUS0_0
MDI_MINUS0_0
A
10BASE-T: In MDI configuration, they are used for the transmit pair, and in MDI-X
configuration, used for the receive pair.
13
82571/82572 Ethernet Controller—Datasheet
Symbol
Type
Name and Function
Media Dependent Interface [1]
1000BASE-T: In MDI configuration, these correspond to BI_DB+/-, and in MDI-X
configuration, they correspond to BI_DA+/-.
MDI_PLUS0_1
MDI_MINUS0_1
A
100BASE-TX: In MDI configuration, they are used for the receive pair, and in MDI-X
configuration, they are used for the transit pair.
10BASE-T: In MDI configuration, they are used for the receive pair, and in MDI-X
configuration, they are used for the transit pair.
Media Dependent Interface [2]
1000BASE-T: In MDI configuration, these correspond to BI_DC+/-, and in MDI-X
MDI_PLUS0_2
MDI_MINUS0_2
configuration, they correspond to BI_DD+/-.
A
A
100BASE-TX: Unused.
10BASE-T: Unused
Media Dependent Interface [3]
1000BASE-T: In MDI configuration, these correspond to BI_DD+/-, and in MDI-X
configuration, they correspond to BI_DC+/-.
100BASE-TX: Unused.
10BASE-T: Unused.
MDI_PLUS0_3
MDI_MINUS0_3
3.9.2
Port 1 (82571 Only)
Symbol
Type
Name and Function
Bias Resistors
These are the reference connections for the Media Dependent Interface. The
recommended resistor value should be connected across the positive/negative pair,
even if the MDI interface is not used. Refer to the 82571EB/82572EI Design Guide
for the recommended value.
RBIAS1p/RSVD_M14
RBIAS1n/RSVD_N14
P
Media Dependent Interface [0]
1000BASE-T: In MDI configuration, these correspond to BI_DA+/-, and in MDI-X
configuration, they correspond to BI_DB+/-.
100BASE-TX: In MDI configuration, these are used for the transmit pair, and in
MDI-X configuration, they are used for the receive pair.
10BASE-T: In MDI configuration, they are used for the transmit pair, and in MDI-X
configuration, used for the receive pair.
MDI_PLUS1_0/RSVD_T14
MDI_MINUS1_0/RSVD_R14
A
A
Media Dependent Interface [1]
1000BASE-T: In MDI configuration, these correspond to BI_DB+/-, and in MDI-X
configuration, they correspond to BI_DA+/-.
100BASE-TX: In MDI configuration, they are used for the receive pair, and in MDI-
X configuration, they are used for the transit pair.
MDI_PLUS1_1/RSVD_T15
MDI_MINUS1_1/RSVD_R15
10BASE-T: In MDI configuration, they are used for the receive pair, and in MDI-X
configuration, they are used for the transit pair.
Media Dependent Interface [2]
1000BASE-T: In MDI configuration, these correspond to BI_DC+/-, and in MDI-X
MDI_PLUS1_2/RSVD_P16
MDI_MINUS1_2/RSVD_P15
configuration, they correspond to BI_DD+/-.
A
A
100BASE-TX: Unused.
10BASE-T: Unused
Media Dependent Interface [3]
1000BASE-T: In MDI configuration, these correspond to BI_DD+/-, and in MDI-X
configuration, they correspond to BI_DC+/-.
100BASE-TX: Unused.
10BASE-T: Unused.
MDI_PLUS1_3/RSVD_N16
MDI_MINUS1_3/RSVD_N15
14
Datasheet—82571/82572 Ethernet Controller
3.10
Serializer / Deserializer Signals
Symbol
Type
Name and Function
SERDES Receive Pairs
Signals SRDSI_0_PLUS and SRDSI_0_MINUS make the differential
receive pair for the 1.25 GHz serial interface for Port 0. Inputs
should be PICMIG 3.1-compliant.
SRDSI_0_PLUS
SRDSI_0_MINUS
SRDSI_1_PLUS/RSVD_M16
SRDSI_1_MINUS/RSVD_L16
A(I)
Signals SRDSI_1_PLUS and SRDSI_1_MINUS make the differential
receive pair for the 1.25 GHz serial interface for Port 1. Inputs
should be PICMIG 3.1-compliant.
If the SERDES interface is not used, these pins should not be
connected.
SERDES Transmit Pairs
Signals SRDSO_0_PLUS and SRDSO_0_MINUS make the
differential transmit pair for the 1.25 GHz serial interface for Port 0.
Outputs drive PICMIG 3.1-compliant signals.
SRDSO_0_PLUS
SRDSO_0_MINUS
SRDSO_1_PLUS/RSVD_K15
SRDSO_1_MINUS/RSVD_L15
A(O)
Signals SRDSO_1_PLUS and SRDSO_1_MINUS make the
differential transmit pair for the 1.25 GHz serial interface for Port 1.
Outputs drive PICMIG 3.1-compliant signals.
If the SERDES interface is not used, these pins should not be
connected.
Signal Detects
These pins (SRDSA_SIG_DET for Port 0; SRDSB_SIG_DET for Port
1) indicate whether the SERDES signals (connected to the 1.25 GHz
serial interface) have been detected by the optical transceivers. If
the SERDES interface is not used, the SIG_DET inputs can be left
unconnected.
SRDSA_SIG_DET
SRDSB_SIG_DET/RSVD_C4
I
SERDES Impedance Compensation.
SRDS_RCOMPp
SRDS_RCOMPn
Connect the recommended resistor value across these balls, even if
not using the SERDES interface. Refer to the 82571EB/82572EI
Design Guide for the recommended value.
A
3.11
Test Interface Signals
Symbol
Type
Name and Function
JTCK
JTDI
I
I
JTAG Test Access Port Clock
JTAG Test Access Port Test Data In
JTAG Test Access Port Test Data Out
JTAG Test Access Port Mode Select
JTDO
JTMS
O
I
IEEE_TEST0p
IEEE_TEST0n
IEEE_TEST1p/RSVD_R13
IEEE_TEST1n/RSVD_T13
IEEE Analog Test Pins
Differential outputs providing reference clocks for IEEE PHY
conformance verification. For prototype testing, connect each pair to
two-pin headers. For production systems, leave pins unconnected.
O
THERM_Dp
THERM_Dn
Thermal Diode Reference
Can be used to measure the slicon device temperature.
O
I
Factory Test Pin
Attach a 1 KΩ pull-down resistor to ground for normal operation.
TEST_EN
15
82571/82572 Ethernet Controller—Datasheet
3.12
Power Supply Connections
Digital and Analog Supplies
3.12.1
Symbol
Type
Name and Function
3.3V Digital Power Supply.
For I/O circuits.
VCC33
P
1.8V Analog Power Supply
VCC18
VCC11
P
P
For PHY analog, PHY I/O, PCI Express analog, and Phase Lock Loop circuits, Connect
all 1.8V pins to a single power supply.
1.1V Digital Power Supply
For core digital, PHY digital, PCI Express digital and clock circuits, connect all 1.1V pins
to a single power supply.
3.12.2
Grounds, Reserved Pins and No Connects
Symbol
Type
Name and Function
Analog Ground
VSSA
P
Connects to PHY analog circuits. Connect directly to analog ground.
Digital Ground
Connects to core and digital I/O. Connect to GND.
VSS
P
P
P
Reserved Pin
These pins are reserved by Intel and may have factory test functions. For normal
operation, do not connect any circuitry to these pins (allow them to “float”). Some
special configurations may require pull-up or pull-down resistors on these pins.
Please refer to the 82571EB/82572EI design guide for more information.
RSVD_ pin#
NC_pin#
No Connect
This pin is not connected internally.
16
Datasheet—82571/82572 Gigabit Ethernet Controller
4.0
Voltage, Temperature, and Timing Specifications
4.1
Targeted Absolute Maximum Ratings
Table 1.
Absolute Maximum Ratingsa
Symbol
VCC(3.3)
Parameter
Min
Max
Unit
DC supply voltage on 3.3V pins
with respect to VSS
VSS - 0.5
4.6
V
DC supply voltage on 1.8V pins
VCC(1.8)
VCC(1.1)
VSS - 0.3
VSS - 0.2
2.5
1.7
V
V
b
with respect to VSS
DC supply voltage on 1.1V pins
b
with respect to VSS
3.3V I/O Voltage
1.8V I/O Voltage
1.1V I/O Voltage
VSS - 0.5
VSS - 0.3
VSS - 0.2
4.6
2.5
1.7
V / V
V
I
O
I
DC output current
N/A
30
mA
O
T
Storage temperature range
-65
140
storage
°C
V
ESD per MIL_STD-883 Test
Method 3015, Specification 2001V
Latchup Over/Undershoot: 150
mA, 125° C
VDD overstress:
VDD(3.3) * (7.2 V)
N/A
a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings
in this table are exceeded for an indefinite duration. These values should not be used as the limits for normal
device operations.
b. During normal device power up and power down, the 1.8V and 1.1V supplies must not ramp before the 3.3V
supply.
4.2
Targeted Recommended Operating Conditions
General Operating Conditions
4.2.1
Table 2.
Recommended Operating Conditions a
Symbol
VCC(3.3)
Parameter
Min
Max
Unit
DC supply voltage on 3.3V pins
DC supply voltage on 1.8V pins
DC supply voltage on 1.1V pins
3.0
1.71
1.045
0
3.6
1.89
1.155
200
V
V
b
VCC(1.8)
VCC(1.1)
tR / tF
V
Input rise/fall time (normal input)
ns
Operating temperature range
(ambient)
c
T
0
55
°C
°C
a
T
Junction temperature
N/A
≤110
J
a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute
maximum rating limits, might result in permanent damage. Device functionality to stated DC and AC limits is
not guaranteed, if conditions exceed recommended operating conditions.
b. See Section 4.2.2 for voltage ramp and sequencing recommendations.
c. 1000BASE-T designs require thermal management (heatsink and/or forced air flow) to achieve 0° to 55° C
operation. Increased thermal management can increase this temperature range to 0° to 70° C. Applications
using the SERDES interface are rated for 0° to 70° C without thermal management.
17
82571/82572 Gigabit Ethernet Controller—Datasheet
4.2.2
Voltage Ramps
Table 3.
3.3V Supply Voltage Ramp
Parameter
Description
Min
Max
Unit
a
Rise Time
Time from 10% to 90% mark
Voltage dip allowed in ramp
0.1
100
ms
Monotonicity
N/A
0
mV
Ramp rate at any time between 10%
to 90%
Slope
24
3
28000
mV/ms
V
Operational
Range
Voltage range for normal operating
conditions
3.6
70
Maximum voltage ripple at a
bandwidth equal to 50 MHz
Ripple
N/A
mV
peak-peak
Overshoot
Settling Time
b
Overshoot time upon ramp
N/A
N/A
0.05
100
ms
b
Overshoot
Maximum voltage allowed
mV
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
b. Excessive overshoot can affect long term reliability.
Table 4.
1.8V Supply Voltage Ramp
Parameter
Description
Min
Max
Unit
a
Rise Time
Time from 10% to 90% mark
Voltage dip allowed in ramp
0.1
100
ms
Monotonicity
N/A
0
mV
Ramp rate at any time between 10%
to 90%
Slope
14
60000
mV/ms
V
Operational
Range
Voltage range for normal operating
conditions
1.71
N/A
1.89
40
Maximum voltage ripple at a
bandwidth equal to 1 MHz
Ripple
mV
peak-peak
Overshoot
SettlingTime
b
Overshoot time upon ramp
N/A
N/A
0.1
ms
b
Overshoot
Maximum voltage allowed
100
mV
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
b. Excessive overshoot can affect long term reliability.
Table 5.
1.1V Supply Voltage Ramp
Parameter
Description
Min
Max
Unit
a
Rise Time
Time from 10% to 90% mark
Voltage dip allowed in ramp
0.1
100
ms
Monotonicity
N/A
0
mV
Ramp rate at any time between 10%
to 90%
Slope
7.6
1.045
N/A
33600
mV/ms
V
Operational
Range
Voltage range for normal operating
conditions
1.155
40
Maximum voltage ripple at a
bandwidth equal to 1 MHz
Ripple
mV
peak-peak
Overshoot
b
Overshoot time upon ramp
N/A
N/A
0.05
100
ms
SettlingTime
b
Overshoot
Maximum voltage allowed
mV
a. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
b. Excessive overshoot can affect long term reliability.
18
Datasheet—82571/82572 Gigabit Ethernet Controller
4.2.3
Voltage Power Sequencing Options
To meet 375 mA inrush current requirements (not including external capacitors) the
ramp time should be 5 ms -100 ms on all power rails. For faster ramps (100 us - 5
ms), expect higher inrush current due to the high charging current of the decoupling
capacitors of 3.3V, 1.8V and 1.1V rails.
4.3
DC Specifications
Table 6.
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
DC supply voltage on 3.3V
pins
VCC(3.3)
3.00
3.30
3.60
V
DC supply voltage on 1.8V
pins
VCC(1.8)
VCC(1.1)
1.71
1.80
1.89
V
V
DC supply voltage on 1.1V
pins
1.045
1.100
1.155
4.3.1
Power Specifications--82571EB
Table 7.
D0a--Active Link
D0a--Active Link
@10
Mbps
@100
Mbps
@ 1000 Mbps
(copper)
@ 1000 Mbps
(SERDES)
Typ
Icc
(mA)
Typ
Icc
(mA)
Typ
Icc
(mA)
Max
Icc
(mA)
Typ
Icc
(mA)
Max
Icc
(mA)
a
a
a
a
a
b
3.3V
1.8V
1.1V
26
26
26
34
42
46
350
370
399
456
893
913
254
529
282
1022
1520
1002
Total
Device
Power
1.12W
1.31W
2.82W
3.43W
1.18W
1.76W
a. Typical conditions: operating temperature (T ) = 25 C, nominal
A
voltages and continuous network traffic at link speed at full duplex.
b. Maximum conditions: maximum operating temperature (T ) values,
J
typical voltage values and continuous network traffic at link speed at
full duplex.
19
82571/82572 Gigabit Ethernet Controller—Datasheet
Table 8.
D0a--Idle Link L0s Only
D0a--Idle Link
L0s Only
Unplugged--no
link
@1000Mbps
(copper)
@10Mbps
@100Mbps
a
Typ Icc (mA)
3.3V
1.8V
1.1V
26
26
26
26
130
332
123
334
306
414
837
839
Total
Device
Power
0.69W
0.67W
1.10W
2.52W
a. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network
(no traffic) at full duplex
Table 9.
D3cold
D3cold - wake-up
D3cold-
enabled
wake
disabled
(no link)
@10
Mbps
@100
Mbps
Typ Icc
Typ Icc
Typ Icc
a,
b
a, b
a b
(mA)
(mA)
(mA)
3.3V
1.8V
1.1V
26
74
26
26
76
243
236
133
123
Total
Device
Power
0.37W
0.78W
0.36W
a. D3 Cold activated on a Windows Server 2003
OS--using Hbernate mode
b. L0s enable, L1 disabled
Table 10.
D(r) Unintialized
D(r) Uninitialized
Disabled through
LAN_DIS_N
Typ Icc (mA)
Disabled through
DEV_OFF_N
Typ Icc (mA)
3.3V
1.8V
1.1V
26
63
26
68
83
130
Total Device
Power
0.34W
0.30W
20
Datasheet—82571/82572 Gigabit Ethernet Controller
4.3.2
Power Specifications--82572EI
Table 11.
D0a--Active Link
D0a--Active Link
@10
Mbps
@100
Mbps
@ 1000 Mbps
(copper)
Typ
Icc
(mA)
Typ
Icc
(mA)
Typ
Icc
(mA)
Max
Icc
(mA)
a
a
a
a
3.3V
1.8V
1.1V
26
26
26
34
210
291
211
232
484
494
502
1023
Total
Device
Power
0.78W
0.72W
1.50W
2.14W
a. Typical conditions: operating temperature (T )
A
=
25 C, nominal voltages and continuous
network traffic at link speed at full duplex.
Table 12.
D0a--Idle Link
D0a--Idle Link
L0s Only
Unplugged--no
link
@1000Mbps
(copper)
@10Mbps
@100Mbps
a
Typ Icc (mA)
3.3V
1.8V
1.1V
26
26
26
26
111
176
102
179
199
218
425
839
Total
Device
0.48W
0.47W
0.68W
1.77W
Power
b
a. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network
(no traffic) at full duplex
b. LOs enabled; L1 disabled
21
82571/82572 Gigabit Ethernet Controller—Datasheet
Table 13.
D3cold
D3cold - wake-up
enabled
D3cold-wake
disabled;
unplugged, no link
@10
Mbps
@100
Mbps
Typ Icc
Typ Icc
a b
Typ Icc (mA)
a,
b
a, b
(mA)
(mA)
3.3V
1.8V
1.1V
26
77
26
26
84
173
163
120
110
Total
Device
Power
0.36W
0.58W
0.36W
a. D3 Cold activated on a Windows Server 2003 OS--using
Hbernate mode
b. LOs enabled, L1 disabled
Table 14.
D(r) Unintialized
D(r) Uninitialized
Disabled through
LAN_DIS_N
Typ Icc (mA)
Disabled through
DEV_OFF_N
Typ Icc (mA)
3.3V
1.8V
1.1V
26
60
26
68
83
114
Total Device
Power
0.32W
0.30W
4.3.3
I/O Characteristics
Table 15.
I/O Characteristicsa
Symbol
Parameter
Condition
Min
Typ
Max
Units
VCC(3.3)
+ 0.5
V
Input high voltage
Input low voltage
Input current
2.0
-0.5
-15
N/A
N/A
N/A
V
V
IH
IL
V
0.8
15
V
V
= VDD(3.3) or
IN
SS
I
µA
IN
I
V
= -16 mA
= Min
OH
2.4
N/A
N/A
N/A
N/A
N/A
N/A
0.4
0.2
CC
V
V
Output high voltage
Output low voltage
V
V
OH
OL
I
V
= -100 µA
= Min
OH
V
- 0.02
CC
CC
I
V
= 14 mA
= Min
OL
N/A
N/A
CC
I
V
= 100 µA
= Min
OL
CC
22
Datasheet—82571/82572 Gigabit Ethernet Controller
Table 15.
I/O Characteristicsa
Symbol
Parameter
Condition
= V or V
SS
Min
Typ
Max
Units
Off-state output leakage
current
I
V
-10
N/A
10
µA
OZ
b
O
CC
C
Input capacitance
Internal pull-up
N/A
2.6
2.5
N/A
5.5
pF
IN
PU
N/A
kΩ
a. The input buffer also has hysteresis > 160 mV.
b. C = 2.5 pF(maximum input capacitance), C
= 16 pF (characterized max output load capacitance per 160
in
out
MHz).
4.4
Targeted AC Characteristics
Table 16.
25 MHz Clock Input Requirements
Symbol
Parameter
Min
Typ
Max
Unit
f0
Frequency
N/A
-50
40
25.000
N/A
N/A
N/A
N/A
N/A
20
N/A
+50
60
MHz
ppm
%
df0
Dc
tr
Frequency Variation
Duty Cycle
Rise Time
N/A
N/A
N/A
N/A
N/A
5
ns
tf
Fall Time
5
ns
a
Jptp
Clock Jitter (peak-to-peak)
Input Capacitance
Operating Temperature
250
N/A
70
ps
C
T
pF
in
N/A
°C
Input clock amplitude (peak-to-
peak)
Aptp
Vcm
1.0
1.2
0.6
1.3
V
V
Clock common mode
N/A
N/A
a. Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE 1000Base-T Standard (at
5
least 10 clock edges, filtered by HPF with cut off frequency of 5000 Hz).
Table 17.
Reference Crystal Specification Requirements
Specification
Value
Vibrational Mode
Fundamental
25.000 MHz at 25 °C
Nominal Frequency
•
•
±30 ppm recommended
±50 ppm across the entire
operating temperature range
(required by IEEE
Frequency Tolerance
specifications)
Temperature Stability
Calibration Mode
Load Capacitance
Shunt Capacitance
Series Resistance, Rs
Drive Level
+/- 30 ppm at 0 °C to 70 °C
Parallel
20 pF to 24 pF
6 pF maximum
50 Ω maximum
0.5 mW maximum
+/- 5.0 ppm per year maximum
500 ΜΩ minimum at DC 100 V
Aging
Insulation Resistance
23
82571/82572 Gigabit Ethernet Controller—Datasheet
Table 17.
Reference Crystal Specification Requirements
Specification
Value
Board Capacitance
External Capacitors
Board Resistance
4 pF
27 pF
0.1 Ω
Table 18.
Link Interface Clock Requirements
Symbol
Parameter
GTX_CLK frequency
Min
Typ
Max
Unit
a
fGTX
N/A
125
N/A
MHz
a. GTX_CLK is used externally for test purposes only.
Table 19.
Table 20.
EEPROM Interface Clock Requirements
Symbol
Parameter
SPI EEPROM Clock
Min
Typ
Max
Unit
fSK
N/A
2
2.1
MHz
AC Test Loads for General Output Pins
Symbol
Parameter
Min
Typ
Max
Unit
C
Capacitance of test load
N/A
16
N/A
pF
L
CL
Figure 2.
AC Test Loads for General Output Pins
4.5
Targeted Timing Specifications
Note:
Timing specifications are preliminary and subject to change. Verify with your local Intel
sales office that you have the latest information before finalizing a design.
24
Datasheet—82571/82572 Gigabit Ethernet Controller
4.5.1
PCI Express Interface
4.5.1.1
Differential Transmitter (TX) Output Specifications
Table 21.
Differential Transmitter (TX) Output Specifications
Symbol
Parameter
Min
Typ
Max
Units
UI
Unit Interval
399.88
400
400.12
ps
DifferentialPeak
to Peak Output
Voltage
V
V
0.800
-3.0
N/A
1.2
V
TX-DIFFp-p
De-Emphasized
Differential
Output Voltage
(Ratio)
-3.5
-4.0
dB
TX-DE-RATIO
Minimum TX
Eye Width
T
0.70
N/A
N/A
N/A
N/A
UI
UI
TX-EYE
D+/D- TX
Output Rise/Fall
Time
T
T
TX-RISE,
TX-FALL
0.125
RMS AC Peak
Common Mode
Output Voltage
V
N/A
0
N/A
N/A
N/A
N/A
20
25
mV
mV
mV
mV
TX-CM-ACp
Absolute Delta
of DC Common
Mode Voltage
between D+
and D-
V
DELTA
TX-CM-DC-LINE-
Electrical Idle
DifferentialPeak
Output Voltage
V
V
0
20
TX-IDLE-DIFFp
TX-RCV-DETECT
The amount of
voltage change
allowed during
Receiver
N/A
600
Detectoin
Differential
Return Loss
RL
12
6
N/A
N/A
100
N/A
N/A
N/A
dB
dB
TX-DIFF
Common Mode
Return Loss
RL
TX-CM
DC Differential
TX Impedance
Z
80
N/A
120
TX-DIFF-DC
Ω
Lane-toLane
Output Skew
L
500 + 2 UI
ps
TX-SKEW
25
82571/82572 Gigabit Ethernet Controller—Datasheet
VTX-DIFF = 0 mV
(D+ D- Crossing Point)
VTX-DIFF = 0 mV
(D+ D- Crossing Point)
[Transition Bit]
TX-DIFFp-p-MIN = 800 mV
V
[De-emphasized Bit]
566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)
0.7 UI = UI - 0.3 UI(JTX-TOTAL-MAX
)
[Transition Bit]
V
TX-DIFFp-p-MIN = 800 mV
Figure 3.
PCI Express Transmitter Eye Diagram
D+ Package Pin
C = C
TX
TX
Silicon + Package
C = C
TX
D- Package Pin
R = 50 Ω
R = 50 Ω
Figure 4.
PCI Express Transmitter Test Load
26
Datasheet—82571/82572 Gigabit Ethernet Controller
4.5.1.2
Differential Receiver (RX) Input Specifications
Differential Receiver (RX) Output Specifications
Table 22.
Symbol
Parameter
Min
Typ
Max
Units
UI
Unit Interval
399.88
400
400.12
ps
DifferentialPeak
to Peak Output
Voltage
V
R
V
0.175
0.4
N/A
N/A
N/A
1.2
N/A
150
V
RX-DIFFp-p
Minimum RX
Eye Width
UI
TX-EYE
AC Peak
Common Mode
Input Voltage
N/A
mV
RX-CM-ACp
Differential
Return Loss
RL
RL
15
6
N/A
N/A
N/A
N/A
dB
dB
RX-DIFF
RX-CM
Common Mode
Return Loss
DC Differential
Input
Z
80
100
N/A
120
20
RX-DIFF-DC
Ω
Impedance
L
Total Skew
N/A
ns
RX-SKEW
VRX-DIFF = 0 mV
VRX-DIFF = 0 mV
(D+ D- Crossing Point)
(D+ D- Crossing Point)
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
Figure 5.
PCI Express Receiver Eye Diagram
27
82571/82572 Gigabit Ethernet Controller—Datasheet
4.5.2
EEPROM Interface
Table 23.
EEPROM Interface Time Specifications
Symbol
Parameter
Min
Typ
Max
Units
SCK clock
frequency
t
0
2
2.1
MHz
SCK
t
t
t
t
t
t
t
Input rise time
Input fall time
N/A
N/A
200
200
250
250
250
2.5 ns
2.5 ns
250
2
µs
µs
ns
ns
ns
ns
ns
RI
2
FI
a
SCK high time
N/A
N/A
N/A
N/A
N/A
WH
WH
CS
a
SCK low time
250
CS high time
CS setup time
CS hold time
N/A
N/A
CSS
CSH
N/A
Data-in setup
time
t
50
N/A
N/A
ns
SU
Data-in hold
time
t
t
t
50
0
N/A
N/A
N/A
N/A
200
N/A
ns
ns
ns
H
Output Valid
V
Output hold
time
0
HO
Output disable
time
t
t
N/A
N/A
N/A
N/A
250
10
ns
DIS
WC
Write cycle time
ms
a. 50% duty cycle.
tCS
VIH
CS
VIL
tCSS
tCSH
VIH
SCK
tWL
tWH
VIL
tSU
tH
VIH
SI
VALID IN
VIL
tV
tHO
tDIO
VIH
SO
VIL
Hi-Z
Hi-Z
Figure 6.
EEPROM Interface Time Diagram
28
Datasheet—82571/82572 Gigabit Ethernet Controller
4.5.3
FLASH Interface
Table 24.
FLASH Interface Time Specifications
Symbol
Parameter
Min
Typ
Max
Units
SCK clock
frequency
t
0
15.625
20
MHz
SCK
t
t
t
t
t
t
t
Input rise time
Input fall time
N/A
N/A
20
2.5 ns
2.5 ns
32
20
ns
ns
ns
ns
ns
ns
ns
RI
20
FI
a
SCK high time
N/A
N/A
N/A
N/A
N/A
WH
WH
CS
a
SCK low time
20
32
CS high time
CS setup time
CS hold time
25
N/A
N/A
N/A
25
CSS
CSH
250
Data-in setup
time
t
5
N/A
N/A
ns
SU
Data-in hold
time
t
t
t
5
0
0
N/A
N/A
N/A
N/A
20
ns
ns
ns
H
Output Valid
V
Output hold
time
N/A
HO
Output disable
time
t
t
N/A
N/A
N/A
60
100
100
ns
DIS
EC
Erase cycle time
per sector
µs
a. 50% duty cycle.
tCS
VIH
CS
VIL
tCSH
tcss
VIH
tWH
tWL
Sck
VIL
tSU
tH
VIH
SI
VALID IN
VIL
tHO
tDIS
tv
VOH
HI-Z
SO
HI-Z
VOL
Figure 7.
FLASH Interface Time Diagram
29
82571/82572 Gigabit Ethernet Controller—Datasheet
30
Datasheet—82571/82572 Gigabit Ethernet Controller
5.0
Package and Pinout Information
This section describes the 82571/82572 Gigabit Ethernet Controller’s physical
characteristics. The pin number-to-signal mapping is indicated beginning with Table 25.
Note:
The targeted signal names are subject to change without notice. Verify with your local
Intel sales office that you have the latest information before finalizing a design.
5.1
Package Information
The device is a 256-lead flip-chip ball grid array (FC-BGA) measuring 17 mm x 17 mm.
The nominal ball pitch is 1 mm. See Figure 9.
Detail Area
0.43 mm
Solder Resist Opening
0.62 mm
Metal Diameter
Figure 8.
82571EB/82572EI Controller FC-BGA Package Ball Pad Dimensions
31
82571/82572 Gigabit Ethernet Controller—Datasheet
Figure 9.
Mechanical Specifications
32
Datasheet—82571/82572 Gigabit Ethernet Controller
5.2
Thermal Specification
The device is specified for operation when the ambient temperature (TA) is within the
range of 0° C to 55° C. For more information about the thermal characteristics of the
device, including operation outside of this range, please refer to the 82571EB/82572EB
Thermal Application Note, AP-490
5.3
Pinout Information
Signal names apply to both the 82571EB and the 82572EI unless there is a “/”, which
indicates that the the first name is for the 82571EB and the second name is for the
82572EI.
Table 25.
PCI Express Signals
Signal
Pin
Signal
Pin
Signal
Pin
PERn0
PERp0
PERn1
PERp1
PERn2
PERp2
PE_CLKn
R2
T2
M2
N2
E1
F1
J2
PERn3
PERp3
PETn0
PETp0
B1
C1
P1
R1
L1
PETn2
PETp2
D2
E2
A2
B2
G2
H2
T6
PETn3
PETp3
PETn1
PETp1
PE_CLKp
PE_RCOMPn
PE_RCOMPp
PE_RST_N
M1
K2
Table 26.
Table 27.
Table 28.
Power Management Signals
Signal
Pin
Signal
Pin
LAN0_DIS_N
B7
PE_WAKE_N
P11
LAN1_DIS_N/
RSVD_B8
B8
T3
AUX_PWR
C8
DEV_OFF_N
SMB/Fast Management Link Bus Signals
Signal
Pin
Signal
Pin
SMBALRT_N/
PCI_PWR_GOOD
SMBCLK0/FLBMCK
SMBD0/FLBMD
T12
R12
R11
FLBSD
P7
R7
FLBINTEX
EEPROM and Serial FLASH Interface Signals
Signal
Pin
Signal
Pin
Signal
Pin
EE_SK
EE_DO
EE_DI
B12
A12
C12
EE_CS_N
FLSH_SCK
FLSH_CE_N
C13
R10
P10
FLSH_SI
FLSH_SO
T9
R9
33
82571/82572 Gigabit Ethernet Controller—Datasheet
Table 29.
Table 30.
Table 31.
LED Signals
Signal
Pin
Signal
Pin
Signal
Pin
LED0_0
LED0_2
LED0_3
B11
B10
C10
LED0_1
C11
P8
LED1_3/RSVD_P9
LED1_1/RSVD_R8
P9
R8
LED1_0/RSVD_P8
LED1_2/RSVD_T8
T8
Other Signals
Signal
Pin
Signal
Pin
SDP0_0
SDP0_1
SDP0_2
SDP0_3
B9
A9
C9
A8
SDP1_0/RSVD_P6
SDP1_1/RSVD_B6
SDP1_2/RSVD_C6
SDP1_3/RSVD_R6
P6
B6
C6
R6
PHY and SERDES Signals
Signal
Pin
Signal
Pin
Signal
Pin
MDI_MINUS1_3/
RSVD_N15
MDI_MINUS0_0
B14
N15
SRDSI_0_MINUS
F16
MDI_PLUS1_3/
RSVD_N16
MDI_PLUS0_0
MDI_MINUS0_1
MDI_PLUS0_1
MDI_MINUS0_2
MDI_PLUS0_2
MDI_MINUS0_3
A14
B15
A15
C15
C16
D15
P16
D16
T15
P15
N16
D14
E14
N14
M14
F15
G15
R14
T14
R15
SRDSI_0_PLUS
E16
L15
K15
C4
SRDSO_1_MINUS/
RSVD_L15
RBIAS0n
RBIAS0p
SRDSO_1_PLUS/
RSVD_K15
RBIAS1n/
RSVD_N14
SRDSB_SIG_DET/
RSVD_C4
RBIAS1p/
RSVD_M14
SRDSI_1_MINUS/
RSVD_L16
L16
M16
B4
SRDSI_1_PLUS/
RSVD_M16
SRDSO_0_MINUS
SRDSO_0_PLUS
MDI_PLUS1_2/
RSVD_P16
SRDSA_SIG_DET
SRDS_RCOMPn
SRDS_RCOMPp
MDI_MINUS1_0/
RSVD_R14
MDI_PLUS0_3
H14
H15
MDI_PLUS1_1/
RSVD_T15
MDI_PLUS1_0/
RSVD_T14
MDI_MINUS1_2/
RSVD_P15
MDI_MINUS1_1/
RSVD_R15
34
Datasheet—82571/82572 Gigabit Ethernet Controller
Table 32.
Test Interface Signals
Signal
Pin
Signal
Pin
Signal
Pin
JTCK
JTDI
P4
R3
IEEE_TEST0n
IEEE_TEST0p
A13
B13
THERM_Dp
THERM_Dn
D4
D5
IEEE_TEST1n/
RSVD_T13
JTDO
P5
T13
R13
IEEE_TEST1p/
RSVD_R13
JTMS
P3
R5
TEST_EN
Table 33.
Table 34.
Crystal Signals
Signal
Pin
XTAL1
XTAL2
J16
H16
Power Signals
Signal
Pin
Signal
Pin
Signal
Pin
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
VCC18
A4
A10
D7
VCC18
VCC18
VCC18
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
M4
M5
K4
E7
E9
E13
F7
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
VCC11
M9
M13
E12
F13
G12
K12
L13
M12
F12
L12
J4
D9
N7
N9
T5
T11
E10
F10
G10
H10
J10
K10
L10
M10
H4
F9
G7
G9
H7
H9
J7
J5
N4
J9
N5
K7
K9
L7
H5
L9
K5
M7
Table 35.
Ground Signals (Sheet 1 of 2)
Signal
Pin
Signal
Pin
Signal
Pin
VSSA
VSSA
VSSA
A1
VSSA
VSSA
VSSA
H13
J3
VSS
VSS
VSS
A5
A11
D6
A16
B16
J11
35
82571/82572 Gigabit Ethernet Controller—Datasheet
Table 35.
Ground Signals (Sheet 2 of 2)
Signal
Pin
Signal
Pin
Signal
Pin
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
C2
C14
D1
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
J12
J13
K1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D8
D10
E5
E6
E8
F5
D3
K3
D11
D12
D13
E3
K11
K13
K14
K16
L2
F6
F8
E4
G6
G8
H6
H8
J6
E11
E15
F2
L3
L4
L5
F3
L11
L14
M3
F4
J8
F11
F14
G1
K6
K8
L6
M11
M15
N1
G3
L8
G4
N3
M6
M8
N6
N8
N10
T4
G5
N11
N12
N13
P2
G11
G13
G14
G16
H3
P14
R16
T1
T10
H11
H12
T16
36
Datasheet—82571/82572 Gigabit Ethernet Controller
Table 36.
82571 Reserved and No Connect Signals
Note:
These pins are reserved by Intel and may have factory test functions. For normal
operation, do not connect any circuitry to these pins (allow them to “float”). Some
configurations may require pull-up or pull-down resistors on these pins. Please refer to
the 82571EB/82572EI design guide for more information.
Signal
Pin
Signal
Pin
RSVD_A3
RSVD_ A6
DEVICE_DIS_N
RSVD_B3
A3
A6
A7
B3
B5
C3
C5
C7
RSVD_H1
RSVD_J1
H1
J1
RSVD_J14
RSVD_J15
SMBD1
J14
J15
P12
P13
R4
RSVD_ B5
RSVD_ C3
RSVD_ C5
RSVD_ C7
SMBCLK1
LAN_PWR_GOOD
NC_T7
T7
37
82571/82572 Gigabit Ethernet Controller—Datasheet
Table 37.
82571 Signal Names in Pin Order
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
A2
VSSA
PETn3
C9
C10
C11
C12
C13
C14
C15
C16
D1
SDP0_2
LED0_3
LED0_1
EE_DI
F1
F2
PERp2
VSSA
A3
RSVD_A3
VCC33
F3
VSSA
A4
F4
VSSA
A5
VSS
EE_CS_N
VSSA
F5
VSS
A6
RSVD_A6
DEVICE_DIS_N
SDP0_3
F6
VSS
A7
MDI_MINUS0_2
MDI_PLUS0_2
VSSA
F7
VCC11
VSS
A8
F8
A9
SDP0_1
F9
VCC11
VCC18
VSSA
A10
A11
A12
A13
A14
A15
A16
B1
VCC33
D2
PETn2
F10
F11
F12
F13
F14
F15
F16
G1
VSS
D3
VSSA
EE_DO
D4
THERM_Dp
THERM_Dn
VSS
VCC11
VCC11
VSSA
IEEE_TEST0n
MDI_PLUS0_0
MDI_PLUS0_1
VSSA
D5
D6
D7
VCC33
SRDSO_0_MINUS
SRDSI_0_MINUS
VSSA
D8
VSS
PERn3
D9
VCC33
B2
PETp3
D10
D11
D12
D13
D14
D15
D16
E1
VSS
G2
PE_RCOMPn
VSSA
B3
RSVD_B3
SRDSA_SIG_DET
RSVD_B5
SDP1_1
VSSA
G3
B4
VSSA
G4
VSSA
B5
VSSA
G5
VSSA
B6
RBIAS0n
MDI_MINUS0_3
MDI_PLUS0_3
PERn2
G6
VSS
B7
LAN0_DIS_N
LAN1_DIS_N
SDP0_0
G7
VCC11
VSS
B8
G8
B9
G9
VCC11
VCC18
VSSA
B10
B11
B12
B13
B14
B15
B16
C1
LED0_2
E2
PETp2
G10
G11
G12
G13
G14
G15
G16
H1
LED0_0
E3
VSSA
EE_SK
E4
VSSA
VCC11
VSSA
IEEE_TEST0p
MDI_MINUS0_0
MDI_MINUS0_1
VSSA
E5
VSS
E6
VSS
VSSA
E7
VCC11
SRDSO_0_PLUS
VSSA
E8
VSS
PERp3
E9
VCC11
RSVD_H1
PE_RCOMPp
VSSA
C2
VSSA
E10
E11
E12
E13
E14
E15
E16
VCC18
H2
C3
RSVD_C3
SRDSB_SIG_DET
RSVD_C5
SDP1_2
VSSA
H3
C4
VCC11
H4
VCC18
VCC18
VSS
C5
VCC11
H5
C6
RBIAS0p
VSSA
H6
C7
RSVD_C7
AUX_PWR
H7
VCC11
VSS
C8
SRDSI_0_PLUS
H8
38
Datasheet—82571/82572 Gigabit Ethernet Controller
Table 37.
82571 Signal Names in Pin Order
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
H9
H10
H11
H12
H13
H14
H15
H16
J1
VCC11
VCC18
VSSA
L1
L2
PETn1
VSSA
N9
N10
N11
N12
N13
N14
N15
N16
P1
VCC33
VSS
L3
VSSA
VSSA
VSSA
L4
VSSA
VSSA
VSSA
L5
VSSA
VSSA
SRDS_RCOMPn
SRDS_RCOMPp
XTAL2
L6
VSS
RBIAS1n
MDI_MINUS1_3
MDI_PLUS1_3
PETn0
L7
VCC11
VSS
L8
RSVD_J1
PE_CLKn
VSSA
L9
VCC11
VCC18
VSSA
J2
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
P2
VSSA
J3
P3
JTMS
J4
VCC11
VCC11
VSS
VCC11
VCC11
VSSA
P4
JTCK
J5
P5
JTDO
J6
P6
SDP1_0
J7
VCC11
VSS
SRDSO_1_MINUS
SRDSI_1_MINUS
PETp1
P7
FLBSD
J8
P8
LED1_0
J9
VCC11
VCC18
VSSA
P9
LED1_3
J10
J11
J12
J13
J14
J15
J16
K1
PERn1
VSSA
P10
P11
P12
P13
P14
P15
P16
R1
FLSH_CE_N
PE_WAKE_N
SMBD1
VSSA
VCC18
VCC18
VSS
VSSA
SMBCLK1
VSSA
RSVD_J14
RSVD_J15
XTAL1
VCC11
VSS
MDI_MINUS1_2
MDI_PLUS1_2
PETp0
VSSA
VCC11
VCC18
VSSA
K2
PE_CLKp
VSSA
R2
PERn0
K3
R3
JTDI
K4
VCC18
VCC18
VSS
VCC11
VCC11
RBIAS1p
VSSA
R4
LAN_PWR_GOOD
TEST_EN
SDP1_3
K5
R5
K6
R6
K7
VCC11
VSS
R7
FLBINTEX
LED1_1
K8
SRDSI_1_PLUS
VSSA
R8
K9
VCC11
VCC18
VSSA
R9
FLSH_SO
FLSH_SCK
SMBALRT_N/PCI_PWR_GOOD
SMBD0
K10
K11
K12
K13
K14
K15
K16
N2
PERp1
VSSA
R10
R11
R12
R13
R14
R15
R16
N3
VCC11
VSSA
N4
VCC11
VCC11
VSS
N5
IEEE_TEST1p
MDI_MINUS1_0
MDI_MINUS1_1
VSSA
VSSA
N6
SRDSO_1_PLUS
VSSA
N7
VCC33
VSS
N8
39
82571/82572 Gigabit Ethernet Controller—Datasheet
Table 37.
82571 Signal Names in Pin Order
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
T1
T2
T3
T4
T5
T6
VSSA
PERp0
T7
T8
NC_T7
LED1_2
FLSH_SI
VSS
T13
T14
T15
T16
IEEE_TEST1n
MDI_PLUS1_0
MDI_PLUS1_1
VSSA
DEV_OFF_N
VSS
T9
T10
T11
T12
VCC33
VCC33
PE_RST_N
SMBCLK0
Table 38.
82572 Reserved and No Connect Signals
Note:
These pins are reserved by Intel and may have factory test functions. For normal
operation, do not connect any circuitry to these pins (allow them to “float”). Some
configurations may require pull-up or pull-down resistors on these pins. Please refer to
the 82571EB/82572EI design guide for more information.
Signal
Pin
RSVD_A3
RSVD_ A6
DEVICE_DIS_N
RSVD_B3
A3
A6
A7
B3
B5
C3
C5
C7
H1
J1
RSVD_ B5
RSVD_ C3
RSVD_ C5
RSVD_ C7
RSVD_H1
RSVD_J1
RSVD_J14
RSVD_J15
SMBD1
J14
J15
P12
P13
R4
T7
SMBCLK1
LAN_PWR_GOOD
NC_T7
40
Datasheet—82571/82572 Gigabit Ethernet Controller
Table 39.
82572 Signal Names in Pin Order
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
A2
VSSA
PETn3
C9
C10
C11
C12
C13
C14
C15
C16
D1
SDP0_2
LED0_3
LED0_1
EE_DI
F1
F2
PERp2
VSSA
A3
RSVD_A3
VCC33
F3
VSSA
A4
F4
VSSA
A5
VSS
EE_CS_N
VSSA
F5
VSS
A6
RSVD_A6
DEVICE_DIS_N
SDP0_3
F6
VSS
A7
MDI_MINUS0_2
MDI_PLUS0_2
VSSA
F7
VCC11
VSS
A8
F8
A9
SDP0_1
F9
VCC11
VCC18
VSSA
A10
A11
A12
A13
A14
A15
A16
B1
VCC33
D2
PETn2
F10
F11
F12
F13
F14
F15
F16
G1
VSS
D3
VSSA
EE_DO
D4
THERM_Dp
THERM_Dn
VSS
VCC11
VCC11
VSSA
IEEE_TEST0n
MDI_PLUS0_0
MDI_PLUS0_1
VSSA
D5
D6
D7
VCC33
SRDSO_0_MINUS
SRDSI_0_MINUS
VSSA
D8
VSS
PERn3
D9
VCC33
B2
PETp3
D10
D11
D12
D13
D14
D15
D16
E1
VSS
G2
PE_RCOMPn
VSSA
B3
RSVD_B3
SRDSA_SIG_DET
RSVD_B5
RSVD_B6
LAN0_DIS_N
RSVD_B8
SDP0_0
VSSA
G3
B4
VSSA
G4
VSSA
B5
VSSA
G5
VSSA
B6
RBIAS0n
MDI_MINUS0_3
MDI_PLUS0_3
PERn2
G6
VSS
B7
G7
VCC11
VSS
B8
G8
B9
G9
VCC11
VCC18
VSSA
B10
B11
B12
B13
B14
B15
B16
C1
LED0_2
E2
PETp2
G10
G11
G12
G13
G14
G15
G16
H1
LED0_0
E3
VSSA
EE_SK
E4
VSSA
VCC11
VSSA
IEEE_TEST0p
MDI_MINUS0_0
MDI_MINUS0_1
VSSA
E5
VSS
E6
VSS
VSSA
E7
VCC11
SRDSO_0_PLUS
VSSA
E8
VSS
PERp3
E9
VCC11
RSVD_H1
PE_RCOMPp
VSSA
C2
VSSA
E10
E11
E12
E13
E14
E15
E16
VCC18
H2
C3
RSVD_C3
RSVD_C4
RSVD_C5
RSVD_C6
RSVD_C7
AUX_PWR
VSSA
H3
C4
VCC11
H4
VCC18
VCC18
VSS
C5
VCC11
H5
C6
RBIAS0p
VSSA
H6
C7
H7
VCC11
VSS
C8
SRDSI_0_PLUS
H8
41
82571/82572 Gigabit Ethernet Controller—Datasheet
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
H9
H10
H11
H12
H13
H14
H15
H16
J1
VCC11
VCC18
VSSA
L1
L2
PETn1
VSSA
N9
N10
N11
N12
N13
N14
N15
N16
P1
VCC33
VSS
L3
VSSA
VSSA
VSSA
L4
VSSA
VSSA
VSSA
L5
VSSA
VSSA
SRDS_RCOMPn
SRDS_RCOMPp
XTAL2
L6
VSS
RSVD_N14
RSVD_N15
RSVD_N16
PETn0
L7
VCC11
VSS
L8
RSVD_J1
PE_CLKn
VSSA
L9
VCC11
VCC18
VSSA
J2
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
N1
P2
VSSA
J3
P3
JTMS
J4
VCC11
VCC11
VSS
VCC11
VCC11
VSSA
P4
JTCK
J5
P5
JTDO
J6
P6
RSVD_P6
FLBSD
J7
VCC11
VSS
RSVD_L15
RSVD_L16
PETp1
PERn1
VSSA
P7
J8
P8
RSVD_P8
RSVD_P9
FLSH_CE_N
PE_WAKE_N
SMBD1
J9
VCC11
VCC18
VSSA
P9
J10
J11
J12
J13
J14
J15
J16
K1
P10
P11
P12
P13
P14
P15
P16
R1
VSSA
VCC18
VCC18
VSS
VSSA
SMBCLK1
VSSA
RSVD_J14
RSVD_J15
XTAL1
VCC11
VSS
RSVD_P15
RSVD_P16
PETp0
VSSA
VCC11
VCC18
VSSA
K2
PE_CLKp
VSSA
R2
PERn0
K3
R3
JTDI
K4
VCC18
VCC18
VSS
VCC11
VCC11
RSVD_M14
VSSA
R4
LAN_PWR_GOOD
TEST_EN
RSVD_R6
FLBINTEX
RSVD_R8
FLSH_SO
FLSH_SCK
PCI_PWR_GOOD
FLBMD
K5
R5
K6
R6
K7
VCC11
VSS
R7
K8
RSVD_M16
VSSA
R8
K9
VCC11
VCC18
VSSA
R9
K10
K11
K12
K13
K14
K15
K16
N2
PERp1
VSSA
R10
R11
R12
R13
R14
R15
R16
N3
VCC11
VSSA
N4
VCC11
VCC11
VSS
N5
RSVD_R13
RSVD_R14
RSVD_R15
VSSA
VSSA
N6
RSVD_K15
VSSA
N7
VCC33
VSS
N8
42
Datasheet—82571/82572 Gigabit Ethernet Controller
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
T1
T2
T3
T4
T5
T6
VSSA
PERp0
T7
T8
NC_T7
RSVD_T8
FLSH_SI
VSS
T13
T14
T15
T16
RSVD_T13
RSVD_T14
RSVD_T15
VSSA
DEV_OFF_N
VSS
T9
T10
T11
T12
VCC33
VCC33
PE_RST_N
FLBMCK
43
82571/82572 Gigabit Ethernet Controller—Datasheet
5.4
Visual Pin Assignments
A
B
C
D
E
F
G
H
MDI_
MDI_
SRDSI_0
_PLUS
SRDSI_0
16
15
14
VSSA
VSSA
VSSA
XTAL2
PLUS0_2
PLUS0_3
_MINUS
MDI_
MINUS0_1
MDI_
MINUS0_2
MDI_
MINUS0_3
SRDSO_0
_MINUS
SRDSO_0
_PLUS
SRDS_RCOMP
p
MDI_PLUS0_1
MDI_PLUS0_0
VSSA
MDI_MINUS0
_0
SRDS_RCOMP
n
VSSA
RBIAS0n
RBIAS0p
VSSA
VSSA
IEEE_TEST0n
EE_DO
IEEE_TEST0p
EE_SK
EE_CS_N
EE_DI
VSSA
VSSA
VSSA
VSS
VCC11
VCC11
VSSA
VCC11
VCC11
VSSA
VSSA
VCC11
VSSA
VSSA
VSSA
13
12
11
10
9
VSS
LED0_0
LED0_1
LED0_3
SDP0_2
VSSA
VCC33
LED0_2
VCC18
VCC11
VCC18
VCC11
VCC18
VCC11
VCC18
VCC11
SDP0_1
SDP0_0
VCC33
LAN1_DIS_N/
RSVD_B8
8
SDP0_3
DEVICE_DIS_N
RSVD_A6
AUX_PWR
RSVD_C7
VSS
VCC33
VSS
VSS
VCC11
VSS
VSS
VCC11
VSS
VSS
VCC11
VSS
VSS
VCC11
VSS
LAN0_DIS_N
7
6
SDP1_1/
RSVD_B6
SDP1_2/
RSVD_C6
THERM_
Dn
5
4
VSS
RSVD_B5
RSVD_C5
VSS
VSS
VSSA
VSSA
VCC18
VCC18
SRDSA_SIG_
DET
SRDSB_SIG_D
ET/RSVD_C4
THERM_
Dp
VCC33
VSSA
VSSA
RSVD_A3
PETn3
RSVD_B3
PETp3
RSVD_C3
VSSA
VSSA
PETn2
VSSA
VSSA
PETp2
PERn2
VSSA
VSSA
PERp2
VSSA
PE_RCOMPn
VSSA
VSSA
3
2
1
PE_RCOMPp
RSVD_H1
VSSA
PERn3
PERp3
Figure 10.
82571EB/82572EI Visual Pin Assignment pt.1 (Top View)
44
Datasheet—82571/82572 Gigabit Ethernet Controller
J
K
L
M
N
P
R
T
SRDSI_1_PL
US/
MDI_PLUS1_
3/
MDI_PLUS1
_2/
RSVD_P16
16
15
14
13
SRDSI_1_MIN
XTAL1
VSSA
VSSA
VSSA
US/RSVD_L16
RSVD_M16
RSVD_N16
SRDSO_1_
PLUS/
RSVD_K15
SRDSO_1_
MINUS/
RSVD_L15
MDI_MINUS
1_3/
RSVD_N15
MDI_MINUS
1_2
/RSVD_P15
MDI_MINUS
1_1/
RSVD_15
MDI_PLUS
1_1/
RSVD_T15
RSVD_J1
5
VSSA
MDI_MINUS
1_0/
RSVD_R14
MDI_PLUS
1_0/
RSVD_T14
RSVD_J1
4
RBIAS1p/
RSVD_M14
RBIAS1n/
RSVD_N14
VSSA
VSSA
VSSA
IEEE_TEST1
p/
RSVD_R13
IEEE_TEST
1n/
RSVD_T13
VSSA
VSSA
VSSA
VSSA
VCC11
VSSA
VCC11
VCC11
VSSA
VCC11
VCC11
VSSA
VSSA
VSSA
VSSA
SMBCLK1
SMBD1
SMBD0/
FLBMD
SMBCLK0/
FLBMCK
12
11
SMBALRT_N/
PCI_PWR_G
OOD
PE_WAKE_N
FLSH_CE_N
VCC33
VCC18
VCC11
VCC18
VCC11
VCC18
VCC11
VCC18
VCC11
VSS
FLSH_SCK
FLSH_SO
VSS
10
9
LED1_3/
RSVD_P9
VCC33
FLSH_SI
LED1_0/
RSVD_P8
LED1_1/
RSVD_R8
LED1_2/
RSVD_T8
8
VSS
VCC11
VSS
VSS
VCC11
VSS
VSS
VCC11
VSS
VSS
VCC11
VSS
VSS
VCC33
VSS
FLBSD
FLBINTEX
NC_T7
7
6
SDP1_0/
RSVD_P6
SDP1_3/
RSVD_R6
PE_RST_N
VCC11
VCC11
VCC18
VCC18
VSSA
VSSA
VCC18
VCC18
VCC11
VCC11
JTDO
JTCK
TEST_EN
RSVD
VCC33
VSS
5
4
3
DEV_OFF_
N
VSSA
VSSA
VSSA
VSSA
VSSA
JTMS
JTDI
PE_CLKn
RSVD_J1
PE_CLKp
VSSA
VSSA
PERn1
PETp1
PERp1
VSSA
VSSA
PERn0
PETp0
PERp0
VSSA
2
1
PETn1
PETn0
Figure 11.
82571EB/82572EI Visual Pin Assignment pt.2 (Top View)
45
82571/82572 Gigabit Ethernet Controller—Datasheet
46
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