LD80C32-24
更新时间:2024-09-18 14:57:44
品牌:INTEL
描述:Microcontroller, 8-Bit, 24MHz, CMOS, CDIP40, CERDIP-40
LD80C32-24 概述
Microcontroller, 8-Bit, 24MHz, CMOS, CDIP40, CERDIP-40 微控制器
LD80C32-24 规格参数
生命周期: | Obsolete | 零件包装代码: | DIP |
包装说明: | DIP, | 针数: | 40 |
Reach Compliance Code: | unknown | HTS代码: | 8542.31.00.01 |
风险等级: | 5.84 | 具有ADC: | NO |
其他特性: | BOOLEAN PROCESSOR | 地址总线宽度: | 16 |
位大小: | 8 | 最大时钟频率: | 24 MHz |
DAC 通道: | NO | DMA 通道: | NO |
外部数据总线宽度: | 8 | JESD-30 代码: | R-GDIP-T40 |
长度: | 52.325 mm | I/O 线路数量: | 32 |
端子数量: | 40 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | PWM 通道: | NO |
封装主体材料: | CERAMIC, GLASS-SEALED | 封装代码: | DIP |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
认证状态: | Not Qualified | 座面最大高度: | 5.72 mm |
速度: | 24 MHz | 最大供电电压: | 6 V |
最小供电电压: | 4 V | 标称供电电压: | 5 V |
表面贴装: | NO | 技术: | CMOS |
温度等级: | INDUSTRIAL | 端子形式: | THROUGH-HOLE |
端子节距: | 2.54 mm | 端子位置: | DUAL |
宽度: | 15.24 mm | uPs/uCs/外围集成电路类型: | MICROCONTROLLER |
Base Number Matches: | 1 |
LD80C32-24 数据手册
通过下载LD80C32-24数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载8XC52/54/58
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial/Express
87C52/80C52/80C32/87C54/80C54/87C58/80C58
*See Table 1 for Proliferation Options
Y
Y
High Performance CHMOS EPROM/
ROM/CPU
6 Interrupt Sources
Y
Y
Programmable Serial Channel with:
Ð Framing Error Detection
Ð Automatic Address Recognition
Y
Y
Y
Y
Y
Y
Y
Y
12/24/33 MHz Operations
Three 16-Bit Timer/Counters
Programmable Clock Out
TTL and CMOS Compatible Logic
Levels
Up/Down Timer/Counter
Y
Y
Y
64K External Program Memory Space
64K External Data Memory Space
Three Level Program Lock System
8K/16K/32K On-Chip Program Memory
256 Bytes of On-Chip Data RAM
MCS 51 Microcontroller Compatible
É
Instruction Set
Improved Quick Pulse Programming
Algorithm
Y
Power Saving Idle and Power Down
Modes
Y
Y
Boolean Processor
Y
Y
Y
ONCE (On-Circuit Emulation) Mode
Four-Level Interrupt Priority
32 Programmable I/O Lines
Extended Temperature Range Except
b
a
for 33 MHz Offering ( 40 C to 85 C)
§
§
MEMORY ORGANIZATION
ROM
EPROM
Version
ROMless
Version
ROM/EPROM
Bytes
RAM
Device
Bytes
80C52
80C54
80C58
87C52
87C54
87C58
80C32
80C32
80C32
8K
16K
32K
256
256
256
These devices can address up to 64 Kbytes of external program/data memory.
The Intel 8XC52/8XC54/8XC58 is a single-chip control-oriented microcontroller which is fabricated on Intel’s
reliable CHMOS III-E technology. Being a member of the MCS 51 family of controllers, the 8XC52/8XC54/
8XC58 uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with
the existing MCS 51 family of products. The 8XC52/8XC54/8XC58 is an enhanced version of the
87C51/80C51BH/80C31BH. The added features make it an even more powerful microcontroller for applica-
tions that require clock output, and up/down counting capabilities such as motor control. It also has a more
versatile serial channel that facilitates multi-processor communications.
Throughout this document 8XC5X will refer to the 8XC52, 80C32, 8XC54 and 8XC58 unless information
applies to a specific device.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1996
March 1996
Order Number: 272336-004
8XC52/54/58
Table 1. Proliferations Options
NOTES:
*1 3.5 MHz to 12 MHz; 5V 20%
*1
Standard
-1
X
X
X
X
X
X
X
-2
X
X
X
X
X
X
X
-24
X
-33
X
g
g
-1 3.5 MHz to 16 MHz; 5V 20%
80C32
80C52
87C52
80C54
87C54
80C58
87C58
X
X
X
X
X
X
X
g
-2 0.5 MHz to 12 MHz; 5V 20%
g
-24 3.5 MHz to 24 MHz; 5V 20%
X
X
g
-33 3.5 MHz to 33 MHz; 5V 10%
X
X
X
X
X
X
X
X
X
X
272336–1
Figure 1. 8XC5X Block Diagram
2
8XC52/54/58
PROCESS INFORMATION
PACKAGES
Part
Prefix
Package Type
This device is manufactured on P629.0, a CHMOS
III-E process. Additional process and reliability infor-
mation is available in Intel’s Components Quality
and Reliability Handbook, Order No. 210997.
8XC5X
87C5X
8XC5X
8XC5X
P
D
N
S
40-Pin Plastic DIP (OTP)
40-Pin CERDIP (EPROM)
44-Pin PLCC (OTP)
44-Pin QFP (OTP)
272336–3
PLCC
272336–2
DIP
272336–4
*Do not connect reserved pins.
QFP
Figure 2. Pin Connections
3
8XC52/54/58
pins that are externally pulled low will source current
(I , on the data sheet) because of the internal pull-
PIN DESCRIPTIONS
IL
ups.
V
V
V
: Supply voltage.
CC
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
: Circuit ground.
SS
: Secondary ground (not on DIP). Provided to
SS1
@
addresses (MOVX DPTR). In this application it
uses strong internal pullups when emitting 1’s. Dur-
ing accesses to external Data Memory that use 8-bit
reduce ground bounce and improve power supply
by-passing.
@
addresses (MOVX Ri), Port 2 emits the contents of
the P2 Special Function Register.
NOTE:
This pin is not a substitute for the V pin (pin 22).
SS
(Connection not necessary for proper operation.)
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verifica-
tion.
Port 0: Port 0 is an 8-bit, open drain, bidirectional
I/O port. As an output port each pin can sink several
LS TTL inputs. Port 0 pins that have 1’s written to
them float, and in that state can be used as high-im-
pedance inputs.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong inter-
nal pullups when emitting 1’s, and can source and
sink several LS TTL inputs.
(I , on the data sheet) because of the pullups.
IL
Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are re-
quired during program verification.
Port Pin
Alternate Function
RXD (serial input port)
TXD (serial output port)
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
(I , on the data sheet) because of the internal pull-
IL
ups.
In addition, Port 1 serves the functions of the follow-
ing special features of the 8XC5X:
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the de-
vice. The port pins will be driven to their reset condi-
tion when a minimum V voltage is applied whether
IHI
the oscillator is running or not. An internal pulldown
resistor permits a power-on reset with only a capaci-
Port Pin
Alternate Function
P1.0
T2 (External Count Input to Timer/
Counter 2), Clock-Out
tor connected to V
.
CC
P1.1
T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to ex-
ternal memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C5X.
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
In normal operation ALE is emitted at a constant
rate of (/6 the oscillator frequency, and may be used
for external timing or clocking purposes. Note, how-
ever, that one ALE pulse is skipped during each ac-
cess to external Data Memory.
4
8XC52/54/58
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With this bit set, the pin is
weakly pulled high. However, the ALE disable fea-
ture will be suspended during a MOVX or MOVC in-
struction, idle mode, power down mode and ICE
mode. The ALE disable feature will be terminated by
reset. When the ALE disable feature is suspended or
terminated, the ALE pin will no longer be pulled up
weakly. Setting the ALE-disable bit has no affect if
the microcontroller is in external execution mode.
272336–5
e
g
30 pF 10 pF for Crystals
C1, C2
For Ceramic Resonators, contact resonator manufac-
turer.
Figure 3. Oscillator Connections
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the in-
put to the internal clocking circuitry is through a di-
vide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the 8XC5X is executing code from external
Program Memory, PSEN is activated twice each
machine cycle, except that two PSEN activations
are skipped during each access to external Data
Memory.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the V
IL
and V specifications the capacitance will not ex-
EA/V
: External Access enable. EA must be
PP
IH
ceed 20 pF.
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFFH. Note, however, that if any of the
Lock bits are programmed, EA will be internally
latched on reset.
EA should be strapped to V
executions.
for internal program
CC
This pin also receives the programming supply volt-
age (V ) during EPROM programming.
PP
272336–6
XTAL1: Input to the inverting oscillator amplifier.
Figure 4. External Clock Drive Configuration
XTAL2: Output from the inverting oscillator amplifi-
er.
IDLE MODE
The user’s software can invoke the Idle Mode. When
the microcontroller is in this mode, power consump-
tion is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respec-
tively, of a inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155, ‘‘Oscillators for Microcontrol-
lers’’, Order No. 230659.
5
8XC52/54/58
Table 2. Status of the External Pins during Idle and Power Down
Program
Mode
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Memory
Internal
External
Internal
External
Idle
1
1
0
0
1
1
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Idle
Power Down
Power Down
Data
When the idle mode is terminated by a hardware
reset, the device normally resumes program exe-
cution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to inter-
nal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
#
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated.
On the 8XC5X either a hardware reset or an external
interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the on-
chip RAM. An external interrupt allows both the
SFRs and on-chip RAM to retain their values.
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the 8XC5X
without the 8XC5X having to be removed from the
circuit. The ONCE Mode is invoked by:
To properly terminate Power Down, the reset or ex-
ternal interrupt should not be executed before V is
restored to its normal operating level, and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
CC
1) Pull ALE low while the device is in reset and
PSEN is high;
With an external interrupt, INT0 and INT1 must be
enabled and configured as level-sensitive. Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains ac-
tive. While the 8XC5X is in this mode, an emulator or
test CPU can be used to drive the circuit. Normal
operation is restored when a normal reset is applied.
DESIGN CONSIDERATION
The window on the D87C5X must be covered by
#
an opaque label. Otherwise, the DC and AC char-
acteristics may not be met, and the device may
be functionally impaired.
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, (Order No. 270645) and Application Note AP-252 (Embedded Applications Handbook, Order No.
270648), ‘‘Designing with the 80C51BH.’’
6
8XC52/54/58
The optional burn-in is dynamic for a minimum time
e
following guidelines in MIL-STD-883, Method 1015.
8XC5X EXPRESS
g
6.9V 0.25V,
of 168 hours at 125 C with V
§
CC
The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS 51 family
of microcontrollers. These EXPRESS products are
designed to meet the needs of those applications
whose operating requirements exceed commercial
standards.
Package types and EXPRESS versions are identified
by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 3.
For the extended temperature range option, this
data sheet specifies the parameters which deviate
from their commercial temperature range limits.
The EXPRESS program includes the commercial
standard temperature range with burn-in and an ex-
tended temperature range with or without burn-in.
NOTE:
Intel offers Express Temperature specifica-
tions for all 8XC5X speed options except for
33 MHz.
With the commercial standard temperature range,
operational characteristics are guaranteed over the
a
tended temperature range option, operational char-
temperature range of 0 C to
70 C. With the ex-
§
§
b
acteristics are guaranteed over the range of 40 C
§
a
to 85 C.
§
Table 3. Prefix Identification
Package
Type
Temperature
Range
Prefix
Burn-In
P
Plastic
Cerdip
PLCC
QFP
Commercial
Commercial
Commercial
Commercial
Extended
Extended
Extended
Extended
Extended
Extended
Extended
Extended
No
No
D
N
No
S
No
TP
TD
TN
TS
LP
LD
LN
LS
Plastic
Cerdip
PLCC
QFP
No
No
No
No
Plastic
Cerdip
PLCC
QFP
Yes
Yes
Yes
Yes
NOTE:
Contact distributor or local sales office to match EXPRESS prefix with proper device.
EXAMPLES:
P80C52 indicates 80C52 in a plastic package and specified for commercial temperature range, without burn-in. TD80C52
indicates 80C52 in a Cerdip package and specified for extended temperature range, without burn-in.
7
8XC52/54/58
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
tions are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
b
a
Ambient Temperature Under Bias À 40 C to 85 C
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
§
b
a
§
§
Voltage on EA/V Pin to V ÀÀÀÀÀÀÀ0V to 13.0V
a
PP
SS
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
b a
ÀÀ 0.5V to 6.5V
Voltage on Any Other Pin to V
SS
I
Per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA
OL
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
T
A
Ambient Temperature Under Bias
Commercial
Express
a
a
0
70
85
C
§
§
b
40
C
V
CC
Supply Voltage
8XC5X-33
4.0
4.5
6.0
5.5
V
V
f
Oscillator Frequency
8XC5X
8XC5X-1
OSC
3.5
3.5
0.5
3.5
3.5
12
16
12
24
33
MHz
MHz
MHz
MHz
MHz
8XC5X-2
8XC5X-24
8XC5X-33
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated.
Typ
Symbol
Parameter
Min
Max
Unit
Test Conditions
(Note 4)
b
b
V
V
V
Input Low Voltage
0.5
0.2 V
0.1
0.3
V
V
V
IL
CC
CC
b
Input Low Voltage EA
0
0.2 V
IL1
IH
a
a
Input High Voltage
(Except XTAL1, RST)
0.2 V
0.9
V
CC
0.5
CC
a
V
V
Input High Voltage
(XTAL1, RST)
0.7 V
V
0.5
V
IH1
OL
CC
CC
e
e
e
e
e
e
Output Low Voltage (Note 5)
(Ports 1, 2 and 3)
0.3
V
V
V
V
V
V
V
V
V
I
I
I
I
I
I
I
I
I
100 mA (Note 1)
1.6 mA (Note 1)
3.5 mA (Note 1)
200 mA (Note 1)
3.2 mA (Note 1)
7.0 mA (Note 1)
OL
OL
OL
OL
OL
OL
OH
OH
OH
0.45
1.0
V
V
Output Low Voltage (Note 5)
(Port 0, ALE, PSEN)
0.3
OL1
OH
0.45
1.0
b
b
b
e b
e b
e b
Output High Voltage
(Ports 1, 2 and 3, ALE, PSEN)
V
CC
V
CC
V
CC
0.3
0.7
1.5
10 mA
30 mA
60 mA
8
8XC52/54/58
Test Conditions
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
All parameter values apply to all devices unless otherwise indicated.
Typ
Symbol
Parameter
Min
Max
Unit
(Note 4)
b
b
b
e b
e b
e b
V
OH1
Output High Voltage
(Port 0 in External Bus Mode)
V
V
V
0.3
0.7
1.5
V
V
V
I
I
I
200 mA
3.2 mA
7.0 mA
CC
CC
CC
OH
OH
OH
I
Logical 0 Input Current
(Ports 1, 2 and 3)
IL
b
g
e
e
50
10
mA
mA
V
V
0.45V
V or V
IL
IN
IN
I
I
Input leakage Current (Port 0)
LI
IH
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
Commercial
TL
b
b
e
650
750
mA
mA
V
2V
IN
Express
RRST
CIO
RST Pulldown Resistor
Pin Capacitance
40
225
KX
@
1 MHz, 25 C
10
pF
§
I
Power Supply Current:
Active Mode
(Note 3)
CC
at 12 MHz (Figure 5)
at 16 MHz
at 24 MHz
15
20
28
35
30
38
56
56
mA
mA
mA
mA
at 33 MHz (8XC5X-33)
Idle Mode
at 12 MHz (Figure 5)
at 16 MHz
at 24 MHz
5
6
7
7
5
5
7.5
9.5
13.5
15
mA
mA
mA
mA
mA
mA
at 33 MHz (8XC5X-33)
Power Down Mode
8XC5X-33
75
50
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V s of ALE and
OL
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Triggers, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the V
address lines are stabilizing.
3. See Figures 6–9 for test conditions. Minimum V
on ALE and PSEN to drop below the 0.9 V specification when the
CC
OH
for Power Down is 2V.
CC
4. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and 5V.
5. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
OL
Maximum I per 8-bit portÐ
10mA
OL
Port 0:
Ports 1, 2 and 3:
Maximum total I for all output pins:
26 mA
15 mA
71 mA
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater
OL OL
than the listed test conditions.
9
8XC52/54/58
272336–7
NOTE:
g
Max at 33 MHz is at 5V 10% V , while
Max at 24 MHz and below is at 5V 20% V
I
I
CC
CC
CC
g
CC
Figure 5. 8XC52/54/58 I vs Frequency
CC
272336–8
All other pins disconnected
e
e
TCLCH
TCHCL
5 ns
Figure 6. I Test Condition, Active Mode
CC
10
8XC52/54/58
272336–9
272336–10
All other pins disconnected
e
All other pins disconnected
e
TCLCH
TCHCL
5 ns
Figure 8. I Test Condition, Power Down Mode
CC
Figure 7. I Test Condition Idle Mode
CC
e
V
2.0V to 6.0V
CC
272336–11
e
e
5 ns
Figure 9. Clock Signal Waveform for I Tests in Active and Idle Modes. TCLCH
CC
TCHCL
11
8XC52/54/58
L: Logic level LOW, or ALE
P: PSEN
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first char-
acter is always a ‘T’ (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
A: Address
C: Clock
D: Input Data
For example,
H: Logic level HIGH
I: Instruction (program memory contents)
e
e
TAVLL
TLLPL
Time from Address Valid to ALE Low
Time from ALE Low to PSEN Low
AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
e
e
80 pF)
PSEN
100 pF, Load Capacitance for All Other Outputs
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated. In this table, 8XC5X refers to 8XC5X,
8XC5X-1, and 8XC5X-2.
Oscillator
Symbol
Parameter
Units
12 MHz
24 MHz
33 MHz
Variable
Min Max Min Max Min Max
Min
Max
1/TCLCL Oscillator Frequency
8XC5X
3.5
3.5
0.5
3.5
3.5
12
16
12
24
33
MHz
MHz
MHz
MHz
MHz
8XC5X-1
8XC5X-2
8XC5X-24
8XC5X-33
b
TLHLL
TAVLL
ALE Pulse Width
127
43
43
12
12
21
2 TCLCL
40
ns
Address Valid to
ALE Low
8XC5X
b
TCLCL 40
ns
ns
ns
b
8XC5X-24
8XC5X-33
TCLCL 30
TCLCL
b
25
5
5
TLLAX
TLLIV
Address Hold After
ALE Low
b
8XC5X/-24
8XC5X-33
53
TCLCL 30
25
ns
ns
b
TCLCL
ALE Low to Valid
Instruction In
8XC5X
b
100 ns
234
4 TCLCL
4 TCLCL
4 TCLCL
b
b
8XC5X-24
8XC5X-33
91
75
65
ns
ns
56
12
8XC52/54/58
EXTERNAL MEMORY CHARACTERISTICS (Continued)
All parameter values apply to all devices unless otherwise indicated.
Oscillator
Symbol
Parameter
Units
12 MHz
24 MHz
33 MHz
Variable
Min Max Min Max Min Max
Min
Max
TLLPL
ALE Low to
PSEN Low
b
b
8XC5X/-24 53
8XC5X-33
12
80
TCLCL 30
25
ns
ns
5
TCLCL
b
TPLPH
TPLIV
PSEN Pulse
Width
205
46
3 TCLCL
45
ns
PSEN Low to
Valid
Instruction In
8XC5X
b
b
145
3 TCLCL 105
3 TCLCL
ns
ns
ns
8XC5X-24
8XC5X-33
35
90
b
3 TCLCL 55
35
TPXIX
TPXIZ
Input
0
0
0
0
ns
Instruction
Hold After
PSEN
Input
Instruction
Float After
PSEN
b
8XC5X
8XC5X-24
8XC5X-33
59
TCLCL 25
ns
ns
ns
b
21
TCLCL 20
b
TCLCL 25
5
TAVIV
TPLAZ
Address to
Valid
Instruction In
8XC5X/-24
8XC5X-33
b
b
312
10
103
10
5 TCLCL 105
80
ns
ns
71
10
5 TCLCL
PSEN Low to
Address
Float
10
ns
b
6 TCLCL 100
TRLRH RD Pulse
Width
400
400
150
150
82
82
ns
ns
b
6 TCLCL 100
TWLWH WR Pulse
Width
13
8XC52/54/58
EXTERNAL MEMORY CHARACTERISTICS (Continued)
All parameter values apply to all devices unless otherwise indicated.
Oscillator
Symbol
Parameter
Units
12 MHz
24 MHz
33 MHz
Variable
Min Max Min Max Min Max
Min
Max
TRLDV RD Low to Valid
Data In
8XC5X
b
b
b
252
113
61
5 TCLCL 165
ns
ns
ns
8XC5X-24
8XC5X-33
5 TCLCL
5 TCLCL
95
90
TRHDX Data Hold After
RD
0
0
0
0
ns
TRHDZ Data Float After
RD
b
b
8XC5X/-24
8XC5X-33
107
517
585
23
2 TCLCL 60
25
ns
ns
35
2 TCLCL
TLLDV ALE Low to
Valid Data In
8XC5X
b
b
8 TCLCL
8 TCLCL
150
90
ns
ns
8XC5X-24/33
243
285
150
TAVDV Address to
Valid Data In
8XC5X
b
9 TCLCL 165
9 TCLCL
ns
ns
b
8XC5X-24/33
180
90
b
a
TLLWL ALE Low to RD 200 300 75 175 41 140 3 TCLCL
or WR Low
50 3 TCLCL
50
ns
TAVWL Address to RD
or WR Low
8XC5X
b
b
203
4 TCLCL
4 TCLCL
130
90
ns
ns
ns
8XC5X-24
8XC5X-33
77
b
4 TCLCL 75
46
14
8XC52/54/58
EXTERNAL MEMORY CHARACTERISTICS (Continued)
All parameter values apply to all devices unless otherwise indicated.
Oscillator
Symbol
Parameter
Units
12 MHz
24 MHz
33 MHz
Variable
Min Max Min Max Min Max
Min
Max
TQVWX Data Valid to
WR Transition
8XC5X
b
b
33
TCLCL 50
TCLCL 30
ns
ns
8XC5X-24/33
12
7
0
TWHQX Data Hold After
WR
b
8XC5X
8XC5X-24
8XC5X-33
33
TCLCL
50
TCLCL 35
ns
ns
ns
b
b
3
TCLCL
27
TQVWH Data Valid to
WR High
8XC5X
b
b
70
433
7 TCLCL
7 TCLCL
150
ns
ns
8XC5X-24/33
222
142
TRLAZ
RD Low to
Address Float
0
0
0
0
ns
TWHLH RD or WR High
to ALE High
8XC5X
b
b
a
a
a
43 123
TCLCL
TCLCL 30
40
TCLCL
TCLCL
TCLCL
40
30
25
ns
ns
ns
8XC5X-24
8XC5X-33
12
71
b
TCLCL 25
5
55
15
8XC52/54/58
EXTERNAL PROGRAM MEMORY READ CYCLE
272336–25
EXTERNAL DATA MEMORY READ CYCLE
272336–26
EXTERNAL DATA MEMORY WRITE CYCLE
272336–27
16
8XC52/54/58
SERIAL PORT TIMING - SHIFT REGISTER MODE
e
Test Conditions: Over Operating Conditions; Load Capacitance 80 pF
Oscillator
Symbol
Parameter
Units
12 MHz
24 MHz
33 MHz
Variable
Min Max Min Max Min Max
Min
Max
TXLXL
Serial Port
Clock
Cycle Time
1
0.50
284
0.36
167
12 TCLCL
ms
b
10 TCLCL 133
TQVXH Output Data
Setup to Clock
Rising Edge
700
ns
TXHQX Output Data
Hold after Clock
Rising Edge
b
8XC5X
50
0
2 TCLCL 117
ns
ns
b
2 TCLCL 50
8XC5X-24/33
34
10
TXHDX Input Data Hold
After Clock
Rising Edge
0
0
0
ns
b
10 TCLCL 133
TXHDV Clock Rising
Edge to Input
Data Valid
700
283
167
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
272336–15
17
8XC52/54/58
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
8XC5X
8XC5X-1
MHz
MHz
MHz
MHz
MHz
MHz
3.5
3.5
0.5
3.5
3.5
12
16
12
24
33
8XC5X-2
8XC5X-24
8XC5X-33
TCHCX
TCLCX
TCLCH
High Time
8XC5X-24/33
20
ns
ns
0.35 T
0.65 T
OSC
OSC
OSC
Low Time
8XC5X-24/33
20
ns
ns
0.35 T
0.65 T
OSC
Rise Time
8XC5X-24
8XC5X-33
20
10
5
ns
ns
ns
TCHCL
Fall Time
8XC5X-24
8XC5X-33
20
10
5
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
272336–16
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
272336–20
272336–19
For timing purposes
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded V /V level occurs.
a port pin is no longer floating when a
b
and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V
AC Inputs during testing are driven at V
0.5V for a Logic ‘‘1’’
CC
IH
OH OL
min for a Logic ‘‘1’’ and V max for a Logic ‘‘0’’.
IL
e
g
20 mA.
I
/I
OL OH
18
8XC52/54/58
PROGRAMMING THE EPROM
DEFINITION OF TERMS
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is ap-
plied to data lines. Control and program signals must
be held at the levels indicated in Table 4. Normally
ADDRESS LINES: P1.0–P1.7, P2.0–P2.5 respec-
tively for A0–A13.
DATA LINES: P0.0–P0.7 for D0–D7.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
EA/V is held at logic high until just before ALE/
PP
PROG is to be pulsed. The EA/V is raised to V
,
PP
is re-
PP
ALE/PROG is pulsed low and then EA/V
PROGRAM SIGNALS: ALE/PROG, EA/V
PP
PP
turned to a high (also refer to timing diagrams).
NOTES:
Exceeding the V maximum for any amount of
#
PP
time could damage the device permanently. The
V source must be well regulated and free of
PP
glitches.
Table 4. EPROM Programming Modes
ALE/
EA/
Mode
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
PROG
V
PP
Program Code Data
Verify Code Data
H
H
H
L
L
L
ß
H
12.75V
H
L
L
L
H
L
H
L
H
H
L
H
H
H
Program Encryption
Array Address 0–3FH
ß
12.75V
H
H
Program Lock
Bits
Bit 1
Bit 2
Bit 3
H
H
H
H
L
L
L
L
ß
ß
ß
H
12.75V
12.75V
12.75V
H
H
H
H
L
H
H
L
H
H
H
L
H
L
H
L
L
L
H
L
Read Signature Byte
L
19
8XC52/54/58
272336–21
*See Table 4 for proper input on these pins
Figure 10. Programming the EPROM
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
PROGRAMMING ALGORITHM
Refer to Table 4 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C5X the following sequence must be exercised.
PROGRAM VERIFY
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
Program verify may be done after each byte or block
of bytes is programmed. In either case a complete
verify of the programmed array will ensure reliable
programming of the 87C5X.
3. Activate the correct combination of control sig-
nals.
g
to 12.75V 0.25V.
4. Raise EA/V from V
PP
CC
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their fea-
tures are enabled.
5. Pulse ALE/PROG 5 times for the EPROM ar-
ray, and 25 times for the encryption table and
the lock bits.
272336–22
Figure 11. Programming Signal’s Waveforms
20
8XC52/54/58
Erasing the EPROM also erases the encryption ar-
ray and the program lock bits, returning the part to
full functionality.
ROM and EPROM Lock System
The program lock system, when programmed, pro-
tects the onboard program against software piracy.
The 80C5X has a one-level program lock system
and a 64-byte encryption table. See line 2 of Table
5. If program protection is desired. the user submits
the encryption table with their code. and both the
lock-bit and encryption array are programmed by the
factory. The encryption array is not available without
the lock bit. For the lock bit to be programmed, the
user must submit an encryption table.
Reading the Signature Bytes
The 8XC5X has 3 signature bytes in locations 30H,
31H, and 60H. To read these bytes follow the proce-
dure for EPROM verify, but activate the control lines
provided in Table 4 for Read Signature Byte.
Location
30H
Device
All
Contents
89H
The 87C5X has a 3-level program lock system and a
64-byte encryption array. Since this is an EPROM
device, all locations are user-programmable. See
Table 5.
31H
All
58H
60H
80C52
87C52
80C54
87C54
80C58
87C58
12H
52H
14H
Encryption Array
54H
Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1’s). Every
time that a byte is addressed during a verify, 6 ad-
dress lines are used to select a byte of the Encryp-
tion Array. This byte is then exclusive-NOR’ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the un-
programmed state (all 1’s), will return the code in its
original, unmodified form. For programming the En-
cryption Array, refer to Table 4 (Programming the
EPROM).
18H
58H
Erasure Characteristics
(Windowed Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in room-
level fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque la-
bel be placed over the window.
When using the encryption array, one important fac-
tor needs to be considered. If a code byte has the
value 0FFH, verifying the byte will produce the en-
l
cryption byte value. If a large block ( 64 bytes) of
code is left unprogrammed, a verification routine will
display the contents of the encryption array. For this
reason all unused code bytes should be pro-
grammed with some value other than 0FFH, and not
all of them the same value. This will ensure maxi-
mum program protection.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
2
ed dose of at least 15 W-sec/cm . Exposing the
2
EPROM to an ultraviolet lamp of 12,000 mW/cm
Program Lock Bits
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
The 87C5X has 3 programmable lock bits that when
programmed according to Table 5 will provide differ-
ent levels of protection for the on-chip code and
data.
Erasure leaves all the EPROM Cells in a 1’s state.
21
8XC52/54/58
Table 5. Program Lock Bits and the Features
Protection Type
Program Lock Bits
LB1
LB2
LB3
1
2
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
P
U
U
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is disabled.
3
4
P
P
P
P
U
P
Same as 2, also verify is disabled.
Same as 3, also external execution is disabled.
NOTE:
Any other combination of the lock bits is not defined.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
e
e
e
0V)
SS
g
5V 20%; V
(T
A
21 C to 27 C; V
§
Symbol
§
CC
Parameter
Min
Max
13.0
75
Units
V
V
Programming Supply Voltage
Programming Supply Current
Oscillator Frequency
12.5
PP
I
mA
PP
1/TCLCL
TAVGL
TGHAX
TDVGL
TGHDX
TEHSH
TSHGL
TGHSL
TGLGH
TAVQV
TELQV
TEHQZ
TGHGL
4
6
MHz
Address Setup to PROG Low
Address Hold after PROG
Data Setup to PROG Low
Data Hold after PROG
48TCLCL
48TCLCL
48TCLCL
48TCLCL
48TCLCL
10
(Enable) High to V
PP
V
V
Setup to PROG Low
ms
ms
ms
PP
PP
Hold after PROG
10
PROG Width
90
110
Address to Data Valid
ENABLE Low to Data Valid
Data Float after ENABLE
PROG High to PROG Low
48TCLCL
48TCLCL
48TCLCL
0
10
ms
22
8XC52/54/58
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
272336–23
*5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
The following differences exist between this data-
sheet (272336-003) and the previous version
(272336-002):
Thermal Impedance
All thermal impedance data is approximate for static
air conditions at 1W of power dissipation. Values will
change depending on operating conditions and ap-
plications. See the Intel Packaging Handbook (Order
Number 240800) for a description of Intel’s thermal
impedance test methodology.
1. Removed 8XC5X-3 and 8XC5X-20 from the data
sheet.
2. Included 8XC5X-24 and 8XC5X-33 devices.
3. Removed the statement ‘‘The 80C32 standard, -1
and -2, and 80C52 standard, -1 and -2, do not
have the . . . ’’ from the section DESIGN CONSID-
ERATION.
Package
i
i
Device
JA
JC
P
D
N
S
45 C/W
§
16 C/W
§
All
All
All
52
54
58
45 C/W
§
15 C/W
§
The following differences exist between this data-
sheet (272336-002) and the previous version
(272336-001):
46 C/W
§
16 C/W
§
87 C/W
§
18 C/W
§
96 C/W
§
24 C/W
§
1. Removed 8XC5X-L from the data sheet.
90 C/W
§
22 C/W
§
2. Included features not available in 80C32-Stan-
dard, -1 and -2, and 80C52-Standard, -1 and -2
devices.
DATA SHEET REVISION HISTORY
This 8XC5X datasheet (272336-001) replaces the
following datasheets:
Data sheets are changed as new device information
becomes available. Verify with your local Intel sales
office that you have the latest version before finaliz-
ing a design or ordering devices.
87C52/80C52/80C32
270757-003
270868-002
272272-001
270816-004
270901-001
270941-003
270900-003
270902-001
272029-002
87C52/80C52/80C32 EXPRESS
87C52-20/80C52-20/80C32-20
87C54/80C54
87C54/80C54 EXPRESS
87C54-20/-3 80C54-20/-3
87C54/80C58
87C58/80C58 EXPRESS
87C58-20/-3 80C58-20/-3
23
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