LE82US15EC/SLGQA [INTEL]
Micro Peripheral IC, CMOS, PBGA1295;
| 型号： | LE82US15EC/SLGQA |
| 厂家： | 
INTEL |
| 描述： | Micro Peripheral IC, CMOS, PBGA1295 |
| 文件： | 总75页 (文件大小：586K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
®
Intel System Controller Hub (Intel
SCH)
Datasheet Addendum for US15WP and US15WPT
Febuary 2009
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Copyright © 2009, Intel Corporation. All Rights Reserved.
2
Datasheet Addendum
Document number: 321422-001
Contents
1
Introduction..............................................................................................................6
1.1
1.2
1.3
Terminology .......................................................................................................7
Reference Documents..........................................................................................9
Overview ......................................................................................................... 10
2
Signal Description ................................................................................................... 15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Host Interface Signals........................................................................................ 16
System Memory Signals..................................................................................... 20
Integrated Display Interfaces.............................................................................. 21
Universal Serial Bus (USB) Signals....................................................................... 24
PCI Express* Signals ......................................................................................... 25
Secure Digital I/O (SDIO)/MultiMedia Card (MMC) Signals ...................................... 25
Parallel ATA (PATA) Signals ................................................................................ 26
Intel® High Definition Audio (Intel® HD Audio) Interface ........................................ 27
LPC Interface.................................................................................................... 28
2.10 SMBus Interface................................................................................................ 29
2.11 Power Management Interface.............................................................................. 30
2.12 Real Time Clock Interface................................................................................... 31
2.13 JTAG Interface.................................................................................................. 32
2.14 Miscellaneous Signals and Clocks......................................................................... 32
2.15 General Purpose I/O.......................................................................................... 33
2.16 Power and Ground Signals.................................................................................. 34
2.17 Functional Straps .............................................................................................. 35
3
4
Pin States................................................................................................................ 36
3.1
3.2
Pin Reset States................................................................................................ 36
Integrated Termination Resistors......................................................................... 42
Absolute Maximums and Operating Conditions ........................................................ 44
4.1
4.2
4.3
Absolute Maximums........................................................................................... 44
Thermal Characteristics...................................................................................... 45
General Operating Conditions.............................................................................. 46
5
DC Characteristics ................................................................................................... 47
5.1
5.2
5.3
Signal Groups................................................................................................... 47
Power and Current Characteristics ....................................................................... 48
General DC Characteristics ................................................................................. 50
6
7
Storage Conditions Specifications............................................................................ 55
Ballout and Package Information............................................................................. 56
7.1
7.2
7.3
Package Diagrams............................................................................................. 57
Reverse Ballout Definition and Signal Location....................................................... 59
Pin List by Ball Name ......................................................................................... 64
Figures
1
2
3
4
5
6
System Block Diagram Example...................................................................................7
Signal Information Diagram....................................................................................... 15
Intel® SCH (Side View)............................................................................................. 57
Intel® SCH Package (Solder Resist Opening) ............................................................... 57
Intel® SCH (Bottom View)......................................................................................... 58
Intel® SCH (Top View).............................................................................................. 58
Datasheet Addendum
Document number: 321422-001
3
Tables
1
2
3
4
5
6
7
8
9
Terminology..............................................................................................................7
Reference documents .................................................................................................9
PCI Devices and Functions......................................................................................... 10
Intel® SCH Signal Description.................................................................................... 16
System Memory Signals............................................................................................ 20
LVDS Signals........................................................................................................... 21
Serial Digital Video Output (SDVO) Signals.................................................................. 22
Display Data Channel (DDC) and GMBUS Support......................................................... 23
Universal Serial Bus (USB) Signals ............................................................................. 24
10 PCI Express* Signals................................................................................................ 25
11 Secure Digital I/O (SDIO)/MultiMedia Card (MMC) Signals ............................................. 25
12 Parallel ATA (PATA) Signals ....................................................................................... 26
13 Intel® High Definition Audio (Intel® HD Audio) Interface.............................................. 27
14 LPC Interface .......................................................................................................... 28
15 SMBus Interface ...................................................................................................... 29
16 Power Management Interface .................................................................................... 30
17 Real Time Clock Interface.......................................................................................... 31
18 JTAG Interface......................................................................................................... 32
19 Miscellaneous Signals and Clocks ............................................................................... 32
20 General Purpose I/O................................................................................................. 33
21 Power and Ground Signals......................................................................................... 34
22 Functional Strap Definitions....................................................................................... 35
23 Reset State Definitions ............................................................................................. 36
24 Intel® SCH Reset State............................................................................................. 37
25 Intel® SCH Integrated Termination Resistors ............................................................... 42
26 Intel® SCH Absolute Maximum Ratings ....................................................................... 44
27 Intel® SCH Thermal Characteristics............................................................................ 45
28 Intel® SCH Maximum Power Consumption................................................................... 46
29 Intel® SCH Buffer Types ........................................................................................... 47
30 Intel® SCH Signal Group Definitions ........................................................................... 47
31 Thermal Design Power.............................................................................................. 48
32 DC Current Characteristics ........................................................................................ 49
33 Operating Condition Power Supply and Reference DC Characteristics............................... 50
34 Active Signal DC Characteristics................................................................................. 51
35 PLL Noise Rejection Specifications .............................................................................. 54
36 Intel® SCH Absolute Maximum Ratings ....................................................................... 55
Datasheet Addendum
Document number: 321422-001
4
Revision History
Revision
Number
Description
•Initial release for Large Package Intel SCH
Revision Date
®
-001
Febuary 2009
Datasheet Addendum
Document number: 321422-001
5
Introduction
1
Introduction
The Intel® System Controller Hub (Intel® SCH) chipset was designed to be used in
conjunction with the Intel® AtomTM Z5xx series processor. The chipset combines
functionality normally found in separate GMCH (integrated graphics, processor
interface, memory controller) and ICH (on-board and end-user I/O expansion)
components into a single component consuming less than 2.3 W of thermal design
power. The System Controller Hub provides functionality necessary for traditional
operating systems (such as Microsoft Windows XP*, Windows XPe*, Win CE* or Linux*)
as well as functionality normally associated with handheld devices (such as SDIO/MMC
and USB client). Figure 1 shows an example system block diagram. Section 1.3
provides an overview of the major features of the Intel® SCH.
This document is the datasheet addendum for the Intel® System Controller Hub (Intel®
SCH) for SKUs US15WP and US15WPT. These SKUs provide the same functionality
found in the smaller package SCH, but with a larger package that is easier to deal with.
The “P” extension to the part number denotes that the part has a larger package then
it’s small form factor counterpart, and the “T” extension to the part number denotes
that the part supports the Industrial Temperature range. These larger package SCH
SKUs were designed to be used in conjunction with the Intel® AtomTM Z5xxPx series
processors. This addendum and datasheet contain signal description, system memory
map, register descriptions, a description of the SCH interfaces and major functional
units, electrical characteristics, ballout definitions, and package characteristics.
Caution:
Warning:
The datasheet addendum provides supplemental information to the Intel® System
Controller Hub (Intel® SCH) Datasheet for the small form factor (SFF) package.
This document contains information on new products. The specifications are subject to
change without notice. Please refer to the Intel® System Controller Hub (SCH)
Specification Update for updates and verify with your local Intel Sales office that you
have the latest document before finalizing a design.
Datasheet Addendum
Document number: 321422-001
6
Introduction
Figure 1.
System Block Diagram Example
Processor
400/533 MHz
400/533 MHz
LVDS
SDVO
DDR2 SDRAM
Internal Display
External Display
Integrated
Graphics
and Video
System
Management
Controller
Intel® High
Definition Audio
Clock Generation
SMBus 1.0
USB
8 hosts ports, or
7 hosts + 1 client
Intel® SCH
PCI Express* x1
System Devices
GPIO
2 ports
3 ports
FWH
Legacy I/O
SDIO/MMC
P-ATA HDD
LPC Interface
1.1
Terminology
Table 1.
Terminology
Term
Description
Advanced Control Programmable Interface
ACPI
Advanced Digital Display 2. An interface specification that accepts serial DVO
inputs and translates them into different display outputs such as DVO, TV-
OUT, and LVDS.
ADD2
Core
The internal base logic in the system controller hub.
Full reset is when PWROK is deasserted and all system rails except VCCRTC
are powered down
Cold Reset
CRT
CT
Cathode Ray Tube
Commercial Temperature - 0 to 70°C
Dynamic Bus Inversion
DBI
DDR2
A second generation Double Data Rate SDRAM memory technology
Digital Video Interface. DVI is a specification that defines the connector and
interface for digital displays.
DVI
Datasheet Addendum
Document number: 321422-001
7
Introduction
Table 1.
Terminology
Term
Description
Enhanced Host Controller Interface. A controller interface that, on Intel® SCH,
supports up to eight USB 2.0 high-speed root ports, two of which are to be
used internally only.
EHCI
FSB
Front Side Bus. FSB is synonymous with host bus or processor bus
Firmware Hub
FWH
High Definition Multimedia Interface. HDMI supports standard, enhanced, or
high-definition video, plus multi-channel digital audio on a single cable. HDMI
transmits all ATSC HDTV standards and supports 8-channel digital audio, with
bandwidth to spare for future requirements and enhancements (additional
details available through: http://www.hdmi.org/)
HDMI
Host
IGD
This term is used synonymously with processor.
Internal Graphics Device. Generic name for a graphics accelerator that
performs decoding of digital video signals.
Intel® GMA
500
Intel® Graphics Media Accelerator 500. A hardware accelerator for 2D and 3D
graphics.
INTx
IT
An interrupt request signal where “x” stands for interrupts A, B, C, and D
Industrial Temperature - AEC-Q100 Grade 3: -40 to 85° C ambient
Liquid Crystal Display
LCD
Low Voltage Differential Signaling. LVDS is a high speed, low power data
transmission standard used for display connections to LCD panels.
LVDS
MSI
Message Signaled Interrupt. MSI is a transaction initiated outside the host,
conveying interrupt information to the receiving agent through the same path
that normally carries read and write commands.
PCI Express* is a high-speed serial interface. The PCI Express* configuration
is software compatible with the existing PCI specifications.
PCI Express*
Processor
Rank
Intel® AtomTM processor
A unit of DRAM corresponding to number of SDRAM devices in parallel such
that a full 64-bit data bus is formed.
Intel® System Controller Hub: a single-chip component that contains the
processor interface, DDR2 SDRAM controller, Intel® GMA 500, various display
interfaces, USB, SDIO, PCI Express*, PATA, LPC, and other I/O capabilities.
Intel® SCH
SCI
System Control Interrupt. SCI is used in the ACPI protocol.
Secure Digital / Secure Digital Input Output Cards
SD/SDIO
Serial Digital Video Out (SDVO). SDVO is a digital display channel that serially
transmits digital display data to an external SDVO device. The SDVO device
accepts this serialized format and then translates the data into the appropriate
display format (i.e., TMDS, LVDS, TV-Out).
SDVO
SMC
Embedded Controller, or External Controller. Refers to a separate system
management controller that handles reset sequences, sleep state transitions,
and other system management tasks.
Third party codec that use SDVO as an input may have a variety of output
formats, including DVI, LVDS, HDMI, TV-Out, etc.
SDVO Device
SERR
System Error. SERR is an indication that an unrecoverable error has occurred
on an I/O bus.
Datasheet Addendum
Document number: 321422-001
8
Introduction
Table 1.
Terminology
Term
Description
System Management Interrupt. SMI is used to indicate any of several system
conditions (such as, thermal sensor events, throttling activated, access to
System Management RAM, chassis open, or other system state related
activity).
SMI
Transition Minimized Differential Signaling. TMDS is a signaling interface from
Silicon Image* that is used in DVI and HDMI. TMDS is based on low-voltage
differential signaling and converts an 8-bit signal into a 10-bit transition-
minimized and DC-balanced signal (equal number of 0s and 1s) in order to
reduce EMI generation and improve reliability.
TMDS
TOLM
Top Of Low Memory. The highest address below 4 GB where a processor-
initiated memory read or write transaction will create a corresponding cycle to
DRAM on the memory interface.
Universal Host Controller Interface. A controller interface that supports two
USB 1.1 ports. The Intel® SCH contains three UHCI controllers.
UHCI
UMA
Unified Memory Architecture. UMA describes an IGD using system memory for
its frame buffers.
VCO
Voltage Controlled Oscillator
Warm Reset
Warm reset is when both RESET# and PWROK are asserted.
1.2
Reference Documents
Table 2.
Reference documents
Document
Document number/ Location
319535
Intel® AtomTM Processor Z5xx Series Datasheet
Intel® AtomTM Processor Z5xx Series Specification
Update
319536
Intel® AtomTM Processor Z5xx Series Datasheet
Addendum and Specification Update Addendum
321423
Intel® System Controller Hub (Intel® SCH) Datasheet
319537
Intel® System Controller Hub (SCH) Specification
Update
319538
PCI Express Base Specification, Revision 1.0a
http://www.pcisig.com/specifications
Low Pin Count Interface Specification, Revision 1.1
(LPC)
http://developer.intel.com/design/
chipsets/industry/lpc.htm
System Management Bus Specification, Version 1.0
(SMBus)
http://www.smbus.org/specs/
PCI Local Bus Specification, Revision 2.3 (PCI)
PCI Power Management Specification, Revision 1.1
http://www.pcisig.com/specifications
http://www.pcisig.com/specifications
Advanced Configuration and Power Interface, Version
3.0 (ACPI)
http://www.acpi.info/
http://download.intel.com/
technology/usb/UHCI11D.pdf
Universal Host Controller Interface, Revision 1.1 (UHCI)
Datasheet Addendum
Document number: 321422-001
9
Introduction
Document
Document number/ Location
Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 (EHCI)
http://developer.intel.com/
technology/usb/ehcispec.htm
Universal Serial Bus Specification (USB), Revision 2.0
http://www.usb.org/developers/docs
http://T13.org (T13 1410D)
AT Attachment - 6 with Packet Interface (ATA/ATAPI -
6)
IA-PC HPET (High Precision Event Timers) Specification, http://www.intel.com/
Revision 1.0
hardwaredesign/hpetspec_1.pdf
1.3
Overview
The Intel® SCH is designed for use with Intel® AtomTM processor-based platforms. The
System Controller Hub connects to the processor as shown in Figure 1.
The Intel® SCH incorporates a variety of PCI functions as listed in Table 3.
Table 3.
PCI Devices and Functions
Device
Function
Function Description
0
2
0
0
0
0
0
1
0
1
2
7
0
1
2
0
1
Host Bridge
Integrated Graphics and Video Device
26
27
USB Client
Intel® High Definition Audio (Intel® HD Audio) Controller
PCI Express* Port 1
28
PCI Express* Port 2
USB Classic UHCI Controller 1
USB Classic UHCI Controller 2
USB Classic UHCI Controller 3
USB2 EHCI Controller
29
SDIO/MMC Port 0
30
31
SDIO/MMC Port 1
SDIO/MMC Port 2
LPC Interface
PATA Controller
NOTE: All devices are on PCI Bus 0.
1.3.1
Processor Interface
The Intel® SCH supports the Intel® AtomTM processor Z5xxP series subset of the
Enhanced Mode Scalable Bus Protocol, and implements a low-power CMOS bus. The
System Controller Hub supports a single bus agent with FSB data rates of 400 MT/s and
533 MT/s. The Intel® SCH features include:
• Intel® AtomTM processor Z5xxPx series support
• CMOS frontside bus signaling for reduced power
• 400 MT/s or 533 MT/s data rate operation
Datasheet Addendum
Document number: 321422-001
10
Introduction
• 64-Byte cache-line size
• 64-bit data bus, 32-bit address bus
• Supports one physical processor attachment with up to two logical processors
• 16 deep IOQ
• 1 deep defer queue
• FSB interrupt delivery
• Power-saving sideband control (DPWR#) for enabling/disabling processor data
input sense amplifiers
• 1.05-V VTT operation
1.3.2
System Memory Controller
The Intel® SCH integrates a DDR2 memory controller with a single 64-bit wide
interface. Only DDR2 memory is supported. The memory controller interface is fully
configurable through a set of control registers. Features of the Intel® SCH memory
controller include:
• Supports 1.8 V DDR2 SDRAM, up to 2 ranks
• Supports 400 MT/s and 533 MT/s data rates
• Single 64-bit wide channel
• Single command per clock (1-N) operation
• Support for a maximum of 2GB of DRAM
• One or two rank operation
• Device density support for 512 Mb, 1024Mb, and 2084 Mb devices
• Device widths of x16
• Aggressive power management to reduce idle power consumption
• Page closing policies to proactively close pages after idle periods
• No on-die termination (ODT) support
• Supports non-terminated and board-terminated bus topologies
1.3.3
1.3.4
USB Host
The Intel® SCH contains three Universal Host Controller Interface (UHCI) USB 1.1
controllers and an Enhanced Host Controller Interface (EHCI) USB 2.0 controller. Port-
routing logic on the system controller hub determines which USB controller is used to
operate a given USB port.
A total of eight USB ports are supported. All eight of these ports are capable of high-
speed data transfers up to 480MB/s, and six of the ports are also capable of full-speed
and low-speed signaling. The two high-speed-only USB ports may only be used
internally within the system platform.
USB Client
The Intel® SCH supports USB client functionality on port 2 of the USB interface. This
permits the platform to attach to a separate USB host as a peripheral mass storage
volume or RNDIS device.
Datasheet Addendum
Document number: 321422-001
11
Introduction
1.3.5
PCI Express*
The Intel® SCH has two PCI Express* root ports supporting the PCI Express Base
Specification, Revision 1.0a. PCI Express* root ports 1–2 can be statically configured as
two x1 lanes. Each root port supports 2.5 Gb/s bandwidth in each direction.
An external graphics device can be used via one of the x1 PCI Express* lanes/ports.
1.3.6
1.3.7
LPC Interface
The Intel® SCH implements an LPC interface as described in the LPC 1.1 Specification.
The LPC bridge function of the system controller hub resides in PCI Device 31: Function
0.
The LPC interface has three PCI-based clock outputs that may be provided to different
I/O devices, such as Firmware Hub flash memory or a legacy I/O chip. The
LPC_CLKOUT signals run at one-fourth the H_CLKINP/N frequency and support a total
of six loads (two loads per clock pair) with no external buffering.
Parallel ATA (PATA)
The PATA Host Controller supports three types of data transfers:
• Programmed I/O (PIO): Processor is in control of the data transfer.
• Multi-word DMA (ATA-5): DMA protocol that resembles the DMA on the ISA bus.
Allows transfer rates of up to 66MB/s.
• Ultra DMA: Synchronous DMA protocol that redefines signals on the PATA cable to
allow both host and target throttling of data and transfer rates up to 100MB/s. Ultra
DMA 100/66/33 are supported.
The frequency of the PATA clock is one-fourth the host bus clock (H_CLKINP/N).
®
1.3.8
Intel Graphics Media Accelerator 500
The Intel® SCH provides integrated graphics (2D and 3D) and high-definition video
decode capabilities with minimal power consumption.
1.3.8.1
Graphics
The highly compact IGD contains an advanced shader architecture (model 3.0+) that
performs pixel shading and vertex shading within a single hardware accelerator. The
processing of pixels is deferred until they are determined to be visible, which minimizes
access to memory and improves render performance.
1.3.8.2
Video
The Intel® SCH supports full hardware acceleration of video decode standards such as
H.264, MPEG2, MPEG4, VC1, and WMV9.
1.3.9
Display Interfaces
The IGD includes LVDS and Serial DVO display ports permitting simultaneous
independent operation of two displays, depending on SKU.
If external graphics is used instead of the internal graphics device, LVDS and SDVO
ports will not function.
Datasheet Addendum
Document number: 321422-001
12
Introduction
1.3.9.1
LVDS
The Intel® SCH supports a Low-Voltage Differential Signaling interface that allows the
IGD to communicate directly to an on-board flat-panel display. The LVDS interface
supports pixel color depths of 18 and 24 bits.
1.3.9.2
Serial DVO (SDVO) Display
The Intel® SCH has a digital display channel capable of driving SDVO adapters that
provide interfaces to a variety of external display technologies (e.g., DVI, TV-Out,
analog CRT).
SDVO lane reversal is not supported.
1.3.10
Secure Digital I/O (SDIO) / Multimedia Card (MMC)
Controller
The Intel® SCH contains three SDIO/MMC expansion ports used to communicate with a
variety of internal or external SDIO and MMC devices. Each port supports SDIO
Revision 1.1 and MMC Revision 4.0 and is backward-compatible with previous interface
specifications.
1.3.11
1.3.12
SMBus Host Controller
The Intel® SCH contains an SMBus host interface that allows the processor to
communicate with SMBus slaves. This interface is compatible with most I2C devices.
The system controller hub SMBus host controller provides a mechanism for the
processor to initiate communications with SMBus peripherals (slaves). See the System
Management Bus (SMBus) Specification, Version 1.0.
®
®
Intel High Definition Audio (Intel HD Audio) Controller
The Intel® High Definition Audio Specification defines a digital interface that can be
used to attach different types of codecs (such as audio and modem codecs). The Intel
HD Audio controller supports up to four audio streams, two in and two out.
With the support of multi-channel audio stream, 32-bit sample depth, and sample rate
up to 192 kHz, the Intel High Definition Audio (Intel HD Audio) controller provides
audio quality that can deliver consumer electronic (CE) levels of audio experience. On
the input side, the Intel® SCH adds support for an array of microphones.
The Intel HD Audio controller uses a set of DMA engines to effectively manage the link
bandwidth and support simultaneous independent streams on the link. The capability
enables new exciting usage models with Intel HD Audio (e.g., listening to music while
playing a multi-player game on the Internet.) The Intel HD Audio controller also
supports isochronous data transfers allowing glitch-free audio to the system.
1.3.13
General Purpose I/O (GPIO)
The Intel® SCH contains a total of 14 GPIO pins. Ten GPIOs are powered by the core
power rail and are turned off during sleep modes (S3 and higher). The remaining four
GPIOs are powered by the system controller hub suspend well power supply. These
GPIOs and remain active during S3. The suspend well GPIOs can be used to wake the
system from the Suspend-to-RAM state.
The GPIOs are not 5V tolerant.
Datasheet Addendum
Document number: 321422-001
13
Introduction
1.3.14
Power Management
The Intel® SCH contains a mechanism to allow flexible configuration of various device
maintenance routines as well as power management functions such as enhanced clock
control and low-power state transitions (e.g., Suspend-to-RAM and Suspend-to-Disk).
A hardware-based thermal management circuit permits software-independent entrance
to low-power states. The system controller hub contains full support for the Advanced
Configuration and Power Interface (ACPI) Specification, Revision 3.0.
Datasheet Addendum
Document number: 321422-001
14
Signal Description
2
Signal Description
This chapter provides a detailed description of the Intel® SCH signals and boot strap
definitions. The signals are arranged in functional groups according to their associated
interface (see Figure 2).
Figure 2.
Signal Information Diagram
LA_DATAP[3:0], LA_DATAN[3:0]
LA_CLKP
LA_CLKN
H_A[31:3]#
H_D[63:0]#
H_ADS#
Display
(LVDS)
Interface
H_BNR#
H_BPRI#
H_DBSY#
H_DEFER#
H_DRDY#
H_DPWR#
H_HIT#
H_HITM#
H_LOCK#
H_REQ[4:0]#
H_TRDY#
SDVOB_GREEN+, SDVOB_GREEN-
SDVOB_BLUE+, SDVOB_BLUE-
SDVOB_RED+, SDVOB_RED-
SDVOB_CLK+, SDVOB_CLK-
Intel®
SDVO
Device
Interface
SDVOB_INT+, SDVOB_INT-
SDVO_TVCLKIN+, SDVO_TVCLKIN-
SDVO_STALL+, SDVO_STALL-
SDVO_CTRLCLK, SDVO_CTRLDATA
L_DDC_CLK, L_DDC_DATA
L_CTLA_CLK / L_CTLB_DATA
L_VDDEN
Display
Data
Channel
H_RS[2:0]#
H_CPURST#
H_BREQ0#
H_DINV[3:0]#
H_ADSTB[1:0]#
H_DSTBP[3:0]#, H_DSTBN[3:0]#
H_THRMTRIP#
H_CPUSLP#
H_PBE#
Processor
Front Side
Bus
L_BKLTEN, L_BKLTCTL
HDA_RST#
HDA_SYNC
HDA_CLK
HDA_SDO
HDA_SDI[1:0]
HDA_DOCKEN#
HDA_DOCKRST#
Interface
Intel®
HD Audio
Interface
H_INIT#
H_INTR
H_NMI
H_SMI#
THRM#
H_STPCLK#
H_CLKINP, H_CLKINN
H_RCOMPO
H_GVREF
RESET#
PWROK
RSMRST#
RTCRST#
SUSCLK
WAKE#
STPCPU#
DPRSLPVR
SLPMODE
RSTWARN
SLPRDY#
RSTRDY#
GPE#
H_CGVREF
H_SWING
H_DPSLP#
H_CPUPWRGD
H_DPRSTP#
Power
Mangm’t
Interface
SM_DQ[63:0]
SM_DQS[7:0]
SM_MA[14:0]
SM_BS[2:0]
SLPIOVR#
System
SM_RAS#
PATA_DCS1#
PATA_DCS3#
PATA_DA[2:0]
PATA_DD[15:0]
PATA_DDREQ
PATA_DDACK#
PATA_DIOR#
PATA_DIOW#
PATA_IORDY
PATA_IDEIRQ
SM_CAS#
SM_WE#
Memory
Interface
Parallel
ATA
(PATA)
Interface
SM_RCVENIN#
SM_RCVENOUT#
SM_CK[1:0]
SM_CK[1:0]#
SM_CS[1:0]#
SM_CKE[1:0]
SM_RCOMPO
SM_VREF
PCIE_PETp[2:1], PCIE_PETn[2:1]
PCIE_PERp[2:1], PCIE_PERn[2:1]
PCIE_CLKINP, PCIE_CLKINN
PCIE_ICOMPO, PCIE_ICOMPI
SMB_DATA
SMB_CLK
SMB_ALERT#
SMBus
Interface
PCI
Express*
Interface
RTC
Interface
RTC_X1
RTC_X2
USB_DP[7:0]/USB_DN[7:0]
USB_OC[7:0]#
DA_REFCLKINP, DA_REFCLKINN
DB_REFCLKINPSSC, DB_REFCLKINNSSC
BSEL2
CFG[1:0]
CLK14
INTVRMEN
SPKR
SMI#, EXTTS0#
CLKREQ#
USB
Interface
USB_RBIASP
USB_RBIASN
USB_CLK48
Misc.
Signals
and
SD[2..0]_PWR#, SD[1,0]_DATA[3:0], SD2_DATA[7:0]
SD[2:0]_CMD
Clocks
SD[2:0]_CD#
SD[2:0]_CLK
SD[2:0]_WP
SD/MMC
Interface
SD[2:0]_PWR#
SD[2:0]_LED
GPIO[9:8, 6:0]
GPIOSUS[3:0]
GPIO
LPC_AD[3:0]
LPC_FRAME#
LPC_SERIRQ
TCK
TMS
TDI
TDO
TRST#
LPC
Interface
JTAG
Interface
LPC_CLKOUT[2:0]
LPC_CLKRUN#
Datasheet Addendum
Document number: 321422-001
15
Signal Description
2.1
Host Interface Signals
Each signal description table has the following headings:
• Signal: The name of the signal/pin.
• Type: The buffer direction and type. Buffer direction can be either input, output, or
I/O (bidirectional). See Table 4 for definitions of the different buffer types.
• Power Well: The power plane used to supply power to that signal. Choices are
Core, DDR, Suspend, and RTC.
• Description: A brief explanation of the signal’s function.
Table 4.
Intel® SCH Signal Description (Sheet 1 of 4)
Power
Well
Signal
Type
Description
I/O
AGTL+
Address Strobe: The host bus owner asserts H_ADS# to
indicate the first of two cycles of a request phase.
H_ADS#
Core
Block Next Request: This signal is used to block the
current request bus owner from issuing a new request. This
signal is used to dynamically control the processor bus
pipeline depth.
I/O
CMOS
H_BNR#
H_BPRI#
Core
Core
Priority Agent Bus Request: The Intel® SCH is the only
Priority Agent on the processor bus. It asserts this signal to
obtain the ownership of the address bus. This signal has
priority over symmetric bus requests and will cause the
current symmetric owner to stop issuing new transactions
unless the H_LOCK# signal was asserted.
O
CMOS
Bus Request 0#: The Intel® SCH pulls the processor bus
H_BREQ0# signal low during H_CPURST#. The signal is
sampled by the processor on the active-to-inactive
transition of H_CPURST#.
I/O
CMOS
H_BREQ0#
Core
Core
H_BREQ0# should be tri-stated after the hold time
requirement has been satisfied.
CPU Reset: H_CPURST# allows the processor to begin
execution in a known state. The Intel® SCH asserts
H_CPURST# and deasserts H_CPUPWRGD upon exit from
its reset. H_CPURST# is deasserted 2–10 ms after
H_CPUPWRGD is asserted.
O
CMOS
H_CPURST#
Data Bus Busy: This signal is used by the data bus owner
to hold the data bus for transfers requiring more than one
cycle.
I/O
AGTL+
H_DBSY#
Core
Core
Defer: The Intel® SCH will generate a deferred response
as defined by the rules of the dynamic defer policy. The
Intel® SCH will also use the H_DEFER# signal to indicate a
processor retry response.
I/O
CMOS
H_DEFER#
Datasheet Addendum
Document number: 321422-001
16
Signal Description
Table 4.
Intel® SCH Signal Description (Sheet 2 of 4)
Power
Well
Signal
Type
Description
Dynamic Bus Inversion: These signals are driven along
with the H_D[63:0]# signals. They indicate if the
associated data bus signals are inverted or not.
H_DINV[3:0]# are asserted such that the number of data
bits driven electrically low (low voltage) within the
corresponding 16-bit group never exceeds 8.
I/O
CMOS
H_DINV[3:0]#
Core
H_DINV[x]# Data Bits
H_DINV3#H_D[63:48]
H_DINV2#H_D[47:32]
H_DINV1#H_D[31:16]
H_DINV0#H_D[15:0]
Data Power: Used by Intel® SCH to indicate that a data
return cycle is pending within 2 host clock cycles or more.
The processor uses this signal during a read-cycle to
activate the data input buffers in preparation for H_DRDY#
and the related data.
O
CMOS
H_DPWR#
Core
I/O
AGTL+
Data Ready: This signal is asserted for each cycle that
data is transferred.
H_DRDY#
Core
Core
Host Address Bus: H_A[31:3]# connect to the processor
address bus. During processor cycles, H_A[31:3]# are
inputs.
I/O
CMOS
H_A[31:3]#
Host Address Strobe: The source synchronous strobes
are used to transfer H_A[31:3]# and H_REQ[4:0]# at the
2x transfer rate.
I/O
AGTL+
H_ADSTB[1:0]#
H_D[63:0]#
Core
Core
H_ADSTB0# maps to H_A[16:3]#, H_REQ[4:0]#
H_ADSTB1# maps to H_A[31:17]#
I/O
CMOS
Host Data: These signals are connected to the processor
data bus.
Host Data Strobes: The source synchronous strobes used
to transfer H_D[63:0]# and H_DINV[3:0]# at the 4x
transfer rate.
H_DSTBP[3:0]#
H_DSTBN[3:0]#
I/O
AGTL+
Strobe Data Bits
Core
Core
H_DSTB[P/N]3#H_D[63:48]#, H_DINV3#
H_DSTB[P/N]2# H_D[47:32]#, H_DINV2#
H_DSTB[P/N]1# H_D[31:16]#, H_DINV1#
H_DSTB[P/N]0# H_D[15:0]#, H_DINV0#
Hit: This signal indicates that a caching agent holds an
unmodified version of the requested line. Also, driven in
conjunction with H_HITM# by the target to extend the
snoop window.
I/O
CMOS
H_HIT#
Hit Modified: This signal indicates that a caching agent
holds a modified version of the requested line and that this
agent assumes responsibility for providing the line. This
signal is also driven in conjunction with H_HIT# to extend
the snoop window.
I/O
CMOS
H_HITM#
H_LOCK#
Core
Core
Host Lock: All processor bus cycles sampled with the
assertion of H_LOCK# and H_ADS#, until the negation of
H_LOCK# must be atomic.
I
CMOS
Datasheet Addendum
Document number: 321422-001
17
Signal Description
Table 4.
Intel® SCH Signal Description (Sheet 3 of 4)
Power
Well
Signal
Type
Description
Host Request Command: These signals are asserted
during both clocks of the request phase. In the first clock,
the signals define the transaction type to a level of detail
that is sufficient to begin a snoop request. In the second
clock, the signals carry additional information to define the
complete transaction type.
I/O
CMOS
H_REQ[4:0]#
Core
Core
Host Target Ready: This signal indicates that the target of
the processor transaction is able to enter the data transfer
phase.
O
CMOS
H_TRDY#
Response Signals: These signals indicate the type of
response as shown below:
000 = Idle State
001 = Retry Response
010 = Deferred Response
O
CMOS
H_RS[2:0]#
Core
011 = Reserved (not driven by Intel® SCH)
100 = Hard Failure (not driven by Intel® SCH)
101 = No data response
110 = Implicit Writeback
111 = Normal data response
Thermal Trip: When low, this signal indicates that a
thermal trip event from the processor occurred, and
corrective action will be taken.
I
H_THRMTRIP#
H_CPUSLP#
H_PBE#
Core
Core
Core
Core
CMOS
CPU SLP: This signal puts the processor into a state that
saves power vs. the Stop-Grant state. However, during that
time, no snoops occur. The signal will go active for all other
sleep states.
O
CMOS
Pending Break Event: This signal can be used in some
states for notification by the processor of pending interrupt
events.
I
CMOS
Initialization: The Intel® SCH can be configured to
support a special meaning to the CPU during H_CPURST#
deassertion. H_INIT# functionality for resetting the CPU is
not supported. This signal requires a board-level pull-up.
O
CMOS
_OD
H_INIT#
Processor Interrupt: H_INTR is asserted by the Intel®
SCH to signal the processor that an interrupt request is
pending and needs to be serviced. It is an asynchronous
output normally driven low.
O
CMOS
H_INTR
H_NMI
Core
Core
Core
Non-Maskable Interrupt: H_NMI is used to force a non-
maskable interrupt to the processor. The processor detects
the rising edge of H_NMI. A non-maskable interrupt is reset
by setting the corresponding NMI source enable/disable bit
in the NMI Status and Control Register.
O
CMOS
System Management Interrupt: H_SMI# is an active
low output synchronous to LPC clock that is asserted by the
Intel® SCH in response to one of many enabled hardware
or software events.
O
CMOS
H_SMI#
Datasheet Addendum
Document number: 321422-001
18
Signal Description
Table 4.
Intel® SCH Signal Description (Sheet 4 of 4)
Power
Well
Signal
Type
Description
Stop Clock Request: H_STPCLK# is an active-low output
synchronous to LPC clock that is asserted by Intel® SCH in
response to one of many hardware or software events.
When the processor samples H_STPCLK# asserted, it
responds by stopping its internal clock.
O
CMOS
H_STPCLK#
Core
Core
Deep Sleep: This signal is asserted by the Intel® SCH to
the processor and system controller hub. When the signal is
low, the processor enters the Deep Sleep state by gating off
the processor Core clock inside the processor. When the
signal is high (default), the processor is not in the Deep
Sleep state. This signal and the H_STPCLK# pin shut the
clock in the processor and at the clock generator,
respectively. The H_DPSLP# assertion time is wider than
the H_STPCLK# assertion time in order for the processor to
receive an active clock input whenever H_DPSLP# is
deasserted.
O
CMOS
H_DPSLP#
Deeper Sleep: When asserted on the platform, this signal
causes the processor to transition from the Deep Sleep
State to the Deeper Sleep state. To return to the deep sleep
state, H_DPRSTP# must be deasserted.
O
CMOS
H_DPRSTP#
Core
Core
CPU Power Good: This signal is used for Enhanced Intel
SpeedStep® technology support. H_CPUPWRGD goes to
the processor. It is kept high during the Intel SpeedStep®
technology state transition to prevent loss of processor
context.
O
CMOS
H_CPUPWRGD
Host Interface Reference and Compensation
Differential clock Input for the Host PLL: This low-
I
H_CLKINP
H_CLKINN
voltage differential signal pair is used for FSB transactions.
The clock input also supplies a signal to the internal core
and memory interface clocks.
CMOS
0.8
Core
Host Resistor Compensation: This is connected to a
reference resistor to dynamically calibrate the driver
strengths.
I/O
A
H_RCOMPO
H_SWING
Core
Core
Core
I
A
Voltage Swing Calibration
Voltage Reference: These pins are for the input buffer
differential amplifier to determine a high versus a low input
voltage.
H_GVREF
H_CGVREF
I
A
Datasheet Addendum
Document number: 321422-001
19
Signal Description
2.2
System Memory Signals
Table 5.
System Memory Signals (Sheet 1 of 2)
Power
Signal
Type
Description
Well
I/O
CMOS1.8
Data Lines: The SM_DQ[63:0] signals interface to the
DRAM data bus.
SM_DQ[63:0]
DDR
Data Strobes: These signals are the data strobes used
for capturing data. Each strobe signal corresponds to 8
data bits. During writes, SM_DQSx is centered in data.
During reads, SM_DQSx is edge aligned with data.
I/O
CMOS1.8
SM_DQS[7:0]
SM_MA[14:0]
SM_BS[2:0]
DDR
DDR
DDR
O
Memory Address: These signals are used to provide
the multiplexed row and column address to the SDRAM.
CMOS1.8
Bank Select (Bank Address): These signals define
which banks are selected within each SDRAM row. Bank
select and memory address signals combine to address
every possible location within an SDRAM device.
O
CMOS1.8
Row Address Strobe: SM_RAS# is used to signify the
presence of the row address on SM_MA[14:0] to the
DRAM device being selected.
O
SM_RAS#
DDR
CMOS1.8
Column Address Strobe: SM_CAS# is used to signify
the presence of the column row address on SM_MA to
the DRAM device being selected.
O
SM_CAS#
SM_WE#
DDR
DDR
CMOS1.8
O
Write Enable: SM_WE# tells the DRAM memory that it
is performing a write operation on the bus.
CMOS1.8
Receive Enable In: This signal connects to
SM_SRCVENOUT# internally. This input (driven from
SM_SRCVENOUT#) enables the DQS input buffers
during reads.
I
SM_RCVENIN#
DDR
DDR
CMOS1.8
Receive Enable Out: This signal connects to
SM_SRCVENIN# internally. It is part of the feedback
used to enable the DQS input buffers during reads.
O
SM_RCVENOUT#
CMOS1.8
Differential DDR Clock: SM_CKx and SM_CKx# pairs
are differential clock outputs. The crossing of the
positive edge of SM_CKx and the negative edge of
SM_CKx# is used to sample the address and control
signals on the DRAM.
SM_CK[1:0]
SM_CK[1:0]#
O
DDR
DDR
CMOS1.8
Chip Select: These signals select particular DRAM
components during the active state. There is one
SM_CSx# for each DRAM rank, toggled on the positive
edge of SM_CKx
O
SM_CS[1:0]#
CMOS1.8
Datasheet Addendum
Document number: 321422-001
20
Signal Description
Table 5.
System Memory Signals (Sheet 2 of 2)
Power
Well
Signal
Type
Description
Clock Enable: SM_CKEx is used to initialize DRAM
during power-up and to place all DRAM rows into and
out of self-refresh during the S3 Suspend-to-RAM low
power state. SM_CKEx is also used to dynamically
power down inactive DRAM rows. There is one
SM_CKEx per SDRAM row, toggled on the positive edge
of SM_CKx.
O
SM_CKE[1:0]
DDR
CMOS1.8
Input Buffer VREF: This signal is for the input buffer
differential amplifier to determine a high versus a low
input voltage.
I
A
SM_VREF
DDR
DDR
Resistor Compensation Output Pin: This pin is
connected to a reference resistor to calibrate the
dynamically calibrate the driver strengths.
I/O
A
SM_RCOMPO
2.3
Integrated Display Interfaces
2.3.1
LVDS Signals
Table 6.
LVDS Signals
Power
Well
Signal
Type
Description
LA_DATAP[3:0]
LA_DATAN[3:0]
O
LVDS
Channel A Differential Data Output: Differential
signal pair.
Core
LA_CLKP
LA_CLKN
O
LVDS
Channel A Differential Clock Output: Differential
signal pair.
Core
Datasheet Addendum
Document number: 321422-001
21
Signal Description
2.3.2
Serial Digital Video Output (SDVO) Signals
Table 7.
Serial Digital Video Output (SDVO) Signals
Power
Signal Name
Type
Description
Well
Serial Digital Video Channel B Red: SDVOB_RED[±]
is a differential data pair that provides red pixel data for
the SDVOB channel during Active periods. During
blanking periods it may provide additional such as sync
information, auxiliary configuration data, etc. This data
pair must be sampled with respect to the
SDVOB_RED+
SDVOB_RED-
O
PCIe
Core
SDVOB_CLK[±] signal pair.
Serial Digital Video Channel B Green:
SDVOB_GREEN[±] is a differential data pair that
provides green pixel data for the SDVOB channel during
Active periods. During blanking periods it may provide
additional such as sync information, auxiliary
configuration data, etc. This data pair must be sampled
with respect to the SDVOB_CLK[±] signal pair.
SDVOB_GREEN+
SDVOB_GREEN-
O
PCIe
Core
Core
Serial Digital Video Channel B Blue:
SDVOB_BLUE[±] is a differential data pair that provides
blue pixel data for the SDVOB channel during Active
periods. During blanking periods it may provide
additional such as sync information, auxiliary
configuration data, etc. This data pair must be sampled
with respect to the SDVOB_CLK[±] signal pair.
SDVOB_BLUE+
SDVOB_BLUE-
O
PCIe
Serial Digital Video Channel B Clock: This
differential clock signal pair is generated by the Intel®
SCH internal PLL and runs between 100 MHz and
200 MHz.
SDVOB_CLK+
SDVOB_CLK-
O
PCIe
Core
Core
If TV-out mode is used, the SDVO_TVCLKIN[±] clock
input is used as the frequency reference for the PLL.
The SDVOB_CLK[±] output pair is then driven back to
the SDVO device.
Serial Digital Video Input Interrupt: Differential
input pair that may be used as an interrupt notification
from the SDVO device to the Intel® SCH. This signal
pair can be used to monitor hot plug attach/detach
notifications for a monitor driven by an SDVO device.
SDVOB_INT+
SDVOB_INT-
I
PCIe
Serial Digital Video TV-OUT Synchronization
Clock: Differential clock pair that is driven by the SDVO
device to the Intel® SCH. If SDVO_TVCLKIN[±] is used,
it becomes the frequency reference for the system
controller hub dot clock PLL, but will be driven back to
the SDVO device through the SDVOB_CLK[±]
differential pair.
SDVO_TVCLKIN+
SDVO_TVCLKIN-
I
Core
PCIe
This signal pair has an operating range of
100–200 MHz, so if the desired display frequency is less
than 100 MHz, the SDVO device must apply a multiplier
to get the SDVO_TVCLKIN[±] frequency into the 100-
to 200-MHz range.
Datasheet Addendum
Document number: 321422-001
22
Signal Description
Table 7.
Serial Digital Video Output (SDVO) Signals
Power
Well
Signal Name
Type
Description
Serial Digital Video Field Stall: Differential input pair
that allows a scaling SDVO device to stall the Intel®
SCH pixel pipeline.
SDVO_STALL+
SDVO_STALL-
I
Core
Core
PCIe
SDVO Control Clock: Single-ended control clock line
from the Intel® SCH to the SDVO device. Similar to I2C
clock functionality, but may run at faster frequencies.
SDVO_CTRLCLK is used in conjunction with
SDVO_CTRLDATA to transfer device configuration,
PROM, and monitor DDC information. This interface
directly connects the system controller hub to the SDVO
device.
I/O
CMOS3.3
_OD
SDVO_CTRLCLK
SDVO Control Data: SDVO_CTRLDATA is used in
conjunction with SDVO_CTRLCLK to transfer device
configuration, PROM, and monitor DDC information.
This interface directly connects the Intel® SCH to the
SDVO device.
I/O
SDVO_CTRLDATA CMOS3.3
_OD
Core
2.3.3
Display Data Channel (DDC) and GMBUS Support
Table 8.
Display Data Channel (DDC) and GMBUS Support
Power
Well
Signal Name
Type
Description
I/O
CMOS3.3
_OD
Display Data Channel Clock: I2C-based control signal
(Clock) for EDID control
L_DDC_CLK
Core
I/O
CMOS3.3
_OD
Display Data Channel Data: I2C-based control signal
(Data) for EDID control
L_DDC_DATA
L_CTLA_CLK
L_CTLB_DATA
Core
Core
Core
I/O
CMOS3.3
_OD
Control A Clock: This signal can be used to control
external clock chip for SSC - optional
I/O
CMOS3.3
_OD
Control B Data: This signal can be used to control
external clock chip for SSC - optional
O
LCD Power Enable: This signal permits panel power
enable control.
L_VDDEN
L_BKLTEN
L_BKLTCTL
Core
Core
Core
CMOS3.3
O
LCD Backlight Enable: This signal permits panel
backlight enable control.
CMOS3.3
O
LCD Backlight Control: This signal allows control of
LCD brightness.
CMOS3.3
Datasheet Addendum
Document number: 321422-001
23
Signal Description
2.4
Universal Serial Bus (USB) Signals
Table 9.
Universal Serial Bus (USB) Signals
Power
Signal Name
Type
Description
Well
USB Port 5:0 Differentials: Bus Data/Address/
Command Bus: These differential pairs are used to
transmit data/address/command signals for ports 0
through 5. These ports can be routed to either the EHCI
controller or one of the three UHCI controllers and are
capable of running at either high, full, or low speed.
USB_DP[5:0]/
USB_DN[5:0]
I/O
USB
Sus
USB Port 7:6 Differentials: Bus Data/Address/
Command Bus: These differential pairs are used to
transmit data/address/command signals for ports 6 and
7. These ports are routed only to the EHCI controller and
should be used ONLY for in-system USB 2.0 devices.
USB_DP[7:6]/
USB_DN[7:6]
I/O
USB
Sus
Resistor Bias P: This pin is an analog connection point
for an external resistor. This signal is used to set
transmit currents and internal load resistors.
O
A
USB_RBIASP
USB_RBIASN
USB_CLK48
Sus
Sus
Sus
Resistor Bias N: This pin is an analog connection point
for an external resistor. This signal is used to set
transmit currents and internal load resistors.
I
A
48-MHz Clock: This optional clock is used to run the
USB controller. By default, the Intel® SCH uses
DA_REFCLKIN to clock the USB logic.
I
USB
Overcurrent Indicators: These signals set
corresponding bits in the USB controllers to indicate that
an overcurrent condition has occurred.
I
USB_OC[7:0]#
Sus
Sus
CMOS3.3
USB_OC[7:0]# are not 5-V tolerant.
USB Client Connect: This signal, on GPIOSUS3, may
be used in systems where USB port 2 is configured for
client mode. This indicates connection to an external
USB host has been established.
USBCC/
GPIOSUS3
I/O
CMOS3.3
NOTE: If USB Client support is enabled, then this signal
is dedicated for USB Client Connect.
Datasheet Addendum
Document number: 321422-001
24
Signal Description
2.5
PCI Express* Signals
Table 10.
PCI Express* Signals
Power
Well
Signal Name
Type
Description
PCIE_PETp[2:1]
PCIE_PETn[2:1]
O
PCIe
PCI Express* Transmit: PCIE_PETp[2:1] are PCI
Express ports 2:1 transmit pair (P and N) signals.
Core
Core
Core
PCIE_PERp[2:1]
PCIE_PERn[2:1]
I
PCI Express Receive: PCIE_PERp[2:1] PCI Express
ports 2:1 receive pair (P and N) signals.
PCIe
PCIE_CLKINP
PCIE_CLKINN
I
PCI Express Input Clock: 100 MHz differential clock
signals.
PCIe
PCI Express Compensation Pin: Output
compensation for both current and resistance. Also
provides buffer compensation for the LVDS and SDVO
buffers.
I/O
A
PCIE_ICOMPO
PCIE_ICOMPI
Core
Core
PCI Express Compensation Pin: Input compensation
for current. Also provides buffer compensation for the
LVDS and SDVO buffers.
I/O
A
2.6
Secure Digital I/O (SDIO)/MultiMedia Card
(MMC) Signals
Table 11.
Secure Digital I/O (SDIO)/MultiMedia Card (MMC) Signals (Sheet 1 of 2)
Power
Signal Name
Type
Description
Well
SDIO Controller 0/1/2 Data: These signals operate in
push-pull mode. The SD card includes internal pull-up
resistors for all data lines. By default, after power-up,
only SDn_DATA0 is used for data transfer. Wider data
bus widths can be configured for data transfer.
NOTE: Port 0 and 1 are 4 bits wide while ports 2 is 8 bits
wide.
SD0_DATA[3:0]
SD1_DATA[3:0]
SD2_DATA[7:0]
I/O
CMOS3.3
Core
SDIO Controller 0/1/2 Command: This signal is used
for card initialization and transfer of commands. It has
two operating modes: open-drain for initialization mode,
and push-pull for fast command transfer.
SD0_CMD
SD1_CMD
SD2_CMD
I/O
CMOS3.3
Core
SDIO Controller 0/1/2 Clock: With each cycle of this
signal a one-bit transfer on the command and each data
line occurs.
This signal is generated by Intel® SCH at a maximum
frequency of:
SD0_CLK
SD1_CLK
SD2_CLK
O
Core
Core
CMOS3.3
24 Mhz for SD and SDIO.
48 Mhz for MMC.
SD0_WP
SD1_WP
SD2_WP
I
SDIO Controller 0/1/2 Write Protect: These signals
denote the state of the write-protect tab on SD cards.
CMOS3.3
Datasheet Addendum
Document number: 321422-001
25
Signal Description
Table 11.
Secure Digital I/O (SDIO)/MultiMedia Card (MMC) Signals (Sheet 2 of 2)
Power
Well
Signal Name
Type
Description
SD0_CD#
SD1_CD#
SD2_CD#
I
SDIO Controller 0/1/2 Card Detect: This signal
indicates when a card is present in an external slot.
Core
Core
Core
CMOS3.3
SD0_LED
SD1_LED
SD2_LED
SDIO Controller 0/1/2 LED: This signal can be used
to drive an external LED and indicate when transfers are
occurring on the bus.
O
CMOS3.3
SD0_PWR#
SD1_PWR#
SD2_PWR#
SDIO/MMC Power Enable: These pins can be used to
enable the power being supplied to an SDIO/MMC
device.
I/O
CMOS3.3
2.7
Parallel ATA (PATA) Signals
Table 12.
Parallel ATA (PATA) Signals (Sheet 1 of 2)
Power
Signal Name
Type
Description
Well
Device Data: These signals drive the corresponding
signals on the PATA connector. There is an internal
13.3-kΩ pull-down on PATA_DD7.
I/O
CMOS3.3-5
PATA_DD[15:0]
Core
Device Address: These output signals are connected
to the corresponding signals on the PATA connectors.
They are used to indicate which byte in either the ATA
command block or control block is being addressed.
O
PATA_DA[2:0]
PATA_DIOR#
Core
Core
CMOS3.3-5
Disk I/O Read (PIO and Non-Ultra DMA): This is
the command to the PATA device that it may drive data
onto the DD lines. Data is latched by the Intel® SCH
on the deassertion edge of PATA_DIOR#. The PATA
device is selected either by the ATA register file chip
selects (PATA_DCS1# or PATA_DCS3#) and the
PATA_DA lines, or the PATA DMA acknowledge
(PATA_DDAK#).
O
CMOS3.3-5
Disk I/O Write (PIO and Non-Ultra DMA): This is
the command to the PATA device that it may latch data
from the PATA_DD lines. Data is latched by the PATA
device on the deassertion edge of PATA_DIOW#. The
PATA device is selected either by the ATA register file
chip selects (PATA_DCS1# or PATA_DCS3#) and the
PATA_DA lines, or the PATA DMA acknowledge
(PATA_DDAK#).
O
PATA_DIOW#
Core
Core
CMOS3.3-5
Device DMA Acknowledge: This signal directly
drives the DAK# signals on the PATA connectors. Each
is asserted by the Intel® SCH to indicate to PATA DMA
slave devices that a given data transfer cycle
(assertion of PATA_DIOR# or PATA_DIOW#) is a DMA
data transfer cycle. This signal is used in conjunction
with the PCI bus master PATA function and are not
associated with any AT-compatible DMA channel.
O
PATA_DDACK#
CMOS3.3-5
Datasheet Addendum
Document number: 321422-001
26
Signal Description
Table 12.
Parallel ATA (PATA) Signals (Sheet 2 of 2)
Power
Well
Signal Name
Type
Description
Device Chip Select for 300 Range: This chip select
is for the ATA control register block. This is connected
to the corresponding signal on the connector.
O
PATA_DCS3#
Core
Core
CMOS3.3-5
Device Chip Selects for 100 Range: This chip select
is for the ATA command register block. This is
connected to the corresponding signal on the PATA
connector.
O
PATA_DCS1#
PATA_DDREQ
CMOS3.3-5
Device DMA Request: This input signal is directly
driven from the DRQ signals on the PATA connector. It
is asserted by the PATA device to request a data
transfer, and used in conjunction with the PCI bus
master PATA function and are not associated with any
AT compatible DMA channel. There is an internal
13.3 kΩ pull-down on this pin.
I
Core
CMOS3.3-5
I/O Channel Ready (PIO): This signal will keep the
strobe active (PATA_DIOR# on reads, PATA_DIOW# on
writes) longer than the minimum width. It adds wait
states to PIO transfers.
I
PATA_IORDY
PATA_IDEIRQ
Core
Core
CMOS3.3-5
I
IDE Interrupt: Input from the PATA device indicating
request for an interrupt. Tied internally to IRQ14.
CMOS3.3-5
2.8
Intel® High Definition Audio (Intel® HD Audio)
Interface
Table 13.
Intel® High Definition Audio (Intel® HD Audio) Interface (Sheet 1 of 2)
Power
Signal Name
Type
Description
Well
O
Intel HD Audio Reset: This signal is the reset to
external codec(s)
HDA_RST#
Core
CMOS_HDA
Intel HD Audio Sync: This signal is an 48-kHz fixed
rate sample sync to the codec(s). It is also used to
encode the stream number.
O
HDA_SYNC
HDA_CLK
Core
Core
CMOS_HDA
Intel HD Audio Clock (Output): This signal is a
24.000-MHz serial data clock generated by the Intel
High Definition Audio (Intel HD Audio) controller. This
signal contains an integrated pull-down resistor so
that it does not float when an Intel HD Audio codec
(or no codec) is connected.
O
CMOS_HDA
Intel HD Audio Serial Data Out: This signal is a
serial TDM data output to the codec(s). The serial
output is double-pumped for a bit rate of 48 MB/s for
HD Audio.
O
HDA_SDO
Core
CMOS_HDA
Datasheet Addendum
Document number: 321422-001
27
Signal Description
Table 13.
Intel® High Definition Audio (Intel® HD Audio) Interface (Sheet 2 of 2)
Power
Well
Signal Name
Type
Description
Intel® HD Audio Serial Data In: These serial
inputs are single-pumped for a bit rate of 24 MB/s.
They have integrated pull-down resistors that are
always enabled.
I
HDA_SDI[1:0]
Core
Core
Core
CMOS_HDA
Intel HD Audio Dock Enable: This active low signal
controls the external Intel HD Audio docking isolation
logic. When deasserted, the external docking switch
is in isolate mode. When asserted, the external
docking switch electrically connects the Intel HD
Audio dock signals to the corresponding Intel® SCH
signals.
O
HDA_DOCKEN#
HDA_DOCKRST#
CMOS_HDA
Intel HD Audio Dock Reset: This signal is a
dedicated reset signal for the codec(s) in the docking
station. It works similar to, but independent of, the
normal HDA_RST# signal.
O
CMOS_HDA
2.9
LPC Interface
Table 14.
LPC Interface
Power
Well
Signal Name
Type
Description
I/O
CMOS3.3
LPC Address/Data: Multiplexed Command, Address,
Data
LPC_AD[3:0]
LPC_FRAME#
LPC_SERIRQ
Core
Core
Core
O
LPC Frame: This signal indicates the start of an LPC/
FHW cycle.
CMOS3.3
I/O
CMOS3.3
Serial Interrupt Request: This signal conveys the
serial interrupt protocol.
Clock Run: This signal gates the operation of the
LPC_CLKOUTx. Once an interrupt sequence has
started, LPC_CLKRUN# should remain asserted to
allow the LPC_CLKOUTx to run.
I/O
CMOS3.3
LPC_CLKRUN#
Core
Core
LPC Clock: These signals are the clocks driven by the
Intel® SCH to LPC devices. Each clock can support up
to two loads.
O
LPC_CLKOUT[2:0]
CMOS3.3
Note: Primary boot device such (behind SMC) should
be connected to LPC_CLKOUT[0]
Datasheet Addendum
Document number: 321422-001
28
Signal Description
2.10
SMBus Interface
Table 15.
SMBus Interface
Signal Name
Power
Well
Type
Description
I/O
CMOS3.3
_OD
SMBus Data: This signal is the SMBus data pin. An
external pull-up resistor is required.
SMB_DATA
SMB_CLK
Core
Core
Core
I/O
CMOS3.3
_OD
SMBus Clock: This signal is the SMBus clock pin. An
external pull-up resistor is required.
I
SMBus Alert: This signal can be used to wake the
system, generate an interrupt, or generate an SMI#.
SMB_ALERT#
CMOS3.3
_OD
Datasheet Addendum
Document number: 321422-001
29
Signal Description
2.11
Power Management Interface
Table 16.
Power Management Interface (Sheet 1 of 2)
Power
Signal Name
Type
Description
Well
Thermal Alarm: This signal is an active low signal
generated by external hardware to generate an SMI
or SCI.
I
THRM#
Core
CMOS3.3
I
System Reset: This signal forces a reset after being
de-bounced. This signal is powered by VCCSM.
RESET#
PWROK
DDR
RTC
CMOS3.3
Power OK: When asserted, PWROK is an indication
to the Intel® SCH that core power is stable. PWROK
can be driven asynchronously.
I
CMOS3.3
Resume Well Reset: This signal is used for resetting
the resume well. An external RC circuit is required to
ensure that the resume well power is valid prior to
RSMRST# going high.
I
RSMRST#
RTC
CMOS3.3
RTC Well Reset: This signal is normally held high (to
VCC_RTC), but can be driven low on the motherboard
to test the RTC power well and reset some bits in the
RTC well registers that are otherwise not reset by
SLPMODE or RSMRST#. An external RC circuit on the
RTCRST# signal creates a time delay such that
RTCRST# will go high some time after the battery
voltage is valid. This allows the Intel® SCH to detect
when a new battery has been installed. The RTCRST#
input must always be high when other non-RTC power
planes are on.
I
RTCRST#
RTC
CMOS3.3
This signal is in the RTC power well.
Suspend Clock: This signal is an output of the RTC
generator circuit (32.768 kHz). SUSCLK can have a
duty cycle from 30% to 70%.
O
SUSCLK
WAKE#
Sus
Sus
CMOS3.3
I
PCI Express* Wake Event: This signal indicates a
PCI Express port wants to wake the system.
CMOS3.3
Stop the CPU Clock: This signal is used to support
the C3 state. Asserting this signal halts the clocks to
the processor by controlling the enable clock chip.
O
STPCPU#
Core
CMOS3.3
Deeper Sleep Voltage Regulator: This signal is
asserted by the Intel® SCH to the processor’s voltage
regulator. When the signal is high, the voltage
regulator outputs the lower “Deeper Sleep” voltage.
When the signal is low (default), the voltage regulator
outputs the higher “Normal” voltage.
O
DPRSLPVR
SLPIOVR#
Core
Core
CMOS3.3
This signal is in the core I/O plane and has a standard
CMOS output (not open drain).
Sleep I/O Voltage Regulator Disable: The
SLPIOVR# can be connected to an external VR and be
used to control power supplied to the processor’s I/O
rail during the C6 state.
O
CMOS3.3
Datasheet Addendum
Document number: 321422-001
30
Signal Description
Table 16.
Power Management Interface (Sheet 2 of 2)
Power
Well
Signal Name
Type
Description
Sleep Mode: SLPMODE determines which sleep state
is entered. When SLPMODE is high, S3 will be chosen.
When SLPMODE is low, S4/S5 will be the selected
sleep mode.
O
SLPMODE
Sus
Sus
CMOS3.3
Reset Warning: Asserting the RSTWARN signal
forces the Intel® SCH to enter a sleep state or begin
to power down. A system management controller
might do so after an external event, such as pressing
of the power button or occurrence of a thermal event.
I
RSTWARN
SLPRDY#
CMOS3.3
Sleep Ready: The Intel® SCH will drive the
SLPRDY# signal low to indicate to the system
management controller that the system controller
hub is awake and able to placed into a sleep state.
Deassertion of this signal indicates that a wake is
being requested from a system device.
O
Sus
CMOS3.3
Reset Ready: Assertion of the RSTRDY# signal
indicates to the system management controller that it
is ready to be placed into a low power state. During a
transition from S0 to S3/4/5 sleep states, the Intel®
SCH asserts RSTRDY# and CPURST# after detecting
assertion of the RSTWARN signal from the external
system management controller.
O
RSTRDY#
GPE#
Sus
Sus
CMOS3.3
General Purpose Event: GPE# is asserted by an
external device (typically, the system management
controller) to log an event in the Intel® SCH ACPI
space and cause an SCI (if enabled).
I
CMOS3.3
_OD
2.12
Real Time Clock Interface
Table 17.
Real Time Clock Interface
Power
Signal Name
Type
Description
Well
Crystal Input 1: This signal is connected to the
32.768-kHz crystal. If no external crystal is used, then
RTC_X1 can be driven with the desired clock rate.
Special
A
RTC_X1
RTC
Crystal Output 2: This signal is connected to the
32.768-kHz crystal. If no external crystal is used, then
RTC_X2 should be left floating.
Special
A
RTC_X2
RTC
Datasheet Addendum
Document number: 321422-001
31
Signal Description
2.13
JTAG Interface
The JTAG interface is accessible only after PWROK is asserted.
Table 18.
JTAG Interface
Power
Signal Name
Type
Description
Well
JTAG Test Clock: TCK is a clock input used to drive
Test Access Port (TAP) state machine during test and
debugging. This input may change asynchronous to the
host clock.
I
TCK
Sus
CMOS
I
JTAG Test Data In: TDI is used to serially shift data
and instructions into the TAP.
TDI
Sus
Sus
Sus
Sus
CMOS
O
JTAG Test Data Out: TDO is used to serially shift data
out of the device.
TDO
TMS
CMOS_OD
I
Test Mode Select: This signal is used to control the
state of the TAP controller.
CMOS
I
Test Reset: This signal resets the controller logic. It
should be pulled down unless TCK is active.
TRST#
CMOS
2.14
Miscellaneous Signals and Clocks
Table 19.
Miscellaneous Signals and Clocks (Sheet 1 of 2)
Power
Signal Name
Type
Description
Well
DA_REFCLKINP/
DA_REFCLKINN
I
Display PLLA CLK Differential Pair: 96 MHz, no
SSC support.
Core
DB_REFCLKINPSSC/
DB_REFCLKINNSSC
I
Display PLLB CLK Differential Pair: display PLL
differential clock pair for SSC support.
Core
Core
O
Clock Required: The SCH will not assert CLKREQ#
to enable a power management mode to the clock
chip.
CLKREQ#
CMOS3.3
_OD
Oscillator Clock: This signal is used for 8254 timers
and HPETs. It runs at 14.31818 MHz. This clock
stops (and should be low) during S3, S4, and S5
states. CLK14 must be accurate to within 500 ppm
over 100 µs (and longer periods) to meet HPET
accuracy requirements.
I
CLK14
Core
RTC
CMOS3.3
Internal VRM Enable: This signal is used to enable
or disable the integrated 1.5-V Voltage Regulators
for the Suspend and Auxiliary wells on the Intel®
SCH. When connected to VSS, the VRMs are
disabled; when connected to the RTC power well, the
VRMs are enabled. This signal is in the RTC well. It is
not latched and must remain valid for the VRMs to
behave properly.
I
INTVRMEN
CMOS3.3
Datasheet Addendum
Document number: 321422-001
32
Signal Description
Table 19.
Miscellaneous Signals and Clocks (Sheet 2 of 2)
Power
Well
Signal Name
Type
Description
Speaker: The SPKR signal is the output of counter 2
and is internally ANDed with Port 61h bit 1 to
provide Speaker Data Enable. This signal drives an
external speaker driver device, which in turn drives
the system speaker. Upon SLPMODE, its output state
is 0.
O
SPKR
Core
Core
CMOS3.3
System Management Interrupt: This signal is
generated by the external system management
controller.
I
SMI#
CMOS3.3
I
EXTTS0#
Core
Core
External Thermal Sensor 0 Event:
CMOS3.3
I
External Thermal Sensor 1 Event: EXTTS1# is
multiplexed with GPIO9.
EXTTS1#/GPIO9
CMOS3.3
Host Bus Speed Select: At the deassertion of
RESET#, the value sampled on BSEL2 determines
the expected frequency of the bus. Refer to Table 22
for more details.
I
BSEL2
Core
Core
CMOS
Configuration: Strap pins used to configure the
graphics/display clock frequency. Refer to Table 22
for more details.
I
CFG[1:0]
CMOS
2.15
General Purpose I/O
Table 20.
General Purpose I/O
Power
Signal Name
Type
Description
Well
General Purpose I/O #9 / External Thermal
Sensor 1: This GPIO can function as a second external
thermal sensor input.
I/O
CMOS3.3
GPIO9/EXTTS1#
Core
General Purpose I/O #8 / Processor Hot: Defaults
to a GPIO.
I/O
CMOS3.3
/
GPIO8/
PROCHOT#
Core
Core
Sus
As PROCHOT#, this signal can function as an Open-
Drain output to the CPU or SMC to signify a processor
thermal event.
OD
I/O
CMOS3.3
General Purpose I/O: These signals are powered off
GPIO[6:0]
of the core well power plane within the Intel® SCH.
Resume Well General Purpose I/O #3/USB Client
Connect: This GPIO can function as an input signifying
connection to an external USB host.
GPIOSUS3/
USBCC
I/O
CMOS3.3
Note: If a USB Client is enabled in the system, then
GPIOSUS3 cannot be used as a general purpose I/O.
General Purpose I/O: These signals are powered from
the suspend well power plane within the Intel® SCH.
They are accessible during the S3 sleep state.
I/O
CMOS3.3
GPIOSUS[2:0]
Sus
Datasheet Addendum
Document number: 321422-001
33
Signal Description
2.16
Power and Ground Signals
Table 21.
Power and Ground Signals
Nominal
Voltage
Interface
Ball Name
Description
VCC
VSS
VTT
1.05
0
Core supply
Ground
Common
1.05
1.5
1.5
Used for FSB input and output devices
Analog Power Supply
Host
VCCAHPLL
VCCDHPLL
Digital Power Supply
1.8
1.5
Driver and Receiver supply
DDR2
VCCSM
Configurable for 1.8-V/1.5-V operation
Dedicated LVDS supply (must be supplied
regardless of LVDS usage).
VCCLVDS
VCCSDVO
1.5
1.5
Dedicated SDVO supply (must be supplied
regardless of SDVO usage).
SDVO/
PCIe/
LVDS
VCCPCIE
1.5
1.5
Dedicated PCIe analog/digital supply.
PCIe PLL.
VCCAPCIEPLL
Band Gap (needs to be enabled for PCIe,
SDVO or LVDS).
VCCAPCIEBG
VSSAPCIEBG
3.3
0
PCIe Band Gap VSS.
Display PLL A power supply (digital and
analog) Must be powered even if DPLLA isn’t
used.
VCCADPLLA
VCCADPLLB
1.5
1.5
Display PLL
Display PLL B power supply (digital and
analog) Must be powered even if DPLLB isn’t
used.
VCC15
1.5
3.3/1.5
3.3
Used for I/O digital logic
Intel® High
Definition
Audio
VCCHDA
VCC33
Configurable for 3.3-V or 1.5-V operation
Used for some internal 3.3-V circuits
Used for I/O digital logic
VCC15
1.5
SDIO/MMC/
CMOS/LPC/
PATA
VCC33
3.3
Used for I/O analog driver
VCC5REF
5
Used for 5-V tolerance on core group inputs
USB PLL Supply. Must be powered even if
USB is not used
VCCAUSBPLL
1.5
VCC15USB
1.5
3.3
3.3
0
Power for USB Logic and Analogs.
USB 3.3-V Supply
VCCP33USBSUS
VCCAUSBBGSUS
VSSAUSBBGSUS
VCC5REFSUS
VCC33SUS
USB
USB Band Gap
USB Band Gap VSS
5
5-V supply in suspend power well
3.3-V suspend Power Supply
Used for Real Time Clock
3.3
3.3
CMOS
Suspend
VCC33RTC
Datasheet Addendum
Document number: 321422-001
34
Signal Description
2.17
Functional Straps
The following signals are used to configure certain Intel® SCH features. All strap signals
are in the core power well. They are sampled at the rising edge of PWROK and then
revert later to their normal usage. Straps should be driven to the desired state at least
four LPC (PCI) clocks prior to the rising edge of PWROK.
Table 22.
Functional Strap Definitions
Signal Name
Strap Function
Comments
BSEL2: Selects the frequency of the host interface
and DDR interface. Normal system configuration will
have this signal connected to the processor’s BSEL2
signal and will not require external pull-up/pull-
down resistors.
FSB/DDR Frequency
Select
CFG[1:0]: Selects the frequency of the internal
graphics device.
BSEL2 and
CFG[1:0]
Graphics Frequency
Select
BSEL2
CFG1
CFG0
FSB Freq
GFX Freq
1
0
0
0
0
1
100 MHz
133 MHz
200 MHz
200 MHz
All other combinations are reserved
Selects the starting address that the CMC will use to
start fetching code (GPIO3 is the most significant).
GPIO3
GPIO0
CMC Base Address
CMC (Chipset
Microcode) Base
Address
GPIO3
GPIO0
0
0
0
1
FFFB0000h
FFFC0000h
FFFD0000h
(default)
1
1
0
1
FFFE0000h
Selects the drive strength of the LPC_CLKOUT0
clock.
LPC_CLKOUT[0]
Buffer Strength
RESERVED1
XOR_TEST
0 = 1 Load driver strength
1 = 2 Load driver strength
Enables XOR chain mode
XOR Chain Enable
0 = XOR mode enable
1 = XOR mode disable (default)
Datasheet Addendum
Document number: 321422-001
35
Pin States
3
Pin States
This chapter describes the states of each Intel® SCH signal in and around reset. It also
documents what signals have internal pull-up/pull-down/series termination resistors
and their values.
3.1
Pin Reset States
Table 23.
Reset State Definitions
Signal State
Description
The Intel® SCH places this output in a high-impedance state. For I/O's,
external drivers are not expected.
High-Z
The state of the input (driven or tri-stated) does not effect the Intel® SCH. For
I/O it is assumed the output buffer is in a high-impedance state.
Don’t Care
VOH
VOL
The Intel® SCH drives this signal high
The Intel® SCH drives this signal low
The Intel® SCH drives this signal to a level defined by internal function
configuration
VOX-known
VOX-unknown
VIH
The Intel® SCH drives this signal, but to an indeterminate value
The Intel® SCH expects/requires the signal to be driven high
The Intel® SCH expects/requires the signal to be driven low
This signal is pulled high by a pull-up resistor (internal or external)
This signal is pulled low by a pull-down resistor (internal or external)
VIL
pull-up
pull-down
The Intel® SCH expects the signal to be driven by an external source, but the
exact electrical level of that input is unknown.
VIX-unknown
Running
Off
The clock is toggling or signal is transitioning because the function has not
stopped.
The power plane for this signal is powered down. The Intel® SCH does not
drive outputs and inputs should not be driven to the Intel® SCH.
Datasheet Addendum
Document number: 321422-001
36
Pin States
Table 24.
Intel® SCH Reset State (Sheet 1 of 5)
Signal Name
Direction
Reset
Post-Reset
S3
S4/S5
Host Interface
H_A[31:3]#
H_D[63:0]#
H_ADS#
I/O
I/O
I/O
I/O
O
VOH
VOH
VOH
VOH
VOH
VOH
VOH
VOH
VOH
VOH
VOH
VIH
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
VOL
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
H_BNR#
H_BPRI#
H_DBSY#
I/O
I/O
I/O
O
H_DEFER#
H_DRDY#
H_DPWR#
H_HIT#
I/O
I/O
I
pull-up
pull-up
pull-up
pull-up
VOH
H_HITM#
H_LOCK#
H_REQ[4:0]#
H_CPUSLP#
H_TRDY#
I/O
O
VOH
VOH
VOH
VOH
VOL
VIL
O
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
H_RS[2:0]#
H_CPURST#
H_BREQ0#
H_DINV[3:0]#
H_ADSTB[1:0]#
O
O
I/O
I/O
I/O
VOH
VOH
H_DSTBP[3:0]#,
H_DSTBN[3:0]#
I/O
VOH
pull-up
Off
Off
H_THERMTRIP
H_PBE#
I
I
VIX-unknown
VIH
pull-up
pull-up
pull-up
VOL
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
H_INIT#
O
VOX-unknown
VOL
H_INTR
O
H_NMI
O
VOL
VOL
H_SMI#
O
VOH
VOH
H_STPCLK#
H_CLKINP, H_CLKINN
H_RCOMPO
H_GVREF
O
VOH
VOH
I
Running
High-Z
Running
High-Z
I/O-A
I-A
I-A
I-A
O
VIX-unknown
VIX-unknown
VIX-unknown
VOH
VIX-unknown
VIX-unknown
VIX-unknown
VOH
H_GCVREF
H_SWING
H_DPSLP#
H_CPUPWRGD
O
VOL
VOL
Datasheet Addendum
Document number: 321422-001
37
Pin States
Table 24.
Intel® SCH Reset State (Sheet 2 of 5)
Signal Name
H_DPRSTP#
System Memory Interface
Direction
Reset
Post-Reset
S3
S4/S5
O
VOH
VOH
Off
Off
SM_DQ[63:0]
SM_DQS[7:0]
SM_MA[14:0]
SM_BS[2:0]
SM_RAS#
I/O
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
VOL
High-Z
High-Z
VOL
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
I/O
O
Off
O
VOL
Off
O
VOH
Off
SM_CAS#
O
VOH
Off
SM_WE#
O
VOH
Off
SM_RCEVENIN#
SM_RCVENOUT#
SM_CK[1:0]
SM_CK[1:0]#
SM_CS[1:0]#
SM_CKE[1:0]
SM_VREF
I
High-Z
High-Z
VOH
Off
O
Off
O
Off
O
VOL
Off
O
VOH
Off
O
VOL
VOL
Don't Care
High-Z
I-A
I-A
VIX-unknown
High-Z
VIX-unknown
High-Z
SM_RCOMP
LVDS
LA_DATAP[3:0],
LA_DATAN[3:0]
O
O
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
Off
LA_CLKP/N
SDVO
SDVOB_GREEN+,
SDVOB_GREEN-
O
O
O
O
I
pull-up
pull-up
High-Z
High-Z
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
SDVOB_BLUE+,
SDVOB_BLUE-
SDVOB_RED+,
SDVOB_RED-
pull-up
High-Z
SDVOB_CLK+,
SDVOB_CLK-
pull-up
High-Z
SDVOB_TVCLKIN+,
SDVOB_TVCLKIN-
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
SDVO_INT+,
SDVO_INT-
I
SDVO_STALL+,
SDVO_STALL-
I
SDVO_CTRLCLK
SDVO_CTRLDATA
I/O
I/O
pull-up
pull-up
High-Z
High-Z
Off
Off
Off
Off
Datasheet Addendum
Document number: 321422-001
38
Pin States
Table 24.
Intel® SCH Reset State (Sheet 3 of 5)
Signal Name
DDC
Direction
Reset
Post-Reset
S3
S4/S5
L_DDC_CLK
L_DDC_DATA
L_CTLCLKA / B
L_VDDEN
I/O
I/O
I/O
O
pull-up
pull-up
pull-up
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
L_BKLTEN
O
L_BKLTCTL
O
USB
USB_DP[7:0]
USB_DN[7:0]
I/O
VOL
VOL
VOX-unknown
Off
USB_OC[7:0]#
USB_RBIASP
USB_RBIASN
USB_CLK48
I
VIX-unknown
High-Z
VIX-unknown VIX-unknown
Off
Off
Off
Off
I-A
I-A
I
High-Z
High-Z
High-Z
High-Z
Off
High-Z
Don't care
don't care
PCI Express*
CLKREQ#
O
O
O
I
VOX
pull-up
VOX
VOL
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
PCIE_PETp[2:1]
PCIE_PETn[2:1]
PCIE_PERp[2:1]
PCIE_PERn[2:1]
VOH
VOH
Don't care
Don't care
Don't care
Don't care
I
PCIE_CLKINP,
PCIE_CLKINN
I
Don't care
High-Z
Don't care
High-Z
Off
Off
Off
Off
PCIE_ICOMPO,
PCIE_ICOMPI
I/O
SDIO/MMC
SD0_DATA[3:0]
SD1_DATA[3:0]
SD2_DATA[7:0]
SD[2:0]_CMD
SD[2:0]_CLK
SD[2:0]_WP
I/O
I/O
I/O
I/O
O
pull-up
pull-up
pull-up
pull-up
VOL
High-Z
High-Z
High-Z
High-Z
VOL
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
I/O
I/O
O
Don't care
Don't care
VOL
Don't care
Don't care
High-Z
High-Z
SD[2:0]_CD#
SD[2:0]_LED
SD[2:0]_PWR#
O
VOL
Datasheet Addendum
Document number: 321422-001
39
Pin States
Table 24.
Intel® SCH Reset State (Sheet 4 of 5)
Signal Name
PATA
Direction
Reset
Post-Reset
S3
S4/S5
PATA_DCS1#
PATA_DCS3#
O
O
VOH
VOH
VOH
VOH
Off
Off
Off
Off
VOX-
unknown
PATA_DA[2:0]
O
VOX-unknown
Off
Off
PATA_DD[15:0]
PATA_DDREQ
PATA_DDACK#
PATA_DIOR#
PATA_DIOW#
PATA_IORDY
PATA_IDEIRQ
I/O
I
High-Z
VIL
High-Z
VIL
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
O
O
O
I
VOH
VOH
VOH
VIH
VOH
VOH
VOH
VIH
I
VIL
VIL
Intel® High Definition Audio
HDA_RST#
O
O
O
O
I
VOL
High-Z
High-Z
High-Z
Don't care
VOH
VOL
High-Z
VOL
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
HDA_SYNC
HDA_CLK
HDA_SDO
High-Z
Don't care
VOH
HDA_SDI[1:0]
HDA_DOCKEN#
HDA_DOCKRST#
O
O
VOH
VOH
LPC
LPC_LAD[3:0]
LPC_FRAME#
LPC_SERIRQ
I/O
O
High-Z
VOH
High-Z
VOH
Off
VOH
Off
Off
Off
Off
Off
Off
I/O
O
High-Z
VOL
High-Z
VOL
LPC_CLKOUT[2:0]
LPC_CLKRUN#
VOL
VOH
I/O
VOH
VOH
SMBus
SMB_DATA
SMB_CLK
I/O
I/O
I
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
Off
Off
Off
SMB_ALERT#
Power Management
THRM#
I
I
VIX-unknown
VIL
VIX-unknown
VIH
Off
VIL
Off
Off
RESET#
PWROK
I
VIX-unknown
VIX-unknown
VIX-unknown
Running
VIL
VIL
VIL
VIH
VIH
Off
RSMRST#
RTCRST#
SUSCLK
I
VIH
VIH
I
VIH
VIH
O
Running
Running
Datasheet Addendum
Document number: 321422-001
40
Pin States
Table 24.
Intel® SCH Reset State (Sheet 5 of 5)
Signal Name
WAKE#
Direction
Reset
Post-Reset
S3
S4/S5
I
O
O
O
I
VIX-unknown
VOH
VIX-unknown VIX-unknown
Off
Off
Off
Off
Off
Off
Off
Off
Off
STPCPU#
DPRSLPVR
SLPMODE
RSTWARN
SLPRDY#
RSTRDY#
GPE#
VOH
VOL
VOL
VIH
Off
Off
VOL
VOL
VOH
VIH
VOL
VOL
VIH
O
O
I
VOH
VOH
VOH
VOH
VIX-unknown
High-Z
VIX-unknown VIX-unknown
SLPIOVR#
I/O
High-Z
Off
Real Time Clock
RTC_X1
RTC_X2
I-A
I-A
Running
Running
Running
Running
Running
Running
Running
Running
JTAG
TCK
I
I
pull-up
pull-up
pull-up
High-Z
pull-up
pull-up
pull-up
pull-up
High-Z
pull-up
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
TMS
TDI
I
TDO
TRST#
O
I
Miscellaneous
BSEL2
I
I
VIX-unknown
VIX-unknown
Running
VIH
VIX-unknown
VIX-unknown
Running
VIH
Off
Off
Off
Off
Off
VIH
Off
Off
Off
CFG[1:0]
CLK14
I
Off
INTVRMEN
SPKR
I
VIH
VOL
Off
O
I
VOL
VOL
SMI#
VIX-unknown
X
VIX-unknown
X
EXTTS
I
Off
GPIO
GPIO[6:0], GPIO[9:8]
GPIOSUS[3:0]
I/O
I/O
High-Z
High-Z
High-Z
High-Z
Off
Off
Off
VIX-unknown
Datasheet Addendum
Document number: 321422-001
41
Pin States
3.2
Integrated Termination Resistors
Table 25.
Intel® SCH Integrated Termination Resistors (Sheet 1 of 2)
Resistor
Type
Nominal
Value
Signal
Tolerance
GPIO3
pull-up
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-up
22 kΩ
22 kΩ
22 kΩ
20 kΩ
22 kΩ
22 kΩ
22 kΩ
22 kΩ
50 Ω
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
GPIO0
HDA_CLK
HDA_DOCKRST#
HDA_RST#
HDA_SDI[1:0]
HDA_SDO
HDA_SYNC
LA_CLKN, LA_CLK_P
LA_DATAN[3:0], LA_DATAP[3:0]
LPC_LAD[3:0]
pull-up
50 Ω
pull-up
50 kΩ
33 Ω
PATA_DA[2:0]
Series
PATA_DCS1#
Series
33 Ω
PATA_DCS3#
Series
33 Ω
PATA_DD[16:0]
PATA_DD7
Series
33 Ω
pull-down
Series
13.3 kΩ
33 Ω
PATA_DDACK#
PATA_DDREQ
Series
33 Ω
PATA_DDREQ
pull-down
Series
13.3 kΩ
33 Ω
PATA_DIOR#
PATA_DIOW#
Series
33 Ω
PATA_IDEIRQ
Series
33 Ω
PATA_IORDY
Series
33 Ω
PCIE_PERn[2:1], PCIE_PERp[2:1]
PCIE_PETn[2:1], PCIE_PETp[2:1]
RESERVED1
pull-down
pull-up
50 Ω
50 Ω
pull-up
300 kΩ
50 kΩ
60 kΩ
RESET#1
pull-down
pull-up
SD[2:0]_PWR#
SD2_DATA[7:0]
pull-up
75 kΩ
±30%
SD[1,0]_DATA[3:0]
SDVOB_RED, SDVOB_RED#
SDVOB_BLUE, SDVOB_BLUE#
SDVOB_GREEN, SDVOB_GREEN#
SDVOB_CLK, SDVOB_CLK#
SDVOB_CLK#
pull-up
pull-up
pull-up
pull-up
pull-up
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
±20%
±20%
±20%
±20%
±20%
Datasheet Addendum
Document number: 321422-001
42
Pin States
Table 25.
Intel® SCH Integrated Termination Resistors (Sheet 2 of 2)
Resistor
Type
Nominal
Value
Signal
Tolerance
SDVOB_INT, SDVOB_INT#
pull-down
pull-down
pull-down
pull-down
pull-up
50 Ω
50 Ω
±20%
±20%
±20%
±20%
±40%
±40%
±40%
±40%
±20%
±20%
SDVOB_STALL, SDVOB_STALL#
SDVOB_TVCLKIN, SDVOB_TVCLKIN#
50 Ω
STPCPU#
20 kΩ
5 kΩ
TRST#2
TCK2
pull-up
5 kΩ
TMS2
pull-up
5 kΩ
TDI2
pull-up
5 kΩ
USB_DN[7:0]. USB_DP[7:0]
USB_DN2, USB_DP2 (Client mode)
pull-down
pull-up
15 kΩ
1.5 kΩ
NOTES:
1.
The Intel® SCH power-on is a very controlled sequence with several intermediate
transitional states before the true reset is reached (this is a reset state from PWROK
asserted high to RESET# deasserted high). Pin values are not ensured to be at the
specified reset state until all power supplies and input clocks are stable. The 3.3 V I/O pins
may glitch, toggle or float.
2.
Refer to the Intel® System Controller Hub (Intel® SCH) Debug Port Design Guide (DPDG)
External Version Revision 1.0 for more information on pull-up/pull-down requirements.
Datasheet Addendum
Document number: 321422-001
43
Absolute Maximums and Operating Conditions
4
Absolute Maximums and
Operating Conditions
4.1
Absolute Maximums
Table 26 lists the Intel® SCH maximum environmental stress ratings. Functional
operation at the absolute maximum and minimum parameters is neither implied nor
guaranteed.
The voltage on a specific pin shall be denoted as “V” followed by the subscripted name
of that pin. For example:
• VTT refers to the voltage applied to the VTT signal (In the case of power supply
signal names, the second V is not repeated in the subscripted portion.)
• VH_SWING refers to the voltage level of the H_SWING signal.
Caution:
At conditions outside functional operation limits, but within absolute maximum and
minimum ratings, neither functionality nor long-term reliability can be expected. If a
device is returned to conditions within functional operation limits after having been
subjected to conditions outside these limits, but within the absolute maximum and
minimum ratings, the device may be functional, but with its lifetime degraded
depending on exposure to conditions exceeding the functional operation condition
limits. If the component is exposed to conditions exceeding absolute maximum and
minimum ratings, neither functionality nor long-term reliability can be expected.
Moreover, if a device is subjected to these conditions for any length of time then, when
returned to conditions within the functional operating condition limits, it will either not
function, or its reliability will be severely degraded. Although the device contains
protective circuitry to resist damage from electro-static discharge, precautions should
always be taken to avoid high static voltages or electric fields.
Table 26.
Intel® SCH Absolute Maximum Ratings (Sheet 1 of 2)
Description /
Signal Names
Parameter
Min
Max
Unit
Tstorage (short-term)
Storage Temperature1
Storage Temperature1
-55
-5
125
40
ºC
V
Tstorage (sustained exposure)
Voltage on any 3.3-V Pin with respect
to Ground
VCC33
0.5
+
-0.5
-0.5
-0.5
VCC5REF
+
0.5
Voltage on any 5-V Tolerant Pin with
respect to Ground (VCC5REF = 5 V)
V
V
1.05-V Supply Voltage with respect to VCC, VTT, VCCSUSBYP,
VSS
2.1
2.1
VCCSUSUSBBYP
VCCAHPLL, VCCDHPLL,
VCCLVDS, VCCSDVO,
VCCPCIE, VCCAPCIEPLL,
VCCADPLLA, VCCADPLLB,
VCC15, VCC15USB,
1.5 V Supply Voltage with respect to
VSS
-0.5
V
VCC15USBSUSBYP,
VCCAUSBPLL, VCC15SUS,
VCCRTCBYP, VCCHDA2
Datasheet Addendum
Document number: 321422-001
44
Absolute Maximums and Operating Conditions
Table 26.
Intel® SCH Absolute Maximum Ratings (Sheet 2 of 2)
Description /
Signal Names
Parameter
Min
Max
Unit
1.8 V Supply Voltage with respect to
VSS
VCCSM
-0.3
2.3
V
VCCAPCIEBG, VCC33,
VCC33, VCCP33USBSUS,
VCCAUSBBGSUS,
3.3 V Supply Voltage with respect to
VSS
-0.5
-0.5
4.6
5.5
V
V
VCC33SUS, VCC33RTC,
VCCHDA2
5.0 V Supply Voltage with respect to
VSS
VCC5REF, VCC5REFSUS
NOTES:
1.
2.
Refer to Section 6 for more information.
VCCHDA is configurable for 1.5-V or 3.3-V operation. Use the appropriate Maximum Limits for the
selected configuration.
4.2
Thermal Characteristics
The Intel® SCH is designed for operation at junction temperatures between 0 °C and
105 °C for commercial temperature parts, and -40 °C and 110 °C for industrial
temperature rated parts. The thermal resistance of the package is given in Table 27.
Package thermal resistance is the measure of the package’s heat dissipation capability
from die active surface (junction) to a specified reference point (case, board, ambient,
etc.).
Table 27.
Intel® SCH Thermal Characteristics
Signal Name
Parameter
Min
Nom
Max
Units
Notes
Characterization
Juntion-to-top
Ψjt
-
0.8
-
ºC/Watt
1
Die Junction Operating
Temperature for CT
Tdie
Tdie
0
-
-
105
110
ºC
ºC
2, 3
2, 3
Die Junction Operating
Temperature for IT
-40
NOTES:
1.
2.
3.
Determined by analyzes under IVI Boundary test conditions.
Measured at top center of the package.
Functionality is not guaranteed for parts that exceed T
temperature above 105 ºC. Full performance
die
may be affected if the on-die thermal sensor is enabled.
Datasheet Addendum
Document number: 321422-001
45
Absolute Maximums and Operating Conditions
4.3
General Operating Conditions
The voltage on a specific pin shall be denoted as “V” followed by the subscripted name
of that pin. For example:
• VTT refers to the voltage applied to the VTT signal. (In the case of power supply
signal names, the second V is not repeated in the subscripted portion.)
• VH_SWING refers to the voltage level of the H_SWING signal.
• Refer to Table 35 for PLL noise rejection specifications.
Table 28.
Intel® SCH Maximum Power Consumption
Power Plane
Symbol
Maximum Power Consumption
Unit
Notes
S0
S3
S4/S5
Table 31
50m
100u
W
1
NOTES:
1.
This specification applies for worst case scenario per rail. In this context, a cumulative use
of these values will represent a non realistic application.
Datasheet Addendum
Document number: 321422-001
46
DC Characteristics
5
DC Characteristics
5.1
Signal Groups
The signal description includes the type of buffer used for the particular signal.
Table 29.
Intel® SCH Buffer Types
Buffer Type
Description
Assisted Gunning Transceiver Logic Plus. Open Drain interface signals
that require termination. Refer to the AGTL+ I/O Specification for
complete details.
AGTL+
CMOS,
1.05-V CMOS buffer
CMOS Open Drain
CMOS buffers for Intel® HD Audio interface that can be configured for
either 1.5-V or 3.3-V operation.
CMOS_HDA
CMOS1.8
1.8-V CMOS buffer. These buffers can be configured as Stub Series
Termination Logic (SSTL1.8)
CMOS3.3,
3.3-V CMOS buffer
CMOS3.3 Open Drain
CMOS3.3-5
USB
3.3-V CMOS buffer, 5-V tolerant
Compliant with USB1.1 and USB2.0 specifications.
PCI Express* interface signals. These signals are compatible with PCI
Express 1.0a Signaling Environment AC Specifications and are AC
coupled. The buffers are not 3.3-V tolerant. Differential voltage
specification = (|D+ - D-|) * 2 = 1.2 Vmax. Single-ended maximum =
1.5 V. Single-ended minimum = 0 V.
PCIE
SDVO
LVDS
Serial-DVO differential output buffers. These signals are AC coupled.
Low Voltage Differential Signal buffers. These signals should drive
across a 100-Ohm resistor at the receiver when driving.
Analog reference or output. Can be used as a threshold voltage or for
buffer compensation.
Analog
Table 30.
Intel® SCH Signal Group Definitions (Sheet 1 of 2)
Signals
s
Signal
Group
Notes
H_ADS#, H_A[31:3]#, H_ADSTB[1:0]#, H_BNR#, H_BREQ0#, H_D[63:0]#,
H_DBSY#, H_DEFER#, H_DINV[3:0]#, H_DRDY#, H_DSTBN[3:0]#, H_DSTBP[3:0]#,
H_HIT#, H_HITM#, H_REQ[4:0]#, H_BPRI#, H_CPURST#, H_TRDY#, H_RS[2:0]#,
H_DPWR#, H_LOCK#
AGTL+
CMOS
H_THRMTRIP#, H_CPUSLP#, H_PBE#, H_INTR, H_NMI, H_SMI#, TDI, TMS, TRST#,
H_STPCLK#, H_DPSLP#, H_DPRSTP#, H_CPUPWRGD, BSEL2, CFG[1:0], TCK
1
2
CMOS
Open Drain
H_INIT#
CMOS_HDA HDA_RST#, HDA_SYNC, HDA_SDO, HDA_SDI[1:0], HDA_DOCKEN#, HDA_DOCKRST#
Datasheet Addendum
Document number: 321422-001
47
DC Characteristics
Table 30.
Intel® SCH Signal Group Definitions (Sheet 2 of 2)
s
Signal
Group
Signals
Notes
SM_DQ[63:0], SM_DQS[7:0], SM_MA[14:0], SM_BS[2:0], SM_RAS#, SM_CAS#,
SM_WE#, SM_RCVENIN, SM_RCVENOUT, SM_CS[1:0]#, SM_CKE[1:0]
CMOS1.8
LPC_AD[3:0], LPC_FRAME#, LPC_SERIRQ, LPC_CLKRUN#
SD[0:2]_DATA[7:0], SD[0:2]_CMD, SD[0:2]_WP, SD[0:2]_CD#, SD[0:2]_LED,
INTVRMEN, SPKR, SMI#, EXTTS, THRM#, RESET#, PWROK, RSMRST#, RTCRST#,
SUSCLK, WAKE#, STPCPU#, DPRSLPVR, SLPMODE, RSTWARN, SLPRDY#, RSTRDY#,
L_VDDEN, L_BKLTEN, L_BKLTCTL, USB_OC[7:0]#, GPIO[9:8], SLPIOVR#, GPIO[6:0],
GPIOSUS[3:0]
CMOS3.3
CMOSS3.3 CLKREQ#, GPE#, TDO, L_DDC_CLK, L_DDC_DATA, L_CTLA_CLK, L_CTLB_CLK,
Open Drain SDVO_CTRLCLK, SDVO_CTRLDATA, SMB_DATA, SMB_ALERT#
PATA_DD[15:0], PATA_DA[2:0], PATA_DIOR#, PATA_DIOW#, PATA_DDACK#,
CMOS3.3-5
PATA_DCS3#, PATA_DCS1#, PATA_DDREQ, PATA_IORDY, PATA_IDEIRQ
PCIE
PCIE_PETp[2:1], PCIE_PETn[2:1], PCIE_PERp[2:1], PCIE_PERn[2:1]
SDVOB_RED+, SDVOB_RED-, SDVOB_GREEN+, SDVOB_GREEN-, SDVOB_BLUE+,
SDVOB_BLUE-, SDVOB_CLK+, SDVOB_CLK-
SDVO
SDVOB_INT+, SDVOB_INT-, SDVO_TVCLKIN+, SDVO_TVCLKIN-, SDVO_STALL+,
SDVO_STALL-
LVDS
USB
LA_DATAP[3:0], LA_DATAN[3:0], LA_CLKP, LA_CLKN
USB_DP[7:0], USB_DN[7:0]
Analog,
Reference
H_RCOMPO, H_SWING, H_GVREF, H_CGVREF, PCIE_ICOMPO, SM_VREF, SM_RCOMPO,
PCIE_ICOMPI, RTC_X1, RTC_X2, USB_RBIASP, USB_RBIASN
H_CLKINP, H_CLKINN, PCIE_CLKINP, PCIE_CLKINN, USB_CLK48, SMB_CLK,
LPC_CLKOUT[1:0], DA_REFCLKINP, DA_REFCLKINN, DB_REFCLKINPSCC,
DB_REFCLKINNSCC, HDA_CLK, SUSCLK, SD[2:0]_CLK, SM_CK[1:0], SM_CK[1:0]#,
CLK14, RTC_X1, RTC_X2
Clocks
NOTES:
1.
2.
These are 1.05-V buffers powered by VTT (except BSEL and TCK which are powered by VCC).
The Intel® HD Audio interface signals can operate in either 1.5-V or 3.3-V ranges. 3.3 V operation is the
default. The HDA interface can be configured to use the low voltage range by setting the Low Voltage Mode
Enable bit of the HDCTL PCI configuration register (D27:F0, offset 40h, bit 0).
5.2
Power and Current Characteristics
Table 31.
Thermal Design Power
Symbol
Parameter
Max
Unit
Notes
Thermal Design Power
TDP
2.3
W
1
(at 1.05-V Core Voltage)
NOTES:
1.
This spec is the Thermal Design Power and is the estimated maximum possible expected
power generated in a component by a realistic application. It is based on extrapolations in
both hardware and software technology over the life of the component. It does not
represent the expected power generated by a power virus. Studies by Intel indicate that
no application will cause thermally significant power dissipation exceeding this
specification, although it is possible to concoct higher power synthetic workloads that write
Datasheet Addendum
Document number: 321422-001
48
DC Characteristics
but never read. Under realistic read/write conditions, this higher power workload can only
be transient and is accounted in the AC (max) spec.
Table 32.
DC Current Characteristics
Symbol
IVTT
IVCC_105
IVCC_15
Parameter
Signal Names
VTT
Max1,2
Unit Notes
1.05-V VTT Supply Current
1.05-V Core Supply Current
1.5-V Core Supply Current
739
1800
10
mA
mA
mA
3
VCC
4,5
VCC15
1.5-V PCI Express* Supply
Current
VCCPCIE,
VCCPCIEPLL
IVCCPCIE
250
mA
6,7
IVCCLVDS
IVCCSDVO
IVCCPCIEBG
IVCC33
1.5-V LVDS Supply Current
1.5-V SDVO Supply Current
3.3-V PCI Express Band Gap
VCCLVDS
62
73
5
mA
mA
mA
mA
VCCSDVO
VCCPCIEBG
3.3-V HV CMOS Supply Current VCC33
100
VCCAHPLL,
VCCDHPLL
15
42
mA
mA
IVCCHPLL
1.5-V Host PLL Supply Current
1.5-V Display PLLA and PLLB
Supply Current
VCCADPLLA,
VCCADPLLB
48
48
mA
mA
IVCCADPLLA,B
IVCCUSB15
1.5-V USB Core Current
VCCUSBCORE
VCC33USBSUS
322
32
mA
mA
IVCCUSBSUS
3.3-V USB Suspend Current
3.3-V USB Suspend Bandgap
Current
IVCCUSBSUSBG
VCC33USBBGSUS
5
mA
IVCCUSBPLL
IVCCSUS33
DDR2 Interface8
DDR2 System Memory:
1.5-V USB PLL Current
VCCAUSBPLL
VCC33SUS
11
5
mA
mA
3.3-V Suspend Current
IVCCSM
(1.8-V, 533 MTs)
(1.5-V, 533 MTs)
VCCSM
VCCSM
568
473
mA
DDR2 System Memory
Interface (1.8-V) Standby
Supply Current
ISUS_VCCSM
~5
10
mA
µA
10
10
DDR2 System Memory
Interface Reference Voltage
(0.90 V) Supply Current
ISMVREF
DDR2 System Memory
Interface Reference Voltage
(0.90 V) Standby Supply
Current
ISUS_SMVREF
10
20
15
µA
mA
µA
DDR2 System Memory
Interface Resister
Compensation Voltage (1.8 V)
Supply Current
ITTRC
VCCSM
VCCSM
DDR2 System Memory
Interface Resister
Compensation Voltage (1.8 V)
Standby Supply Current
ISUS_TTRC
10
Datasheet Addendum
Document number: 321422-001
49
DC Characteristics
NOTES:
1.
2.
3.
These are pre-silicon estimates, subject to change without notice.
CCMAX is determined on a per-interface basis, and all cannot happen simultaneously.
Can vary from CPU. This estimate does not include sense Amps, as they are on a separate
rail, or CPU-specific signals.
I
4.
5.
6.
7.
8.
Estimate is only for max current coming through the chipset’s supply balls.
Includes maximum leakage.
Rail includes PLL current.
I
CCMAX number includes max current for all signal names listed in the table.
Determined with 2x Intel® SCH DDR2 buffer strength settings into a 50 Ohms to ½ VCCSM
(DDR/DDR2) test load.
9.
Specified at the measurement point into a timing and voltage compliance test load as
shown in Transmitter compliance eye diagram of PCI Express* specification and measured
over any 250 consecutive TX Ul's. Specified at the measurement point and measured over
any 250 consecutive ULS. The test load shown in receiver compliance eye diagram of PCI
Express specification. Should be used as the RX device when taking measurements
Standby refers to system memory in Self Refresh during S3 (STR).
10.
5.3
General DC Characteristics
The voltage on a specific pin shall be denoted as “V” followed by the subscripted name
of that pin. For example:
• VTT refers to the voltage applied to the VTT signal. (In the case of power supply
signal names, the second V is not repeated in the subscripted portion.)
• VH_SWING refers to the voltage level of the H_SWING signal
Table 33.
Operating Condition Power Supply and Reference DC Characteristics
Signal Name
Parameter
Min
Nom
Max
Unit
Power Supply Voltages
VCC
VTT
1.05 V Intel® SCH Core Supply Voltage
1.05 V Host AGTL+ Termination Voltage 0.9975 1.05
0.9975 1.05
1.1025
1.1025
V
V
VCC15
VCCPCIE
VCCSDVO
VCCLVDS
VCC15USB
1.5 V Supply Voltage
1.425
1.425
1.50
1.5
1.575
1.575
V
V
VCCAHPLL
VCCDHPLL
VCCAPCIEPLL
VCCADPLLA
VCCADPLLB
VCCAUSBPLL
Various 1.5 V PLL Supply Voltages
1.8 V DDR2 I/O Supply Voltage
1.5 V DDR2 I/O Supply Voltage
1.7
1.8
1.5
1.9
VCCSM
V
V
V
1.425
1.575
VCC33
VCCPCIEBG
3.3 V Power Supply Voltage
3.135
3.3
3.465
1.5/3.3 V Supply for Intel® High
Definition Audio
1.425
3.135
1.5
3.3
1.575
3.465
VCCHDA
VCC33SUS
VCCP33USBSUS
VCCAUSBBGSUS
3.3 V Suspend-Well Power Supplies
3.135
3.3
3.465
V
Datasheet Addendum
Document number: 321422-001
50
DC Characteristics
Table 33.
Operating Condition Power Supply and Reference DC Characteristics
Signal Name
Parameter
5 V Reference Voltages
Min
4.75
Nom
5.0
Max
5.25
Unit
VCC5REF
VCC5REFSUS
V
V
VCC33RTC
Battery Voltage
2.0
3.3
3.6
Reference Signals
0.3125
0.3125
0.3125
x VTT
H_SWING
H_GVREF
Host Compensation Reference Voltage
Host AGTL+ Reference Voltage
x VTT
1%
–
x VTT
1%
+
V
V
V
2/3 x
2/3 x
2/3 x
VTT
VTT
1%
–
VTT
1%
+
1/2 x
1/2 x
1/2 x
VTT
H_CGVREF
SM_VREF
Host CMOS Reference Voltage
DDR2 Reference Voltage
VTT
1%
–
VTT
1%
+
0.49 x 0.50 x 0.51 x
VCCSM
VCCSM
VCCSM
H_RCOMPO
SM_RCOMPO
PCIE_ICOMPO
PCIE_ICOMPI
USB_RBIASP
USB_RBIASN
Table 34.
Active Signal DC Characteristics (Sheet 1 of 4)
Symbol
AGTL+
Parameter
Min
Nom
Max
Unit Notes
VIL
Input Low Voltage
Input High Voltage
–0.1
0.0
2/3 VTT – 0.1
VTT + 0.1
V
V
VIH
2/3 VTT + 0.1
VTT
VOL
VOH
Output Low Voltage
Output High Voltage
1/3 VTT + 0.1
V
V
VTT – 0.1
VTT
VTTMAX
IOL
Output Low Current
mA
1
2
÷ (1.5 Rttmin
)
ILEAK
CIN
Input Leakage Current
Input Capacitance
20
µA
pF
2
3.5
CMOS, CMOS Open Drain
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
Input Capacitance
–0.1
0.0
½ VTT – 0.1
VTT + 0.1
0.1 x VTT
VTT
V
V
4
4
VIH
½ VTT + 0.7
VTT
VOL
VOH
ILEAK
CIN
V
4
0.9 x VTT
V
4
20
µA
pF
2, 3
1
3.5
Datasheet Addendum
Document number: 321422-001
51
DC Characteristics
Table 34.
Active Signal DC Characteristics (Sheet 2 of 4)
Symbol
Parameter
Min
Nom
Max
Unit Notes
CMOS_HDA
VIL
Input Low Voltage
Input High Voltage
–0.1
0.0
½ VCCHDA – 1
V
V
½ VCCHDA
0.7
+
VIH
VCCHDA VCCHDA + 0.1
0.1 VCCHDA
VOL
Output Low Voltage
Output High Voltage
Input Leakage Current
Input Capacitance
V
V
VOH
ILEAK
CIN
0.9 VCCHDA
20
µA
pF
2
3.5
CMOS1.8
VSM_VREF
– 0.250
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
V
V
VSM_VREF
+ 0.250
VIH
VOL
VOH
VSM_VREF
– 0.250
VSM_VREF
+ 0.250
V
IOL
Output Low Current
Input Leakage Current
Input Capacitance
0.3
1.4
3.4
mA
ILEAK
CIN
µA
pF
5
2.0
CMOS3.3, CMOS3.3 Open Drain
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Input Leakage Current
Input Capacitance
–0.1
0.0
½ V – 1
VCC33 + 0.1
0.1 VCC33
V
V
VIH
VOL
VOH
IOL
IOH
ILEAK
CIN
½ VCC33 + 0.7 VCC33
V
3
3
0.9 VCC33
V
1.5
-0.5 mA
20
mA
mA
µA
pF
3
1
3.5
CMOS3.3–5
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
Input Capacitance
–0.1
0.0
½ VCC33 – 0.1
VCC33 + 0.1
0.1 VCC33
V
V
VIH
½ VCC33 + 0.7 VCC33
VOL
VOH
ILEAK
CIN
V
0.9 VCC33
V
20
µA
pF
1
3.5
USB
Datasheet Addendum
Document number: 321422-001
52
DC Characteristics
Table 34.
Active Signal DC Characteristics (Sheet 3 of 4)
Symbol
Parameter
Min
Nom
Max
Unit Notes
Refer to the Universal Serial Bus (USB) Base Specification, Rev. 2.0.
PCIE
Differential Peak to Peak
Output Voltage
VTX-DIFF P-P
VTX_CM-ACp
ZTX-DIFF-DC
VRX-DIFF p-p
0.400
0.6
20
V
6
6
AC Peak Common Mode
Output Voltage
mV
DC Differential TX
Impedance
80
100
120
1.2
150
Ω
V
Differential Input Peak to
Peak Voltage
0.175
6
AC peak Common Mode
Input Voltage
VRX_CM-ACp
SDVO
mV
Differential Peak to Peak
Output Voltage
VTX-DIFF P-P
0.400
0.6
20
V
6
6
AC Peak Common Mode
Output Voltage
VTX_CM-ACp
ZTX-DIFF-DC
VRX-DIFF p-p
VRX_CM-ACp
mV
DC Differential TX
Impedance
80
100
120
1.2
150
Ω
V
Differential Input Peak to
Peak Voltage
0.175
6
AC peak Common Mode
Input Voltage
mV
LVDS
VOD
Differential Output Voltage
250
0.8
350
450
50
mV
mV
V
Change in VOD between
Complementary Output
States
ΔVOD
VOS
Offset Voltage
1.25
1.375
50
Change in VOS between
Complementary Output
States
ΔVOS
Output Short Circuit
Current
IOs
IOZ
-3.5
-10
Output Tristate Current
±1
±10
Differential Clocks
VSWING Input swing
300
300
mV
mV
7, 8
7, 9,
10, 11
VCROSS
Crossing point
550
Datasheet Addendum
Document number: 321422-001
53
DC Characteristics
Table 34.
Active Signal DC Characteristics (Sheet 4 of 4)
Symbol
Parameter
Min
Nom
Max
Unit Notes
7, 9,
mV
VCROSS_VAR VCROSS Variance
140
10, 12
7, 9,
13
VIH
Maximum input voltage
Minimum input voltage
1.15
V
7, 9,
14
VIL
-0.3
V
NOTES:
1.
2.
3.
Rttmin = 50 Ohm
OL < VPAD < VTT
V
For CMOS Open Drain signals defined in Table 34, VOH, VOL, and ILEAK DC specs are not
applicable due to the pull-up/pull-down resister that is required on the board.
BSEL2, CFG[1:0] and TCK signals reference VCC, not VTT.
4.
5.
6.
At VCCSM = 1.7 V.
Specified at the measurement point into a timing and voltage compliance test load as
shown in Transmitter compliance eye diagram of PCI Express* specification and measured
over any 250 consecutive TX Ul's. Specified at the measurement point and measured over
any 250 consecutive ULS. The test load shown in receiver compliance eye diagram of PCI
Express specification. Should be used as the RX device when taking measurements.
Applicable to the following signals: H_CLKINN/P, PCIE_CLKINN/P,
DB_DREFCLKIN[N,P]SCC, DA_DREFCLKINN/P
7.
8.
Measurement taken from differential waveform.
9.
Measurement taken from single ended waveform.
10.
11.
12.
VCROSS is defined as the voltage where Clock = Clock#.
Only applies to the differential rising edge (i.e., Clock rising and Clock# falling)
The total variation of all VCROSS measurements in any particular system. This is a subset of
V
CROSSMIN /VCROSSmax (VCROSS absolute) allowed. The intent is to limit VCROSS induced
modulation by setting VCROSS_VAR to be smaller than VCROSS absolute.
The max voltage including overshoot.
The min voltage including undershoot.
13.
14.
s
Table 35.
PLL Noise Rejection Specifications
PLL
Noise Rejection Specification
Notes
34 dB(A) attenuation of power supply noise in 1-MHz (f1) to 66-
MHz (f2) range, <0.2 dB gain in pass band and peak to peak noise
should be limited to < 120 mV
VCCAHPLL
VCCDHPLL
VCCAPCIE
peak to peak noise should be limited to < 120 mV
< 0 dB(A) in 0 to 1MHz, 20 dB(A) attenuation of power supply noise
in 1 MHz(f1) to 1.25 GHz(f2) range, <0.2 dB gain in pass band and
peak to peak noise should be limited to < 40 mV
20 dB(A) attenuation of power supply noise in 10-kHz(f1) to
2.5-MHz(f2) range, <0.2 dB gain in pass band and peak to peak
noise should be limited to < 100 mV
VCCADPLLA
20 dB(A) attenuation of power supply noise in 10-kHz(f1) to
2.5-MHz(f2) range, <0.2 dB gain in pass band and peak to peak
noise should be limited to < 100 mV
VCCADPLLB
VCCAUSBPLL
USB PLL
Datasheet Addendum
Document number: 321422-001
54
Storage Conditions Specifications
6
Storage Conditions
Specifications
Environmental storage condition limits define the temperature and relative humidity
limits which the device is exposed to while being stored in a Moisture Barrier Bag. The
specified storage conditions are for component level prior to board attach (see notes
below guideline on post board attach limits).
Table 36 specifies absolute maximum and minimum storage temperature limits which
represent the maximum or minimum device condition beyond which damage, latent or
otherwise, may occur. The table also specifies sustained storage temperature, relative
humidity, and time-duration limits. These limits specify the maximum or minimum
device storage conditions for a sustained period of time. At conditions outside sustained
limits, but within absolute maximum and minimum ratings, quality & reliability may be
affected.
.
Table 36.
Intel® SCH Absolute Maximum Ratings
Description /
Signal Names
Parameter
Min
Max
Unit
The minimum/maximum device storage
temperature beyond which damage
(latent or otherwise) may occur when
subjected to for any length of
time.1,2,3,4,5
Tstorage (short-term)
-55
125
ºC
The minimum/maximum device storage
temperature for a sustained period of
time.1,2,3,4,5
Tstorage (sustained exposure)
-5
-
40
ºC
The maximum device storage relative
humidity for a sustained period of
time.1,2,3,4,5
60%
@24ºC
RHsustained storage
A prolonged or extended period of time;
typically associated with sustained storage
conditions.1,2,3,4,5
Timesustained storage
-
6
months
NOTES:
1.
Storage conditions are applicable to storage environments only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not
affect the long-term reliability of the device. For functional operation, please refer to the processor case
temperature specifications
2.
3.
4.
These ratings apply to the Intel component and do not include the tray or packaging
Failure to adhere to this specification can affect the long-term reliability of the processor.
Non operating storage limits post board attach: Storage condition limits for the component once
attached to the application board are not specified. Intel® does not conduct component level
certification assessments post board attach given the multitude of attach methods, socket types and
board types used by customers. Provided as general guidance only, Intel® board products are specified
and certified to meet the following temperature and humidity limits (Non-Operating Temperature Limit:
-40C to 70C & Humidity: 50% to 90%, non condensing with a maximum wet bulb of 28C)
Device storage temperature qualification methods follow JESD22-A119 (low temp) and JESD22-A103
(high temp) standards.
5.
Datasheet Addendum
Document number: 321422-001
55
Ballout and Package Information
7
Ballout and Package
Information
The Intel® SCH comes in an Flip-Chip Ball Grid Array (FCBGA) package and consists of
a silicon die mounted face down on an organic substrate populated with 1295 solder
balls on the bottom side. Capacitors may be placed in the area surrounding the die.
Because the die-side capacitors are electrically conductive, and only slightly shorter
than the die height, care should be taken to avoid contacting the capacitors with
electrically conductive materials. Doing so may short the capacitors and possibly
damage the device or render it inactive.
The use of an insulating material between the capacitors and any thermal solution
should be considered to prevent capacitor shorting. An exclusion, or keep out zone,
surrounds the die and capacitors, and identifies the contact area for the package. Care
should be taken to avoid contact with the package inside this area.
Unless otherwise specified, interpret the dimensions and tolerances in accordance with
ASME Y14.5-1994. The dimensions are in millimeters. Key package attributes are listed
below:
Dimensions:
• Silicon Process: P861, 6 metal
• Physical Die Size: 10.725 mm x 10.985 mm
• Package parameters: 37.5 mm x 37.5 mm
• Ball Count: 1295
• Package Land/Pitch: 1.016 mm
• Land metal diameter: 375 microns
• Solder resist opening: 321 microns
Tolerances:
• .X - ± 0.1
• .XX - ± 0.05
• Angles - ± 1.0 degrees
Datasheet Addendum
Document number: 321422-001
56
Ballout and Package Information
7.1
Package Diagrams
Figure 3.
Intel® SCH (Side View)
Figure 4.
Intel® SCH Package (Solder Resist Opening)
Datasheet Addendum
Document number: 321422-001
57
Ballout and Package Information
Figure 5.
Intel® SCH (Bottom View)
NOTE: Maximum outgoing package coplanarity not to exceed 8 mils.
Figure 6.
Intel® SCH (Top View)
Datasheet Addendum
Document number: 321422-001
58
Ballout and Package Information
7.2
Reverse Ballout Definition and Signal Location
AT
AR
AP
AN
AM
AL
AK
AJ
VSS
VSS
VSS
VSS
H_D31#
H_DSTBP1#
H_D21#
H_D22#
1
VSS
VSS
VSS
VSS
VSS
VSS
H_D26#
H_D30#
H_D19#
VSS
VSS
VSS
H_DSTBN1#
H_D16#
H_D24#
H_D18#
H_D25#
H_D57#
H_D52#
H_DINV3#
H_D59#
H_D32#
H_D33#
H_D40#
RESERVED5
H_THRMTRIP#
VSS
VSS
VSS
H_D29#
H_D17#
H_D20#
H_D1#
H_D14#
H_D8#
H_D15#
VSS
2
3
VSS
H_DPWR#
VSS
H_D28#
VSS
VSS
VSS
4
H_D50#
H_D53#
H_D48#
H_D60#
H_D54#
H_D39#
H_D36#
H_D43#
H_D47#
H_DSTBP2#
VSS
VSS
VSS
5
H_DSTBN3#
VSS
H_DSTBP3#
VSS
H_D49#
VSS
H_D27#
VSS
H_D23#
VSS
6
7
H_D61#
VSS
H_D55#
VSS
H_D63#
VSS
H_D51#
VSS
H_DINV1#
VSS
8
9
H_D34#
VSS
H_D42#
VSS
H_D56#
VSS
H_D58#
VSS
H_D62#
VSS
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS
H_DINV2#
VSS
H_D44#
VSS
H_D35#
VSS
H_D37#
VSS
H_D45#
VSS
VSS
VSS
H_DSTBN2#
H_TESTIN#
VSS
H_D46#
VSS
H_D41#
H_DPRSTP#
VSS
H_D38#
VSS
RESERVED4
VSS
VSS
VSS
SM_DQ63
SM_DQS7
SM_DQ60
SM_DQS6
SM_DQ48
SM_DQ47
SM_DQ41
SM_DQ34
SM_DQ37
SM_DQ31
SM_DQS3
SM_DQ24
SM_DQ22
SM_DQ17
SM_DQ15
SM_DQ9
SM_DQ2
VSS
SM_DQ59
VSS
SM_DQ58
VSS
SM_DQ62
VSS
VSS
SM_DQ61
VSS
SM_DQ57
VSS
SM_DQ56
VSS
VSS
SM_DQ51
VSS
SM_DQ50
VSS
SM_DQ55
VSS
SM_CK1#
SM_CK1
VSS
SM_DQ54
VSS
SM_DQ53
VSS
SM_DQ49
VSS
SM_DQ52
VSS
SM_DQ43
VSS
SM_DQ42
VSS
SM_DQ46
VSS
SM_DQS5
VSS
SM_DQ45
VSS
RESERVED2
VSS
SM_DQ40
VSS
SM_DQ44
VSS
SM_DQ35
VSS
SM_DQ39
VSS
SM_DQS4
VSS
SM_DQ38
VSS
SM_CAS#
VSS
SM_DQ33
VSS
SM_DQ32
VSS
SM_DQ36
VSS
SM_DQ27
VSS
SM_DQ26
VSS
SM_DQ30
VSS
SM_BS0
VSS
SM_DQ29
VSS
SM_DQ28
VSS
SM_DQ25
VSS
SM_DQ23
VSS
SM_DQ19
VSS
SM_DQ18
VSS
SM_MA3
VSS
SM_DQS2
VSS
SM_DQ21
VSS
SM_DQ20
VSS
SM_DQ16
VSS
SM_DQ11
VSS
SM_DQ10
VSS
SM_MA8
VSS
SM_DQS1
VSS
SM_DQ14
VSS
SM_DQ13
VSS
SM_DQ8
VSS
SM_DQ12
VSS
SM_DQ3
VSS
SM_MA7
VSS
SM_DQ7
VSS
SM_DQS0
VSS
SM_DQ5
VSS
SM_DQ6
VSS
SM_DQ1
VSS
SM_CKE0
VSS
SM_CKE1
VSS
VSS
SM_DQ0
VSS
SM_CK0#
SM_CK0
VSS
VSS
VSS
VSS
SM_DQ4
VSS
VSS
SM_VREF
VSS
VSS
VSS
VSS
VSS
VSS
SM_RCVENIN
Datasheet Addendum
Document number: 321422-001
59
Ballout and Package Information
AH
H_D4#
VSS
AG
AF
H_DSTBN0#
VSS
AE
H_DSTBP0#
H_D6#
AD
H_DBSY#
VSS
AC
H_TRDY#
H_BNR#
H_RS0#
H_ADS#
H_LOCK#
H_RS2#
H_BPRI#
H_CPUSLP#
VSS
AB
H_HITM#
VSS
H_D11#
H_D13#
H_D3#
1
2
VSS
VSS
H_D10#
H_RS1#
H_INIT#
H_INTR
H_STPCLK#
H_NMI
VSS
VSS
3
VSS
H_D9#
VSS
VSS
VSS
4
VSS
H_D2#
VSS
VSS
VSS
5
VSS
H_D0#
VSS
VSS
VSS
6
H_D7#
VSS
H_D5#
H_DINV0#
VSS
H_HIT#
VSS
H_DPSLP#
VSS
7
H_D12#
VSS
8
VSS
VTT
VSS
VTT
VTT
9
VTT
VTT
VTT
VTT
VTT
VTT
VTT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS
VSS
VSS
VSS
VCCDHPLL
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
VCCAHPLL
VSS
VTT
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
VCCSM
VCCSM
VSS
VCCSM
VSS
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
VSS
VSS
VCC
VSS
VSS
VCC
VCCSM
VSS
VCCSM
VSS
VSS
VCC
VSS
VCC
VSS
VSS
VSS
VCC
VCCSM
VCCSM
VSS
VCCSM
VCCSM
VSS
VSS
VCC
VSS
VSS
VCC
VSS
VSS
VCC
VSS
RESERVED3
SM_MA13
SM_CS1#
SM_RAS#
SM_WE#
SM_MA10
SM_MA1
SM_MA5
SM_MA4
SM_MA9
SM_MA6
SM_BS2
SM_MA14
VSS
VSS
VSS
VCC
SM_CS0#
VSS
VSS
VSS
VCC
VSS
VSS
VCC
SM_BS1
VSS
VSS
VSS
VSS
VSS
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VSS
VCCSDVO
VSS
VCCSDVO
VCCSDVO
VCCSDVO
VSS
SM_MA0
VSS
VSS
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VSS
VSS
VSS
SM_MA2
VSS
VSS
VCCPCIE
VSS
VSS
PCIE_PERn2
VSS
SM_MA12
VSS
VSS
PCIE_PERp2
VSS
VSS
PCIE_PETn2
VSS
VCCAPCIEBG
VSS
SM_MA11
VSS
VSS
PCIE_PETp2
VSS
VSSAPCIEBG
VSS
VSS
PCIE_PETp1
VSS
PCIE_PERp1
VSS
VSS
VSS
PCIE_PETn1
VSS
PCIE_PERn1
VSS
SM_RCVENOUT
VSS
VSS
RESET#
VSS
PCIE_ICOMPI
VSS
PCIE_CLKINN
VSS
SM_RCOMPO
PCIE_ICOMPO
PCIE_CLKINP
Datasheet Addendum
Document number: 321422-001
60
Ballout and Package Information
AA
Y
H_REQ0#
VSS
W
H_A16#
H_A13#
H_A10#
H_A12#
H_A14#
H_ADSTB0#
H_A7#
V
H_A15#
VSS
U
H_A4#
T
H_A17#
VSS
H_BREQ0#
H_DEFER#
H_DRDY#
H_A3#
1
H_A9#
2
VSS
VSS
H_REQ2#
H_A21#
H_A26#
H_A19#
H_A25#
H_A18#
VSS
VSS
3
VSS
VSS
VSS
4
H_A8#
VSS
VSS
VSS
5
H_REQ3#
H_A6#
VSS
VSS
VSS
6
H_A5#
VSS
H_A11#
VSS
H_A24#
VSS
7
H_REQ4#
VSS
H_REQ1#
VSS
8
VTT
VTT
VTT
9
VTT
VTT
VTT
VTT
VTT
VTT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS
VTT
VSS
VTT
VSS
VTT
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC15USB
VCC15USB
VSS
VCC15USB
VCC15USB
VCCLVDS
VCCADPLLA
VCCLVDS
VSS
VCC15USB
VCC15USB
RESERVED17
VCCAUSBBGSUS
VCC5REFSUS
RESERVED11
VSS
RESERVED15
VSS
VCC
VSS
VCCSDVO
VCCSDVO
VSS
VSS
RESERVED16
VSSAUSBBGSUS
RESERVED13
VSS
VCCADPLLB
VCCLVDS
VSS
VCCLVDS
VCCAUSBPLL
VCCLVDS
VSS
VCCAPCIEPLL
VSS
SDVOB_INT#
VSS
RESERVED7
VSS
LA_DATAN2
VSS
SDVOB_INT
VSS
RESERVED6
VSS
LA_DATAP2
VSS
SDVOB_GREEN#
VSS
SDVOB_CLK#
VSS
DA_REFCLKINP
VSS
SDVOB_GREEN
VSS
SDVOB_CLK
VSS
DA_REFCLKINN
VSS
SDVOB_RED#
VSS
SDVOB_STALL#
VSS
LA_DATAP0
VSS
SDVOB_RED
VSS
SDVOB_STALL
VSS
LA_DATAN0
VSS
SDVOB_TVCLKIN#
VSS
SDVOB_BLUE#
VSS
LA_DATAN1
VSS
SDVOB_TVCLKIN
SDVOB_BLUE
LA_DATAP1
Datasheet Addendum
Document number: 321422-001
61
Ballout and Package Information
R
P
N
M
L
K
J
H_A27#
H_ADSTB1#
H_A23#
H_A30#
H_A29#
H_A31#
H_A28#
H_A22#
VSS
H_A20#
H_SMI#
VSS
H_CLKINP
H_CLKINN
VSS
1
VSS
H_CPURST#
H_RCOMPO
H_CGVREF
H_GVREF
H_SWING
H_CPUPWRGD
VSS
VSS
VSS
VSS
VSS
VSS
VCC33
VSS
VSS
VSS
2
VSS
3
VSS
VSS
VCC33
VSS
VCC33
VSS
4
VSS
VSS
VCC33
VSS
5
VSS
VSS
VCC33
VSS
VCC33
VSS
6
H_PBE#
VSS
VSS
VCC33
VSS
7
VSS
VCC33
VSS
VCC33
VSS
8
VTT
VSS
VTT
VCC33
VSS
9
VTT
VTT
VTT
VSS
VCC33
VSS
VCC33
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VTT
VSS
VSS
VCC33
VSS
VCC
VSS
VCCHDA
VCC
VCCHDA
VCC
VSS
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VSS
VCC
VCC
VSS
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VCC15
VSS
VSS
VSS
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VSS
RESERVED14
VCCP33USBSUS
RESERVED12
VSS
VSS
VSS
VSS
VSS
VCCP33USBSUS
VSS
VSS
VCC33SUS
VCC33SUS
VCC33SUS
VSS
VCC5REF
VCC33SUS
VSS
VSS
VCCP33USBSUS
VSS
VSS
RESERVED10
VSS
VCC33SUS
VSS
VSS
VSS
VSS
VSS
VSS
GPIOSUS3
VSS
VSS
USB_OC6#
VSS
VSS
USB_OC3#
VSS
VSS
USB_OC0#
VSS
USB_OC1#
VSS
USB_OC7#
VSS
USB_OC2#
VSS
USB_OC4#
VSS
LA_CLKN
VSS
USB_DP0
VSS
USB_DP3
VSS
LA_CLKP
USB_DN0
USB_DN3
DB_REFCLKINPS
SC
VSS
LA_DATAP3
VSS
LA_DATAN3
VSS
VSS
USB_DN1
VSS
USB_DP1
VSS
VSS
USB_DP5
VSS
USB_DN5
VSS
VSS
USB_DP7
VSS
33
34
35
36
USB_RBIASP
VSS
USB_DP2
VSS
USB_DP4
VSS
USB_RBIASN
USB_DN2
USB_DN4
USB_DP6
Datasheet Addendum
Document number: 321422-001
62
Ballout and Package Information
H
G
F
E
D
C
B
A
VSS
VSS
VSS
HDA_CLK
VSS
VSS
VSS
1
2
3
VSS
VSS
VSS
VSS
HDA_SYNC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC33
HDA_DOCKEN#
HDA_DOCKRST
#
VSS
VCC33
VSS
HDA_SDO
VSS
VSS
HDA_SDI0
VSS
HDA_SDI1
VSS
VSS
HDA_RST#
SD0_CD#
VSS
SD0_DATA1
VSS
SD0_CLK
VSS
VSS
4
SD2_PWR#
SD1_CMD
SD1_CD#
5
XOR_TEST
VSS
SD0_DATA3
VSS
SD1_PWR#
VSS
SD1_WP
VSS
6
VCC33
VSS
RESERVED19
SD0_WP
VSS
7
SD2_LED
SD2_DATA3
SD1_DATA1
SD2_DATA0
SD2_CD#
L_CTLB_DATA
GPIO9
SD1_LED
VSS
SD0_LED
VSS
SD1_DATA3
VSS
SD1_DATA0
VSS
SD2_WP
8
VSS
SD2_DATA4
SD2_DATA1
SD2_DATA5
SD2_DATA2
SD0_DATA2
SD1_DATA2
L_CTLA_CLK
CLKREQ#
9
VSS
SD2_CLK
VSS
SD0_DATA0
VSS
SD2_CMD
VSS
VSS
SD2_DATA7
VSS
10
11
12
13
14
15
16
VSS
VSS
VSS
SD2_DATA6
VSS
SD0_CMD
VSS
RESERVED20
VSS
SD0_PWR#
VSS
RESERVED18
VSS
VSS
VSS
CFG0
L_DDCDATA
VSS
BSEL2
SD1_CLK
VSS
RESERVED21
VSS
VSS
L_DDCCLK
STPCPU#
VSS
VSS
VSS
GPIO0
SDVO_CTRLC
LK
L_VDDEN
SMI#
SDVO_CTRLDA
TA
VSS
VSS
L_BKLTEN
L_BKLTCTL
LPC_AD2
LPC_CLKRUN#
SMB_CLK
LPC_CLKOUT0
LPC_AD0
LPC_AD1
LPC_FRAME#
LPC_AD3
VSS
VSS
SMB_ALERT#
VSS
VSS
SLPIOVR#
GPIO8
VSS
CLK14
GPIO3
VSS
VSS
THRM#
GPIO2
VSS
VSS
EXTTS
DPRSLPVR
VSS
GPIO1
RESERVED1
CFG1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VSS
VSS
VSS
VSS
LPC_CLKOUT1
GPIO6
VSS
SMB_DATA
VSS
LPC_SERIRQ
VSS
GPIO4
VSS
SPKR
GPIO5
VSS
VSS
VSS
LPC_CLKOUT2
PATA_DD6
PATA_DD10
PATA_DD3
PATA_DD13
PATA_DD0
PATA_DIOW#
VSS
PATA_DD4
VSS
PATA_DD5
VSS
PATA_DD9
VSS
PATA_DD7
VSS
PATA_DD8
VSS
VSS
VSS
PATA_DD11
VSS
PATA_DD14
VSS
PATA_DD1
VSS
PATA_DD2
VSS
PATA_DD12
VSS
VSS
RESERVED9
VSS
PATA_DA0
RSMRST#
PATA_DCS3#
RESERVED0
GPIOSUS2
PATA_IORDY
VSS
PATA_DIOR#
VSS
PATA_DDREQ
VSS
PATA_DD15
VSS
INTVRMEN
VSS
USB_OC5#
VSS
PATA_DCS1#
VSS
PATA_DA2
VSS
PATA_DA1
VSS
PATA_IDEIRQ PATA_DDACK#
RTCRST#
VSS
VSS
VCC33RTC
RTC_X2
DB_REFCLKI
NNSSC
SLPMODE
PWROK
WAKE#
SUSCLK
VSS
USB_DN7
VSS
TMS
VSS
VSS
TRST#
VSS
GPIOSUS1
VSS
VSS
TDI
VSS
SLPRDY#
RSTWARN
VSS
VSS
RSTRDY#
VSS
RTC_X1
VSS
32
33
34
35
36
TDO
TCK
VSS
GPE#
VSS
VSS
USB_DN6
VSS
VSS
VSS
VSS
VSS
VSS
GPIOSUS0
VSS
USB_CLK48
VSS
VSS
VSS
Datasheet Addendum
Document number: 321422-001
63
Ballout and Package Information
7.3
Pin List by Ball Name
Ball
Ball
Ball Name
H_A20#
Ball Name
H_D14#
Number
Number
Ball
Ball Name
BSEL2
Number
P1
AJ6
D14
F14
A19
D18
A16
U32
T31
H_A21#
U4
H_D15#
H_D16#
H_D17#
H_D18#
H_D19#
H_D2#
AJ8
CFG0
H_A22#
R8
AL3
CFG1
H_A23#
R3
AJ3
CLK14
H_A24#
T7
AL5
CLKREQ#
DA_REFCLKINN
DA_REFCLKINP
H_A25#
U7
AN4
AG5
AJ4
H_A26#
U5
H_A27#
R1
H_D20#
H_D21#
H_D22#
H_D23#
H_D24#
H_D25#
H_D26#
H_D27#
H_D28#
H_D29#
H_D3#
DB_REFCLKINNSSC H31
DB_REFCLKINPSSC J32
H_A28#
R7
AK1
H_A29#
R5
AJ1
DPRSLPVR
EXTTS
B19
B18
D35
F16
A17
C19
D19
D21
B21
A21
E18
E19
G14
G36
E32
F31
J28
W3
V7
H_A3#
AA4
R4
AK6
H_A30#
AL4
GPE#
H_A31#
R6
AL6
GPIO0
H_A4#
U1
AN2
AM6
AP4
GPIO1
H_A5#
Y7
GPIO2
H_A6#
AA7
W7
AA5
U2
GPIO3
H_A7#
AJ2
GPIO4
H_A8#
AG3
AN3
AM1
AL11
AL12
AR10
AN12
AT11
AM12
AM14
AT10
AH1
AL13
AN14
AP10
AT12
AP12
AK12
AP14
AT13
GPIO5
H_A9#
H_D30#
H_D31#
H_D32#
H_D33#
H_D34#
H_D35#
H_D36#
H_D37#
H_D38#
H_D39#
H_D4#
GPIO6
H_ADS#
H_ADSTB0#
H_ADSTB1#
H_BNR#
H_BPRI#
H_BREQ0#
H_CGVREF
H_CLKINN
H_CLKINP
H_CPUPWRGD
H_CPURST#
H_CPUSLP#
H_D0#
AC4
W6
R2
SLPIOVR#
GPIO8
GPIO9
AC2
AC7
AA1
N4
GPIOSUS0
GPIOSUS1
GPIOSUS2
GPIOSUS3
H_A10#
H_A11#
H_A12#
H_A13#
H_A14#
H_A15#
H_A16#
H_A17#
H_A18#
H_A19#
K1
L1
N7
W4
W2
W5
V1
N2
H_D40#
H_D41#
H_D42#
H_D43#
H_D44#
H_D45#
H_D46#
H_D47#
AC8
AG6
AJ5
AE3
AG1
AG8
AG2
H_D1#
W1
T1
H_D10#
H_D11#
U8
H_D12#
H_D13#
U6
Datasheet Addendum for US15WP and US15WPT
64
Ballout and Package Information
Ball
Ball
Ball
Ball Name
Ball Name
H_D48#
Ball Name
H_GVREF
Number
Number
Number
AT7
N5
LA_CLKN
P31
R32
U34
T35
T29
P33
T33
U36
U30
R34
G23
G24
G19
G26
G22
A20
A22
G20
G25
E21
F27
C29
D29
E29
F29
A27
D25
A24
F25
B25
A26
E25
B27
C25
A25
F23
E23
A23
C23
H_D49#
AN6
AG7
AT5
H_HIT#
AD7
AB1
AE5
AE6
AC5
AE8
P7
LA_CLKP
H_D5#
H_HITM#
LA_DATAN0
LA_DATAN1
LA_DATAN2
LA_DATAN3
LA_DATAP0
LA_DATAP1
LA_DATAP2
LA_DATAP3
LPC_AD0
H_D50#
H_INIT#
H_D51#
AM8
AL8
H_INTR
H_D52#
H_LOCK#
H_NMI
H_D53#
AT6
H_D54#
AT9
H_PBE#
H_D55#
AP8
AN10
AL7
H_RCOMPO
H_REQ0#
H_REQ1#
H_REQ2#
H_REQ3#
H_REQ4#
H_RS0#
N3
H_D56#
Y1
H_D57#
W8
H_D58#
AM10
AL10
AE2
AT8
U3
LPC_AD1
H_D59#
AA6
AA8
AC3
AE4
AC6
N1
LPC_AD2
H_D6#
LPC_AD3
H_D60#
LPC_CLKOUT0
LPC_CLKOUT1
LPC_CLKOUT2
LPC_CLKRUN#
LPC_FRAME#
LPC_SERIRQ
PATA_DA0
H_D61#
AR8
AK10
AN8
AH7
AJ7
H_RS1#
H_D62#
H_RS2#
H_D63#
H_SMI#
H_D7#
H_STPCLK#
H_SWING
H_TESTIN#
H_THRMTRIP#
H_TRDY#
HDA_CLK
HDA_DOCKEN#
HDA_DOCKRST#
HDA_RST#
HDA_SDI0
HDA_SDI1
HDA_SDO
HDA_SYNC
INTVRMEN
L_BKLTCTL
L_BKLTEN
L_CTLA_CLK
L_CTLB_DATA
L_DDCCLK
L_DDCDATA
L_VDDEN
AE7
N6
H_D8#
H_D9#
AG4
AD1
AA2
AF7
AK8
AR12
AL9
AR15
AL15
AC1
E1
H_DBSY#
H_DEFER#
H_DINV0#
H_DINV1#
H_DINV2#
H_DINV3#
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_DRDY#
H_DSTBN0#
H_DSTBN1#
H_DSTBN2#
H_DSTBN3#
H_DSTBP0#
H_DSTBP1#
H_DSTBP2#
H_DSTBP3#
PATA_DA1
PATA_DA2
PATA_DCS1#
PATA_DCS3#
PATA_DD0
PATA_DD1
PATA_DD10
PATA_DD11
PATA_DD12
PATA_DD13
PATA_DD14
PATA_DD15
PATA_DD2
PATA_DD3
PATA_DD4
PATA_DD5
PATA_DD6
PATA_DD7
F3
D3
D5
AN15
AB7
AR4
AA3
AF1
AL2
F5
E4
G4
E2
G28
G18
G17
A15
G13
G15
E14
D16
AR14
AR6
AE1
AL1
AT14
AP6
65
Datasheet Addendum for US15WP and US15WPT
Ballout and Package Information
Ball
Ball
Number
Ball
Ball Name
Ball Name
RESERVED6
Ball Name
SD2_DATA6
Number
Number
PATA_DD8
B23
W30
V29
H27
AF35
F28
B33
C34
A32
A31
G30
D6
F12
PATA_DD9
D23
RESERVED7
RESERVED9
RESET#
SD2_DATA7
SD2_LED
B10
PATA_DDACK#
PATA_DDREQ
PATA_DIOR#
PATA_DIOW#
PATA_IDEIRQ
PATA_IORDY
PCIE_CLKINN
PCIE_CLKINP
PCIE_ICOMPI
PCIE_ICOMPO
PCIE_PERn1
PCIE_PERn2
PCIE_PERp1
PCIE_PERp2
PCIE_PETn1
PCIE_PETn2
PCIE_PETp1
PCIE_PETp2
PWROK
A29
G8
C27
SD2_PWR#
SD2_WP
A5
D27
RSMRST#
RSTRDY#
RSTWARN
RTC_X1
A8
A28
SDVO_CTRLCLK
SDVO_CTRLDATA
SDVOB_BLUE
SDVOB_BLUE#
SDVOB_CLK
SDVOB_CLK#
SDVOB_GREEN
SDVOB_GREEN#
SDVOB_INT
SDVOB_INT#
SDVOB_RED
SDVOB_RED#
SDVOB_STALL
SDVOB_STALL#
SDVOB_TVCLKIN
SDVOB_TVCLKIN#
SLPMODE
E16
B29
B16
E27
W36
V35
AB35
AC36
AD35
AE36
AC34
AB29
AB33
AC30
AE34
AD31
AD33
AE32
D31
RTC_X2
RTCRST#
SD0_CD#
W32
V31
SD0_CLK
B4
AA32
Y31
SD0_CMD
SD0_DATA0
SD0_DATA1
SD0_DATA2
SD0_DATA3
SD0_LED
E12
E10
C4
AA30
Y29
A13
E6
AA34
Y33
D8
W34
V33
SD0_PWR#
SD0_WP
C12
F8
AA36
Y35
SD1_CD#
A7
RESERVED0
RESERVED1
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED2
RESERVED20
RESERVED21
RESERVED3
RESERVED4
RESERVED5
F30
SD1_CLK
C14
A6
E31
A18
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD1_LED
SLPRDY#
C33
J26
B8
SM_BS0
AJ25
AH24
AG32
AJ23
AM35
AM34
AJ19
AJ18
AL33
AJ33
AH22
AG23
AP34
AN33
AL29
AN29
U28
G10
A14
C8
SM_BS1
R26
SM_BS2
T27
SM_CAS#
R24
E8
SM_CK0
T23
SD1_PWR#
SD1_WP
C6
SM_CK0#
T25
B6
SM_CK1
U25
SD2_CD#
G12
F10
D10
G11
A10
A12
G9
SM_CK1#
B12
SD2_CLK
SM_CKE0
F7
SD2_CMD
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
SD2_DATA4
SD2_DATA5
SM_CKE1
AJ21
D12
SM_CS0#
SM_CS1#
B14
SM_DQ0
AG21
AK14
AL14
SM_DQ1
A9
SM_DQ10
A11
SM_DQ11
Datasheet Addendum for US15WP and US15WPT
66
Ballout and Package Information
Ball
Number
Ball
Number
Ball
Ball Name
Ball Name
SM_DQ12
Ball Name
SM_DQ48
Number
AN31
AK30
AM30
AT30
AR29
AT29
AL27
AN27
AT32
AK28
AM28
AT28
AR27
AT27
AK26
AN25
AR25
AM26
AP26
AL31
AL25
AT25
AM24
AP24
AT23
AK22
AK24
AT24
AL23
AR23
AN35
AP22
AT22
AK20
AM20
AM22
AL21
AR21
AT21
AT20
AL19
AK32
AM18
AP18
AP20
AN19
AR19
AK18
AL17
AN17
AM16
AP16
AR33
AT18
AR17
AK16
AT16
AP32
AR31
AT31
AM32
AP30
AP28
AT26
AN23
AN21
AT19
AT17
AH26
AG27
AG26
AH32
AH30
AG22
AG33
AH28
AJ27
AG29
SM_MA5
SM_MA6
SM_MA7
SM_MA8
SM_MA9
SM_RAS#
SM_RCOMPO
SM_RCVENIN
SM_RCVENOUT
SM_VREF
SM_WE#
SMB_ALERT#
SMB_CLK
SMB_DATA
SMI#
AG28
AG31
AJ31
AJ29
AG30
AG24
AG36
AJ36
AH35
AK35
AG25
F18
SM_DQ13
SM_DQ14
SM_DQ15
SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ2
SM_DQ49
SM_DQ5
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59
SM_DQ6
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ3
G21
F21
SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63
SM_DQ7
C16
C21
G16
B31
SPKR
STPCPU#
SUSCLK
TCK
E34
SM_DQ8
TDI
D33
G34
C18
G32
F33
SM_DQ30
SM_DQ31
SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35
SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39
SM_DQ4
SM_DQ9
TDO
SM_DQS0
SM_DQS1
SM_DQS2
SM_DQS3
SM_DQS4
SM_DQS5
SM_DQS6
SM_DQS7
SM_MA0
THRM#
TMS
TRST#
USB_CLK48
USB_DN0
USB_DN1
USB_DN2
USB_DN3
USB_DN4
USB_DN5
USB_DN6
USB_DN7
USB_DP0
USB_DP1
USB_DP2
USB_DP3
USB_DP4
USB_DP5
E36
N32
N34
N36
L32
L36
SM_MA1
K33
SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47
SM_MA10
SM_MA11
SM_MA12
SM_MA13
SM_MA14
SM_MA2
H35
H33
M31
M33
M35
K31
SM_MA3
K35
SM_MA4
L34
67
Datasheet Addendum for US15WP and US15WPT
Ballout and Package Information
Ball
Number
Ball
Number
Ball
Number
Ball Name
Ball Name
Ball Name
USB_DP6
USB_DP7
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_RBIASN
USB_RBIASP
VCC
J36
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
M23
N13
N15
N17
N19
N21
N23
P13
P15
P17
P19
P21
P23
R12
R13
R15
R17
R19
R21
R23
T13
T15
T17
T19
T21
U12
U13
U15
U17
U19
U21
V13
V15
V17
V19
V21
W12
W13
W15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W17
W19
W21
Y13
Y15
Y17
Y19
Y21
Y23
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
U23
U24
V23
V24
W23
W24
J34
K29
R30
L30
M29
J30
H29
P29
N30
VCC15
R36
VCC15
P35
VCC15
AA12
AA13
AA15
AA17
AA19
AA21
AA23
AA24
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
M13
M14
M15
M17
M18
M19
M21
M22
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15
VCC
VCC15USB
VCC15USB
VCC15USB
VCC15USB
VCC15USB
VCC15USB
VCC
VCC
VCC
VCC
VCC
Datasheet Addendum for US15WP and US15WPT
68
Ballout and Package Information
Ball
Ball
Ball
Ball Name
Ball Name
VCC33
Ball Name
Number
Number
Number
H3
VCCP33USBSUS
VCCP33USBSUS
VCCP33USBSUS
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VCCPCIE
VCCSDVO
VCCSDVO
VCCSDVO
VCCSDVO
VCCSDVO
VCCSDVO
VCCSM
N26
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSS
AE18
AE19
AE20
AE21
AE22
AE23
AF12
AF15
AF18
AF19
AG12
AG13
AG15
AG18
AG19
AH12
AH13
AH14
AH15
AH16
AH17
A2
VCC33
H5
P25
VCC33
H7
R25
VCC33
J4
AC28
AD26
AD27
AD28
AD29
AE25
AE26
AE27
AE28
AE29
AE30
AA25
AA26
AB25
AB26
AB27
AC25
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AE12
AE13
AE14
AE15
AE16
AE17
VCC33
J6
VCC33
J8
VCC33
J10
K3
VCC33
VCC33
K5
VCC33
K7
VCC33
K9
VCC33
K11
L4
VCC33
VCC33
L6
VCC33
L8
VCC33
L10
A30
L26
M25
M26
M27
P27
L25
U27
V26
Y26
AC11
AB31
AA28
U26
W27
AD11
M12
N12
V25
V27
W26
W28
Y27
VCC33RTC
VCC33SUS
VCC33SUS
VCC33SUS
VCC33SUS
VCC33SUS
VCC5REF
VCC5REFSUS
VCCADPLLA
VCCADPLLB
VCCAHPLL
VCCAPCIEBG
VCCAPCIEPLL
VCCAUSBBGSUS
VCCAUSBPLL
VCCDHPLL
VCCHDA
VCCHDA
VCCLVDS
VCCLVDS
VCCLVDS
VCCLVDS
VCCLVDS
VCCSM
VCCSM
VSS
A3
VCCSM
VSS
A4
VCCSM
VSS
A33
VCCSM
VSS
A34
VCCSM
VSS
A35
VCCSM
VSS
A36
VCCSM
VSS
AA9
VCCSM
VSS
AA11
AA14
AA16
AA18
AA20
AA22
AA27
AA29
AA31
AA33
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
VCCSM
VSS
69
Datasheet Addendum for US15WP and US15WPT
Ballout and Package Information
Ball
Number
Ball
Number
Ball
Number
Ball Name
Ball Name
Ball Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA35
AB2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG9
AD25
AD30
AD32
AD34
AD36
AE9
AG11
AG14
AG16
AG17
AG20
AG34
AG35
AH2
AB3
AB4
AB5
AB6
AB8
AB12
AB24
AB28
AB30
AB32
AB34
AB36
AC9
AE11
AE24
AE31
AE33
AE35
AF2
AH3
AH4
AH5
AH6
AF3
AH8
AF4
AH9
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC26
AC27
AC29
AC31
AC33
AC35
AD2
AF5
AH11
AH18
AH19
AH20
AH21
AH23
AH25
AH27
AH29
AH31
AH33
AH34
AH36
AJ9
AF6
AF8
AF11
AF13
AF14
AF16
AF17
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF36
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ20
AJ22
AD3
AD4
AD5
AD6
Datasheet Addendum for US15WP and US15WPT
70
Ballout and Package Information
Ball
Number
Ball
Number
Ball
Ball Name
Ball Name
Ball Name
Number
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ24
AJ26
AJ28
AJ30
AJ32
AJ34
AJ35
AK2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AP5
AM3
AP7
AM4
AP9
AM5
AP11
AP13
AP15
AP17
AP19
AP21
AP23
AP25
AP27
AP29
AP31
AP33
AP35
AP36
AR1
AM7
AM9
AM11
AM13
AM15
AM17
AM19
AM21
AM23
AM25
AM27
AM29
AM31
AM33
AM36
AN1
AK3
AK4
AK5
AK7
AK9
AK11
AK13
AK15
AK17
AK19
AK21
AK23
AK25
AK27
AK29
AK31
AK33
AK34
AK36
AL16
AL18
AL20
AL22
AL24
AL26
AL28
AL30
AL32
AL34
AL35
AL36
AR2
AR3
AN5
AR5
AN7
AR7
AN9
AR9
AN11
AN13
AN16
AN18
AN20
AN22
AN24
AN26
AN28
AN30
AN32
AN34
AN36
AP1
AR11
AR13
AR16
AR18
AR20
AR22
AR24
AR26
AR28
AR30
AR32
AR34
AR35
AR36
AT1
AP2
AP3
AT2
71
Datasheet Addendum for US15WP and US15WPT
Ballout and Package Information
Ball
Number
Ball
Number
Ball
Number
Ball Name
Ball Name
Ball Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AT3
AT4
AT15
AT33
AT34
AT35
AT36
B1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C22
C24
C26
C28
C30
C32
C35
C36
D1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E30
E33
E35
F1
F2
F4
F6
F9
B2
F11
F13
F15
F17
F19
F20
F22
F24
F26
F32
F34
F35
F36
G1
B3
D2
B5
D4
B7
D7
B9
D9
B11
B13
B15
B17
B20
B22
B24
B26
B28
B30
B32
B34
B35
B36
C1
D11
D13
D15
D17
D20
D22
D24
D26
D28
D30
D32
D34
D36
E3
G2
G3
G5
G7
G27
G29
G31
G33
G35
H1
E5
C2
E7
C3
E9
C5
E11
E13
E15
E17
E20
E22
E24
E26
E28
C7
C9
H2
C10
C11
C13
C15
C17
C20
H4
H6
H8
H9
H10
H11
Datasheet Addendum for US15WP and US15WPT
72
Ballout and Package Information
Ball
Number
Ball
Number
Ball
Ball Name
Ball Name
Ball Name
Number
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H28
H30
H32
H34
H36
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K24
K25
K26
K27
K28
K30
K32
K34
K36
L2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M6
M7
M8
M10
M11
M16
M20
M24
M28
M30
M32
M34
M36
N8
L3
L5
L7
L9
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L27
L28
L29
L31
L33
L35
M1
N9
N11
N14
N16
N18
N20
N22
N24
N25
N27
N28
N29
N31
N33
N35
P2
J2
J3
J5
J7
J9
J11
J25
J27
J29
J31
J33
J35
K2
P3
P4
P5
P6
K4
P8
K6
M2
P12
P14
P16
P18
K8
M3
K10
K12
M4
M5
73
Datasheet Addendum for US15WP and US15WPT
Ballout and Package Information
Ball
Number
Ball
Number
Ball
Number
Ball Name
Ball Name
Ball Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P20
P22
P24
P26
P28
P30
P32
P34
P36
R9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T36
U9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W33
W35
Y2
U11
U14
U16
U18
U20
U22
U29
U31
U33
U35
V2
Y3
Y4
Y5
Y6
Y8
Y12
Y14
Y16
Y18
Y20
Y22
Y24
Y25
Y28
Y30
Y32
Y34
Y36
AC32
T26
AA10
AB9
AB10
AB11
AC10
AD9
AD10
AE10
AF9
AF10
AG10
AH10
M9
R11
R14
R16
R18
R20
R22
R27
R28
R29
R31
R33
R35
T2
V3
V4
V5
V6
V8
V12
V14
V16
V18
V20
V22
V28
V30
V32
V34
V36
W9
VSSAPCIEBG
VSSAUSBBGSUS
T3
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
T4
T5
T6
T8
T12
T14
T16
T18
T20
T22
T24
T28
T30
T32
T34
W11
W14
W16
W18
W20
W22
W25
W29
W31
N10
P9
P10
Datasheet Addendum for US15WP and US15WPT
74
Ballout and Package Information
Ball
Number
Ball Name
VTT
P11
R10
T9
VTT
VTT
VTT
T10
T11
U10
V9
VTT
VTT
VTT
VTT
V10
V11
W10
Y9
VTT
VTT
VTT
VTT
Y10
Y11
C31
G6
VTT
WAKE#
XOR_TEST
Datasheet Addendum
Document number: 321422-001
75
相关型号：
LE82US15EE/SLGQ9
Multifunction Peripheral, CMOS, PBGA1295, 37.50 X 37.50 MM, 1.016 MM PITCH, FCBGA-1295
INTEL
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