LF80550KF0604M_技术文档

Dual-Core Intel® Xeon® Processor

7100 Series

Datasheet

September 2006

Reference Number: 314553 Revision: 002

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PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or

life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them.

The Dual-Core Intel® Xeon® Processor 7100 Series, Processor 7110, 7120, 7130, 7140 and 7150 processor may contain design

defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized

errata are available on request.

2

I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed

by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and

North American Philips Corporation.Contact your local Intel sales office or your distributor to obtain the latest specifications and

before placing your product order.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device

drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an

Intel® 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult

with your system vendor for more information.

Intel, Pentium, Intel Xeon, Intel NetBurst, Enhanced Intel SpeedStep Technology, Intel 64 and the Intel logo are trademarks or

registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

* Other names and brands may be claimed as the property of others.

2

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Contents

1

Introduction............................................................................................................ 11

1.1

1.2

1.3

Terminology ..................................................................................................... 13

References ....................................................................................................... 14

State of Data.................................................................................................... 15

2

Electrical Specifications........................................................................................... 17

2.1

Front Side Bus and GTLREF ................................................................................ 17

2.1.1 Front Side Bus Clock and Processor Clocking.............................................. 18

2.1.2 Front Side Bus Clock Select (BSEL[1:0]).................................................... 19

2.1.3 Phase Lock Loop (PLL) Power and Filter..................................................... 20

Voltage Identification (VID) ................................................................................ 21

Cache Voltage Identification (CVID)..................................................................... 22

Reserved, Unused, and TESTHI Pins..................................................................... 23

Mixing Processors.............................................................................................. 24

Front Side Bus Signal Groups.............................................................................. 24

GTL+ Asynchronous and AGTL+ Asynchronous Signals........................................... 26

Test Access Port (TAP) Connection....................................................................... 27

Maximum Ratings.............................................................................................. 27

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10 Processor DC Specifications ................................................................................ 28

2.10.1 Flexible Motherboard (FMB) Guidelines...................................................... 28

2.10.2 VCC Overshoot Specification.................................................................... 34

2.10.3 VCACHE Overshoot Specification .............................................................. 35

2.10.4 Die Voltage Validation............................................................................. 36

2.10.5 Clock, Miscellaneous and AGTL+ Specifications........................................... 36

2.11 AGTL+ Front Side Bus Specifications.................................................................... 40

3

Mechanical Specifications........................................................................................ 41

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Package Mechanical Drawing............................................................................... 42

Processor Component Keep-Out Zones................................................................. 45

Package Loading Specifications ........................................................................... 45

Package Handling Guidelines............................................................................... 46

Package Insertion Specifications.......................................................................... 46

Processor Mass Specifications ............................................................................. 46

Processor Materials............................................................................................ 46

Processor Markings............................................................................................ 46

Processor Pin-Out Coordinates ............................................................................ 48

4

Pin Listing ............................................................................................................... 49

4.1

Dual-Core Intel® Xeon® Processor 7100 Series Pin Assignments ............................ 49

4.1.1 Pin Listing by Pin Name........................................................................... 49

4.1.2 Pin Listing by Pin Number........................................................................ 57

5

6

Signal Definitions .................................................................................................... 65

5.1 Signal Definitions .............................................................................................. 65

Thermal Specifications ............................................................................................ 73

6.1

Package Thermal Specifications........................................................................... 73

6.1.1 Thermal Specifications ............................................................................ 73

6.1.2 Thermal Metrology ................................................................................. 77

Processor Thermal Features................................................................................ 77

6.2.1 Thermal Monitor..................................................................................... 77

6.2.2 Thermal Monitor 2.................................................................................. 78

6.2.3 On-Demand Mode .................................................................................. 79

6.2.4 PROCHOT# Signal Pin............................................................................. 80

6.2.5 FORCEPR# Signal Pin.............................................................................. 80

6.2

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

3

6.2.6 THERMTRIP# Signal Pin...........................................................................80

6.2.7 TCONTROL and Fan Speed Reduction ........................................................80

6.2.8 Thermal Diode........................................................................................81

7

Features ..................................................................................................................83

7.1

7.2

Power-On Configuration Options ..........................................................................83

Clock Control and Low Power States.....................................................................83

7.2.1 Normal State .........................................................................................84

7.2.2 HALT or Enhanced Power Down State........................................................84

7.2.3 Stop-Grant State ....................................................................................85

7.2.4 Enhanced HALT Snoop State or HALT Snoop State,

Stop Grant Snoop State...........................................................................86

Enhanced Intel SpeedStep® Technology...............................................................86

System Management Bus (SMBus) Interface .........................................................87

7.4.1 SMBus Device Addressing ........................................................................88

7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions.........................90

7.4.3 Processor Information ROM (PIROM) .........................................................90

7.4.4 Checksums ..........................................................................................109

7.4.5 Scratch EEPROM...................................................................................110

7.4.6 SMBus Thermal Sensor..........................................................................110

7.4.7 Thermal Sensor Supported SMBus Transactions........................................111

7.4.8 SMBus Thermal Sensor Registers............................................................113

7.4.9 SMBus Thermal Sensor Alert Interrupt.....................................................116

7.3

7.4

8

Boxed Processor Specifications..............................................................................117

8.1

8.2

Introduction....................................................................................................117

Mechanical Specifications..................................................................................118

8.2.1 Boxed Processor Heatsink Dimensions .....................................................118

8.2.2 Boxed Processor Heatsink Weight ...........................................................125

8.2.3 Boxed Processor Retention Mechanism and Heatsink Supports....................125

Thermal Specifications......................................................................................125

8.3.1 Boxed Processor Cooling Requirements....................................................125

8.3.2 Boxed Processor Contents......................................................................126

8.3

9

Debug Tools Specifications ....................................................................................127

9.1

Logic Analyzer Interface (LAI) ...........................................................................127

9.1.1 Mechanical Considerations .....................................................................127

9.1.2 Electrical Considerations........................................................................127

Figures

2-1

On-Die Front Side Bus Termination ......................................................................18

Phase Lock Loop (PLL) Filter Requirements............................................................20

Dual-Core Intel® Xeon® Processor 7100 Series Load Current vs. Time.....................30

VCC Static and Transient Tolerance......................................................................32

VCACHE Static and Transient Tolerance at the Die Sense Location............................33

VCACHE Static and Transient Tolerance at the Board..............................................34

VCC Overshoot Example Waveform......................................................................35

VCACHE Overshoot Example Waveform ................................................................36

Processor Package Assembly Sketch.....................................................................41

Processor Package Drawing (Sheet 1 of 2) ............................................................43

Processor Package Drawing (Sheet 2 of 2) ............................................................44

Processor Topside Markings.................................................................................47

Processor Bottom-Side Markings..........................................................................47

Processor Pin-Out Coordinates, Top View ..............................................................48

150W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile......................75

2-2

2-3

2-4

2-5

2-6

2-7

2-8

3-1

3-2

3-3

3-4

3-5

3-6

6-1

4

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

6-2

6-3

6-4

7-1

7-2

8-1

95W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile....................... 76

Case Temperature (TCASE) Measurement Location ................................................ 77

Thermal Monitor 2 Frequency and Voltage Ordering ............................................... 79

Stop Clock State Machine ................................................................................... 85

Logical Schematic of SMBus Circuitry ................................................................... 88

Passive Dual-Core Intel® Xeon® Processor 7100 Series

Thermal Solution (3U and larger) ...................................................................... 118

Top Side Board Keep-Out Zones (Part 1) ............................................................ 119

Top Side Board Keep-Out Zones (Part 2) ............................................................ 120

Bottom Side Board Keep-Out Zones................................................................... 121

Board Mounting-Hole Keep-Out Zones................................................................ 122

Thermal Solution Volumetric............................................................................. 123

Recommended Processor Layout and Pitch.......................................................... 124

8-2

8-3

8-4

8-5

8-6

8-7

Tables

1-1

Features of the Dual-Core Intel® Xeon® Processor 7100 Series .............................. 12

166 MHz Core Frequency to Front Side Bus Multiplier Configuration.......................... 18

200 MHz Core Frequency to Front Side Bus Multiplier Configuration.......................... 19

BSEL[1:0] Frequency Table for BCLK[1:0] ............................................................ 19

Voltage Identification (VID) Definition.................................................................. 22

Cache Voltage Identification (CVID) Definition....................................................... 23

Front Side Bus Pin Groups .................................................................................. 25

Signal Description Table..................................................................................... 26

Signal Reference Voltages .................................................................................. 26

Processor Absolute Maximum Ratings................................................................... 27

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10 Voltage and Current Specifications....................................................................... 28

2-11 VCC Static and Transient Tolerance ..................................................................... 31

2-12 VCACHE Static and Transient Tolerance at the Die Sense Location ........................... 33

2-13 VCACHE Static and Transient Tolerance at the Board.............................................. 34

2-14 VCC Overshoot Specification............................................................................... 35

2-15 VCACHE Overshoot Specification ......................................................................... 35

2-16 Front Side Bus Differential BCLK Specifications...................................................... 36

2-17 BSEL[1:0], VID[5:0], and CVID[3:0] DC Specifications .......................................... 37

2-18 VIDPWRGD DC Specifications.............................................................................. 37

2-19 AGTL+ Signal Group DC Specifications ................................................................. 38

2-20 PWRGOOD and TAP Signal Group DC Specifications................................................ 38

2-21 GTL+ Asynchronous and AGTL+ Asynchronous Signal Group

DC Specifications .............................................................................................. 39

2-22 SMBus Signal Group DC Specifications ................................................................. 39

2-23 AGTL+ Bus Voltage Definitions............................................................................ 40

3-1

3-2

3-3

4-1

4-2

5-1

6-1

6-2

6-3

7-1

7-2

Processor Loading Specifications ......................................................................... 45

Package Handling Guidelines............................................................................... 46

Processor Materials............................................................................................ 46

Pin Listing by Pin Name...................................................................................... 49

Pin Listing by Pin Number................................................................................... 57

Signal Definitions .............................................................................................. 65

Dual-Core Intel® Xeon® Processor 7100 Series Thermal Specifications.................... 74

150W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile ..................... 75

95W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile....................... 76

Power-On Configuration Option Pins..................................................................... 83

Thermal Sensor SMBus Addressing ...................................................................... 89

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

5

7-3

7-4

7-5

7-6

7-7

7-8

7-9

Memory Device SMBus Addressing .......................................................................89

Read Byte SMBus Packet ....................................................................................90

Write Byte SMBus Packet....................................................................................90

Processor Information ROM Data Sections.............................................................91

128 Byte ROM Checksum Values........................................................................109

Write Byte SMBus Packet..................................................................................111

Read Byte SMBus Packet ..................................................................................111

7-10 Send Byte SMBus Packet ..................................................................................111

7-11 Receive Byte SMBus Packet...............................................................................111

7-12 ARA SMBus Packet...........................................................................................111

7-13 SMBus Thermal Sensor Command Byte Bit Assignments .......................................112

7-14 Thermal Value Register Encoding.......................................................................113

7-15 SMBus Thermal Sensor Status Register 1............................................................114

7-16 SMBus Thermal Sensor Status Register 2............................................................114

7-17 SMBus Thermal Sensor Configuration Register.....................................................114

7-18 SMBus Thermal Sensor Conversion Rate Register.................................................115

6

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Revision History

Document Number

Revision Number

Description

Release Date

314553

001

•

Initial Release

August 2006

•

Added 3.5GHz at 667 ratio

Updated Processor Mixing

314553

002

September 2006

§

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

7

8

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

Available at 3.4, 3.33, 3.2, 3.16, 3.0, 2.6 or

Machine Check Architecture (MCA)

2.5 GHz

Includes 16-KB Level 1 (L1) data cache

65 nm process technology

2 MB Advanced Transfer Cache (On-die, full

speed Level 2 (L2) Cache) with 8-way

Binary compatible with application running on

previous members of Intel's IA-32

microprocessor line

associativity and Error Correcting Code (ECC)

Up to 16MB Level 3 (L3) Cache with 16-way

Intel® 64 architecture

associativity and Error Correcting Code (ECC)

Intel NetBurst® microarchitecture

Hyper-Threading Technology

Intel® Cache Safe Technology

Fast 667 or 800 MHz system bus with Error

Correcting Code (ECC)

Hardware support for multithreaded

applications

Enables system support of up to 64 GB of

physical memory

Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor core

frequency

Demand Based Switching (DBS) with

Enhanced Intel SpeedStep® Technology

Hyper Pipelined Technology

Advanced Dynamic Execution

Very deep out-of-order execution

Enhanced branch prediction

Intel® Virtualization Technology

Execute Disable Bit

Enhanced thermal and power management

capabilities:

—Thermal Monitor (TM1)

—Thermal Monitor 2 (TM2)

144 Streaming SIMD Extensions 2 (SSE2)

instructions

13 Streaming SIMD Extensions 3 (SSE3)

instructions

Enhanced floating-point and multimedia unit

for enhanced video, audio, encryption, and 3D

performance

System Management mode

The Dual-Core Intel® Xeon® processor 7100 series is designed for high-performance

multi-processor server applications for mid-tier enterprise serving and server consolidation.

Based on the Intel NetBurst® microarchitecture and the new Hyper-Threading Technology,

it is binary compatible with pervious Intel Architecture (IA-32) processors. The addition of

Intel® 64 architecture provides 64-bit computing and 40-bit addressing provides up to 1

Terabyte of direct memory addressability. The Dual-Core Intel Xeon processor 7100 series

is scalable to four processors and beyond in a multiprocessor system providing exceptional

performance for applications running on advanced operating systems such as Microsoft

Windows* 2003 server, and Linux* operating systems. The Dual-Core Intel Xeon processor

7100 series delivers compute power at unparalleled value and flexibility for internet

infrastructure and departmental server applications, including application servers,

databases, and business intelligence. The Intel NetBurst microarchitecture with

Hyper-Threading Technology and Intel 64 architecture delivers outstanding performance

and headroom from peak internet server workloads, resulting in faster response times,

support for more users, and improved scalability.

§

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

9

10

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Introduction

1 Introduction

The Dual-Core Intel® Xeon® Processor 7100 Series, Processor Number 7150, 7140,

7130, 7120 and 7110 is a dual core product for multi-processor servers. The Dual-Core

Intel Xeon processor 7100 series is a 64-bit server processor utilizing two physical Intel

NetBurst® microarchitecture cores in one package. It maintains the tradition of

compatibility with IA-32 software and includes features found in the Intel® Xeon®

processor such as Hyper Pipelined Technology, a Rapid Execution Engine, and an

Execution Trace Cache. Hyper Pipelined Technology includes a multi-stage pipeline,

allowing the processor to reach much higher core frequencies. The 667 MTS (Mega

Transfer per Seconds) front side bus is a quad-pumped bus running off a 166 MHz

system clock making 5.3 GB per second data transfer rates possible. The 800 MTS front

side bus (FSB) is a quad-pumped bus running off a 200 MHz system clock making

6.4 GB per second data transfer rates possible. The Execution Trace Cache is a level 1

(L1) cache that stores decoded micro-operations, which removes the decoder from the

main execution path, thereby increasing performance. In addition, the Dual-Core Intel

Xeon processor 7100 series includes the Intel® Extended Memory 64 Technology,

providing additional address capability.

In addition, enhanced thermal and power management capabilities are implemented,

including Thermal Monitor, Thermal Monitor 2 (TM2), and Enhanced Intel SpeedStep®

technology. Thermal Monitor and Thermal Monitor 2 provide efficient and effective

cooling in high temperature situations. Enhanced Intel SpeedStep technology allows

trade-offs to be made between performance and power consumption. This may lower

average power consumption (in conjunction with OS support).

The Dual-Core Intel Xeon processor 7100 series supports Hyper-Threading Technology.

This feature allows a single, physical processor to function as two logical processors.

While some execution resources such as caches, execution units, and buses are shared,

each logical processor has its own architectural state with its own set of general-

purpose registers, control registers to provide increased system responsiveness in

multitasking environments, and headroom for next generation multi-threaded

applications. More information on Hyper-Threading Technology can be found at

http://www.intel.com/technology/hyperthread.

Support for Intel's Execute Disable Bit functionality has been added which can prevent

certain classes of malicious “buffer overflow” attacks when combined with a supporting

operating system. Execute Disable Bit allows the processor to classify areas in memory

by where application code can execute and where it cannot. When a malicious worm

attempts to insert code in the buffer, the processor disables code execution, preventing

damage or worm propagation.

Other features within the Intel NetBurst microarchitecture include Advanced Dynamic

Execution, Advanced Transfer Cache, enhanced floating point and multi-media unit, and

Streaming SIMD Extensions 2 (SSE2). The Advanced Dynamic Execution improves

speculative execution and branch prediction internal to the processor. The Advanced

Transfer Cache is a 2 MB total on-die level 2 (L2) cache, organized as 1 MB dedicated

per core. The floating point and multi-media units include 128-bit wide registers and a

separate register for data movement. SSE2 instructions provide highly efficient double-

precision floating point, SIMD integer, and memory management operations. In

addition, Streaming SIMD Extensions 3 (SSE3) instructions have been added to further

extend the capabilities of Intel processor technology. Other processor enhancements

include core frequency improvements and microarchitectural improvements.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

11

Introduction

The Dual-Core Intel Xeon processor 7100 series processor supports Intel® 64 as an

enhancement to Intel’s IA-32 architecture. This enhancement allows the processor to

execute operating systems and applications written to take advantage of the 64-bit

extension technology. Further details can be found in the 64-bit Extension Technology

Software Developer’s Guide at http://developer.intel.com/technology/64bitextensions/.

Dual-Core Intel Xeon processor 7100 series are intended for high performance multi-

processor server systems with support for up to two processors on a 667 or 800 MTS

FSB. Dual-Core Intel Xeon processor 7100 series will be available with 4 MB, 8 MB or

16 MB of on-die level 3 (L3) cache. All versions of the Dual-Core Intel Xeon processor

7100 series will include manageability features. Components of the manageability

features include an OEM EEPROM and Processor Information ROM which are accessed

through an SMBus interface and contain information relevant to the particular

processor and system in which it is installed.

Table 1-1.

Features of the Dual-Core Intel® Xeon® Processor 7100 Series

# of Supported

Symmetric Agents

Per FSB

L2 Advanced

Transfer Cache

Integrated L3

FSB

Frequency

2

1

Cache

Dual-Core Intel®

Xeon® Processor

7100 Series

1 - 2

2 MB total

(1 MB per core)

4 MB, 8 MB or

16 MB

667 or

800 MTS

Notes:

1.

Total accessible size of L2 caches may vary by one cache line pair (128 bytes) per core, depending on

usage and operating environment.

2.

Total accessible size of the L3 cache may vary by up to thirty-two (32) cache lines (64 bytes per line),

depending on usage and operating environment.

The Dual-Core Intel Xeon processor 7100 series is packaged in a 604-pin Flip-Chip

Micro Pin Grid Array (FC-mPGA6) package and utilizes a surface-mount Zero Insertion

Force (ZIF) mPGA604 socket. The Dual-Core Intel Xeon processor 7100 series supports

40-bit addressing, data bus ECC protection (single-bit error correction with double-bit

error detection), and the bus protocol addition of the Deferred Phase.

The Dual-Core Intel Xeon processor 7100 series uses a scalable system bus protocol

referred to as the “front side bus” in this document. The front side bus utilizes a split-

transaction, deferred reply and Deferred Phase protocol. The front side bus uses

Source-Synchronous Transfer (SST) of address and data to improve performance. The

processor transfers data four times per bus clock (4X data transfer rate). Along with

the 4X data bus, the address bus can deliver addresses two times per bus clock and is

referred to as a ‘double-clocked’, ‘double-pumped’, or the 2X address bus. In addition,

the Request Phase completes in one clock cycle. Working together, the 4X data bus and

2X address bus provide a data bus bandwidth of up to 5.3 GB (667 MTS) or 6.4 GB

(800 MTS) per second. Finally, the front side bus is also used to deliver interrupts.

The Dual-Core Intel Xeon processor 7100 series supports a threshold-based

mechanism for enhanced cache error reporting (IA32_MCG_CAP[11] = 1). Intel

recommends that fault prediction handlers rely on this mechanism to assess processor

cache health. Please refer to the IA-32 Intel® Architecture Software Developer’s

Manual, Volume 3A for more detailed information. Please note that the Dual-Core Intel

Xeon processor 7100 series does not support the newly added overwrite rules.

12

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Introduction

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating that a signal

is in the asserted state when driven to a low level. For example, when RESET# is low

(i.e. when RESET# is asserted), a reset has been requested. Conversely, when NMI is

high (i.e. when NMI is asserted), a nonmaskable interrupt request has occurred. In the

case of signals where the name does not imply an active state but describes part of a

binary sequence (such as address or data), the ‘#’ symbol implies that the signal is

inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also

refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“Front side bus” refers to the interface between the processor, system core logic (i.e.

the chipset components), and other bus agents. The front side bus supports

multiprocessing and cache coherency. For this document, “front side bus” is used as the

generic term for the “Dual-Core Intel Xeon processor 7100 series system bus”.

Commonly used terms are explained here for clarification:

• Enhanced Intel SpeedStep Technology — Enhanced Intel SpeedStep

Technology is the next generation implementation of the Geyserville technology

which extends power management capabilities of servers.

• FC-mPGA6 — The Dual-Core Intel Xeon processor 7100 series is available in a

Flip-Chip Micro Pin Grid Array 6 package, consisting of a processor core mounted

on a pinned substrate with an integrated heat spreader (IHS). This packaging

technology employs a 1.27 mm [0.05 in] pitch for the substrate pins.

• Front Side Bus (FSB) — The electrical interface that connects the processor to

the chipset. Also referred to as the processor system bus or the system bus. All

memory and I/O transactions as well as interrupt messages pass between the

processor and chipset over the FSB.

• Functional Operation — Refers to the normal operating conditions in which all

processor specifications, including DC, AC, system bus, signal quality, mechanical,

and thermal, are satisfied.

• Integrated Heat Spreader (IHS) — A component of the processor package used

to enhance the thermal performance of the package. Component thermal solutions

interface with the processor at the IHS surface.

• mPGA604 — The Dual-Core Intel Xeon processor 7100 series processor mates

with the system board through this surface mount, 604-pin, zero insertion force

(ZIF) socket.

• OEM — Original Equipment Manufacturer.

• Processor core — The processor’s execution engine. All AC timing and signal

integrity specifications are to the pads of the processor core.

• Processor Information ROM (PIROM) — A memory device located on the

processor and accessible via the System Management Bus (SMBus) which contains

information regarding the processor’s features. This device is shared with the

Scratch EEPROM, is programmed during manufacturing, and is write-protected.

• Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory)

— A memory device located on the processor and addressable via the SMBus which

can be used by the OEM to store information useful for system management.

• SMBus — System Management Bus. A two-wire interface through which simple

system and power management related devices can communicate with the rest of

the system. It is based on the principals of the operation of the I²C* two-wire serial

bus from Phillips Semiconductor.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

13

Introduction

Note:

I²C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset

of the I²C bus/protocol and was developed by Intel. Implementations of the I²C

bus/protocol or the SMBus bus/protocol may require licenses from various entities,

including Philips Electronics N.V. and North American Philips Corporation.

• Storage Conditions — Refers to a non-operational state. The processor may be

installed in a platform, in a tray, or loose. Processors may be sealed in packaging or

exposed to free air. Under these conditions, processor pins should not be connected

to any supply voltages, have any I/Os biased, or receive any clocks.

• Symmetric Agent - A symmetric agent is a processor which shares the same I/O

subsystem and memory array, and runs the same operating system as another

processor in a system. Systems using symmetric agents are known as Symmetric

MultiProcessing (SMP) systems. Dual-Core Intel Xeon processor 7100 series

processors should only be used in SMP systems which have two or fewer symmetric

agents per front side bus.

• Dual-Core Intel Xeon processor 7100 series — The entire product, including

processor core substrate and integrated heat spreader (IHS).

1.2

References

Material and concepts available in the following documents may be beneficial when

reading this document:

Document

Intel Order Number

Notes

AP-485, Intel® Processor Identification and the CPUID Instruction

IA-32 Intel® Architecture Software Developer's Manual

241618

4

•

Volume 1: Basic Architecture

253665

253666

253667

253668

253669

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

IA-32 Intel® Architecture Software Developer's Manual Documentation

Changes

252046

4

IA-32 Intel® Architecture Optimization Reference Manual

248966

4

Intel® Extended Memory 64 Technology Software Developer’s Manual

•

Volume 1

Volume 2

300834

300835

IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology

Software Developer's Manual Documentation Changes

252046

4

Dual-Core Intel® Xeon® Processor 7100 Series Specification Update

314554

4

Dual-Core Intel® Xeon® Processor 7100 Series Boundary Scan

Descriptive Language (BSDL) Files

Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical

Design Guidelines

314555

4

1

2

Dual-Core Intel® Xeon® Processor 7100 Series Thermal Test Vehicle

and Cooling Solution Thermal Models

64-bit Intel® Xeon® Processor MP with up to 8MB L3 Cache Cooling

Solution Mechanical Models

64-bit Intel® Xeon® Processor MP with up to 8MB L3 Cache Mechanical

Models

Cedar Mill Processor Family BIOS Writer’s Guide (BWG)

eXtended Debug Port: Debug Port Design Guide for MP Platforms

mPGA604 Socket Design Guidelines

3

4

254239

14

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Introduction

Document

Intel Order Number

Notes

Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator

Down (EVRD) 10.2 Design Guidelines

306760

4

VRM 9.1 DC-DC Converter Design Guidelines

ATX/ATX12V Power Supply Design Guidelines

306826

4

5

6

MPS Power Supply: A Server System Infrastructure (SSI) Specification

For Midrange Chassis Power Supplies

System Management Bus (SMBus) Specification

7

Notes:

1.

The Dual-Core Intel® Xeon® Processor 7100 Series utilizes the 64-bit Intel® Xeon® Processor MP with up

to 8MB L3 Cache Cooling Solution Mechanical Models in ProE* and IGES format which are available

electronically.

The Dual-Core Intel® Xeon® Processor 7100 Series utilizes the 64-bit Intel® Xeon® Processor MP with up

to 8MB L3 Cache Mechanical Models in ProE* and IGES formats which are available electronically.

Contact your Intel representative to receive the latest revisions of these documents.

This collateral is available publicly at http://developer.intel.com.

This document is available at http://www.formfactors.org.

2.

3.

4.

5.

6.

7.

This document is available at http://www.ssiforum.org.

This document is available at http://www.smbus.org.

1.3

State of Data

The data contained within this document is subject to change. It is the most accurate

information available by the publication date of this document. For processor stepping

info, refer to the Dual-Core Intel® Xeon® Processor 7100 Series Specification Update.

§

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

15

Introduction

16

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

2 Electrical Specifications

2.1

Front Side Bus and GTLREF

Most Dual-Core Intel® Xeon® Processor 7100 Series processor front side bus (FSB)

signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This

technology provides improved noise margins and reduced ringing through low voltage

swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up

resistors to provide the high logic level and termination. AGTL+ output buffers differ

from GTL+ buffers with the addition of an active pMOS pull-up transistor to “assist” the

pull-up resistors during the first clock of a low-to-high voltage transition. Platforms

implement a termination voltage level for AGTL+ signals defined as V_TT. Because

platforms implement separate power planes for each processor, separate V_CCand V_TT

supplies are necessary. This configuration allows for improved noise tolerance as

processor frequency increases. Speed enhancements to data and address busses have

caused signal integrity considerations and platform design methods to become even

more critical than with previous processor families. Design guidelines for the processor

front side bus are detailed in the appropriate platform design guides (refer to

Section 1.2).

The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers

to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the

motherboard (see Table 2-23 for GTLREF specifications). Please refer to the appropriate

platform design guidelines for details. Termination resistors (R_TT) for AGTL+ signals are

provided on the processor silicon and are terminated to V_TT. The on-die termination

resistors are a selectable feature and can be enabled or disabled via the ODTEN signal.

For end bus agents, on-die termination resistors are enabled to control reflections on

the transmission line. For the middle bus agent, on-die termination R_TTresistors must

be disabled. Intel chipsets will also provide on-termination, thus eliminating the need

to terminate the bus on the motherboard for most AGTL+ signals. Processor wired-OR

signals may also include additional on-die resistors (R_L) to further ensure proper noise

margin and signal integrity. R_Lis not configurable and is always enabled for these

signals. See Table 2-7 for a list of these signals.

Figure 2-1 illustrates the active on-die termination.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

17

Electrical Specifications

Figure 2-1. On-Die Front Side Bus Termination

End Agent

Middle Agent

V_TT

R_TT

Signal

R_L

R_TT- On-die termination resistors for AGTL+ signals

R_L- Additional on-die resistance implemented for proper noise margin and

signal integrity (wired-OR signals only)

Note:

Some AGTL+ signals do not include on-die termination (R_TT) and must be terminated

on the motherboard. See Table 2-7 for details regarding these signals.

2.1.1

Front Side Bus Clock and Processor Clocking

BCLK[1:0] directly controls the front side bus interface speed as well as the core

frequency of the processor. The Dual-Core Intel® Xeon® Processor 7100 Series

processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus

ratio multiplier will be set at its default ratio during manufacturing. The default setting

generates the maximum speed for the processor. It is possible to override this setting

using software. Refer to the Cedar Mill Processor Family BIOS Writer’s Guide for details.

This will permit operation at a speed lower than the processor’s tested frequency.

The processor core frequency is configured during reset by using values stored

internally during manufacturing. The stored values set the highest bus fraction at which

the particular processor can operate. If lower speeds are desired, the appropriate bus

ratio multiplier can be configured by driving the A[21:16]# pins at reset. For details of

operation at core frequencies lower than the maximum rated processor speed, refer to

the Cedar Mill Processor Family BIOS Writer’s Guide.

The bus ratio multipliers supported are shown in Table 2-1 and Table 2-2. Other

combinations will not be validated or supported by Intel. For a given processor, only the

ratios which result in a core frequency equal to or less than the frequency marked on

the processor are supported.

Table 2-1.

166 MHz Core Frequency to Front Side Bus Multiplier Configuration

(Sheet 1 of 2)

Core Frequency

to Front Side Bus

Multiplier

A21#

A20#

A19#

A18#

A17#

A16#

(166 MHz)

1/15

1/18

2.5 GHz

3 GHz

H

L

H

18

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

Table 2-1.

166 MHz Core Frequency to Front Side Bus Multiplier Configuration

(Sheet 2 of 2)

Core Frequency

to Front Side Bus

Multiplier

A21#

A20#

A19#

A18#

A17#

A16#

(166 MHz)

1/19

1/20

1/21

3.16 GHz

3.33 GHz

3.50 GHz

H

L

H

L

H

L

H

L

Notes:

1.

2.

3.

Individual processors operate only at or below the frequency marked on the package.

Listed frequencies are not necessarily committed production frequencies.

For valid core frequencies of the processor, refer to the Dual-Core Intel® Xeon® Processor 7100 Series

Specification Update.

4.

As described in Section 1.1, “H” refers to a high logic level (i.e. signal asserted) and “L” refers to a low logic

level (i.e. signal deasserted).

Table 2-2.

200 MHz Core Frequency to Front Side Bus Multiplier Configuration

Core Frequency

to Front Side Bus

Multiplier

A21#

A20#

A19#

A18#

A17#

A16#

(200MHz)

1/13

1/15

1/16

1/17

2.6 GHz

3 GHz

H

L

H

L

3.20 GHz

3.40 GHz

H

L

Notes:

1.

2.

3.

Individual processors operate only at or below the frequency marked on the package.

Listed frequencies are not necessarily committed production frequencies.

For valid core frequencies of the processor, refer to the Dual-Core Intel® Xeon® Processor 7100 Series

Specification Update.

4.

As described in Section 1.1, “H” refers to a high logic level (i.e. signal asserted) and “L” refers to a low logic

level (i.e. signal deasserted).

The Dual-Core Intel Xeon processor 7100 series uses a differential clocking

implementation. For more information on the Dual-Core Intel Xeon processor 7100

series clocking, refer to the appropriate clock driver design guidelines.

2.1.2

Front Side Bus Clock Select (BSEL[1:0])

The BSEL[1:0] signals are used to select the frequency of the processor input clock

(BCLK[1:0]). Table 2-3 defines the possible combinations of the signals and the

frequency associated with each combination. The required frequency is determined by

the processor, chipset, and clock synthesizer. All processors must operate at the same

front side bus frequency.

The Dual-Core Intel Xeon processor 7100 series operates at a 667 MTS or 800 MTS

front side bus frequency (selected by a 166 MHz or 200 MHz BCLK[1:0] frequency).

Individual processors operate at the front side bus frequency specified by BSEL[1:0].

For more information about these pins, refer to Section 5.1 and the appropriate

platform design guide.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

19

Electrical Specifications

Table 2-3.

BSEL[1:0] Frequency Table for BCLK[1:0]

BSEL1

BSEL0

Function

0

1

0

1

0

1

RESERVED

200 MHz

166 MHz

2.1.3

Phase Lock Loop (PLL) Power and Filter

V_CCA, V_CCIOPLL, and V_{CCA_CACHE}are power sources required by the PLL clock generators

on the Dual-Core Intel Xeon processor 7100 series. These are analog PLLs and they

require low noise power supplies for minimum jitter. These supplies must be low pass

filtered from V_TT.

The AC low-pass requirements, with input at V_TT, are as follows:

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 2-2. For recommendations on

implementing the filter, refer to the appropriate platform design guide.

Figure 2-2. Phase Lock Loop (PLL) Filter Requirements

0.2 dB

0 dB

-0.5 dB

forbidden

zone

-28 dB

forbidden

zone

-34 dB

DC

passband

1 Hz

fpeak

1 MHz

66 MHz

fcore

high frequency

band

Notes:

1.

2.

Diagram not to scale.

No specification for frequencies beyond f

(core frequency).

core

20

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

3.

4.

f

, if existent, should be less than 0.05 MHz.

represents the maximum core frequency supported by the platform.

peak

core

2.2

Voltage Identification (VID)

The VID[5:0] pins supply the encodings that determine the voltage to be supplied by

the V_CC(the core voltage for the Dual-Core Intel Xeon processor 7100 series) voltage

regulator. The VID specification for the Dual-Core Intel Xeon processor 7100 series is

defined by the Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator

Down (EVRD) 10.2 Design Guidelines. The voltage set by the VID signals is the

maximum V_CCvoltage allowed by the processor. VID signals are open drain outputs,

which must be pulled up to V_TT. Please refer to Table 2-17 for the DC specifications for

these signals. A minimum V_CCvoltage is provided in Table 2-10 and changes with

frequency. This allows processors running at a higher frequency to have a relaxed

minimum V_CCvoltage specification. The specifications have been set such that one

voltage regulator can work with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two

devices at the same core speed may have different default VID settings. Furthermore,

any Dual-Core Intel® Xeon® Processor 7100 Series processor, even those on the same

processor front side bus, can drive different VID settings during normal operation.

The Dual-Core Intel Xeon processor 7100 series uses six voltage identification pins,

VID[5:0], to support automatic selection of power supply voltages. Table 2-4 specifies

the voltage level corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a

high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is

empty (i.e. VID[5:0] = x11111), or the voltage regulation circuit cannot supply the

voltage that is requested, the processor’s voltage regulator must disable itself. See the

Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)

10.2 Design Guidelines for more details.

The Dual-Core Intel Xeon processor 7100 series provides the ability to operate while

transitioning to an adjacent VID and its associated processor core voltage (V_CC). This

will represent a DC shift in the load line. It should be noted that a low-to-high or high-

to-low voltage state change may result in as many VID transitions as necessary to

reach the target core voltage. Transitions above the specified VID are not permitted.

Table 2-10 includes VID step sizes and DC shift ranges. Minimum and maximum

voltages must be maintained as shown in Table 2-11 and Figure 2-4.

The VRM or VRD utilized must be capable of regulating its output to the value defined

by the new VID. DC specifications for VID transitions are included in Table 2-10 and

Table 2-11. Please refer to the Vcc Voltage Regulator Module (VRM) and Enterprise

Voltage Regulator-Down (EVRD) 10.2 Design Guidelines for further details.

Power source characteristics must be guaranteed to be stable whenever the supply to

the voltage regulator is stable.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

21

Electrical Specifications

Table 2-4.

Voltage Identification (VID) Definition

VID5

0

VID4

0

VID3

1

VID2

0

VID1

1

VID0

0

VID (V)

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

VRM off

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

VID5

0

VID4

1

VID3

1

VID2

0

VID1

1

VID0

0

VID (V)

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2.3

Cache Voltage Identification (CVID)

The CVID[3:0] pins supply the encodings that determine the voltage to be supplied by

the V_CACHE(the L3 cache voltage for the Dual-Core Intel Xeon processor 7100 series)

voltage regulator. The CVID specification for the Dual-Core Intel Xeon processor 7100

22

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

series is defined by the VRM 9.1 DC-DC Converter Design Guidelines. The voltage set

by the CVID pins is the maximum V_CACHEvoltage allowed by the processor. A minimum

V_CACHEvoltage is provided in Table 2-10.

Dual-Core Intel Xeon processor 7100 series with the same front side bus frequency,

internal cache sizes, and stepping will have consistent CVID values.

The Dual-Core Intel Xeon processor 7100 series uses four voltage identification pins

(CVID[3:0]) to support automatic selection of power supply voltages. Table 2-5

specifies the voltage level corresponding to the state of CVID[3:0]. A ‘1’ in this table

refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor

socket is empty (in a single processor per regulator design), or if both processor

sockets are empty (in a two processors per regulator design), or the voltage regulation

circuit cannot supply the voltage that is requested, the processor’s voltage regulator

must disable itself. See the VRM 9.1 DC-DC Converter Design Guidelines for more

details.

Table 2-5.

Cache Voltage Identification (CVID) Definition

CVID3

CVID2

CVID1

CVID0

CVID (V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Off

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

Note: The voltage regulator will have a fifth VID input and, for VRM 10.2-compliant regulators, a sixth VID

input as well. The extra input(s) should be tied to a high voltage on the motherboard for correct

operation. Refer to the appropriate platform design guide for further implementation details.

2.4

Reserved, Unused, and TESTHI Pins

All RESERVED pins must be left unconnected. Connection of these pins to V_CC, V_SS, or

to any other signal (including each other) can result in component malfunction or

incompatibility with future processors. See Section 5 for a pin listing for the processor

and the location of all RESERVED pins.

For reliable operation, always terminate unused inputs or bidirectional signals to their

respective deasserted states. On-die termination has been included on the Dual-Core

Intel Xeon processor 7100 series to allow signals to be terminated within the processor

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

23

Electrical Specifications

silicon. Most unused AGTL+ inputs may be left as no-connects since AGTL+ termination

is provided on the processor silicon. See Table 2-7 for details on AGTL+ signals that do

not include on-die termination. Unused active-high inputs should be connected through

a resistor to ground (V_SS). Unused outputs may be left unconnected. However, this may

interfere with some TAP functions, complicate debug probing, and prevent boundary

scan testing. A resistor must be used when tying bidirectional signals to power or

ground. When tying any signal to power or ground, a resistor will also allow for system

testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same

value as the on-die termination resistors (R_TT). See Table 2-15.

Most TAP signals, GTL+ asynchronous inputs, and GTL+ asynchronous outputs do not

include on-die termination (see Table 2-7 for those signals which do not have on-die

termination). Inputs and used outputs must be terminated on the system board.

Unused outputs may be terminated on the system board or left connected. Note that

leaving unused outputs unterminated may interfere with some TAP functions,

complicate debug probing, and prevent boundary scan testing. Signal termination for

these signal types is discussed in the appropriate platform design guide and the

appropriate debug port design guide.

Don’t Care pins are pins on the processor package that are not connected to the

processor die. These pins can be connected on the motherboard in any way necessary

for compatible motherboard designs to support other processor versions.

The TESTHI pins should be tied to V_TTusing a matched resistor, where a matched

resistor has a resistance value within +/-20% of the impedance of the board

transmission line traces. For example, if the trace impedance is 50 Ω, then a value

between 40 Ω and 60 Ω is required.

The TESTHI pins may use individual pull-up resistors or be grouped together as

detailed below. Please note that utilization of boundary scan test will not be functional if

pins are connected together. A matched resistor should be used for each group:

• TESTHI[3:0]

• TESTHI[6:5]

• TESTHI4 --- cannot be grouped with other TESTHI signals

2.5

Mixing Processors

Intel supports and validates multi-processor configurations in which all processors

operate with the same front side bus frequency, core frequency and internal cache

sizes. Mixing processors operating at different internal clock frequencies is not

supported and will not be validated by Intel. Intel does not support or validate

operation of processors with different cache sizes. Mixing different processor steppings

but the same model (as per the CPUID instruction) is supported. Details on CPUID are

provided in the Cedar Mill Processor Family BIOS Writer’s Guide document and the

Intel^®Processor Identification and the CPUID Instruction application note.

The Dual-Core Intel Xeon processor 7100 series does not support mixing of the 7110,

7120, 7130 or 7140 Processor Numbers. The Dual-Core Intel Xeon processor 7100

series does support mixing of the 7150 and 7140 Processor Numbers.

2.6

Front Side Bus Signal Groups

The front side bus signals are grouped by buffer type as listed in Table 2-6. The buffer

type indicates which AC and DC specifications apply to the signals. AGTL+ input signals

have differential input buffers that use GTLREF as a reference level. In this document,

24

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O

group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as

well as the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become

active anytime and include an active pMOS pull-up transistor to assist during the first

clock of a low-to-high voltage transition.

Implementing a source synchronous data bus requires specifying two sets of timing

parameters. One set is for common clock signals which are dependent upon the rising

edge of BCLK0 (ADS#, HIT#, HITM#, etc.). The second set is for the source

synchronous signals that are relative to their respective strobe lines (data and address)

as well as the rising edge of BCLK0. Asynchronous signals are present (A20M#,

IGNNE#, etc.) and can become active at any time during the clock cycle. Table 2-6

identifies signals as common clock, source synchronous, and asynchronous.

Table 2-6.

Front Side Bus Pin Groups

1

Signal Group

Type

Signals

AGTL+ Common Clock Input

Synchronous to BCLK[1:0]

BPRI#, BR[3:1]#, DEFER#, ID[7:0]#, IDS#,

OOD#, RESET#, RS[2:0]#, RSP#, TRDY#

AGTL+ Common Clock I/O

Synchronous to BCLK[1:0]

ADS#, AP[1:0]#, BINIT#, BNR#, BPM[5:0]#,

BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#,

HITM#, LOCK#, MCERR#

AGTL+ Source Synchronous I/ Synchronous to associated

O

strobe

Signals

REQ[4:0]#,

Associated Strobe

ADSTB0#

A[37:36,16:3]#

A[39:38,35:17]#

ADSTB1#

D[15:0]#,

DEP[1:0]#, DBI0#

DSTBP0#,

DSTBN0#

D[31:16]#,

DEP[3:2]#, DBI1#

DSTBP1#,

DSTBN1#

D[47:32]#,

DEP[5:4]#, DBI2#

DSTBP2#,

DSTBN2#

D[63:48]#,

DEP[7:6]#, DBI3#

DSTBP3#,

DSTBN3#

AGTL+ Strobe Input/Output

AGTL+ Asynchronous Output

GTL+ Asynchronous Input

Synchronous to BCLK[1:0]

Asynchronous

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

FERR#/PBE#, IERR#, PROCHOT#

Asynchronous

A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/

INTR, LINT1/NMI, SMI#, STPCLK#

GTL+ Asynchronous Output

TAP Input

Asynchronous

THERMTRIP#

TCK, TDI, TMS

TRST#

Synchronous to TCK

Asynchronous

TAP Input

TAP Output

Synchronous to TCK

Clock

TDO

Front Side Bus Clock Input

SMBus

BCLK[1:0]

Synchronous to SM_CLK

SM_ALERT#, SM_CLK, SM_DAT,

SM_EP_A[2:0], SM_TS_A[1:0], SM_WP

Power/Other

BOOT_SELECT, BSEL[1:0], COMP0,

CVID[3:0], GTLREF[3:0], ODTEN, PWRGOOD,

RESERVED, SKTOCC#, SM_VCC, TEST_BUS,

TESTHI[6:0], V

CC_CACHE_SENSE

VID[5:0], VIDPWRGD, V , V

, V , V

CCIOPLL

,

CACHE

CC

CCA

V

, V

,

CCSENSE

CCPLL

,

SS

SSA

V

, V

, V , VTTEN

SS_CACHE_SENSE

SSSENSE TT

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

25

Electrical Specifications

Notes:

1.

Refer to Section 5.1 for signal descriptions.

Table 2-7.

Signal Description Table

1

Signals with R

TT

2

A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOT_SELECT , BPRI#, D[63:0]#, DBI[3:0]#,

DBSY#, DEFER#, DEP[7:0]#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, ID[7:0]#,

IDS#, LOCK#, MCERR#, OOD#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

Signals with R

L

BINIT#, BNR#, HIT#, HITM#, MCERR#

Notes:

1.

Signals not included in the “Signals with R ” list require termination on the baseboard. Please refer to

Table 2-6 for the signal type and Table 2-17 to Table 2-22 for the corresponding DC specifications.

TT

2.

The BOOT_SELECT pin is not terminated to R . It has a 500-5000 Ω internal pullup.

TT

The ODTEN signals enables or disables R_TT. Those signals affected by ODTEN still

present R_TTtermination to the signal’s pin when the processor is placed in tri-state

mode.

Furthermore, the following signals are not affected when the processor is placed in tri-

state mode: BSEL[1:0], CVID[3:0], SKTOCC#, SM_ALERT#, SM_CLK, SM_DAT,

SM_EP_A[2:0], SM_TS_A[1:0], SM_WP, TEST_BUS, TESTHI[6:0], VID[5:0], and

VTTEN.

Table 2-8.

Signal Reference Voltages

GTLREF

V

/ 2

TT

1

A20M#, A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,

BINIT#, BNR#, BPM[5:0]#, BPRI#, BR[3:0]#,

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DEP[7:0]#,

DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,

FORCEPR#, HIT#, HITM#, ID[7:0]#, IDS#,

IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, LOCK#,

MCERR#, ODTEN, OOD#, REQ[4:0]#, RESET#,

RS[2:0]#, RSP#, SMI#, STPCLK#, TRDY#

BOOT_SELECT, PWRGOOD , TCK , TDI , TMS ,

TRST# , VIDPWRGD

1

Notes:

1.

These signals also have hysteresis added to the reference voltage. See Table 2-20 for more information.

2.7

GTL+ Asynchronous and AGTL+ Asynchronous

Signals

The Dual-Core Intel® Xeon® Processor 7100 Series processor does not utilize CMOS

voltage levels on any signals that connect to the processor silicon. As a result, inputs

signals such as A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,

and STPCLK# utilize GTL buffers. Legacy output THERMTRIP# utilizes a GTL+ output

buffer. All of these asynchronous signals follow the same DC requirements as GTL+

signals; however, the outputs are not driven high (during the logical 0-to-1 transition)

by the processor. FERR#/PBE#, IERR#, and PROCHOT# have now been defined as

AGTL+ asynchronous signals as they include an active pMOS device. GTL+

asynchronous and AGTL+ asynchronous signals do not have setup or hold time

specifications in relation to BCLK[1:0]. However, all of the GTL+ asynchronous and

AGTL+ asynchronous signals are required to be asserted/deasserted for at least six

BCLKs in order for the processor to recognize the proper signal state, except during

power-on configuration. See Table 2-21 for the DC specifications for the GTL+

asynchronous and AGTL+ asynchronous signal groups.

26

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

2.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the TAP logic, Intel

recommends that the Dual-Core Intel® Xeon® Processor 7100 Series processor(s) be

first in the TAP chain, followed by any other components within the system. Use of a

translation buffer to connect to the rest of the chain is recommended unless one of the

other components is capable of accepting an input of the appropriate voltage. Similar

considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two copies of each

signal may be required, each driving a different voltage level.

2.9

Maximum Ratings

Table 2-9 specifies absolute maximum and minimum ratings. Within functional

operation limits, functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long-term reliability can be

expected. If a device is returned to conditions within functional operation limits after

having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded depending on exposure to conditions exceeding the functional operation

condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time then, when returned to conditions within the

functional operating condition limits, it will either not function, or its reliability will be

severely degraded.

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

Table 2-9.

Processor Absolute Maximum Ratings

1,2

Symbol

Parameter

Min

Max

Unit

Notes

V

Processor core supply voltage with

respect to VSS

-0.3

1.55

V

CC

Processor L3 cache voltage with

respect to VSS

-0.3

1.55

V

CACHE

TT

Front side bus termination voltage

with respect to VSS

T

Processor case temperature

See Section 6 See Section 6

-40 85

°C

CASE

Processor storage temperature

3, 4

STORAGE

Notes:

1.

2.

3.

For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must

be satisfied.

Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 3.

Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

Storage temperature is applicable to storage conditions only. In this scenario, the processor must not

receive a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect

the long-term reliability of the device. For functional operation, please refer to the processor case

temperature specifications.

4.

This rating applies to the processor and does not include any packaging or trays.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

27

Electrical Specifications

2.10

Processor DC Specifications

The following notes apply:

• The processor DC specifications in this section are defined at the processor core

silicon and not at the package pins unless noted otherwise.

• The notes associated with each parameter are part of the specification for that

parameter.

• Unless otherwise noted, all specifications in the tables apply to all frequencies and

cache sizes.

• Unless otherwise noted, all the specifications in the tables are based on estimates

and simulations. These specifications will be updated with characterized data from

silicon measurements at a later date.

See Section 5 for the pin signal definitions. Most of the signals on the processor front

side bus are in the AGTL+ signal group. The DC specifications for these signals are

listed in Table 2-19.

Table 2-10 through Table 2-22 list the DC specifications for the Dual-Core Intel®

Xeon® Processor 7100 Series processor and are valid only while meeting specifications

for case temperature, clock frequency, and input voltages.

2.10.1

Flexible Motherboard (FMB) Guidelines

The FMB guidelines are estimates of the maximum values that the Dual-Core Intel Xeon

processor 7100 series processor will have over certain time periods. The values are

only estimates as actual specifications for future processors may differ. The Dual-Core

Intel Xeon processor 7100 series may or may not have specifications equal to the FMB

value in the foreseeable future. System designers should meet the FMB values to

ensure that their systems will be compatible with future releases of the Dual-Core Intel

Xeon processor 7100 series.

Table 2-10. Voltage and Current Specifications (Sheet 1 of 2)

Core

Freq

Symbol

Parameter

Min

Typ

Max

VID

Unit

Notes

VID Range

V

for processor core

All freq

Refer to Table 2-11

1.1000 -

1.3500

V

1,2,3,

4,5,7

CC

VID Transition

VID step size during

transition

All freq.

12.5

450

mV

V

18

19

17

Total allowable DC load line

shift from VID steps

CVID Range

V

for processor L3 cache

Refer to Table 2-12 or Table 2-13

1.1000 -

1.3500

CC

V

FSB termination voltage

(DC specification)

1.176

1.140

3.135

1.20

1.224

1.260

V

11,12,

13

TT

FSB termination voltage

(AC specification)

All freq.

V

11,12,

13,14

TT

SM_VCC

SMBus supply voltage

All freq.

All freq

3.300

3.465

135

V

A

13

7,10

20

I

for processor core

CC

Core Thermal Design

Current (TDC)

115

CC_TDC

I

for processor L3 cache

CC

All freq

40

A

CACHE

28

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

Table 2-10. Voltage and Current Specifications (Sheet 2 of 2)

Core

Freq

Symbol

Parameter

Min

Typ

Max

VID

Unit

Notes

I

Cache Thermal Design

Current (TDC)

All freq

35

A

CACHE_TDC

I

FSB termination current

FSB mid-agent current

All freq.

4

1.3

122.5

70

A

11,15

11,16

11

TT

I

for SMBus supply

Stop-Grant Core

Stop-Grant Cache

100

mA

A

SM_VCC

SGnt_CORE

SGnt_CACHE

TCC

CC

I

6,9

CC

I

35

A

6,9

CC

I

TCC active

for PLL pin

I

A

8

CC

I

60

mA

µA

CC VCCA

CC VCCIOPLL

CC VCCA_CACHE

CC GTLREF

I

for I/O PLL pin

CC

I

for L3 cache PLL pin

60

CC

I

per GTLREF pin

200

CC

Notes:

1.

2.

These voltages and frequencies are targets only. A variable voltage source should exist on systems in the event that a

different voltage is required. See Section 2.2 and Table 2-4 for more information.

The voltage specification requirements are measured across the V

and V

pins using an oscilloscope set to a

CCSENSE

SSSENSE

100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 MΩ minimum impedance at the processor socket.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not

coupled into the scope probe.

3.

Refer to Table 2-11 for the minimum, typical, and maximum V allowed for a given current. The processor should not be

CC

subjected to any V and I combination wherein V exceeds V for a given current.

CC_MAX

CC

4.

5.

6.

7.

Moreover, V should never exceed the VID voltage. Failure to adhere to this specification can shorten the processor lifetime.

CC

V

and V

are defined at the frequency’s associated I

on the V load line.

CC_MIN

CC_MAX

CC_MAX CC

The current specified is also for the HALT State.

FMB is the Flexible Motherboard guideline. These guidelines are for estimation purposes only. See Section 2.10.1 for further

details on FMB guidelines.

The maximum instantaneous current the processor will draw while the thermal control circuit (TCC) is active as indicated by

8.

the assertion of PROCHOT# is the same as the maximum I for the processor.

CC

9.

The core and cache portions of Stop-Grant current is specified at V and V

max.

CC

CACHE

10. Icc_Max specification is based on Vcc Maximum loadline. Refer to Figure 2-4 for details

11. These parameters are based on design characterization and are not tested.

12.

V

must be provided via a separate voltage source and must not be connected to V

.

TT

CC

13. These specifications are measured at the package pin.

14. Baseboard bandwidth is limited to 20 MHz.

15. This specification refers to a single processor with R enabled.

TT

16. This specification refers to a single processor with R disabled.

TT

17. The voltage specification requirements are measured across the V

and V

pins at the socket with

CC_CACHE_SENSE

SS_CACHE_SENSE

a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length

of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the scope

probe.

18. This specification represents the V reduction due to each VID transition. See Section 2.2.

CC

19. This specification refers to the total reduction of the load line due to VID transitions below the specified VID.

20.

I

is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used for

CC_TDC

the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its temperature and

asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable design guidelines for

further details. The processor is capable of drawing I

indefinitely. Refer to Figure 2-3 for further details on the average

CC_TDC

processor current draw over various time durations. This parameter is based on design characterization and is not tested.

is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used

21.

I

CACHE_TDC

for the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its temperature and

asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable design guidelines for

further details. The processor is capable of drawing I

and is not tested.

indefinitely. This parameter is based on design characterization

CACHE_TDC

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

29

Electrical Specifications

Figure 2-3. Dual-Core Intel® Xeon® Processor 7100 Series Load Current vs. Time

1 4 0

1 3 5

1 3 0

1 2 5

1 2 0

1 1 5

1 1 0

0 .0 1

0 .1

1

1 0

1 0 0

1 0 0 0

T im e D u r a tio n (s )

Notes:

1.

Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than

I

.

CC_TDC

2.

Not 100% tested. Specified by design characterization.

30

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

Table 2-11. V_CCStatic and Transient Tolerance

I_CC[A]

V_{CC_MAX}[V]

V_{CC_TYP}[V]

V_{CC_MIN}[V]

Notes

0

VID - 0.000

VID - 0.006

VID - 0.013

VID - 0.019

VID - 0.025

VID - 0.031

VID - 0.038

VID - 0.044

VID - 0.050

VID - 0.056

VID - 0.063

VID - 0.069

VID - 0.075

VID - 0.081

VID - 0.087

VID - 0.094

VID - 0.100

VID - 0.106

VID - 0.113

VID - 0.119

VID - 0.125

VID - 0.131

VID - 0.138

VID - 0.144

VID - 0.150

VID - 0.156

VID - 0.163

VID - 0.169

VID - 0.020

VID - 0.026

VID - 0.033

VID - 0.039

VID - 0.045

VID - 0.051

VID - 0.058

VID - 0.064

VID - 0.070

VID - 0.076

VID - 0.083

VID - 0.089

VID - 0.095

VID - 0.101

VID - 0.108

VID - 0.114

VID - 0.120

VID - 0.126

VID - 0.133

VID - 0.139

VID - 0.145

VID - 0.151

VID - 0.158

VID - 0.164

VID - 0.170

VID - 0.176

VID - 0.183

VID - 0.189

VID - 0.040

VID - 0.046

VID - 0.053

VID - 0.059

VID - 0.065

VID - 0.071

VID - 0.078

VID - 0.084

VID - 0.090

VID - 0.096

VID - 0.103

VID - 0.109

VID - 0.115

VID - 0.121

VID - 0.128

VID - 0.134

VID - 0.140

VID - 0.146

VID - 0.153

VID - 0.159

VID - 0.165

VID - 0.171

VID - 0.178

VID - 0.184

VID - 0.190

VID - 0.196

VID - 0.203

VID - 0.209

1,2,3

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

80

85

90

95

100

105

110

115

120

125

130

135

Notes:

1.

2.

3.

The V

and V

load lines represent static and transient limits.

CC_MAX

CC_MIN

This table is intended to aid in reading discrete points on Figure 2-4.

The load lines specify voltage limits at the die measured at the V

and V

pins. Voltage

SSSENSE

CCSENSE

regulation feedback for voltage regulator circuits must be taken from processor V and V pins. Refer to

CC

SS

the Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 10.2 Design

Guidelines for socket load line guidelines and VR implementation.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

31

Electrical Specifications

Figure 2-4. V_CCStatic and Transient Tolerance

Icc [A]

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135

VID- 0.000

VID- 0.050

VID- 0.100

VID- 0.150

VID- 0.200

VID- 0.250

V_CC

Max imum

V_CC

Typical

V_CC

Minimum

Notes:

1.

2.

3.

The V

and V

load lines represent static and transient limits.

CC_MAX

CC_MIN

Refer to Table 2-10 for processor VID information for V

The load lines specify voltage limits at the die measured at the V

.

CC

and V

pins. Voltage

SSSENSE

CCSENSE

regulation feedback for voltage regulator circuits must be taken from processor V and V pins. Refer to

CC

SS

the Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 10.2 Design

Guidelines for socket load line guidelines and VR implementation.

32

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

Table 2-12. V_CACHEStatic and Transient Tolerance at the Die Sense Location

I_CACHE[A]

V_{CACHE_MAX}[V]

V_{CACHE_TYP}[V]

V_{CACHE_MIN}[V]

Notes

1,2

0

CVID - 0.000

CVID - 0.021

CVID - 0.043

CVID - 0.064

CVID - 0.085

CVID - 0.106

CVID - 0.128

CVID - 0.149

CVID - 0.170

CVID - 0.041

CVID - 0.065

CVID - 0.089

CVID - 0.113

CVID - 0.138

CVID - 0.162

CVID - 0.186

CVID - 0.210

CVID - 0.234

CVID - 0.082

CVID - 0.109

CVID - 0.136

CVID - 0.163

CVID - 0.190

CVID - 0.217

CVID - 0.244

CVID - 0.271

CVID - 0.298

5

10

15

20

25

30

35

40

Notes:

1.

I

refers to the current drawn by a single Dual-Core Intel® Xeon® Processor 7100 Series cache. The

CACHE

CACHE_MIN

V

loadline assumes two Dual-Core Intel® Xeon® Processor 7100 Series caches are powered off

one VRM and that the second cache is drawing I

= 40A.

CACHE_MAX

2.

and V

are VRM voltage regulation requirements measured across the V

and

VRM_MAX

VRM_MIN

CC_CACHE_SENSE

V

pins at the socket.

SS_CACHE_SENSE

Figure 2-5. V_CACHEStatic and Transient Tolerance at the Die Sense Location

Icache [A]

0

5

10

15

20

25

30

35

40

CVID - 0.000

CVID - 0.050

CVID - 0.100

CVID - 0.150

CVID - 0.200

CVID - 0.250

CVID - 0.300

V_Cache

Maximum

V_Cache

Typical

V_Cache

Minimum

Notes:

1.

I

refers to the current drawn by a single Dual-Core Intel Xeon processor 7100 series cache. The

CACHE

CACHE_MIN

V

loadline assumes two Dual-Core Intel Xeon processor 7100 series caches are powered off one

VRM and that the second cache is drawing I

= 40A.

CACHE_MAX

2.

and V

are VRM voltage regulation requirements measured across the V

and

VRM_MAX

VRM_MIN

CC_CACHE_SENSE

V

pins at the socket.

SS_CACHE_SENSE

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

33

Electrical Specifications

Table 2-13. V_CACHEStatic and Transient Tolerance at the Board

I_CACHE[A]

V_{CACHE_MAX}[V]

V_{CACHE_TYP}[V]

V_{CACHE_MIN}[V]

Notes

1,2

0

CVID - 0.000

CVID - 0.003

CVID - 0.006

CVID - 0.009

CVID - 0.011

CVID - 0.014

CVID - 0.017

CVID - 0.020

CVID - 0.023

CVID - 0.041

CVID - 0.044

CVID - 0.048

CVID - 0.051

CVID - 0.055

CVID - 0.058

CVID - 0.061

CVID - 0.065

CVID - 0.068

CVID - 0.082

CVID - 0.086

CVID - 0.090

CVID - 0.094

CVID - 0.098

CVID - 0.102

CVID - 0.106

CVID - 0.110

CVID - 0.114

5

10

15

20

25

30

35

40

Notes:

1.

I

refers to the current drawn by a single Dual-Core Intel Xeon processor 7100 series cache. The

CACHE

V

loadline assumes two Dual-Core Intel Xeon processor 7100 series caches are powered off one

CACHE_MIN

VRM and that the second cache is drawing I

V

= 40A.

CACHE_MAX

2.

and V

are VRM voltage regulation requirements measured at the power plane reference

VRM_MAX

VRM_MIN

point (the VRM remote-sense point is on the system board, not at the socket.)

Figure 2-6. V_CACHEStatic and Transient Tolerance at the Board

Icache [A]

0

5

10

15

20

25

30

35

40

CVID - 0.000

CVID - 0.020

CVID - 0.040

CVID - 0.060

CVID - 0.080

CVID - 0.100

CVID - 0.120

V_Cache

Maximum

V_Cache

Typical

V_Cache

Minimum

2.10.2

V

Overshoot Specification

CC

The Dual-Core Intel Xeon processor 7100 series can tolerate short transient overshoot

events where V_CCexceeds the VID voltage when transitioning from a high-to-low

current load condition. This overshoot cannot exceed VID + V_{OS_MAX}. (V_{OS_MAX}is the

maximum allowable overshoot above VID). These specifications apply to the processor

die voltage as measured across the V_CCSENSEand V_SSSENSEpins.

34

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

Table 2-14. V_CCOvershoot Specification

Symbol

Parameter

Min

Max

Units

Figure

Notes

Magnitude of V

CC

V

0.025

V

2-7

OS_MAX

overshoot above VID

Time duration of V

CC

T

5

μs

2-7

OS_MAX

overshoot above VID

Figure 2-7. V_CCOvershoot Example Waveform

2.10.3

V

Overshoot Specification

CACHE

The Dual-Core Intel Xeon processor 7100 series can tolerate short transient overshoot

events where V_CACHEexceeds the V_CACHEmaximum loadline voltage when transitioning

from a high-to-low current load condition. This overshoot cannot exceed V_{CACHE_MAX}

VOS_cache_MAX. (VOS_cache_MAX is the maximum allowable overshoot above

+

V_{CACHE_MAX}at the low current load). These specifications apply to the processor cache

voltage as measured across the V_{CC_CACHE_SENSE}and V_{SS_CACHE_SENSE}pins.

Table 2-15. V_CACHEOvershoot Specification

Symbol

Parameter

Magnitude of V

Min

Max

Units

Figure

Notes

CACHE

V

T

overshoot above

0.025

V

2-8

1

OS_CACHE_MAX

V

CACHE_MAX

Time duration of V

CACHE

overshoot above

50

μs

2-8

OS_CACHE_MAX

V

CACHE_MAX

Note:

1.

V

is defined in Table 2-12 and Table 2-13 where I

is the low, ending current of the high-to-

CACHE_MAX

CACHE

low current load condition.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

35

Electrical Specifications

Figure 2-8. V_CACHEOvershoot Example Waveform

Vcache Overshoot Example Waveform

Vcache_max after

unloading transient

VOS_cache

TOS_cache

Vcache_max prior to

unloading transient

Time (10 µs per division)

Notes:

1.

2.

V

is measured overshoot voltage.

is measured time duration above Vcache_max.

OS_CACHE

T

2.10.4

2.10.5

Die Voltage Validation

Overshoot events from application testing on the processor must meet the

specifications in Table 2-14 when measured across the V_CCSENSEand V_SSSENSEpins and

Table 2-15 when measured across the V_{CC_CACHE_SENSE}and V_{SS_CACHE_SENSE}pins.

Overshoot events that are < 10 ns in duration may be ignored. These measurements of

processor die level overshoot should be taken with a 100 MHz bandwidth limited

oscilloscope.

Clock, Miscellaneous and AGTL+ Specifications

Table 2-16. Front Side Bus Differential BCLK Specifications (Sheet 1 of 2)

Symbol

VL

Parameter

Min

Typ

Max

Unit

Notes

Input Low Voltage

Input High Voltage

-0.150

0.660

0.250

0.000

0.700

N/A

V

VH

0.850

0.550

VCROSS(abs)

Absolute Crossing

Point

1,7

VCROSS(rel)

Δ VCROSS

VOV

Relative Crossing

Point

0.250 + 0.5*

Havg

N/A

0.550 + 0.5*

Havg

V

2,7,8

(V

- 0.700)

(V

- 0.700)

Range of Crossing

Point

N/A

0.140

+ 0.300

Overshoot

3

36

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

Table 2-16. Front Side Bus Differential BCLK Specifications (Sheet 2 of 2)

Symbol

VUS

Parameter

Min

Typ

Max

Unit

Notes

Undershoot

- 0.300

0.200

N/A

V

4

5

6

VRBM

VTM

Ringback Margin

Threshold Margin

V

-0.100

V

+0.100

CROSS

Notes:

1.

Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to

the falling edge of BCLK1.

2.

3.

4.

5.

V

is the statistical average of the V measured by the oscilloscope.

Havg H

Overshoot is defined as the absolute value of the maximum voltage.

Undershoot is defined as the absolute value of the minimum voltage.

Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback

and the maximum Falling Edge Ringback.

6.

Threshold Region is defined as a region entered around the crossing point voltage in which the differential

receiver switches. It includes input threshold hysteresis.

7.

8.

The crossing point must meet the absolute and relative crossing point specifications simultaneously.

Havg

V

can be measured directly using “Vtop” on Agilent scopes and “High” on Tektronix scopes.

Table 2-17.BSEL[1:0], VID[5:0], and CVID[3:0] DC Specifications

Symbol

Parameter

Typ

Max

Unit

Notes

R

Buffer On Resistance

Pull up resistor to 3.3V

Max Pin Current

80

Ω

1

2

ON

Rpull_up

1000

I

8

mA

µA

V

OL

LO

Output Leakage Current

Voltage Tolerance

200

3

4

V

3.3 * 1.05

TOL

Notes:

1.

2.

These parameters are not tested and are based on design simulations.

®

Pull up each line to 3.3 V using 1 KΩ, 5% resistor. Refer to 64-bit Intel Xeon™ Processor MP Platform

Design Guide.

3.

4.

Leakage to V with pin held at 2.5 V.

SS

Represents the maximum allowable termination voltage.

Table 2-18. VIDPWRGD DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes

V

Input Low Voltage

Input High Voltage

0.0

0.30

V

IL

IH

0.90

V

TT

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

37

Electrical Specifications

Table 2-19. AGTL+ Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes

VIL

Input Low Voltage

Input High Voltage

Output High Voltage

Output Low Current

0.0

GTLREF - (0.10 * V

)

V

1,3

2,3

3

TT

VIH

VOH

IOL

GTLREF + (0.10 * V

)

V

TT

0.90 * V

N/A

V

TT

V

/

mA

5

TT

(0.50 * Rtt_min +

RON_min || R )

L

ILI

Input Leakage Current

Output Leakage Current

Buffer On Resistance

N/A

8

± 200

12

µA

Ω

4

6

ILO

RON

Notes:

1.

2.

3.

4.

5.

V_ILis defined as the voltage level at a receiving agent that will be interpreted as a logical low value.

V_IHis defined as the voltage level at a receiving agent that will be interpreted as a logical high value.

The V_TTreferred to in these specifications refers to the instantaneous V .

TT

Leakage to V with pin held at V

The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load.

.

SS

TT

6.

Leakage to V with pin held at 300 mV.

TT

Table 2-20. PWRGOOD and TAP Signal Group DC Specifications

1

Symbol

Parameter

Min

Max

Unit

Notes

V

Input Hysteresis

120

396

mV

V

5

HYS

PWRGOOD Input Low to

High Threshold Voltage

0.5 (V + V

+

0.5 * (V + V

HYS_MAX

+

)

3, 6

TT

HYS_MIN

TT

0.24)

0.5 * (V + V

HYS_MAX

V_T+

TAP Input Low to High

Threshold Voltage

0.5 * (V + V

)

V

3

TT

HYS_MIN

TT

PWRGOOD Input High to

Low Threshold Voltage

0.4 * V_TT

0.6 * V_TT

V_T-

TAP Input High to Low

Threshold Voltage

0.5 * (V - V

)

0.5 * (V - V

)

HYS_MIN

TT

HYS_MAX

TT

V

Output High Voltage

Output Low Current

N/A

V

mA

µA

Ω

2,3

4

OH

OL

LI

TT

I

45

±200

12

Input Leakage Current

Output Leakage Current

Buffer On Resistance

LO

R

8

7

ON

TDO Buffer On

Resistance

12

Ω

Notes:

1.

2.

3.

4.

All outputs are open drain.

TAP signal group must meet system signal quality specification in Chapter 3.

The V referred to in these specifications refers to instantaneous V .

The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load.

V

TT

5.

6.

represents the amount of hysteresis, nominally centered about 0.5 * V for all TAP inputs.

HYS TT

0.24 V is defined at 20% of nominal V of 1.2 V.

TT

38

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Electrical Specifications

Table 2-21. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group

DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes

VIL

VIH

VIL

Input Low Voltage

Input High Voltage

0

GTLREF - (10% * V

)

V

2

3,4

2

TT

GTLREF + (10% * V

)

V

TT

A20M#, SMI#, IGNNE#

Input Low Voltage

0

0.4 * V

TT

VIH

A20M#, SMI#, IGNNE#

Input High Voltage

0.6 * V

V

3,4

TT

VOH

IOL

ILI

Output High Voltage

Output Low Current

V

mA

µA

Ω

1,4

5

50

Input Leakage Current

Output Leakage Current

Buffer On Resistance

N/A

8

± 200

12

6

ILO

Ron

7

Notes:

1.

2.

3.

4.

5.

All outputs are open-drain.

V

is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

TT

IL

IH

The V referred to in these specifications refers to instantaneous V .

TT

The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load.

6.

7.

Leakage to V with pin held at V

SS TT

Leakage to V with pin held at 300 mV.

TT

Table 2-22. SMBus Signal Group DC Specifications

1,2

Symbol

Parameter

Min

Max

Unit

Notes

V

Input Low Voltage

Input High Voltage

-0.30

0.30 * SM_VCC

3.465

V

IL

IH

OL

LI

V

0.70 * SM_VCC

Output Low Voltage

Output Low Current

Input Leakage Current

Output Leakage Current

SMBus Pin Capacitance

0

0.400

V

I

N/A

3.0

mA

µA

pF

± 10

LO

C

15.0

3

SMB

Notes:

1.

2.

3.

These parameters are based on design characterization and are not tested.

All DC specifications for the SMBus signal group are measured at the processor pins.

Platform designers may need this value to calculate the maximum loading of the SMBus and to determine

maximum rise and fall times for SMBus signals.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

39

Electrical Specifications

2.11

AGTL+ Front Side Bus Specifications

Routing topology recommendations are in the appropriate platform design guide.

Termination resistors are not required for most AGTL+ signals because they are

integrated into the processor silicon.

Valid high and low levels are determined by the input buffers which compare a signal’s

voltage with a reference voltage called GTLREF.

Table 2-23 lists the GTLREF specifications. GTLREF should be generated on the system

board using high-precision voltage divider circuits. For more details on platform design,

see the appropriate platform design guide.

Table 2-23. AGTL+ Bus Voltage Definitions

Symbol

GTLREF

Parameter

Min

Typ

Max

Units

Notes

Bus Reference

Voltage

0.98 * (0.63 *

0.63 * V

1.02 * (0.63 *

V

1,2,6

TT

V

)

V )

TT

R

Termination

45

50

55

Ω

3

4

TT

L

Resistance (pull-up)

Termination

Resistance (pull-

down)

360

450

540

COMP0

COMP Resistance

49.4

49.9

50.4

Ω

5

Notes:

1.

The tolerances for this specification have been stated generically to enable system designers to calculate

the minimum values across the range of V_TT.

2.

3.

4.

5.

GTLREF is generated from V_TTon the baseboard by a voltage divider of 1% resistors.

R_TTis the on-die termination resistance measured at V /2 of the AGTL+ output driver.

TT

R_Lis the on-die termination resistance for improved noise margin and signal integrity.

The COMP0 resistor is provided by the baseboard with 1% resistors. See the appropriate platform design

guide for implementation details.

6.

The V_TTreferred to in these specifications refers to instantaneous V_TT.

§

40

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Mechanical Specifications

3 Mechanical Specifications

The Dual-Core Intel Xeon processor 7100 series is packaged in a Flip-Chip Micro Pin

Grid Array 6 (FC-mPGA6) package that interfaces with the motherboard via a mPGA604

socket. The package consists of a processor core mounted on a substrate pin-carrier.

An integrated heat spreader (IHS) is attached to the package substrate and core and

serves as the mating surface for processor component thermal solutions, such as a

heatsink. Figure 3-1 shows a sketch of the processor package components and how

they are assembled together. Refer to the mPGA604 Socket Design Guidelines for

complete details on the mPGA604 socket.

The package components shown in Figure 3-1 include the following:

1. Integrated Heat Spreader (IHS)

2. Processor die

3. FC-mPGA6 package

4. Pin-side capacitors

5. Package pin

Figure 3-1. Processor Package Assembly Sketch

1

2

3

4

5

Note:

This drawing is not to scale and is for reference only. The mPGA604 socket is not

shown.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

41

Mechanical Specifications

3.1

Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The

drawings include dimensions necessary to design a thermal solution for the processor.

These dimensions include:

1. Package reference with tolerances (total height, length, width, etc.)

2. IHS parallelism and tilt

3. Pin dimensions

4. Top-side and back-side component keep-out dimensions

5. Reference datums

All drawing dimensions are in millimeters.

42

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Mechanical Specifications

Figure 3-2. Processor Package Drawing (Sheet 1 of 2)

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

43

Mechanical Specifications

Figure 3-3. Processor Package Drawing (Sheet 2 of 2)

44

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Mechanical Specifications

3.2

3.3

Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-

out zone requirements. A thermal and mechanical solution design must not intrude into

the required keep-out zones. Decoupling capacitors are typically mounted to either the

topside or pin-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout

zones.

Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package.

These mechanical load limits should not be exceeded during heatsink assembly,

shipping conditions, or standard use condition. Also, any mechanical system or

component testing should not exceed the maximum limits. The processor package

substrate should not be used as a mechanical reference or load-bearing surface for

thermal and mechanical solutions. The minimum loading specification must be

maintained by any thermal and mechanical solution.

Table 3-1.

Processor Loading Specifications

Parameter

Minimum

Maximum

Unit

Notes

Static Compressive

Load

44

10

222

50

N

lbf

1, 2, 3, 4

44

10

288

65

N

1, 2, 3, 5

1, 3, 4, 6, 7

1, 3, 5, 6, 7

1, 3, 8

lbf

Dynamic

Compressive Load

222 N + 0.45 kg * 100 G

50 lbf (static) + 1 lbm * 100 G

N

lbf

288 N + 0.45 kg * 100 G

65 lbf (static) + 1 lbm * 100 G

N

lbf

Transient

445

100

N

lbf

Notes:

1.

2.

3.

These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top

surface.

This is the minimum and maximum static force that can be applied by the heatsink and retention solution

to maintain the heatsink and processor interface.

These parameters are based on limited testing for design characterization. Loading limits are for the

package only and do not include the limits of the processor socket.

4.

5.

This specification applies for thermal retention solutions that allow baseboard deflection.

This specification applies either for thermal retention solutions that prevent baseboard deflection or for the

Intel enabled reference solution (CEK).

6.

7.

Dynamic loading is defined as an 11 ms duration average load superimposed on the static load

requirement.

Experimentally validated test condition used a heatsink mass of 1 lbm (~0.45 kg) with 100 G acceleration

measured at heatsink mass. The dynamic portion of this specification in the product application can have

flexibility in specific values, but the ultimate product of mass times acceleration should not exceed this

validated dynamic load (1 lbm x 100 G = 100 lb).

8.

Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement,

representative of loads experienced by the package during heatsink installation.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

45

Mechanical Specifications

3.4

Package Handling Guidelines

Table 3-2 includes a list of guidelines on package handling in terms of recommended

maximum loading on the processor IHS relative to a fixed substrate. These package

handling loads may be experienced during heatsink removal.

Table 3-2.

Package Handling Guidelines

Parameter

Maximum Recommended

Notes

Shear

Tensile

Torque

356 N [80 lbf]

156 N [35 lbf]

1, 4, 5

2, 4, 5

3, 4, 5

8 N-m [70 lbf-in]

Notes:

1.

2.

3.

A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.

A tensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface.

A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top

surface.

4.

5.

These guidelines are based on limited testing for design characterization and incidental applications (one

time only).

Handling guidelines are for the package only and do not include the limits of the processor socket.

3.5

3.6

Package Insertion Specifications

The Dual-Core Intel Xeon processor 7100 series can be inserted into and removed from

a mPGA604 socket 15 times. The socket should meet the mPGA604 requirements

detailed in the mPGA604 Socket Design Guidelines.

Processor Mass Specifications

The typical mass of the Dual-Core Intel Xeon processor 7100 series is 34 g [1.20 oz].

This mass [weight] includes all the components that are included in the package.

3.7

Processor Materials

Table 3-3 lists some of the package components and associated materials.

Table 3-3.

Processor Materials

Component

Material

Integrated Heat Spreader (IHS)

Substrate

Nickel Plated Copper

Fiber-Reinforced Resin

Gold Plated Copper

Substrate Pins

3.8

Processor Markings

Figure 3-4 shows the topside markings and Figure 3-5 shows the bottom-side markings

on the processor. These diagrams are to aid in the identification of the Dual-Core Intel

Xeon processor 7100 series.

46

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Mechanical Specifications

Figure 3-4. Processor Topside Markings

2D Matrix

Includes ATPO and Serial

Number (front end mark)

Processor Name

i(m) ©’05

Pin 1 Indicator

Notes:

1.

2.

All characters will be in upper case.

Drawing is not to scale.

Figure 3-5. Processor Bottom-Side Markings

Pin 1 Indicator

Processor/Speed/Cache/Bus

Number

Pin Field

7140M 3400/16M/800

SL9HA COSTA RICA

C0096109-0021

S-Spec

Country of Assy

Cavity

with

Components

FPO – Serial #

(13 Characters)

Text Line1

Text Line2

Text Line3

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

47

Mechanical Specifications

3.9

Processor Pin-Out Coordinates

Figure 3-6 shows the top view of the processor pin coordinates. The coordinates are

referred to throughout the document to identify processor pins.

Figure 3-6. Processor Pin-Out Coordinates, Top View

COMMON

ADDRESS

COMMON

CLOCK

Async /

JTAG

CLOCK

1

3

5

7

9

11 13

15 17 19

21 23 25

27

29

31

A

B

A

B

C

D

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

Processor

Top View

R

T

U

V

W

Y

U

V

W

Y

AA

AB

AC

AD

AB

AC

AD

AE

2

4

6

8

10 12 14

16 18

20 22

24 26 28

30

CLOCKS

DATA

= Signal

= VCC

= Ground

= VTT

= Reserved/No Connect

= VCache

§

48

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Pin Listing

4 Pin Listing

4.1

Dual-Core Intel® Xeon® Processor 7100 Series

Pin Assignments

Section 2.6 contains the front side bus signal groups for the Dual-Core Intel Xeon

processor 7100 series (see Table 2-6). This section provides a sorted pin list in

Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor pins ordered

alphabetically by pin name. Table 4-2 is a listing of all processor pins ordered by pin

number.

4.1.1

Pin Listing by Pin Name

Table 4-1. Pin Listing by Pin Name

(Sheet 2 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 1 of 16)

Signal Buffer

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

Type

A30#

A31#

C11

B7

Source Sync

Async GTL+

Common Clk

Source Sync

Common Clk

FSB Clk

Input/Output

Source Sync

Input

A3#

A4#

A22

A20

B18

C18

A19

C17

D17

A13

B16

B14

B13

A12

C15

C14

D16

D15

F15

A10

B10

B11

C12

E14

D13

A9

Source Sync

Input/Output

A32#

A6

A5#

A33#

A7

A6#

A34#

C9

A7#

A35#

C8

A8#

A36#

F16

F22

B6

A9#

A37#

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

A28#

A29#

A38#

A39#

C16

F27

D19

F17

F14

E10

D9

A20M#

ADS#

Input/Output

Input

ADSTB0#

ADSTB1#

AP0#

AP1#

BCLK0

BCLK1

BINIT#

BNR#

Y4

W5

F11

F20

G7

F6

FSB Clk

Input

Common Clk

Power/Other

Common Clk

Input/Output

Input

BOOT_SELECT

BPM0#

BPM1#

BPM2#

BPM3#

BPM4#

BPM5#

Input/Output

F8

E7

F5

B8

E8

E13

D12

E4

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

49

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 3 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 4 of 16)

Signal Buffer

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

Type

BPRI#

BR0#

BR1#

BR2#

BR3#

BSEL0

BSEL1

COMP0

CVID0

CVID1

CVID2

CVID3

D0#

D23

D20

Common Clk

Power/Other

Source Sync

Input

D28#

D29#

D30#

D31#

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

D41#

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#

DBI0#

DBI1#

DBI2#

DBI3#

AE20

AD21

AD19

AB17

AB16

AA16

AC17

AE13

AD18

AB15

AD13

AD14

AD11

AC12

AE10

AC11

AE9

Source Sync

Input/Output

Input

F12

E11

Input

D10

Input

AA3

Output

AB3

Output

AD16

E2

Input

Output

D1

Output

C2

Output

A2

Output

Y26

Input/Output

D1#

AA27

Y24

D2#

D3#

AA25

AD27

Y23

D4#

D5#

AD10

AD8

D6#

AA24

AB26

AB25

AB23

AA22

AA21

AB20

AB22

AB19

AA19

AE26

AC26

AD25

AE25

AC24

AD24

AE23

AC23

AA18

AC20

AC21

AE22

D7#

AC9

D8#

AA13

AA14

AC14

AB12

AB13

AA11

AA10

AB10

AC8

D9#

D10#

D11#

D12#

D13#

D14#

D15#

D16#

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

D26#

D27#

AD7

AE7

AC6

AC5

AA8

Y9

AB6

AC27

AD22

AE12

AB9

50

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 5 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 6 of 16)

Signal Buffer

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

Type

DBSY#

DEFER#

DEP0#

F18

C23

AD31

AD30

AE16

AE15

AE8

AD6

AC4

AA4

AC18

AE19

AC15

AE17

E18

Y21

Y18

Y15

Y12

Y20

Y17

Y14

Y11

B4

Common Clk

Source Sync

Common Clk

Source Sync

Input/Output

Input

ID1#

ID2#

B26

D25

D27

C28

B29

B30

A30

A28

E5

Common Clk

Async GTL+

Common Clk

Power/Other

Common Clk

Async GTL+

Source Sync

Input

Input/Output

ID3#

Input

DEP1#

ID4#

Input

DEP2#

ID5#

Input

DEP3#

ID6#

Input

DEP4#

ID7#

Input

DEP5#

IDS#

Input

DEP6#

IERR#

Output

DEP7#

IGNNE#

INIT#

C26

D6

Input

DP0#

Input

DP1#

LINT0/INTR

LINT1/NMI

LOCK#

B24

G23

A17

D7

Input

DP2#

Input

DP3#

Input/Output

Input

DRDY#

MCERR#

ODTEN

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

Don’t Care

FERR#/PBE#

FORCEPR#

GTLREF0

GTLREF1

GTLREF2

GTLREF3

HIT#

B5

OOD#

D29

B25

AB7

B19

B21

C21

C20

B22

A31

E16

W3

Input

PROCHOT#

PWRGOOD

REQ0#

REQ1#

REQ2#

REQ3#

REQ4#

Reserved

RESET#

RS0#

Output

Input

Input/Output

A4

C1

C5

AC1

AC30

AE2

AE3

E27

A15

W23

W9

Y27

Y28

AE30

Y8

Common Clk

Power/Other

SMBus

Input

Async GTL+

Power/Other

Common Clk

Output

Input

E21

D22

F21

C6

RS1#

Input

RS2#

Input

RSP#

Input

F23

F9

Input

SKTOCC#

SM_ALERT#

SM_CLK

SM_DAT

SM_EP_A0

A3

Output

Input

AD28

AC28

AC29

AA29

E22

A23

A26

Input/Output

Input

SMBus

HITM#

SMBus

Input/Output

Input

ID0#

SMBus

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

51

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 7 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 8 of 16)

Signal Buffer

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

Type

SM_EP_A1

SM_EP_A2

SM_TS1_A0

SM_TS1_A1

SM_VCC

SM_WP

AB29

AB28

AA28

Y29

AE28

AE29

AD29

C27

D4

SMBus

Input

V

N3

N5

Power/Other

CACHE

SMBus

N7

SMBus

N9

Power/Other

SMBus

R1

R3

Input

Output

Input

Output

Input

R5

SMI#

Async GTL+

TAP

R7

STPCLK#

TCK

R9

E24

C24

E25

A16

W6

W7

W8

Y6

U1

TDI

TAP

U3

TDO

TAP

U5

TEST_BUS

TESTHI0

TESTHI1

TESTHI2

TESTHI3

TESTHI4

TESTHI5

TESTHI6

THERMTRIP#

TMS

Power/Other

Async GTL+

TAP

U7

U9

V

A8

CC

A14

A18

A24

B20

C4

AA7

AD5

AE5

F26

A25

E19

F24

H1

C22

C30

D8

TRDY#

Common Clk

TAP

TRST#

D14

D18

D24

D31

E6

V

Power/Other

CACHE

H3

H5

H7

H9

E20

E26

E28

E30

F1

K1

K3

K5

K7

K9

F4

M1

F29

F31

G2

M3

M5

M7

G4

M9

G6

N1

G8

52

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 9 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 10 of 16)

Signal Buffer

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

Type

V

G24

G26

G28

G30

H23

H25

H27

H29

H31

J2

Power/Other

V

P2

P4

Power/Other

CC

P6

P8

P24

P26

P28

P30

R23

R25

R27

R29

R31

T2

J4

J6

J8

J24

J26

J28

J30

K23

K25

K27

K29

K31

L2

T4

T6

T8

T24

T26

T28

T30

U23

U25

U27

U29

U31

V2

L4

L6

L8

L24

L26

L28

L30

M23

M25

M27

M29

M31

N23

N25

N27

N29

N31

V4

V6

V8

V24

V26

V28

V30

W1

W25

W27

W29

W31

Y2

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

53

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 11 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 12 of 16)

Signal Buffer

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

Type

V

Y16

Y22

Power/Other

V

A29

B2

Power/Other

CC

SS

Y30

B9

AA1

AA6

AA20

AA26

AA31

AB2

AB8

AB14

AB18

AB24

AB30

AC3

AC16

AC22

AC31

AD2

AD20

AD26

AE14

AE18

AE24

AB4

B31

AD4

AD1

B27

F3

B15

B17

B23

B28

C7

C13

C19

C25

C29

D2

D5

D11

D21

D28

D30

E9

V_CC

V

E15

E17

E23

E29

E31

F2

CC

V

Input

Output

Input

CCA

CC_CACHE_SENSE

V

F7

V

F13

F19

F25

F28

F30

G1

CCIOPLL

V

Input

CCPLL

V

Output

Input

CCSENSE

VID0

VID1

VID2

VID3

VID4

VID5

E3

D3

C3

G3

B3

G5

A1

G9

VIDPWRGD

B1

G25

G27

G29

G31

H2

V

A5

SS

A11

A21

A27

54

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 13 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 14 of 16)

Signal Buffer

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

Type

V

H4

H6

Power/Other

V

M26

M28

M30

N2

Power/Other

SS

H8

H24

H26

H28

H30

J1

N4

N6

N8

N24

N26

N28

N30

P1

J3

J5

J7

J9

J23

J25

J27

J29

J31

K2

P3

P5

P7

P9

P23

P25

P27

P29

P31

R2

K4

K6

K8

K24

K26

K28

K30

L1

R4

R6

R8

R24

R26

R28

R30

T1

L3

L5

L7

L9

L23

L25

L27

L29

L31

M2

M4

M6

M8

M24

T3

T5

T7

T9

T23

T25

T27

T29

T31

U2

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

55

Pin Listing

Table 4-1. Pin Listing by Pin Name

(Sheet 15 of 16)

Table 4-1. Pin Listing by Pin Name

(Sheet 16 of 16)

Signal Buffer

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

Type

V

U4

U6

Power/Other

V

AA23

AA30

AB1

AB5

Power/Other

SS

U8

V_SS

U24

U26

U28

U30

V1

V

SS

AB11

AB21

AB27

AB31

AC2

V3

V5

AC7

V7

AC13

AC19

AC25

AD3

V9

V23

V25

V27

V29

V31

W2

AD9

AD15

AD17

AD23

AE6

W4

W24

W26

W28

W30

Y1

AE11

AE21

AE27

AA5

V

Input

Output

SSA

SS_CACHE_SENSE

V

C31

Y3

V

D26

SSSENSE

Y5

V

B12

TT

Y7

C10

Y13

Y19

Y25

Y31

AA2

AA9

AA15

AA17

E12

F10

Y10

AA12

AC10

AD12

AE4

V_SS

V

SS

VTTEN

E1

Output

56

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Pin Listing

4.1.2

Pin Listing by Pin Number

Table 4-2.Pin Listing by Pin Number

(Sheet 2 of 16)

Table 4-2.Pin Listing by Pin Number

(Sheet 1 of 16)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

C1

V

Power/Other

SS

A1

A2

VID5

Power/Other

Output

A21#

A22#

Source Sync Input/Output

Power/Other

CVID3

A3

SKTOCC#

Don’t Care

V

TT

A4

A13#

A12#

Source Sync Input/Output

Power/Other

A5

V

Power/Other

SS

A6

A32#

A33#

Source Sync Input/Output

Power/Other

V

SS

A7

A11#

Source Sync Input/Output

Power/Other

A8

V

CC

V

SS

A9

A26#

A20#

Source Sync Input/Output

Power/Other

A5#

Source Sync Input/Output

Common Clk Input/Output

Power/Other

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

B1

REQ0#

V

SS

V

CC

A14#

A10#

Source Sync Input/Output

Power/Other

REQ1#

REQ4#

Common Clk Input/Output

Power/Other

V

CC

V

SS

FORCEPR#

TEST_BUS

LOCK#

Power/Other

Input

LINT0/INTR

PROCHOT#

ID1#

Async GTL+

Power/Other

Common Clk

Power/Other

Common Clk

Power/Other

Input

Output

Input

Common Clk Input/Output

Power/Other

V

CC

V

Output

CCSENSE

A7#

A4#

Source Sync Input/Output

Power/Other

V

SS

ID5#

ID6#

Input

V

SS

A3#

Source Sync Input/Output

Common Clk Input/Output

Power/Other

V

CC_CACHE_SENSE

Don’t Care

HITM#

V

CC

C2

CVID2

VID3

Power/Other

Output

TMS

TAP

Input

C3

ID0#

Common Clk

Power/Other

Common Clk

Power/Other

Common Clk

C4

V

CC

V

SS

C5

Don’t Care

RSP#

IDS#

Input

Output

Input

C6

Common Clk

Power/Other

Input

V

SS

C7

V

SS

ID7#

C8

A35#

A34#

Source Sync Input/Output

Power/Other

Reserved

VIDPWRGD

C9

Power/Other

C10

C11

C12

C13

C14

C15

C16

V

TT

B2

V

SS

A30#

A23#

Source Sync Input/Output

Power/Other

B3

VID4

Don’t Care

ODTEN

A38#

B4

V

SS

B5

A16#

A15#

A39#

Source Sync Input/Output

B6

Source Sync Input/Output

B7

A31#

B8

A27#

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

57

Pin Listing

Table 4-2.Pin Listing by Pin Number

(Sheet 3 of 16)

Table 4-2.Pin Listing by Pin Number

(Sheet 4 of 16)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

D1

A8#

A6#

Source Sync Input/Output

Power/Other

D26

D27

D28

D29

D30

D31

E1

V

Power/Other

Common Clk

Power/Other

Common Clk

Power/Other

Output

Input

SSSENSE

ID3#

V

SS

REQ3#

REQ2#

Common Clk Input/Output

Power/Other

OOD#

Input

V

SS

CC

V

CC

DEFER#

TDI

Common Clk

TAP

Input

VTTEN

CVID0

VID1

Output

E2

V

Power/Other

Async GTL+

Common Clk

Power/Other

Async GTL+

Power/Other

Async GTL+

E3

SS

IGNNE#

SMI#

E4

BPM5#

IERR#

Common Clk Input/Output

E5

Common Clk

Power/Other

Output

ID4#

E6

V

CC

V

E7

BPM2#

BPM4#

Common Clk Input/Output

Power/Other

SS

CC

V

E8

V

E9

V

SS

SS_CACHE_SENSE

CVID1

Output

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

F1

AP0#

BR2#

Common Clk Input/Output

D2

V

Common Clk

Power/Other

Input

SS

D3

VID2

Output

Input

V

TT

D4

STPCLK#

A28#

A24#

Source Sync Input/Output

Power/Other

D5

V

SS

D6

INIT#

Input

V

SS

D7

MCERR#

Common Clk Input/Output

Power/Other

Reserved

D8

V

Power/Other

CC

SS

D9

AP1#

BR3#

Common Clk Input/Output

DRDY#

TRDY#

Common Clk Input/Output

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

Common Clk

Power/Other

Input

Common Clk

Power/Other

Common Clk

Input

V

CC

SS

A29#

A25#

Source Sync Input/Output

Power/Other

RS0#

HIT#

Input

Common Clk Input/Output

Power/Other

V

SS

CC

A18#

A17#

A9#

Source Sync Input/Output

Power/Other

TCK

TDO

TAP

Input

TAP

Output

V

Power/Other

Async GTL+

Power/Other

CC

V

FERR#/PBE#

Output

CC

ADS#

BR0#

Common Clk Input/Output

Power/Other

V

CC

SS

CC

SS

CC

SS

V

SS

RS1#

Common Clk

Power/Other

Common Clk

Input

BPRI#

V

F2

CC

ID2#

Input

F3

VID0

Output

58

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Pin Listing

Table 4-2.Pin Listing by Pin Number

(Sheet 5 of 16)

Table 4-2.Pin Listing by Pin Number

(Sheet 6 of 16)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

F4

F5

V

Power/Other

G26

G27

G28

G29

G30

G31

H1

V

Power/Other

CC

SS

CC

SS

CC

SS

BPM3#

BPM0#

Common Clk Input/Output

Power/Other

F6

F7

V

SS

F8

BPM1#

Common Clk Input/Output

F9

GTLREF3

Power/Other

Input

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

F27

F28

F29

F30

F31

G1

V

TT

CACHE

BINIT#

BR1#

Common Clk Input/Output

H2

V

SS

Common Clk

Power/Other

Input

H3

CACHE

V

H4

V

SS

ADSTB1#

A19#

Source Sync Input/Output

Common Clk Input/Output

Power/Other

H5

CACHE

H6

V

SS

A36#

H7

CACHE

ADSTB0#

DBSY#

H8

V

SS

H9

CACHE

V

H23

H24

H25

H26

H27

H28

H29

H30

H31

J1

V

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

BNR#

RS2#

Common Clk Input/Output

Common Clk

Input

A37#

Source Sync Input/Output

GTLREF2

TRST#

Power/Other

TAP

Input

V

Power/Other

Async GTL+

Power/Other

Async GTL+

Power/Other

SS

THERMTRIP#

A20M#

Output

Input

V

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

J2

J3

J4

J5

G2

J6

G3

J7

G4

J8

G5

J9

G6

J23

J24

J25

J26

J27

J28

J29

G7

BOOT_SELECT

Input

G8

V

CC

SS

G9

G23

G24

G25

LINT1/NMI

V

CC

SS

V

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

59

Pin Listing

Table 4-2.Pin Listing by Pin Number

(Sheet 7 of 16)

Table 4-2.Pin Listing by Pin Number

(Sheet 8 of 16)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

J30

J31

K1

V

Power/Other

M3

M4

V

Power/Other

CC

CACHE

V

SS

V

M5

CACHE

K2

V

M6

V

SS

CACHE

SS

K3

M7

CACHE

K4

V

M8

V

SS

CACHE

SS

K5

M9

CACHE

K6

V

M23

M24

M25

M26

M27

M28

M29

M30

M31

N1

V

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

K7

CACHE

K8

V

SS

K9

CACHE

K23

K24

K25

K26

K27

K28

K29

K30

K31

L1

V

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

V

CACHE

N2

V

SS

CACHE

N3

N4

V

SS

N5

CACHE

L2

N6

V

SS

L3

N7

CACHE

L4

N8

V

SS

L5

N9

CACHE

L6

N23

N24

N25

N26

N27

N28

N29

N30

N31

P1

V

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

L7

L8

L9

L23

L24

L25

L26

L27

L28

L29

L30

L31

M1

M2

P2

P3

P4

V

P5

CACHE

V

P6

SS

60

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Pin Listing

Table 4-2.Pin Listing by Pin Number

(Sheet 9 of 16)

Table 4-2.Pin Listing by Pin Number

(Sheet 10 of 16)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

P7

P8

V

Power/Other

T24

T25

T26

T27

T28

T29

T30

T31

U1

V

Power/Other

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

P9

P23

P24

P25

P26

P27

P28

P29

P30

P31

R1

V

CACHE

U2

V

SS

U3

CACHE

U4

V

SS

V

U5

CACHE

R2

V

U6

V

SS

R3

U7

CACHE

R4

V

U8

V

SS

R5

U9

CACHE

R6

V

U23

U24

U25

U26

U27

U28

U29

U30

U31

V1

V

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

R7

CACHE

R8

V

SS

R9

CACHE

R23

R24

R25

R26

R27

R28

R29

R30

R31

T1

V

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

V2

V3

V4

V5

T2

V6

T3

V7

T4

V8

T5

V9

T6

V23

V24

V25

V26

V27

T7

T8

T9

T23

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

61

Pin Listing

Table 4-2.Pin Listing by Pin Number

(Sheet 11 of 16)

Table 4-2.Pin Listing by Pin Number

(Sheet 12 of 16)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

V28

V29

V30

V31

W1

W2

W3

W4

W5

W6

W7

W8

W9

W23

W24

W25

W26

W27

W28

W29

W30

W31

Y1

V

Power/Other

Y19

Y20

V

Power/Other

CC

SS

CC

SS

CC

SS

DSTBP0#

DSTBN0#

Source Sync Input/Output

Power/Other

Y21

Y22

V

CC

Y23

D5#

D2#

Source Sync Input/Output

Power/Other

Y24

Reserved

Y25

V

SS

V

Power/Other

FSB Clk

Y26

D0#

Source Sync Input/Output

SS

BCLK1

Input

Y27

Reserved

SM_TS1_A1

TESTHI0

TESTHI1

TESTHI2

GTLREF1

GTLREF0

Power/Other

FSB Clk

Y28

Y29

SMBus

Input

Y30

V

Power/Other

CC

SS

CC

SS

Y31

AA1

V

AA2

SS

CC

SS

CC

SS

CC

SS

CC

SS

CC

SS

AA3

BSEL0

DEP7#

Output

AA4

Source Sync Input/Output

AA5

V

Power/Other

Input

SSA

AA6

V

CC

AA7

TESTHI4

D61#

Input

AA8

Source Sync Input/Output

Power/Other

AA9

V

SS

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AA27

D54#

D53#

Source Sync Input/Output

Power/Other

Y2

Y3

V

TT

Y4

BCLK0

Input

D48#

D49#

Source Sync Input/Output

Power/Other

Y5

V

Power/Other

Common Clk

SS

Y6

TESTHI3

V

SS

Y7

V

D33#

Source Sync Input/Output

Power/Other

SS

Y8

RESET#

D62#

V

SS

Y9

Source Sync Input/Output

Power/Other

D24#

D15#

Source Sync Input/Output

Power/Other

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

V

TT

DSTBP3#

DSTBN3#

Source Sync Input/Output

Power/Other

V

CC

D11#

D10#

Source Sync Input/Output

Power/Other

V

SS

DSTBP2#

DSTBN2#

Source Sync Input/Output

Power/Other

V

SS

D6#

D3#

Source Sync Input/Output

Power/Other

V

CC

DSTBP1#

DSTBN1#

Source Sync Input/Output

V

CC

D1#

Source Sync Input/Output

62

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Pin Listing

Table 4-2.Pin Listing by Pin Number

(Sheet 13 of 16)

Table 4-2.Pin Listing by Pin Number

(Sheet 14 of 16)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

AA28

AA29

AA30

AA31

AB1

SM_TS1_A0

SM_EP_A0

SMBus

Input

AC6

AC7

D59#

Source Sync Input/Output

Power/Other

SMBus

V

SS

V

Power/Other

AC8

D56#

D47#

Source Sync Input/Output

Power/Other

SS

CC

SS

CC

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AC27

AC28

AC29

AC30

AC31

AD1

V

TT

AB2

D43#

D41#

Source Sync Input/Output

Power/Other

AB3

BSEL1

Output

Input

AB4

V

SS

CCA

AB5

V

D50#

DP2#

Source Sync Input/Output

Common Clk Input/Output

Power/Other

SS

AB6

D63#

Source Sync Input/Output

AB7

PWRGOOD

Async GTL+

Power/Other

Input

V

CC

AB8

V

D34#

DP0#

Source Sync Input/Output

Common Clk Input/Output

Power/Other

CC

AB9

DBI3#

D55#

Source Sync Input/Output

Power/Other

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AB27

AB28

AB29

AB30

AB31

AC1

V

SS

V

D25#

D26#

Source Sync Input/Output

Power/Other

SS

D51#

D52#

Source Sync Input/Output

Power/Other

V

CC

V

D23#

D20#

Source Sync Input/Output

Power/Other

CC

D37#

D32#

D31#

Source Sync Input/Output

Power/Other

V

SS

D17#

DBI0#

Source Sync Input/Output

V

CC

D14#

D12#

Source Sync Input/Output

Power/Other

SM_CLK

SM_DAT

Don’t Care

SMBus

Input

Output

V

SS

D13#

D9#

Source Sync Input/Output

Power/Other

V

Power/Other

CC

V

Input

CCPLL

V

AD2

V

CC

D8#

D7#

Source Sync Input/Output

Power/Other

AD3

SS

AD4

V

Input

CCIOPLL

V

AD5

TESTHI5

DEP5#

D57#

SS

SM_EP_A2

SM_EP_A1

SMBus

Input

AD6

Source Sync Input/Output

Power/Other

AD7

V

Power/Other

AD8

D46#

CC

SS

AD9

V

SS

Don’t Care

AD10

AD11

AD12

AD13

AD14

D45#

D40#

Source Sync Input/Output

Power/Other

AC2

V

Power/Other

SS

CC

AC3

V

TT

AC4

DEP6#

D60#

Source Sync Input/Output

D38#

D39#

Source Sync Input/Output

AC5

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

63

Pin Listing

Table 4-2.Pin Listing by Pin Number

(Sheet 15 of 16)

Table 4-2.Pin Listing by Pin Number

(Sheet 16 of 16)

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

AE2

V

Power/Other

AE8

DEP4#

D44#

D42#

Source Sync Input/Output

Power/Other

SS

COMP0

Input

AE9

V

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AE27

AE28

AE29

AE30

SS

D36#

D30#

Source Sync Input/Output

Power/Other

V

SS

DBI2#

D35#

Source Sync Input/Output

Power/Other

V

CC

D29#

Source Sync Input/Output

Power/Other

V

CC

DBI1#

DEP3#

DEP2#

DP3#

Source Sync Input/Output

Common Clk Input/Output

Power/Other

V

SS

D21#

D18#

Source Sync Input/Output

Power/Other

V

CC

V

DP1#

D28#

Common Clk Input/Output

Source Sync Input/Output

Power/Other

CC

D4#

SM_ALERT#

SM_WP

Source Sync Input/Output

SMBus

Output

Input

V

SS

D27#

D22#

Source Sync Input/Output

Power/Other

DEP1#

Source Sync Input/Output

DEP0#

V

CC

Don’t Care

D19#

D16#

Source Sync Input/Output

Power/Other

AE3

AE4

V

SS

TT

AE5

TESTHI6

Power/Other

Input

SM_VCC

Reserved

Power/Other

AE6

V

Power/Other

SS

AE7

D58#

Source Sync Input/Output

§

64

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Signal Definitions

5 Signal Definitions

5.1

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 1 of 8)

Name

A[39:3]#

Type

Description

40

I/O

A[39:3]# (Address) define a 2 -byte physical memory address space. In sub-

phase 1 of the address phase, these pins transmit the address of a transaction.

In sub-phase 2, these pins transmit transaction type information. These signals

must connect the appropriate pins of all agents on the Dual-Core Intel Xeon

processor 7100 series front side bus. A[39:3]# are protected by parity signals

AP[1:0]#. A[39:3]# are source synchronous signals and are latched into the

receiving buffers by ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processors sample a subset

of the A[39:3]# pins to determine their power-on configuration. See

Section 7.1.

A20M#

I

If A20M# (Address-20 Mask) is asserted, the processor masks physical address

bit 20 (A20#) before looking up a line in any internal cache and before driving

a read/write transaction on the bus. Asserting A20M# emulates the 8086

processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M#

is only supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid 6 clks before the I/O write’s

response.

ADS#

I/O

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[39:3]# and transaction request type on REQ[4:0]# pins. All

bus agents observe the ADS# activation to begin parity checking, protocol

checking, address decode, internal snoop, or deferred reply ID match

operations associated with the new transaction. This signal must connect the

appropriate pins on all Dual-Core Intel Xeon processor 7100 series processor

front side bus agents.

ADSTB[1:0]#

AP[1:0]#

I/O

Address strobes are used to latch A[39:3]# and REQ[4:0]# on their rising and

falling edge.

AP[1:0]# (Address Parity) are driven by the requestor one common clock after

ADS#, A[39:3]#, REQ[4:0]# are driven. A correct parity signal is electrically

high if an even number of covered signals are electrically low and electrically

low if an odd number of covered signals are electrically low. This allows parity

to be electrically high when all the covered signals are electrically high.

AP[1:0]# should connect the appropriate pins of all Dual-Core Intel Xeon

processor 7100 series front side bus agents. The following table defines the

coverage for these signals.

Request Signals

Subphase 1

Subphase 2

A[39:24]#

A[23:3]#

AP0#

AP1#

AP0#

REQ[4:0]#

BCLK[1:0]

I

The differential bus clock pair BCLK[1:0] determines the bus frequency. All

processor front side bus agents must receive these signals to drive their

outputs and latch their inputs.

All external timing parameters are specified with respect to the rising edge of

BCLK0 crossing the falling edge of BCLK1.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

65

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 2 of 8)

Name

BINIT#

Type

Description

I/O

BINIT# (Bus Initialization) may be observed and driven by all processor front

side bus agents. If used, BINIT# must connect the appropriate pins of all such

agents. If the BINIT# driver is enabled, BINIT# is asserted to signal any bus

condition that prevents reliable future operation.

If BINIT# observation is enabled during power-on configuration (see

Section 7.1) and BINIT# is sampled asserted, symmetric agents reset their bus

LOCK# activity and bus request arbitration state machines. The bus agents do

not reset their I/O Queue (IOQ) and transaction tracking state machines upon

observation of BINIT# assertion. Once the BINIT# assertion has been

observed, the bus agents will re-arbitrate for the front side bus and attempt

completion of their bus queue and IOQ entries.

If BINIT# observation is enabled during power on configuration, a central

agent may handle an assertion of BINIT# as appropriate to the error handling

architecture of the system.

BNR#

I/O

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who

is unable to accept new bus transactions. During a bus stall, the current bus

owner cannot issue any new transactions.

Since multiple agents might need to request a bus stall at the same time,

BNR# is a wire-OR signal which must connect the appropriate pins of all

processor system bus agents. In order to avoid wire-OR glitches associated

with simultaneous edge transitions driven by multiple drivers, BNR# is

activated on specific clock edges and sampled on specific clock edges.

BOOT_

SELECT

I

The BOOT_SELECT input informs the processor whether the platform supports

the Dual-Core Intel Xeon processor 7100 series. Incompatible platform designs

will have this input connected to V . Thus, this pin is essentially an electrical

SS

key to prevent the Dual-Core Intel Xeon processor 7100 series from running in

a system that is not designed for it. For platforms that are designed to support

the Dual-Core Intel Xeon processor 7100 series, this pin should be changed to

a no-connect.

BPM[5:0]#

I/O

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor

signals. They are outputs from the processor which indicate the status of

breakpoints and programmable counters used for monitoring processor

performance. BPM[5:0]# should connect the appropriate pins of all Dual-Core

Intel Xeon processor 7100 series front side bus agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is

a processor output used by debug tools to determine processor debug

readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ#

is a processor input and is used by debug tools to request debug operation of

the processors.

BPM[5:4]# must be bussed to all bus agents. Please refer to the appropriate

platform design guide for more detailed information.

BPRI#

I

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor

front side bus. It must connect the appropriate pins of all processor front side

bus agents. Observing BPRI# active (as asserted by the priority agent) causes

all other agents to stop issuing new requests, unless such requests are part of

an ongoing locked operation. The priority agent keeps BPRI# asserted until its

requests are issued, then releases the bus by deasserting BPRI#.

66

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 3 of 8)

Name

Type

Description

BR0#

BR[3:1]#

I/O

I

BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The

BREQ[3:0]# signals are interconnected in a rotating manner to individual

processor pins. The tables below give the rotating interconnect between the

processor and bus signals for 3-load configurations.

BR[3:0]# Signals Rotating Interconnect, 3-Load Configuration

Agent 0

Pins

Agent 1

Pins

Bus Signal

BREQ0#

BREQ1#

BREQ2#

BREQ3#

BR0#

BR1#

BR2#

BR3#

BR1#

BR0#

BR3#

BR2#

During power-on configuration, the central agent must assert the BR0# bus

signal. All symmetric agents sample their BR[3:0]# pins on the active-to-

inactive transition of RESET#. The pin which the agent samples asserted

determines its agent ID.

BSEL[1:0]

O

These output signals are used to select the front side bus frequency. The

frequency is determined by the processor(s), chipset, and frequency

synthesizer capabilities. All front side bus agents must operate at the same

frequency. Individual processors will only operate at their specified front side

bus frequency. See the appropriate platform design guide for implementation

examples.

See Table 2-3 for output values. Refer to the appropriate platform design guide

for termination recommendations.

COMP0

I

COMP0 must be terminated to V on the baseboard using precision resistors.

SS

This input configures the AGTL+ drivers of the processor. Refer to the

appropriate platform design guide and Table 2-23 for implementation details.

CVID[3:0]

O

CVID[3:0] (Cache Voltage ID) pins are used to support automatic selection of

V

. These are open drain signals that are driven by the processor and must

CACHE

be pulled to no more than 3.3 V (+5% tolerance) with a resistor. Conversely,

the V VR output must be disabled prior to the voltage supply for these

CACHE

pins becoming invalid. The CVID pins are needed to support processor voltage

specification variations. See Table 2-5 for definitions of these pins. The V

CACHE

VR must supply the voltage that is requested by these pins, or disable itself.

D[63:0]#

I/O

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the processor front side bus agents, and must connect the

appropriate pins on all such agents. The data driver asserts DRDY# to indicate

a valid data transfer.

D[63:0]# are quad-pumped signals, and will thus be driven four times in a

common clock period. D[63:0]# are latched off the falling edge of both

DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to

a pair of one DSTBP# and one DSTBN#. The following table shows the

grouping of data signals to strobes and DBI#.

Furthermore, the DBI# pins determine the polarity of the data signals. Each

group of 16 data signals corresponds to one DBI# signal. When the DBI#

signal is active, the corresponding data group is inverted and therefore

sampled active high.

DBI[3:0]#

I/O

DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]#

and DEP[7:0]# signals. The DBI[3:0]# signals are activated when the data on

the data bus is inverted. If more than half the data bits, within an 18-bit group

(including ECC bits), would have been asserted electrically low, the bus agent

may invert the data bus and corresponding ECC signals for that particular sub-

phase for that 18-bit group.

DBSY#

I/O

I

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data

on the processor front side bus to indicate that the data bus is in use. The data

bus is released after DBSY# is deasserted. This signal must connect the

appropriate pins on all processor front side bus agents.

DEFER#

DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the

responsibility of the addressed memory or I/O agent. This signal must connect

the appropriate pins of all processor front side bus agents.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

67

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 4 of 8)

Name

DEP[7:0]#

Type

Description

I/O

The DEP[7:0]# (data bus ECC protection) signals provide optional ECC

protection for the data bus. They are driven by the agent responsible for

driving D[63:0]#, and, if ECC is implemented, must connect the appropriate

pins of all bus agents which use them.

Furthermore, the DBI# pins determine the polarity of the ECC signals. Each

pair of 2 ECC signals corresponds to one DBI# signal. When the DBI# signal is

active, the corresponding ECC pair is inverted and therefore sampled active

high.

DP[3:0]#

DRDY#

I/O

DP[3:0]# (Data Parity) provide optional parity protection for the data bus.

They are driven by the agent responsible for driving D[63:0]#, and, if parity is

implemented, must connect the appropriate pins of all bus agents which use

them.

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

indicating valid data on the data bus. In a multi-common clock data transfer,

DRDY# may be deasserted to insert idle clocks. This signal must connect the

appropriate pins of all processor front side bus agents.

DSTBN[3:0]#

DSTBP[3:0]#

FERR#/PBE#

I/O

O

Data strobe used to latch in D[63:0]#, DEP[7:0]# and DBI[3:0]#.

FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal

and its meaning is qualified by STPCLK#. When STPCLK# is not asserted,

FERR#/PBE# indicates a floating-point error and will be asserted when the

processor detects an unmasked floating-point error. When STPCLK# is not

asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387

coprocessor, and is included for compatibility with systems using MS-DOS*-

type floating-point error reporting. When STPCLK# is asserted, an assertion of

FERR#/PBE# indicates that the processor has a pending break event waiting

for service. The assertion of FERR#/PBE# indicates that the processor should

be returned to the Normal state. For additional information on the pending

break event functionality, including the identification of support of the feature

®

and enable/disable information, refer to Vol 3 of the Intel

Architecture

®

Software Developer’s Manual and the Intel Processor Identification and the

CPUID Instruction application note.

FORCEPR#

I

This input can be used to force activation of the Thermal Control Circuit.

GTLREF[3:0]

GTLREF determines the signal reference level for AGTL+ input pins. GTLREF is

used by the AGTL+ receivers to determine if a signal is an electrical 0 or an

electrical 1. Please refer to Table 2-23 for further details.

HIT#

HITM#

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop

operation results. Any front side bus agent may assert both HIT# and HITM#

together to indicate that it requires a snoop stall, which can be continued by

reasserting HIT# and HITM# together, every other common clock.

Since multiple agents may deliver snoop results at the same time, HIT# and

HITM# are wire-OR signals which must connect the appropriate pins of all

processor front side bus agents. In order to avoid wire-OR glitches associated

with simultaneous edge transitions driven by multiple drivers, HIT# and HITM#

are activated on specific clock edges and sampled on specific clock edges.

ID[7:0]#

I

ID[7:0]# are the Transaction ID signals. They are driven during the Deferred

Phase by the deferring agent.

IDS#

I

IDS# is the ID Strobe signal. It is asserted to begin the Deferred Phase.

IERR#

O

IERR# (Internal Error) is asserted by a processor as the result of an internal

error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction

on the processor front side bus. This transaction may optionally be converted

to an external error signal (e.g., NMI) by system core logic. The processor will

keep IERR# asserted until the assertion of RESET#.

IGNNE#

I

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

numeric error and continue to execute noncontrol floating-point instructions. If

IGNNE# is deasserted, the processor generates an exception on a noncontrol

floating-point instruction if a previous floating-point instruction caused an

error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this

signal following an I/O write instruction, it must be valid a 6 clks before the I/O

write’s response.

68

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 5 of 8)

Name

Type

Description

INIT#

I

INIT# (Initialization), when asserted, resets integer registers inside all

processors without affecting their internal caches or floating-point registers.

Each processor then begins execution at the power-on Reset vector configured

during power-on configuration. The processor continues to handle snoop

requests during INIT# assertion. INIT# is an asynchronous signal and must

connect the appropriate pins of all processor front side bus agents.

If INIT# is sampled active on the active to inactive transition of RESET#, then

the processor executes its Built-in Self-Test (BIST).

LINT0/INTR

LINT1/NMI

I

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front

side bus agents. When the APIC functionality is disabled, the LINT0 signal

becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI,

a nonmaskable interrupt. INTR and NMI are backward compatible with the

signals of those names on the Pentium processor. Both signals are

asynchronous.

These signals must be software configured via BIOS programming of the APIC

register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is

enabled by default after Reset, operation of these pins as LINT[1:0] is the

default configuration.

LOCK#

I/O

LOCK# indicates to the system that a set of transactions must occur atomically.

This signal must connect the appropriate pins of all processor front side bus

agents. For a locked sequence of transactions, LOCK# is asserted from the

beginning of the first transaction to the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the

processor front side bus, it will wait until it observes LOCK# deasserted. This

enables symmetric agents to retain ownership of the processor front side bus

throughout the bus locked operation and ensure the atomicity of lock.

MCERR#

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error

or a bus protocol violation. It may be driven by all processor front side bus

agents.

MCERR# assertion conditions are configurable at a system level. Assertion

options are defined as follows:

•

Enabled or disabled.

Asserted, if configured, for internal errors along with IERR#.

Asserted, if configured, by the request initiator of a bus transaction after it

observes an error.

•

Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the IA-32

®

Intel Software Developer’s Manual, Volume 3: System Programming Guide or

the BIOS Writer’s Guide which includes the Dual-Core Intel® Xeon® Processor

7100 Series processor.

Since multiple agents may drive this signal at the same time, MCERR# is a

wired-OR signal which must connect the appropriate pins of all processor front

side bus agents. In order to avoid wire-OR glitches associated with

simultaneous edge transitions driven by multiple drivers, MCERR# is activated

on specific clock edges and sampled on specific clock edges.

ODTEN

I

ODTEN (On-die termination enable) should be connected to V through a

TT

resistor to enable on-die termination for end bus agents. For middle bus

agents, pull this signal down via a resistor to ground to disable on-die

termination. Whenever ODTEN is high, on-die termination will be active,

regardless of other states of the bus.

OOD#

I

O

I

OOD# allows data delivery to occur subsequent to IDS# assertion during the

Deferred Phase.

PROCHOT#

PWRGOOD

The assertion of PROCHOT# (processor hot) indicates that the processor die

temperature has reached its thermal limit. See Section 6.2.4 for more details.

PWRGOOD (Power Good) is an input. The processor requires this signal to be a

clean indication that all Dual-Core Intel Xeon processor 7100 series clocks and

power supplies are stable and within their specifications. “Clean” implies that

the signal will remain low (capable of sinking leakage current), without

glitches, from the time that the power supplies are turned on until they come

within specification. The signal must then transition monotonically to a high

state. PWRGOOD can be driven inactive at any time, but clocks and power

must again be stable before a subsequent rising edge of PWRGOOD.

The PWRGOOD signal must be supplied to the processor. This signal is used to

protect internal circuits against voltage sequencing issues. It should be driven

high throughout boundary scan operation.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

69

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 6 of 8)

Name

REQ[4:0]#

Type

Description

I/O

REQ[4:0]# (Request Command) must connect the appropriate pins of all

processor front side bus agents. They are asserted by the current bus owner to

define the currently active transaction type. These signals are source

synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for

details on parity checking of these signals.

RESET#

I

Asserting the RESET# signal resets all processors to known states and

invalidates their internal caches without writing back any of their contents. For

a power-on Reset, RESET# must stay active for at least 1 ms after VCC and

BCLK have reached their specified levels. On observing active RESET#, all front

side bus agents will deassert their outputs within two clocks. RESET# must not

be kept asserted for more than 10 ms.

A number of bus signals are sampled at the active-to-inactive transition of

RESET# for power-on configuration. These configuration options are described

in Section 7.1.

RS[2:0]#

RSP#

I

RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect to the

appropriate pins of all processor front side bus agents.

RSP# (Response Parity) is driven by the response agent (the agent responsible

for completion of the current transaction) during assertion of RS[2:0]#, the

signals for which RSP# provides parity protection. It must connect to the

appropriate pins of all processor front side bus agents.

A correct parity signal is electrically high if an even number of covered signals

are electrically low and electrically low if an odd number of covered signals are

electrically low. If RS[2:0]# are all electrically high, RSP# is also electrically

high, since this indicates it is not being driven by any agent guaranteeing

correct parity.

SKTOCC#

O

SKTOCC# (Socket occupied) will be pulled to ground by the processor to

indicate that the processor is present. There is no connection to the processor

silicon for this signal.

SM_ALERT#

SM_ALERT# (SMBus Alert) is an asynchronous interrupt line associated with

the SMBus Thermal Sensor device. It is an open-drain output and the

processor includes a 10kΩ pull-up resistor to SM_VCC for this signal. For more

information on the usage of the SM_ALERT# pin, see Section 7.4.9.

SM_CLK

I/O

The SM_CLK (SMBus Clock) signal is an input clock to the system management

logic which is required for operation of the system management features of the

Dual-Core Intel Xeon processor 7100 series. This clock is driven by the SMBus

controller and is asynchronous to other clocks in the processor.The processor

includes a 10 kΩ pull-up resistor to SM_VCC for this signal.

SM_DAT

I/O

I

The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal

provides the single-bit mechanism for transferring data between SMBus

devices. The processor includes a 10 kΩ pull-up resistor to SM_VCC for this

signal.

SM_EP_A[2:0]

The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in

conjunction with the upper address bits in order to maintain unique addresses

on the SMBus in a system with multiple processors. To set an SM_EP_A line

high, a pull-up resistor should be used that is no larger than 1 kΩ. The

processor includes a 10 kΩ pull-down resistor to V for each of these signals.

SS

For more information on the usage of these pins, see Section 7.4.1.

SM_TS_A[1:0]

I

The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the SMBus

in conjunction with the upper address bits in order to maintain unique

addresses on the SMBus in a system with multiple processors.

The device’s addressing, as implemented, includes a Hi-Z state for both

address pins. The use of the Hi-Z state is achieved by leaving the input floating

(unconnected).

For more information on the usage of these pins, see Section 7.4.1.

SM_VCC

SM_WP

I

SM_VCC provides power to the SMBus components on the Dual-Core Intel

Xeon processor 7100 series package.

WP (Write Protect) can be used to write protect the Scratch EEPROM. The

Scratch EEPROM is write-protected when this input is pulled high to SM_VCC.

The processor includes a 10 kΩ pull-down resistor to V for this signal.

SS

70

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 7 of 8)

Name

Type

Description

SMI#

I

SMI# (System Management Interrupt) is asserted asynchronously by system

logic. On accepting a System Management Interrupt, processors save the

current state and enter System Management Mode (SMM). An SMI

Acknowledge transaction is issued, and the processor begins program

execution from the SMM handler.

On the Dual-Core Intel Xeon processor 7100 series, it is required that SMI#

assertion be observed 8 BCLKs before the Response Status (RS[2:0]#) is

observed by the processor.

If SMI# is asserted during the deassertion of RESET#, the processor will tri-

state its outputs.

STPCLK#

I

STPCLK# (Stop Clock), when asserted, causes processors to enter a low power

Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction,

and stops providing internal clock signals to all processor core units except the

front side bus and APIC units. The processor continues to snoop bus

transactions and service interrupts while in Stop-Grant state. When STPCLK# is

deasserted, the processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#

is an asynchronous input.

TCK

TDI

I

TCK (Test Clock) provides the clock input for the processor Test Access Port.

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO

O

I

TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TEST_BUS

TESTHI[6:0]

THERMTRIP#

Must be connected to all other processor TEST_BUS signals in the system. See

the appropriate platform design guideline for termination details.

I

TESTHI[6:0] must be connected to a V power source through a resistor for

TT

proper processor operation. See Section 2.4 for more details.

O

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction

temperature has reached a temperature beyond which permanent silicon

damage may occur. THERMTRIP# (Thermal Trip) will activate at a temperature

that is approximately 15°C above the maximum case temperature (TC).

Measurement of the temperature is accomplished through an internal thermal

sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal

clocks (thus halting program execution) in an attempt to reduce the processor

junction temperature. To protect the processor its core voltage (VCC) must be

removed following the assertion of THERMTRIP#. Driving of the THERMTRIP#

signals is enabled within 10 µs of the assertion of PWRGOOD and is disabled on

de-assertion of PWRGOOD. Once activated, THERMTRIP# remains latched until

PWRGOOD is de-asserted. While the deassertion of the PWRGOOD signal will

de-assert THERMTRIP#, if the processor’s junction temperature remains at or

above the trip level, THERMTRIP# will again be asserted within 10 µs of the

assertion of PWRGOOD. Thermtrip should not be sampled until 10 µs after

PWRGOOD assertion at the processor.

TMS

I

TMS (Test Mode Select) is a JTAG specification support signal used by debug

tools.

TRDY#

TRDY# (Target Ready) is asserted by the target (chipset) to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY# must

connect the appropriate pins of all front side bus agents.

TRST#

I

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be

driven electrically low during power on Reset. Please refer to the eXtended

Debug Port: Debug Port Design Guide for Twin Castle Chipset Platforms or the

eXtended Debug Port: Debug Port Design Guide for MP Platforms for details.

V

I

V

provides power to the L3 cache on the Dual-Core Intel Xeon processor

CACHE

CC

CACHE

7100 series.

V

provides power to the core logic of the Dual-Core Intel Xeon processor

CC

7100 series.

V

provides isolated power for the analog portion of the internal PLL’s. Use a

CCA

discrete RLC filter to provide clean power. Refer to the appropriate platform

design guide for complete implementation details.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

71

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 8 of 8)

Name

Type

Description

provide isolated, low impedance

V

O

V

and V

CC_CACHE_SENSE SS_CACHE_SENSE

CC_CACHE_SENSE

SS_CACHE_SENSE

connections to the processor cache voltage (V

) and ground (V ). They

CACHE

SS

can be used to sense or measure voltage or ground near the silicon with little

noise.

V

I

V

provides isolated power for digital portion of the internal PLL’s. Follow

CCIOPLL

CCPLL

the guidelines for V

, and refer to the appropriate platform design guide for

CCA

complete implementation details.

I

The on-die PLL filter solution will not be implemented on this platform. The

V

input should be left unconnected.

CCPLL

V

O

V

and V

provide isolated, low impedance connections to the

CCSENSE

SSSENSE

CCSENSE

SSSENSE

processor core voltage (V ) and ground (V ). These signals must be

CC

SS

connected to the voltage regulator feedback signals, which ensure the output

voltage (i.e. processor voltage) remains within specification. Please see the

applicable platform design guide for implementation details.

VID[5:0]

O

VID[5:0] (Voltage ID) pins are used to support automatic selection of V

These are open drain signals that are driven by the processor and must be

pulled to no more than 3.3 V (+5% tolerance) with a resistor. Conversely, the

.

CC

V

VR output must be disabled prior to the voltage supply for these pins

CC

becoming invalid. The VID pins are needed to support processor voltage

specification variations. See Table 2-4 for definitions of these pins. The V VR

CC

must supply the voltage that is requested by these pins, or disable itself.

VIDPWRGD

I

The processor requires this input to determine that the supply voltage for

BSEL[1:0], VID[5:0], and CVID[3:0] is stable and within specification.

V

I

V

is the ground plane for the Dual-Core Intel Xeon processor 7100 series.

SS

provides an isolated, internal ground for internal PLL’s. Do not connect

SSA

directly to ground. This pin is to be connected to V

discrete filter circuit.

and V

through a

CCA

CCIOPLL

V

I

V

is the front side bus termination voltage.

TT

VTTEN

O

VTTEN can be used as an output enable for the V regulator. VTTEN is used as

TT

an electrical key to prevent processors with mechanically-equivalent pinouts

from accidentally booting in a Dual-Core Intel Xeon processor 7100 series

platform. Since VTTEN is an open circuit on the processor package, VTTEN

must be pulled up on the motherboard. Refer to the appropriate platform

design guide for implementation details.

§

72

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Thermal Specifications

6 Thermal Specifications

6.1

Package Thermal Specifications

The Dual-Core Intel Xeon processor 7100 series requires a thermal solution to maintain

temperatures within operating limits. Any attempt to operate the processor outside

these operating limits may result in permanent damage to the processor and

potentially other components within the system. As processor technology changes,

thermal management becomes increasingly crucial when building computer systems.

Maintaining the proper thermal environment is key to reliable, long-term system

operation.

A complete solution includes both component and system level thermal management

features. Component level thermal solutions can include active or passive heatsinks

attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal

solutions may consist of system fans combined with ducting and venting.

For more information on designing a component level thermal solution, refer to the

Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines.

Note:

The boxed processor will ship with a component thermal solution. Refer to Section 8 for

details on the boxed processor.

6.1.1

Thermal Specifications

To allow the optimal operation and long-term reliability of Intel processor-based

systems, the processor must remain within the minimum and maximum case

temperature (T_CASE) specifications as defined by the applicable thermal profile (see

Table 6-1 and Figure 6-1or Figure 6-2). Thermal solutions not designed to provide this

level of thermal capability may affect the long-term reliability of the processor and

system. For more details on thermal solution design, please refer to the appropriate

processor thermal/mechanical design guidelines.

The Dual-Core Intel Xeon processor 7100 series uses a methodology for managing

processor temperatures which is intended to support acoustic noise reduction through

fan speed control and assure processor reliability. Selection of the appropriate fan

speed will be based on the temperature reported by the processor’s Thermal Diode. If

the diode temperature is greater than or equal to Tcontrol (see Section 6.2.7), then the

processor case temperature must remain at or below the temperature as specified by

the thermal profile (see Figure 6-1 or Figure 6-2). If the diode temperature is less than

Tcontrol, then the case temperature is permitted to exceed the thermal profile, but the

diode temperature must remain at or below Tcontrol. Systems that implement fan

speed control must be designed to take these conditions into account. Systems that do

not alter the fan speed only need to guarantee the case temperature meets the thermal

profile specifications.

The Dual-Core Intel Xeon processor 7100 series thermal profile ensures adherence to

Intel reliability requirements. The thermal profile is representative of a industry

enabled 2U heat sink. In this scenario, it is expected that the Thermal Control Circuit

(TCC) would only be activated for very brief periods of time when running the most

power intensive applications. Refer to the Dual-Core Intel® Xeon® Processor 7100

Series Thermal/Mechanical Design Guidelines for details on system thermal solution

design, thermal profiles, and environmental considerations.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

73

Thermal Specifications

The upper point of the thermal profile consists of the Thermal Design Power (TDP)

defined in Table 6-1and the associated T_CASEvalue. The lower point of the thermal

profile consists of x = P_{CONTROL_BASE}and y = T_{CASE_MAX}@ P_{CONTROL_BASE}. Pcontrol is

defined as the processor power at which T_CASE, calculated from the thermal profile,

corresponds to the lowest possible value of Tcontrol. This point is associated with the

Tcontrol value (see Section 6.2.7). However, because Tcontrol represents a diode

temperature, it is necessary to define the associated case temperature. This is

T_{CASE_MAX}@ P_{CONTROL_BASE}. Please see Section 6.2.7 and the Dual-Core Intel® Xeon®

Processor 7100 Series Thermal/Mechanical Design Guidelines for proper usage of the

Tcontrol specification.

The case temperature is defined at the geometric top center of the processor IHS.

Analysis indicates that real applications are unlikely to cause the processor to consume

maximum power dissipation for sustained time periods. Intel recommends that

complete thermal solution designs target the TDP indicated in Table 6-1. The Thermal

Monitor feature is intended to help protect the processor in the event that an

application exceeds the TDP recommendation for a sustained time period. For more

details on this feature, refer to Section 6.2. To ensure maximum flexibility for future

requirements, systems should be designed to the Flexible Motherboard (FMB)

guidelines, even if a processor with a lower thermal dissipation is currently planned.

Thermal Monitor or Thermal Monitor 2 feature must be enabled for the

processor to remain within specification.

Table 6-1.

Dual-Core Intel® Xeon® Processor 7100 Series Thermal Specifications

Thermal

Design Power

(W)

Minimum

TCASE

(°C)

Maximum

TCASE

QDF / S-Spec

Frequency

Notes

(°C)

Greater than 3.0 GHz

150

95

5

See Figure 6-1

and Table 6-2

1,2

Less than or equal to

3.0 GHz

See Figure 6-2

and Table 6-3

Note:

1.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not

the maximum power that the processor can dissipate. TDP is measured at maximum T

FMB, or Flexible Motherboard, guidelines provide a design target for meeting future thermal requirements.

See Section 2.10.1 for further information on FMB.

.

CASE

2.

74

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Thermal Specifications

Figure 6-1. 150W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile

70

65

60

55

50

45

20

40

60

80

100

Power [W]

120

140

160

y = 0.158 * x + 45

Note: Refer to the Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines for

system and environmental implementation details.

Table 6-2.

150W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile

Power [W]

T_{CASE_MAX}[°C]

Power [W]

100

T_{CASE_MAX}[°C]

P_{CONTROL_BASE}= 31

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

35

40

45

50

55

60

65

70

75

80

85

90

95

105

110

115

120

125

130

135

140

145

150

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

75

Thermal Specifications

Figure 6-2. 95W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile

65

60

55

50

45

40

35

-35 -25 -15

-5

5

15

25

35

45

55

65

75

85

95

Power [W]

y = 0.158 * x + 45

Notes:

1.

Refer to the Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines for

system and environmental implementation details.

2.

The T

for 95W TDP parts is greater than or equal to 16 °C

CONTROL_OFFSET

Table 6-3.

95W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile

Power [W]

T_{CASE_MAX}[°C]

Power [W]

T_{CASE_MAX}[°C]

P_{CONTROL_BASE}= -31

40

41

42

43

44

45

46

47

48

85

50

51

40

45

50

55

60

65

70

75

80

85

90

95

51

52

53

54

55

56

57

58

85

59

60

-25

-20

-15

-10

-5

0

5

10

15

20

25

30

35

Note: The T

for 95W TDP parts is greater than or equal to 16 °C

CONTROL_OFFSET

76

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Thermal Specifications

6.1.2

Thermal Metrology

The maximum and minimum case temperatures (T_CASE) specified in Table 6-1 are

measured at the geometric top center of the processor integrated heat spreader (IHS).

Figure 6-3 illustrates the location where T_CASEtemperature measurements should be

made. For detailed guidelines on temperature measurement methodology, refer to the

Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines.

Figure 6-3. Case Temperature (T_CASE) Measurement Location

Measure from edge of IHS

19.2 mm [0.756 in]

Measure T

at this point

(geometric^Cc^Ae^Sn^Eter of IHS)

19.2 mm [0.756 in]

53.34 mm FC-mPGA4 Package

Thermal grease should cover

entire area of IHS

6.2

Processor Thermal Features

6.2.1

Thermal Monitor

The Thermal Monitor feature helps control the processor temperature by activating the

Thermal Control Circuit (TCC) when the processor silicon reaches its maximum

operating temperature. The TCC reduces processor power consumption as needed by

modulating (starting and stopping) the internal processor core clocks. The Thermal

Monitor (or Thermal Monitor 2) must be enabled for the processor to be operating

within specifications. The temperature at which Thermal Monitor activates the thermal

control circuit is not user configurable and is not software visible. Bus traffic is snooped

in the normal manner, and interrupt requests are latched (and serviced during the time

that the clocks are on) while the TCC is active.

When the Thermal Monitor is enabled and a high temperature situation exists (i.e. TCC

is active), the clocks will be modulated by alternately turning the clocks off and on at a

duty cycle specific to the processor (typically 30-50%). Clocks will not be off for more

than 3 microseconds when the TCC is active. Cycle times are processor speed

dependent and will decrease as processor core frequencies increase. A small amount of

hysteresis has been included to prevent rapid active/inactive transitions of the TCC

when the processor temperature is near its maximum operating temperature. Once the

temperature has dropped below the maximum operating temperature and the

hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

77

Thermal Specifications

With a thermal solution designed to meet the thermal profile, it is anticipated that the

TCC would only be activated for very short periods of time when running the most

power intensive applications. The processor performance impact due to these brief

periods of TCC activation is expected to be so minor that it would be immeasurable. A

thermal solution that is significantly under-designed may not be capable of cooling the

processor even when the TCC is active continuously. Refer to the Dual-Core Intel®

Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines for information on

designing a thermal solution.

The duty cycle for the TCC, when activated by the Thermal Monitor, is factory

configured and cannot be modified. The Thermal Monitor does not require any

additional hardware, software drivers, or interrupt handling routines.

6.2.2

Thermal Monitor 2

The Dual-Core Intel Xeon processor 7100 series also supports an additional power

reduction capability known as Thermal Monitor 2 (TM2). This mechanism provides an

efficient means for limiting the processor temperature by reducing the power

consumption within the processor. The Thermal Monitor (or Thermal Monitor 2) feature

must be enabled for the processor to be operating within specifications.

When Thermal Monitor 2 is enabled and a high temperature situation is detected, the

Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust

its operating frequency (via the bus multiplier) and input voltage (via the VID signals).

This combination of reduced frequency and VID results in a decrease to the processor

power consumption.

A processor enabled for Thermal Monitor 2 includes two operating points, each

consisting of a specific operating frequency and voltage. The first operating point

represents the normal operating condition for the processor. Under this condition, the

core-frequency-to-system-bus multiplier utilized by the processor is that contained in

the IA32_FLEX_BRVID_SEL MSR and the VID is that specified in Table 2-10. These

parameters represent normal system operation.

The second point consists of both a lower operating frequency and voltage. When the

TCC is activated, the processor automatically transitions to the new frequency. This

transition occurs very rapidly (on the order of 5 microseconds). During the frequency

transition, the processor is unable to service any bus requests, and consequently, all

bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until

the processor resumes operation at the new frequency.

Once the new operating frequency is engaged, the processor will transition to the new

core operating voltage by issuing a new VID code to the voltage regulator. The voltage

regulator must support dynamic VID steps in order to support Thermal Monitor 2.

During the voltage change, it will be necessary to transition through multiple VID codes

to reach the target operating voltage. Each step will be one VID table entry (see

Table 2-10). The processor continues to execute instructions during the voltage

transition. Operation at the lower voltage reduces the power consumption of the

processor.

A small amount of hysteresis has been included to prevent rapid active/inactive

transitions of the TCC when the processor temperature is near its maximum operating

temperature. Once the temperature has dropped below the maximum operating

temperature, and the hysteresis timer has expired, the operating frequency and

voltage transition back to the normal system operating point. Transition of the VID code

will occur first, in order to ensure proper operation once the processor reaches its

normal operating frequency. Refer to Figure 6-4 for an illustration of this ordering.

78

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Thermal Specifications

Figure 6-4. Thermal Monitor 2 Frequency and Voltage Ordering

T_TM2

Temperature

f_MAX

f_TM2

Frequency

V_NOM

V_TM2

Vcc

Time

T(hysteresis)

The PROCHOT# signal is asserted when a high temperature situation is detected,

regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.

If a processor has its Thermal Control Circuit activated via a Thermal Monitor 2 event,

and an Enhanced Intel SpeedStep® Technology transition to a higher target frequency

(through the applicable MSR write) is attempted, this frequency transition will be

delayed until the TCC is deactivated and the TM2 event is complete.

Note:

Not all processors are capable of supporting Thermal Monitor 2. More details on which

processor frequencies will support this feature will be provided in future releases of the

NDA Specification Update.

6.2.3

On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force

the processor to reduce its power consumption. This mechanism is referred to as “On-

Demand” mode and is distinct from the Thermal Monitor and Thermal Monitor 2

features. On-Demand mode is intended as a means to reduce system level power

consumption. Systems utilizing the Dual-Core Intel Xeon processor 7100 series

processor must not rely on software usage of this mechanism to limit the processor

temperature.

If bit 4 of the IA_32_CLOCK_MODULATION MSR is written to a ‘1’, the processor will

immediately reduce its power consumption via modulation (starting and stopping) of

the internal core clock, independent of the processor temperature. When using On-

Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of

the same IA_32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can

be programmed from 12.5% on / 87.5% off to 87.5% on / 12.5% off in 12.5%

increments. On-Demand mode may be used in conjunction with the Thermal Monitor or

Thermal Monitor 2. If Thermal Monitor is enabled and the system tries to enable On-

Demand mode at the same time the TCC is engaged, the factory configured duty cycle

of the TCC will override the duty cycle selected by the On-Demand mode.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

79

Thermal Specifications

6.2.4

PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot), is asserted when the processor die

temperature has reached its factory configured trip point. If the Thermal Monitor is

enabled (note that the Thermal Monitor must be enabled for the processor to be

operating within specification), the TCC will be active when PROCHOT# is asserted. The

processor can be configured to generate an interrupt upon the assertion or de-

assertion of PROCHOT#. Refer to the IA-32 Intel^®Architecture Software Developer’s

Manual and the Cedar Mill Processor Family BIOS Writer’s Guide for specific register

and programming details.

PROCHOT# is designed to assert at or a few degrees higher than maximum T_CASE(as

specified by the thermal profile) when dissipating TDP power, and cannot be interpreted

as an indication of processor case temperature. This temperature delta accounts for

processor package, lifetime, and manufacturing variations and attempts to ensure the

Thermal Control Circuit is not activated below maximum T_CASEwhen dissipating TDP

power. There is no defined or fixed correlation between the PROCHOT# trip

temperature, the case temperature, or the thermal diode temperature. Thermal

solutions must be designed to the processor specifications and cannot be adjusted

based on experimental measurements of T_CASE, PROCHOT#, or Tdiode on random

processor samples.

6.2.5

FORCEPR# Signal Pin

The FORCEPR# (force power reduction) input can be used by the platform to force the

Dual-Core Intel Xeon processor 7100 series to activate the TCC. If the Thermal Monitor

is enabled, the TCC will be activated upon the assertion of the FORCEPR# signal. The

TCC will remain active until the system deasserts FORCEPR#. FORCEPR# is an

asynchronous input. FORCEPR# can be used to thermally protect other system

components. To use the voltage regulator (VR) as an example, when the FORCEPR# pin

is asserted, the TCC in the processor will activate, reducing the current consumption of

the processor and the corresponding temperature of the VR.

It should be noted that assertion of FORCEPR# does not automatically assert

PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high

temperature situation is detected. A minimum pulse width of 500 microseconds is

recommended when FORCEPR# is asserted by the system. Sustained activation of the

FORCEPR# pin may cause noticeable platform performance degradation.

Refer to the appropriate platform design guide for details on implementing the

FORCEPR# signal feature.

6.2.6

THERMTRIP# Signal Pin

Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the

event of a catastrophic cooling failure, the processor will automatically shut down when

the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in

Table 5-1). At this point, the system bus signal THERMTRIP# will go active and stay

active as described in Table 5-1. THERMTRIP# activation is independent of processor

activity and does not generate any bus cycles. Intel also recommends removal of V_TT.

6.2.7

T

and Fan Speed Reduction

CONTROL

T_CONTROLis a temperature specification based on a temperature reading from the

thermal diode. The value for T_{CONTROL_OFFSET}will be calibrated in manufacturing and

configured for each processor. The T_CONTROLtemperature for a given processor can be

80

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Thermal Specifications

obtained by reading the IA32_TEMPERATURE_TARGET MSR in the processor. The

_{CONTROL_OFFSET}value that is read from the IA32_TEMPERATURE_TARGET MSR (1A2H)

T

must be converted from Hexadecimal to Decimal and added to a T_{CONTROL_BASE}value of

50°C for 150W TDP parts and added to a T_{CONTROL_BASE}value of 40°C for 95W TDP

parts.

The Platform Id Bits located in the IA32_PLATFORM_ID MSR (17H) Bits[52:50] may be

used by the BIOS to determine the TDP of the processor. A 150W TDP part has a

Platform ID of ‘001’(Processor Flag 1) and a 95W TDP part has a Platform ID of ‘101’

(Processor Flag 5). Refer to the Cedar Mill Processor Family BIOS Writers Guide for

specific register details.

The value of T_{CONTROL_OFFSET}may vary from 0x00h to 0x1Eh. Refer to the Cedar Mill

Processor Family BIOS Writers Guide for specific register details.

When Tdiode is above T_CONTROL, then T_CASEmust be at or below T_{CASE_MAX}as defined

by the thermal profile (see Figure 6-1 and Table 6-2 or Figure 6-2 and Table 6-3).

Otherwise, the processor temperature can be maintained at T_CONTROL

.

6.2.8

Thermal Diode

The processor incorporates two on-die thermal diodes. A thermal sensor located on the

processor package monitors the die temperature of the processor for thermal

management/long term die temperature change purposes. The thermal diodes are

separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the

behavior of the Thermal Monitor.

§

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

81

Thermal Specifications

82

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

7 Features

7.1

Power-On Configuration Options

Several configuration options can be set by hardware. The Dual-Core Intel Xeon

processor 7100 series samples its hardware configuration at reset, on the active-to-

inactive transition of RESET#. For specifications on these options, refer to Table 7-1.

The sampled information configures the processor for subsequent operation. These

configuration options can only be changed by another reset. All resets configure the

processor. For reset purposes, the processor does not distinguish between a “warm”

reset and a “power-on” reset.

Table 7-1.

Power-On Configuration Option Pins

1,2

Configuration Option

Output tri state

SMI#

or

A[39]# for Arb ID 3 (middle agent)

A[36]# for Arb ID 0 (end agent)

Execute BIST (Built-In Self Test)

In Order Queue de-pipelining (set IOQ depth to 1)

Disable MCERR# observation

INIT# or A[3]#

A[7]#

A[9]#

Disable BINIT# observation

A[10]#

APIC cluster ID

A[12:11]#

A[15]#

Disable bus parking

Core Frequency-to-Front Side Bus Multiplier

Symmetric agent arbitration ID

Disable Hyper-Threading Technology (HT Technology)

A[21:16]#

BR[1:0]#

A[31]#

Note:

1.

2.

Asserting this signal during RESET# selects the corresponding option.

Address pins not identified in this table as configuration options should not be asserted during RESET#.

7.2

Clock Control and Low Power States

The processor allows the use of HALT and Stop-Grant states to reduce power

consumption by stopping the clock to internal sections of the processor, depending on

each particular state. See Figure 7-1 for a visual representation of the processor low

power states.

The Dual-Core Intel Xeon processor 7100 series adds support for Enhanced HALT power

down state. Refer to Figure 7-1 and the following sections. For more configuration

details, also refer to the Cedar Mill Processor Family BIOS Writer’s Guide.

The Stop-Grant state requires chipset and BIOS support on multiprocessor systems. In

a multiprocessor system, all the STPCLK# signals are bussed together, thus all

processors are affected in unison. The Hyper-Threading Technology feature adds the

conditions that all logical processors share the same STPCLK# signal internally. When

the STPCLK# signal is asserted, the processor enters the Stop-Grant state, issuing a

Stop-Grant Special Bus Cycle (SBC) for each processor or logical processor. The chipset

needs to account for a variable number of processors asserting the Stop-Grant SBC on

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Features

the bus before allowing the processor to be transitioned into one of the lower processor

power states. Refer to the applicable chipset specification and the Cedar Mill Processor

Family BIOS Writer’s Guide for more information.

7.2.1

7.2.2

Normal State

This is the normal operating state for the processor.

HALT or Enhanced Power Down State

The Enhanced HALT power down state is configured and enabled via the BIOS. Refer to

the Cedar Mill Processor Family BIOS Writer’s Guide for Enhanced HALT state

configuration information. If the Enhanced HALT state is not enabled, the default power

down state entered will be HALT. Refer to the section below for details on HALT and

Enhanced HALT states.

7.2.2.1

HALT Power Down State

HALT is a low power state entered when all logical processors have executed the HALT

or MWAIT instruction. When one of the logical processors executes the HALT or MWAIT

instruction, that logical processor is halted; however, the other processor continues

normal operation. The processor transitions to the Normal state upon the occurrence of

SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the front

side bus. RESET# causes the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either

Normal Mode or the HALT Power Down state. See the IA-32 Intel^®Architecture Software

Developer's Manual, Volume III: System Programming Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT Power Down

state. When the system deasserts the STPCLK# interrupt, the processor returns

execution to the HALT state.

While in HALT Power Down state, the processor processes bus snoops and interrupts.

7.2.2.2

Enhanced HALT Power Down State

Enhanced HALT state is a low power state entered when all logical processors have

executed the HALT or MWAIT instructions and Enhanced HALT state has been enabled

via the BIOS. When one of the logical processors executes the HALT instruction, that

logical processor is halted; however, the other processor continues normal operation.

The Enhanced HALT state is generally a lower power state than the Stop Grant state.

The processor automatically transitions to a lower core frequency and voltage operating

point before entering the Enhanced HALT state. Note that the processor FSB frequency

is not altered; only the internal core frequency is changed. When entering the low

power state, the processor first switches to the lower bus ratio and then transitions to

the lower VID.

While in the Enhanced HALT state, the processor processes bus snoops.

The processor exits the Enhanced HALT state when a break event occurs. When the

processor exits the Enhanced HALT state, it first transitions the VID to the original

value and then changes the bus ratio back to the original value.

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Figure 7-1. Stop Clock State Machine

HALT or MWAIT Instruction and

HALT Bus Cycle Generated

Enhanced HALT or HALT State

BCLK running

Normal State

INIT#, BINIT#, INTR, NMI, SMI#,

RESET#, FSB interrupts

Normal execution

Snoops and interrupts allowed

Snoop

Event

Occurs Serviced

Snoop

Event

STPCLK#

Asserted

STPCLK#

De-asserted

Enhanced HALT Snoop or HALT

Snoop State

BCLK running

Service snoops to caches

Snoop Event Occurs

Snoop Event Serviced

Stop Grant State

Stop Grant Snoop State

BCLK running

Snoops and interrupts allowed

Service snoops to caches

7.2.3

Stop-Grant State

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20

bus clocks after the response phase of the processor-issued Stop Grant Acknowledge

special bus cycle. For the Dual-Core Intel Xeon processor 7100 series, both logical

processors must be in the Stop-Grant state before the deassertion of STPCLK#.

Since the AGTL+ signal pins receive power from the front side bus, these pins should

not be driven (allowing the level to return to V_TT) for minimum power drawn by the

termination resistors in this state. In addition, all other input pins on the front side bus

should be driven to the inactive state.

BINIT# is not serviced while the processor is in Stop-Grant state. The event is latched

and can be serviced by software upon exit from the Stop-Grant state.

RESET# causes the processor to immediately initialize itself, but the processor will stay

in Stop-Grant state. A transition back to the Normal state occurs with the deassertion

of the STPCLK# signal.

A transition to the Grant Snoop state occurs when the processor detects a snoop on the

front side bus (see Section 7.2.4).

While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] are latched by the

processor, and only serviced when the processor returns to the Normal state. Only one

occurrence of each event is recognized upon return to the Normal state.

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While in Stop-Grant state, the processor processes snoops on the front side bus and

latches interrupts delivered on the front side bus.

The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is

asserted if there is any pending interrupt latched within the processor. Pending

interrupts that are blocked by the EFLAGS.IF bit being clear still cause assertion of

PBE#. Assertion of PBE# indicates to system logic that it should return the processor to

the Normal state.

7.2.4

Enhanced HALT Snoop State or HALT Snoop State,

Stop Grant Snoop State

The Enhanced HALT Snoop state is used in conjunction with the Enhanced HALT state.

If Enhanced HALT state is not enabled in the BIOS, the default Snoop state entered will

be the HALT Snoop state. Refer to the sections below for details on HALT Snoop state,

Grant Snoop state and Enhanced HALT Snoop state.

7.2.4.1

HALT Snoop State, Stop Grant Snoop State

The processor responds to snoop or interrupt transactions on the front side bus while in

Stop-Grant state or in HALT Power Down state. During a snoop or interrupt transaction,

the processor enters the HALT/Grant Snoop state. The processor stays in this state

until the snoop on the front side bus has been serviced (whether by the processor or

another agent on the front side bus) or the interrupt has been latched. After the snoop

is serviced or the interrupt is latched, the processor will return to the Stop-Grant state

or HALT Power Down state, as appropriate.

7.2.4.2

Enhanced HALT Snoop State

The Enhanced HALT Snoop state is the default Snoop state when the Enhanced HALT

state is enabled via the BIOS. The processor remains in the lower bus ratio and VID

operating point of the Enhanced HALT state.

While in the Enhanced HALT Snoop state, snoops and interrupt transactions are

handled the same way as in the HALT Snoop state. After the snoop is serviced or the

interrupt is latched, the processor returns to the Enhanced HALT state.

7.3

Enhanced Intel SpeedStep® Technology

Enhanced Intel SpeedStep Technology enables the processor to switch between

frequency and voltage points, which may result in platform power savings. In order to

support this technology, the system must support dynamic VID transitions. Switching

between voltage/frequency states is software controlled. For more configuration details

also refer to the Cedar Mill Processor Family BIOS Writer's Guide.

Note:

Not all processors are capable of supporting Enhanced Intel SpeedStep Technology.

More details on which processor frequencies will support this feature will be provided in

future releases of the NDA Specification Update.

Enhanced Intel SpeedStep Technology is a technology that creates processor

performance states (P-states). P-states are power consumption and capability states

within the Normal state. Enhanced Intel SpeedStep technology enables real-time

dynamic switching between frequency and voltage points. It alters the performance of

the processor by changing the bus to core frequency ratio and voltage. This allows the

processor to run at different core frequencies and voltages to best serve the

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performance and power requirements of the processor and system. Note that the front

side bus is not altered; only the internal core frequency is changed. In order to run at

reduced power consumption, the voltage is altered in step with the bus ratio.

The following are key features of Enhanced Intel SpeedStep technology:

• Voltage/frequency selection is software controlled by writing to processor MSR’s

(Model Specific Registers), thus eliminating chipset dependency.

— If the target frequency is higher than the current frequency, V_CCis incremented

in steps (+12.5 mV) by placing a new value on the VID signals and the

processor shifts to the new frequency. Note that the top frequency for the

processor can not be exceeded.

— If the target frequency is lower than the current frequency, the processor shifts

to the new frequency and V_CCis then decremented in steps (-12.5 mV) by

changing the target VID through the VID signals.

Refer to the Cedar Mill Processor Family BIOS Writer’s Guide for specific information to

enable and configure Enhanced Intel SpeedStep technology in BIOS.

7.4

System Management Bus (SMBus) Interface

The Dual-Core Intel Xeon processor 7100 series package includes an SMBus interface

which allows access to a memory component with two sections (referred to as the

Processor Information ROM and the Scratch EEPROM) and a thermal sensor on the

substrate. The SMBus thermal sensor may be used to read the thermal diode

mentioned in Section 6.2.8. These devices and their features are described below.

The SMBus thermal sensor and its associated thermal diode are not related to and are

completely independent of the precision, on-die temperature sensor and thermal

control circuit (TCC) of the Thermal Monitor or Thermal Monitor 2 features discussed in

Section 6.2.1.

The processor SMBus implementation uses the clock and data signals of the System

Management Bus (SMBus) Specification. It does not implement the SMBSUS# signal.

Layout and routing guidelines are available in the appropriate platform design guide

document.

For platforms which do not implement any of the SMBus features found on the

processor, all of the SMBus connections, except SM_VCC, to the socket pins may be

left unconnected (SM_ALERT#, SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0],

SM_WP).

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Figure 7-2. Logical Schematic of SMBus Circuitry

Note: Actual implementation may vary. This figure is provided to offer a general understanding of the

architecture. All SMBus pull-up and pull-down resistors are 10 kΩ and located on the processor.

7.4.1

SMBus Device Addressing

Of the addresses broadcast across the SMBus, the memory component claims those of

the form “1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors

on the system baseboard. These address pins are pulled down weakly (10 kΩ) on the

processor substrate to ensure that the memory components are in a known state in

systems which do not support the SMBus (or only support a partial implementation).

The “Z” bit is the read/write bit for the serial bus transaction.

The thermal sensor internally decodes one of three upper address patterns from the

bus of the form “0011XXXZb”, “1001XXXZb”, or “0101XXXZb”. The device’s addressing,

as implemented, uses the SM_TS_A[1:0] pins in either the HI, LO, or Hi-Z state.

Therefore, the thermal sensor supports nine unique addresses. To set either pin for the

Hi-Z state, the pin must be left floating. As before, the “Z” bit is the read/write bit for

the serial transaction.

Note that addresses of the form “0000XXXXb” are Reserved and should not be

generated by an SMBus master. The thermal sensor samples and latches the

SM_TS_A[1:0] signals at power-up. System designers should ensure that these signals

are at valid V_IH, V_IL, or floating input levels prior to or while the thermal sensor’s

SM_VCC supply powers up. This should be done by pulling the pins to SM_VCC or V_SS

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via a 1 kΩ or smaller resistor, or leaving the pins floating to achieve the Hi-Z state. If

the system designer wants to drive the SM_TS_A[1:0] pins with logic, the designer

must still ensure that the pins are at valid input levels prior to or while the SM_VCC

supply ramps up. The system designer must also ensure that their particular

implementation does not add excessive capacitance to the address inputs. Excess

capacitance at the address inputs may cause address recognition problems. Refer to

the appropriate platform design guide document.

Figure 7-2 shows a logical diagram of the pin connections. Table 7-2 and Table 7-3

describe the address pin connections and how they affect the addressing of the

devices.

Table 7-2.

Thermal Sensor SMBus Addressing

Address

(Hex)

Upper

Device Select

8-bit Address Word on Serial Bus

b[7:0]

Address¹

SM_TS_A1

SM_TS_A0

3Xh

5Xh

9Xh

0011

0101

1001

0

Z²

1

0011000Xb

0011001Xb

0011010Xb

0101001Xb

0101010Xb

0101011Xb

1001100Xb

1001101Xb

1001110Xb

0

Z²

1

0

Z²

1

0

Z²

1

Notes:

1.

2.

Upper address bits are decoded in conjunction with the device select pins.

A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.

Note:

System management software must be aware of the processor dependent addresses

for the thermal sensor.

Table 7-3.

Memory Device SMBus Addressing

Address

(Hex)

Upper

Device Select

R/W

bit 0

1

Address

SM_EP_A2

bit 3

SM_EP_A1

bit 2

SM_EP_A0

bit 1

bits 7-4

A0h/A1h

A2h/A3h

A4h/A5h

A6h/A7h

A8h/A9h

AAh/ABh

ACh/ADh

AEh/AFh

1010

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

Note:

1. This addressing scheme will support up to 8 processors on a single SMBus.

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7.4.2

PIROM and Scratch EEPROM Supported SMBus

Transactions

The Processor Information ROM (PIROM) responds to two SMBus packet types: Read

Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge a

Write Byte command but ignore the data. The Scratch EEPROM responds to Read Byte

and Write Byte commands. Table 7-4 diagrams the Read Byte command. Table 7-5

diagrams the Write Byte command. Following a write cycle to the scratch ROM,

software must allow a minimum of 10 ms before accessing either ROM of the processor.

In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents

a read bit, ‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’

represents a negative acknowledge (NACK). The shaded bits are transmitted by the

Processor Information ROM or Scratch EEPROM, and the bits that aren’t shaded are

transmitted by the SMBus host controller. In the tables, the data addresses indicate 8

bits. The SMBus host controller should transmit 8 bits with the most significant bit

indicating which section of the EEPROM is to be addressed: the Processor Information

ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).

Table 7-4.

Read Byte SMBus Packet

Slave

Addres

s

Comman

d Code

Slave

Address

S

Write

A

S

Read

A

Data

///

P

1

7-bits

1

8-bits

1

7-bits

1

8-bits

1

Table 7-5.

Write Byte SMBus Packet

S

Slave Address

Write

A

Command Code

A

Data

A

P

1

7-bits

1

8-bits

1

8-bits

1

7.4.3

Processor Information ROM (PIROM)

The lower half (128 bytes) of the SMBus memory component is an electrically

programmed read-only memory with information about the processor. This information

is permanently write-protected. Table 7-6 shows the data fields and Section 7.4.3

provides the formats of the data fields included in the Processor Information ROM

(PIROM).

The PIROM consists of the following sections:

• Header

• Processor Data

• Processor Core Data

• Cache Data

• Package Data

• Part Number Data

• Thermal Reference Data

• Feature Data

• Other Data

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Table 7-6.

Processor Information ROM Data Sections (Sheet 1 of 2)

# of

Bits

Offset/Section

Function

Notes

Header:

00h

01 - 02h

03h

8

16

8

Data Format Revision

PIROM Size

Two 4-bit hex digits

Size in bytes (MSB first)

Processor Data Address

Byte pointer, 00h if not present

04h

8

Processor Core Data

Address

05h

06h

07h

08h

8

L3 Cache Data Address

Package Data Address

Byte pointer, 00h if not present

Part Number Data Address

Thermal Reference Data

Address

09h

0Ah

8

Feature Data Address

Other Data Address

Reserved

Byte pointer, 00h if not present

Reserved

0B - 0Ch

0Dh

16

8

Checksum

1 byte checksum

Processor Data:

0E - 13h

14h

48

S-spec/QDF Number

Six 8-bit ASCII characters

6

2

Reserved

Sample/Production

Reserved (most significant bits)

00b = Sample, 01b = Production

15h

8

Checksum

1 byte checksum

Processor Core

Data:

16 - 17h

2

4

Processor Core Type

Processor Core Family

Processor Core Model

Processor Core Stepping

Reserved

From CPUID

4

From CPUID

4

From CPUID

2

Reserved for future use

16-bit binary number (in MHz)

18 - 19h

1A - 1Bh

1Ch

16

Reserved

Front Side Bus Speed

2

6

Multiprocessor Support

Reserved

00b = UP,01b = DP,10b = RSVD,11b = MP

Reserved

1D - 1Eh

1F - 20h

16

Maximum Core Frequency

Maximum Core VID

16-bit binary number (in MHz)

Maximum V requested by VID outputs in

CC

mV

21 - 22h

23h

16

8

Minimum Core Voltage

Minimum processor DC V in mV

CC

T

Maximum

Maximum case temperature spec in °C

1 byte checksum

CASE

24h

8

Checksum

Cache Data:

25 - 26h

27 - 28h

29 - 2Ah

2B - 2Ch

16

Reserved

Reserved for future use

16-bit binary number (in KB)

L2 Cache Size

L3 Cache Size

Maximum Cache CVID

Maximum V

requested by CVID

outputs in mV

CACHE

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Table 7-6.

Processor Information ROM Data Sections (Sheet 2 of 2)

# of

Bits

Offset/Section

Function

Notes

2D - 2Eh

16

8

Minimum Cache Voltage

Reserved

Minimum processor DC V

Reserved

in mV

CACHE

2F - 30h

31h

Checksum

1 byte checksum

Package Data:

32 - 35h

32

8

Package Revision

Reserved

Four 8-bit ASCII characters

Reserved for future use

1 byte checksum

36h

37h

8

Checksum

Part Number Data:

38 - 3Eh

56

112

64

Processor Part Number

Reserved

Seven 8-bit ASCII characters

Reserved

3F - 4Ch

4D - 54h

Processor Electronic

Signature

64-bit identification number

55 - 6Eh

6Fh

208

8

Reserved

Checksum

1 byte checksum

Thermal Ref. Data:

70h

8

16

8

Reserved

Checksum

Reserved

71 - 72h

73h

1 byte checksum

Feature Data:

74 - 77h

32

8

Processor Core Feature

Flags

From CPUID function 1, EDX contents

78h

Processor Feature Flags

[7] = Multi-Core

[6] = Serial Signature

[5] = Electronic Signature Present

[4] = Thermal Sense Device Present

[3] = Reserved

[2] = OEM EEPROM Present

[1] = Core VID Present

[0] = L3 Cache Present

79h

7Ah

8

Processor Thread and Core

Information

[7:4] = Reserved

[3:2] = Number of cores

[1:0] = Number of threads per core

Additional Processor Feature [7] = Reserved

®

Flags

[6] = Intel Cache Safe Technology

[5] = C1E State

®

[4] = Intel Virtualization Technology

[3] = Execute Disable

®

[2] = Intel 64

[1] = Thermal Monitor TM2

®

[0] = Enhanced Intel SpeedStep

Technology

7B-7Ch

16

Thermal Adjustment Factors [15:8] = Measurement Correction Factor

(Pending)

Reserved

Checksum

[7:0] = Temperature Target

7D-7Eh

7Fh

16

8

Reserved

1 byte checksum

Details on each of these sections are described below.

Note:

Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not

rely on this model.

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7.4.3.1

Header

To maintain backward compatibility, the Header defines the starting address for each

subsequent section of the PIROM. Software should check for the offset before reading

data from a particular section of the ROM.

Example: Code looking for the cache data of a processor would read offset 05h to find

a value of 25h. 25h is the first address within the 'Cache Data' section of the PIROM.

7.4.3.1.1

DFR: Data Format Revision

This location identifies the data format revision of the PIROM data structure. Writes to

this register have no effect.

Offset:

00h

Bit

Description

7:0

Data Format Revision

The data format revision is used whenever fields within the PIROM are

redefined. The initial definition will begin at a value of 1. If a field, or bit

assignment within a field, is changed such that software needs to discern

between the old and new definition, then the data format revision field will be

incremented.

00h: Reserved

01h: Initial definition

02h: Second revision

03h: Third revision (Defined by this EMTS)

04h-FFh: Reserved

7.4.3.1.2

PISIZE: PIROM Size

This location identifies the PIROM size. Writes to this register have no effect.

Offset:

01h-02h

Bit

Description

15:0

PIROM Size

The PIROM size provides the size of the device in hex bytes. The MSB is at

location 01h, the LSB is at location 02h.

0000h - 007Fh: Reserved

0080h: 128 byte PIROM size

0081- FFFFh: Reserved

7.4.3.1.3

PDA: Processor Data Address

This location provides the offset to the Processor Data Section. Writes to this register

have no effect.

Offset:

03h

Bit

Description

7:0

Processor Data Address

Byte pointer to the Processor Data section

00h: Processor Data section not present

01h - 0Dh: Reserved

0Eh: Processor Data section pointer value

0Fh-FFh: Reserved

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Features

7.4.3.1.4

7.4.3.1.5

7.4.3.1.6

PCDA: Processor Core Data Address

This location provides the offset to the Processor Core Data Section. Writes to this

register have no effect.

Offset:

04h

Bit

Description

7:0

Processor Core Data Address

Byte pointer to the Processor Data section

00h: Processor Core Data section not present

01h - 15h: Reserved

16h: Processor Core Data section pointer value

17h-FFh: Reserved

L3CDA: L3 Cache Data Address

This location provides the offset to the L3 Cache Data Section. Writes to this register

have no effect.

Offset:

05h

Bit

Description

7:0

L3 Cache Data Address

Byte pointer to the L3 Cache Data section

00h: L3 Cache Data section not present

01h - 24h: Reserved

25h: L3 Cache Data section pointer value

26h-FFh: Reserved

PKDA: Package Data Address

This location provides the offset to the Package Data Section. Writes to this register

have no effect.

Offset:

06h

Bit

Description

7:0

Package Data Address

Byte pointer to the Package Data section

00h: Package Data section not present

01h - 31h: Reserved

32h: Package Data section pointer value

33h-FFh: Reserved

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Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

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7.4.3.1.7

PNDA: Part Number Data Address

This location provides the offset to the Part Number Data Section. Writes to this

register have no effect.

Offset:

07h

Bit

Description

7:0

Part Number Data Address

Byte pointer to the Part Number Data section

00h: Part Number Data section not present

01h - 37h: Reserved

38h: Part Number Data section pointer value

39h-FFh: Reserved

7.4.3.1.8

TRDA: Thermal Reference Data Address

This location provides the offset to the Thermal Reference Data Section. Writes to this

register have no effect.

Offset:

08h

Bit

Description

7:0

Thermal Reference Data Address

Byte pointer to the Thermal Reference Data section

00h: Thermal Reference Data section not present

01h - 6Fh: Reserved

70h: Thermal Reference Data section pointer value

71h-FFh: Reserved

7.4.3.1.9

FDA: Feature Data Address

This location provides the offset to the Feature Data Section. Writes to this register

have no effect.

Offset:

09h

Bit

Description

7:0

Feature Data Address

Byte pointer to the Feature Data section

00h: Feature Data section not present

01h - 73h: Reserved

74h: Feature Data section pointer value

75h-FFh: Reserved

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7.4.3.1.10

ODA: Other Data Address

This location provides the offset to the Other Data Section. Writes to this register have

no effect.

Offset:

0Ah

Bit

Description

7:0

Other Data Address

Byte pointer to the Other Data section

00h: Other Data section not present

01h - 7Dh: Reserved

7Eh: Other Data section pointer value

7Fh- FFh: Reserved

7.4.3.1.11

RES1: Reserved 1

This locations are reserved. Writes to this register have no effect.

Offset:

0Bh-0Ch

Bit

Description

15:0

RESERVED

0000h-FFFFh: Reserved

7.4.3.1.12

HCKS: Header Checksum

This location provides the checksum of the Header Section. Writes to this register have

no effect.

Offset:

0Dh

Bit

Description

7:0

Header Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.2

Processor Data

This section contains two pieces of data:

• The S-spec/QDF of the part in ASCII format

• (1) 2-bit field to declare if the part is a pre-production sample or a production unit

7.4.3.2.1

SQNUM: S-Spec QDF Number

This location provides the S-SPec or QDF number of the processor. The S-spec/QDF

field is six ASCII characters wide and is programmed with the same S-spec/QDF value

as marked on the processor. If the value is less than six characters in length, leading

spaces (20h) are programmed in this field. Writes to this register have no effect.

Example: A processor with a QDF mark of QEU5 contains the following in field 0E-13h:

20, 20, 51, 45, 55, 35h. This data consists of two blanks at 0Eh and 0Fh followed by

the ASCII codes for QEU5 in locations 10 - 13h.

96

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

Offset:

0Eh-13h

Bit

Description

47:40

Character 6

S-SPEC or QDF character or 20h

00h-0FFh: ASCII character

39:32

31:24

23:16

15:8

Character 5

S-SPEC or QDF character or 20h

00h-0FFh: ASCII character

Character 4

S-SPEC or QDF character

00h-0FFh: ASCII character

Character 3

S-SPEC or QDF character

00h-0FFh: ASCII character

Character 2

S-SPEC or QDF character

00h-0FFh: ASCII character

7:0

Character 1

S-SPEC or QDF character

00h-0FFh: ASCII character

7.4.3.2.2

SAMPROD: Sample/Production

This location contains the sample/production field, which is a two-bit field and is LSB

aligned. All Q-spec material will use a value of 00b. All S-spec material will use a value

of 01b. All other values are reserved. Writes to this register have no effect.

Example: A processor with a Qxxx mark (engineering sample) will have offset 14h set

to 00h. A processor with an Sxxxx mark (production unit) will use 01h at offset 14h.

Offset:

14h

Bit

Description

7:2

RESERVED

000000b-111111b: Reserved

1:0

Sample/Production

Sample or Production indictor

00b: Sample

01b: Production

10b-11b: Reserved

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

97

Features

7.4.3.2.3

PDCKS: Processor Data Checksum

This location provides the checksum of the Processor Data Section. Writes to this

register have no effect.

Offset:

15h

Bit

Description

7:0

Processor Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.3

Processor Core Data

This section contains core silicon-related data.

7.4.3.3.1

CPUID: CPUID

This location contains the CPUID, Processor Type, Family, Model and Stepping. The

CPUID field is a copy of the results in EAX[13:0] from Function 1 of the CPUID

instruction. The MSB is at location 16h, the LSB is at location 17h. Writes to this

register have no effect.

Example: If the CPUID of a processor is 0F68h, then the value programmed into offset

16 - 17h of the PIROM is 3DA0h.

Note:

The field is not aligned on a byte boundary since the first two bits of the offset are

reserved. Thus, the data must be shifted right by two in order to obtain the same

results.

The first two bits of the PIROM are reserved, as highlighted in the example below.

CPUID instruction results 0000

1111

1101

0110

1010

1000 (0F68h)

PIROM content

0011

0000 (3DA0h)

Offset:

16h-17h

Bit

Description

15:14

Processor Type

00b-11b: Processor Type

13:10

9:6

Processor Family

00h-0Fh: Processor Family

Processor Model

00h-0Fh: Processor Model

5:2

Processor Stepping

00h-0Fh: Processor Stepping

1:0

Reserved

00b-11b: Reserved

98

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

7.4.3.3.2

RES2: Reserved 2

These locations are reserved. Writes to this register have no effect.

Offset:

18h-19h

Bit

Description

15:0

RESERVED 2

0000h-FFFFh: Reserved

7.4.3.3.3

FSB: Front Side Bus Speed

This location contains the front side bus frequency information. Systems may need to

read this offset to decide if all installed processors support the same front side bus

speed. Because the Intel NetBurst microarchitecture bus is described as a 4X data bus,

the frequency given in this field is currently 667 MHz or 800 MHz. The data provided is

the speed, rounded to a whole number, and reflected in hex. Writes to this register

have no effect.

Example: The Dual-Core Intel Xeon processor 7100 series supports a 667 or 800 MHz

front side bus. Therefore, offset 1A - 1Bh has a value of 029Bh or 0320h.

Offset:

1Ah-1Bh

Bit

Description

15:0

Front Side Bus Speed

0000h-029Ah: Reserved

029Bh: 667 MHz

029Ch-031Fh: Reserved

0320h: 800 Mhz

0321h-FFFFh: Reserved

7.4.3.3.4

MPSUP: Multiprocessor Support

This location contains 2 bits for representing the supported number of physical

processors on the bus. These two bits are MSB aligned where 00b equates to single-

processor operation, 01b is a dual-processor operation, and 11b represents multi-

processor operation. The Dual-Core Intel Xeon processor 7100 series is an MP

processor. The remaining six bits in this field are reserved for the future use. Writes to

this register have no effect.

Example: An MP processor will use C0h at offset 1Ch.

Offset:

1Ch

Bit

Description

7:6

Multiprocessor Support

UP, DP or MP indictor

00b: UP

01b: DP

10b: Reserved

11b: MP

5:0

RESERVED

000000b-111111b: Reserved

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

99

Features

7.4.3.3.5

MCF: Maximum Core Frequency

This location contains the maximum core frequency for the processor. The frequency

should equate to the markings on the processor and/or the QDF/S-spec speed even if

the parts are not limited or locked to the intended speed. Format of this field is in MHz,

rounded to a whole number, and encoded in hex format. Writes to this register have no

effect.

Example: A 3.40 GHz processor will have a value of 0D48h, which equates to 3400

decimal. Therefore, offset 1D - 1Eh has a value of 0D48.

Offset:

1Dh-1Eh

Bit

Description

15:0

Maximum Core Frequency

0000h-09C3: Reserved

09C4h: 2.5 Ghz

09C5h-0A27h: Reserved

0A28h: 2.6 GHz

0A29h-0BB7h: Reserved

0BB8h: 3.0 GHz

0BB9h-0C5Eh: Reserved

0C5Fh: 3.167 GHz

0C60h-0C7Fh: Reserved

0C80h: 3.2 GHz

0C81h-0D5Eh: Reserved

0D05h: 3.333 GHz

0D06h-0D47h: Reserved

0D48h: 3.4 GHz

0D49h-FFFFh: Reserved

7.4.3.3.6

MAXVID: Maximum Core VID

This location contains the maximum Core VID (Voltage Identification) voltage that may

be requested via the VID pins. This field, rounded to the next thousandth, is in mV and

is reflected in hex. Writes to this register have no effect.

Example: From Table 2-10 the maximum VID is 1.3500 V maximum voltage. Offset 1F

- 20h would contain 0546h (1350 decimal).

Offset:

1Fh-20h

Bit

Description

15:0

Maximum Core VID

0000h-0545h: Reserved

0546h: 1.35 V

0548h-FFFFh: Reserved

7.4.3.3.7

MINV: Minimum Core Voltage

This location contains the minimum Processor Core voltage. This field, rounded to the

next thousandth, is in mV and is reflected in hex. The minimum V_CCreflected in this

field is the minimum allowable voltage assuming the FMB maximum current draw.

Writes to this register have no effect.

Note:

The minimum core voltage value in offset 21 - 22h is a single value that assumes the

FMB maximum current draw. Refer to Table 2-10 and Table 2-11 for the minimum core

voltage specifications based on actual real-time current draw.

100

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

Example: For a Dual-Core Intel Xeon processor 7100 series the minimum voltage is

0.991 V = 1.100 V (Min VID) - 0.209 V (Voltage Offset at maximum current). Offset 21

- 22h would contain 03DFh (0991 decimal).

Offset:

21h-22h

Bit

Description

15:0

Minimum Core Voltage

0000h-03DEh: Reserved

03DF: 0.991 V

03E0h-FFFFh: Reserved

7.4.3.3.8

TCASE: T_CASEMaximum

This location provides the maximum T_CASEfor the processor. The field reflects

temperature in degrees Celsius in hex format. This data can be found in the Table 6-1.

The thermal specifications are specified at the case Integrated Heat Spreader

(IHS).Writes to this register have no effect.

Offset:

23h

Bit

Description

7:0

T

Maximum

CASE

00h-FFh: Maximum Case Temperature of the processor

7.4.3.3.9

PCDCKS: Processor Core Data Checksum

This location provides the checksum of the Processor Core Data Section. Writes to this

register have no effect.

Offset:

24h

Bit

Description

7:0

Processor Core Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.4

Cache Data

This section contains cache-related data.

7.4.3.4.1

RES3: Reserved 3

These locations are reserved. Writes to this register have no effect.

Offset:

25h-26h

Bit

Description

15:0

RESERVED 3

0000h-FFFFh: Reserved

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

101

Features

7.4.3.4.2

L2SIZE: L2 Cache Size

This location contains the size of the level two cache in kilobytes. Writes to this register

have no effect.

Example: The Dual-Core Intel Xeon processor 7100 series has a 2 MB (2048 KB) L2

cache total (1 MB L2 cache per core). Thus, offset 27 - 28h will contain 0800h.

Offset:

27h-28h

Bit

Description

15:0

L2 Cache Size

0000h-07FFh: Reserved

0800h: 2 MB

0801h-FFFFh: Reserved

7.4.3.4.3

L3SIZE: L3 Cache Size

This location contains the size of the level three cache in kilobytes. Writes to this

register have no effect.

Example: The Dual-Core Intel Xeon processor 7100 series has either a 4 MB

(4096 KB), 8 MB (8192 KB) or 16 MB (16384 KB) L3 cache. Thus, offset 29 - 2Ah will

contain 1000h (for 4 MB), 2000h (for 8 MB) or 4000h (for 16 MB).

Offset:

29h-2Ah

Bit

Description

15:0

L3 Cache Size

0000h-0FFFh: Reserved

1000h: 4MB

1001h-1FFFh: Reserved

2000h: 8MB

2001h-3FFFh: Reserved

4000h: 16MB

4001h-FFFFh: Reserved

7.4.3.4.4

MAXCVID: Maximum Cache VID

This location contains the maximum Cache VID (Voltage Identification) voltage that

may be requested via the CVID pins. This field, rounded to the next thousandth, is in

mV and is reflected in hex. Writes to this register have no effect.

Example: From Table 2-10 the maximum CVID is 1.3500 V maximum voltage. Offset

2B - 2Ch would contain 0546h (1350 decimal).

Offset:

2Bh-2Ch

Bit

Description

15:0

Maximum Cache VID

0000h-0545h: Reserved

0546h: 1.35 V

0548h-FFFFh: Reserved

102

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

7.4.3.4.5

MINCV: Minimum Cache Voltage

This location contains the minimum Cache voltage. This field, rounded to the next

thousandth, is in mV and is reflected in hex. The minimum V_CACHEreflected in this field

is the minimum allowable voltage assuming the FMB maximum current draw for two

processors. Writes to this register have no effect.

Note:

The minimum core voltage value in offset 2D - 2Eh is a single value that assumes the

FMB maximum current draw for two processors. Refer to Table 2-10 and Table 2-12 for

the minimum cache voltage specifications based on actual real-time current draw.

Example: For a Dual-Core Intel Xeon processor 7100 series the minimum voltage is

0.802 V = 1.100 V (Min CVID) - 0.298 V (Voltage Offset at maximum current). Offset

2D - 2Eh would contain 0322h (0802 decimal).

Offset:

2Dh-2Eh

Bit

Description

15:0

Minimum Cache Voltage

0000h-0321h: Reserved

0322: 0.802 V

0323h-FFFFh: Reserved

7.4.3.4.6

RES4: Reserved 4

These locations are reserved. Writes to this register have no effect.

Offset:

2Fh-30h

Bit

Description

15:0

RESERVED 4

0000h-FFFFh: Reserved

7.4.3.4.7

CDCKS: Cache Data Checksum

This location provides the checksum of the Cache Data Section. Writes to this register

have no effect.

Offset:

31h

Bit

Description

7:0

Cache Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.5

Package Data

This section provides package revision information.

7.4.3.5.1

PREV: Package Revision

This location tracks the highest level package revision. It is provided in ASCII format of

four characters (8 bits x 4 characters = 32 bits). The package is documented as 1.0,

2.0, etc. If this only consumes three ASCII characters, a leading space is provided in

the data field.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

103

Features

Example: The A-0 and A-1 steppings of the Dual-Core Intel Xeon processor 7100

series utilizes the first revision package (FC-mPGA4). Thus, at offset 32-35h, the data

is a space followed by 1.0. In hex, this would be 20, 31, 2E, 30. The B-0 stepping of the

Dual-Core Intel Xeon processor 7100 series utilizes the second revision package

(FC-mPGA6). Thus, at offset 32-35h, the data is a space followed by 2.0. In hex, this

would be 20, 32, 2E, 30.

Offset:

32h-35h

Bit

Description

31:24

Character 4

ASCII character or 20h

00h-0FFh: ASCII character

23:16

15:8

7:0

Character 3

ASCII character

00h-0FFh: ASCII character

Character 2

ASCII character

00h-0FFh: ASCII character

Character 1

ASCII character

00h-0FFh: ASCII character

7.4.3.5.2

RES5: Reserved 5

This location is reserved. Writes to this register have no effect.

Offset:

36h

Bit

Description

7:0

RESERVED 5

00h-FFh: Reserved

7.4.3.5.3

PKDCKS: Package Data Checksum

This location provides the checksum of the Package Data Section. Writes to this register

have no effect.

Offset:

37h

Bit

Description

7:0

Package Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.6

Part Number Data

This section provides traceability. There are 208 available bytes in this section for

future use.

104

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

7.4.3.6.1

PREV: Package Revision

This location contains seven ASCII characters reflecting the Intel part number for the

processor. This information is typically marked on the outside of the processor. If the

part number is less than 7 characters, a leading space is inserted into the value. The

part number should match the information found in the marking specification found in

Section 3. Writes to this register have no effect.

Example: A processor with a part number of 80546KF will have data found at offset 38

- 3Eh is 38, 30, 35, 34, 36, 4B, 46.

Offset:

38h-3Eh

Bit

Description

4F:48

Character 7

ASCII character or 20h

00h-0FFh: ASCII character

47:40

39:32

31:24

23:16

15:8

Character 6

ASCII character or 20h

00h-0FFh: ASCII character

Character 5

ASCII character or 20h

00h-0FFh: ASCII character

Character 4

ASCII character

00h-0FFh: ASCII character

Character 3

ASCII character

00h-0FFh: ASCII character

Character 2

ASCII character

00h-0FFh: ASCII character

7:0

Character 1

ASCII character

00h-0FFh: ASCII character

7.4.3.6.2

RES6: Reserved 6

This location is reserved. Writes to this register have no effect.

Offset:

3Fh-4Ch

Bit

Description

111:0

RESERVED 6

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

105

Features

7.4.3.6.3

PSERSIG: Processor Serial/Electronic Signature

This location contains a 64-bit identification number. The value in this field is either a

serial signature or an electronic signature. Bits 5 & 6 of the Processor Feature Flags

(Offset 78h) indicates which signature is present. Intel does not guarantee that each

processor will have a unique value in this field. Writes to this register have no effect.

Offset:

4Dh=54h

Bit

Description

63:0

Processor Serial/Electronic Signature

00000000h-FFFFFFFFh: Electronic Signature

7.4.3.6.4

RES7: Reserved 7

This location is reserved. Writes to this register have no effect.

Offset:

55h-6Eh

Bit

Description

207:0

RESERVED 7

7.4.3.6.5

PNDCKS: Part Number Data Checksum

This location provides the checksum of the Part Number Data Section. Writes to this

register have no effect.

Offset:

6F

Bit

Description

7:0

Part Number Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.7

Thermal Reference Data

This section is reserved for future use.

7.4.3.7.1

RES8: Reserved 8

This location is reserved. Writes to this register have no effect.

Offset:

70h

Bit

Description

7:0

RESERVED 8

106

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

7.4.3.7.2

RES9: Reserved 9

This location is reserved. Writes to this register have no effect.

Offset:

71h-72h

Bit

Description

15:0

RESERVED 9

7.4.3.7.3

TRDCKS: Thermal Reference Data Checksum

This location provides the checksum of the Thermal Reference Data Section. Writes to

this register have no effect.

Offset:

73h

Bit

Description

7:0

Thermal Reference Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.3.8

Feature Data

This section provides information on key features that the platform may need to

understand without powering on the processor.

7.4.3.8.1

PCFF: Processor Core Feature Flags

This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID

instruction. These details provide instruction and feature support by product family. A

decode of these bits is found in the Cedar Mill Processor Family BIOS Writers Guide or

the AP-485 Intel^®Processor Identification and CPUID Instruction application note.

Writes to this register have no effect.

Offset:

74h-77h

Bit

Description

31:0

Processor Core Feature Flags

0000h-FFFFF: Feature Flags

7.4.3.8.2

PFF: Processor Feature Flags

This location contains additional feature information from the processor. Writes to this

register have no effect.

Note:

Bit 5 and Bit 6 are mutually exclusive (only one bit will be set).

Offset:

Bit

78h

Description

7

6

5

4

Multi-Core (set if the processor is a dual core processor)

Serial signature (set if there is a serial signature at offset 4D - 54h)

Electronic signature present (set if there is a electronic signature at 4D - 54h)

Thermal Sense Device present (set if an SMBus thermal sensor on package)

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

107

Features

Offset:

Bit

78h

Description

3

2

1

0

Reserved

OEM EEPROM present (set if there is a scratch ROM at offset 80 - FFh)

Core VID present (set if there is a VID provided by the processor)

L3 Cache present (set if there is a level 3 cache on the processor)

7.4.3.8.3

PTCI: Processor Thread and Core Information

This location contains information regarding the number of cores and threads on the

processor. Writes to this register have no effect.

Example: The Dual-Core Intel Xeon processor 7100 series has two cores and two

threads per core. Therefore, this register will have a value of 0Ah.

Offset:

Bit

79h

Description

7:4

3:2

1:0

Reserved

Number of cores

Number of threads per core

7.4.3.8.4

APFF: Additional Processor Feature Flags

This location contains additional feature information for the processor. This field is

defined as follows: Writes to this register have no effect.

Offset:

Bit

7Ah

Description

7

6

5

4

3

2

1

0

Reserved

®

Intel Cache Safe Technology

C1E State

®

Intel Virtualization Technology

Execute Disable

®

Intel 64

Thermal Monitor 2

®

Enhanced Intel Speed Step Technology

Bits are set when a feature is present, and cleared when they are not.

108

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

7.4.3.8.5

TAF: Thermal Adjustment Factors

This location contains information on thermal adjustment factors for the processor. This

field and it’s details are pending and will be updated in a future revision. Writes to this

register have no effect.

Offset:

Bit

7Bh-7Ch

Description

15:8

7:0

Measurement Correction Factor

Temperature Target

7.4.3.9

Other Data

7.4.3.9.1

RES10: Reserved 10

These locations are reserved. Writes to this register have no effect.

Offset:

7Dh-7Eh

Bit

Description

15:0

RESERVED

7.4.3.9.2

FDCKS: Feature Data Checksum

This location provides the checksum of the Feature Data Section. Writes to this register

have no effect.

Offset:

7Fh

Bit

Description

7:0

Feature Data Checksum

One Byte Checksum of the Header Section

00h- FFh: See Section 7.4.4 for calculation of the value

7.4.4

Checksums

The PIROM includes multiple checksums. Table 7-7 includes the checksum values for

each section defined in the 128 byte ROM.

Table 7-7.

128 Byte ROM Checksum Values

Section

Checksum Address

Header

0Dh

15h

24h

31h

37h

6Fh

73h

7Fh

Processor Data

Processor Core Data

Cache Data

Package Data

Part Number Data

Thermal Ref. Data

Feature Data

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

109

Features

Checksums are automatically calculated and programmed by Intel. The first step in

calculating the checksum is to add each byte from the field to the next subsequent

byte. This result is then negated to provide the checksum.

Example: For a byte string of AA445Ch, the resulting checksum will be B6h.

AA = 10101010

44 = 01000100

5C = 0101100

AA + 44 + 5C = 01001010

Negate the sum: 10110101 +1 = 101101 (B6h)

7.4.5

7.4.6

Scratch EEPROM

Also available in the memory component on the processor SMBus is an EEPROM which

may be used for other data at the system or processor vendor’s discretion. The data in

this EEPROM, once programmed, can be write-protected by asserting the active-high

SM_WP signal. This signal has a weak pull-down (10 kΩ) to allow the EEPROM to be

programmed in systems with no implementation of this signal. The Scratch EEPROM

resides in the upper half of the memory component (addresses 80 - FFh). The lower

half comprises the Processor Information ROM (addresses 00 - 7Fh), which is

permanently write-protected by Intel.

SMBus Thermal Sensor

The processor’s SMBus thermal sensor provides a means of acquiring thermal data

from the processor’s two thermal diodes. The thermal sensor is composed of control

logic, SMBus interface logic, a precision analog-to-digital converter, and a single bank

of precision current sources. The A/D converter and the current source are muxed

between the two sensor channels. The sensor drives a small current through the p-n

junction for the thermal diodes located on the processor core. The forward bias voltage

generated across each thermal diode is sensed and the precision A/D converter derives

a byte of thermal reference data, or a “thermal byte reading.” The resolution of the

least significant bit of a thermal byte is 1° Celsius.

The processor incorporates the SMBus thermal sensor onto the processor package.

Upper and lower thermal reference thresholds can be individually programmed for each

channel of the SMBus thermal sensor. Comparator circuits sample the register where

the single byte of thermal data (thermal byte reading) is stored. These circuits compare

the single-byte result against programmable threshold bytes. If enabled, the alert

signal on the processor SMBus (SM_ALERT#) will be asserted when the sensor detects

that either the high or low threshold is reached or crossed for each channel. Analysis of

SMBus thermal sensor data may be useful in detecting changes in the system

environment that may require attention.

The processor SMBus thermal sensor may be used to monitor long term temperature

trends, but can not be used to manage the short term temperature of the processor or

predict the activation of the thermal control circuit. As mentioned earlier, the

processor’s high thermal ramp rates make this infeasible. Refer to the thermal design

guidelines listed in Section 1.2 for more details.

The SMBus thermal sensor feature in the processor cannot be used to measure T_CASE

.

The T_CASEspecification in Section 6 must be met regardless of the reading of the

processor's thermal sensor in order to ensure adequate cooling for the entire processor.

The SMBus thermal sensor feature is only available while V_CCand SM_VCC are at valid

levels and the processor is not in a low-power state.

110

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

7.4.7

Thermal Sensor Supported SMBus Transactions

The thermal sensor responds to five of the SMBus packet types: Write Byte, Read Byte,

Send Byte, Receive Byte, and Alert Response Address (ARA). The Send Byte packet can

be used for sending one-shot commands. The Receive Byte packet accesses the

register commanded by the last Read Byte packet and can be used to continuously read

from a register. If a Receive Byte packet was preceded by a Write Byte or send Byte

packet more recently than a Read Byte packet, then the behavior is undefined.

Table 7-8 through Table 7-12 diagram the five packet types. In these figures, ‘S’

represents the SMBus start bit, ‘P’ represents a stop bit, ‘Ack’ represents an

acknowledge, and ‘///’ represents a negative acknowledge (NACK). The shaded bits are

transmitted by the thermal sensor, and the bits that aren’t shaded are transmitted by

the SMBus host controller.

Table 7-8.

Table 7-9.

Write Byte SMBus Packet

S

Slave Address

Write

Ack

Command Code

Ack

Data

Ack

P

1

7-bits

0

1

8-bits

1

8-bits

1

Read Byte SMBus Packet

/

Slave

Address

Command

Code

Slave

Address

S

Write

Ack

S

Read

Ack

Data

P

1

7-bits

0

1

8-bits

1

7-bits

1

8-

bits

1

Table 7-10. Send Byte SMBus Packet

S

Slave Address

Write

Ack

Command Code

Ack

P

1

7-bits

0

1

8-bits

1

Table 7-11. Receive Byte SMBus Packet

S

Slave Address

Read

Ack

Data

///

P

1

7-bits

1

8-bits

1

Table 7-12. ARA SMBus Packet

S

ARA

Read

Ack

Address

///

P

1

0001 100

1

Device Address¹

1

Note:

1.

This is an 8-bit field. The device which sent the alert will respond to the ARA Packet with its address in the

seven most significant bits. The least significant bit is undefined and may return as a ‘1’ or ‘0’. See

Section 7.4.1 for details on the Thermal Sensor Device addressing.

2.

The shaded bits are transmitted by the thermal sensor, and the bits that aren’t shaded are transmitted by

the SMBus host controller.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

111

Features

Table 7-13. SMBus Thermal Sensor Command Byte Bit Assignments

4

Register

Command

R/W

Lock

Reset State

2

RESERVED

00h

01h

N/A

R

N/A

N

RESERVED

0000 0000

Undefined

0000 0000

0000 0111

RESERVED

0101 0101

0000 0000

0000 0111

RESERVED

0101 0101

0000 0000

N/A

1

Ch. 1 Temp. Value

Status Register 1

02h

R

N

Configuration Register 1

Conversion Rate Register

03h

R

Y

04h

R

Y

2

RESERVED

05h - 06h

07h

N/A

R

N/A

Y

1,4

Ch. 1 Temp. High Limit

1,4

Ch. 1 Temp. Low Limit

08h

R

Y

Configuration Register

09h

W

Y

Conversion Rate Register

0Ah

W

Y

2

RESERVED

0Bh - 0Ch

0Dh

N/A

W

N/A

Y

1,4

Ch. 1 Temp. High Limit

1,4

Ch. 1 Temp. Low Limit

0Eh

W

Y

One-shot

0Fh

W

N/A

Y

2

RESERVED

10h

N/A

R/W

N/A

R

RESERVED

0000 0000

RESERVED

0000 0000

RESERVED

0000 0000

0101 0101

0000 0000

RESERVED

0100 0001

1001xxxx

1

Ch. 1 Temp. Offset

11h

2

RESERVED

12h - 22h

23h

N/A

N

Status Register 2

2

RESERVED

24h - 29h

30h

N/A

R

N/A

N

Ch. 2 Temp. Value

4

Ch. 2 Temp. High Limit

31h

R/W

R

Y

4

Ch. 2 Temp. Low Limit

32h

Y

2

RESERVED

33h

N/A

Y

Ch. 2 Temp. Offset

34h

R/W

N/A

R

2

RESERVED

35h - FDh

FEh

N/A

Manufacturer ID

3

Die Revision Code

FFh

R

Notes:

1.

2.

Bit 3 of Configuration register 1 must be set to 0 (default value is 0).

Writing to RESERVED bits may cause unexpected results. RESERVED bits that must be correctly

programmed are identified in the register definitions in the following section. Reading from RESERVED bits

will return unknown values.

3.

The 4 least significant bits of the thermal sensor die revision code may change and should not be used for

identification.

All of the commands in Table 7-13 are for reading or writing registers in the SMBus

thermal sensor, except the one-shot register (0Fh). The one-shot command forces the

immediate start of a new conversion cycle. If a conversion is in progress when the one-

shot command is received, then the command is ignored. If the thermal sensor is in

stand-by mode when the one-shot command is received, a conversion is performed

and the sensor returns to stand-by mode. The one-shot command is not supported

when the thermal sensor is in auto-convert mode.

Note:

Writing to a read-command register or reading from a write-command register will

produce invalid results.

112

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

The default command after reset is to a reserved value (00h). After reset, Receive Byte

SMBus packets will return invalid data until another command is sent to the thermal

sensor.

7.4.8

SMBus Thermal Sensor Registers

7.4.8.1

Thermal Value Registers

Once the SMBus thermal sensor reads a processor thermal diode, it performs an analog

to digital conversion and stores the data in a temperature value register. The supported

range is +127 to 0 decimal and is expressed as an eight-bit number representing

temperature in degrees Celsius. This eight-bit value consists of seven bits of data and a

sign bit (MSB) where the sign is always positive (sign = 0) and is shown in Table 7-14.

The values shown are also used to program the Thermal Limit Registers.

The values of these registers should be treated as saturating values. Values above 127

are represented at 127 decimal, and values of zero and below may be represented as 0

to -127 decimal. If the device returns a value where the sign bit is set (1) and the data

is 000_0000 through 111_1110, the temperature should be interpreted as 0° Celsius.

Table 7-14. Thermal Value Register Encoding

Temperature

(°C)

Register Value

(binary)

+127

+126

+100

+50

+25

+1

0 111 1111

0 111 1110

0 110 0100

0 011 0010

0 001 1001

0 000 0001

0 000 0000

0

7.4.8.2

7.4.8.3

Thermal Limit Registers

The SMBus thermal sensor has high and low Thermal Limit Registers for each channel.

These registers allow the user to define high and low limits for the processor core

thermal diode readings. The encoding for these registers is the same as for the thermal

reference registers shown in Table 7-14. If either processor thermal diode reading

equals or exceeds one of these limits, then the alarm bit (R1HIGH, R1LOW, R2HIGH, or

R2LOW) in the Thermal Sensor Status Register is triggered.

Status Registers

The Status Registers shown in Table 7-15 and Table 7-16 indicates which, if any,

thermal value thresholds for the processor core thermal diode have been exceeded. It

also indicates whether a conversion is in progress or an open circuit has been detected

in either processor core thermal diode connection. Once set, alarm bits stay set until

they are cleared by a Status Register read. A successful read to the Status Register will

clear any alarm bits that may have been set (unless the alarm condition persists). If

the SM_ALERT# signal is enabled via the Thermal Sensor Configuration Register and a

thermal diode threshold is exceeded, an alert will be sent to the platform via the

SM_ALERT# signal.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

113

Features

Table 7-15. SMBus Thermal Sensor Status Register 1

Bit

Name

Reset State

Function

7 (MSB)

BUSY

N/A

If set, indicates that the device’s analog to digital

converter is busy.

6

5

4

RESERVED

R1HIGH

RESERVED

0

Reserved for future use.

If set, indicates the processor core 1 thermal diode high

temperature alarm has activated.

3

2

R1LOW

0

If set, indicates the processor core 1 thermal diode low

temperature alarm has activated.

R1OPEN

If set, indicates an open fault in the connection to the

processor core 1 diode.

1

RESERVED

Reserved for future use.

0 (LSB)

Table 7-16. SMBus Thermal Sensor Status Register 2

Bit

Name

Reset State

Function

Reserved for future use.

7 (MSB)

RESERVED

R2HIGH

RESERVED

0

6

5

4

Reserved for future use.

If set, indicates the processor core 2 thermal diode high

temperature alarm has activated.

3

2

R2LOW

0

If set, indicates the processor core 2 thermal diode low

temperature alarm has activated.

R2OPEN

If set, indicates an open fault in the connection to the

processor core 2 diode.

1

RESERVED

ALERT

RESERVED

0

Reserved for future use.

0 (LSB)

If set, indicates the ALERT pin has been asserted low.

This bit gets reset when the ALERT output gets reset.

7.4.8.4

Configuration Register

The Configuration Register controls several functions of the temperature sensor such as

ALERT# masking, stand-by mode, and others. Table 7-17 and Table 7-18 shows the bit

definitions of the Configuration Registers.

Table 7-17. SMBus Thermal Sensor Configuration Register (Sheet 1 of 2)

Bit

Name

Reset State

Function

7 (MSB)

MASK

0

Mask SM_ALERT# bit. Clear the bit to allow interrupts

via SM_ALERT# and allow the thermal sensor to

respond to the ARA command when an alarm is active.

Set the bit to disable interrupt mode. The bit is not used

to clear the state of the SM_ALERT# output. An ARA

command may not be recognized if the mask is enabled.

6

5

RUN/STOP

AL/TH

0

Stand-by mode control bit. If set, the device

immediately stops converting and enters stand-by

mode. It will perform new temperature measurements

when a one-shot is performed. If cleared, the device

automatically updates on a timed basis.

This bit selects the function of pin 13. Default = 0 =

ALERT. Always set this bit to 0.

114

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Features

Table 7-17. SMBus Thermal Sensor Configuration Register (Sheet 2 of 2)

Bit

Name

Reset State

Function

Reserved for future use.

4

3

RESERVED

Remote 1/2

RESERVED

0

Setting this bit to 1 enables the user to read the

processor core 2 values from the processor core 1

registers. Default = 0 means Read processor core 1

values from the processor core 1 registers. Always set

this bit to 0.

2

1

0

Temp Range

Mask R1

0

Setting this bit to 1 enables the extended temperature

measurement range (-50 °C to +150 °C). Default = 0 =

(0 °C to 127 °C). Always set this bit to 0.

Setting this bit to 1 masks ALERTS due to the processor

core 1 temperature exceeding a programmed limit.

Default = 0. Always set this bit to 0.

Mask R2

Setting this bit to 1 masks ALERTS due to the processor

core 2 temperature exceeding a programmed limit.

Default = 0. Always set this bit to 0.

7.4.8.5

Conversion Rate Register

The contents of the Conversion Rate Registers determine the nominal rate at which

analog-to-digital conversions happen when the SMBus thermal sensor is in auto-

convert mode. There are two Conversion Rate Registers: address 04h for reading the

conversion rate value; and address 0Ah for writing the value. Table 7-18 shows the

mapping between Conversion Rate Register values and the conversion rate. As

indicated in Table 7-13, the Conversion Rate Register is set to its default state of 1000b

(16 Hz nominally) when the thermal sensor is powered up. There is a ±30% error

tolerance between the conversion rate indicated in the conversion rate register and the

actual conversion rate.

Table 7-18. SMBus Thermal Sensor Conversion Rate Register

Bit

Name

Reset State

Function

7 (MSB)

Averaging

0

Setting this bit to 1 disables averaging of the

temperature measurements at the slower conversion

rates. Default = 0 = Averaging enabled.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

115

Features

Table 7-18. SMBus Thermal Sensor Conversion Rate Register

Bit

Name

Reset State

Function

Reserved for future use.

6

RESERVED

00

5:4

Channel Selector

These bits are used to select the temperature

measurement channels.

00 = Round robin

01 = Local Temperature

10 = Processor Core 1 Temperature

11 = Processor Core 2 Temperature

Default = 00. Always set these bits to 00

3:0

Conversion Rates

1000

These bits determine how often the temperature sensor

measures each temperature channel.

Bit encoding = Conversions / sec

0000 = 0.0625

0001 = 0.125

0010 = 0.25

0011 = 0.5

0100 = 1

0101 = 2

0110 = 4

0111 = 8

1000 = 16 = default

1001 = 32

1010 = Continuous Measurements

7.4.9

SMBus Thermal Sensor Alert Interrupt

The SMBus thermal sensor located on the processor includes the ability to interrupt the

SMBus when a fault condition exists. The fault conditions consist of:

1. a processor thermal diode value measurement that exceeds a user-defined high or

low threshold programmed into the Command Register; or

2. disconnection of the processor thermal diode from the thermal sensor.

The interrupt can be enabled and disabled via the thermal sensor Configuration

Register and is delivered to the system board via the SM_ALERT# open drain output.

Once latched, the SM_ALERT# should only be cleared by reading the Alert Response

byte from the Alert Response Address of the thermal sensor. The Alert Response

Address is a special slave address shown in Table 7-12. The SM_ALERT# will be cleared

once the SMBus master device reads the slave ARA unless the fault condition persists.

Reading the Status Register or setting the mask bit within the Configuration Register

does not clear the interrupt.

§

116

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Boxed Processor Specifications

8 Boxed Processor Specifications

8.1

Introduction

Intel boxed processors are intended for system integrators who build systems from

components available through distribution channels. Future revisions may have

solutions that differ from those discussed here.

The thermal solution for the boxed Dual-Core Intel Xeon processor 7100 series, for

each processor frequency, includes an unattached passive heatsink. This solution is

targeted at chassis which are 3U and above in height.

This section documents baseboard and platform requirements for the thermal solution,

supplied with the boxed Dual-Core Intel Xeon processor 7100 series. This section is

particularly important to companies that design and manufacture baseboards, chassis

and complete systems. Figure 8-1 shows the conceptual drawing of the boxed

processor thermal solution.

Drawings in this section reflect only the specifications on the Intel boxed processor

product. These dimensions should not be used as a generic keep-out zone for all

cooling solutions. It is the system designer’s responsibility to consider their proprietary

cooling solution when designing to the required keep-out zone on their system platform

and chassis.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

117

Boxed Processor Specifications

Figure 8-1. Passive Dual-Core Intel® Xeon® Processor 7100 Series

Thermal Solution (3U and larger)

Note:

1.

2.

The heatsink in this image is for reference only.

This drawing shows the retention scheme for the boxed processor.

8.2

Mechanical Specifications

This section documents the mechanical specifications of the boxed processor passive

heatsink.

8.2.1

Boxed Processor Heatsink Dimensions

The boxed processor is shipped with an unattached passive heatsink. Clearance is

required around the heatsink to ensure unimpeded airflow for proper cooling. The

physical space requirements and dimensions for the boxed processor and assembled

heatsink are shown in the following figures.

118

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Boxed Processor Specifications

Figure 8-2. Top Side Board Keep-Out Zones (Part 1)

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

119

Boxed Processor Specifications

Figure 8-3. Top Side Board Keep-Out Zones (Part 2)

120

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Boxed Processor Specifications

Figure 8-4. Bottom Side Board Keep-Out Zones

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

121

Boxed Processor Specifications

Figure 8-5. Board Mounting-Hole Keep-Out Zones

122

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Boxed Processor Specifications

Figure 8-6. Thermal Solution Volumetric

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

123

Boxed Processor Specifications

Figure 8-7. Recommended Processor Layout and Pitch

124

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Boxed Processor Specifications

8.2.2

8.2.3

Boxed Processor Heatsink Weight

The boxed processor heatsink weight is approximately 530 grams. See Section 3 of this

document for details on the processor weight and the Dual-Core Intel® Xeon®

Processor 7100 Series Thermal/Mechanical Design Guidelines for the enabled heatsink

requirements.

Boxed Processor Retention Mechanism and Heatsink

Supports

Baseboards and chassis’s designed for use by system integrators should include holes

that are in proper alignment with each other to support the boxed processor. See

Figure 8-7 for example of processor pitch and layout.

Figure 8-1 illustrates the retention solution. This is designed to extend air-cooling

capability through the use of larger heatsinks with minimal airflow blockage and

minimal bypass. These retention mechanisms can allow the use of much heavier

heatsink masses compared to legacy solution limitations by using a load path attached

to the chassis pan. The CEK spring on the under side of the baseboard provides the

necessary compressive load for the thermal interface material. The baseboard is

intended to be isolated such that the dynamic loads from the heatsink are transferred

to the chassis pan via the heatsink screws and heatsink standoffs. This reduces the risk

of package pullout and solder joint failures in a shock and vibe situation.

The assembly requires larger diameter holes to compensate for the CEK spring

embosses. See Figure 8-2 and Figure 8-3 for processor mounting thru holes. For

further details on the solution, refer to the Dual-Core Intel® Xeon® Processor 7100

Series Thermal/Mechanical Design Guidelines.

8.3

Thermal Specifications

This section describes the cooling requirements of the heatsink solution utilized by the

boxed processor.

8.3.1

Boxed Processor Cooling Requirements

The boxed processor will be cooled by forcing ducted chassis fan airflow through the

passive heat sink solution. Meeting the processor’s temperature specifications is a

function of the thermal design of the entire system, and ultimately the responsibility of

the system integrator. The processor temperature specification is found in Section 6 of

this document. For the boxed processor passive heatsink to operate properly, chassis

air movement devices are required. Necessary airflow and associated flow impedance is

29 cfm at 0.14” H₂O.

In addition, the processor pitch should be 3.25 inches, or slightly more, when placed in

side by side orientation. Figure 8-7 illustrates the side by side orientation and pitch.

Note that the heatsinks are interleaved to reduce air bypass.

It is also recommended that the ambient air temperature outside of the chassis be kept

at or below 35 °C. The air passing directly over the processor heatsink should not be

preheated by other system components (such as another processor), and should be

kept at or below 40 °C. Again, meeting the processor’s temperature specification is the

responsibility of the system integrator.

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

125

Boxed Processor Specifications

8.3.2

Boxed Processor Contents

The boxed processor will include the following items:

• Dual-Core Intel Xeon processor 7100 series

• Unattached Passive Heatsink with captive screws

• Thermal Interface Material (pre-attached)

• Warranty / Installation manual with Intel Inside logo

The other items listed in Figure 8-1, required with this thermal solution should be

shipped with either the chassis or the mainboard. They include:

• CEK Spring (typically included with mainboard)

• Chassis Standoffs

• System fans

§

126

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

Debug Tools Specifications

9 Debug Tools Specifications

Please refer to the eXtended Debug Port: Debug Port Design Guide for MP Platforms,

and the appropriate platform design guide for more detailed information regarding

debug tools specifications.

9.1

Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces

(LAIs) for use in debugging Dual-Core Intel® Xeon® Processor 7100 Series processor

systems. Tektronix and Agilent should be contacted to get specific information about

their logic analyzer interfaces. The following information is general in nature. Specific

information must be obtained from the logic analyzer vendor.

Due to the complexity of Dual-Core Intel® Xeon® Processor 7100 Series processor-

based multiprocessor systems, the LAI is critical in providing the ability to probe and

capture front side bus signals. There are two sets of considerations to keep in mind

when designing a Dual-Core Intel® Xeon® Processor 7100 Series processor-based

system that can make use of an LAI: mechanical and electrical.

9.1.1

Mechanical Considerations

The LAI is installed between the processor socket and the processor. The LAI pins plug

into the socket, while the processor pins plug into a socket on the LAI. Cabling that is

part of the LAI egresses the system to allow an electrical connection between the

processor and a logic analyzer. The maximum volume occupied by the LAI, known as

the keepout volume, as well as the cable egress restrictions, should be obtained from

the logic analyzer vendor. System designers must make sure that the keepout volume

remains unobstructed inside the system. Note that it is possible that the keepout

volume reserved for the LAI may differ from the space normally occupied by the Dual-

Core Intel® Xeon® Processor 7100 Series processor heatsink. If this is the case, the

logic analyzer vendor will provide a cooling solution as part of the LAI.

9.1.2

Electrical Considerations

The LAI will also affect the electrical performance of the front side bus; therefore, it is

critical to obtain electrical load models from each of the logic analyzer vendors to be

able to run system level simulations to prove that their tool will work in the system.

Contact the logic analyzer vendor for electrical specifications and load models for the

LAI solution they provide.

§

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

127

Debug Tools Specifications

128

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet


型号：	LF80550KF0604M
厂家：	INTEL
描述：	Microprocessor, 64-Bit, 2500MHz, CMOS, CPGA604, 1.27 MM PITCH, FCMPGA-604 时钟外围集成电路
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