LW80603004728AA/SLC38 [INTEL]
RISC Microprocessor, 64-Bit, 1460MHz;
| 型号： | LW80603004728AA/SLC38 |
| 厂家： | 
INTEL |
| 描述： | RISC Microprocessor, 64-Bit, 1460MHz |
| 文件： | 总172页 (文件大小：2564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Intel Itanium Processor 9300
Series and 9500 Series
Intel® Itanium® Processor Quad-Core 1.86-1.73 GHz with 24 MB L3 Cache 9350
Intel® Itanium® Processor Quad-Core 1.73-1.60 GHz with 20 MB L3 Cache 9340
Intel® Itanium® Processor Quad-Core 1.60-1.46 GHz with 20 MB L3 Cache 9330
Intel® Itanium® Processor Quad-Core 1.46-1.33 GHz with 16 MB L3 Cache 9320
Intel® Itanium® Processor Dual-Core 1.60 GHz Fixed Frequency with 10 MB L3 Cache 9310
Intel® Itanium® Processor Eight-Core 2.53 GHz with 32 MB LLC Cache 9560
Intel® Itanium® Processor Four-Core 2.40 GHz with 32 MB LLC Cache 9550
Intel® Itanium® Processor Eight-Core 2.13 GHz with 24 MB LLC Cache 9540
Intel® Itanium® Processor Four-Core 1.73 GHz with 20 MB LLC Cache 9520
Datasheet
November 2012
Reference Number: 322821-002
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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm%20
2
2
I C is a two-wire communication bus /protocol developed by Phillips. SMBus is a subset of the I C bus/protocol developed by Intel.
2
Implementation of the I C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips
Electronics, N.V. and North American Phillips Corporation.
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible
with all operating systems. Please check with your application vendor.
Intel, Itanium, and the Intel logo are trademarks of Intel Corporation in the U. S. and\or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2012, Intel Corporation. All Rights Reserved.
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Contents
1
Introduction..............................................................................................................9
1.1
1.2
Overview ...........................................................................................................9
Architectural Overview....................................................................................... 15
1.2.1 Intel® Itanium® Processor 9300 Series Overview ....................................... 15
1.2.2 Intel® Itanium® Processor 9500 Series Overview ....................................... 16
Processor Feature Comparison ............................................................................ 19
Processor Abstraction Layer................................................................................ 20
Mixing Processors of Different Frequencies and Cache Sizes .................................... 20
Terminology ..................................................................................................... 20
State of Data.................................................................................................... 21
Reference Documents........................................................................................ 21
1.3
1.4
1.5
1.6
1.7
1.8
2
Electrical Specifications........................................................................................... 23
2.1
Intel® QuickPath Interconnect and Intel® Scalable Memory Interconnect
Differential Signaling ......................................................................................... 23
Signal Groups................................................................................................... 24
Reference Clocking Specifications ........................................................................ 26
Intel® QuickPath Interconnect and Intel® SMI Signaling Specifications..................... 28
2.4.1 Intel® Itanium® Processor 9300 Series
2.2
2.3
2.4
Intel® QuickPath Interconnect and
Intel® SMI Specifications for 4.8 GT/s....................................................... 28
2.4.2 Intel® Itanium® Processor 9500 Series Requirements for
Intel® QuickPath Interconnect for 4.8 and 6.4 GT/s .................................... 32
2.4.3 Intel® Itanium® Processor 9500 Series Processor Requirements for
Intel® SMI Specifications for 6.4 GT/s....................................................... 37
Processor Absolute Maximum Ratings................................................................... 38
2.5.1 Intel® Itanium® Processor 9300 Series Absolute Maximum Ratings............... 39
2.5.2 Intel® Itanium® Processor 9500 Series Absolute Maximum Ratings............... 39
Processor DC Specifications ................................................................................ 39
2.6.1 Flexible Motherboard Guidelines for the Intel® Itanium®
2.5
2.6
Processor 9300 Series............................................................................. 40
2.6.2 Flexible Motherboard Guidelines for the Intel® Itanium®
Processor 9500 Series............................................................................. 43
2.6.3 Intel® Itanium® Processor 9300 Series Uncore, Core, and Cache Tolerances.. 44
2.6.4 Intel® Itanium® Processor 9500 Series Uncore and Core Tolerances ............. 49
2.6.5 Overshoot and Undershoot Guidelines....................................................... 52
2.6.6 Signal DC Specifications.......................................................................... 53
2.6.7 Motherboard-Socket Specification for VR Sense Point .................................. 57
Core and Uncore Voltage Identification................................................................. 57
2.7.1 Core and Uncore Voltage Identification for the
2.7
Intel® Itanium® Processor 9300 Series.................................................... 58
2.7.2 Core and Uncore Voltage Identification for the
Intel® Itanium® Processor 9500 Series ..................................................... 59
Cache Voltage Identification (Intel® Itanium® Processor 9300 Series only) ............... 62
RSVD, Unused, and DEBUG Pins.......................................................................... 63
2.8
2.9
2.10 Mixing Processors.............................................................................................. 64
2.11 Supported Power-up Voltage Sequence ................................................................ 64
2.11.1 Supported Power-up Voltage Sequence for the
Intel® Itanium® Processor 9300 Series.................................................... 66
2.11.2 Supported Power-up Voltage Sequence for the
Intel® Itanium® Processor 9500 Series ..................................................... 67
2.11.3 Power-up Voltage Sequence Timing Requirements ...................................... 68
2.12 Supported Power-down Voltage Sequence ............................................................ 68
2.13 Timing Relationship Between RESET_N and SKTID................................................. 69
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
3
2.14 Test Access Port (TAP) Connection .......................................................................71
3
4
5
Pin Listing................................................................................................................73
3.1
Processor Package Bottom Pin Assignments...........................................................73
3.1.1 Package Bottom Pin Listing by Pin Name....................................................73
3.1.2 Pin Listing by Pin Number ........................................................................89
Processor Package Top Pin Assignments..............................................................105
3.2.1 Top-Side J1 Connector Two-Dimensional Table .........................................105
3.2.2 Top-Side J2 Connector Two-Dimensional Table .........................................108
3.2.3 Top-Side J3 Connector Two-Dimensional Table .........................................111
3.2.4 Top-Side J4 Connector Two-Dimensional Table .........................................114
3.2
Mechanical Specifications ......................................................................................119
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Package Mechanical Drawing.............................................................................120
Intel® Itanium® Processor 9300 Series...............................................................121
Processor Component Keepout Zones.................................................................129
Package Loading Specifications..........................................................................129
Package Handling Guidelines.............................................................................129
Processor Mass Specifications............................................................................130
Processor Materials ..........................................................................................130
Package Markings............................................................................................130
Thermal Specifications...........................................................................................133
5.1
Thermal Features.............................................................................................133
5.1.1 Digital Thermometer .............................................................................134
5.1.2 Thermal Management............................................................................135
5.1.3 Thermal Alert.......................................................................................136
5.1.4 TCONTROL...........................................................................................137
5.1.5 Thermal Warning..................................................................................137
5.1.6 Thermal Trip ........................................................................................137
5.1.7 PROCHOT ............................................................................................138
5.1.8 FORCEPR_N Signal Pin...........................................................................138
5.1.9 Ararat Voltage Regulator Thermal Signals ................................................138
Package Thermal Specifications and Considerations..............................................139
Storage Conditions Specifications.......................................................................140
5.2
5.3
6
System Management Bus Interface........................................................................143
6.1
6.2
Introduction....................................................................................................143
SMBus Memory Component...............................................................................144
6.2.1 Processor Information ROM (PIROM) .......................................................144
6.2.2 Scratch EEPROM...................................................................................149
6.2.3 PIROM and Scratch EEPROM Supported SMBus Transactions.......................150
Memory Component Addressing.........................................................................150
PIROM Field Definitions.....................................................................................152
6.4.1 General...............................................................................................152
6.4.2 Processor Data.....................................................................................152
6.4.3 Processor Core Data..............................................................................152
6.4.4 Processor Uncore Data ..........................................................................153
6.4.5 Cache Data..........................................................................................154
6.4.6 Package Data.......................................................................................155
6.4.7 Part Number Data.................................................................................155
6.4.8 Thermal Reference Data ........................................................................155
6.4.9 Feature Data........................................................................................156
6.4.10 Other Data ..........................................................................................157
6.4.11 Checksums ..........................................................................................157
6.3
6.4
7
Signal Definitions...................................................................................................159
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Figures
1-1
Intel® Itanium® Processor 9300 Series Processor Block Diagram............................. 16
Intel® Itanium® Processor 9500 Series Processor Block Diagram............................. 17
Intel® Itanium® Processor 9500 Series Firmware Diagram...................................... 18
Active ODT for a Differential Link Example............................................................ 23
Single-ended Maximum and Minimum Levels and Vcross Levels............................... 27
Vcross-delta Definition....................................................................................... 27
Differential Edge Rate Definition.......................................................................... 28
VRB and TStable Definitions................................................................................ 28
TX Equalization Diagram .................................................................................... 31
TX Return Loss ................................................................................................. 32
RX Return Loss ................................................................................................. 32
Processor ICC_CORE Load Current versus Time........................................................ 42
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10 VCCUNCORE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series ................................................................ 45
2-11 VCCCORE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series ................................................................ 47
2-12 VCCCACHE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series ................................................................ 48
2-13 VCCUNCORE Static and Transient Tolerance for the
Intel® Itanium® Processor 9500 Series ................................................................ 50
2-14 VCCUNCORE Load Line for the Intel® Itanium® Processor 9500 Series ..................... 50
2-15 VCCCORE Load Line for the Intel® Itanium® Processor 9500 Series ......................... 51
2-16 VR Sense Point (Representation)......................................................................... 57
2-17 Supported Power-up Voltage Sequence Timing Requirements for the
Intel® Itanium® Processor 9300 Series............................................................... 66
2-18 Supported Power-up Sequence Timing Requirements for
Intel® Itanium® Processor 9500 Series............................................................... 67
2-19 Supported Power-down Voltage Sequence Timing Requirements.............................. 69
2-20 RESET_N and SKITID Timing for Warm and Cold Resets ......................................... 70
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
Processor Package Assembly Sketch .................................................................. 119
Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 1 of 4)................. 121
Intel® Itanium® Processor 9300 Series Processor Package Drawing (Sheet 2 of 4)... 122
Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 3 of 4)................. 123
Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 4 of 4)................. 124
Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 1 of 4)................ 125
Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 2 of 4)................. 126
Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 3 of 4)................. 127
Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 4 of 4)................. 128
4-10 Processor Marking Zones.................................................................................. 131
5-1
5-2
6-1
Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series’ Thermal States ....................................... 134
Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series Package Thermocouple Location................. 140
Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series Package................................................. 151
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
5
Tables
1-1
Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series Feature Comparison....................................19
Signals with RTT................................................................................................24
Signal Groups ...................................................................................................24
Intel® QuickPath Interconnect/Intel® Scalable Memory
2-1
2-2
2-3
‘Interconnect Reference Clock Specifications26
2-4
2-5
Intel® Itanium® Processor 9300 Series Clock Frequency Table.................................29
Intel® Itanium® Processor 9300 Series Transmitter Parameter Values for Intel®
QuickPath Interconnect and Intel SMI Channels @ 4.8 GT/s ....................................29
Intel® Itanium® Processor 9300 Series Receiver Parameter
2-6
Values for Intel® QuickPath Interconnect and Intel® SMI Channels @ 4.8 GT.............30
Intel® Itanium® Processor 9500 Series Clock Frequency Table.................................33
Intel® Itanium® Processor 9500 Series Link Speed Independent Specifications ..........33
Intel® Itanium® Processor 9500 Series Transmitter and
2-7
2-8
2-9
Receiver Parameter Values for Intel® QPI Channel at 4.8 GT/s.................................34
2-10 Intel® Itanium® Processor 9500 Series Transmitter and
Receiver Parameter Values for Intel® QPI at 6.4 GT/s.............................................35
2-11 Intel® Itanium® Processor 9500 Series Transmitter and
Receiver Parameter Values for Intel® SMI at 6.4 GT/s and lower..............................37
2-12 PLL Specification for TX and RX ...........................................................................38
2-13 Intel® Itanium® Processor 9300 Series Absolute Maximum Ratings..........................39
2-14 Intel® Itanium® Processor 9500 Series Processor Absolute Maximum Ratings............39
2-15 FMB Voltage Specifications for the Intel® Itanium® Processor 9300 Series ................40
2-16 FMB 130W Current Specifications for the Intel® Itanium® Processor 9300 Series .......41
2-17 FMB 155W/185W Current Specifications for the
Intel® Itanium® Processor 9300 Series.................................................................42
2-18 FMB Voltage Specifications for the Intel® Itanium® Processor 9500 Series ................43
2-19 FMB 170W and 130W Current Specifications for the
Intel® Itanium® Processor 9500 Series.................................................................44
2-20 VCCUNCORE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series.................................................................45
2-21 VCCCORE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series.................................................................46
2-22 VCCCACHE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series.................................................................48
2-23 VCCUNCORE Static and Transient Tolerance for the
Intel® Itanium® Processor 9500 Series.................................................................49
2-24 VCCCORE Static and Transient Tolerance for the
Intel® Itanium® Processor 9500 Series.................................................................51
2-25 Overshoot and Undershoot Specifications For Differential
Intel® QuickPath Interconnect and Intel® SMI and Single-Ended Signals
for the Intel® Itanium® Processor 9300 Series ......................................................52
2-26 Overshoot and Undershoot Specifications For Differential
Intel® QuickPath Interconnect and Intel® SMI and Single-Ended
Signals for the Intel® Itanium® Processor 9500 Series ...........................................53
2-27 Voltage Regulator Signal Group DC Specifications ..................................................53
2-28 Voltage Regulator Control Group DC Specification ..................................................54
2-29 TAP and System Management Group DC Specifications ...........................................54
2-30 Error, FLASHROM, Power-Up, Setup, and Thermal Group DC Specifications................54
2-31 VID_VCCCORE[6:0], VID_VCCUNCORE[6:0] and VID_VCCCACHE[5:0] DC
Specifications for the Intel® Itanium® Processor 9300 Series...................................55
2-32 SVID Group DC Specifications for the Intel® Itanium® Processor 9500 Series ............55
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
2-33 SMBus and Serial Presence Detect (SPD) Bus Signal Group DC Specifications ............ 55
2-34 Debug Signal Group DC Specifications.................................................................. 56
2-35 PIROM Signal Group DC Specifications ................................................................. 56
2-36 Intel® Itanium® Processor 9300 Series VCCCORE (VID_VCCCORE) and
VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for Ararat........ 58
2-37 Intel® Itanium® Processor 9500 Series VCCCORE (VID_VCCCORE)
and VCCUNCORE and (VID_VCCUNCORE) Voltage Identification
Definition for Ararat II ....................................................................................... 59
2-38 Cache (VID_VCCCACHE) Voltage Identification Definition for Ararat ......................... 63
2-39 Power-up Voltage Sequence Timing Requirements ................................................. 68
2-40 RESET_N and SKTID Timing ............................................................................... 70
3-1
3-2
3-3
Pin List by Pin Name.......................................................................................... 73
Pin List by Pin Number....................................................................................... 89
Top-Side J1 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9300 Series)............................................................ 105
Top-Side J1 Connector Two-Dimensional Table
3-4
3-5
3-6
3-7
3-8
3-9
(Intel® Itanium® Processor 9500 Series)............................................................ 106
Top-Side J2 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9300 Series)............................................................ 108
Top-Side J2 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9500 Series)............................................................ 110
Top-Side J3 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9300 Series)............................................................ 111
Top-Side J3 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9500 Series)............................................................ 113
Top-Side J4 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9300 Series)............................................................ 114
3-10 Top-Side J4 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9500 Series)............................................................ 116
4-1
4-2
4-3
4-4
4-5
5-1
Processor Loading Specifications ....................................................................... 129
Package Handling Guidelines............................................................................. 129
Processor Package Insertion Specification........................................................... 130
Package Materials............................................................................................ 130
1248 FCLGA Package Marking Zones.................................................................. 130
Thermal Sensor Accuracy Distribution for the
Intel® Itanium® Processor 9300 Series .............................................................. 134
Thermal Sensor Accuracy Distribution for the
5-2
Intel® Itanium® Processor 9500 Series............................................................. 135
Thermal Specification for the Intel® Itanium® Processor 9300 Series ..................... 139
Thermal Specification for the Intel® Itanium® Processor 9500 Series Processor....... 139
Storage Condition Ratings ................................................................................ 141
Processor Information ROM Data....................................................................... 144
Read Byte SMBus Packet.................................................................................. 150
Write Byte SMBus Packet ................................................................................. 150
Offset 78h/79h Definitions................................................................................ 156
128 Byte PIROM Checksum Values .................................................................... 157
Signal Definitions for the Intel® Itanium® Processor 9300
5-3
5-4
5-5
6-1
6-2
6-3
6-4
6-5
7-1
Series and Intel® Itanium® 9500 Series............................................................. 159
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
7
Revision History
Document
Number
Revision
Number
Description
Date
322821
322821
-002
-001
•
•
Initial release of the 9300/9500 document.
Initial release of the document.
November 2012
February 2010
§
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Introduction
1
Introduction
1.1
Overview
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
employ Explicitly Parallel Instruction Computing (EPIC) design concepts for a tighter
coupling between hardware and software. In this design style, the interface between
hardware and software is designed to enable the software to exploit all available
compile-time information, and efficiently deliver this information to the hardware. It
addresses several fundamental performance bottlenecks in modern computers, such as
memory latency, memory address disambiguation, and control flow dependencies. The
EPIC constructs provide powerful architectural semantics, and enable the software to
make global optimizations across a large scheduling scope, thereby exposing available
Instruction Level Parallelism (ILP) to the hardware. The hardware takes advantage of
this enhanced ILP, and provides abundant execution resources. Additionally, it focuses
on dynamic run-time optimizations to enable the compiled code schedule to flow at
high throughput. This strategy increases the synergy between hardware and software,
and leads to greater overall performance.
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
system interface, with its 4 full width and 2 half width Intel® QuickPath Interconnects,
enables each processor to directly connect to other system components, thus can be
used as an effective building block for very large systems. The balanced core and
memory subsystem provide high performance for a wide range of applications ranging
from commercial workloads to high performance technical computing.
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
are pin compatible and support a range of computing needs and configurations from a
2-way to large SMP servers (although OEM field upgrade methodologies vary). This
document provides the electrical, mechanical and thermal specifications that must be
met when using the Intel® Itanium® Processor 9300 Series and Intel® Itanium®
Processor 9500 Series in your systems.
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
9
Introduction
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10
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Introduction
®
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Intel Itanium Processor 9300 Series
Intel® Itanium® Processor Quad-Core 1.86-1.73 GHz with 24 MB L3 Cache 9350
Intel® Itanium® Processor Quad-Core 1.73-1.60 GHz with 20 MB L3 Cache 9340
Intel® Itanium® Processor Quad-Core 1.60-1.46 GHz with 20 MB L3 Cache 9330
Intel® Itanium® Processor Quad-Core 1.46-1.33 GHz with 16 MB L3 Cache 9320
Intel® Itanium® Processor Dual-Core 1.60 GHz Fixed Frequency with 10 MB L3 Cache 9310
Product Features
Quad Core
On-die Memory Controller
— Four complete 64-bit processing cores on one
— Each memory controller supports two Intel®
Scalable Memory Interconnects.
— Support for one Scalable Memory Buffer per Intel
Scalable Memory Interconnect; four Scalable
Memory Buffers per processor.
processor.
— Includes Dynamic Domain Partitioning.
Advanced EPIC (Explicitly Parallel Instruction
Computing) Architecture for current and future
requirements of high-end enterprise and technical
workloads.
— High memory bandwidth, thus improved
performance.
— 4.8 GT/s for the Intel® 7500 Scalable Memory
Buffer.
— Provide a variety of advanced implementations of
parallelism, predication, and speculation,
resulting in superior Instruction-Level Parallelism
(ILP).
Intel® Virtualization Technology for virtualization for
data-intensive applications.
Intel® Hyper-Threading Technology
— Reduce virtualization complexity.
— Improve virtualization performance.
— Increase operating system compatibility.
— Two times the number of OS threads per core.
Wide, parallel hardware based on Intel® Itanium®
Intel® Cache Safe Technology ensures mainframe-
architecture for high performance:
caliber availability.
— Integrated on-die L3 cache of up to 24 MB; cache
hints for L1, L2, and L3 caches for reduced
memory latency.
— Minimize L3 cache errors.
— Disable cache entries that have become hard
errors.
— 128 general and 128 floating-point registers
— Improve availability.
supporting register rotation.
High bandwidth Intel® QuickPath Interconnect for
— Register stack engine for effective management
of processor resources.
multiprocessor scalability:
— Support for predication and speculation.
— 4 full and 2 half width Intel QPI Links
— 4.8GT/s transfer rate.
Extensive RAS features for business-critical
applications, for example:
— Systems are easily scaled without sacrificing
performance.
— Machine check architecture with extensive ECC
and parity protection.
Features to support flexible platform environments:
— IA-32 Execution Layer supports IA-32 application
binaries.
— On-chip thermal management.
— Built-in processor information ROM (PIROM).
— Built-in programmable EEPROM.
— Hot-Plug Socket
— Bi-endian support.
— Processor abstraction layer eliminates processor
— Hot-add and hot removal.
dependencies.
— Double Device Data Correction (DDDC) for x4
DRAMs, plus correction of a single bit error.
— Single Device Data Correction (SDDC) for x8
DRAMs, plus correction of a single bit error.
— Intel® QuickPath Interconnect Dynamic Link
Width Reduction.
— Intel® QuickPath Interconnect Clock Fail-Safe
Feature.
— Intel QuickPath Interconnect (Intel® QPI) Hot-
Add and Removal.
— DIMM Sparing, Memory Scrubbing, Memory
Mirroring, and Memory Migration.
— Architected firmware stack, including PAL and
SAL support.
— Directory-based and source-based coherency
protocol.
— Intel QPI poisoning, viral containment and
cleanup.
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
11
Introduction
The Intel® Itanium® Processor 9300 Series delivers new levels of flexibility, reliability,
performance, and cost-effective scalability for your most data-intensive business and
technical applications. It provides 24 megabytes L3 cache accessed at core speed,
Hyper-Threading Technology for increased performance, Intel® Virtualization
Technology for improved virtualization, Intel® Cache Safe Technology for increased
availability.
The Intel® Itanium® Processor 9300 Series consists of up to 4 core processors and a
system interface unit. Each processor core provides a 6-wide, 8-stage deep execution
pipeline. The resources consist of six integer units, six multimedia units, two load and
two store units, three branch units and two floating-point units each capable of
extended, double and single precision arithmetic. The hardware employs dynamic
prefetch, branch prediction, a register scoreboard, and non-blocking caches to optimize
for compile-time non-determinism. Each core provides duplication of all architectural
state to support hardware multithreading, thus enabling greater throughput. Three
levels of on-die cache minimize overall memory latency. It interfaces with the Ararat
“1” Voltage Regulator Module, which used exclusively with the Intel® Itanium®
Processor 9300 Series.
®
®
12
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Introduction
®
®
Intel Itanium Processor 9500 Series
Intel® Itanium® Processor Eight-Core 2.53 GHz with 32 MB LLC Cache 9560
Intel® Itanium® Processor Four-Core 2.40 GHz with 32 MB LLC Cache 9550
Intel® Itanium® Processor Eight-Core 2.13 GHz with 24 MB LLC Cache 9540
Intel® Itanium® Processor Four-Core 1.73 GHz with 20 MB LLC Cache 9520
Product Features
Eight Core
— Intel® Turbo Boost Technology, featuring
sustained boost.
— Eight complete 64-bit processing cores on one
processor, with two threads per core.
— Each core provides in-order issue and execution
of up to twelve instructions per cycle.
— Includes dynamic domain partitioning and static
hard partitioning.
— Architected firmware stack, including PAL and
SAL support.
— Directory-based and source-based coherency
protocol.
— Intel QPI poisoning, viral containment and
cleanup.
Advanced EPIC (Explicitly Parallel Instruction
Computing) Architecture for current and future
requirements of high-end enterprise and technical
workloads.
Two On-die Memory Controllers
— Each memory controller supports two Intel®
Scalable Memory Interconnects that operate in
lockstep.
— Provide a variety of advanced implementations of
parallelism, predication, and speculation,
resulting in superior Instruction-Level Parallelism
(ILP).
— Support for one Scalable Memory Buffer per Intel
Scalable Memory Interconnect; four Scalable
Memory Buffers per processor.
— High memory bandwidth, thus improved
performance.
Intel® Hyper-Threading Technology
— Dual Domain Multithreading with independent
front end and back end thread domains providing
hardware support for 2 threads per core.
— Support for Intel® Itanium® Processor New-
Instructions.
— 4.8 GT/s for the Intel® 7500 Scalable Memory
Buffer.
— 6.4 GT/s for the Intel® 7510 Scalable Memory
Buffer.
Intel® Instruction Replay Technology to replay core
Wide, parallel hardware based on Intel® Itanium®
pipeline for pipeline management and core RAS.
architecture for high performance:
Intel® Virtualization Technology (Intel® VT) for
Intel® 64 or Itanium ®architecture (Intel ® Vt-i) 3 -
Virtualization Support Extensions for Intel®
Virtualization Technology.
— Integrated on-die LLC cache of up to 32MB;
cache hints for FLC, MLC, and LLC caches for
reduced memory latency.
— 160 general and 128 floating-point registers
supporting register rotation.
— Reduce virtualization complexity.
— Improve virtualization performance via hardware
optimization.
— Register stack engine for effective management
of processor resources.
— Support for predication and speculation.
— Increase operating system compatibility.
Intel® Cache Safe Technology ensure mainframe-
Extensive RAS features for business-critical
applications, for example:
caliber availability.
— Machine check architecture with extensive ECC
and parity protection with firmware first error
handling.
— Minimize LLC cache errors.
— Disable cache entries that have become hard
errors.
— Directory Cache covers 33% more cache lines.
— Improve availability.
— End-to-end error detection.
— On-chip thermal management and power
management.
High bandwidth Intel® QuickPath Interconnect for
— Built-in processor information ROM (PIROM).
— Built-in programmable EEPROM.
— Hot Plug Socket.
multiprocessor scalability:
— 4 full and 2 half width Intel QPI Links
— 6.4GT/s transfer rate with aggregate data
bandwidth of 28.8 GB/s.
— Hot-add and hot removal support.
— Double Device Data Correction (DDDC) for x4
DRAMs, plus correction support of a single bit
error.
— Systems are easily scaled without sacrificing
performance.
— Single Device Data Correction (SDDC) for x8 and Features to support flexible platform environments:
x4 DRAMs, plus correction of a single bit error.
— Intel® QuickPath Interconnect Dynamic Link
Width Reduction.
— Fully compatible with binaries for the Intel
Itanium processor family with Instruction level
advancements.
— Intel® QuickPath Interconnect Clock Fail-Safe
Feature.
— LGA1248 Socket Level compatible with the Intel®
Itanium® Processor 9300 Series.
— Bi-endian support.
— Intel® QuickPath Interconnect Hot-Add and
Removal.
— Processor abstraction layer eliminates processor
— Memory DIMM and Rank Sparing, Memory
Scrubbing, Memory Mirroring, and Memory
Migration.
dependencies.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
13
Introduction
The Intel® Itanium® Processor 9500 Series delivers increased levels of flexibility,
reliability, performance, and cost-effective scalability for your most data-intensive
business and technical applications.
The Intel® Itanium® Processor 9500 Series processor provides up to 32 megabytes LLC
cache, Hyper-Threading Technology for increased performance, Intel® Virtualization
Technology for improved virtualization, Intel® Cache Safe Technology for increased
availability. Intel® Turbo Boost Technology, featuring sustained boost. The Intel®
Itanium® Processor 9500 Series employs advanced power monitoring and control to
deliver a higher processor frequency at all times, for maximum performance on all
workloads. The result is a higher thermal envelope utilization for more overall
performance. The Intel® Itanium® Processor 9500 Series offers large cache arrays
covered by ECC including the large LLC utilizing double correct/triple detect (DECTED)
and protecting the MLI/MLD with in-line single correct/double detect (SECDED). In
addition, the processor provides extensive parity protection and parity interleaving on
nearly all RFs, end-to-end parity protection with recovery-support on all critical internal
buses and data paths including the ring. Residue protection on Floating Point unit,
along with the adoption of radiation-hardened (RAD) sequential latching elements for
vulnerable architectural and state. The Intel® Itanium® Processor 9500 Series
processor interfaces exclusively with the Ararat II Voltage Regulator Module.
The Intel® Itanium® Processor 9500 Series consists of up to 8 core processors and a
system interface unit. Each processor core provides a 12-wide, 11-stage deep
execution pipeline. The resources consist of six integer units, one integer multiply unit,
four multimedia units, two load/store units, three branch units and two floating-point
units each capable of extended, double and single precision arithmetic. The hardware
employs dynamic prefetch, branch prediction, a register scoreboard, and non-blocking
caches to optimize for compile-time non-determinism. 32 additional stacked general
registers are provided over the Intel® Itanium® Processor 9300 Series, and hardware
support is provided for denormal, unnormal, and pseudo-normal operands for floating
point software assist offloading.
New instructions on the Intel® Itanium® Processor 9500 Series simplify common tasks.
They include: clz (count leading zeros), mpy4 and mpyshl4(unsigned integer multiply/
shift and multiply), mov-to-DAHR/mv-from-DAHR (for improved MLD/FLD prefetcher
hinting and performance), and hint@priority (used by the processor to temporarily
allocate more resources to a thread). Advanced Explicitly Parallel Instruction
Computing (EPIC) is enhanced on the Intel® Itanium® Processor 9500 Series by
increasing the capacity of retiring instructions per cycle from 6 to a maximum of 12
instructions per cycle per core.
Intel® Hyper-threading Technology is enhanced in the Intel® Itanium® Processor 9500
Series with dual domain multithreading, which enables independent front-end and
back-end pipeline execution to improve multi-thread efficiency and performance for
both new and legacy applications. It provides hardware support for two threads per
core, with a threaded 96 entry per thread Instruction Buffer and threaded MLDTLB and
FLDTLB, and a dedicated load return path from the MLD to the integer register file.
Three levels of on-die cache minimize overall memory latency, with 16 KB instruction
cache FLI/16 KB write-through data cache FLD that comprise the FLC and 512 KB MLI/
256 KB writeback data cache MLD that comprise the MLC.
The Intel® Itanium® Processor 9500 Series offers a new RAS feature: Intel®
Instruction Replay Technology. Pipeline replay resolves stall conditions that occur when
the microprocessor pipeline encounters a resource hazard that prevents immediate
execution. In a replay, the instruction that encountered the resource hazard is removed
from the pipeline, along with all the instructions that come after it. The instruction is
then read again out of the instruction buffer for replay and re-executed. To ensure a
®
®
14
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Introduction
replay can be initiated for any instruction in the pipeline that encounters a resource
hazard, a copy of each instruction is maintained in the instruction buffer until the
instruction has successfully traversed the pipeline and is no longer needed. If
necessary, an instruction can replay multiple times. As a result, Intel® Instruction
Replay Technology automatically detects and many corrects soft errors in the
instruction pipeline. With this technology, soft errors can be identified and corrected in
as few as seven clock cycles, which is fast enough to be invisible to the software
running on the platform.
1.2
Architectural Overview
The sections below give an overview of the Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series.
®
®
1.2.1
Intel Itanium Processor 9300 Series Overview
The Intel® Itanium® Processor 9300 Series processor is a quad-core architecture. It
supports up to four processor cores, each with its own L3, L2, and L1 level cache. Also
supported are the following page sizes for purges or inserts: 4K, 8K, 16K, 64K, 256K,
1M, 4M, 16M, 64M, 256M, 1G, 4G.
The architecture interfacing the cores to the system is referred to as the System
Interface. Each processor core has it own Caching Agent (CPE). The CPE interfaces
between the processor core and the Intel QuickPath Interconnect. The Intel® Itanium®
Processor 9300 Series processor has two Home Agents (Bbox). The Bbox interfaces
between the memory controller and the Intel® QuickPath Interconnect and supports a
directory cache. Each Bbox interfaces with a memory controllers (Zbox). Each memory
controller supports two Intel SMI in lockstep. The Intel SMI are the interconnects to
Intel® 7500 Scalable Memory Buffer. The processor supports six Intel QuickPath
Interconnects at the socket, four full width and two half width. The Caching Agent,
Home Agent, and Intel QuickPath Interconnects are connected via a 12-port Crossbar
Router, each port supporting the Intel QuickPath Interconnect protocol. Figure 1-1
shows the Intel® Itanium® Processor 9300 Series block diagram.
The Intel QPI viral and poison fields are used to flag corrupted system state and bad
data accordingly. Once it has “gone viral”, an Intel QPI agent will set the viral field
within all packet headers. Viral mode is entered in three ways: receiving a viral packet,
upon a detecting fatal/panic error, or when a global viral signal (from Cboxes) is
asserted. Viral is cleared on Reset. Poisoning is used to indicate bad data on a per-flit
basis. Poison does not indicate corrupted system coherency, but rather that a particular
block of data is not reliable.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
15
Introduction
Figure 1-1. Intel® Itanium® Processor 9300 Series Processor Block Diagram
Core0
CPE0
Core1
CPE1
Core2
CPE2
Core3
CPE3
8
7
3
2
Intel® SMI
Intel® SMI
Intel® SMI
Intel® SMI
Pbox
PZ1
Pbox
PZ0
0xA
1
0
Zbox0 Bbox0
Rbox
Bbox1 Zbox1
6
9
5
4
0xB
Pbox
PH4
Pbox
PR 0
Pbox
PR1
Pbox
PR 2
Pbox
PR 3
Pbox
PH5
Intel®
QPI
Intel®
QPI
Intel®
QPI
Intel®
QPI
Intel®
QPI
Intel®
QPI
®
®
1.2.2
Intel Itanium Processor 9500 Series Overview
The Intel® Itanium® Processor 9500 Series is an eight core architecture. It supports up
to eight cores, each with its own First Level Cache (FLC) and Mid Level Cache (MLC),
both of which are split into instruction and data caches (FLI/FLD and MLI/MLD,
respectively). The Last Level Cache (LLC) is shared among the cores and supports up to
32 MB. Also supported are the following page sizes for purges or inserts: 4K, 8K, 16K,
64K, 256K, 1M, 4M, 16M, 64M, 256M, 1G, 4G.
The architecture interfacing the cores to the system is referred to as the uncore. Each
Intel® Itanium® Processor 9500 Series core interfaces to the Ring. The Ring provides
connectivity to the Last Level Cache via the Cache Controllers (Cboxes). The Ring also
provides connectivity to Intel QPI via Ring/Sbox. The Sbox and Cbox provide the
supports for the two Intel QPI Caching Agents. The processor has two Home Agents
(Bbox). The Bbox interfaces between the memory controller and the Intel® QuickPath
Interconnect and supports a directory cache. Each memory controller supports two
Intel® Scalable Memory Interconnects (Intel® SMI) in lockstep. The Intel SMI are the
interconnects to Scalable Memory Buffer. The Intel® Itanium® Processor 9500 Series
processor supports six Intel® QuickPath Interconnects at the socket, four full width and
two half width. The Caching Agent, Home Agent, and Intel® QuickPath Interconnects
are connected via a 10-port Crossbar Router, each port supporting the Intel® QuickPath
Interconnect protocol. Figure 1-2 shows the processor block diagram.
®
®
16
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Introduction
Figure 1-2. Intel® Itanium® Processor 9500 Series Processor Block Diagram
The Intel QPI viral and poison fields are used to flag corrupted system state and bad
data accordingly. Once it has “gone viral”, an Intel QPI agent will set the viral field
within all packet headers. Viral mode is entered in three ways: receiving a viral packet,
upon a detecting fatal/panic error, or when a global viral signal (from Cboxes) is
asserted. Viral is cleared on Reset. Poisoning is used to indicate bad data on a per-flit
basis. Poison does not indicate corrupted system coherency, but rather that a particular
block of data is not reliable.
Intel® Itanium® Processor 9500 Series PAL's Demand Based Switching (DBS) support
includes implementations of Power/Performance states (P-states) and Halt states (C-
states). For the PAL Halt state interface and architected specifications of the PAL P-
state interface, see the Intel® Itanium® Architecture Software Developer's Manual,
Volume 2, Section 11.6. PAL controls the Intel® Itanium® Processor 9500 Series
processor power through a special built-in microcontroller that manipulates voltage and
frequency. PAL communicates requested P-states to this controller through internal
registers.
As shown in Figure 1-3, Itanium architecture-based firmware consists of several major
components: Processor Abstraction Layer (PAL), System Abstraction Layer (SAL),
Unified Extensible Firmware Interface (UEFI) and Advanced Configuration and Power
Interface (ACPI). PAL, SAL, UEFI and ACPI together provide processor and system
initialization for an operating system boot. PAL and SAL provide machine check abort
handling. PAL, SAL, UEFI and ACPI provide various run-time services for system
functions which may vary across implementations. The interactions of the various
services that PAL, SAL, UEFI and ACPI provide are illustrated in Figure 1-3. In the
context of this model and throughout the rest of this chapter, the System Abstraction
Layer (SAL) is a firmware layer which isolates operating system and other higher level
software from implementation differences in the platform, while PAL is the firmware
layer that abstracts the processor implementation.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
17
Introduction
Protection Keys provide a method to restrict permission by tagging each virtual page
with a unique protection domain identifier. The Protection Key Registers (PKR)
represent a register cache of all protection keys required by a process. The operating
system is responsible for management and replacement polices of the protection key
cache. Before a memory access (including IA-32) is permitted, the processor compares
a translation’s key value against all keys contained in the PKRs. If a matching key is not
found, the processor raises a Key Miss fault. If a matching Key is found, access to the
page is qualified by additional read, write and execute protection checks specified by
the matching protection key register. If these checks fail, a Key Permission fault is
raised. Upon receipt of a Key Miss or Key Permission fault, software can implement the
desired security policy for the protection domain. Some processor models may
implement additional protection key registers and protection key bits. Unimplemented
bits and registers are reserved. Please see the processor-specific documentation for
further information on the number of protection key registers and protection key bits
implemented on the processor.
Figure 1-3. Intel® Itanium® Processor 9500 Series Firmware Diagram
®
®
18
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Introduction
1.3
Processor Feature Comparison
The Intel® Itanium® Processor 9300 Series processor and Intel® Itanium® Processor
9500 Series processor features are compared below in Table 1-1.
Table 1-1.
Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series Feature Comparison
®
®
®
®
Intel Itanium Processor 9300
Series
Intel Itanium Processor 9500
Series
Description
Socket
LG1248
2 billion
up to 4/8
LG1248
3.1 billion
Transistors
Cores/Threads
Clock speeds
up to 8/16
®
up to 1.86 GHz via Intel Turbo Boost
1.73 - 2.53 GHz
with sustained boost
Integrated on-die cache
L1 (L1I 16K/L1D 16K),
L2 (L2I 512K, L2D 256K),
inclusive L3 (6 MB per core,
up to 24 MB)
FLC (FLI 16K/FLD 16K),
MLC (MLI 512K, MLD 256K),
LLC (shared, up to 32 MB)
Ararat Voltage Regulator Module Support
Supported speeds
Ararat “I”
DDR3-800
Ararat II
DDR3-800 and DDR3-1067
Intel QPI links
6
6
(4 full/2 half width at up to 4.8 GT/s)
(4 full/2 half width at up to 6.4 GT/s)
Intel QPI Hot-plug
Supported
Supported
Supported
Supported
Not Supported
2
Supported
Supported
Supported
Required
Intel QPI Link self-healing
Intel QPI Clock fail-safe
Intel QPI Data scrambling
Intel QPI Periodic retraining
Integrated memory controllers
1
Required
2
®
®
®
Intel SMI Interface
Intel 7500 Scalable Memory Buffer
Intel 7500 Scalable Memory Buffer
(4.8 GT/s)
(4.8 GT/s)
®
Intel 7510 Scalable Memory Buffer
(6.4 GT/s)
®
Intel SMI Hot-plug
Supported
Supported
Physical address space/virtual address
space
50 physical/64 virtual
50 physical/64 virtual
Caching agent architecture
four caching agents per socket where
each agent is responsible for all of the
address space and dedicated to a core
two caching agents per socket are
responsible for half the address space
and shared among the cores
Home agents per socket
Directory Cache
2
2
Supported
Supported
®
®
®
®
Intel Virtualization Technology (Intel VT)
Intel Vt-i 2
Intel Vt-i 3
Hot add/hot removal at Intel QPI link and
DIMM memory interface
Supported
Supported
2,3
2,3
Hot add CPU
Supported
Supported
2,3
2,3
Hot add memory
Supported
Supported
2,3
2,3
Hot remove/hot replace memory
Memory sparing technique
Memory scrubbing
Supported
Supported
DIMM
DIMM and Rank
Supported
Supported
Supported
Memory mirroring
Supported
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
19
Introduction
®
®
®
®
Intel Itanium Processor 9300
Series
Intel Itanium Processor 9500
Series
Description
Memory patrolling
Supported
Supported
Supported
Supported
Supported
Memory migration
Support for mixing of x4 and x8 on the
same DDR channel
Not Supported
Online/Offline CPU (OS assisted)
Online/Offline Memory (OS assisted)
Online/Offline I/O Hub
Supported
Supported
Supported
Supported
Supported
Supported
Thermal Design Power (TDP) SKUs
130W, 155W, 185W
130W and 170W
Notes:
1. OEM responsible for specifying platform-specific retraining interval.
2. Electrical isolation only, no physical add/remove supported.
3. Assume spare is installed.
1.4
Processor Abstraction Layer
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
require implementation-specific Processor Abstraction Layer (PAL) firmware. PAL
firmware supports processor initialization, error recovery, and other functionality. It
provides a consistent interface to system firmware and operating systems across
processor hardware implementations. The Intel® Itanium® Architecture Software
Developer’s Manual, Volume 2: System Architecture, describes PAL. Platforms must
provide access to the firmware address space and PAL at reset to allow the processors
to initialize.
The System Abstraction Layer (SAL) firmware contains platform-specific firmware to
initialize the platform, boot to an operating system, and provide runtime functionality.
Further information about SAL is available in the Intel® Itanium® Processor Family
System Abstraction Layer Specification.
1.5
1.6
Mixing Processors of Different Frequencies and
Cache Sizes
All Intel® Itanium® Processor 9300 Series processors and Intel® Itanium® Processor
9500 Series in the same system partition are required to have the same last level
cache size and identical core frequency. Mixing processors of different core frequencies,
cache sizes, and mixing Intel® Itanium® Processor 9300 Series with Intel® Itanium®
Processor 9500 Series is not supported and has not been validated by Intel. Operating
system support for multiprocessing with mixed components should also be considered.
Terminology
In this document, “the processor” refers to the Intel® Itanium® Processor 9300 Series
and/or Intel® Itanium® Processor 9500 Series, unless otherwise indicated.
An ‘_N’ notation after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low
level. For example, when RESET_N is low, a processor reset has been requested. When
NMI is high, a non-maskable interrupt has occurred. In the case of lines where the
name does not imply an active state but describes part of a binary sequence (such as
®
®
20
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Introduction
address or data), the ‘_N’ notation implies that the signal is inverted. For example,
D[3:0] = ‘HLHL’ refers to a Hex ‘A’, and D [3:0] _N = ‘LHLH’ also refers to a Hex ‘A’ (H
= High logic level, L = Low logic level).
A signal name has all capitalized letters, for example, VCTERM.
A symbol referring to a voltage level, current level, or a time value carries a plain
subscript, for example, Vccio, or a capitalized abbreviated subscript, for example, TCO.
1.7
1.8
State of Data
The data contained in this document is subject to change. It is the best information
that Intel is able to provide at the publication date of this document.
Reference Documents
The reader of this specification should also be familiar with material and concepts
presented in the following documents:
Document Name
®
®
Intel Itanium Processor 9300 Series and 9500 Series Specification Update
®
®
Intel Itanium Architecture Software Developer’s Manual, Volume 1:
Application Architecture
®
®
Intel Itanium Architecture Software Developer’s Manual, Volume 2: System
Architecture
®
®
Intel Itanium Architecture Software Developer’s Manual,
Volume 3: Instruction Set Reference
®
®
Intel Itanium Architecture Software Developer’s Manual,
Volume 4: IA-32 Instruction Set Reference
®
®
Intel Itanium 9300 Series Processor Reference Manual for Software
Development and Optimization
®
®
Intel Itanium 9500 Series Processor Reference Manual for Software
Development and Optimization
®
®
Intel Itanium Processor Family System Abstraction Layer Specification
®
®
®
®
Intel Itanium Processor 9300 Series and Intel Itanium Processor 9500
Series Platform Design Guide
System Management Bus (SMBus) Specification
Note:
Contact your Intel representative or check http://developer.intel.com for the latest
revision of the reference documents.
§
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
21
Introduction
®
®
22
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
2
Electrical Specifications
This chapter describes the electrical specifications of the Intel® Itanium® Processor
9300 Series and 9500 Series processors.
2.1
Intel® QuickPath Interconnect and Intel®
Scalable Memory Interconnect
Differential Signaling
The links for Intel® QuickPath Interconnect (Intel® QPI) and Intel® Scalable Memory
Interconnect (Intel® SMI) signals use differential signaling. The Intel® SMI bus pins are
referred to as FB-DIMM pins on the package. The termination voltage level for the
processor for uni-directional serial differential links, each link consisting of a pair of
opposite-polarity (D+, D-) signals, is VSS
.
Termination resistors are provided on the processor silicon and are terminated to VSS,
thus eliminating the need to terminate the links on the system board for the Intel®
QuickPath Interconnect and FB-DIMM signals.
When designing a system, Intel strongly recommends that design teams perform
analog simulations of the Intel® QuickPath Interconnect and FB-DIMM pins. Please
refer to the latest available revision of the Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series Platform Design Guide.
Figure 2-1 illustrates the active on-die termination (ODT) of these differential signals.
All the differential signals listed in Table 2-1 have ODT resistors. Also included in the
table are the debug signals.
Figure 2-1. Active ODT for a Differential Link Example
TX
RX
Signal
Signal
RTT
RTT
RTT
RTT
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
23
Electrical Specifications
Table 2-1.
Signals with RTT
Signal
Termination
CSI[3:0]R[P/N]Dat[19:0]
CSI[5:4]R[P/N]Dat[9:0]
CSI[3:0]T[P/N]Dat[19:0]
CSI[5:4]T[P/N]Dat[9:0]
CSI[5:0]R[P/N]Clk
VSS
VSS
CSI[5:0]T[P/N]Clk
FBD0NBICLK[A/B][P/N]0
FBD1NBICLK[C/D][P/N]0
FBD0SBOCLK[A/B][P/N]0
FBD1SBOCLK[C/D][P/N]0
FBD0NBI[A/B][P/N][13:0]
FBD1NBI[C/D][P/N][13:0]
FBD0SBO[A/B][P/N][10:0]
FBD1SBO[C/D][P/N][10:0]
XDPOCPD_N[7:0]
TRIGGER_N[1:0]
VCCIO
XDPOCPFRAME_N
XDPOCP_STRB_IN_N
PRBMODE_REQST_N
XDPOCP_STRB_OUT_N
PRBMODE_RDY_N
2.2
Signal Groups
The signals are grouped by buffer type and similar characteristics as listed in Table 2-2.
The buffer type indicates which signaling technology and specifications apply to the
signals.
Table 2-2.
Signal Groups (Sheet 1 of 3)
Signal Group
Buffer Type
Signals 1, 2, 3
Differential System Reference Clock
Differential
CMOS In Differential Pair
SYSCLK, SYSCLK_N;
SYSUTST_REFCLK_N, SYSUTST_REFCLK
®
Intel QuickPath Interconnect Signal Groups
Differential
Differential
Input
CSI[3:0]R[P/N]Dat[19:0], CSI[5:4]R[P/N][9:0]
CSI[5:0]R[P/N]CLK
Output
CSI[3:0]T[P/N]Dat[19:0], CSI[5:4]T[P/N][9:0],
CSI[5:0]T[P/N]CLK
FB-DIMM Signals
Differential
Differential
Differential
Differential
Input
FBD0NBICLK[A/B][P/N]0
FBD1NBICLK[C/D][P/N]0
Output
Input
FBD0SBOCLK[A/B][P/N]0
FBD1SBOCLK[C/D][P/N]0
FBD0NBI[A/B][P/N][13:0]
FBD1NBI[C/D][P/N][13:0]
Output
FBD0SBO[A/B][P/N][10:0]
FBD1SBO[C/D][P/N][10:0]
TAP
®
®
24
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-2.
Signal Groups (Sheet 2 of 3)
Signal Group
Buffer Type
CMOS Inputs
Signals 1, 2, 3
TCK, TDI, TMS, TRST_N
Single-ended
GTL Open Drain Output
TDO
SMBus
Single-ended
GTL I/O
SMBCLK,
SMBDAT
SPD Bus
Single-ended
GTL I/O
SPDCLK
SPDDAT
Setup
Single-ended
GTL Input
BOOTMODE[1:0], SKTID[2:0]
LRGSCLSYS
System Management
Single-ended
CMOS Input
Flash ROM Port
Single-ended
GTL-open Drain Input
GTL-open Drain Output
FLASHROM_CFG[2:0],
FLASHROM_DATI
FLASHROM_CS[3:0]_N, FLASHROM_CLK,
FLASHROM_DATO, FLASHROM_WP_N
ERROR Bus
Single-ended
GTL Open Drain Output
GTL Input
ERROR[0]_N, ERROR[1]_N
MEM_THROTTLE_L
Power-up
Single-ended
Thermal
GTL Input
PWRGOOD, RESET_N
Single-ended
GTL-Open Drain Output
GTL Input
PROCHOT_N, THERMTRIP_N, THERMALERT_N
FORCEPR_N
4
®
®
VID Port (Intel Itanium Processor 9300 Series)
Single-ended
CMOS Output
VID_VCCCORE[6:0], VID_VCCCACHE[5:0],
VID_VCCUNCORE[6:0]
4
®
®
SVID Port (Intel Itanium Processor 9500 Series)
Single-ended
GTL Output
GTL I/O
SVID_CLK
SVD_DATIO
GTL Input
SVID_ALERT_N
4
Voltage Regulator
®
®
Single-ended
Open Collector/Drain Output
VR_THERMTRIP_N, VRPWRGD (Intel Itanium
®
Processor 9300 Series processor), VR_READY (Intel
®
Itanium Processor 9500 Series processor), VR_FAN_N
4
Voltage Regulator Control
Single-ended
CMOS Input
VROUTPUT_ENABLE0
GTL Input
VR_THERMALERT_N
Open Collector/Drain Output
VR_THERMTRIP_N, VRPWRGD, VR_FAN_N
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
25
Electrical Specifications
Table 2-2.
Signal Groups (Sheet 3 of 3)
Signal Group
Debug
Buffer Type
Signals 1, 2, 3
GTL I/O
XDPOCPD_N[7:0],TRIGGER_N[1:0]
XDPOCPFRAME_N
Single-ended
GTL Input
XDPOCP_STRB_IN_N, PRBMODE_REQST_N
XDPOCP_STRB_OUT_N, PRBMODE_RDY_N
GTL Output
Power Supplies
4
Core
V
V
V
CCCORE
4
Uncore
CCUNCORE
®
®
4
Cache (Intel Itanium
Processor 9300 Series)
CCCACHE
Analog
I/O
V
V
V
CCA
CCIO
Stand-by
CC33_SM
V
Pins
CC33_SM
Input
I/O
PIR_SCL
PIR_SDA
PIR_A0
PIR_A1
SM_WP
PIROM
Input
Input
Input
Notes:
1. CMOS signals have a reference voltage (Vref) equal to VCCIO/2.
2. GTL signals have a reference voltage (Vref) equal to VCCIO*(2/3).
3. All single-ended buffer types, including inputs, outputs and input/outputs, include an on-die pull up resistor
between 4 kOhms and 8.7 kOhms. Recommended values for external pull-downs on the inputs and input/
output signals must meet the V specification for that buffer.
il
2.3
Reference Clocking Specifications
The processor has one input reference clock, SYSCLK/SYSCLK_N for the Intel® QPI
interface. The processor timing specified in this section is defined at the processor pins
unless otherwise noted.
Table 2-3.
Intel® QuickPath Interconnect/Intel® Scalable Memory Interconnect
Reference Clock Specifications (Sheet 1 of 2)
Symbol
Parameter
Min
Nom
Max
Units
Notes
133.31
133.33
133.34
MHz
fsysclk (ssc-off)
Fsyclk (scc-on)
System clock frequency
System clock frequency
132.62
1.0
132.99
133.37
4.0
MHz
V/ns
ER
ER
Differential Rising and Falling Edge
Rates
3,4
3
sysclk-diff-Rise,
sysclk-diff-Fall
T
Duty cycle of Reference clock
Clock Input Capacitance
Differential High Input Voltage
Differential Low Input Voltage
Absolute crossing point
40
0.5
60
% period
sysclk_dutycycle
C
2.0
pf
V
i-CK
VH
VL
0.15
3
-0.15
0.55
140
V
3
V
V
V
0.25
-100
0.35
V
1, 5, 6
1, 5, 7
3, 10
Cross
Peak-peak variation
mv
mV
Cross_delta
RB-Diff
Differential Ringback voltage
threshold
100
®
®
26
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-3.
Intel® QuickPath Interconnect/Intel® Scalable Memory Interconnect
Reference Clock Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Nom
Max
Units
Notes
T
Allowed time before ringback
500
ps
ps
3, 10
2
Stable
0.5
Accumulated rms jitter over n UI of a
given PLL model output in response to
the jittery reference clock input. The
PLL output is generated by convolving
the measured reference clock phase
jitter with a given PLL transfer
TREFCLK-JITTER-RMS-
ONEPLL
function. Here n=12.
Note:
1.
2.
Measurement taken from single-ended waveform.
The given PLL parameters are: Underdamping (z) = 0.8 and natural frequency = fn = 7.86E6 Hz; wn = 2 *fn. N_minUI = 12
®
for Intel QuickPath Interconnect 4.8 Gt/s channel.
3.
4.
Measurement taken from differential waveform.
Measured from -150 mV to +150 mV on the differential waveform (derived from SYSCLK minus SYSCLK_N). The signal must
be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the
differential zero crossing. See Figure 2-4.
5.
6.
7.
Measured at crossing point where the instantaneous voltage value of the rising edge SYSCLK equals the falling edge
SYSCLK_N. See Figure 2-2.
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all
crossing points for this measurement. See Figure 2-3.
Defined as the total variation of all crossing voltages of Rising SYSCLK and falling SYSCLK_N. This is the maximum allowed
variance in Vcross for any particular system. See Figure 2-2.
Defined as the maximum instantaneous voltage including overshoot. See Figure 2-2.
Defined as the minimum instantaneous voltage including undershoot. See Figure 2-2.
8.
9.
10.
T
is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges
Stable
before it is allowed to droop back into the VRB ±100 mV range. See Figure 2-5.
Figure 2-2. Single-ended Maximum and Minimum Levels and Vcross Levels
Figure 2-3. Vcross-delta Definition
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
27
Electrical Specifications
Figure 2-4. Differential Edge Rate Definition
ERRefclk-diff-Rise
ERRefclk-diff-Fall
VRefclk-diff-ih = 150 mV
0.0 V
VRefclk-diff-il = –150 mV
REFCLKdiff
Figure 2-5. VRB and TStable Definitions
TStable
VRefclk-diff-ih = 150 mV
V
100 mV
0.0 V
RB- diff max
VRB-diff min =– 100 mV
VRefclk-diff-ih =– 150 mV
REFCLK
diff
TStable
2.4
Intel® QuickPath Interconnect and Intel® SMI
Signaling Specifications
.
®
®
®
2.4.1
Intel Itanium Processor 9300 Series Intel QuickPath
®
Interconnect and Intel SMI Specifications for 4.8 GT/s
The applicability of this section applies to Intel® QPI for the Intel® Itanium® Processor
9300 Series. This section contains information for Intel® QPI slow boot up speed
(1/4 frequency of the reference clock) and processor’s normal operating frequency, 4.8
GT/s, for Intel® QPI and Intel® SMI.
For Intel® QPI slow boot up speed, the signaling rate is defined as 1/4 the rate of the
system reference clock. For example, a 133 MHz system reference clock would have a
forwarded clock frequency of 33.33 MHz and the signaling rate would be 66.67 MT/s.
The transfer rates available for the processor are shown in Table 2-4. Transmitter and
receiver parameters for Intel® QPI slow mode, Intel® QPI and Intel® SMI are shown in
Table 2-5 and Table 2-6 respectively.
®
®
28
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-4.
Intel® Itanium® Processor 9300 Series Clock Frequency Table
®
®
Intel QuickPath Interconnect
Intel QuickPath Interconnect Data
Forwarded Clock Frequency
Transfer Rate
)
33.33 MHz
2.40 GHz
66.66 MT/s (see note 1
4.8 GT/s
Notes:
1. This speed is the 1/4 SysClk Frequency.
Table 2-5.
Intel® Itanium® Processor 9300 Series Transmitter Parameter Values for
Intel® QuickPath Interconnect and Intel SMI Channels @ 4.8 GT/s (Sheet 1 of
2)
Symbol
Parameter
Min
Nom
Max
Units
Notes
UI
Average UI size at 4.8 GT/s
208.33
ps
avg
N
# of UI over which the eye mask voltage and
timing spec needs to be validated
1E6
6
MIN-UI-Validation
T
Defined as the slope of the rising or falling
waveform as measured between ±100 mV of
the differential transmitter output, data or
clock
12
V/ns
slew-rise-fall-pin
V
Transmitter differential swing
900
37.4
500
1300
47.6
mV
Ω
Tx-diff-pp-pin
R
Z
V
Transmitter termination resistance
Link Detection Resistor
4
TX
2000
Ω
TX_LINK_DETECT
TX_LINK_DETECT
Link Detection Resistor Pull-up Voltage
Skew between first to last data termination
max VCCIO
V
T
600
780
UI
2
2
DATA_TERM_SKEW
®
meeting Z
RX_LOW_CM_DC
Intel QPI
T
Skew between first to last data termination
UI
DATA_TERM_SKEW
®
meeting Z
RX_LOW_CM_DC
Intel SMI
T
Time taken by inband reset detector to sense
Inband Reset
8k
8k
256k
256k
500
25
UI
UI
ps
dB
INBAND_RESET_SENSE
CLK_DET
T
Time taken by clock detector to observe clock
stability
TSYSCLK-TX-VARIABILITY
Phase variability between reference Clk (at Tx
input) and Tx output.
TX
Voltage ratio between the cursor and the
post-cursor when transmitting successive
ones
0
3
EQ-BOOST
V
V
Transmitter data or clock common mode level
23
0
27
14
%
%
TX-CM-PIN
Transmitter data or clock common mode
ripple
8,9
TX-CM-RIPPLE-PIN
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
29
Electrical Specifications
Table 2-5.
Intel® Itanium® Processor 9300 Series Transmitter Parameter Values for
Intel® QuickPath Interconnect and Intel SMI Channels @ 4.8 GT/s (Sheet 2 of
2)
Symbol
Parameter
Min
Nom
Max
Units
Notes
TXDUTY-CYCLE-PIN
Transmitter clock or data duty cycle at the
pin. Transmit duty cycle at the pin, defined as
-0.076
0.076
UI-UI
6
®
UI to UI jitter as specified by the Intel QPI
Electrical Specification, Rev 1.0.
T
Delay of any data lane relative to clock lane,
as measured at Tx output
-0.5
0
0.5
UI
UI
1,2
5
TX-DATA-CLK-SKEW-PIN
TXACC-JIT-N_UI-1E-9
Peak-to-peak accumulated jitter out of any TX
data or clock over 0<= n <= N UI where
N=12, measured with 1E-9 probability.
0.18
TXJITUI-UI-1E-9PIN
RL
Transmitter clock or data UI-UI jitter at 1E-9
probability.
0
0.17
dB
UI
5
7
7
Transmitter Differential return loss from
50MHz to 2GHz
-10
-6
TX-DIFF
RL
Transmitter Differential return loss from
2GHz to 4GHz
dB
TX-DIFF
Notes:
®
1.
2.
3.
4.
5.
6.
Parameter value at full Intel QPI Refclk.
Stagger offset = 0xF.
See Figure 2-6.
The termination small signal resistance; tolerance over the entire signalling voltage range shall not exceed ±5 ohms.
Requires Matlab script.
Refer to Intel QuickPath Interconnect (Intel QPI) - Electrical Specifications for calculation of this value. Note that UI to UI.
®
®
definition is used herein, where the value of UI-UI DCD = 2*UI DCD.
See Figure 2-7.
7.
8.
9.
Applies to Vtx-diff-pp-pin.
Peak-to-peak value of the ripple.
Table 2-6.
Intel® Itanium® Processor 9300 Series Receiver Parameter Values for Intel®
QuickPath Interconnect and Intel® SMI Channels @ 4.8 GT (Sheet 1 of 2)
Symbol
Parameter
RX termination resistance
Min
Nom
Max
Units
Notes
R
37.4
47.6
Ω
3
RX
T
Delay of any data lane relative to the clock lane, as
measured at the end of Tx+ channel. This parameter is
a collective sum of effects of data clock mismatches in
Tx and on the medium connecting Tx and Rx.
Rx-data-clk-skew-pin
-0.5
0.48
3.5
UI
UI
2
Delay of any data lane relative to the clock lane, as
measured at the end of Tx+ channel. This parameter is
a collective sum of effects of data clock mismatches in
Tx and on the medium connecting Tx and Rx.
T
0.52
1
6
Rx-data-clk-skew-pin
RL
RL
Receiver differential return loss from 50 MHz to 2 GHz
Receiver differential return loss from 2GHz to 4GHz
-10
-6
dB
dB
RX-DIFF
6
2
RX-DIFF
V
V
Receiver data common mode level
Receiver data common mode ripple
125
0
350
100
mV
Rx-data-cm-pin
mV
Rx-data-cm-ripple-
p-p
pin
V
V
Receiver clock common mode level
Receiver clock common mode ripple
175
0
350
100
mV
Rx-clk-cm-pin
mV
Rx-clk-cm-ripple-pin
p-p
V
Minimum eye height at pin for data
Minimum eye height at pin for clk
200
225
mV
mV
4
5
RX-eye-data-pin
RX-eye-clk-pin
V
®
®
30
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-6.
Intel® Itanium® Processor 9300 Series Receiver Parameter Values for Intel®
QuickPath Interconnect and Intel® SMI Channels @ 4.8 GT (Sheet 2 of 2)
Symbol
Parameter
Min
Nom
Max
Units
Notes
T
Minimum eye width at pin for clk and data
0.6
UI
4
RX-eye-pin
QPI BER
Bit Error Rate per lane valid for 4.8 and 6.4 GT/s
Bit Error Rate per lane valid for 4.8 and 6.4 GT/s
1.0E-14
1.0E-12
Events
Events
Lane
SMI BER
Lane
Notes:
®
®
1.
2.
3.
Parameter value at 1/4 Intel QPI Refclk.
Parameter value at full Intel QPI Refclk.
The termination small signal resistance; tolerance over the entire signalling voltage range shall not exceed ±5 ohms with
regard to the average of the values measured in the high output voltage state and the low output voltage state for that pin.
HVM guaranteed error free value for stressed PRBS signaling across PVT. Link BER is the dominant spec of which eye
dimensions are only one factor, and improving another factor could compensate for eye height or width.
HVM guaranteed error free value for stressed ‘1010 signaling across PVT. Link BER is the dominant spec of which eye
dimensions are only one factor, and improving another factor could compensate for eye height or width.
See Figure 2-8.
4.
5.
6.
Figure 2-6. TX Equalization Diagram
C-1
C0
C1
C2
C-1
C0
C1
C2
A
Vpost
Vsust
0
Vpre
-A
C0 = 1 – sum of abs value of other coeficents
Vpre = A(C-1 - C0 - C1 - C2)
Vpost - Vpre – Vsust = |C-1| + |C0 |+ |C1 |+ |C2| = 1
%Peaking = Vpost/Vsust
Vpost = A(C-1 + C0 - C1 - C2)
Vsust = A(C-1 + C0 + C1 + C2
)
Example: A=500mV, C-1= -0.035, C0= 0.685, C1= -0.28, C2= 0
Vpre = 0.500(-0.035 – 0.685 + 0.28) = 0.5(-0.44) = -220mV
Vpost = 0.500(-0.035 + 0.685 + 0.28) = 0.5(0.93) = 465mV
Vsust = 0.500(-0.035 + 0.685 – 0.28) = 0.5(0.37) = 185mV
TXEQ-BOOST = 20log(Vpost/Vsust) = 20log(465/185) = 8dB
Peaking = 465/185 = 251%
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
31
Electrical Specifications
Figure 2-7. TX Return Loss
Figure 2-8. RX Return Loss
®
®
®
2.4.2
Intel Itanium Processor 9500 Series Requirements for
Intel QuickPath Interconnect for 4.8 and 6.4 GT/s
The applicability of this section applies to Intel® Itanium® Processor 9500 Series. This
section contains information for slow boot up speed (1/4 frequency of the reference
clock), 4.8 GT/s, and 6.4 GT/s, for Intel® QPI and Intel® SMI.
For Intel® QPI slow boot up speed, the signaling rate is defined as 1/4 the rate of the
system reference clock. For example, a 133 MHz system reference clock would have a
forwarded clock frequency of 33.33 MHz and the signaling rate would be 66.67 MT/s.
®
®
32
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
The transfer rates available for the processor are shown in Table 2-7. Transmitter and
receiver parameters for Intel® QPI slow mode, Intel® QPI and Intel® SMI are shown in
Table 2-8 and Table 2-9 respectively.
Table 2-7.
Intel® Itanium® Processor 9500 Series Clock Frequency Table
®
®
Intel QuickPath Interconnect
Intel QuickPath Interconnect Data
Forwarded Clock Frequency
Transfer Rate
33.33 MHz
2.40 GHz
3.2 GHz
66.66 MT/s (see note 1)
4.8 GT/s
6.4 GT/s
Notes:
1. This speed is the 1/4 SysClk Frequency.
The applicability of this section applies to Intel® QPI for the Intel® Itanium® Processor
9500 Series. This section contains information for slow boot up speed (1/4 frequency of
the reference clock), 4.8 GT/s, and 6.4 GT/s.
Specifications for link speed independent specifications are called out in Table 2-8.
Electrical specifications for Transmit and Receive for 4.8 GT/s are captured in Table 2-9
and for 6.4 GT/s are captured in Table 2-10.
Table 2-8.
Intel® Itanium® Processor 9500 Series Link Speed Independent Specifications
(Sheet 1 of 2)
Symbol
UIavg
Parameter
Min
Nom
Max
Unit
Notes
Average UI size at “G”
GT/s (Where G = 4.8,
6.4, and so on)
0.999 *
nominal
1000/G
1.001 *
nominal
psec
T
Defined as the slope of
the rising or falling
waveform as measured
between ±100mV of the
differential transmitter
output, for any data or
clock
9
20
V/nsec
slew-rise-fall-pin
ΔZ
ΔZ
Defined as:
-6
-6
6
6
% of
TX_LOW_CM_DC
RX_LOW_CM_DC
MIN-UI-Validation
(max(Z
) -
Z
TX_LOW_CM_DC
TX_LOW_CM_DC
min(Z
)) /
TX_LOW_CM_DC
Z
expressed
TX_LOW_CM_DC
in %, over full range of Tx
single ended voltage
Defined as:
0
% of
(max(Z
) -
)) /
expressed
Z
TX_LOW_CM_DC
TX_LOW_CM_DC
min(Z
TX_LOW_CM_DC
Z
TX_LOW_CM_DC
in %, over full range of Tx
single ended voltage
N
Z
# of UI over which the
eye mask voltage and
timing spec needs to be
validated
1,000,000
Single ended DC
4k
4k
Ω
Ω
TX_HIGH_CM_DC
impedance to GND for
either D+ or D- of any
data bit at Tx
Z
Single ended DC
1
RX_HIGH_CM_DC
impedance to GND for
either D+ or D- of any
data bit at Rx
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
33
Electrical Specifications
Table 2-8.
Intel® Itanium® Processor 9500 Series Link Speed Independent Specifications
(Sheet 2 of 2)
Symbol
Parameter
Min
500
Nom
Max
2000
Unit
Notes
Z
V
Link Detection Resistor
Ω
TX_LINK_DETECT
TX_LINK_DETECT
Link Detection Resistor
Pull-up Voltage
max VCCIO
V
T
T
Skew between first to last
data termination meeting
RX_LOW_CM_DC
128
UI
μs
UI
DATA_TERM_SKEW
Z
Time taken by inband
reset detector to sense
Inband Reset
1.5
20K
32
INBAND_RESET_
SENSE
Tclk
Time taken by clock
detector to observe clock
stability
_DET
T
Time taken by clock
frequency detector to
decide slow vs.
Reference
Clock Cycles
CLK_FREQ_DET
operational clock after
stable clock
T
T
Phase variability between
reference Clk (at Tx
500
psec
psec
UI
Refclk-Tx-Variability
Refclk-Rx-Variability
D+/D-RX-Skew
input) and Tx output.
Phase variability between 1000
reference Clk (at Rx
input) and Rx output.
L
Phase skew between D+
and D- lines for any data
bit at Rx
0.03
BER
Bit Error Rate per lane
valid for 4.8 and 6.4 GT/s
1.0E-14
Events
Lane
Notes:
1. Used during initialization. It is the state of “OFF” condition for the receiver when only the minimum termination
is connected.
Table 2-9.
Intel® Itanium® Processor 9500 Series Transmitter and Receiver Parameter
Values for Intel® QPI Channel at 4.8 GT/s (Sheet 1 of 2)
Symbol
Parameter
Min
900
Nom
Max
1400
Unit
Notes
V
Z
Transmitter differential swing
mV
1
Tx-diff-pp-pin
DC resistance of Tx terminations
at half the single ended swing
37.4
50
Ω
TX_LOW_CM_DC
RX_LOW_CM_DC
(which is usually 0.25*V
Tx-diff-pp-
) bias point
pin
Z
DC resistance of Rx terminations
at half the single ended swing
37.4
50
Ω
(which is usually 0.25*V
pin
Tx-diff-pp-
) bias point
V
V
Transmitter output DC common
mode, defined as average of V
0.23
0.27
Fraction of
Tx-diff-pp-pin
Tx-cm-dc-pin
Tx-cm-ac-pin
V
D+
and V
D-
Transmitter output AC common
mode, defined as ((V + V )/2 -
-0.0375
-0.055
0.0375
Fraction of
2
V
D+
D-
Tx-diff-pp-pin
V
)
Tx-cm-dc-pin
TX
TX
Average of UI-UI jitter
0.055
0.075
UI
UI
duty-pin
UI-UI jitter measured at Tx output -0.075
pins with 1E-7 probability
jitUI-UI-1E-7-pin
TX
UI-UI jitter measured at Tx output -0.085
pins with 1E-9 probability.
0.085
UI
jitUI-UI-1E-9-pin
®
®
34
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-9.
Intel® Itanium® Processor 9500 Series Transmitter and Receiver Parameter
Values for Intel® QPI Channel at 4.8 GT/s (Sheet 2 of 2)
Symbol
Parameter
Min
Nom
Max
0.15
Unit
Notes
TX
p-p accumulated jitter out of
transmitter over 0 <= n <= N UI
where N=12, measured with 1E-7
probability.
0
0
UI
UI
clk-acc-jit-N_UI-1E-7
TX
p-p accumulated jitter out of
transmitter over 0 <= n <= N UI
where N=12, measured with 1E-9
probability.
0.17
clk-acc-jit-N_UI-1E-9
Tx-data-clk-skew-pin
T
Delay of any data lane relative to
clock lane, as measured at Tx
output
-0.5
0.5
UI
V
Voltage eye opening at the end of 225
Tx+ channel for any data or clock
channel measured with a
cumulative probability of 1E-9
(UI).
1200
mV
Rx-diff-pp-pin
T
T
Timing eye opening at the end of
Tx+ channel for any data or clock
channel measured with a
0.63
1
3
UI
UI
Rx-diff-pp-pin
cumulative probability of 1E-9 (UI)
Delay of any data lane relative to
the clock lane, as measured at the
end of Tx+ channel. This
-1
Rx-data-clk-skew-pin
parameter is a collective sum of
effects of data clock mismatches
in Tx and on the medium
connecting Tx and Rx.
V
V
Forward CLK Rx input voltage
sensitivity (differential pp)
180
350
mV
mV
Rx-CLK
DC common mode ranges at the
Rx input for any data or clock
channel
125
-50
Rx-cm-dc-pin
V
AC common mode ranges at the
Rx input for any data or clock
channel, defined as:
50
mV
2
Rx-cm-ac-pin
((V
+ V /2 - V
)
RX-cm-dc-pin
D+
D-
Notes:
1.
1300 mVpp swing is recommended when CPU to CPU or CPU to IOH length is within 2” of PDG max trace
length. Note that default value is 1100 mVpp.
2.
Measure AC CM noise at the TX and decimate to its spectral components. For all spectral components above
3.2 GHz, apply the attenuation of the channel at the appropriate frequency. If the resultant AC CM at the
receiver is met after taking out the appropriate spectral components meets the RX AC CM spec then we can
allow the transmitter AC CM noise to pass.
Table 2-10. Intel® Itanium® Processor 9500 Series Transmitter and Receiver Parameter
Values for Intel® QPI at 6.4 GT/s (Sheet 1 of 2)
Symbol
Parameter
Min
900
Nom
Max
1400
Unit
Notes
V
Z
Transmitter differential swing
mV
1
Tx-diff-pp-pin
DC resistance of Tx terminations
at half the single ended swing
37.4
37.4
0.23
50
Ω
TX_LOW_CM_DC
RX_LOW_CM_DC
Tx-cm-dc-pin
(which is usually 0.25*V
Tx-diff-pp-
) bias point
pin
Z
V
DC resistance of Rx terminations
at half the single ended swing
50
Ω
(which is usually 0.25*V
pin
Tx-diff-pp-
) bias point
Transmitter output DC common
mode, defined as average of V
0.27
Fraction of
4
V
D+
Tx-diff-pp-pin
and V
D-
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
35
Electrical Specifications
Table 2-10. Intel® Itanium® Processor 9500 Series Transmitter and Receiver Parameter
Values for Intel® QPI at 6.4 GT/s (Sheet 2 of 2)
Symbol
Parameter
Min
Nom
Max
Unit
Notes
V
Transmitter output AC common
-0.0375
0.0375
Fraction of
Tx-diff-pp-pin
2
Tx-cm-ac-pin
mode, defined as ((V
+ V )/2 -
V
D+
D-
V
)
Tx-cm-dc-pin
TX
TX
Average of absolute UI-UI jitter
-0.06
0.06
UI
UI
duty-pin
UI-UI jitter measured at Tx output -0.085
pins with 1E-7 probability.
0.085
3
jitUI-UI-1E-7-pin
jitUI-UI-1E-9-pin
clk-acc-jit-N_UI-1E-7
TX
TX
UI-UI jitter measured at Tx output -0.09
pins with 1E-9 probability.
0.09
0.15
UI
UI
p-p accumulated jitter out of
transmitter over 0 <= n <= N UI
where N=12, measured with 1E-7
probability.
0
TX
p-p accumulated jitter out of
transmitter over 0 <= n <= N UI
where N=12, measured with 1E-9
probability.
0
0.17
UI
clk-acc-jit-N_UI-1E-9
Tx-data-clk-skew-pin
T
Delay of any data lane relative to
clock lane, as measured at Tx
output
-0.5
0.5
UI
V
Voltage eye opening at the end of 155
Tx+ channel for any data or clock
channel measured with a
cumulative probability of 1E-9
(UI).
1400
mV
2, 5
Rx-diff-pp-pin
T
T
Timing eye opening at the end of
Tx+ channel for any data or clock
channel measured with a
0.61
1
4
UI
UI
Rx-diff-pp-pin
cumulative probability of 1E-9 (UI)
Delay of any data lane relative to
the clock lane, as measured at the
end of Tx+ channel. This
-1
Rx-data-clk-skew-pin
parameter is a collective sum of
effects of data clock mismatches
in Tx and on the medium
connecting Tx and Rx.
V
V
Forward CLK Rx input voltage
sensitivity (differential pp)
150
350
mV
mV
Rx-CLK
DC common mode ranges at the
Rx input for any data or clock
channel
90
Rx-cm-dc-pin
V
AC common mode ranges at the
Rx input for any data or clock
channel, defined as:
-50
50
mV
Rx-cm-ac-pin
((V
+ V /2 - V
)
RX-cm-dc-pin
D+
D-
Notes:
1.
1300 mVpp swing is recommended when CPU to CPU or CPU to IOH length is within 2” of PDG max trace
length. Note that default value is 1200 mVpp.
2.
Measure AC CM noise at the TX and decimate to its spectral components. For all spectral components above
3.2 GHz, apply the attenuation of the channel at the appropriate frequency. If the resultant AC CM at the
receiver is met after taking out the appropriate spectral components meets the RX AC CM spec then we can
allow the transmitter AC CM noise to pass.
3.
4.
5.
Measured with neighboring lines being quiet and the remaining lines toggling PRBS patterns.
DC CM can be relaxed to 0.20 and 0.30 Vdiffp-p swing if RX has wide DC common mode range.
Based on transmitting a PRBS pattern.
®
®
36
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
®
®
2.4.3
Intel Itanium Processor 9500 Series Processor
®
Requirements for Intel SMI Specifications for 6.4 GT/s
This section defines the high-speed differential point-to-point signaling link for Intel®
SMI for the Intel® Itanium® Processor 9500 Series. The link consists of a transmitter
and a receiver and the interconnect between them. The specifications described in this
section covers 6.4 Gb/s operation. The parameters for Intel® SMI at 6.4 GT/s and
lower are captured in Table 2-11 and the PLL specification for transmit and receive are
captured in Table 2-12.
Table 2-11. Intel® Itanium® Processor 9500 Series Transmitter and Receiver Parameter
Values for Intel® SMI at 6.4 GT/s and lower (Sheet 1 of 2)
Symbol
Parameter
Min
Nom
Max
1200
Unit
Notes
V
Z
Transmitter differential swing
800
mV
Tx-diff-pp-pin
DC resistance of Tx terminations at half
the single ended swing (which is usually
37.4
50
Ω
TX_LOW_CM_DC
0.25*V
) bias point
Tx-diff-pp-pin
Z
DC resistance of Rx terminations at half
the single ended swing (which is usually
37.4
50
Ω
RX_LOW_CM_DC
0.25*V
) bias point
Tx-diff-pp-pin
V
V
Transmitter differential swing using a CLK 0.9*min(VTx-
max(VTxdiff mV
-pp-pin)
1
Tx-diff-pp-CLK-pin
Tx-cm-dc-pin
like pattern
diff-pp-pin)
Transmitter output DC common mode,
0.23
0.27
Fraction of
V
3
defined as average of V
and V
D+
D-
Tx-diff-pp-
pin
V
Transmitter output AC common mode,
defined as ((V + V )/2 - V
-0.0375
0
0.0375
0.018
Fraction of
Tx-diff-pp-
pin
UI
Tx-cm-ac-pin
)
V
D+
D-
Tx-cm-dc-pin
TX
This is computed as absolute difference
duty-UI-pin
between average value of all UI with that
of average of odd UI, which in magnitude
would equal absolute difference between
average of all UI and average of all even
UI.
Rj value of 1-UI jitter. With X-talk off, but
on-die system like noise present. This
extraction is to be done after software
correction of DCD
0
0.008
UI
2
TX1UI-Rj-NoXtalk-pin
pp Dj value of 1-UI jitter. With X-talk off,
but on-die system like noise present.
-0.01
0
0.01
UI
UI
2
2
TX1UI-Dj-NoXtalk--pin
TXN-UI-Rj-NoXtalkpin
Rj value of N-UI jitter. With X-talk off, but
on-die system like noise present. Here 1
< N < 9.This extraction is to be done
after software correction of DCD
0.012
pp Dj value of N-UI jitter. With X-talk off,
but on-die system like noise present.
Here 1 < N < 9.Dj here indicated Djdd of
dual-dirac fitting, after software
correction of DCD
-0.04
0.04
0.2
UI
2
TXN-UI-Dj-NoXtalkpin
T
T
Delay of any data lane relative to clock
lane, as measured at Tx output
-0.5
-1
0.5
3.5
UI
UI
Tx-data-clk-skew-pin
Delay of any data lane relative to the
clock lane, as measured at the end of Tx+
channel. This parameter is a collective
sum of effects of data clock mismatches
in Tx and on the medium connecting Tx
and Rx.
Rx-data-clk-skew-pin
V
Forward CLK Rx input voltage sensitivity
(differential pp)
150
mV
Rx-CLK
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
37
Electrical Specifications
Table 2-11. Intel® Itanium® Processor 9500 Series Transmitter and Receiver Parameter
Values for Intel® SMI at 6.4 GT/s and lower (Sheet 2 of 2)
Symbol
Parameter
Min
Nom
Max
Unit
Notes
Any data lane Rx input voltage
100
mV
UI
VRx-Vmargin
(differential pp) measured at BER=1E-9
Timing width for any data lane using
repetitive patterns and clean forwarded
CLK, measured at BER=1E-9
0.8
TRx-Tmargin
V
V
DC common mode ranges at the Rx input 125
for any data or clock channel, defined as
average of VD+ and VD-.
350
50
mV
mV
Rx-cm-dc-pin
AC common mode ranges at the Rx input -50
for any data or clock channel, defined as:
Rx-cm-ac-pin
((V
+ V /2 - V
)
RX-cm-dc-pin
D+
D-
Notes:
1.
This is the swing specification for the forwarded CLK output. Note that this specification will also have to be suitably de-
embedded for package/PCB loss to translate the value to the pad, since there is a significant variation between traces in a
setup.
2.
While the X-talk is off, on-die noise similar to that occurring with all the transmitter and receiver lanes toggling will still need
to be present. When a socket is not present in the transmitter measurement setup, in many cases the contribution of the
cross-talk is not significant or can be estimated within tolerable error even with all the transmitter lanes sending patterns.
Therefore for all Tx measurements, use of a socket should be avoided. The contribution of cross-talk may be significant and
should be done using the same setup at Tx and compared against the expectations of full link signaling. Note that there may
be cases when one of Dj and Rj specs is met and another violated in which case the signaling analysis should be ran to
determine link feasibility.
3.
DC CM can be relaxed to 0.20 and 0.30 Vdiffp-p swing if RX has wide DC common mode range.
Table 2-12. PLL Specification for TX and RX
Symbol
Parameter
Min
Max
16
Units
Notes
F
-3dB bandwidth
Jitter Peaking
4
MHz
dB
PLL-BW_TX-RX
JitPk
3
TX-RX
2.5
Processor Absolute Maximum Ratings
Table 2-13 specifies absolute maximum and minimum ratings for the Intel® Itanium®
Processor 9300 Series. Within operational maximum and minimum limits, the
processor functionality and long-term reliability can be expected. The processor
maximum ratings listed in Table 2-13 are applicable for the 130 W, 155 W, and 185 W
parts.
Table 2-14 specifies absolute maximum and minimum ratings for the Intel® Itanium®
Processor 9500 Series. Within operational maximum and minimum limits, the
processor functionality and long-term reliability can be expected. The processor
maximum ratings listed in Table 2-14 are applicable for the 130 W and 170 W parts.
At conditions outside operational maximum ratings, but within absolute maximum and
minimum ratings, neither functionality nor long-term reliability can be expected. If a
device is returned to conditions within operational maximum and minimum ratings
after having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
®
®
38
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time, then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
2.5.1
Intel® Itanium® Processor 9300 Series Absolute
Maximum Ratings
Table 2-13. Intel® Itanium® Processor 9300 Series Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Notes
V
V
V
V
V
Processor core supply voltage with respect to VSS
Processor uncore supply voltage with respect to VSS
Processor Analog Supply Voltage with respect to VSS
Processor I/O Supply Voltage with respect to VSS
Processor 3.3 V Supply Voltage with respect to VSS
–0.3
–0.3
–0.3
–0.3
-0.3
1.55
1.55
1.89
1.55
3.465
V
V
V
V
V
1,2
1,2
1,2
1,2
1,2
CCCORE
CCUNCORE
CCA
CCIO
CC33_SM
Notes:
1.
2.
For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must be satisfied.
Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 2.6.3. Excessive
overshoot or undershoot on any signal will likely result in permanent damage to the processor.
2.5.2
Intel® Itanium® Processor 9500 Series Absolute
Maximum Ratings
Table 2-14. Intel® Itanium® Processor 9500 Series Processor Absolute Maximum Ratings
Notes
Symbol
Parameter
Min
Max
Units
V
V
V
V
V
Processor core supply voltage with respect to VSS
Processor uncore supply voltage with respect to VSS
Processor Analog Supply Voltage with respect to VSS
Processor I/O Supply Voltage with respect to VSS
Processor 3.3 V Supply Voltage with respect to VSS
-0.3
-0.3
-0.3
-0.3
-0.3
1.42
1.42
1.89
1.55
3.465
V
V
V
V
V
1,2
1,2
1,2
1,2
1,2
CCCORE
CCUNCORE
CCA
CCIO
CC33_SM
Notes:
1.
2.
For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must be satisfied.
Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 2.6.4. Excessive
overshoot or undershoot on any signal will likely result in permanent damage to the processor.
2.6
Processor DC Specifications
Table 2-15 through Table 2-35 list the DC specifications for the Intel® Itanium®
Processor 9300 Series and 9500 Series and are valid only while meeting specifications
for case temperature, clock frequency, and input voltages.
The following notes apply:
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
39
Electrical Specifications
• Unless otherwise noted, all specifications in the tables apply to all frequencies
• For the Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor
9500 Series, these specifications are based on characterized data from silicon
measurements.
®
®
2.6.1
Flexible Motherboard Guidelines for the Intel Itanium
Processor 9300 Series
The Flexible Motherboard (FMB) guidelines are estimates of the maximum ratings that
the processor will have over certain time periods. The ratings are only estimates as
actual specifications for future processors may differ. The processor may or may not
have specifications equal to the FMB value in the foreseeable future.
Table 2-15 defines the FMB voltage specification values applied to the 130W, and
155W/185W Intel® Itanium® Processor 9300 Series stock-keeping units (SKUs).
Current specifications are identified for each processor SKU separately in Table 2-16
through Table 2-17.
Table 2-18 defines the FMB voltage specification values applied to the 130 W and
170 W SKUs for the Intel® Itanium® Processor 9500 Series. Current specifications are
identified for each processor SKU separately in Table 2-19.
Table 2-15. FMB Voltage Specifications for the Intel® Itanium® Processor 9300 Series
Symbol
Parameter
VCCCORE VID Range
Min
0.8
0.8
Typ
1.1
1.1
Max
1.35
1.35
Units
Notes
VID
V
V
Range
UVID
VCCUNCORE VID Range
Range
VCCUNCORE
VCCCORE
Processor uncore supply voltage
Processor core supply voltage
Processor cache supply voltage
VID step size during transition
See Table 2-20 and Figure 2-10
See Table 2-21 and Figure 2-11
See Table 2-22 and Figure 2-12
± ±12.5
V
V
2,1
2,3,4
5
VCCCACHE
VID Transition
V
mV
VID_DCshift
VCCIO
Total allowable DC load line shift from VID
steps.
-450
mV
V
6
7
Processor I/O supply voltage at die
including all AC and DC
1.08
0
1.15
1.22
50
VCCIO
Processor I/O supply voltage (high
frequency AC p-p noise at die)
mV
V
VCCIO
Processor I/O supply voltage at package
pin including all AC and DC
1.147
1.764
1.175
1.203
8
VCCA
VCCA
Processor analog supply voltage (DC spec)
1.8
1.8
1.836
V
Processor analog supply voltage (AC
tolerance for noise at scope full
bandwidth)
± 25
mV
9, 10
9, 11
VCCA
VCCA
Processor analog supply voltage (AC
tolerance for noise > 1MHz)
1.8
1.8
3.3
± 15
mV
V
Processor analog supply voltage (Total =
DC spec + AC tolerance)
1.739
3.135
1.861
3.465
VCC33_SM
3.3 V supply voltage
V
Notes:
1. The voltage specification requirements are measured across the VCCUNCORESENSE and VSSUNCORESENSE pins using an
oscilloscope set to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 mOhms minimum impedance
at the processor socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled into the scope probe.
®
®
40
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
2. These voltages are target only. A variable voltage source should exist on systems in the event that a different voltage is required.
See Ararat Voltage Regulator Module Design Guide for more information.
3. Uncore, Core, and Cache voltage and Current Rating are at the Package Pad.
4. The voltage specification requirements are measured across the VCCCORESENSE and VSSCORESENSE pins using an oscilloscope
set to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 MOhm minimum impedance at the processor
socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is
not coupled into the scope probe.
5. The voltage specification requirements are measured across the VCCCACHESENSE and VSSCACHESENSE pins using an
oscilloscope set to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 mOhms minimum impedance
at the processor socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled into the scope probe.
6. Warm boot reset, only in downward direction.
7. Min and Max range is spec at the die for both VCCIO. This range includes 50 mV p-p AC noise. It also includes any DC and AC
tolerances at package pin.
8. The FMB remote sense tolerance is ±2.5% for DC to 20 MHz at the package, where ±1.5% is allotted for a DC to 1 MHz range
and an additional ±1% for 1 MHz to 20 MHz. Similarly, ±6.4% is allotted for DC to 20 MHz at the die. It is expected that VCCIO
regulators meet ±1.5% at the remote sense location based on the general remote sense termination point location as described
in Figure 2-16, VR Sense Point (Representation). For future processor compatibility, it is strongly recommended that the platform
query the PIROM to assure VCCIO is set to the appropriate level prior to powering up the VCCIO supply.
9. All voltage regulation measurements taken at remote sense termination points.
10.For peak-to-peak Ripple and Noise (R&N) measured with full bandwidth (BW) of the scope (Min 1 GHz BW scope is required):
set scope diff probe and the scope at full BW (capture waveform A, channel 1).
11.For peak-to-peak Ripple and Noise (R&N) measured above 1 MHz:
Step 1 = set both: scope diff probe and/or the scope at 1 MHz BW limit (capture waveform B, channel 2).
Step 2 = calculate A-B (use scope Math function: subtract channel 1 - channel 2).
Table 2-16. FMB 130W Current Specifications for the Intel® Itanium® Processor 9300
Series
Symbol
Parameter
Max
Units
Notes
I
I
for core
CC
151
A
CC_CORE
I
I
Thermal Design Current for Core
Max Load step for core
100
95
A
A
1
2
CC_CORE_TDC
CC_CORE_STEP
d
Slew rate for core at Ararat output
154
A/us
ICC_CORE/dt
I
ICC for uncore
50
A
CC_UNCORE
I
I
Thermal Design Current for Uncore
Max Load step for uncore
43
22
75
A
A
3
4
CC_UNCORE_TDC
CC_UNCORE_STEP
dI
Slew rate for uncore at Ararat output
A/us
CC_UNCORE/dt
I
I
ICC for processor I/O
22
4
A
A
5
CC_IO
ICC for processor Analog
CC_Analog
I
ICC33 for main supply
200
mA
CC33_SM
Notes:
1. ICC_CORE_TDC is the sustained (DC equivalent) current that the processor core is capable of drawing indefinitely and should be
used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its
temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor
and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see
the Ararat Voltage Regulator Module Design Guide for further details. The processor is capable of drawing ICC_CORE_TDC
indefinitely. Refer to Figure 2-9 for further details on the average processor current draw over various time durations. This
parameter is based on design characterization and is not tested.
2. During system power on, the pulse inrush (ICC_CORE_STEP) can be as high as 130A peak-to-peak.
3. ICC_UNCORE_TDC is the sustained (DC equivalent) current that the processor uncore is capable of drawing indefinitely and
should be used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for
monitoring its temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform
the processor and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor.
Please see the Ararat Voltage Regulator Module Design Guide for further details. The processor is capable of drawing
ICC_UNCORE_TDC indefinitely. This parameter is based on design characterization and is not tested.
4. During system power on, the pulse inrush (ICC_UNCORE_STEP) can be as high as 40A peak-to-peak.
5. The ICC_IO current specification applies to the total current from VCCIO pins.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
41
Electrical Specifications
Table 2-17. FMB 155W/185W Current Specifications for the Intel® Itanium® Processor
9300 Series
Symbol
Parameter
Max
Units
Notes
I
I
for core
CC
180
A
CC_CORE
I
I
Thermal Design Current for Core
Max Load step for core
131
95
A
A
1
2
CC_CORE_TDC
CC_CORE_STEP
d
Slew rate for core at Ararat output
154
A/us
ICC_CORE/dt
I
I
for uncore
50
A
CC_UNCORE
CC
I
I
Thermal Design Current for Uncore
Max Load step for uncore
43
22
75
A
A
3
4
CC_UNCORE_TDC
CC_UNCORE_STEP
dI
Slew rate for uncore at Ararat output
A/us
CC_UNCORE/dt
I
I
I
I
for processor I/O
22
4
A
A
5
CC_IO
CC
CC
for processor Analog
CC_Analog
I
I
for main supply
200
mA
CC33_SM
CC33
Notes:
1. ICC_CORE_TDC is the sustained (DC equivalent) current that the processor core is capable of drawing indefinitely and should be
used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its
temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor
and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see
the Ararat Voltage Regulator Module Design Guide for further details. The processor is capable of drawing ICC_CORE_TDC
indefinitely. Refer to Figure 2-9 for further details on the average processor current draw over various time durations. This
parameter is based on design characterization and is not tested.
2. During system power on, the pulse inrush (ICC_CORE_STEP) can be as high as 130A peak-to-peak.
3. ICC_UNCORE_TDC is the sustained (DC equivalent) current that the processor uncore is capable of drawing indefinitely and
should be used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for
monitoring its temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform
the processor and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor.
Please see the Ararat Voltage Regulator Module Design Guide for further details. The processor is capable of drawing
ICC_UNCORE_TDC indefinitely. This parameter is based on design characterization and is not tested.
4. During system power on, the pulse inrush (ICC_UNCORE_STEP) can be as high as 40A peak-to-peak.
5. The ICC_IO current specification applies to the total current from VCCIO pins.
Figure 2-9. Processor ICC_CORE Load Current versus Time
IMax
ITDC
0.01
0.1
1
10
100 1000
Time Duration (us)
®
®
42
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
®
®
2.6.2
Flexible Motherboard Guidelines for the Intel Itanium
Processor 9500 Series
The Flexible Motherboard (FMB) guidelines are estimates of the maximum ratings that
the processor will have over certain time periods. The ratings are only estimates as
actual specifications for future processors may differ. The processor may or may not
have specifications equal to the FMB value in the foreseeable future.
Table 2-18 defines the FMB voltage specification values applied to the 130 W and
170 W SKUs for the Intel® Itanium® Processor 9500 Series. Current specifications are
identified for each processor SKU separately in Table 2-19.
Table 2-18. FMB Voltage Specifications for the Intel® Itanium® Processor 9500 Series
Symbol
Parameter
VCCCORE VID Range
Min
Typ
1.105
0
Max
Units
Notes
1
1
1
1
CVID
0.800
1.22
V
V
V
V
Range
Boot
CVID
UVID
UVID
VCCCORE VID default value
VCCUNCORE VID Range
0.800
0.975
1.0
1.19
Range
Boot
VCCUNCORE VID default value
VCCUNCORE
VCCCORE
Processor uncore supply voltage
Processor core supply voltage
VID step size during transition
See Table 2-23 and Figure 2-15
See Table 2-24 and Figure 2-14
± ±5
V
V
2, 1
2, 3, 4
VID Transition
mV
VID_DCshift
VCCIO
Total allowable DC load line shift from VID
steps.
-420
mV
V
5
6
Processor I/O supply voltage at die
including all AC and DC
1.011
1.050
1.094
35
VCCIO
Processor I/O supply voltage (high
frequency AC p-p noise at die)
mV
V
VCCIO
Processor I/O supply voltage at package
pin including all AC and DC
1.026
1.764
1.075
1.088
7
8
VCCA
VCCA
Processor analog supply voltage (DC spec)
1.8
1.8
1.836
V
Processor analog supply voltage (AC
tolerance for noise at scope full
bandwidth)
± 25
mV
8, 9
VCCA
Processor analog supply voltage (AC
tolerance for noise > 1MHz)
1.8
1.8
± 15
1.861
10
mV
V
9, 10
VCCA
Processor analog supply voltage (Total =
DC spec + AC tolerance)
1.739
1
VCCA Ramp
Min time allowed to ramp VCCA from 10%
to 90% typical value
ms
V
VCC33_SM
3.3 V supply voltage
3.135
3.3
3.465
Notes:
1. The voltage specification requirements are measured across the VCCUNCORESENSE and VSSUNCORESENSE pins using an
oscilloscope set to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 mOhms minimum impedance
at the processor socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled into the scope probe.
2. These voltages are target only. A variable voltage source should exist on systems in th e event that a different voltage is required.
See the Ararat II Voltage Regulator Module Design Guide for more information.
3. Uncore and Core voltage and Current Rating are at the Package Pad.
4. The voltage specification requirements are measured across the VCCCORESENSE and VSSCORESENSE pins using an oscilloscope
set to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 mOhms minimum impedance at the
processor socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled into the scope probe.
5. Warm boot reset, only in downward direction.
6. Min and Max range is spec at the die for VCCIO. This range includes 35 mV p-p AC noise. It also includes any DC and AC
tolerances at package pin.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
43
Electrical Specifications
7. The FMB remote sense tolerance is ±2.5% for DC to 20 MHz at the package, where ±1.5% is allotted for a DC to 1 MHz range
and an additional ±1.0% for 1 MHz to 20 MHz. Similarly, ±6.4% is allotted for DC to 20 MHz at the die. It is expected that VCCIO
regulators meet ±1.5% at the remote sense location based on the general remote sense termination point location as described
in Figure 2-16 VR Sense Point (Representation). For future processor compatibility, it is strongly recommended that the platform
query the PIROM to assure VCCIO is set to the appropriate level prior to powering up the VCCIO supply.
8. All voltage regulation measurements taken at remote sense termination points.
9. For peak-to-peak Ripple and Noise (R&N) measured with full bandwidth (BW) of the scope (Min 1 GHz BW scope is required):
set scope diff probe and the scope at full BW (capture waveform A, channel 1).
10.For peak-to-peak Ripple and Noise (R&N) measured above 1 MHz:
Step 1 = set both: scope diff probe and/or the scope at 1 MHz BW limit (capture waveform B, channel 2)
Step 2 = calculate A-B (use scope Math function: subtract channel 1 - channel 2).
Table 2-19. FMB 170W and 130W Current Specifications for the Intel® Itanium® Processor
9500 Series
Symbol
Parameter
Max
Min
Units
Notes
I
I
I
I
for core
CC
35.0
30.0
A
A
1
1, 2
1, 3
1
CC_CORE
Thermal Design Current for Core
Max Load step for core
CC_CORE_TDC
CC_CORE_STEP
14.62
34.4
A
d
Slew rate for core at Ararat output
A/us
ICC_CORE/dt
I
I
for uncore
80.0
A
CC_UNCORE
CC
I
I
Thermal Design Current for Uncore
Max Load step for uncore
75.0
30.4
A
A
4
5
CC_UNCORE_TDC
CC_UNCORE_STEP
dI
Slew rate for uncore at Ararat output
168.0
A/us
CC_UNCORE/dt
I
I
for processor I/O
17.2
54.0
A
6
CC_IO
CC
d
Slew rate for IO at the package pin
A/us
ICC_IO/dt
I
Max Load step for max slew rate
Time between steps
5.1
A
7
7
CC_IO_STEP
T
4.7
us
CC_IO_STEP
CC_Analog
CC33_SM
I
I
I
I
for processor Analog
4
A
CC
for main supply
200
mA
CC33
Notes:
1. Values per core pair.
2. ICC_CORE_TDC is the sustained (DC equivalent) current that the processor core is capable of drawing indefinitely and should be
used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its
temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor
and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see
the Ararat II Voltage Regulator Module Design Guide for further details. The processor is capable of drawing ICC_CORE_TDC
indefinitely.
3. During system power on, the pulse inrush (ICC_CORE_STEP) can be as high as 35A peak-to-peak.
4. ICC_UNCORE_TDC is the sustained (DC equivalent) current that the processor uncore is capable of drawing indefinitely and
should be used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for
monitoring its temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform
the processor and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor.
Please see the Ararat II Voltage Regulator Module Design Guide for further details. The processor is capable of drawing
ICC_UNCORE_TDC indefinitely. This parameter is based on design characterization and is not tested.
5. During system power on, the pulse inrush (ICC_UNCORE_STEP) can be as high as 40A peak-to-peak.
6. The ICC_IO current specification applies to the total current from VCCIO pins.
®
®
7. The max load step represents the maximum current required during Intel QPI and Intel SMI port initialization. The min time
®
®
between steps represents the time between Intel QPI and Intel SMI initialization.
®
®
2.6.3
Intel Itanium Processor 9300 Series Uncore, Core, and
Cache Tolerances
2.6.3.1
Uncore Static and Transient Tolerances
Table 2-20 and Figure 2-10 specify static and transient tolerances for the uncore
outputs.
®
®
44
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-20. VCC
Static and Transient Tolerance for Intel® Itanium® Processor 9300
UNCORE
Series
Uncore
Current (A)
Voltage Deviation from VID Setting (V)1,2,3,4
V
I
V
V
CC_Min
CC_UNCORE
CC_Max
CC_Typ
0
VID - 0
VID - 0.02
VID - 0.04
VID - 0.06
VID - 0.08
VID - 0.1
VID - 0.04
VID - 0.06
VID - 0.08
VID - 0.1
5
VID - 0.02
VID - 0.04
VID - 0.06
VID - 0.08
VID - 0.1
VID - 0.12
VID - 0.14
VID - 0.16
VID - 0.18
VID - 0.2
10
15
20
25
30
35
40
45
50
VID - 0.12
VID - 0.14
VID - 0.16
VID - 0.18
VID - 0.2
VID - 0.12
VID - 0.14
VID - 0.16
VID - 0.18
VID - 0.2
VID - 0.22
VID - 0.24
VID - 0.22
Notes:
1.
2.
3.
The V
and V
load lines represent static and transient limits.
CC_MAX
CC_MIN
This table is intended to aid in reading discrete points on Figure 2-10.
The load lines specify voltage limits at the die measured at the V
Voltage regulation feedback for voltage regulator circuits must be taken from processor V and V pins.
and V
pins.
CCUNCORESENSE
SSUNCORESENSE
CC
SS
Refer to the Ararat Voltage Regulator Module Design Guide for socket load line guidelines and VR
implementation.
4.
V
(max)=VID-R *I -5 mV; V (min)=VID-R *I -35mV; R =4 mW.
DC ll CC DC ll CC ll
Figure 2-10. VCC
Static and Transient Tolerance for Intel® Itanium® Processor 9300
UNCORE
Series
VccUNCORE Tolerance Bands
AC max (V)
DC max (V)
Typical Vcc (V)
DC min (V)
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
-0.14
-0.16
-0.18
-0.20
-0.22
-0.24
AC min (V)
0
5
10
15
20
25
Icc (A)
30
35
40
45
50
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
45
Electrical Specifications
2.6.3.2
Core Static and Transient Tolerances
Table 2-21 and Figure 2-11 specify static and transient tolerances for the core outputs.
Table 2-21. VCC
Static and Transient Tolerance for Intel® Itanium® Processor 9300
CORE
Series (Sheet 1 of 2)
Core Current (A)
Voltage Deviation from VID Setting (V)1,2,3,4
V
I
V
V
CC_Min
CC_CORE
CC_Max
CC_Typ
0
VID - 0
VID - 0.02
VID - 0.024
VID - 0.029
VID - 0.033
VID - 0.037
VID - 0.041
VID - 0.046
VID - 0.05
VID - 0.04
VID - 0.044
VID - 0.049
VID - 0.053
VID - 0.057
VID - 0.061
VID - 0.066
VID - 0.07
5
VID - 0.004
VID - 0.009
VID - 0.013
VID - 0.017
VID - 0.021
VID - 0.026
VID - 0.03
10
15
20
25
30
35
40
VID - 0.034
VID - 0.038
VID - 0.043
VID - 0.047
VID - 0.051
VID - 0.055
VID - 0.06
VID - 0.054
VID - 0.058
VID - 0.063
VID - 0.067
VID - 0.071
VID - 0.075
VID - 0.08
VID - 0.074
VID - 0.078
VID - 0.083
VID - 0.087
VID - 0.091
VID - 0.095
VID - 0.1
45
50
55
60
65
70
75
VID - 0.064
VID - 0.068
VID - 0.072
VID - 0.077
VID - 0.081
VID - 0.085
VID - 0.089
VID - 0.094
VID - 0.098
VID - 0.102
VID - 0.106
VID - 0.111
VID - 0.115
VID - 0.119
VID - 0.123
VID - 0.128
VID - 0.132
VID - 0.136
VID - 0.14
VID - 0.084
VID - 0.088
VID - 0.092
VID - 0.097
VID - 0.101
VID - 0.105
VID - 0.109
VID - 0.114
VID - 0.118
VID - 0.122
VID - 0.126
VID - 0.131
VID - 0.135
VID - 0.139
VID - 0.143
VID - 0.148
VID - 0.152
VID - 0.156
VID - 0.16
VID - 0.104
VID - 0.108
VID - 0.112
VID - 0.117
VID - 0.121
VID - 0.125
VID - 0.129
VID - 0.134
VID - 0.138
VID - 0.142
VID - 0.146
VID - 0.151
VID - 0.155
VID - 0.159
VID - 0.163
VID - 0.168
VID - 0.172
VID - 0.176
VID - 0.18
80
85
90
95
100
105
110
115
120
125
130
135
140
145
150
155
160
165
®
®
46
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-21. VCC
Static and Transient Tolerance for Intel® Itanium® Processor 9300
CORE
Series (Sheet 2 of 2)
Core Current (A)
Voltage Deviation from VID Setting (V)1,2,3,4
V
I
V
V
CC_Min
CC_CORE
CC_Max
CC_Typ
170
175
180
VID - 0.145
VID - 0.149
VID - 0.165
VID - 0.169
VID - 0.185
VID - 0.189
Notes:
1.
2.
3.
The V
and V
load lines represent static and transient limits.
CC_MAX
CC_MIN
This table is intended to aid in reading discrete points on Figure 2-11.
The load lines specify voltage limits at the die measured at the V
and V
pins.
SSCORESENSE
CCCORESENSE
Voltage regulation feedback for voltage regulator circuits must be taken from processor V and V pins.
CC
SS
Refer to the Ararat Voltage Regulator Module Design Guide for socket load line guidelines and VR
implementation.
4.
V
(max)=VID-R *I -4 mV;V (nom)=VID-R *I -19 mV;V (min)=VID-R *I -34mV; R =0.85 mΩ.
DC ll CC DC ll CC DC ll CC ll
Figure 2-11. VCC
Static and Transient Tolerance for Intel® Itanium® Processor 9300
CORE
Series
VccCORE Tolerance Bands
AC max (V)
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
-0.14
-0.16
-0.18
-0.20
DC max (V)
Typical Vcc (V)
DC min (V)
AC min (V)
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180
Icc (A)
2.6.3.3
Cache Static and Transient Tolerances
Table 2-22 and Figure 2-12 specify static and transient tolerances for the cache
outputs.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
47
Electrical Specifications
Table 2-22. VCC
Static and Transient Tolerance for Intel® Itanium® Processor 9300
CACHE
Series
Cache Current (A)
Voltage Deviation from VID Setting (V)1,2,3,4
V
I
V
V
CC_Min
CC_CACHE
CC_Max
CC_Typ
0
VID - 0
VID - 0.02
VID - 0.037
VID - 0.055
VID - 0.072
VID - 0.089
VID - 0.106
VID - 0.124
VID - 0.141
VID - 0.158
VID - 0.175
VID - 0.193
VID - 0.21
VID - 0.04
VID - 0.057
VID - 0.075
VID - 0.092
VID - 0.109
VID - 0.126
VID - 0.144
VID - 0.161
VID - 0.178
VID - 0.195
VID - 0.213
VID - 0.23
5
VID - 0.017
VID - 0.035
VID - 0.052
VID - 0.069
VID - 0l.086
VID - 0.104
VID - 0.121
VID - 0.138
VID - 0.155
VID - 0.173
VID - 0.19
10
15
20
25
30
35
40
45
50
55
Notes:
1.
2.
3.
The V
and V
load lines represent static and transient limits.
CC_MIN
CC_MAX
This table is intended to aid in reading discrete points on Figure 2-12.
The load lines specify voltage limits at the die measured at the V
and V
pins.
SSCACHESENSE
CCCACHESENSE
Voltage regulation feedback for voltage regulator circuits must be taken from processor V and V pins.
CC
SS
Refer to the Ararat Voltage Regulator Module Design Guide for socket load line guidelines and VR
implementation.
4.
V
(max)=VID-R *I -5 mV; V (min)=VID-R *I -35 mV; R =3.45 mW.
DC ll CC DC ll CC ll
Figure 2-12. VCC
Static and Transient Tolerance for Intel® Itanium® Processor 9300
CACHE
Series
V ccC AC H E To lerance B an ds
A C m ax (V )
DC m ax (V )
Typical V cc (V )
DC m in (V )
0.0 0
-0.0 2
-0.0 4
-0.0 6
-0.0 8
-0.1 0
-0.1 2
-0.1 4
-0.1 6
-0.1 8
-0.2 0
-0.2 2
A C m in (V )
0
5
10
15
20
25
Icc (A)
3 0
35
40
45
5 0
®
®
48
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
®
®
2.6.4
Intel Itanium Processor 9500 Series Uncore and Core
Tolerances
2.6.4.1
Uncore Static and Transient Tolerances
Table 2-23 and Figure 2-13 specify static and transient tolerances for the uncore
outputs.
Table 2-23. VCC
Static and Transient Tolerance for the Intel® Itanium® Processor
UNCORE
9500 Series
Uncore
Voltage Deviation from VID Setting (V)1,2,3,4
V
Current (A)
I
V
V
CC_Min
CC_UNCORE
CC_Max
CC_Typ
0
VID + 0.015
VID + 0.00875
VID + 0.0025
VID - 0.00375
VID - 0.01
VID
VID - 0.015
VID - 0.02125
VID - 0.0275
VID - 0.03375
VID - 0.04
5
VID - 0.00625
VID - 0.0125
VID - 0.01875
VID - 0.025
10
15
20
25
30
35
40
45
50
55
60
65
70
VID - 0.01625
VID - 0.0225
VID - 0.02875
VID - 0.035
VID - 0.03125
VID - 0.0375
VID - 0.04375
VID - 0.05
VID - 0.04625
VID - 0.0525
VID - 0.05875
VID - 0.065
VID - 0.04125
VID - 0.0475
VID - 0.05375
VID - 0.06
VID - 0.05625
VID - 0.0625
VID - 0.06875
VID - 0.075
VID - 0.07125
VID - 0.0775
VID - 0.08375
VID - 0.09
VID - 0.06625
VID - 0.0725
VID - 0.08125
VID - 0.0875
VID - 0.09625
VID - 0.1025
Notes:
1. The V
and V
load lines represent static and transient limits.
CC_MAX
CC_MIN
2. This table is intended to aid in reading discrete points on Figure 2-14.
3. The load lines specify voltage limits at the die measured at the VCCUNCORESENSE and VSSUNCORESENSE
pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS
pins. Refer to the Ararat II Voltage Regulator Module Design Guide for socket load line guidelines and VR
implementation.
4. V (max)=VID-R *I +15 mV; V (min)=VID-R *I -15 mV; R =1.25 mOhm.
DC
ll CC
DC
ll CC
ll
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
49
Electrical Specifications
Figure 2-13. VCC
Static and Transient Tolerance for the Intel® Itanium® Processor
UNCORE
9500 Series
Figure 2-14. VCC
Load Line for the Intel® Itanium® Processor 9500 Series
UNCORE
VccUnCore Tolerance Band
VccUnCore ACMax (V)
VccUnCore DCMax (V)
Normalized VccUnCore (V)
VccUnCore DCMin (V)
VccUnCore ACMin (V)
0.0150
-0.0050
-0.0250
-0.0450
-0.0650
-0.0850
-0.1050
-0.1250
-0.1450
-0.1650
0
20
40
60
80
100
120
IccUnCore (A)
2.6.4.2
Core Static and Transient Tolerances
Table 2-24 and Figure 2-15 specify static and transient tolerances for the core outputs.
®
®
50
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-24. VCC
Static and Transient Tolerance for the Intel® Itanium® Processor
CORE
9500 Series
Core Current (A)
Voltage Deviation from VID Setting (V)1,2,3,4
V
I
V
V
CC_Min
CC_CORE
CC_Max
CC_Typ
0
VID + 0.015
VID + 0.005
VID - 0.005
VID - 0.015
VID - 0.025
VID - 0.035
VID - 0.045
VID
VID - 0.015
VID - 0.025
VID - 0.035
VID - 0.045
VID - 0.055
VID - 0.065
VID - 0.075
5
VID - 0.010
VID - 0.020
VID - 0.030
VID - 0.040
VID - 0.050
VID - 0.060
10
15
20
25
30
Notes:
1. The V
and V
load lines represent static and transient limits.
CC_MAX
CC_MIN
2. This table is intended to aid in reading discrete points on Figure 2-15.
3. The load lines specify voltage limits at the die measured at the VCCCORESENSE and VSSCORESENSE pins.
Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins.
Refer to the Ararat II Voltage Regulator Module Design Guide for socket load line guidelines and VR
implementation.
4. V (max)=VID-R *I +15 mV; V (nom)=VID-R *I ; V (min)=VID-R *I -15 mV; R = 2 mOhms.
DC
ll CC
DC
ll CC
DC
ll CC
ll
Figure 2-15. VCC
Load Line for the Intel® Itanium® Processor 9500 Series
CORE
VccCore[1-4] Tolerance Band
VccCore ACMax (V)
0.02
VccCore DCMax (V)
Normalized VccCore (V)
VccCore DCMin (V)
VccCore ACMin (V)
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.1
-0.11
0
5
10
15
20
25
30
35
40
45
IccCore (A)
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
51
Electrical Specifications
2.6.5
Overshoot and Undershoot Guidelines
Overshoot (or undershoot) is the value of the maximum voltage above or below VSS.
The overshoot and undershoot specifications limit transitions beyond VCCIO or VSS due
to the fast signal edge rates. The processor can be damaged by single and/or repeated
overshoot or undershoot events on any input, output, or I/O buffer if the charge is
large enough (that is, if the overshoot or undershoot is great enough). Determining the
impact of an overshoot or undershoot condition requires knowledge of the magnitude,
the pulse duration, and the activity factor (AF). Permanent damage to the processor is
the likely result of excessive overshoot or undershoot.
2.6.5.1
Overshoot/Undershoot Magnitude, Pulse Duration and Activity Factor
Magnitude describes the maximum potential difference between a signal and its voltage
reference level. For the Intel® Itanium® Processor 9300 Series and Intel® Itanium®
Processor 9500 Series, both are referenced to VSS. It is important to note that
overshoot and undershoot conditions are separate and their impact must be
determined independently.
Pulse duration describes the total amount of time that an overshoot or undershoot
event exceeds the overshoot or undershoot reference voltage. Activity factor (AF)
describes the frequency of overshoot or undershoot occurrence relative to a clock.
Since the highest frequency of assertion of a single-ended signal is every other clock,
an AF = 1 indicates that the specific overshoot or undershoot waveform occurs every
other clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot or
undershoot waveform occurs one time in every 200 clock cycles. The highest frequency
of assertion of any differential signal is every active edge of its associated clock (not
the reference clock). So, an AF = 1 indicates that the specific overshoot or undershoot
waveform occurs every cycle.
2.6.5.2
Overshoot/Undershoot Specifications
The overshoot and undershoot specifications listed in the following table specify the
allowable overshoot or undershoot for a single overshoot or undershoot event.
Table 2-25 specifies the maximum overshoot and undershoot for the Intel® Itanium®
Processor 9300 Series, while Table 2-26 specifies the maximum overshoot and under-
shoot for the Intel® Itanium® Processor 9500 Series, respectively, identifying both the
single ended and the differential signalling pins. The overshoot and undershoot values
assume an activity factor of 100% and a pulse width of 25% over the signal pulse
width. The tables also include the absolute maximum and minimum values beyond
which the processor is not guaranteed to operate properly. These values assume a
pulse width of 1% and an activity factor of 100%.
2.6.5.2.1
Overshoot and Undershoot Specifications for the Intel® Itanium® Processor
9300 Series
Table 2-25. Overshoot and Undershoot Specifications For Differential
Intel® QuickPath Interconnect and Intel® SMI and Single-Ended Signals
for the Intel® Itanium® Processor 9300 Series (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Unit
V
V
V
V
V
Overshoot for single-ended signals
Undershoot for single-ended signals
Absolute Max for single-ended signals
Absolute Min for single-ended signals
1.45
MAX-OS-SE
-0.247
-0.425
V
MIN-US-SE
1.6
V
ABSMAX-OS-SE
ABSMIN-US-SE
V
®
®
52
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-25. Overshoot and Undershoot Specifications For Differential
Intel® QuickPath Interconnect and Intel® SMI and Single-Ended Signals
for the Intel® Itanium® Processor 9300 Series (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Unit
®
®
V
V
V
V
Overshoot for Intel QPI and Intel SMI
signals
1.54
V
MAX-OS-DIFF
®
®
Undershoot for Intel QPI and Intel SMI
signals
-0.337
V
V
V
MAX-US-DIFF
®
®
Absolute Max for Intel QPI and Intel
1.7
ABSMAX-OS-DIFF
ABSMAX-US-DIFF
SMI signals
®
®
Absolute Min for Intel QPI and Intel SMI -0.525
signals
V
V
Sysclk single-ended maximum voltage
1.54
V
V
MAX_OS_SYSCLK
MIN_US_SYSCLK
Sysclk single-ended minimum voltage
-0.337
2.6.5.2.2
Overshoot and Undershoot Specifications for the Intel® Itanium® Processor
9500 Series
Table 2-26. Overshoot and Undershoot Specifications For Differential
Intel® QuickPath Interconnect and Intel® SMI and Single-Ended
Signals for the Intel® Itanium® Processor 9500 Series
Symbol
Parameter
Min
Max
Unit
V
V
V
V
V
V
Overshoot for single-ended signals
Undershoot for single-ended signals
Absolute Max for single-ended signals
Absolute Min for single-ended signals
1.36
MAX-OS-SE
-0.22
-0.32
V
MIN-US-SE
1.46
1.3
V
ABSMAX-OS-SE
ABSMIN-US-SE
MAX-OS-DIFF
V
®
®
Overshoot for Intel QPI and Intel SMI
signals
V
®
®
V
V
V
Undershoot for Intel QPI and Intel
-0.3
V
V
V
MAX-US-DIFF
SMI signals
®
®
Absolute Max for Intel QPI and Intel
SMI signals
1.4
1.3
ABSMAX-OS-DIFF
ABSMAX-US-DIFF
®
®
Absolute Min for Intel QPI and Intel
-0.4
-0.3
SMI signals
V
V
Sysclk single-ended maximum voltage
Sysclk single-ended minimum voltage
V
V
MAX_OS_SYSCLK
MIN_US_SYSCLK
2.6.6
Signal DC Specifications
Table 2-27 through Table 2-35 state the DC specifications for the single-ended signal
groups defined in Table 2-2.
Table 2-27. Voltage Regulator Signal Group DC Specifications
Symbol
Parameter
Input Low Voltage
Min
Max
Unit
Notes
V
V
V
V
0
0.4
3.6
3.6
0.4
V
V
V
V
IL
Input High Voltage
Output High Voltage
Output Low Voltage
0.8
0.8
0
IH
OH
OL
1, 2, 3, 4, 5
1, 2, 3, 4, 5
Notes:
1. Open collector and drain outputs need pull-up resistors on the motherboard.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
53
Electrical Specifications
2. These outputs can be pulled up to VCCIO or VCC_STDBY on the platform.
3. Pull-up resistance should limit current to 2 mA.
4. Actual V
and V levels are determined by pull-up resistance and supply voltage values.
OH
OL
5. These values are based on 2.2 KΩ pull-up to 3.3 V supply.
Table 2-28. Voltage Regulator Control Group DC Specification
Symbol
Parameter
Input Low Voltage
Input High Voltage
Min
Max
(VCCIO*0.67) - 0.2
VCCIO
Unit
V
Notes
V
0
IL
V
(VCCIO*0.67) + 0.2
V
IH
V
V
Output High Voltage
Output Low Voltage
V
V
1, 2, 3, 4
1, 2, 3, 4
OH
OL
Notes:
1. Open collector and drain outputs need pull-up resistors on the motherboard.
2. Actual V and V levels determined by pull-up resistance and supply voltage value. Refer to the Ararat
OH
OL
Voltage Regulator Module Design Guide or the Ararat II Voltage Regulator Module Design Guide for I max.
OL
®
®
®
®
3. See Intel Itanium 9300 Series and Intel Itanium 9500 Series Platform Design Guide for recommended
resistor values.
4. VR_THERMALERT_N is an input to the top of the package and an output from the bottom of the package. V
IH
and V levels are for the input at the top of the package, sensed by the processor; V
and V are for the
IL
OH
OL
output levels on the package pins at the bottom of the package.
Table 2-29. TAP and System Management Group DC Specifications
Symbol
Parameter
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Voltage
Min
Max
(VCCIO*0.5) - 0.2
VCCIO
Unit
Notes
V
V
V
V
0
(VCCIO*0.5) + 0.2
VCCIO-0.2
0
V
V
V
V
IL
IH
VCCIO
OH
OL
1
0.25
I
I
I
Output Low Current
16
23
mA
µA
µA
1
OL
Input Leakage Current
Output Leakage Current
–200
–1000
200
200
2, 3, 4
ILeak
OLeak
Notes:
1. With 50 W termination to VCCIO at the far end.
2. With V at the pin at 1.1 V and 0 V. System designers are advised to check the tolerance of their voltage
regulator solutions to ensure V at the pin is 1.1 V.
3. Internal weak pull-up included for TCLK.
4. Internal weak pull-up included for TRST_N, TMS and TDI.
Table 2-30. Error, FLASHROM, Power-Up, Setup, and Thermal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
V
V
Input Low Voltage
Input High Voltage
0
(VCCIO*0.67) - 0.2
VCCIO
V
V
IL
(VCCIO*0.67) + 0.2
IH
V
V
Output High Voltage
Output Low Voltage
VCCIO-0.2
0
VCCIO
0.25
V
V
OH
OL
1
I
I
I
Output Low Current
16
23
mA
µA
µA
1
2
OL
Input Leakage Current
Output Leakage Current
–1000
–1000
200
200
ILeak
OLeak
Notes:
1. With 50W termination to VCCIO at the far end.
®
®
54
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
2. With input leakage current measured at the pin with 0V and with 1.1 V supplied to the pin. System designers
are advised to check the tolerance of their voltage regulator solutions to ensure a voltage of 1.1 V at the pin.
2.6.6.1
VID_VCCCORE, VID_VCCUNCORE, and VID_VCCCACHE DC
®
®
Specifications for the Intel Itanium Processor 9300 Series
The Intel® Itanium® Processor 9300 Series processor supplies top side VID signal pins
to the Arafat Voltage Regulator Module, as shown in Table 2-31.
Table 2-31. VID_VCCCORE[6:0], VID_VCCUNCORE[6:0] and VID_VCCCACHE[5:0] DC
Specifications for the Intel® Itanium® Processor 9300 Series
Symbol
Parameter
Output High Voltage
Min
VCCIO-0.1
0
Max
VCCIO
0.1
Unit
V
Notes
V
V
1
OH
1
Output Low Voltage
V
OL
I
Output Leakage Current
–200
200
µA
1, 2
OLeak
Notes:
1. These parameters are not tested and are based on design simulations.
2. Leakage to VSS with pin held at 1.1 V and leakage to 1.1 V with pin held at VSS.
®
®
2.6.6.2
SVID Group DC Specifications for the Intel Itanium Processor 9500
Series
The Intel® Itanium® Processor 9500 Series implements a Serial VID BUS that is used
to transfer power management information between the microprocessor and the five
output voltages. Voltage levels are compliant to the VR12.0 1V TTL signaling
requirements and are shown in Table 2-32.
Table 2-32. SVID Group DC Specifications for the Intel® Itanium® Processor 9500 Series
Symbol
Parameter
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Voltage
Min
Max
(VCCIO*0.5) - 0.2
VCCIO
Unit
V
Notes
V
0
(VCCIO*0.5) + 0.2
VCCIO-0.2
0
IL
V
V
V
V
IH
OH
OL
VCCIO
V
1
0.25
V
I
I
I
Output Low Current
16
23
mA
µA
µA
1
2
OL
Input Leakage Current
Output Leakage Current
–200
–200
200
200
ILeak
OLeak
Notes:
1. With 50W termination to VCCIO at the far end.
2. With input leakage current measured at the pin with 0V and with 1.075V supplied to the pin. System designers
are advised to check the tolerance of their voltage regulator solutions to ensure Vpin of 1.1 V.
Table 2-33. SMBus and Serial Presence Detect (SPD) Bus Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
V
Input Low Voltage
0
(VCCIO*0.67) -0.2
V
V
1
1
IL
V
V
Input High Voltage
Output Low Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
(VCCIO*0.67) + 0.2
VCCIO
0.25
23
IH
0
V
1
OL
I
I
I
16
mA
µA
µA
1,2
1
OL
–1000
–1000
200
LEAK
LO
200
1
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
55
Electrical Specifications
Notes:
1.
2.
These parameters are based on design characterization and are not tested.
With 50Ω termination to VCCIO at the far end.
Table 2-34. Debug Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
V
Input Low Voltage
0
(VCCIO*0.67) - 0.2
V
V
IL
V
V
V
Input High Voltage
Output High Voltage
Output Low Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
(VCCIO*0.67) + 0.2
VCCIO
VCCIO
0.35
23
IH
VCCIO-0.2
0
V
OH
V
1
1
2
OL
I
I
I
13
mA
µA
µA
OL
–1000
–1000
200
ILeak
OLeak
200
Notes:
1. With 2 parallel 50Ω termination to VCCIO at the far end.
2. With input leakage current measured at the pin with 0V and with 1.1V supplied to the pin. System designers
are advised to check the tolerance of their voltage regulator solutions to ensure Vpin of 1.1 V.
Table 2-35. PIROM Signal Group DC Specifications
Symbol
Parameter
Input Low Voltage
Min
TYP
Max
Unit
Notes
V
V
V
-0.6
Vcc*0.7
Vcc*0.3
Vcc +0.5
0.4
2,1
2,1
2
IL
Input High Voltage
IH
Output Low Voltage (I
= 2.1 mA)
OL2
OL
V
Output Low Voltage (I
= 0.15 mA)
0.2
OL1
OL
2
I
I
Input Leakage Current
Output Leakage Current
0.1
3.0
3.0
2
2
ILeak
0.05
OLeak
Notes:
1. V (min) and V (max) are reference only and are not tested.
IL
IH
2. Applicable over recommended operating range T = -40 °C to +88 °C; Vcc = +1.7 V to +3.6 V.
®
®
56
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
2.6.7
Motherboard-Socket Specification for VR Sense Point
Figure 2-16. VR Sense Point (Representation)
FBD pins
VR Sense point
Note:
±1.5% DC (DC to 1 MHz) and ±1% AC (1 MHz to 20 MHz) specified at MB/socket.
2.7
Core and Uncore Voltage Identification
The VID_VCCCORE[6:0] and VID_VCCUNCORE[6:0] lands supply the encoding that
determine the voltage to be supplied by the VCCCORE and VCCUNCORE voltage
regulators. The VID_VCCCORE and VID_VCCUNCORE specifications for the Intel®
Itanium® Processor 9300 Series and 9500 Series are defined in the Ararat 170 Watt
Voltage Regulator Module Design Guide and Ararat II Voltage Regulator Module
Design Guide, respectively. The voltage set by the VID_VCCCORE and
VID_VCCUNCORE lands are the maximum VCCCORE and VCCUNCORE voltage allowed
by the processor.
Individual processor VID_VCCCORE and VID_VCCUNCORE values may be calibrated
during manufacturing such that two devices at the same core speed may have different
default VID_VCCCORE and VID_VCCUNCORE settings. Furthermore, any Intel®
Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series can drive
different VID_VCCCORE and VID_VCCUNCORE settings during normal operation.
Table 2-36 and Table 2-37 specify the voltage levels corresponding to the state of
VID_VCCCORE and VID_VCCUNCORE for the Intel® Itanium® Processor 9300 Series
and Intel® Itanium® Processor 9500 Series respectively. A ‘1’ in this table refers to a
high voltage level and a ‘0’ refers to a low voltage level.
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
provide the ability to operate while transitioning to an adjacent VID and its associated
processor core voltage (VCCCORE). This will represent a DC shift in the load line. It
should be noted that a low-to-high or high-to-low voltage state change may result in
many VID transitions as necessary to reach the target core voltage. Transitions above
the specified VID are not permitted.
The Ararat voltage regulator must be capable of regulating its output to the value
defined by the new VID. Please refer to the Ararat 170 Watt Voltage Regulator Module
Design Guide for the Intel® Itanium® Processor 9300 Series processor or the Ararat II
Voltage Regulator Module Design Guide for the Intel® Itanium® Processor 9500 Series.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
57
Electrical Specifications
2.7.1
Core and Uncore Voltage Identification for the Intel®
Itanium® Processor 9300 Series
Table 2-36. Intel® Itanium® Processor 9300 Series VCCCORE (VID_VCCCORE) and
VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for
Ararat (Sheet 1 of 2)
VID VID
VID VID VID
VI
D0
Hex
VID6
VID3
VID (V)
Hex VID6 VID5 VID4 VID3 VID2 VID1
VID (V)
5
4
2
1
0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OFF
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.0375
1.0250
1.0125
1.000
1.6000
1.5875
1.5750
1.5625
1.5500
1.5375
1.5250
1.5125
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2870
1.2750
1.2625
1.2500
1.2375
1.2250
1.2125
1.2000
1.1875
1.1750
1.1625
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
0.7750
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
®
®
58
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-36. Intel® Itanium® Processor 9300 Series VCCCORE (VID_VCCCORE) and
VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for
Ararat (Sheet 2 of 2)
VID VID
VID VID VID
VI
D0
Hex
VID6
VID3
VID (V)
Hex VID6 VID5 VID4 VID3 VID2 VID1
VID (V)
5
4
2
1
0
25
26
27
28
29
2A
2B
2C
2D
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1.1500
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
53
54
55
56
57
58
59
7F
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
OFF
®
2.7.2
Core and Uncore Voltage Identification for the Intel
®
Itanium Processor 9500 Series
Table 2-37. Intel® Itanium® Processor 9500 Series VCCCORE (VID_VCCCORE) and
VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for
Ararat II (Sheet 1 of 4)
VID
7
VID VID VID VID VID VID
VID VID VID VID VID VID VID VI
VID
(V)
Hex
VID6
VID (V)
Hex
5
4
3
2
1
0
7
6
5
4
3
2
1
D0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OFF
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.440
0.445
0.450
0.455
0.460
0.465
0.470
0.475
0.480
0.485
0.490
0.495
0.500
0.505
0.510
0.515
0.520
0.525
0.530
0.535
0.540
0.545
0.250
0.255
0.260
0.265
0.270
0.275
0.280
0.285
0.290
0.295
0.300
0.305
0.310
0.315
0.320
0.325
0.330
0.335
0.340
0.345
0.350
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
59
Electrical Specifications
Table 2-37. Intel® Itanium® Processor 9500 Series VCCCORE (VID_VCCCORE) and
VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for
Ararat II (Sheet 2 of 4)
VID
7
VID VID VID VID VID VID
VID VID VID VID VID VID VID VI
VID
(V)
Hex
VID6
VID (V)
Hex
5
4
3
2
1
0
7
6
5
4
3
2
1
D0
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.355
0.360
0.365
0.370
0.375
0.380
0.385
0.390
0.395
0.400
0.405
0.410
0.415
0.420
0.425
0.430
0.435
0.635
0.640
0.645
0.650
0.655
0.660
0.665
0.670
0.675
0.680
0.685
0.690
0.695
0.700
0.705
0.710
0.715
0.720
0.725
0.730
0.735
0.740
0.745
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.550
0.555
0.560
0.565
0.570
0.575
0.580
0.585
0.590
0.595
0.600
0.605
0.610
0.615
0.620
0.625
0.630
0.835
0.840
0.845
0.850
0.855
0.860
0.865
0.870
0.875
0.880
0.885
0.890
0.895
0.900
0.905
0.910
0.915
0.920
0.925
0.930
0.935
0.940
0.945
®
®
60
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-37. Intel® Itanium® Processor 9500 Series VCCCORE (VID_VCCCORE) and
VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for
Ararat II (Sheet 3 of 4)
VID
7
VID VID VID VID VID VID
VID VID VID VID VID VID VID VI
VID
(V)
Hex
VID6
VID (V)
Hex
5
4
3
2
1
0
7
6
5
4
3
2
1
D0
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.750
0.755
0.760
0.765
0.770
0.775
0.780
0.785
0.790
0.795
0.800
0.805
0.810
0.815
0.820
0.825
0.830
1.035
1.040
1.045
1.050
1.055
1.060
1.065
1.070
1.075
1.080
1.085
1.090
1.095
1.100
1.105
1.110
1.115
1.120
1.125
1.130
1.135
1.140
1.145
8D
8E
8F
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.950
0.955
0.960
0.965
0.970
0.975
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
1.025
1.030
1.235
1.240
1.245
1.250
1.255
1.260
1.265
1.270
1.275
1.280
1.285
1.290
1.295
1.300
1.305
1.310
1.315
1.320
1.325
1.330
1.335
1.340
1.345
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
61
Electrical Specifications
Table 2-37. Intel® Itanium® Processor 9500 Series VCCCORE (VID_VCCCORE) and
VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for
Ararat II (Sheet 4 of 4)
VID
7
VID VID VID VID VID VID
VID VID VID VID VID VID VID VI
VID
(V)
Hex
VID6
VID (V)
Hex
5
4
3
2
1
0
7
6
5
4
3
2
1
D0
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0
C1
C2
C3
C4
C5
EE
EF
F0
F1
F2
F3
F4
F5
F6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.150
1.155
1.160
1.165
1.170
1.175
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
1.225
1.230
1.435
1.440
1.445
1.450
1.455
1.460
1.465
1.470
1.475
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1.350
1.355
1.360
1.365
1.370
1.375
1.380
1.385
1.390
1.395
1.400
1.405
1.410
1.415
1.420
1.425
1.430
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
2.8
Cache Voltage Identification (Intel® Itanium®
Processor 9300 Series only)
The Cache Voltage Identification (CVID) value supplies the voltage for VCCCACHE, the
L3 cache voltage for the Intel® Itanium® Processor 9300 Series. The VID_VCCCACHE
specification for the processor is supported by the Ararat I Regulator Module Design
Guide. The voltage set by the VID_VCCCACHE value is the maximum VCCCACHE
voltage allowed by the processor.
Individual processor CVID values may be calibrated during manufacturing such that
two devices at the same core speed may have different default VID_VCCCACHE
settings.
®
®
62
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
The processor uses the VID_VCCCACHE value to support automatic selection of the
power supply voltages. Table 2-38 specifies the voltage level corresponding to the state
of VID_VCCCACHE. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a
low voltage level. See the Ararat I Regulator Module Design Guide for more details.
Table 2-38. Cache (VID_VCCCACHE) Voltage Identification Definition for Ararat
VID
5
VID
4
VID
3
VID
2
VID
1
VID
0
VID
(V)
VID
(V)
Hex
Hex VID5 VID4 VID3 VID2 VID1 VID0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OFF
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.2125
1.2000
1.1875
1.1750
1.1625
1.1500
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
1.0250
1.0125
1.000
1.6000
1.5875
1.5750
1.5625
1.5500
1.5375
1.5250
1.5125
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2870
1.2750
1.2625
1.2500
1.2375
1.2250
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
2.9
RSVD, Unused, and DEBUG Pins
All RSVD (RESERVED) pins must be left unconnected. Connection of these pins to
power, VSS, or to any other signal (including each other) can result in component
malfunction or incompatibility with future processors.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
63
Electrical Specifications
For reliable operation, always terminate unused inputs or bi-directional signals to their
respective deasserted states. A resistor must be used when tying bi-directional signals
to power or ground, also allowing for system testability. Unused pins of Intel®
QuickPath Interconnect and FB-DIMM ports may be left as no-connects since
termination is provided on the processor silicon.
Unused outputs may be terminated on the system board or left connected. Note that
leaving unused outputs unterminated may interfere with some Test Access Port (TAP)
functions, complicate debug probing, and prevent boundary scan testing. Signal
termination for these signal types is discussed in latest revisions of Intel® Itanium®
Processor 9300 Series and Intel® Itanium® Processor 9500 Series Platform Design
Guide.
Debug pins have ODT and can be left as no-connects. Their routing guidelines are
provided in the Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor
9500 Series Platform Design Guide.
2.10
Mixing Processors
Intel will support mixing CPUs in the same system or hard partition as defined below. A
hard partition is a smaller system capable of booting an OS, consisting of one or more
processors, memory and I/O controller hubs that are formed by domain partitioning.
1. CPUs from adjacent steppings. For example if one cpu is from stepping N, and
another cpu is from the next stepping, N+1, then CPUN and CPUN+1 are compatible.
Similarly CPUN is not compatible with CPUN+2
.
2. All CPUs in the system or hard partition must have the same core clock speed or
speed range and the same cache size.
3. All Intel® QPI links must have the same data rate, except for Intel® QPI links which
are disabled or in slow mode.
Additionally, for the Intel® Itanium® Processor 9300 Series:
4. If variable frequency mode (VFM) is enabled in one CPU it must be enabled in all
CPUs. If VFM mode is disabled in one CPU it must be disabled in all CPUs.
5. Mixing an enabled VFM part with an fixed frequency mode (FFM) part within the
same system or hard partition.
2.11
Supported Power-up Voltage Sequence
The supported order of voltage sequencing for the processor, detailed in Figure 2-17
and Figure 2-18 and Table 2-39, is VCC33_SM, VccArarat(12V), VCCA, VCCIO,
VCCUNCORE and VCCCORE for the Intel® Itanium® Processor 9500 Series processor
and followed by VCCCACHE for the Intel® Itanium® Processor 9300 Series processor. If
customers need to apply VccArarat(12V) before VCC33_SM, the processor will not
sustain damage. The application of VCC33_SM before VccArarat(12V) allows the PIROM
to be read before the processor is powered.
Once started, the power up sequence must complete within 1000 ms, as defined by the
time limit for PWRGOOD to be asserted. VCC33_SM is brought up first to allow
platforms to read the socket Processor Information data and the PROCTYPE pin.
VccArarat (12V) is the input voltage to the Ararat regulator. The VCCA supply is used to
power the processor’s analog circuits. VCCIO is used to power the I/O circuits. Once
VCCIO is up and stable the external environment can generate the SYSINT clock
signals. Once the SYSINT clocks are valid, the external environment can assert the
®
®
64
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
VROUTPUT_ENABLE0 signal. After VROUTPUT_ENABLE0 is asserted the sequence of
powering up the VCCUNCORE and VCCCORE supplies and the VCCCACHE (Intel®
Itanium® Processor 9300 Series) begins.
For the Intel® Itanium® Processor 9300 Series, the VCCUNCORE, VCCCORE and
VCCCACHE supplies power the sysint, cores and large cache arrays respectively.
For the Intel® Itanium® Processor 9500 Series, the VCCUNCORE and VCCCORE
supplies power the sysint, the cores and the large cache arrays respectively.
When all supplies are up and stable, Ararat asserts VRPWRGD which signals the
external environment that it can assert the PWRGOOD signal. PWRGOOD assertion
initiates the processor internal cold reset sequence.
With reference to the power sequencing timing requirements imposed by the Ararat VR
as shown in Figure 2-17 and Figure 2-18, timing specifications for the elapsed time
taken for an Ararat regulator to bring up each of its output voltages can be found in the
Ararat 170 Watt Voltage Regulator Module Design Guide for the Intel® Itanium®
Processor 9300 Series and the Ararat II Voltage Regulator Module Design Guide for the
Intel® Itanium® Processor 9500 Series.
When the platform asserts PWRGOOD to the processor, the Intel® Itanium® Processor
9300 Series requires a minimum of 10 ms to complete its internal reset sequence
before deasserting RESET_N, while the Intel® Itanium® Processor 9500 Series
requires a minimum of 15 ms. For platforms that use both processors, a minimum of
15 ms is needed to meet the requirements of both processors.
During platform initialization, the RESET_N pin to any component in the platform can
be removed ONLY after all other components have had sufficient time to sample their
respective reset pins. This is needed to prevent unknown behavior that may result if
any one system component comes out of reset before other components have received
the reset signal.
With the exception of standby miscellaneous pins, all input pins, bi-directional pins, and
terminated output pins must not be allowed to exceed the processor's actual VCCIO
voltage prior to and during ramp up of the VCCIO supply.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
65
Electrical Specifications
2.11.1
Supported Power-up Voltage Sequence for the Intel®
Itanium® Processor 9300 Series
Figure 2-17. Supported Power-up Voltage Sequence Timing Requirements for the
Intel® Itanium® Processor 9300 Series
VCC33_SM (3.3v)
>1uS
>0uS
PROCTYPE
pulled to VSS on package for Intel® Itanium® processor 9300 series (VCC33_SM for other products)
>0us
VccArarat (12V)
>=0us
VCCA (1.8V)
>=0us
VCCIO
>1
us *
VR_PROCTYPE[1:0]
pulled to VSS on package for Intel® Itanium® processor 9300 series (VCC33_SM for other products)
>0us
SYSCLK (133MHz)
>0us
>1us *
>100ms *
Core and Cache Vids
may change to vfuse values
Uncore Vid may
change to on-die
fuse based value
Core Vid may
change in response
to power manager
VROUTPUT_ENABLE0
VCCUNCORE VID Value
VCCCORE VID Value
Vids = 0x29 (1.1V)
uncore fuse value
vfuse value
>0us
VCCCACHE VID Value
>0us
>0us
>0us
VCCUNCORE
VCCCORE
>0us
>0us
VCCCACHE
VRPWRGD
> 0us
>0us
>0us
> 200 ms*
<=1000mS
PWRGOOD
RESET_N
>=10ms
* Nominal value; refer to Ararat Spec for actual number
®
®
66
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
®
2.11.2
Supported Power-up Voltage Sequence for the Intel
®
Itanium Processor 9500 Series
Figure 2-18. Supported Power-up Sequence Timing Requirements for Intel® Itanium®
Processor 9500 Series
>0us
VCCSTBY33
(3.3V)
Pulled to 3.3VSM pin on platform
PROCTYPE
VCC (12V)
>= 0us
>= 0us
VCCA
(1.8V)
VCCIO
Pulled to Ararat’s internal 3.3V rail on Ararat itself
VR_PROCTYPE
> 0us
SYSCLK
(133MHz)
> 0us
svid_vcccore
svid changes
to vfuse
values
VROUTPUT_ENABLE0
SVID
may change in
response to
power
svids change
to hfuse values
> 100ms
manager
> 1 ms
All inputs low prior to VCCIO
Vstrap
1V
Vhfuse
0.9V
VCCUNCORE
VCCVUNCOREREADY
V=vfuse
V=hfuse
VCCCORE[1-4]
VR_READY
Pwrgd reset can change core VR set
<200ms
>0us
≥15ms
<=1000ms
PWRGOOD
RESET_N
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
67
Electrical Specifications
2.11.3
Power-up Voltage Sequence Timing Requirements
Table 2-39. Power-up Voltage Sequence Timing Requirements
Parameter
Min
Max
Unit
VCC33_SM stable high to VCCA delay
VCCA to VCCIO delay time
>0
0
μs
ms
μs
VCCIO to PWRGOOD high delay time
VCCIO stable high to SYSCLK
1000
>0
>0
>1
SYSCLK valid before VROUTPUTENABLE0 high
μs
®
VCCIO stable before VROUTPUT_ENABLE0 high for Intel
μs
®
1
Itanium Processor 9300 Series
®
VCCIO stable before VROUTPUT_ENABLE0 high for Intel
Itanium Processor 9500 Series
>1
ms
ms
ms
®
2
®
VROUTPUT_ENABLE0 high to VRPWRGOOD high for Intel
200
200
®
1
Itanium Processor 9300 Series
®
®
VROUTPUT_ENABLE0 high to VR_READY for Intel Itanium
2
Processor 9500 Series
1
VCCUNCORE time to stabilize
1
5
8
ms
ms
ms
1
Delay from VCCUNCORE at programmed VID value to VCCCORE
0.05
0.05
1
VCCCORE steady at safe VID value
3
1
VCCCORE transition time from safe VID to programmed VID
2.5
3
Delay from VCCCORE/VCCUNCORE/VCCCACHE at programmed
values to VRPWRGOOD high for Intel Itanium Processor 9300
0.05
®
®
1
Series
®
®
VRPWRGD high to PWRGOOD high for Intel® Intel Itanium
>0
>0
10
15
ms
ms
ms
ms
Processor 9300 Series
®
®
VR_READY high to PWRGOOD high for Intel Itanium Processor
9500 Series
®
®
PWRGOOD high to RESET_N high (t
Processor 9300 Series
) Intel Itanium
RESET_N
®
®
PWRGOOD high to RESET_N high (t
Processor 9500 Series
) Intel Itanium
RESET_N
2.12
Supported Power-down Voltage Sequence
The supported power down sequence of voltage for the processor is detailed in
Figure 2-19. It should be noted that when the processor is required to be physically
removed from its socket, power rails VCC33_SM and Vcc(12V) must also be powered
down before removal of the processor.
®
®
68
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Figure 2-19. Supported Power-down Voltage Sequence Timing Requirements
tR E S E T _ N
A s fa s t a s p o s s ib le
R E S E T _ N
P W G O O D
> = 0 u s
A ll s u p p lie s to p o w e r d o w n a s fa s t a s
P o s s ib le a fte r P W R G O O D d e a s s e rtio n
V R _ O U T P U T _ E N
V ID s
c h a n g e to s a fe V ID
V C C C O R E
V C C U N C O R E
V C C C A C H E
> 1 u s
> 0 u s
R E F C L K
(1 3 3 M H z )
V C C IO
V C C A
V C C A M U S T U N P O W E R A L O N G W IT H V C C IO
tR E S E T _ N = 1 0 m s fo r In te l Ita n iu m 9 3 0 0 S e rie s P ro c e s s o r
= 1 5 m s fo r P o u ls o n -M C P ro c e s s o r
2.13
Timing Relationship Between RESET_N and SKTID
In the processor, the SKTID pins are time-shared:
SKTID[0] is interpreted as a NodeID bit during cold reset and pwrgood reset. It is
interpreted as the error reset modifier during warm-logic reset if SKTID[0] is asserted.
SKTID[2] is interpreted as a NodeID bit during cold reset and pwrgood reset, and it is
interpreted as an error input being signaled by the system at all other times (except
during non-cold resets when it is ignored). Figure 2-20 and Table 2-40 show the timing
relationship between RESET_N and SKTID pins for different reset cases.
The LRGSCLSYS pin is sampled only during the PWRGOOD and cold reset period.
The BOOTMODE[2:0] and FLASHROM_CFG[1:0] pins are sampled during the assertion
of all resets except warm-logic resets.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
69
Electrical Specifications
Figure 2-20. RESET_N and SKITID Timing for Warm and Cold Resets
COLD RESET
WARM-
STATE OR WARM-
LOGIC RESETS
(PWR CYCLE OR PWRGOOD)
SYSCLK
T 3
T 3
T 2
T 4
T5
RESET_N
T 1
PWRGOOD
T 7
T9
T6
T 8
T 10
socket id
socket id
SKTID[1:0]
SKTID[2]
Error Reset
T 11
(Warm-Logic) if
0
SKTID[ ]==1
error_in
T12
strap value
LRGSCLSYS
T13
T 13
FLASHROM
[1:0]
_CFG
strap values
strap values
BOOTMODE[2:0]
T14
Table 2-40. RESET_N and SKTID Timing (Sheet 1 of 2)
Parameter
Description
MIN
MAX
UNIT
PWRGOOD deasserted delay to RESET_N
asserted
T1
0
200
ns
PWRGOOD asserted delay to RESET_N
deasserted (Intel® Itanium® Processor 9300
Series)
T2
T2
10
ms
PWRGOOD asserted delay to RESET_N
deasserted (Intel® Itanium® Processor 9500
Series)
15
ms
ps
RESET_N setup and hold relative to SYSCLK
asserted
T3
T4
T5
T5
T6
500
8
RESET_N deasserted pulse width
SYSCLK
cycles
RESET_N asserted pulse width (Intel® Itanium®
Processor 9300 Series)
10
15
0
ms
ms
ns
RESET_N asserted pulse width (Intel® Itanium®
Processor 9500 Series)
SKTID[2:0] (as rst modifier, error) hold after
PWRGOOD deasserted
SKTID[2:0] (as socket id), LRGSCLSYS,
BOOTMODE[2:0], FLASHROM_CFG[1:0] setup to
PWRGOOD deasserted
T7
0
ns
SKTID[2:0] (as socket id), LRGSCLSYS hold
after RESET_N deasserted
T8
T9
0
ns
ns
ns
SKTID[1:0] (as rst modifier) setup to RESET_N
asserted
200
200
SKTID[1:0] (as rst modifier) hold after RESET_N
asserted
T10
®
®
70
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Electrical Specifications
Table 2-40. RESET_N and SKTID Timing (Sheet 2 of 2)
Parameter
Description
MIN
MAX
UNIT
RESET_N deasserted delay to SKTID[2]
deasserted (as error in)
T11
100
ns
SKTID[2] (as error in) asserted pulse width
SYSCLK
cycles
T12
T13
T14
3
1
0
BOOTMODE[2:0], FLASHROM_CFG[1:0] hold
after RESET_N deasserted
us
ns
BOOTMODE[2:)], FLASHROM_CFG[1:0] setup to
RESET_N asserted
2.14
Test Access Port (TAP) Connection
The recommended TAP connectivity is detailed in the Intel® Itanium® Platform Debug
Port Design Guide (DPDG).
§
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
71
Electrical Specifications
®
®
72
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
3 Pin Listing
3.1
Processor Package Bottom Pin Assignments
This section provides a sorted package bottom pin list in Table 3-1 and Table 3-2.
Table 3-1 is a listing of all processor package bottom side pins ordered alphabetically
by pin name. Table 3-2 is a listing of all processor package bottom side pins ordered by
pin number. All pins are defined for both Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series except where noted.
3.1.1
Package Bottom Pin Listing by Pin Name
Table 3-1.
Pin List by Pin Name (Sheet 2
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 1
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
A33
C34
B35
E35
D36
E38
F37
G36
H37
J36
CSI0RPDAT[0]
CSI0RPDAT[1]
CSI0RPDAT[2]
CSI0RPDAT[3]
CSI0RPDAT[4]
CSI0RPDAT[5]
CSI0RPDAT[6]
CSI0RPDAT[7]
CSI0RPDAT[8]
CSI0RPDAT[9]
CSI0RPDAT[10]
CSI0RPDAT[11]
CSI0RPDAT[12]
CSI0RPDAT[13]
CSI0RPDAT[14]
CSI0RPDAT[15]
CSI0RPDAT[16]
CSI0RPDAT[17]
CSI0RPDAT[18]
CSI0RPDAT[19]
CSI0TNCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
I
I
G10
G9
BOOTMODE[0]
BOOTMODE[1]
CPU_PRES1_N
CPU_PRES2_N
CPU_PRES3_N
CPU_PRES4_N
CSI0RNCLK
I
I
I
C3
I/O
I
D37
AT36
AT3
J37
I/O
I
I/O
I
I/O
I
I
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
I
B33
D34
B34
D35
C36
E37
F36
G35
H36
J35
CSI0RNDAT[0]
CSI0RNDAT[1]
CSI0RNDAT[2]
CSI0RNDAT[3]
CSI0RNDAT[4]
CSI0RNDAT[5]
CSI0RNDAT[6]
CSI0RNDAT[7]
CSI0RNDAT[8]
CSI0RNDAT[9]
CSI0RNDAT[10]
CSI0RNDAT[11]
CSI0RNDAT[12]
CSI0RNDAT[13]
CSI0RNDAT[14]
CSI0RNDAT[15]
CSI0RNDAT[16]
CSI0RNDAT[17]
CSI0RNDAT[18]
CSI0RNDAT[19]
CSI0RPCLK
I
I
I
I
I
L37
M38
N38
P37
R38
T37
U38
V36
V37
W36
K33
K30
J31
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
L36
L38
N37
P36
R37
T36
T38
U36
V38
W37
K37
I
I
I
I
I
O
O
O
O
O
O
O
O
I
CSI0TNDAT[0]
CSI0TNDAT[1]
CSI0TNDAT[2]
CSI0TNDAT[3]
CSI0TNDAT[4]
CSI0TNDAT[5]
CSI0TNDAT[6]
I
I
G31
F30
K32
F31
E32
I
I
I
I
I
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
73
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 3
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 4
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
F33
H33
L31
CSI0TNDAT[7]
CSI0TNDAT[8]
CSI0TNDAT[9]
CSI0TNDAT[10]
CSI0TNDAT[11]
CSI0TNDAT[12]
CSI0TNDAT[13]
CSI0TNDAT[14]
CSI0TNDAT[15]
CSI0TNDAT[16]
CSI0TNDAT[17]
CSI0TNDAT[18]
CSI0TNDAT[19]
CSI0TPCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
AP36
AP37
AN37
AM36
AL37
AJ37
AH38
AG36
AF38
AF36
AE37
AD36
AC37
AA38
Y38
CSI1RNDAT[5]
CSI1RNDAT[6]
CSI1RNDAT[7]
CSI1RNDAT[8]
CSI1RNDAT[9]
CSI1RNDAT[10]
CSI1RNDAT[11]
CSI1RNDAT[12]
CSI1RNDAT[13]
CSI1RNDAT[14]
CSI1RNDAT[15]
CSI1RNDAT[16]
CSI1RNDAT[17]
CSI1RNDAT[18]
CSI1RNDAT[19]
CSI1RPCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
L33
M34
N32
N34
R34
R33
U33
V32
V34
W32
K34
J30
CSI0TPDAT[0]
CSI0TPDAT[1]
CSI0TPDAT[2]
CSI0TPDAT[3]
CSI0TPDAT[4]
CSI0TPDAT[5]
CSI0TPDAT[6]
CSI0TPDAT[7]
CSI0TPDAT[8]
CSI0TPDAT[9]
CSI0TPDAT[10]
CSI0TPDAT[11]
CSI0TPDAT[12]
CSI0TPDAT[13]
CSI0TPDAT[14]
CSI0TPDAT[15]
CSI0TPDAT[16]
CSI0TPDAT[17]
CSI0TPDAT[18]
CSI0TPDAT[19]
CSI1RNCLK
H31
G30
E30
J32
AK37
AT33
AV32
AU34
AR33
AU35
AP35
AR37
AN36
AM35
AL36
AJ36
AH37
AH36
AG38
AF37
AE38
AD37
AC38
AB38
Y37
CSI1RPDAT[0]
CSI1RPDAT[1]
CSI1RPDAT[2]
CSI1RPDAT[3]
CSI1RPDAT[4]
CSI1RPDAT[5]
CSI1RPDAT[6]
CSI1RPDAT[7]
CSI1RPDAT[8]
CSI1RPDAT[9]
CSI1RPDAT[10]
CSI1RPDAT[11]
CSI1RPDAT[12]
CSI1RPDAT[13]
CSI1RPDAT[14]
CSI1RPDAT[15]
CSI1RPDAT[16]
CSI1RPDAT[17]
CSI1RPDAT[18]
CSI1RPDAT[19]
CSI1TNCLK
F32
E33
G33
H34
L32
M33
M35
N33
P34
R35
T33
U34
V33
W34
Y32
AK38
AU33
AV33
AV34
AR34
AT35
CSI1RNDAT[0]
CSI1RNDAT[1]
CSI1RNDAT[2]
CSI1RNDAT[3]
CSI1RNDAT[4]
I
I
AJ32
AL27
AN28
AL28
I
CSI1TNDAT[0]
CSI1TNDAT[1]
CSI1TNDAT[2]
I
I
®
®
74
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 5
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 6
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AN29
AP31
AL30
AN32
AN34
AM31
AL33
AK33
AH34
AH32
AG33
AE33
AE34
AC34
AB34
AA35
Y34
CSI1TNDAT[3]
CSI1TNDAT[4]
CSI1TNDAT[5]
CSI1TNDAT[6]
CSI1TNDAT[7]
CSI1TNDAT[8]
CSI1TNDAT[9]
CSI1TNDAT[10]
CSI1TNDAT[11]
CSI1TNDAT[12]
CSI1TNDAT[13]
CSI1TNDAT[14]
CSI1TNDAT[15]
CSI1TNDAT[16]
CSI1TNDAT[17]
CSI1TNDAT[18]
CSI1TNDAT[19]
CSI1TPCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
H21
G20
F21
E23
E20
D21
C21
B20
C22
B23
B25
C26
A25
D26
C27
B28
B30
C31
C33
A22
J21
CSI2RNDAT[1]
CSI2RNDAT[2]
CSI2RNDAT[3]
CSI2RNDAT[4]
CSI2RNDAT[5]
CSI2RNDAT[6]
CSI2RNDAT[7]
CSI2RNDAT[8]
CSI2RNDAT[9]
CSI2RNDAT[10]
CSI2RNDAT[11]
CSI2RNDAT[12]
CSI2RNDAT[13]
CSI2RNDAT[14]
CSI2RNDAT[15]
CSI2RNDAT[16]
CSI2RNDAT[17]
CSI2RNDAT[18]
CSI2RNDAT[19]
CSI2RPCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AK32
AL26
AN27
AM28
AP29
AP30
AM30
AP32
AN33
AN31
AL32
AK34
AJ34
AH33
AG34
AF33
AE35
AD34
AB35
AA36
Y35
CSI1TPDAT[0]
CSI1TPDAT[1]
CSI1TPDAT[2]
CSI1TPDAT[3]
CSI1TPDAT[4]
CSI1TPDAT[5]
CSI1TPDAT[6]
CSI1TPDAT[7]
CSI1TPDAT[8]
CSI1TPDAT[9]
CSI1TPDAT[10]
CSI1TPDAT[11]
CSI1TPDAT[12]
CSI1TPDAT[13]
CSI1TPDAT[14]
CSI1TPDAT[15]
CSI1TPDAT[16]
CSI1TPDAT[17]
CSI1TPDAT[18]
CSI1TPDAT[19]
CSI2RNCLK
CSI2RPDAT[0]
CSI2RPDAT[1]
CSI2RPDAT[2]
CSI2RPDAT[3]
CSI2RPDAT[4]
CSI2RPDAT[5]
CSI2RPDAT[6]
CSI2RPDAT[7]
CSI2RPDAT[8]
CSI2RPDAT[9]
CSI2RPDAT[10]
CSI2RPDAT[11]
CSI2RPDAT[12]
CSI2RPDAT[13]
CSI2RPDAT[14]
CSI2RPDAT[15]
CSI2RPDAT[16]
CSI2RPDAT[17]
CSI2RPDAT[18]
CSI2RPDAT[19]
G21
G19
F20
E22
D20
D22
B21
A20
C23
A23
B24
B26
A26
D27
C28
B29
A30
B31
C32
A21
J22
CSI2RNDAT[0]
I
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
75
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 7
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 8
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
H29
H23
G24
F25
D24
H26
F26
E29
J26
CSI2TNCLK
CSI2TNDAT[0]
CSI2TNDAT[1]
CSI2TNDAT[2]
CSI2TNDAT[3]
CSI2TNDAT[4]
CSI2TNDAT[5]
CSI2TNDAT[6]
CSI2TNDAT[7]
CSI2TNDAT[8]
CSI2TNDAT[9]
CSI2TNDAT[10]
CSI2TNDAT[11]
CSI2TNDAT[12]
CSI2TNDAT[13]
CSI2TNDAT[14]
CSI2TNDAT[15]
CSI2TNDAT[16]
CSI2TNDAT[17]
CSI2TNDAT[18]
CSI2TNDAT[19]
CSI2TPCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
V31
W31
CSI2TPDAT[18]
CSI2TPDAT[19]
CSI3RNCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AU21
AN18
AL17
AM16
AN17
AP19
AR19
AV17
AU18
AV19
AT20
AT22
AU23
AV24
AU25
AU26
AT27
AU28
AV29
AU30
AV31
AT21
AM18
AL16
AM15
AN16
AN19
AR18
AV16
AT18
AU19
AR20
AR22
AT23
AV23
AU24
AT26
AR27
CSI3RNDAT[0]
CSI3RNDAT[1]
CSI3RNDAT[2]
CSI3RNDAT[3]
CSI3RNDAT[4]
CSI3RNDAT[5]
CSI3RNDAT[6]
CSI3RNDAT[7]
CSI3RNDAT[8]
CSI3RNDAT[9]
CSI3RNDAT[10]
CSI3RNDAT[11]
CSI3RNDAT[12]
CSI3RNDAT[13]
CSI3RNDAT[14]
CSI3RNDAT[15]
CSI3RNDAT[16]
CSI3RNDAT[17]
CSI3RNDAT[18]
CSI3RNDAT[19]
CSI3RPCLK
F28
H27
K28
M29
P30
M31
R30
P32
T31
U29
U31
W30
J29
G23
G25
E25
E24
G26
F27
D29
J27
CSI2TPDAT[0]
CSI2TPDAT[1]
CSI2TPDAT[2]
CSI2TPDAT[3]
CSI2TPDAT[4]
CSI2TPDAT[5]
CSI2TPDAT[6]
CSI2TPDAT[7]
CSI2TPDAT[8]
CSI2TPDAT[9]
CSI2TPDAT[10]
CSI2TPDAT[11]
CSI2TPDAT[12]
CSI2TPDAT[13]
CSI2TPDAT[14]
CSI2TPDAT[15]
CSI2TPDAT[16]
CSI2TPDAT[17]
CSI3RPDAT[0]
CSI3RPDAT[1]
CSI3RPDAT[2]
CSI3RPDAT[3]
CSI3RPDAT[4]
CSI3RPDAT[5]
CSI3RPDAT[6]
CSI3RPDAT[7]
CSI3RPDAT[8]
CSI3RPDAT[9]
CSI3RPDAT[10]
CSI3RPDAT[11]
CSI3RPDAT[12]
CSI3RPDAT[13]
CSI3RPDAT[14]
CSI3RPDAT[15]
G28
H28
K29
M30
P31
N31
T30
R32
T32
U30
®
®
76
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 9
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 10
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AT28
AV28
AU29
AU31
AK29
AL20
AM20
AM23
AN21
AN23
AM24
AP25
AN26
AM26
AJ27
AH29
AJ30
AG31
AF30
AF31
AD32
AC31
AB33
AA31
AA32
AK28
AK20
AM21
AL23
AP21
AN22
AN24
AR25
AP26
AM25
AK27
AJ29
AJ31
AH31
AG30
CSI3RPDAT[16]
CSI3RPDAT[17]
CSI3RPDAT[18]
CSI3RPDAT[19]
CSI3TNCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
I
AF32
AE32
AC32
AC33
AB31
AA33
H18
B15
D15
C16
A17
B18
C17
D19
E17
E18
F17
CSI3TPDAT[14]
CSI3TPDAT[15]
CSI3TPDAT[16]
CSI3TPDAT[17]
CSI3TPDAT[18]
CSI3TPDAT[19]
CSI4RNCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
O
O
O
O
O
O
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
CSI3TNDAT[0]
CSI3TNDAT[1]
CSI3TNDAT[2]
CSI3TNDAT[3]
CSI3TNDAT[4]
CSI3TNDAT[5]
CSI3TNDAT[6]
CSI3TNDAT[7]
CSI3TNDAT[8]
CSI3TNDAT[9]
CSI3TNDAT[10]
CSI3TNDAT[11]
CSI3TNDAT[12]
CSI3TNDAT[13]
CSI3TNDAT[14]
CSI3TNDAT[15]
CSI3TNDAT[16]
CSI3TNDAT[17]
CSI3TNDAT[18]
CSI3TNDAT[19]
CSI3TPCLK
CSI4RNDAT[0]
CSI4RNDAT[1]
CSI4RNDAT[2]
CSI4RNDAT[3]
CSI4RNDAT[4]
CSI4RNDAT[5]
CSI4RNDAT[6]
CSI4RNDAT[7]
CSI4RNDAT[8]
CSI4RNDAT[9]
CSI4RPCLK
I
I
I
I
I
I
I
I
I
I
G18
A15
D16
B16
A18
B19
C18
C19
D17
E19
F18
I
CSI4RPDAT[0]
CSI4RPDAT[1]
CSI4RPDAT[2]
CSI4RPDAT[3]
CSI4RPDAT[4]
CSI4RPDAT[5]
CSI4RPDAT[6]
CSI4RPDAT[7]
CSI4RPDAT[8]
CSI4RPDAT[9]
CSI4TNCLK
I
I
I
I
I
I
I
I
CSI3TPDAT[0]
CSI3TPDAT[1]
CSI3TPDAT[2]
CSI3TPDAT[3]
CSI3TPDAT[4]
CSI3TPDAT[5]
CSI3TPDAT[6]
CSI3TPDAT[7]
CSI3TPDAT[8]
CSI3TPDAT[9]
CSI3TPDAT[10]
CSI3TPDAT[11]
CSI3TPDAT[12]
CSI3TPDAT[13]
I
I
L21
O
O
O
O
O
O
O
O
O
O
O
O
M14
K13
K15
J14
CSI4TNDAT[0]
CSI4TNDAT[1]
CSI4TNDAT[2]
CSI4TNDAT[3]
CSI4TNDAT[4]
CSI4TNDAT[5]
CSI4TNDAT[6]
CSI4TNDAT[7]
CSI4TNDAT[8]
CSI4TNDAT[9]
CSI4TPCLK
G15
J16
K17
L18
K19
L20
L22
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
77
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 11
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 12
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
M15
K14
CSI4TPDAT[0]
CSI4TPDAT[1]
CSI4TPDAT[2]
CSI4TPDAT[3]
CSI4TPDAT[4]
CSI4TPDAT[5]
CSI4TPDAT[6]
CSI4TPDAT[7]
CSI4TPDAT[8]
CSI4TPDAT[9]
CSI5RNCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
O
O
O
O
O
O
O
O
O
O
I
AG19
AJ20
AL21
AK22
AH13
AJ14
AK15
AH16
AJ17
AJ19
AK19
AG20
AJ21
AL22
H12
CSI5TNDAT[7]
CSI5TNDAT[8]
CSI5TNDAT[9]
CSI5TPCLK
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
J15
H14
G16
CSI5TPDAT[0]
CSI5TPDAT[1]
CSI5TPDAT[2]
CSI5TPDAT[3]
CSI5TPDAT[4]
CSI5TPDAT[5]
CSI5TPDAT[6]
CSI5TPDAT[7]
CSI5TPDAT[8]
CSI5TPDAT[9]
ERROR[0]_N
H16
J17
K18
J19
K20
AP17
AL12
AM13
AN14
AP15
AR13
AT13
AU14
AR15
AU15
AT16
AR17
AL13
AN13
AP14
AP16
AR14
AU13
AV14
AT15
AU16
AT17
AJ22
AG13
AH14
AJ15
AG16
AH17
AH19
AK18
CSI5RNDAT[0]
CSI5RNDAT[1]
CSI5RNDAT[2]
CSI5RNDAT[3]
CSI5RNDAT[4]
CSI5RNDAT[5]
CSI5RNDAT[6]
CSI5RNDAT[7]
CSI5RNDAT[8]
CSI5RNDAT[9]
CSI5RPCLK
I
I
I
I
I
J12
ERROR[1]_N
I
AT11
AU9
FBD0NBIAN[0]
FBD0NBIAN[1]
FBD0NBIAN[2]
FBD0NBIAN[3]
FBD0NBIAN[4]
FBD0NBIAN[5]
FBD0NBIAN[6]
FBD0NBIAN[7]
FBD0NBIAN[8]
FBD0NBIAN[9]
FBD0NBIAN[10]
FBD0NBIAN[11]
FBD0NBIAN[12]
FBD0NBIAN[13]
FBD0NBIAN[14]
FBD0NBIAP[0]
FBD0NBIAP[1]
FBD0NBIAP[2]
FBD0NBIAP[3]
FBD0NBIAP[4]
FBD0NBIAP[5]
FBD0NBIAP[6]
FBD0NBIAP[7]
FBD0NBIAP[8]
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
I
I
I
AV8
I
I
AR10
AT8
I
I
I
I
AT6
I
CSI5RPDAT[0]
CSI5RPDAT[1]
CSI5RPDAT[2]
CSI5RPDAT[3]
CSI5RPDAT[4]
CSI5RPDAT[5]
CSI5RPDAT[6]
CSI5RPDAT[7]
CSI5RPDAT[8]
CSI5RPDAT[9]
CSI5TNCLK
I
AP4
I
I
AN2
I
I
AN3
I
I
AL3
I
I
AL1
I
I
AK2
I
I
AR2
I
I
AU4
I
I
AV11
AU11
AU10
AV9
I
I
I
O
O
O
O
O
O
O
O
I
CSI5TNDAT[0]
CSI5TNDAT[1]
CSI5TNDAT[2]
CSI5TNDAT[3]
CSI5TNDAT[4]
CSI5TNDAT[5]
CSI5TNDAT[6]
I
AT10
AU8
I
I
AU6
I
AR4
I
AP2
I
AN4
I
®
®
78
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 13
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 14
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AM3
AL2
AK3
AR3
AU5
AV12
AN9
AM9
AP7
AP6
AM5
AK5
AG1
AF3
AF2
AE3
AD1
AB1
AH2
AJ4
FBD0NBIAP[9]
FBD0NBIAP[10]
FBD0NBIAP[11]
FBD0NBIAP[12]
FBD0NBIAP[13]
FBD0NBIAP[14]
FBD0NBIBN[0]
FBD0NBIBN[1]
FBD0NBIBN[2]
FBD0NBIBN[3]
FBD0NBIBN[4]
FBD0NBIBN[5]
FBD0NBIBN[6]
FBD0NBIBN[7]
FBD0NBIBN[8]
FBD0NBIBN[9]
FBD0NBIBN[10]
FBD0NBIBN[11]
FBD0NBIBN[12]
FBD0NBIBN[13]
FBD0NBIBN[14]
FBD0NBIBP[0]
FBD0NBIBP[1]
FBD0NBIBP[2]
FBD0NBIBP[3]
FBD0NBIBP[4]
FBD0NBIBP[5]
FBD0NBIBP[6]
FBD0NBIBP[7]
FBD0NBIBP[8]
FBD0NBIBP[9]
FBD0NBIBP[10]
FBD0NBIBP[11]
FBD0NBIBP[12]
FBD0NBIBP[13]
FBD0NBIBP[14]
FBD0NBICLKAN0
FBD0NBICLKAP0
FBD0NBICLKBN0
FBD0NBICLKBP0
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AL6
AL7
V4
FBD0REFSYSCLKN
FBD0REFSYSCLKP
FBD0SBOAN[0]
FBD0SBOAN[1]
FBD0SBOAN[2]
FBD0SBOAN[3]
FBD0SBOAN[4]
FBD0SBOAN[5]
FBD0SBOAN[6]
FBD0SBOAN[7]
FBD0SBOAN[8]
FBD0SBOAN[9]
FBD0SBOAN[10]
FBD0SBOAP[0]
FBD0SBOAP[1]
FBD0SBOAP[2]
FBD0SBOAP[3]
FBD0SBOAP[4]
FBD0SBOAP[5]
FBD0SBOAP[6]
FBD0SBOAP[7]
FBD0SBOAP[8]
FBD0SBOAP[9]
FBD0SBOAP[10]
FBD0SBOBN[0]
FBD0SBOBN[1]
FBD0SBOBN[2]
FBD0SBOBN[3]
FBD0SBOBN[4]
FBD0SBOBN[5]
FBD0SBOBN[6]
FBD0SBOBN[7]
FBD0SBOBN[8]
FBD0SBOBN[9]
FBD0SBOBN[10]
FBD0SBOBP[0]
FBD0SBOBP[1]
FBD0SBOBP[2]
FBD0SBOBP[3]
FBD0SBOBP[4]
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
W1
V2
U1
T1
N3
M1
L3
L1
P1
J2
W4
W2
V3
V1
T2
N2
N1
AM10
AP9
AM8
AR7
AN6
AM6
AL5
AH1
AG3
AF1
AE2
AD2
AC1
AJ2
M3
L2
P2
K2
AK8
AJ7
AH6
AF7
AF6
AC4
AB3
AD6
AA2
AD7
Y3
AK4
AL10
AR5
AT5
AH3
AH4
AK9
AK7
AH7
AF8
AG6
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
79
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 15
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 16
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AD4
AC3
AD5
AA3
AE7
Y4
FBD0SBOBP[5]
FBD0SBOBP[6]
FBD0SBOBP[7]
FBD0SBOBP[8]
FBD0SBOBP[9]
FBD0SBOBP[10]
FBD0SBOCLKAN0
FBD0SBOCLKAP0
FBD0SBOCLKBN0
FBD0SBOCLKBP0
FBD1NBICLKCN0
FBD1NBICLKCP0
FBD1NBICLKDN0
FBD1NBICLKDP0
FBD1NBICN[0]
FBD1NBICN[1]
FBD1NBICN[2]
FBD1NBICN[3]
FBD1NBICN[4]
FBD1NBICN[5]
FBD1NBICN[6]
FBD1NBICN[7]
FBD1NBICN[8]
FBD1NBICN[9]
FBD1NBICN[10]
FBD1NBICN[11]
FBD1NBICN[12]
FBD1NBICN[13]
FBD1NBICN[14]
FBD1NBICP[0]
FBD1NBICP[1]
FBD1NBICP[2]
FBD1NBICP[3]
FBD1NBICP[4]
FBD1NBICP[5]
FBD1NBICP[6]
FBD1NBICP[7]
FBD1NBICP[8]
FBD1NBICP[9]
FBD1NBICP[10]
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
O
O
O
O
O
O
O
O
O
O
I
F10
L11
M10
Y9
FBD1NBICP[11]
FBD1NBICP[12]
FBD1NBICP[13]
FBD1NBICP[14]
FBD1NBIDN[0]
FBD1NBIDN[1]
FBD1NBIDN[2]
FBD1NBIDN[3]
FBD1NBIDN[4]
FBD1NBIDN[5]
FBD1NBIDN[6]
FBD1NBIDN[7]
FBD1NBIDN[8]
FBD1NBIDN[9]
FBD1NBIDN[10]
FBD1NBIDN[11]
FBD1NBIDN[12]
FBD1NBIDN[13]
FBD1NBIDN[14]
FBD1NBIDP[0]
FBD1NBIDP[1]
FBD1NBIDP[2]
FBD1NBIDP[3]
FBD1NBIDP[4]
FBD1NBIDP[5]
FBD1NBIDP[6]
FBD1NBIDP[7]
FBD1NBIDP[8]
FBD1NBIDP[9]
FBD1NBIDP[10]
FBD1NBIDP[11]
FBD1NBIDP[12]
FBD1NBIDP[13]
FBD1NBIDP[14]
FBD1REFSYSCLKN
FBD1REFSYSCLKP
FBD1SBOCLKCN0
FBD1SBOCLKCP0
FBD1SBOCLKDN0
FBD1SBOCLKDP0
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
AB6
AA6
W7
W6
U5
R2
R3
AE5
AF5
L8
T7
M6
M5
N8
K4
M8
R7
I
I
P7
I
V9
I
L7
V7
I
J7
T8
I
P5
U10
R9
I
R5
I
AC8
AB5
AA7
Y7
P9
I
K9
I
J11
G11
G8
H9
I
I
V6
I
U6
I
T6
F11
L12
M9
Y8
I
N6
L5
I
I
N7
K5
I
W9
V8
I
L6
I
K7
U8
I
P6
U9
I
T5
R8
I
AB8
AD9
AC9
A8
N9
I
K8
I
J10
H11
H8
I
I
A7
I
E4
J9
I
E3
®
®
80
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 17
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 18
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
D12
E8
FBD1SBOCN[0]
FBD1SBOCN[1]
FBD1SBOCN[2]
FBD1SBOCN[3]
FBD1SBOCN[4]
FBD1SBOCN[5]
FBD1SBOCN[6]
FBD1SBOCN[7]
FBD1SBOCN[8]
FBD1SBOCN[9]
FBD1SBOCN[10]
FBD1SBOCP[0]
FBD1SBOCP[1]
FBD1SBOCP[2]
FBD1SBOCP[3]
FBD1SBOCP[4]
FBD1SBOCP[5]
FBD1SBOCP[6]
FBD1SBOCP[7]
FBD1SBOCP[8]
FBD1SBOCP[9]
FBD1SBOCP[10]
FBD1SBODN[0]
FBD1SBODN[1]
FBD1SBODN[2]
FBD1SBODN[3]
FBD1SBODN[4]
FBD1SBODN[5]
FBD1SBODN[6]
FBD1SBODN[7]
FBD1SBODN[8]
FBD1SBODN[9]
FBD1SBODN[10]
FBD1SBODP[0]
FBD1SBODP[1]
FBD1SBODP[2]
FBD1SBODP[3]
FBD1SBODP[4]
FBD1SBODP[5]
FBD1SBODP[6]
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
Differential
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
D6
F6
FBD1SBODP[7]
FBD1SBODP[8]
Differential
Differential
Differential
Differential
O
O
O
O
I
E7
B5
FBD1SBODP[9]
C9
H6
FBD1SBODP[10]
FLASHROM_CFG[0]
FLASHROM_CFG[1]
FLASHROM_CFG[2]
FLASHROM_CLK
C8
N28
M28
L28
N27
B10
C11
A12
C13
B9
I
I
O
O
O
O
O
I
L30
P29
FLASHROM_CS[0]_N
FLASHROM_CS[1]_N
FLASHROM_CS[2]_N
FLASHROM_CS[3]_N
FLASHROM_DATI
FLASHROM_DATO
FLASHROM_WP_N
FORCEPR_N
LRGSCLSYS
MEM_THROTTLE_L
PIR_A0
B13
D11
E9
R29
N29
T28
D7
D9
C7
R28
L27
O
I
K10
M11
K12
AJ25
AJ24
AG24
AH24
AF11
AF12
L10
I
A10
B11
A11
C12
B8
I
I
Power/Other
Power/Other
Power/Other
Power/Other
I
PIR_A1
I
PIR_SCL
I
A13
H1
PIR_SDA
I/O
O
I
PRBMODE_RDY_N
PRBMODE_REQST_N
PROCHOT_N
PROCTYPE
PWRGOOD
RESET_N
G3
G4
F2
O
I
AP1
D2
C4
AR9
V12
AD12
A1
I
Power/Other
I
B6
RSVD
I
D5
F7
RSVD
A2
RSVD
B4
A35
A37
A38
A4
RSVD
G6
H2
RSVD
RSVD
H3
RSVD
G5
F3
AA11
AA27
AC12
AC27
AC28
RSVD
RSVD
E2
RSVD
D4
C6
RSVD
RSVD
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
81
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 19
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 20
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AC29
AD27
AD29
AD30
AE12
AE27
AE30
AG21
AH21
AK12
AL31
AL8
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
C37
D1
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
D38
F1
F38
G1
G38
H13
J20
L13
M13
M20
M21
M36
M4
AM11
AM38
AN11
AN38
AP27
AR1
RSVD
®
®
P10
RSVD (Intel Itanium
Processor 9300 Series)
®
SVID_CLK2 (Intel
®
Itanium Processor
9500 Series)
AR38
AT2
P27
R10
RSVD
®
®
RSVD (Intel Itanium
AT37
AT38
AU1
Processor 9300 Series)
®
SVID_DATIO (Intel
®
Itanium Processor
9500 Series)
R27
T11
RSVD
AU2
®
®
RSVD (Intel Itanium
Processor 9300 Series)
AU3
AU36
AU37
AV1
2
®
SVID_ALERT_N (Intel
®
Itanium Processor
9500 Series)
U4
RSVD
AV2
V27
RSVD
AV35
AV37
AV38
AV4
V29
RSVD
W10
W12
W27
Y10
RSVD
RSVD
RSVD
B2
RSVD
B3
AG29
AH28
AG28
AE28
AT32
AR32
SKTID[0]
SKTID[1]
SKTID[2]
SM_WP
SMBCLK
SMBDAT
I
I
B36
B37
I
B38
I
C1
SMBus
SMBus
I/O
I/O
C2
®
®
82
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 21
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 22
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AT30
AT31
Y12
SPDCLK
SPDDAT
I/O
AG35
AH12
AH22
AH27
AK13
AK17
AK23
AL15
AL25
AL35
AM14
AM19
AM29
AM33
AN12
AP20
AP24
AP34
AR12
AR23
AR28
AR30
AR35
AT25
AU20
C14
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
I/O
SYSCLK
Differential
Differential
Differential
Differential
I
I
AA12
V11
SYSCLK_N
SYSUTST_REFCLK
I
U11
P11
SYSUTST_REFCLK_N
TCK
I
I
P12
TDI
I
N12
TDO
O
I
Y28
TESTHI[1]
TESTHI[2]
TESTHI[4]
THERMALERT_N
THERMTRIP_N
TMS
W29
V28
I
I
A5
O
O
I
A6
R12
AL11
AP11
N11
TRIGGER[0]_N
TRIGGER[1]_N
TRST_N
VCC33_SM
VCC33_SM
VCCA
I/O
I/O
I
AV6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AV7
A27
A28
VCCA
A31
VCCA
A32
VCCA
AV21
AV22
AV26
AV27
AA37
AB28
AB30
AB36
AD11
AD31
AE29
AF10
AF27
AG14
AG18
AG25
VCCA
VCCA
VCCA
C24
VCCA
C29
VCCIO
D32
VCCIO
E14
VCCIO
E27
VCCIO
E34
VCCIO
F16
VCCIO
F23
VCCIO
F35
VCCIO
G13
VCCIO
G29
VCCIO
G34
VCCIO
H17
VCCIO
H19
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
83
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 23
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 24
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
H22
H24
H32
J34
VCCIO
VCCIO
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
H7
J1
VCCIO_FBD
VCCIO_FBD
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCCIO
J4
VCCIO_FBD
VCCIO
N4
VCCIO_FBD
K24
K27
K35
L15
M18
M23
M26
N36
T27
T35
U28
W35
Y27
Y30
Y33
AA1
AA8
AB4
AB9
AC2
AC6
AE4
AE8
AG4
AJ1
VCCIO
T10
T3
VCCIO_FBD
VCCIO
VCCIO_FBD
VCCIO
W5
Y2
VCCIO_FBD
VCCIO
VCCIO_FBD
VCCIO
T12
AN1
K38
H38
VFUSERM
I
VCCIO
VR_FAN_N
O
O
O
I
VCCIO
VR_THERMALERT_N
VR_THERMTRIP_N
VCCIO
VCCIO
AL38
AM1
VROUTPUT_ENABLE0
®
VCCIO
VRPWRGD (Intel
O
®
Itanium Processor
VCCIO
9300 Series)
2
®
VR_READY (Intel
VCCIO
®
Itanium Processor
9500 Series)
VCCIO
A14
A16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCCIO
VCCIO
A19
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
VCCIO_FBD
A24
A29
A3
A34
A36
A9
AA10
AA28
AA29
AA30
AA34
AA4
AJ5
AM4
AN7
AP10
AP5
AR8
AT7
E10
E12
E5
AA5
AA9
AB10
AB11
AB12
AB2
AB27
AB29
AB32
F8
®
®
84
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 25
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 26
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AB37
AB7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AG7
AH10
AH15
AH18
AH20
AH23
AH25
AH26
AH30
AH35
AH5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AC10
AC11
AC30
AC35
AC36
AC5
AC7
AD10
AD28
AD3
AJ12
AJ13
AJ16
AJ18
AJ23
AJ26
AJ28
AJ3
AD33
AD35
AD38
AD8
AE1
AE10
AE11
AE31
AE36
AE6
AJ33
AJ35
AJ38
AJ6
AE9
AF28
AF29
AF34
AF35
AF4
AJ8
AK1
AK11
AK14
AK16
AK21
AK24
AK25
AK26
AK30
AK31
AK35
AK36
AK6
AF9
AG12
AG15
AG17
AG2
AG22
AG23
AG26
AG27
AG32
AG37
AG5
AL14
AL18
AL19
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
85
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 27
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 28
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AL24
AL29
AL34
AL4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AR6
AT1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AT12
AT14
AT19
AT24
AT29
AT34
AT4
AL9
AM12
AM17
AM2
AM22
AM27
AM32
AM34
AM37
AM7
AT9
AU12
AU17
AU22
AU27
AU32
AU38
AU7
AN10
AN15
AN20
AN25
AN30
AN35
AN5
AV10
AV13
AV15
AV18
AV20
AV25
AV3
AN8
AP12
AP13
AP18
AP22
AP23
AP28
AP3
AV30
AV36
AV5
B1
B12
AP33
AP38
AP8
B14
B17
B22
AR11
AR16
AR21
AR24
AR26
AR29
AR31
AR36
B27
B32
B7
C10
C15
C20
C25
C30
®
®
86
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 29
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 30
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
C35
C38
C5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
G17
G2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
G22
G27
G32
G37
G7
D10
D13
D14
D18
D23
D25
D28
D3
H10
H15
H20
H25
H30
H35
H4
D30
D31
D33
D8
H5
E1
J13
J18
J23
J24
J25
J28
J3
E11
E13
E15
E16
E21
E26
E28
E31
E36
E6
J33
J38
J5
J6
F12
F13
F14
F15
F19
F22
F24
F29
F34
F4
J8
K1
K11
K16
K21
K22
K23
K25
K26
K3
F5
K31
K36
K6
F9
G12
G14
L14
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
87
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 31
of 33)
Table 3-1.
Pin List by Pin Name (Sheet 32
of 33)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
L16
L17
L19
L23
L24
L25
L26
L29
L34
L35
L4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
R6
T29
T34
T4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
T9
U12
U2
U27
U3
U32
U35
U37
U7
L9
M12
M16
M17
M19
M2
V10
V30
V35
V5
M22
M24
M25
M27
M32
M37
M7
W11
W28
W3
W33
W38
W8
Y1
N10
N30
N35
N5
Y11
Y29
Y31
Y36
Y5
P28
P3
Y6
P33
P35
P38
P4
AJ11
AH11
AH8
XDPOCP_STRB_IN_N
XDPOCP_STRB_OUT_N
XDPOCPD[0]_N
XDPOCPD[1]_N
XDPOCPD[2]_N
XDPOCPD[3]_N
XDPOCPD[4]_N
XDPOCPD[5]_N
XDPOCPD[6]_N
XDPOCPD[7]_N
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AG8
P8
AJ9
R1
AG9
R11
R31
R36
R4
AH9
AG10
AJ10
AK10
®
®
88
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-1.
Pin List by Pin Name (Sheet 33
of 33)
Pin
Number
Signal
Buffer Type
Pin Name
Direction
AG11
XDPOCPFRAME_N
I/O
3.1.2
Pin Listing by Pin Number
Table 3-2.
Pin List by Pin Number (Sheet 2
of 32)
Table 3-2.
Pin List by Pin Number (Sheet 1
of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
A34
A35
VSS
RSVD
Power/Other
A1
A2
RSVD
RSVD
A36
VSS
Power/Other
A3
VSS
Power/Other
A37
RSVD
A4
RSVD
A38
RSVD
A5
THERMALERT_N
THERMTRIP_N
FBD1SBOCLKCP0
FBD1SBOCLKCN0
VSS
O
O
O
O
AA1
VCCIO_FBD
FBD0SBOBN[8]
FBD0SBOBP[8]
VSS
Power/Other
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Power/Other
Power/Other
Power/Other
A6
AA2
O
O
A7
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Power/Other
Power/Other
Power/Other
Differential
Power/Other
Power/Other
Differential
AA3
A8
AA4
A9
AA5
VSS
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
FBD1SBOCP[5]
FBD1SBOCP[7]
FBD1SBOCN[7]
FBD1SBOCP[10]
VSS
O
O
O
O
AA6
FBD1NBIDN[1]
FBD1NBIDP[1]
VCCIO_FBD
VSS
I
I
AA7
AA8
AA9
AA10
AA11
AA12
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB1
VSS
CSI4RPDAT[0]
VSS
I
RSVD
SYSCLK_N
RSVD
Differential
I
CSI4RNDAT[3]
CSI4RPDAT[3]
VSS
I
I
VSS
Power/Other
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
VSS
CSI2RPDAT[8]
CSI2RNCLK
CSI2RPCLK
CSI2RPDAT[10]
VSS
I
I
I
I
VSS
CSI3TNDAT[18]
CSI3TNDAT[19]
CSI3TPDAT[19]
VSS
O
O
O
CSI2RNDAT[13]
CSI2RPDAT[13]
VCCA
I
I
CSI1TNDAT[18]
CSI1TPDAT[18]
VCCIO
O
O
VCCA
CSI1RNDAT[18]
FBD0NBIBN[11]
VSS
I
I
VSS
CSI2RPDAT[17]
VCCA
I
I
AB2
AB3
FBD0SBOBN[6]
VCCIO_FBD
O
VCCA
AB4
CSI0RPDAT[0]
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
89
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet 3
of 32)
Table 3-2.
Pin List by Pin Number (Sheet 4
of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AB5
AB6
FBD1NBIDP[0]
FBD1NBIDN[0]
VSS
Differential
Differential
Power/Other
Differential
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Differential
Power/Other
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Power/Other
Power/Other
Power/Other
Differential
Differential
Power/Other
Power/Other
I
I
AC35
AC36
AC37
AC38
AD1
VSS
VSS
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Power/Other
AB7
CSI1RNDAT[17]
CSI1RPDAT[17]
FBD0NBIBN[10]
FBD0NBIBP[10]
VSS
I
I
I
I
AB8
FBD1NBIDP[14]
VCCIO_FBD
VSS
I
AB9
AB10
AB11
AB12
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AB35
AB36
AB37
AB38
AC1
AD2
VSS
AD3
VSS
AD4
FBD0SBOBP[5]
FBD0SBOBP[7]
FBD0SBOBN[7]
FBD0SBOBN[9]
VSS
O
O
O
O
VSS
AD5
VCCIO
AD6
VSS
AD7
VCCIO
AD8
CSI3TPDAT[18]
VSS
O
AD9
FBD1REFSYSCLKN
VSS
I
AD10
AD11
AD12
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE1
CSI3TNDAT[17]
CSI1TNDAT[17]
CSI1TPDAT[17]
VCCIO
O
O
O
VCCIO
RSVD
RSVD
VSS
Power/Other
VSS
RSVD
CSI1RPDAT[18]
FBD0NBIBP[11]
VCCIO_FBD
FBD0SBOBP[6]
FBD0SBOBN[5]
VSS
I
I
RSVD
VCCIO
Power/Other
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Power/Other
Power/Other
Power/Other
Power/Other
AC2
CSI3TNDAT[15]
VSS
O
O
AC3
O
O
AC4
CSI1TPDAT[16]
VSS
AC5
AC6
VCCIO_FBD
VSS
CSI1RNDAT[16]
CSI1RPDAT[16]
VSS
I
I
AC7
AC8
FBD1NBIDN[14]
FBD1REFSYSCLKP
VSS
I
I
AC9
VSS
AC10
AC11
AC12
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AE2
FBD0NBIBP[9]
FBD0NBIBN[9]
VCCIO_FBD
FBD0SBOCLKBN0
VSS
I
I
VSS
AE3
RSVD
AE4
RSVD
AE5
O
O
RSVD
AE6
RSVD
AE7
FBD0SBOBP[9]
VCCIO_FBD
VSS
VSS
Power/Other
Differential
Differential
Differential
Differential
AE8
CSI3TNDAT[16]
CSI3TPDAT[16]
CSI3TPDAT[17]
CSI1TNDAT[16]
O
O
O
O
AE9
AE10
AE11
AE12
VSS
VSS
RSVD
®
®
90
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet 5
of 32)
Table 3-2.
Pin List by Pin Number (Sheet 6
of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AE36
AE37
AE38
AF1
RSVD
SM_WP
AG5
AG6
VSS
FBD0SBOBP[4]
VSS
Power/Other
Differential
Power/Other
I
O
VCCIO
Power/Other
AG7
RSVD
AG8
XDPOCPD[1]_N
XDPOCPD[3]_N
XDPOCPD[5]_N
XDPOCPFRAME_N
VSS
I/O
I/O
I/O
I/O
VSS
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
AG9
CSI3TPDAT[15]
CSI1TNDAT[14]
CSI1TNDAT[15]
CSI1TPDAT[15]
VSS
O
O
O
O
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AG31
AG32
AG33
AG34
AG35
AG36
AG37
AG38
AH1
Power/Other
Differential
Power/Other
Power/Other
Differential
Power/Other
Power/Other
Differential
Differential
CSI5TNDAT[0]
VCCIO
O
O
CSI1RNDAT[15]
CSI1RPDAT[15]
FBD0NBIBP[8]
FBD0NBIBN[8]
FBD0NBIBN[7]
VSS
I
I
I
I
I
VSS
CSI5TNDAT[3]
VSS
AF2
VCCIO
AF3
CSI5TNDAT[7]
CSI5TPDAT[7]
RSVD
O
O
AF4
AF5
FBD0SBOCLKBP0
FBD0SBOBN[4]
FBD0SBOBN[3]
FBD0SBOBP[3]
VSS
O
O
O
O
AF6
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AF7
VSS
AF8
PIR_SCL
I
AF9
VCCIO
AF10
AF11
VCCIO
VSS
PRBMODE_RDY_N
O
I
VSS
AF12
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AF36
AF37
AF38
AG1
PRBMODE_REQST_N
VCCIO
SKTID[2]
I
I
Power/Other
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
SKTID[0]
VSS
CSI3TPDAT[13]
CSI3TNDAT[12]
VSS
Differential
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Differential
Differential
Differential
Power/Other
Differential
O
O
VSS
CSI3TNDAT[13]
CSI3TNDAT[14]
CSI3TPDAT[14]
CSI1TPDAT[14]
VSS
O
O
O
O
CSI1TNDAT[13]
CSI1TPDAT[13]
VCCIO
O
O
CSI1RNDAT[12]
VSS
I
VSS
CSI1RNDAT[14]
CSI1RPDAT[14]
CSI1RNDAT[13]
FBD0NBIBN[6]
VSS
I
I
I
I
CSI1RPDAT[13]
FBD0NBIBP[6]
FBD0NBIBN[12]
FBD0NBICLKBN0
FBD0NBICLKBP0
VSS
I
I
I
I
I
AH2
AH3
AG2
AH4
AG3
FBD0NBIBP[7]
VCCIO_FBD
I
AH5
AG4
AH6
FBD0SBOBN[2]
O
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
91
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet 7
of 32)
Table 3-2.
Pin List by Pin Number (Sheet 8
of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AH7
AH8
FBD0SBOBP[2]
XDPOCPD[0]_N
XDPOCPD[4]_N
VSS
Differential
O
AJ9
XDPOCPD[2]_N
XDPOCPD[6]_N
I/O
I/O
I
I/O
I/O
AJ10
AH9
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AJ37
AJ38
AK1
XDPOCP_STRB_IN_N
VSS
AH10
Power/Other
Power/Other
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Power/Other
Power/Other
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AH33
AH34
AH35
AH36
AH37
AH38
AJ1
XDPOCP_STRB_OUT_N
VCCIO
O
VSS
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
CSI5TPDAT[1]
CSI5TNDAT[2]
VSS
O
O
CSI5TPDAT[0]
CSI5TNDAT[1]
VSS
O
O
CSI5TPDAT[4]
VSS
O
CSI5TPDAT[3]
CSI5TNDAT[4]
VSS
O
O
CSI5TPDAT[5]
CSI5TNDAT[8]
CSI5TPDAT[8]
CSI5TNCLK
VSS
O
O
O
O
CSI5TNDAT[5]
VSS
O
RSVD
VCCIO
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
PIR_A1
I
I
VSS
PIR_A0
PIR_SDA
I/O
VSS
VSS
CSI3TNDAT[9]
VSS
O
VSS
VCCIO
CSI3TPDAT[10]
CSI3TNDAT[11]
CSI3TPDAT[11]
CSI1TNCLK
VSS
O
O
O
O
SKTID[1]
I
CSI3TNDAT[10]
VSS
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Power/Other
Power/Other
Differential
Power/Other
O
CSI3TPDAT[12]
CSI1TNDAT[12]
CSI1TPDAT[12]
CSI1TNDAT[11]
VSS
O
O
O
O
CSI1TPDAT[11]
VSS
O
CSI1RPDAT[10]
CSI1RNDAT[10]
VSS
I
I
CSI1RPDAT[12]
CSI1RPDAT[11]
CSI1RNDAT[11]
VCCIO_FBD
FBD0NBIBP[12]
VSS
I
I
I
VSS
AK2
FBD0NBIAN[11]
FBD0NBIAP[11]
FBD0NBIBP[13]
FBD0NBIBN[5]
VSS
I
I
I
I
AK3
AJ2
I
I
AK4
AJ3
AK5
AJ4
FBD0NBIBN[13]
VCCIO_FBD
VSS
AK6
AJ5
AK7
FBD0SBOBP[1]
FBD0SBOBN[0]
FBD0SBOBP[0]
XDPOCPD[7]_N
O
O
AJ6
AK8
AJ7
FBD0SBOBN[1]
VSS
O
AK9
O
AJ8
AK10
I/O
®
®
92
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet 9
of 32)
Table 3-2.
Pin List by Pin Number (Sheet
10 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL1
VSS
RSVD
Power/Other
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AL36
AL37
CSI5RPDAT[0]
VSS
Differential
Power/Other
Power/Other
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Differential
I
VCCIO
Power/Other
Power/Other
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Power/Other
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Power/Other
Differential
VCCIO
VSS
CSI3RPDAT[1]
CSI3RNDAT[1]
VSS
I
I
CSI5TPDAT[2]
VSS
O
VCCIO
VSS
CSI5TNDAT[6]
CSI5TPDAT[6]
CSI3TPDAT[0]
VSS
O
O
O
CSI3TNDAT[0]
CSI5TNDAT[9]
CSI5TPDAT[9]
CSI3TPDAT[2]
VSS
O
O
O
O
CSI5TPCLK
VCCIO
O
VCCIO
VSS
CSI1TPDAT[0]
CSI1TNDAT[0]
CSI1TNDAT[2]
VSS
O
O
O
VSS
VSS
CSI3TPDAT[9]
CSI3TPCLK
CSI3TNCLK
VSS
O
O
O
CSI1TNDAT[5]
RSVD
O
CSI1TPDAT[9]
CSI1TNDAT[9]
VSS
Differential
Differential
Power/Other
Power/Other
Differential
Differential
O
O
VSS
CSI1TPCLK
CSI1TNDAT[10]
CSI1TPDAT[10]
VSS
O
O
O
VCCIO
CSI1RPDAT[9]
CSI1RNDAT[9]
I
I
VSS
AL38
AM1
VROUTPUT_ENABLE0
I
®
CSI1RPCLK
CSI1RNCLK
FBD0NBIAN[10]
FBD0NBIAP[10]
FBD0NBIAN[9]
VSS
I
I
I
I
I
VRPWRGD (Intel
O
®
Itanium Processor
9300 Series) VR_READY
®
®
(Intel Itanium
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Processor 9500 Series)
AL2
AM2
AM3
AM4
AM5
AM6
AM7
AM8
AM9
AM10
AM11
AM12
VSS
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Differential
AL3
FBD0NBIAP[9]
VCCIO_FBD
FBD0NBIBN[4]
FBD0NBIBP[4]
VSS
I
AL4
AL5
FBD0NBIBP[5]
FBD0REFSYSCLKN
FBD0REFSYSCLKP
RSVD
I
I
I
I
I
AL6
AL7
AL8
FBD0NBIBP[1]
FBD0NBIBN[1]
FBD0NBIBN[14]
RSVD
I
I
I
AL9
VSS
Power/Other
Differential
AL10
AL11
AL12
FBD0NBIBP[14]
TRIGGER[0]_N
CSI5RNDAT[0]
I
I/O
I
Differential
VSS
Power/Other
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
93
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
11 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
12 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM37
AM38
AN1
CSI5RNDAT[1]
VCCIO
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Power/Other
Power/Other
Differential
Differential
Power/Other
I
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP1
VSS
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
CSI3RPDAT[3]
CSI3RNDAT[3]
CSI3RNDAT[0]
CSI3RPDAT[4]
VSS
I
I
I
I
CSI3RPDAT[2]
CSI3RNDAT[2]
VSS
I
I
CSI3RPDAT[0]
VCCIO
I
CSI3TNDAT[3]
CSI3TPDAT[4]
CSI3TNDAT[4]
CSI3TPDAT[5]
VSS
O
O
O
O
CSI3TNDAT[1]
CSI3TPDAT[1]
VSS
O
O
CSI3TNDAT[2]
CSI3TNDAT[5]
CSI3TPDAT[8]
CSI3TNDAT[8]
VSS
O
O
O
O
CSI3TNDAT[7]
CSI1TPDAT[1]
CSI1TNDAT[1]
CSI1TNDAT[3]
VSS
O
O
O
O
CSI1TPDAT[2]
VCCIO
O
CSI1TPDAT[8]
CSI1TNDAT[6]
CSI1TPDAT[7]
CSI1TNDAT[7]
VSS
O
O
O
O
CSI1TPDAT[5]
CSI1TNDAT[8]
VSS
O
O
VCCIO
VSS
CSI1RPDAT[7]
CSI1RNDAT[7]
RSVD
I
I
CSI1RPDAT[8]
CSI1RNDAT[8]
VSS
I
I
PROCTYPE
I
I
RSVD
AP2
FBD0NBIAP[7]
VSS
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
VR_FAN_N
FBD0NBIAN[7]
FBD0NBIAN[8]
FBD0NBIAP[8]
VSS
O
I
AP3
AN2
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Power/Other
Differential
Power/Other
AP4
FBD0NBIAN[6]
VCCIO_FBD
FBD0NBIBN[3]
FBD0NBIBN[2]
VSS
I
AN3
I
AP5
AN4
I
AP6
I
I
AN5
AP7
AN6
FBD0NBIBP[3]
VCCIO_FBD
VSS
I
I
AP8
AN7
AP9
FBD0NBIBP[0]
VCCIO_FBD
TRIGGER[1]_N
VSS
I
AN8
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AN9
FBD0NBIBN[0]
VSS
I/O
AN10
AN11
AN12
AN13
AN14
Power/Other
Power/Other
Differential
Differential
Differential
RSVD
VSS
VCCIO
Power/Other
Differential
Differential
CSI5RPDAT[2]
CSI5RNDAT[3]
CSI5RPDAT[3]
I
I
I
CSI5RPDAT[1]
CSI5RNDAT[2]
I
I
®
®
94
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
13 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
14 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AR1
CSI5RNCLK
VSS
Differential
Power/Other
Differential
Power/Other
Differential
Power/Other
Power/Other
Power/Other
Differential
Differential
I
AR19
AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AT1
CSI3RNDAT[5]
CSI3RPDAT[9]
VSS
Differential
Differential
Power/Other
Differential
Power/Other
Power/Other
Differential
Power/Other
Differential
Power/Other
Power/Other
Power/Other
Power/Other
SMBus
I
I
CSI3RNDAT[4]
VCCIO
I
CSI3RPDAT[10]
VCCIO
I
CSI3TPDAT[3]
VSS
O
VSS
VSS
CSI3TPDAT[6]
VSS
O
I
VCCIO
CSI3TNDAT[6]
CSI3TPDAT[7]
RSVD
O
O
CSI3RPDAT[15]
VCCIO
VSS
VSS
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
VCCIO
CSI1TPDAT[3]
CSI1TPDAT[4]
CSI1TNDAT[4]
CSI1TPDAT[6]
VSS
O
O
O
O
VSS
SMBDAT
I/O
CSI1RPDAT[3]
CSI1RNDAT[3]
VCCIO
Differential
Differential
Power/Other
Power/Other
Differential
I
I
VCCIO
VSS
CSI1RPDAT[5]
CSI1RNDAT[5]
CSI1RNDAT[6]
VSS
I
I
I
CSI1RPDAT[6]
RSVD
I
VSS
Power/Other
AT2
RSVD
RSVD
AT3
CPU_PRES4_N
VSS
I/O
AR2
FBD0NBIAN[12]
FBD0NBIAP[12]
FBD0NBIAP[6]
FBD0NBICLKAN0
VSS
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
I
I
I
I
AT4
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
AR3
AT5
FBD0NBICLKAP0
FBD0NBIAN[5]
VCCIO_FBD
FBD0NBIAN[4]
VSS
I
I
AR4
AT6
AR5
AT7
AR6
AT8
I
AR7
FBD0NBIBP[2]
VCCIO_FBD
PWRGOOD
FBD0NBIAN[3]
VSS
I
AT9
AR8
AT10
AT11
AT12
AT13
AT14
AT15
AT16
AT17
AT18
AT19
AT20
FBD0NBIAP[3]
FBD0NBIAN[0]
VSS
I
I
AR9
I
I
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR17
AR18
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Differential
Differential
CSI5RNDAT[5]
VSS
I
VCCIO
CSI5RNDAT[4]
CSI5RPDAT[4]
CSI5RNDAT[7]
VSS
I
I
I
CSI5RPDAT[7]
CSI5RNDAT[9]
CSI5RPDAT[9]
CSI3RPDAT[7]
VSS
I
I
I
I
CSI5RPCLK
CSI3RPDAT[5]
I
I
CSI3RNDAT[9]
I
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
95
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
15 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
16 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AT21
AT22
AT23
AT24
AT25
AT26
AT27
AT28
AT29
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU1
CSI3RPCLK
CSI3RNDAT[10]
CSI3RPDAT[11]
VSS
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
I
I
I
AU23
AU24
AU25
AU26
AU27
AU28
AU29
AU30
AU31
AU32
AU33
AU34
AU35
AU36
AU37
AU38
AV1
CSI3RNDAT[11]
CSI3RPDAT[13]
CSI3RNDAT[13]
CSI3RNDAT[14]
VSS
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
I
I
I
I
VCCIO
CSI3RPDAT[14]
CSI3RNDAT[15]
CSI3RPDAT[16]
VSS
I
I
I
CSI3RNDAT[16]
CSI3RPDAT[18]
CSI3RNDAT[18]
CSI3RPDAT[19]
VSS
I
I
I
I
SPDCLK
I/O
I/O
I/O
I
SPDDAT
CSI1RNDAT[0]
CSI1RPDAT[2]
CSI1RPDAT[4]
RSVD
I
I
I
SMBCLK
SMBus
CSI1RPDAT[0]
VSS
Differential
Power/Other
Differential
CSI1RNDAT[4]
CPU_PRES3_N
RSVD
I
RSVD
I/O
VSS
Power/Other
Power/Other
RSVD
RSVD
AV2
RSVD
RSVD
AV3
VSS
AU2
RSVD
AV4
RSVD
AU3
RSVD
AV5
VSS
Power/Other
Power/Other
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
Power/Other
Power/Other
Differential
Differential
AU4
FBD0NBIAN[13]
FBD0NBIAP[13]
FBD0NBIAP[5]
VSS
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
I
I
I
AV6
VCC33_SM
VCC33_SM
FBD0NBIAN[2]
FBD0NBIAP[2]
VSS
AU5
AV7
AU6
AV8
I
I
AU7
AV9
AU8
FBD0NBIAP[4]
FBD0NBIAN[1]
FBD0NBIAP[1]
FBD0NBIAP[0]
VSS
I
I
I
I
AV10
AV11
AV12
AV13
AV14
AV15
AV16
AV17
AV18
AV19
AV20
AV21
AV22
AV23
AV24
AU9
FBD0NBIAN[14]
FBD0NBIAP[14]
VSS
I
I
AU10
AU11
AU12
AU13
AU14
AU15
AU16
AU17
AU18
AU19
AU20
AU21
AU22
CSI5RPDAT[6]
VSS
I
CSI5RPDAT[5]
CSI5RNDAT[6]
CSI5RNDAT[8]
CSI5RPDAT[8]
VSS
I
I
I
I
CSI3RPDAT[6]
CSI3RNDAT[6]
VSS
I
I
CSI3RNDAT[8]
VSS
I
CSI3RNDAT[7]
CSI3RPDAT[8]
VCCIO
I
I
VCCA
VCCA
CSI3RNCLK
VSS
I
CSI3RPDAT[12]
CSI3RNDAT[12]
I
I
®
®
96
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
17 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
18 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
AV25
AV26
AV27
AV28
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AV37
AV38
B1
VSS
VCCA
Power/Other
Power/Other
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
C1
VSS
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
CSI2RNDAT[16]
CSI2RPDAT[16]
CSI2RNDAT[17]
CSI2RPDAT[18]
VSS
I
I
I
I
VCCA
CSI3RPDAT[17]
CSI3RNDAT[17]
VSS
I
I
CSI3RNDAT[19]
CSI1RPDAT[1]
CSI1RNDAT[1]
CSI1RNDAT[2]
RSVD
I
I
I
I
CSI0RNDAT[0]
CSI0RNDAT[2]
CSI0RPDAT[2]
RSVD
I
I
I
RSVD
VSS
Power/Other
Power/Other
RSVD
RSVD
RSVD
RSVD
C2
RSVD
VSS
C3
CPU_PRES1_N
FBD1SBODN[5]
VSS
I/O
O
B2
RSVD
C4
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
B3
RSVD
C5
B4
FBD1SBODN[9]
FBD1SBODP[9]
FBD1SBODN[6]
VSS
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
O
O
O
C6
FBD1SBODP[6]
FBD1SBOCP[4]
FBD1SBOCN[4]
FBD1SBOCN[3]
VSS
O
O
O
O
B5
C7
B6
C8
B7
C9
B8
FBD1SBOCP[9]
FBD1SBOCN[9]
FBD1SBOCN[5]
FBD1SBOCP[6]
VSS
O
O
O
O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
B9
FBD1SBOCN[6]
FBD1SBOCP[8]
FBD1SBOCN[8]
VCCIO
O
O
O
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
FBD1SBOCN[10]
VSS
O
VSS
CSI4RNDAT[2]
CSI4RNDAT[5]
CSI4RPDAT[5]
CSI4RPDAT[6]
VSS
I
I
I
I
CSI4RNDAT[0]
CSI4RPDAT[2]
VSS
I
I
CSI4RNDAT[4]
CSI4RPDAT[4]
CSI2RNDAT[8]
CSI2RPDAT[7]
VSS
I
I
I
I
CSI2RNDAT[7]
CSI2RNDAT[9]
CSI2RPDAT[9]
VCCIO
I
I
I
CSI2RNDAT[10]
CSI2RPDAT[11]
CSI2RNDAT[11]
CSI2RPDAT[12]
I
I
I
I
VSS
CSI2RNDAT[12]
CSI2RNDAT[15]
CSI2RPDAT[15]
I
I
I
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
97
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
19 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
20 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
D1
VCCIO
VSS
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
D31
D32
D33
D34
D35
D36
D37
D38
E1
VSS
VCCIO
Power/Other
Power/Other
Power/Other
Differential
Differential
Differential
CSI2RNDAT[18]
CSI2RPDAT[19]
CSI2RNDAT[19]
CSI0RPDAT[1]
VSS
I
I
I
I
VSS
CSI0RNDAT[1]
CSI0RNDAT[3]
CSI0RPDAT[4]
CPU_PRES2_N
RSVD
I
I
I
I/O
CSI0RNDAT[4]
RSVD
I
VSS
Power/Other
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Power/Other
Differential
Differential
Power/Other
Differential
Differential
VSS
Power/Other
E2
FBD1SBODP[4]
FBD1SBOCLKDP0
FBD1SBOCLKDN0
VCCIO_FBD
VSS
O
O
O
RSVD
E3
D2
FBD1SBODN[4]
VSS
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
O
E4
D3
E5
D4
FBD1SBODP[5]
FBD1SBODN[7]
FBD1SBODP[7]
FBD1SBOCP[2]
VSS
O
O
O
O
E6
D5
E7
FBD1SBOCN[2]
FBD1SBOCN[1]
VCCIO_FBD
VSS
O
O
D6
E8
D7
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
D8
D9
FBD1SBOCP[3]
VSS
O
VCCIO_FBD
VSS
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
FBD1SBOCP[0]
FBD1SBOCN[0]
VSS
O
O
VCCIO
VSS
VSS
VSS
CSI4RNDAT[7]
CSI4RNDAT[8]
CSI4RPDAT[8]
CSI2RNDAT[5]
VSS
I
I
I
I
CSI4RNDAT[1]
CSI4RPDAT[1]
CSI4RPDAT[7]
VSS
I
I
I
CSI4RNDAT[6]
CSI2RPDAT[5]
CSI2RNDAT[6]
CSI2RPDAT[6]
VSS
I
I
I
I
CSI2RPDAT[4]
CSI2RNDAT[4]
CSI2TPDAT[3]
CSI2TPDAT[2]
VSS
I
I
O
O
CSI2TNDAT[3]
VSS
O
VCCIO
VSS
CSI2RNDAT[14]
CSI2RPDAT[14]
VSS
I
I
CSI2TNDAT[6]
CSI0TPDAT[3]
VSS
O
O
CSI2TPDAT[6]
VSS
O
CSI0TNDAT[6]
CSI0TPDAT[6]
O
O
®
®
98
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
21 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
22 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
E34
E35
E36
E37
E38
E9
VCCIO
CSI0RPDAT[3]
VSS
Power/Other
Differential
Power/Other
Differential
Differential
Differential
F35
F36
F37
F38
G1
VCCIO
CSI0RNDAT[6]
CSI0RPDAT[6]
RSVD
Power/Other
Differential
Differential
I
I
I
CSI0RNDAT[5]
CSI0RPDAT[5]
FBD1SBOCP[1]
RSVD
I
I
RSVD
O
G2
VSS
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
F1
G3
FBD1SBODN[1]
FBD1SBODN[2]
FBD1SBODP[2]
FBD1SBODN[10]
VSS
O
O
O
O
F2
FBD1SBODN[3]
FBD1SBODP[3]
VSS
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Power/Other
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
O
O
G4
F3
G5
F4
G6
F5
VSS
G7
F6
FBD1SBODP[8]
FBD1SBODN[8]
VCCIO_FBD
VSS
O
O
G8
FBD1NBICN[9]
BOOTMODE[1]
BOOTMODE[0]
FBD1NBICN[8]
VSS
I
I
I
I
F7
G9
F8
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
F9
Differential
Power/Other
Power/Other
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
FBD1NBICP[11]
FBD1NBICN[11]
VSS
I
I
VCCIO
VSS
VSS
CSI4TNDAT[4]
CSI4TPDAT[4]
VSS
O
O
VSS
VSS
VCCIO
CSI4RPCLK
CSI2RPDAT[2]
CSI2RNDAT[2]
CSI2RPDAT[1]
VSS
I
I
I
I
CSI4RNDAT[9]
CSI4RPDAT[9]
VSS
I
I
CSI2RPDAT[3]
CSI2RNDAT[3]
VSS
I
I
CSI2TPDAT[0]
CSI2TNDAT[1]
CSI2TPDAT[1]
CSI2TPDAT[4]
VSS
O
O
O
O
VCCIO
VSS
CSI2TNDAT[2]
CSI2TNDAT[5]
CSI2TPDAT[5]
CSI2TNDAT[8]
VSS
O
O
O
O
CSI2TPDAT[8]
VCCIO
O
CSI0TPDAT[2]
CSI0TNDAT[2]
VSS
O
O
CSI0TNDAT[3]
CSI0TNDAT[5]
CSI0TPDAT[5]
CSI0TNDAT[7]
VSS
O
O
O
O
CSI0TPDAT[7]
VCCIO
O
CSI0RNDAT[7]
CSI0RPDAT[7]
I
I
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
99
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
23 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
24 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
G37
G38
H1
VSS
RSVD
Power/Other
J1
VCCIO_FBD
FBD0SBOAN[10]
VSS
Power/Other
Differential
Power/Other
Power/Other
Power/Other
Power/Other
Differential
Power/Other
Differential
Differential
Differential
J2
O
FBD1SBODN[0]
FBD1SBODP[0]
FBD1SBODP[1]
VSS
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
O
O
O
J3
H2
J4
VCCIO_FBD
VSS
H3
J5
H4
J6
VSS
H5
VSS
J7
FBD1NBIDN[11]
VSS
I
H6
FBD1SBODP[10]
VCCIO_FBD
FBD1NBICP[9]
FBD1NBICN[10]
VSS
O
J8
H7
J9
FBD1NBICP[10]
FBD1NBICP[7]
FBD1NBICN[7]
ERROR[1]_N
VSS
I
I
H8
I
I
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
K1
H9
I
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
O
FBD1NBICP[8]
ERROR[0]_N
RSVD
I
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
O
CSI4TNDAT[3]
CSI4TPDAT[2]
CSI4TNDAT[5]
CSI4TPDAT[6]
VSS
O
O
O
O
CSI4TPDAT[3]
VSS
Differential
Power/Other
Differential
Power/Other
Differential
Power/Other
Power/Other
Differential
Power/Other
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Differential
O
O
I
CSI4TPDAT[5]
VCCIO
CSI4TPDAT[8]
RSVD
O
CSI4RNCLK
VCCIO
CSI2RPDAT[0]
CSI2RNDAT[0]
VSS
Differential
Differential
Power/Other
Power/Other
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Power/Other
Differential
I
I
VSS
CSI2RNDAT[1]
VCCIO
I
VSS
CSI2TNDAT[0]
VCCIO
O
VSS
CSI2TNDAT[7]
CSI2TPDAT[7]
VSS
O
O
VSS
CSI2TNDAT[4]
CSI2TNDAT[9]
CSI2TPDAT[9]
CSI2TNCLK
VSS
O
O
O
O
CSI2TPCLK
CSI0TPDAT[0]
CSI0TNDAT[1]
CSI0TPDAT[4]
VSS
O
O
O
O
CSI0TPDAT[1]
VCCIO
O
VCCIO
CSI0TNDAT[8]
CSI0TPDAT[8]
VSS
O
O
CSI0RNDAT[9]
CSI0RPDAT[9]
CSI0RNCLK
VSS
I
I
I
CSI0RNDAT[8]
CSI0RPDAT[8]
VR_THERMTRIP_N
I
I
VSS
O
K2
FBD0SBOAP[10]
O
®
®
100
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
25 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
26 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
K3
K4
VSS
FBD1NBIDN[9]
FBD1NBIDP[9]
VSS
Power/Other
Differential
Differential
Power/Other
Differential
Differential
Differential
L5
FBD1NBIDP[7]
FBD1NBIDP[10]
FBD1NBIDN[10]
FBD1NBICLKCN0
VSS
Differential
Differential
Differential
Differential
Power/Other
I
I
I
I
I
I
L6
K5
L7
K6
L8
K7
FBD1NBIDP[11]
FBD1NBICP[6]
FBD1NBICN[6]
FORCEPR_N
VSS
I
I
I
I
L9
K8
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
PROCHOT_N
FBD1NBICP[12]
FBD1NBICN[12]
RSVD
O
I
K9
Differential
Differential
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
K35
K36
K37
K38
L1
I
Power/Other
MEM_THROTTLE_L
CSI4TNDAT[1]
CSI4TPDAT[1]
CSI4TNDAT[2]
VSS
I
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Differential
Power/Other
Differential
Differential
Differential
Power/Other
Power/Other
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Power/Other
Power/Other
Differential
O
O
O
VCCIO
VSS
VSS
CSI4TNDAT[7]
VSS
O
CSI4TNDAT[6]
CSI4TPDAT[7]
CSI4TNDAT[8]
CSI4TPDAT[9]
VSS
O
O
O
O
CSI4TNDAT[9]
CSI4TNCLK
CSI4TPCLK
VSS
O
O
O
VSS
VSS
VSS
VSS
VCCIO
VSS
VSS
FLASHROM_WP_N
FLASHROM_CFG[2]
VSS
I
I
VSS
VCCIO
Power/Other
CSI2TNDAT[10]
CSI2TPDAT[10]
CSI0TNDAT[0]
VSS
O
O
O
L30
L31
L32
L33
L34
L35
L36
L37
L38
M1
FLASHROM_CS[0]_N
CSI0TNDAT[9]
CSI0TPDAT[9]
CSI0TNDAT[10]
VSS
O
O
O
O
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
CSI0TNDAT[4]
CSI0TNCLK
CSI0TPCLK
VCCIO
O
O
O
VSS
CSI0RNDAT[10]
CSI0RPDAT[10]
CSI0RNDAT[11]
FBD0SBOAN[6]
VSS
I
I
VSS
I
CSI0RPCLK
VR_THERMALERT_N
FBD0SBOAN[8]
FBD0SBOAP[8]
FBD0SBOAN[7]
VSS
I
O
O
O
O
O
M2
Differential
Differential
Differential
Power/Other
M3
FBD0SBOAP[7]
RSVD
O
L2
M4
L3
M5
FBD1NBIDN[7]
FBD1NBIDN[6]
Differential
Differential
I
I
L4
M6
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
101
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
27 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
28 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
M7
M8
VSS
FBD1NBICLKCP0
FBD1NBICN[13]
FBD1NBICP[13]
LRGSCLSYS
VSS
Power/Other
Differential
Differential
Differential
N9
FBD1NBICP[5]
VSS
Differential
I
I
I
I
I
N10
N11
N12
N27
N28
Power/Other
M9
TRST_N
I
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
M31
M32
M33
M34
M35
M36
M37
M38
N1
TDO
O
O
I
FLASHROM_CLK
FLASHROM_CFG[0]
Power/Other
RSVD
N29
N30
N31
N32
N33
N34
N35
N36
N37
N38
P1
FLASHROM_CS[3]_N
VSS
O
CSI4TNDAT[0]
CSI4TPDAT[0]
VSS
Differential
Differential
O
O
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Differential
CSI2TPDAT[13]
CSI0TNDAT[12]
CSI0TPDAT[12]
CSI0TNDAT[13]
VSS
O
O
O
O
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VCCIO
VSS
RSVD
VCCIO
RSVD
CSI0RNDAT[12]
CSI0RPDAT[12]
FBD0SBOAN[9]
FBD0SBOAP[9]
VSS
I
I
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCCIO
O
O
VSS
P2
VSS
P3
VCCIO
P4
VSS
VSS
P5
FBD1NBIDN[12]
FBD1NBIDP[12]
FBD1NBICLKDP0
VSS
I
I
I
FLASHROM_CFG[1]
CSI2TNDAT[11]
CSI2TPDAT[11]
CSI2TNDAT[13]
VSS
I
P6
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
O
O
O
P7
P8
P9
FBD1NBICN[5]
I
1
®
®
P10
RSVD (Intel
Itanium Processor
9300 Series)
CSI0TPDAT[10]
CSI0TNDAT[11]
CSI0TPDAT[11]
RSVD
O
O
O
2
®
SVID_CLK2 (Intel
®
Itanium Processor
9500 Series)
P11
P12
P27
P28
P29
P30
P31
P32
P33
P34
P35
TCK
TDI
I
I
VSS
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
CSI0RPDAT[11]
FBD0SBOAP[6]
FBD0SBOAP[5]
FBD0SBOAN[5]
VCCIO_FBD
VSS
I
RSVD
O
O
O
VSS
Power/Other
N2
FLASHROM_CS[1]_N
CSI2TNDAT[12]
CSI2TPDAT[12]
CSI2TNDAT[15]
VSS
O
O
O
O
N3
Differential
Differential
Differential
Power/Other
Differential
Power/Other
N4
N5
N6
FBD1NBIDP[6]
FBD1NBIDP[8]
FBD1NBIDN[8]
I
I
I
N7
CSI0TPDAT[13]
VSS
O
N8
®
®
102
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
29 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
30 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
1
®
®
P36
P37
P38
R1
CSI0RNDAT[13]
CSI0RPDAT[13]
VSS
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Differential
I
I
T11
RSVD (Intel
Itanium Processor
9300 Series)
2
®
SVID_ALERT_N (Intel
®
Itanium Processor
VSS
9500 Series)
R2
FBD0SBOCLKAN0
FBD0SBOCLKAP0
VSS
O
O
T12
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
U1
VFUSERM
I
I
R3
VCCIO
Power/Other
R4
FLASHROM_DATI
VSS
R5
FBD1NBIDN[13]
VSS
I
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
R6
CSI2TPDAT[14]
CSI2TNDAT[16]
CSI2TPDAT[16]
CSI0TPDAT[15]
VSS
O
O
O
O
R7
FBD1NBICLKDN0
FBD1NBICP[4]
FBD1NBICN[4]
I
I
I
R8
R9
1
®
®
R10
RSVD (Intel
Itanium Processor
VCCIO
9300 Series)
2
®
SVID_DATIO (Intel
CSI0RNDAT[15]
CSI0RPDAT[15]
CSI0RNDAT[16]
FBD0SBOAN[3]
VSS
I
I
®
Itanium Processor
9500 Series)
R11
R12
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
T1
VSS
Power/Other
I
TMS
I
O
RSVD
U2
FLASHROM_DATO
FLASHROM_CS[2]_N
CSI2TNDAT[14]
VSS
O
O
O
U3
VSS
U4
RSVD
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
U5
FBD1NBIDN[4]
FBD1NBIDP[4]
VSS
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Power/Other
Power/Other
Differential
Differential
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Power/Other
I
I
U6
CSI2TPDAT[15]
CSI0TNDAT[15]
CSI0TNDAT[14]
CSI0TPDAT[14]
VSS
O
O
O
O
U7
U8
FBD1NBICP[2]
FBD1NBICP[3]
FBD1NBICN[3]
I
I
I
I
U9
U10
U11
U12
U27
U28
U29
U30
U31
U32
U33
U34
U35
U36
U37
SYSUTST_REFCLK_N
VSS
CSI0RNDAT[14]
CSI0RPDAT[14]
FBD0SBOAN[4]
FBD0SBOAP[4]
VCCIO_FBD
VSS
I
I
VSS
O
O
VCCIO
T2
CSI2TNDAT[17]
CSI2TPDAT[17]
CSI2TNDAT[18]
VSS
O
O
O
T3
T4
T5
FBD1NBIDP[13]
FBD1NBIDP[5]
FBD1NBIDN[5]
FBD1NBICN[2]
VSS
I
I
I
I
T6
CSI0TNDAT[16]
CSI0TPDAT[16]
VSS
O
O
T7
T8
T9
CSI0RNDAT[17]
VSS
I
T10
VCCIO_FBD
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
103
Pin Listing
Table 3-2.
Pin List by Pin Number (Sheet
31 of 32)
Table 3-2.
Pin List by Pin Number (Sheet
32 of 32)
Pin
Number
Signal
Buffer Type
Pin
Number
Signal
Buffer Type
Pin Name
Direction
Pin Name
Direction
U38
V1
CSI0RPDAT[16]
FBD0SBOAP[3]
FBD0SBOAN[2]
FBD0SBOAP[2]
FBD0SBOAN[0]
VSS
Differential
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
I
W30
W31
W32
W33
W34
W35
W36
W37
W38
Y1
CSI2TNDAT[19]
CSI2TPDAT[19]
CSI0TNDAT[19]
VSS
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Power/Other
Power/Other
Differential
Differential
Power/Other
Power/Other
Differential
Differential
Differential
O
O
O
O
O
O
O
V2
V3
V4
CSI0TPDAT[18]
VCCIO
O
V5
V6
FBD1NBIDP[3]
FBD1NBICN[1]
FBD1NBICP[1]
FBD1NBICN[0]
VSS
I
I
I
I
CSI0RPDAT[19]
CSI0RNDAT[19]
VSS
I
I
V7
V8
V9
VSS
V10
V11
V12
V27
V28
V29
V30
V31
V32
V33
V34
V35
V36
V37
V38
W1
Y2
VCCIO_FBD
FBD0SBOBN[10]
FBD0SBOBP[10]
VSS
SYSUTST_REFCLK
RESET_N
I
I
Y3
O
O
Y4
RSVD
Y5
TESTHI[4]
RSVD
I
Y6
VSS
Y7
FBD1NBIDP[2]
FBD1NBICN[14]
FBD1NBICP[14]
RSVD
I
I
I
VSS
Power/Other
Differential
Differential
Differential
Differential
Power/Other
Differential
Differential
Differential
Differential
Differential
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Y8
CSI2TPDAT[18]
CSI0TNDAT[17]
CSI0TPDAT[17]
CSI0TNDAT[18]
VSS
O
O
O
O
Y9
Y10
Y11
Y12
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
VSS
Power/Other
Differential
Power/Other
SYSCLK
I
I
VCCIO
CSI0RPDAT[17]
CSI0RPDAT[18]
CSI0RNDAT[18]
FBD0SBOAN[1]
FBD0SBOAP[1]
VSS
I
I
TESTHI[1]
VSS
Power/Other
Power/Other
Power/Other
Differential
Power/Other
Differential
Differential
Power/Other
Differential
Differential
I
VCCIO
O
O
VSS
W2
CSI0TPDAT[19]
VCCIO
O
W3
W4
FBD0SBOAP[0]
VCCIO_FBD
FBD1NBIDN[3]
FBD1NBIDN[2]
VSS
O
CSI1TNDAT[19]
CSI1TPDAT[19]
VSS
O
O
W5
W6
I
I
W7
CSI1RPDAT[19]
CSI1RNDAT[19]
I
I
W8
W9
FBD1NBICP[0]
RSVD
I
W10
W11
W12
W27
W28
W29
VSS
Power/Other
Power/Other
RSVD
RSVD
VSS
TESTHI[2]
I
®
®
104
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
3.2
Processor Package Top Pin Assignments
This section provides two-dimensional tables of the package top pin assignments.
These pins connect to the Ararat Voltage Regulator Power Module and do not connect to
the motherboard.
3.2.1
Top-Side J1 Connector Two-Dimensional Table
3.2.1.1
Top-Side J1 Connector Two-Dimensional Table for the Intel® Itanium®
Processor 9300 Series
Table 3-3 is a two dimensional table of the Intel® Itanium® Processor 9300 Series
package top-side J1 connector.
Table 3-3.
Top-Side J1 Connector Two-Dimensional Table (Intel® Itanium® Processor
9300 Series) (Sheet 1 of 2)
1
2
3
4
VID_VCCCORE[1]
VID_VCCCORE[2]
A
B
A
B
VID_VCCCORE[3]
VID_VCCCORE[5]
VID_VCCCORE[4]
VID_VCCCORE[6]
NO CONNECT
VCCCORE
NO CONNECT
C
C
D
E
D
E
VCCCORE
VSS
VSS
F
F
G
H
J
G
H
J
VCCCORE
VCCCORE
VSS
K
K
VSS
L
L
VCCCORE
VCCCORE
VSS
M
N
P
M
N
P
VSS
R
R
VCCCACHE
VCCCACHE
VSS
T
T
U
V
U
V
VSS
W
Y
W
Y
VCCCACHE
VCCCACHE
VCCCACHE
AA
AB
AA
AB
1
2
3
4
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
105
Pin Listing
Table 3-3.
Top-Side J1 Connector Two-Dimensional Table (Intel® Itanium® Processor
9300 Series) (Sheet 2 of 2)
1
2
3
4
VSS
VSS
AC
AD
AE
AF
AG
AH
AJ
AC
AD
AE
AF
AG
AH
AJ
VCCCACHE
VCCCACHE
VSS
VSS
VCCCORE
VCCCORE
VSS
AK
AL
AM
AN
AP
AR
AT
AK
AL
VSS
AM
AN
AP
AR
AT
VCCCORE
VCCCORE
VSS
VSS
Reserved
Reserved
AU
AV
AW
AY
AU
AV
AW
AY
VSSCACHESENSE
VROUTPUT_ENABLE0
VR_PROCTYPE_0
VCCCACHESENSE
CPU_PRESA_N
NO CONNECT
NO CONNECT
VR_PROCTYPE_1
1
2
3
4
®
®
3.2.1.2
Top-Side J1 Connector Two-Dimensional Table for the Intel Itanium
Processor 9500 Series
Table 3-4 is a two-dimensional table of the Intel® Itanium® Processor 9500 Series
package top-side J1 connector.
Table 3-4.
Top-Side J1 Connector Two-Dimensional Table (Intel® Itanium® Processor
9500 Series) (Sheet 1 of 3)
1
2
3
4
A
B
C
D
E
A
B
C
D
E
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
RESERVED
VCCCORE
VSS
1
2
3
4
®
®
106
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-4.
Top-Side J1 Connector Two-Dimensional Table (Intel® Itanium® Processor
9500 Series) (Sheet 2 of 3)
1
2
3
4
VSS
VCCCORE
VCCCORE
VCCCORE
VSS
F
G
F
G
H
H
J
J
K
K
VSS
L
L
VCCUNCORE
VCCUNCORE
VCCUNCORE
VCCUNCORE
VSS
M
M
N
N
P
P
R
R
T
T
VSS
U
U
VSS
V
V
VCCUNCORE
VCCUNCORE
VCCUNCORE
VCCUNCORE
VSS
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
VSS
VSS
VCCUNCORE
VCCUNCORE
VCCUNCORE
VCCUNCORE
VSS
VSS
VCCCORE
VCCCORE
VCCCORE
VSS
VSS
1
2
3
4
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
107
Pin Listing
Table 3-4.
Top-Side J1 Connector Two-Dimensional Table (Intel® Itanium® Processor
9500 Series) (Sheet 3 of 3)
1
2
3
4
VSS
VSS
AU
AV
AU
AV
CPU_PRESA_N
NO CONNECT
VCCUNCORE
NO CONNECT
NO CONNECT
VROUTPUT_ENABLE0
AW
AY
AW
AY
VR_PROCTYPE_0
VR_PROCTYPE_1
1
2
3
4
3.2.2
Top-Side J2 Connector Two-Dimensional Table
3.2.2.1
Top-Side J2 Connector Two-Dimensional Table for the Intel® Itanium®
Processor 9300 Series
Table 3-5 is a two-dimensional table of the Intel® Itanium® Processor 9300 Series
Processor package top-side J2 connector.
Table 3-5.
Top-Side J2 Connector Two-Dimensional Table (Intel® Itanium® Processor
9300 Series) (Sheet 1 of 2)
1
2
3
4
VID_VCCUNCORE[1]
VID_VCCUNCORE[3]
A
B
C
D
E
A
B
C
D
E
VID_VCCUNCORE[2]
VID_VCCUNCORE[4]
VID_VCCUNCORE[5]
VID_VCCUNCORE[6]
NO CONNECT
VCCCORE
NO CONNECT
VCCCORE
VSS
VSS
F
F
G
H
J
G
H
J
VCCCORE
VCCCORE
VSS
K
L
K
L
VSS
VCCCORE
VCCCORE
VSS
M
N
P
R
T
M
N
P
R
T
VSS
VCCUNCORE
VCCUNCORE
VSS
U
V
U
V
1
2
3
4
®
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-5.
Top-Side J2 Connector Two-Dimensional Table (Intel® Itanium® Processor
9300 Series) (Sheet 2 of 2)
1
2
3
4
VSS
VCCUNCORE
VCCUNCORE
VCCUNCORE
VSS
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AA
AB
AC
AD
AE
AF
AG
AH
AJ
VSS
VCCUNCORE
VCCUNCORE
VSS
VSS
VCCCORE
VCCCORE
VSS
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
VSS
VCCCORE
VCCCORE
VSS
VSS
Reserved
Reserved
VR_THERMTRIP_N
VCCCORESENSE
VSSCORESENSE
NO CONNECT
NO CONNECT
VR_THERMALERT_N
VID_VCCCORE[0]
CPU_PRESB_N
1
2
3
4
®
®
3.2.2.2
Top-Side J2 Connector Two-Dimensional Table for the Intel Itanium
Processor 9500 Series
Table 3-6 is a two-dimensional table of the Intel® Itanium® Processor 9500 Series
package top-side J2 connector.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
109
Pin Listing
Table 3-6.
Top-Side J2 Connector Two-Dimensional Table (Intel® Itanium® Processor
9500 Series) (Sheet 1 of 2)
1
2
3
4
NO CONNECT
NO CONNECT
RESERVED
NO CONNECT
A
B
A
B
VR_READY
RESERVED
NO CONNECT
NO CONNECT
C
C
VCCCORE
D
D
VSS
VSS
E
E
F
F
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VSS
G
G
H
H
J
J
K
K
L
L
VSS
M
N
M
N
VSS
VSS
P
P
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VSS
R
R
T
T
U
U
V
V
W
Y
W
Y
VSS
VSS
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
VSS
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VSS
VSS
VSS
VSS
1
2
3
4
®
®
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-6.
Top-Side J2 Connector Two-Dimensional Table (Intel® Itanium® Processor
9500 Series) (Sheet 2 of 2)
1
2
3
4
VCCCOCRE
VCCCORE
VCCCORE
VCCCORE
VSS
AL
AM
AN
AP
AR
AT
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
VSS
AU
AV
AW
AY
VSS
VSS
VR_THERMTRIP_N
CPU_PRESB_N
NO CONNECT
NO CONNECT
NO CONNECT
VR_THERMALERT_N
NO CONNECT
NO CONNECT
1
2
3
4
3.2.3
Top-Side J3 Connector Two-Dimensional Table
3.2.3.1
Top-Side J3 Connector Two-Dimensional Table for the Intel® Itanium®
Processor 9300 Series
Table 3-7 is a two-dimensional table of the Intel® Itanium® Processor 9300 Series
package top-side J3 connector.
Table 3-7.
Top-Side J3 Connector Two-Dimensional Table (Intel® Itanium® Processor
9300 Series) (Sheet 1 of 2)
1
2
3
4
A
B
C
D
E
Reserved
VR_FAN_N
Reserved
Reserved
Reserved
VRPWRGD
A
B
C
D
E
NO CONNECT
VCCCORE
NO CONNECT
VCCCORE
VSS
F
F
VSS
G
H
J
G
H
J
VCCCORE
VCCCORE
VSS
K
L
K
L
VSS
VCCCORE
M
M
1
2
3
4
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
111
Pin Listing
Table 3-7.
Top-Side J3 Connector Two-Dimensional Table (Intel® Itanium® Processor
9300 Series) (Sheet 2 of 2)
1
2
3
4
VCCCORE
VSS
N
P
N
P
VSS
R
R
VCCCACHE
VCCCACHE
VSS
T
T
U
U
V
V
VSS
W
W
VCCCACHE
VCCCACHE
VCCCACHE
VSS
Y
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
VSS
VCCCACHE
VCCCACHE
VSS
VSS
VCCCORE
VCCCORE
VSS
VSSVSS
VCCCORE
VCCCORE
VSS
VSS
Reserved
CPU_PRESB_N
VID_VCCUNCORE[0]
Reserved
Reserved
AU
AV
AW
AY
VSSUNCORESENSE
VCCUNCORESENSE
Reserved
NO CONNECT
NO CONNECT
1
2
3
4
®
®
112
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
®
®
3.2.3.2
Top-Side J3 Connector Two-Dimensional Table for the Intel Itanium
Processor 9500 Series
Table 3-8 is a two-dimensional table of the Intel® Itanium® Processor 9500 Series
package top-side J3 connector.
Table 3-8.
Top-Side J3 Connector Two-Dimensional Table (Intel® Itanium® Processor
9500 Series) (Sheet 1 of 2)
1
2
3
4
A
B
NO CONNECT
VR_FAN_N
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
A
NO CONNECT
VCCCORE
B
C
NO CONNECT
C
D
D
VSS
VSS
E
E
F
F
VCCCORE
VCCCORE
VCCCORE
VSS
G
G
H
H
J
J
K
K
VSS
L
L
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VSS
M
N
M
N
P
P
R
R
T
T
VSS
U
U
VSS
V
V
VCCUNCORE
VCCUNCORE
VCCUNCORE
VCCUNCORE
VSS
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AG
AA
AB
AC
AD
AE
AF
AG
VSS
VSS
VCCUNCORE
VCCUNCORE
1
2
3
4
®
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
113
Pin Listing
Table 3-8.
Top-Side J3 Connector Two-Dimensional Table (Intel® Itanium® Processor
9500 Series) (Sheet 2 of 2)
1
2
3
4
VCCUNCORE
VCCUNCORE
VSS
AH
AJ
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AK
AL
VSS
VCCCORE
VCCCORE
VCCCORE
VSS
AM
AN
AP
AR
AT
VSS
SVID_DATA
VSS
SVID_CLK
VSS
AU
AV
AW
AY
AU
AV
AW
AY
NO CONNECT
NO CONNECT
SVID_ALERT_N
NO CONNECT
CPU_PRESB_N
Reserved
1
2
3
4
3.2.4
Top-Side J4 Connector Two-Dimensional Table
®
®
3.2.4.1
Top-Side J4 Connector Two-Dimensional Table for the Intel Itanium
Processor 9300 Series
Table 3-9 is a two-dimensional table of the Intel® Itanium® Processor 9300 Series
package top-side J4 connector.
Table 3-9.
Top-Side J4 Connector Two-Dimensional Table (Intel® Itanium® Processor
9300 Series) (Sheet 1 of 2)
1
2
3
4
A
B
C
D
E
F
A
B
C
D
E
F
VID_VCCCACHE[0]
VID_VCCCACHE[5]
VID_VCCCACHE[4]
VID_VCCCACHE[1]
VID_VCCCACHE[2]
VID_VCCCACHE[3]
NO CONNECT
VCCCORE
NO CONNECT
VCCCORE
VSS
VSS
G
H
J
G
H
J
VCCCORE
VCCCORE
1
2
3
4
®
®
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-9.
Top-Side J4 Connector Two-Dimensional Table (Intel® Itanium® Processor
9300 Series) (Sheet 2 of 2)
1
2
3
4
VSS
VSS
K
L
K
L
VCCCORE
VCCCORE
VSS
M
M
N
N
P
P
VSS
R
R
VCCUNCORE
VCCUNCORE
VSS
T
T
U
U
V
V
VSS
W
W
VCCUNCORE
VCCUNCORE
VCCUNCORE
VSS
Y
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
VSS
VCCUNCORE
VCCUNCORE
VSS
VSS
VCCCORE
VCCCORE
VSS
VSS
VCCCORE
VCCCORE
VSS
VSS
VCCIO
Reserved
Reserved
Reserved
Reserved
Reserved
1
NO CONNECT
NO CONNECT
CPU_PRESA_N
Reserved
2
3
4
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
115
Pin Listing
®
®
3.2.4.2
Top-Side J4 Connector Two-Dimensional Table for the Intel Itanium
Processor 9500 Series
Table 3-10 is a two-dimensional table of the Intel® Itanium® Processor 9500 Series
package top-side J4 connector.
Table 3-10. Top-Side J4 Connector Two-Dimensional Table (Intel® Itanium® Processor
9500 Series) (Sheet 1 of 2)
1
2
3
4
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
A
B
A
B
RESERVED
RESERVED
RESERVED
RESERVED
C
C
VCCCORE
D
D
VSS
VSS
E
E
F
F
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VSS
G
G
H
H
J
J
K
K
L
L
VSS
M
N
M
N
VSS
VSS
P
P
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VSS
R
R
T
T
U
U
V
V
W
Y
W
Y
VSS
VSS
AA
AB
AC
AD
AE
AF
AG
AA
AB
AC
AD
AE
AF
AG
VSS
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VSS
1
2
3
4
®
®
116
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Pin Listing
Table 3-10. Top-Side J4 Connector Two-Dimensional Table (Intel® Itanium® Processor
9500 Series) (Sheet 2 of 2)
1
2
3
4
VSS
VSS
AH
AJ
AH
AJ
VSS
AK
AL
AK
AL
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VSS
AM
AN
AP
AR
AT
AU
AV
AW
AY
AM
AN
AP
AR
AT
AU
AV
AW
AY
VSS
VCCIO
VSS
RESERVED
NO CONNECT
NO CONNECT
Reserved
CPU_PRESA_N
NO CONNECT
1
NO CONNECT
NO CONNECT
2
3
4
§
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
117
Pin Listing
®
®
118
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Mechanical Specifications
4
Mechanical Specifications
The Intel® Itanium® Processor 9300 Series and 9500 Series are packaged in a FC-LGA
package that interfaces with the motherboard via an LGA1248 socket. The package top
side consists of lands that interface with a LGA connector for direct power delivery to
the core, cache and system interface. The package also consists of an integrated
heatsink spreader (IHS), which is attached to the package substrate and die and serves
as the mating surface for the processor component thermal solutions, such as a
heatsink. The bottom side of the package has 1248 lands, a 38 x 38 mm pad array
which interfaces with the LGA1248 socket. Figure 4-1 shows a sketch of the processor
package components and how they are assembled together.
The package components shown in Figure 4-1 include the following:
1. Integrated Heat Spreader (IHS).
2. Processor die.
3. Internal test pads for power delivery.
4. LGA lands for I/O.
5. Decoupling and server management components.
6. LGA lands for power delivery.
Figure 4-1. Processor Package Assembly Sketch
2
1
6
5
3
4
Note: This drawing is not to scale and is for reference only. Processor power delivery and thermal solutions,
and the socket are not shown.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
119
Mechanical Specifications
4.1
Package Mechanical Drawing
The package mechanical drawings are shown in Figure 4-2, Figure 4-3, Figure 4-4 and
Figure 4-5. The package mechanical drawings for the Intel® Itanium® Processor 9500
Series processor are shown in Figure 4-6, Figure 4-7, Figure 4-8 and Figure 4-9. The
drawings include dimensions necessary to design a thermal solution for the processor.
These dimensions will include:
1. Package reference with tolerances (total height, length, width, and so on).
2. IHS parallelism and tilt.
3. Land dimensions.
4. Top-side and back-side component keepout dimensions.
5. Reference datums.
All drawing dimensions are in mm.
®
®
120
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Mechanical Specifications
4.2
Intel® Itanium® Processor 9300 Series
Figure 4-2. Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 1 of 4)
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
121
Mechanical Specifications
Figure 4-3. Intel® Itanium® Processor 9300 Series Processor Package Drawing (Sheet 2
of 4)
®
®
122
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Mechanical Specifications
Figure 4-4. Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 3 of 4)
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
123
Mechanical Specifications
Figure 4-5. Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 4 of 4)
®
®
124
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Mechanical Specifications
Figure 4-6. Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 1 of 4)
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
125
Mechanical Specifications
Figure 4-7. Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 2 of 4)
®
®
126
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Mechanical Specifications
Figure 4-8. Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 3 of 4)
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
127
Mechanical Specifications
Figure 4-9. Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 4 of 4)
®
®
128
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Mechanical Specifications
4.3
Processor Component Keepout Zones
The processor may contain components on the substrate that define component
keepout zone requirements. A thermal and mechanical solution design must not intrude
into the required keepout zones. Decoupling capacitors are typically mounted to both
the top-side and bottom-side of the package substrate. See Figure 4-4 for Intel®
Itanium® 9300 Series Processor keepout zones and Figure 4-8 for Intel® Itanium®
9500 Series Processor keepout zones.
4.4
Package Loading Specifications
Table 4-1 provides dynamic and static load specifications for the processor package.
These mechanical load limits should not be exceeded during heatsink assembly,
shipping conditions, or standard use condition. Also, any mechanical system or
component testing should not exceed the maximum limits. The processor package
substrate should not be used as a mechanical reference or load-bearing surface for
thermal and mechanical solutions.
Table 4-1.
Processor Loading Specifications
Parameter
Maximum
1000
Unit
N
Notes
1, 2, 3
Static Compressive Load
1
3
Dynamic Compressive Load
t < 30 ms
1793
N
,
1
3
Transient
t < 1 s
1090
N
,
Notes:
1. These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface.
2. This is the allowable static force that can be applied by the heatsink and retention solution to maintain the
heatsink and processor interface.
3. These parameters are based on limited testing for design characterization. Loading limits are for the package
only and do not include the limits of the processor socket.
4.5
Package Handling Guidelines
Table 4-2 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 4-2.
Package Handling Guidelines
Parameter
Maximum Recommended
Unit
Notes
Shear
Tensile
Torque
356
156
8
N
N
1, 4
2, 4
3, 4
N-m
Note:
1.
2.
3.
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
A tensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top
surface.
4.
These guidelines are based on limited testing for design characterization.
The Intel® Itanium® Processor 9300 Series can be inserted into and removed from a
LGA1248 socket and engaged and disengaged with the Ararat voltage regulator up to a
maximum limit as specified in Table 4-3.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
129
Mechanical Specifications
Table 4-3.
4.6
Processor Package Insertion Specification
Package
Durability Limit
15
1248-Land FCLGA
Processor Mass Specifications
The typical mass of the Intel® Itanium® Processor 9300 Series and 9500 Series is 55 g.
This mass [weight] includes all the components that are included in the package.
4.7
Processor Materials
Table 4-4 lists some of the package components and associated materials.
Lead and other materials banned in Restriction on Hazardous Substances (RoHS)
Directive are either (1) below all applicable substrate thresholds as proposed by the EU
or (2) an approved/pending exemption applies.
Note:
RoHS implementation details are not fully defined and may change.
Table 4-4.
Package Materials
Component
Material
Integrated Heat Spreader (IHS)
Substrate
Nickel Plating over Copper
Fiber-Reinforced Resin
Gold Plating over Nickel
Package Lands
4.8
Package Markings
Bottom side marks on the package substrate provide the necessary processor
identification and tracking information. This information is captured in Table 4-5 and
their locations are illustrated in Figure 4-10.
Table 4-5.
1248 FCLGA Package Marking Zones
Zone
Engineering Samples
2D Matrix Mark: VID
Visual Identification (VID) Mark
Line 1: Product Name
Production Units
Zone A
Zone B
Zone C
Line 1: INTEL CONFIDENTIAL
Line 2: Mask and Copy Right Date Codes
Line 2: Mask and Copy Right Date Codes,
Lead Free product designator
Zone E
Intel
Zone F
Zone G
Finish Process Order (FPO) and Serial #
Processor ID
Zone H
2D Matrix Mark: Finish Process Order (FPO) and Serial #
Notes:
1.
VID (Visual Identification): Is a unique number which can be used for the purpose of tracking the
processor. It is used by Intel to retrieve processor related information.
2.
FPO (Finish Process Order): Is a unique number. It can be used for tracking purposes. It is used by Intel to
retrieve processor and shipping order information.
®
®
130
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Mechanical Specifications
Figure 4-10. Processor Marking Zones
A
C
B
Top Side
H
G
E
F
Bottom Side
§
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
131
Mechanical Specifications
®
®
132
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Thermal Specifications
5
Thermal Specifications
This chapter provides the thermal specifications of the Intel® Itanium® Processor 9300
Series and the Intel® Itanium® Processor 9500 Series processors.
The Intel® Itanium® Processor 9300 Series and the Intel® Itanium® Processor 9500
Series processors’ power and thermal management is built from four subsystems or
components. These are power measurement components, the temperature
measurement components, the frequency control components and the voltage control
components that work in concert allowing the management system to maximize
performance within a given power and thermal envelope. This results in higher average
core frequency performance compared to a worst-case fixed frequency. It boosts
performance based on application activity. The power and thermal management
system is fully integrated within the Intel® Itanium® Processor 9300 Series and Intel®
Itanium® Processor 9500 Series.
The power and thermal management system is designed for repeatable performance
under the same operating conditions. It provides several hooks to the OS and system
management to monitor and change the processor performance and thermal status.
With the power and thermal management system on the Intel® Itanium® Processor
9300 Series and Intel® Itanium® Processor 9500 Series, typical applications see a
higher core frequency, resulting in higher performance.
For the Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500
Series, base frequency is based on an activity factor determined by the highest known
activity factor in benchmark suites. Boost frequency is available when the processor is
not power limited.
The Intel® Itanium® Processor 9500 Series enables Intel® Turbo Boost Technology
featuring sustained boost. Processor performance is optimized for a given power
envelope and is integrated into the processor core. Power management optimizes the
processor performance for a given TDP “Thermal Design Power”. The core activity levels
are monitored in real time, and each core enforces its own AFT “Activity Factor
Throttling” to keep the processor at TDP for high activity applications. Instruction
dispersal is lowered in a core to keep the activity of the core within TDP when an over
TDP condition is detected. AFT is transparent to software running on the processor.
5.1
Thermal Features
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
have internal thermal sensors which sense when a certain temperature is reached on
the processor core. These sensors are used to control various thermal states.
Figure 5-1 shows an approximate relationship between temperature, time, and the
THERMALERT, TCONTROL, PROCHOT, THERMWARN, and THERMTRIP points.
Note:
Figure 5-1 is not intended to show an exact relationship in time or temperature as a
processor's thermal state advances from one state to the next state. Cooling solution
performance degradation and processor workload variations will affect the processor
thermal state.
®
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
133
Thermal Specifications
Figure 5-1. Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500
Series’ Thermal States
THERMTRIP
THERMWARN
Max Operating Temperature
PROCHOT
TCONTROL
THERMALERT
Time
Diagram not to scale
5.1.1
Digital Thermometer
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
uses a thermal sensing device called Digital Thermometer (DT) to read the values from
the thermal sensors available on the processor die. The DT also compares these values
to a thermal trip point that is hard-wired. Calibration information is used to translate
the DT output to processor temperature in degrees Celsius relative to the PROCHOT
setpoint. DT readout is available in CSR or via SMBus. When it is below the PROCHOT
setpoint the DT readout will have a positive value. The DT has a limited range. It will
report out the value of its upper or lower limits when it has reached the limits and set
QR_CSR_IPF_THERM_STATUS.valid = 1’b0.
®
®
5.1.1.1
Thermal Sensor Accuracy Distribution for the Intel Itanium
Processor 9300 Series
Table 5-1 shows the processor thermal sensor accuracy with respect to the DT readout
for the an Intel® Itanium® Processor 9300 Series. The margin of error is relative to
PROCHOT and represents the typical ±3-sigma range. This data is for a large sample of
parts. It should be noted that a particular part should be consistent across the entire
operating range.
Table 5-1.
Thermal Sensor Accuracy Distribution for the Intel® Itanium® Processor 9300
Series (Sheet 1 of 2)
Expected Margin of Error
DT Readout
Relative to PROCHOT
0x83 - 0x80, 0x00 - 0x07
0x08 - 0x0E
±1°C
±2°C
±3°C
±4°C
±5°C
±6°C
0x0F - 0x14
0x15 - 0x1B
0x1C - 0x22
0x23 - 0x29
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Table 5-1.
Thermal Sensor Accuracy Distribution for the Intel® Itanium® Processor 9300
Series (Sheet 2 of 2)
Expected Margin of Error
Relative to PROCHOT
DT Readout
0x2A - 0x30
0x31 - 0x37
0x38- 0x3E
0x3F - 0x45
±7°C
±8°C
±9°C
±10°C
®
®
5.1.1.2
Thermal Sensor Accuracy Distribution for the Intel Itanium
Processor 9500 Series
Table 5-2 shows the processor thermal sensor accuracy with respect to the DT readout
for the Intel® Itanium® Processor 9500 Series . The margin of error is relative to
PROCHOT and represents the typical ±3-sigma range. For the Intel® Itanium®
Processor 9500 Series, it is based on presilicon simulation data. It should be noted that
a particular part should be consistent across the entire operating range.
Table 5-2.
Thermal Sensor Accuracy Distribution for the Intel® Itanium® Processor
9500 Series
DT Readout
Expected Margin of Error
Relative to PROCHOT
0x83 - 0x80, 0x00 - 0x03
0x04 - 0x32
± 1°C
± 3°C
± 5°C
0x33 - 0x49
5.1.2
Thermal Management
5.1.2.1
Overview
The Thermal Management controller on the processor will measure the die temperature
using thermal sensors placed in several key locations on the die. Each sensor is fed into
a central thermometer logic block. For the Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series, the central thermometer logic block will report
the highest temperature of all sensors. Referring to Figure 5-1, the sequence of steps
taken by the processor thermal management system are presented in steps (a) to (d).
a. If T>=TPROCHOT and the Intel® Itanium® Processor 9300 Series is operating at
boost frequency, then the thermal management system will instruct the
processor to go to base voltage and frequency.
After a delay, if the processor temperature is below the TPROCHOT threshold,
normal operation will resume including the Intel® Itanium® Processor 9300
Series being allowed to operate at boost frequency if appropriate.
If T>=TPROCHOT, the Intel® Itanium® Processor 9500 Series thermal
management system will reduce the activity factor maximum limit. After a
delay, if the processor temperature is below TPROCHOT threshold, normal
operation will resume and the previous Intel® Itanium® Processor 9500 Series
activity factor maximum limit will be restored.
b. If T>=TPROCHOT and the Intel® Itanium® Processor 9300 Series is already at or
below base voltage and frequency, then the thermal management system will
assert PROCHOT_N and the processor will enter Single Issue Mode (SIM) and
transition to the voltage and frequency of the lowest supported P-state.
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A Corrected Machine Check Interrupt (CMCI) is issued when processor enters
and exits SIM.
If T>= TPROCHOT the Intel® Itanium® Processor 9500 Series and the activity
factor maximum limit is already reduced, then the thermal management
system will assert PROCHOT_N and the processor will enter Single Issue Mode
(SIM) and transition to the lowest P-state.
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor
9500 Series will remain in this low power mode until the temperature
decreases and drops below (TPROCHOT - THYSTERESIS). The processor will be
in this low power mode for a minimum of 1 second and after 1 second will
resume normal operation as soon as the temperature has decreased
sufficiently.
c. If T>=TTHERMWARN, then the processor will issue a fatal MCA and PROCHOT_N
will remain asserted; the thermal management controller becomes non-
functional. The processor cannot recover except via cold reset. The processor
will continue to throttle if T>=TPROCHOT when it comes out of reset.
Data integrity is not guaranteed beyond TTHERMWARN
.
d. If T>= TTHERMTRIP, then the thermal management system will assert
THERMTRIP_N and halt processor clocks.
TTHERMTRIP is enforced to prevent physical damage to the processor.
Cold reset is required to recover.
5.1.2.2
Implementation
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
thermal management features are designed to operate independently of software,
including the operating system. The thermal sensors are on the die of the processor
and the frequency and voltage control resides completely on the processor. In order to
reduce the processor power while throttling, some execution units on the processor are
shut down, limiting the processor to executing only one instruction per cycle.
When the PROCHOT threshold is crossed and the processor enters low power mode, a
CMCI is sent to the OS and to the System Abstraction Layer (SAL). This interrupt is
sent out when entering throttling (CMCI entry) and also when the processor is exiting
the SIM phase (CMCI exit) to inform the system of the performance status. Note that
the temperature could cool below the throttle trip point but exiting SIM is still subject to
the minimum time of 1 second. Information on the CMCI interrupt can be found in the
Intel® Itanium® Processor Family Interrupt Architecture Guide.
There is a mechanism to bypass the PROCHOT setpoint. When it is bypassed, both the
THERMALERT_N and THERMTRIP_N signals, as well as THERMWARN threshold, still
operate as normal. There is also a mode that emulates PROCHOT setpoint for testing.
The processor can be placed in this mode by a Processor Abstraction Layer (PAL) call.
Another PAL call will return the processor to normal operation. These special modes are
intended for debug purposes only.
5.1.3
Thermal Alert
THERMALERT_N is a programmable thermal alert signal which is part of the Intel Intel®
Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series’ thermal
management system. THERMALERT_N is asserted when the measured temperature
from the processor’s digital thermometer (DT) is equal to or exceeds
QR_CSR_IPF_THERM_CONFIG.thermalert_assert_hot_thresh below PROCHOT.
THERMALERT_N will deassert after the DT readout is below PROCHOT by the sum of the
values in QR_CSR_IPF_THERM_CONFIG.thermalert_assert_hot_thresh and
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Thermal Specifications
QR_CSR_IPF_THERM_CONFIG.thermalert_deassert_thresh. Intel recommends using
the values listed in the PIROM when programming
QR_CSR_IPF_THERM_CONFIG.thermalert_assert_hot_thresh and
QR_CSR_IPF_THERM_CONFIG.thermalert_deassert_thresh. The default values for
QR_CSR_IPF_THERM_CONFIG.thermalert_assert_hot_thresh and
QR_CSR_IPF_THERM_CONFIG.thermalert_deassert_thresh are 10°C and 4°C
respectively for the Intel® Itanium® Processor 9300 Series. For the Intel® Itanium®
Processor 9500 Series, the default values are 0°C.
This signal can be used by the platform to implement thermal regulation features such
as generating an external interrupt to tell the operating system that the processor core
die temperature is increasing.
5.1.4
T
CONTROL
TCONTROL is a thermal monitoring setpoint which is specified as a relative temperature
in degrees Celsius below the PROCHOT_N threshold. The minimum value of the
TCONTROLthreshold is specified in Table 5-3 for the Intel® Itanium® Processor 9300
Series and Table 5-4 for the Intel® Itanium® Processor 9500 Series, and the default
value is available in the PIROM. TCONTROL value applies to the full range of the
processor operating power and is independent of the processor core configuration or
executed applications. A server thermal management controller can monitor the
processor temperature via the Digital Thermal Sensor (DTS) readout, and use the
TCONTROL value as the threshold at which active system thermal management must be
engaged. This will ensure reliable processor operation over its expected life. Note that
no internal response is generated by the processor at TCONTROL. Customers can utilize
THERMALERT_N as an interrupt to program an alternative temperature monitoring
threshold value to provide margin in their cooling solution design. See Intel® Itanium®
Processor 9300 Series Thermal Mechanical Design Guide for additional guidance on
implementing a compliant processor thermal solution.
5.1.5
5.1.6
Thermal Warning
THERMWARN is the temperature beyond which data integrity is not guaranteed and
PROCHOT_N remains asserted.
Thermal Trip
The Intel® Itanium® Processor 9300 Series nd Intel® Itanium® Processor 9500 Series
protects itself from catastrophic overheating by use of an internal thermal sensor. The
sensor trip point is set well above the maximum operating temperature to ensure that
there are no false trips. The Intel® Itanium® Processor 9300 Series and Intel®
Itanium® Processor 9500 Series will issue THERMTRIP_N and stop all execution when
the junction temperature exceeds a safe operating level. At this point THERMTRIP_N is
asserted. If THERMTRIP_N is asserted, processor voltages (VCCCORE, VCCUNCORE,
AND VCCCACHE) must be removed within the timeframe defined in Table 2-36.
Data will be lost or corrupt, and transaction time outs will occur if the Intel® Itanium®
Processor 9300 Series and Intel® Itanium® Processor 9500 Series go into thermal trip.
The part that shuts down may still have pending snoops or memory reads that the
other sockets in the partition may have requested.
Once THERMTRIP_N is asserted, the Intel® Itanium® Processor 9300 Series and Intel®
Itanium® Processor 9500 Series remain stopped until RESET_N is asserted. If the die
temperature has dropped below the trip level, a RESET_N pulse can be used to reset
the processor. If the temperature has not dropped below the trip level, the processor
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Thermal Specifications
will continue to drive THERMTRIP_N and remain stopped. It is recommended to allow
the processor case temperature to drop below the specified design target before issuing
a reset to the processor. Please see Section 5.2 and Table 5-3 for details on the case
temperature.
Note:
In a partitioned system, sockets in the same partition are in the same coherency
domain, so they cannot continue to operate if even one of the processors asserts
THERMTRIP_N and shuts down. Moreover, a cold reset is required to get the part back
up after a THERMTRIP event. Because cold reset will reset all the sockets in the
partition, the other sockets cannot continue running without a reset event.
5.1.7
PROCHOT
The temperature at PROCHOT represents the maximum normal operating temperature
of the processor. PROCHOT_N is asserted when the processor temperature is greater
than or equal to TPROCHOT.
PROCHOT_N is a signal from the processor to the platform indicating that the processor
has detected an over-temperature condition and it is taking corrective measures. This
pin is not asserted when FORCEPR_N or VR_THERMALERT_N is asserted unless the
thermal system has detected a PROCHOT condition independent of those input signals.
The condition may occur due to any of the following conditions:
• The thermal environment is outside of the limits defined for full performance
operation.
• The processor power consumption is unbalanced due to very high activity factors in
some cores coupled with very low activity factors in others.
5.1.8
5.1.9
FORCEPR_N Signal Pin
FORCEPR_N is an input pin that will force the processor into one of two modes. The
default mode is the same state as PROCHOT_N. The processor will go into Single Issue
Mode (SIM) and also transition to the voltage and frequency of the lowest supported
P-state. Time limits and CMCI generation are the same as PROCHOT_N. The second
mode, selectable via QR_CSR_IPF_THERM_CONFIG.forcepr_mode, disables SIM and
timer functions while maintaining core frequency and voltage throttling. Both modes
can be disabled via QR_CSR_IPF_THERM_CONFIG.forcepr_disable.
Ararat Voltage Regulator Thermal Signals
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
package allows the Ararat Voltage Regulator to signal to the platform when it
approaches its own thermal limits. The specific signals for this purpose are VR_FAN_N,
VR_THERMALERT_N, and VR_THERMTRIP_N.
The processor does not monitor or respond to the VR_FAN_N and VR_THERMTRIP_N
pins. The response to VR_THERMALERT_N is to force the processor into the same state
as PROCHOT_N. The processor will go into SIM and also transition to the voltage and
frequency of the lowest supported P-state. Time limits and CMCI generation are active.
This response may be disabled via R_CSR_IPF_THERM_CONFIG.vr_thermalert_disable.
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Thermal Specifications
5.2
Package Thermal Specifications and
Considerations
This section lists the thermal parameters of the Intel® Itanium® Processor 9300 Series
and Intel® Itanium® Processor 9500 Series package. See Table 5-3 and Table 5-4 for
the TCASE design target at Thermal Design Power (TDP) and the minimum Tcontrol
specification for the Intel® Itanium® Processor 9300 Series and the Intel® Itanium®
Processor 9500 Series, respectively. The case temperature is defined as the
temperature measured at the center of the processor substrate on the top surface of
the IHS.
Table 5-3.
Thermal Specification for the Intel® Itanium® Processor 9300 Series
TDP - Thermal
Design Power
(W)
Max Operating
Temperature
(DT Readout)
Minimum
T
(°C)
T
(°C)
CASE
CASE
T
Notes
CONTROL
Min
@ TDP
(DT Readout)
185
155
130
0
0
0
5
5
5
88
88
88
5
5
5
1, 2, 3, 4, 5
1, 2, 3, 4, 5
1, 2, 3, 4, 5
Notes:
1.
2.
The processor maximum temperature is reached at T
. That is when DT readout is equal to zero.
PROCHOT
Intel recommends that the thermal solution designs target the processor Thermal Design Power (TDP),
instead of its spontaneous maximum power consumption.
Processor TDP is determined at the T
3.
4.
5.
equal to T
@TDP
CASE
CASE
Tcase is provided for the purpose of designing a processor compatible thermal solution.
The THERMALERT and TCONTROL values are temperature offsets below T
.
PROCHOT
TCASE cannot be used as proxy for power dissipation due to the variation in work load
imbalances between cores.
TDPmax is 185 W or 155 W or 130 W depending on the SKU.
The combined max short-term (<250 ms) power for the Ararat supplies (VCC_CORE,
VCC_UNCORE and VCC_CACHE) is limited to 230 W, and the total of all supplies is
limited to 250 W for the 185 W SKUs.
Table 5-4.
Thermal Specification for the Intel® Itanium® Processor 9500 Series
Processor
TDP - Thermal
Design Power
(W)
Max Operating
Temperature
(DT Readout)
Minimum
CONTROL
(DT Readout)
T
(°C)
T
(°C)
CASE
CASE
T
Notes
Min
@ TDP
1
170
0
0
5
5
78
78
3
3
130
1,2,3,4,5
Notes:
1. The processor maximum temperature is reached at T
. That is when DT readout is equal to zero.
PROCHOT
TCASE cannot be used as proxy for power dissipation due to the variation in work load
imbalances between cores.
TDPmax is 170W or 130W depending on the SKU.
Figure 5-2 contains dimensions for the thermocouple location on the Intel® Itanium®
Processor 9300 Series and Intel® Itanium® Processor 9500 Series. This location must
be used for the placement of a thermocouple for case temperature measurement.
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
139
Thermal Specifications
Figure 5-2. Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500
Series Package Thermocouple Location
C
LSubstrate
C
LSubstrate
1.5 mm
C
LIHS
Thermocouple
Attach Point
Not to scale.
Note: Refer to the Package Mechanical Drawings in Chapter 4.
5.3
Storage Conditions Specifications
Environmental Storage Condition limits define the temperature and relative humidity
limits to which the device is exposed to while being stored. The specified storage
conditions are for component level prior to installation onto board.
Non operating storage condition limits for the component once installed onto the
application board are not specified. Intel does not conduct component level certification
assessments post subsequent applications such as components sub-assembly (FRU:
Field Replaceable Unit), or installation onto a board given the multitude of attach
methods, and board types used by customers. Provided as general guidance only,
Intel® board products are specified and certified to meet the following temperature and
humidity limits (Non-Operating Temperature Limit: -40°C to 70°C and Humidity: 50%
to 90%, non condensing with a maximum wet bulb of 28°C).
Table specifies absolute maximum and minimum storage temperature limits which
represent the maximum or minimum device condition beyond which damage, latent or
otherwise, may occur. The table also specifies sustained storage temperature, relative
humidity, and time-duration limits. These limits specify the maximum or minimum
device storage conditions for a sustained period of time. At conditions outside
sustained limits, but within absolute maximum and minimum ratings, quality and
reliability may be affected.
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Thermal Specifications
Table 5-5.
Storage Condition Ratings
Symbol
Parameter
Min
-55°C
Max
125°C
Notes
T
The minimum/maximum device storage
temperature beyond which damage (latent
or otherwise) may occur when subjected to
for any length of time.
1, 2, 3, 4
abs storage
T
The minimum/maximum device storage
temperature for a sustained period of time.
-5°C
40°C
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
sustained storage
RH
The maximum device storage relative
humidity for a sustained period of time.
-
60% @ 24°C
12 months
sustained storage
T
A prolonged or extended period of time;
typically associated with sustained storage
conditions.
0 months
imesustained storage
Notes:
1.
Storage conditions are applicable to storage environments only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, please refer to the processor case
temperature specifications.
2.
3.
4.
These ratings apply to the Intel component and do not include the tray or packaging.
Failure to adhere to this specification can affect the long-term reliability of the processor.
Device storage temperature qualification methods follow JESD22-A119 (low temp) and JESD22-A103 (high
temp) standards.
§
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Thermal Specifications
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
System Management Bus Interface
6
System Management Bus
Interface
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
package includes a system management bus (SMBus) interface. This chapter describes
the features of the SMBus and its components.
6.1
Introduction
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
package includes an SMBus interface which allows access to a memory component
subdivided into two sections (referred to as the PIROM and the Scratch EEPROM), and
sideband access to the processor’s control & status registers (CSRs). This chapter is
devoted to the PIROM field definitions of the memory component. For details of SMBus
transactions used to access processor Control and Status Registers (CSRs), refer to the
RS - Intel® Itanium® 9300 Processor External Design Specification or the RS - Intel®
Itanium® Processor 9500 Series External Design Specification.
The PIROM consists of the following sections:
• General
• Processor
• Processor Core
• Processor Uncore
• Cache
• Package
• Part Number
• Thermal Reference
• Feature
• Other
Details on each of these sections are described in Section 6.4.
The processor SMBus implementation uses the clock and data signals of the System
Management Bus (SMBus) Specification. Layout and routing guidelines are available in
the Intel® Itanium® 9300 Series and Intel® Itanium® 9500 Series Platform Design
Guide.
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System Management Bus Interface
6.2
SMBus Memory Component
6.2.1
Processor Information ROM (PIROM)
Table 6-1 maps the PIROM offsets to the field definitions, which are described in
Section 6.4.
Table 6-1.
Processor Information ROM Data (Sheet 1 of 6)
Sec #
Offset
Field Name
Data Type
General
Description
Example
0
00h
Data Format Revision
EEPROM Size
Hex
Hex
Incremented with PIROM Table
revisions
Rev 1.6 = 0x10
1
2
01h
02h
Size in Bytes
128 bytes = 0080h; that
is,
02h[7:0] = 0x00
01h[7:0] = 0x80
3
03h
Processor Data Address
Processor Core Address
Hex Byte pointer
Pointer to the section of PIROM
containing Processor Production
Data
0x0F; 0x00 if not
present
4
5
6
7
04h
05h
06h
07h
Hex Byte pointer
Hex Byte pointer
Hex Byte pointer
Hex Byte pointer
Pointer to the section of PIROM
containing Processor Core Data
0x22; 0x00 if not
present
Processor Uncore
Address
Pointer to the section of PIROM
containing Processor Uncore Data
0x2E; 0x00 if not
present
Processor Cache
Address
Pointer to the section of PIROM
containing Processor Cache Data
0x46; 0x00 if not
present
Package Data Address
Pointer to the section of PIROM
containing Processor Package
Data
0x4F; 0x00 if not
present
8
9
08h
09h
0Ah
0Bh
Part Number Data
Address
Hex Byte pointer
Hex Byte pointer
Hex Byte pointer
Pointer to the section of PIROM
containing Processor Part Number
Data
0x56; 0x00 if not
present
Thermal Reference Data
Address
Pointer to the section of PIROM
containing Processor Thermal
Reference Data
0x6B; 0x00 if not
present
10
11
Feature Data Address
Pointer to the section of PIROM
containing Processor Features
Data
0x72; 0x00 if not
present
Other Data Address
RESERVED
Hex Byte pointer
Hex
Pointer to the section of PIROM
containing Processor “Other” Data
0x7D; 0x00 if not
present
12
13
14
0Ch
0Dh
0Eh
Reserved for future use
0Ch = 0x00
0Dh = 0x00
Checksum
Hex
Add up by byte and take 2's
complement
Processor
21
22
15h
16h
Sample/Production
Hex
Hex
Identifies sample parts separately
from production parts
0x01 = Production
0x00 = Sample
Voltage Regulator Type
Required
Identifies Ararat type required
0x00 for Intel®
Itanium® Processor
9300 Series,
0x01 for Intel®
Itanium® Processor
9500 Series
23
24
17h
18h
VCCA
4 binary coded
decimal (bcd)
digits
Processor Analog Voltage Supply
in four 4-bit Hex digits (in mV)
1.800V = 1800
17h = 00
18h = 18
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
System Management Bus Interface
Table 6-1.
Processor Information ROM Data (Sheet 2 of 6)
Sec #
Offset
Field Name
Data Type
Description
Example
25
19h
1Ah
VCCA Voltage Tolerance
High
2 Hex digits
Total tolerance (DC+AC) in mV
61mV = 3Dh
26
VCCA Voltage Tolerance
Low
2 Hex digits
6 bcd digits
Total tolerance (DC+AC) in mV
61mV = 3Dh
27
28
29
1Bh
1Ch
1Dh
VCCIO Voltage
Voltage in six 4-bit Hex digits in
mV^-2
1.11250V = 001125
1Bh = 25
1Ch = 11
1Dh = 00
30
31
1Eh
1Fh
VCCIO Voltage Tolerance
High
2 Hex digits
2 Hex digits
Total tolerance (DC+AC) in mV
Total tolerance (DC+AC) in mV
Reserved for future use
28 mV = 0x1C
28 mV = 0x1C
0x00
VCCIO Voltage Tolerance
Low
32
33
20h
21h
RESERVED
Checksum
Hex
Hex
Add up by byte and take 2's
complement
Core
34
35
36
37
22h
23h
24h
25h
Architecture Revision
Processor Core Family
Processor Core Model
Processor Core Stepping
Boost Core Frequency
2 Hex Digits
2 Hex Digits
2 Hex Digits
2 Hex Digits
4 bcd digits
From CPUID
From CPUID
From CPUID
From CPUID
Taken from
CPUID[3].archrev
Taken from
CPUID[3].family
Taken from
CPUID[3].model
Taken from
CPUID[3].revision
38
39
26h
27h
Maximum Specified operating
frequency of this part in MHz
(Intel® Itanium® Processor 9300
Series)
1733 MHz = 1733
26h = 33
27h = 17
(Intel® Itanium®
(Intel® Itanium®
Processor 9300 Series)
(Intel® Itanium®
Processor 9300
Series)
Processor 9300 Series)
2 bcd digits (0x26)
Core Count (0x26)
RESERVED (0x27)
(Intel® Itanium®
2 Hex digits
(0x27)
(Intel® Itanium®
Processor 9500
Series)
Number of available cores in the
processor (0x26) (Intel®
Itanium® Processor 9500 Series)
26h = 08
27h = 0x00
(Intel® Itanium®
Processor 9500 Series)
Processor 9500 Series)
40
41
28h
29h
Core Voltage ID
4 bcd digits
Voltage in four 4-bit Hex digits (in
mV)
1200 mV = 1200h
28h = 00
29h = 12
42
43
2Ah
2Bh
Core Voltage Tolerance,
High
2 Hex digits
2 Hex digits
Edge finger tolerance in mV, +
Edge finger tolerance in mV, -
Reserved for future use
20 mV = 0x14
20 mV = 0x14
0x00
Core Voltage Tolerance,
Low
44
45
2Ch
2Dh
RESERVED
Checksum
Hex
Hex
Add up by byte and take 2's
complement
Uncore
®
®
46
47
48
2Eh
2Fh
30h
Maximum Intel
6 bcd digits
Maximum Intel QuickPath
4.8 GT/s = 004800
2Eh = 00
QuickPath Interconnect
Link Transfer Rate
Interconnect Link Transfer rate
for this part in MT/s
2Fh = 48
30h = 00
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
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System Management Bus Interface
Table 6-1.
Processor Information ROM Data (Sheet 3 of 6)
Sec #
Offset
Field Name
Data Type
Description
Example
®
®
49
50
51
31h
32h
33h
Minimum Intel
6 bcd digits
Minimum Intel QuickPath
4.8 GT/s = 004800
31h = 00
QuickPath Interconnect
Link Transfer Rate
Interconnect Link Transfer rate
for this part in MT/s
32h = 48
33h = 00
®
®
52
53
54
55
56
34h
35h
36h
37h
38h
Intel QuickPath
4 8-bit ASCII Hex Intel QuickPath Interconnect
01.0 =
Interconnect version
Number
characters
version number supported by
processor
34h = 0x30
35h = 0x2E
36h = 0x31
37h = 0x30
Memory Support flags
Hex
Bit[0] FBD1 Support (LSB)
Bit[1] MB1 Support
0x01 = FB-DIMM 1 only
0x02 = MB1 only
0x03 = FB-DIMM 1 and
MB1 supported
Bit[2] MB2 Support
Bits[7:3] (MSBs) reserved
1 = supported, 0 = not supported
0x04 = MB2 only
0x06=MB2 and MB1
support
(Intel® Itanium®
Processor 9500 Series)
57
58
59
39h
3Ah
3Bh
Maximum Memory
Transfer Rate
6 bcd digits
6 bcd digits
4 bcd digits
Maximum Memory Transfer rate
for this part in GT/s
800 MT/s = 000800 GT/
s
39h = 00
3Ah = 08
3Bh = 00
60
61
62
3Ch
3Dh
3Eh
Minimum Memory
Transfer Rate
Minimum Memory Transfer rate
for this part in MT/s
800 MT/s = 000800 GT/
s
3Ch = 00
3Dh = 08
3Eh = 00
63
64
3Fh
40h
Uncore Voltage ID
Voltage in four 4-bit Hex digits (in
mV)
1200 mV = 1200
3Fh = 00
40h = 12
65
66
41h
42h
Uncore Voltage
Tolerance, High
2 Hex digits
2 Hex digits
Hex
Edge finger tolerance in mV, +
Edge finger tolerance in mV, -
Reserved for future use
20 mV = 0x14
Uncore Voltage
Tolerance, Low
20 mV = 0x14
67
68
69
43h
44h
45h
RESERVED
42h = 0x00
43h = 0x00
Checksum
Hex
Add up by byte and take 2's
complement
Cache
70
71
46h
47h
L3 (LLC) Cache Size
Cache Voltage ID
4 bcd digits
Size of the Cache, in MB.
24MB = 0024
46h = 24
47h = 00
72
73
48h
49h
4 bcd digits
Voltage in four 4-bit bcd digits (in
1163 mV = 1163
48h = 63
49 = 11
(Intel® Itanium®
(Intel® Itanium® mV) (Intel® Itanium® Processor
(Intel® Itanium®
Processor 9300 Series)
Processor 9300
Series)
2 Hex digits
(Intel® Itanium®
Processor 9500
Series)
9300 Series)
Processor 9300 Series)
RESERVED (Intel®
Itanium® Processor
9500 Series
48h = 0x00
49h = 0x00
(Intel® Itanium®
Reserved for future use
(Intel® Itanium® Processor 9500
Series)
Processor 9500 Series)
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Table 6-1.
Processor Information ROM Data (Sheet 4 of 6)
Sec #
Offset
4Ah
Field Name
Data Type
Description
Example
74
Cache Voltage
Tolerance, High (Intel®
Itanium® Processor
9300 Series)
2 Hex digits
Edge finger tolerance in mV, +
(Intel® Itanium® Processor 9300
Series)
20 mV = 0x14
(Intel® Itanium®
Processor 9300 Series)
4Ah = 0x00
(Intel® Itanium®
Processor 9500 Series)
RESERVED (Intel®
Itanium® Processor
9500 Series)
Reserved for future use
(Intel® Itanium® Processor 9500
Series)
75
4Bh
Cache Voltage
Tolerance, Low (Intel®
Itanium® Processor
9300 Series)
2 Hex digits
Edge finger tolerance in mV, -
(Intel® Itanium® Processor 9300
Series)
20 mV = 0x14
(Intel® Itanium®
Processor 9300 Series)
Reserved for future use
(Intel® Itanium® Processor 9500
Series)
4Bh = 0x00
(Intel® Itanium®
Processor 9500 Series)
RESERVED (Intel®
Itanium® Processor
9500 Series)
76
77
78
4Ch
4Dh
4Eh
RESERVED
Hex
Hex
Reserved for future use
4Ch = 0x00
4Dh = 0x00
Checksum
Add up by byte and take 2's
complement
Package
79
80
81
82
83
84
4Fh
50h
51h
52h
53h
54h
Package Revision
Five 8-bit ASCII
Hex characters
Package Revision Tracking
Number
Revision = 0INT3
4Fh = 0x30
50h = 0x49
51h = 0x4E
52h = 0x54
53h = 0x33
Substrate Revision
Software ID (Intel®
Itanium® Processor
9300 Series)
Hex
2-bit substrate revision number:
2 Bits (MSB)
6 Bits reserved (LSB)
(Intel® Itanium® Processor 9300
Series)
00b MSB
000000b Reserved
(Intel® Itanium®
Processor 9300 Series)
0x00 (Intel® Itanium®
Processor 9500 Series)
Reserved for future use for Intel®
Itanium® Processor 9500 Series
RESERVED (Intel®
Itanium® Processor
9500 Series)
85
55h
Checksum
Hex
Add up by byte and take 2's
complement
Part Numbers
86
87
88
89
90
91
92
56h
57h
58h
59h
5Ah
5Bh
5Ch
Processor Part Number
Seven 8-bit ASCII Processor Part Number
Hex Characters
PPN = 80603LW
56h = 0x57 = “W”
57h = 0x4C = “L”
58h = 0x33 = “3”
59h = 0x30 = “0”
5Ah = 0x36 = “6”
5Bh = 0x30 = “0”
5Ch = 0x38 = “8”
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System Management Bus Interface
Table 6-1.
Processor Information ROM Data (Sheet 5 of 6)
Sec #
Offset
Field Name
Data Type
Description
Example
93
94
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
Processor Electronic
Signature
16 Digit Hex
Number
64 - bit identification number;
may have padded zeros.
95
96
97
98
99
100
101
102
Base Core Freq
4 bcd digits
4 bcd digits
Base Core Frequency for this part
f = 1600 Mhz
65h = 00
66h = 16
103
104
67h
68h
RESERVED (Intel®
Itanium® Processor
9300 Series)
Reserved for future use (Intel®
Itanium® processor 9300 series)
67h = 0x00
68h = 0x00 (Intel®
Itanium® Processor
9300 Series)
Uncore Frequency
(Intel® Itanium®
Processor 9500 Series)
Nominal operating uncore
frequency in MHz
(Intel® Itanium® Processor 9500
Series)
2.4 GHz =
67h=0x00
68h=0x24
(Intel® Itanium®
Processor 9500 Series)
105
106
69h
6Ah
RESERVED
Checksum
Hex
Hex
Reserved for future use
69h = 0x00
Add up by byte and take 2's
complement
Thermal Reference
107
108
6Bh
6Ch
THERMALERT_N hot
assertion
2 Hex digits
2 Hex digits
Recommended THERMALERT_N
assertion threshold value
10C below PROCHOT_N
= 0x0A
THERMALERT_N hot
deassertion hysteresis
Recommended THERMALERT_N
deassertion threshold value
2C deassert = 0x02
This indicates a
THERMALERT_N
deassert of 10C + 2C
=12C below
PROCHOT_N
109
110
6Dh
6Eh
Maximum TDP
TCONTROL
2 Hex digits
2 Hex digits
Thermal Design Power Max
185 W = 0xB9
Default processor thermal
monitoring setpoint in C
5C below PROCHOT_N =
0x5
111
112
113
6Fh
70h
71h
6Fh = 0x00
70h = 0x00
RESERVED
Checksum
Hex
Hex
Reserved for future use
Add up by byte and take 2's
complement
®
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Table 6-1.
Processor Information ROM Data (Sheet 6 of 6)
Sec #
Offset
Field Name
Data Type
Features
Description
Example
114
115
116
117
72h
73h
74h
75h
Processor Core Feature
Flags
8 digit Hex
number
From CPUID
Flag = 0x4387FBFF
72h = 0xFF
73h = 0xFB
74h = 0x87
75h = 0x43
(Intel® Itanium®
Processor 9300 Series)
72h = 0x00
73h = 0x00
74h = 0x00
75h = 0x00
RESERVED
(Intel® Itanium®
Processor 9500 Series)
Reserved for future use (Intel®
Itanium® Processor 9500 Series)
(Intel® Itanium®
Processor 9500 Series)
118
119
120
121
76h
77h
78h
79h
RESERVED
Hex
Hex
Reserved for future use
76h = 0x00
77h = 0x00
Package Feature Flags
Bit[7:4] reserved
Flag = 0x000E
78h = 0x0E
79h = 0x00
Bit[3] = THERMALERT_N
threshold values present
Bit[2] = SCRATCH EEPROM
present
Bit[1] = Core VID present
Bit[0] reserved
where a 1 indicates valid data
122
123
7Ah
7Bh
RESERVED
Hex
Hex
Reserved for future use
7Ah = 0x00
Number of Devices in
TAP Chain
Bits [7:4] Number Devices in
processor TAP chain
Bits [3:0] Reserved
5 devices for Intel®
Itanium® Processor
9300 Series = 0x50
9 devices for Intel®
Itanium® Processor
9500 Series = 0x90
124
7Ch
Checksum
RESERVED
Hex
Add up by byte and take 2's
complement
Other
125
126
127
7Dh
7Eh
7Fh
Hex
Reserved for future use
7Dh = 0x00
7Eh = 0x00
7Fh = 0x00
6.2.2
Scratch EEPROM
Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
support a Scratch EEPROM section, which may be used for other data at the system
vendor’s discretion. The data in this EEPROM, once programmed, can be write-
protected by asserting the active-high SM_WP signal. This signal has a weak pull-down
(10 kΩ) to allow the EEPROM to be programmed in systems with no implementation of
this signal. The Scratch EEPROM resides in the upper half of the memory component
(addresses 80 - FFh). The lower half comprises the Processor Information ROM
(addresses 00 - 7Fh), which is permanently write-protected.
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6.2.3
PIROM and Scratch EEPROM Supported SMBus
Transactions
The PIROM responds to two SMBus packet types: Read Byte and Write Byte. However,
since the PIROM is write-protected, it will acknowledge a Write Byte command but
ignores the data. The Scratch EEPROM responds to Read Byte and Write Byte
commands. Table 6-2 illustrates the Read Byte command. Table 6-3 illustrates the
Write Byte command.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘A’ represents
an acknowledge (ACK), and ‘///’ represents a negative acknowledge (NACK). The
shaded bits are transmitted by the PIROM or Scratch EEPROM, and the bits that aren’t
shaded are transmitted by the SMBus host controller. In the tables, the data addresses
indicate 8 bits.
The SMBus host controller should transmit 8 bits with the most significant bit indicating
which section of the EEPROM is to be addressed: the PIROM (MSB = 0) or the Scratch
EEPROM (MSB = 1).
Table 6-2.Read Byte SMBus Packet
Slave
Address
Command
Code
Slave
Address
S
Write
A
A
S
Read
A
Data
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
8-bits
1
1
Table 6-3.Write Byte SMBus Packet
Slave
Command
Code
S
Write
A
A
Data
8-bits
A
P
Address
1
7-bits
1
1
8-bits
1
1
1
6.3
Memory Component Addressing
The Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500 Series
PIR_A[1:0] pins are used as the memory address selection signals. The processor does
not specify the value on these pins. It is left to the system architect to set the SMBus
memory map. If the processor is the only device on the bus, these pins may be tied to
VSS. PIR_A[2] is tied to VSS internal to the processor. Figure 6-1 shows the address
connections within the processor package.
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Figure 6-1. Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500
Series Package
SDA
SCL
PIR_SDA
PIR_SCL
WP
SM_WP
VSS
A2
A1
PIR_A1
PIR_A0
VCC33_SM
A0
VCC
SMBDAT
SMBCLK
SPDDAT
SPDCLK
SMBDAT
SMBCLK
SPDDAT
SPDCLK
BOOTMODE[1]
BOOTMODE[0]
THERMALERT_N
BOOTMODE[1]
BOOTMODE[0]
THERMALERT_N
SKTID[0]
SKTID[1]
SKTID[2]
SKTID[0]
SKTID[1]
SKTID[2]
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6.4
PIROM Field Definitions
PIROM data is divided into sections containing similar data. Each section contains
specific fields defined in the following sections.
6.4.1
General
To maintain backward compatibility, the General section defines the starting address for
each subsequent section of the PIROM. Software should check for the offset before
reading data from a particular section of the ROM.
The General section begins with offset 00h which contains Data Format Revision
information, followed by the EEPROM size, both formatted in Hex bytes. The data
format revision is used whenever fields within the PIROM are updated with new values.
Normally the revision would begin at a value of 1. If a field, or bit assignment within a
field, is changed such that software needs to discern between the old and new
definition, then the data format revision field should be incremented.
6.4.2
Processor Data
This section contains following pieces of data:
• Sample or Production field to identify a pre-production sample or a production unit.
• Required voltage regulator field
• VCCA and VCCIO voltage specs.
The sample or production field is a two-bit, LSB-aligned value. 0x00 indicates unlocked
PIROM section. This is the case in most samples. 0x01 indicates a locked PIROM
section. Some samples and all production parts will be locked.
The required voltage regulator field for the Intel® Itanium® Processor 9300 Series is
0x00. The required voltage regulator field for the Intel® Itanium® Processor 9500
Series is 0x01.
6.4.3
Processor Core Data
This section contains silicon-related data relevant to the processor cores.
6.4.3.1
CPUID
Offset 22h-25h contains a copy of the results in EAX[31:0] from Function 1 of the
CPUID instruction.
6.4.3.2
Boost Core Frequency
Offset 26h-27h provides the boost core frequency for the processor. The frequency
should equate to the markings on the processor even if the parts are not limited or
locked to the intended speed. Format of this field is in MHz, rounded to a whole
number, and encoded as four 4 bit-bcd digits. Offset 26h contains the core count for the
Intel® Itanium® Processor 9500 Series, while offset 27h is RESERVED for the Intel®
Itanium® Processor 9500 Series.
Example: For the Intel® Itanium® processor 9300 series, the 1733 GHz processor will
have a value of 1733. For the Intel® Itanium® Processor 9500 Series eight core SKU,
0x26 will have a value of 8.
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6.4.3.3
6.4.3.4
Core Voltage
Offset 28h-29h is the nominal core voltage for this part, rounded to the next
thousandth, is in mV and is reflected in bcd.
Example: 1500 mV is represented as 1500.
Core Voltage Tolerance
Offsets 2Ah and 2Bh contain the core voltage tolerances, high and low respectively.
These use a decimal to Hexadecimal conversion.
Example: 19 mV tolerance would be saved as 13h.
6.4.4
Processor Uncore Data
This section contains silicon-related data relevant to the processor Uncore.
®
6.4.4.1
Maximum Intel QuickPath Interconnect Link Transfer Rate
Offset 2Eh-30h provides maximum operating link transfer rate for the Intel® QuickPath
Interconnect. A link rate of 4.8 GT/s is expressed as 6 bcd digits in MT/s.
Example: 4.8 GT/s = 004800.
®
6.4.4.2
6.4.4.3
Minimum Operating Intel QuickPath Interconnect Link Transfer Rate
Offset 31h-33h provides minimum “operating” link transfer rate for the Intel®
QuickPath Interconnect. Systems may need to read this offset to decide if all installed
processors support the same link transfer rate. This does not relate to the “link power
up” transfer rate of 1/4th Ref Clk. This value is represented by 6 bcd digits.
®
Intel QuickPath Interconnect Version Number
Offset 34h-37h provides the Intel® QuickPath Interconnect Version Number as four 8-
bit ASCII characters.
Example: The Intel® Itanium® Processor 9300 Series processor supports Intel®
QuickPath Interconnect Version Number 1.0. Therefore, offset 34h-37h has an ASCII
value “01.0”, in reverse order.
34h: 30h, 35h: 2E, 36h: 31h, 37h: 30h.
6.4.4.4
Memory Type Support
Offset 38h signifies the type of memory support for this processor and platform.
A 01h signifies FBD1 support only (for Intel® Itanium® Processor 9300 Series), 02h is
Intel® 7500 Scalable Memory Buffer support only, and 04h represents support for
Intel® 7510/7520 Scalable Memory Buffers (Intel® Itanium® Processor 9500 Series)
only. A 06h represents support for both Intel® 7500 Scalable Memory Buffer and Intel®
7510/7520 Scalable Memory Buffers.
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6.4.4.5
Maximum Memory Transfer Rate
Offset 39h-3Bh provides maximum memory transfer rate on the Intel® Scalable
Memory Interconnect (Intel® SMI). Systems may need to read this offset to decide if
processors and Intel® 75xx Scalable Memory Buffers support the same Intel® SMI
transfer rate. Six 4-bit BCD digits are used to provide the maximum transfer rate in
MT/s.
Example: A speed of 4.8 GT/s is shown as 004800h.
6.4.4.6
6.4.4.7
Minimum Memory Transfer Rate
Offset 3Ch-3Eh provides minimum “operating” memory transfer rate on the Intel®
Scalable Memory Interconnect. Six 4-bit BCD digits are used to provide the minimum
transfer rate in MT/s.
Uncore Voltage
Offset 3Fh-40h is the nominal processor Uncore voltage for this part, rounded to the
next thousandthin mV and reflected in BCD.
Example: 1200 mV is stored as 3Fh: 00h, 40h: 12h.
6.4.4.8
Uncore Voltage Tolerance
Offset 41h and 42h contain the Uncore voltage tolerances, high and low respectively.
These use a decimal to Hexadecimal conversion. Example: 20 mV tolerance would be
saved as 14h.
6.4.5
Cache Data
This section contains cache related data.
6.4.5.1
L3 Cache Size
Offset 46h-47h is the L3 cache size field. The field reflects the size of the level three
cache in MBytes in bcd format.
Example: The Intel® Itanium® Processor 9300 Series has a 24 MB L3 cache. Thus,
offsets 46h & 47h will contain 24 & 00 respectively.
6.4.5.2
6.4.5.3
Cache Voltage
Offset 48h-49h is the nominal processor cache voltage for the Intel® Itanium®
Processor 9300 Series processor, rounded to the next thousandth, in mV and is
reflected in bcd.
These fields are RESERVED for the Intel® Itanium® Processor 9500 Series.
Cache Voltage Tolerance
Offset 4Ah and 4Bh contain the cache voltage tolerances, high and low respectively.
These use a decimal to Hexadecimal conversion.
Example: 20 mV tolerance would be saved as 14h.
These fields are RESERVED for the Intel® Itanium® Processor 9500 Series.
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6.4.6
Package Data
6.4.6.1
Package Revision
This section describes the package revision location at offset 4Fh-53h used to capture
package technology. This field tracks the highest level revision. It is provided in ASCII
Hex format of five characters.
This field is at offset 4Fh through 53h for the substrate layout design.
6.4.6.2
Substrate Revision Software ID
This field is at offset 54h for the substrate layout design for the Intel® Itanium®
Processor 9300 Series.
The field at offset 54h is reserved for the Intel® Itanium® Processor 9500 Series.
6.4.7
Part Number Data
This section between 56h and 6Ah provides part tracing ability. It also includes the
processor’s base frequency at 65h-66h.
6.4.7.1
Processor Part Number
Offset 56h-5Ch contains seven ASCII characters reflecting the Intel part number for the
processor. This information is typically marked on the outside of the processor. If the
part number is less than 7 characters, a leading space is inserted into the value.
Example: A processor with a part number of 80546KF will have data as 46h, 4bh, 36h,
34h, 35h, 30h, 38h starting at offset 56h.
6.4.7.2
6.4.7.3
Processor Electronic Signature
Offset 5Dh-64h contains a unique 64-bit identification number.
Base Frequency (Core)
Offset 65h-66h contain a bcd representation of core base frequency.
Example: A processor with a core base frequency of 1600 MHz will have data as 00, 16
starting at offset 65h.
6.4.7.4
Base Frequency (Uncore)
Offset 67h-68h contain the uncore frequency for the Intel® Itanium® Processor 9500
Series.
Example: a processor with an uncore frequency of 2.4 GHz will have data as 00, 24
starting at offset 67h.
6.4.8
Thermal Reference Data
6.4.8.1
Recommended Thermalert Hot Assertion Byte
Offset 6Bh contains the thermalert threshold expressed as the number of degrees C
below the PROCHOT_N (thermal throttling) temperature in Hex format.
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6.4.8.2
Recommended Thermalert Hot De-assertion Hysteresis
The de-assertion threshold is expressed as the number of degrees C below the
thermalert hot threshold value in Hex format.
Example: reading offset 6Bh=00001010 and 6Ch=0000010, then programming the
CSRs with these values means THERMALERT_N will be asserted when junction
temperature rises to 10C below the PROCHOT_N (thermal throttle) threshold and will
remain asserted until the junction temperature drops to 12°C below the PROCHOT_N
threshold.
6.4.8.3
6.4.8.4
Thermal Design Power
Offset 6Dh is programmed with 2 Hex digits representing the max TDP of the part.
Example: 6Dh = 0xB9 indicates a 185 W part.
TControl
Offset 6Eh contains the recommended TControl spec in degrees C below PROCHOT_N
temperature in Hex format.
6.4.9
Feature Data
This section provides information on key features that the platform may need to
understand without powering on the processor.
6.4.9.1
Processor Core Feature Flags
For the Intel® Itanium® Processor 9300 Series, offset 72h-75h contains a copy of
results in EDX[31:0] from Function 1 of the CPUID instruction. These details provide
instruction and feature support by product family. These fields are RESERVED for the
Intel® Itanium® Processor 9500 Series processor.
6.4.9.2
Package Feature Flags
Offset 78h-79h provides additional feature information from the processor. This field is
defined as follows:
Table 6-4.
Offset 78h/79h Definitions
Bit
Definition
4-32
Reserved
3
2
1
0
Thermal calibration offset byte present
Scratch (OEM) EEPROM present (set if there is a scratch ROM at offset 80 - FFh)
Core VID present (set if there is a VID provided by the processor)
Reserved
6.4.9.3
Number of Devices in TAP Chain
At offset 7Bh, a 4-bit Hex digit is used to tell how many devices are in the TAP Chain.
The four bits are the most significant bits at this offset.
Since Intel® Itanium® Processor 9300 Series and Intel® Itanium® Processor 9500
Series processors have one TAP per core plus a sysint TAP, this field would be set to 50h
for the Intel® Itanium® Processor 9300 Series processor and 90 for the Intel®
®
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Itanium® Processor 9500 Series. Note that even reduced core count Itanium products
(for example, 2-core Intel® Itanium® Processor 9300 Series) will still have all devices
on the TAP chain.
6.4.10
6.4.11
Other Data
Addresses 7Dh-7Fh are listed as reserved.
Checksums
The Processor Information section of the ROM includes multiple checksums. Table 6-5
includes the checksum values for each section defined in the 128 byte PIROM section,
except the Other Data section.
Table 6-5.
128 Byte PIROM Checksum Values
Section
Checksum Address
General
Processor Data
0Eh
21h
Processor Core Data
Processor Uncore Data
Cache Data
2Dh
45h
4Eh
Package Data
55h
Part Number Data
Thermal Reference Data
Feature Data
6Ah
71h
7Ch
Other Data
None Defined
Checksums are automatically calculated and programmed. The first step in calculating
the checksum is to add each byte from the field to the next subsequent byte. The
second step is to take the 2’s complement of the first step. This value is the checksum.
Example: For a byte string of AA445Ch, the resulting checksum will be B6h.
AA = 10101010
44 = 01000100
5C = 0101100
First step: add the bytes.
AA + 44 + 5C = 01001010
Second step: take 2’s complement.
10110101 +1 = 10110110
Checksum is 0xB6.
§
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Signal Definitions
7
Signal Definitions
This Chapter provides an alphabetical listing of all Intel® Itanium® Processor 9300
Series and Intel® Itanium® Processor 9500 Series signals. The tables list the signal
directions (Input, Output, I/O) and signal descriptions.
For a complete pinout listing including processor specific pins, please refer to
Chapter 3, “Pin Listing”.
Table 7-1.
Signal Definitions for the Intel® Itanium® Processor 9300 Series and Intel®
Itanium® 9500 Series (Sheet 1 of 8)
Name
Type
Description
®
®
BOOTMODE[1:0]
I
The BOOTMODE[1:0] inputs specify which way the Intel Itanium Processor 9300
®
®
Series and Intel Itanium Processor 9500 Series will boot. For details on the
modes, refer to the Intel Itanium Processor 9300 Series External Design
Specification or the Intel Itanium Processor 9500 Series External Design
Specification. To pull any of these inputs high, they should be strapped to VCCIO
through a pull-up resistor, and to pull these low, they should be strapped to GND.
These pins are sampled during all resets except warm-logic reset.
®
®
®
®
CPU_PRES[A|B]_N
CPU_PRES[1:4]_N
I/O
I/O
CPU Present pads. These pins at the top of the package are part of a daisy chain
that indicates to the platform that the processor and Ararat are properly installed
into the socket.
CPU Present Pads. These pads at the bottom of the package are part of a daisy
chain that indicates to the platform that the processor and Ararat are properly
installed into the socket. Motherboard routing guidelines for these pins are
®
®
®
®
documented in the Intel Itanium 9300 Series Processor and Intel Itanium
Processor 9500 Series Platform Design Guide.
®
®
CSI[5:0]R[P/N]CLK
I
The receive clock signals are inputs to the Intel Itanium Processor 9300 Series
®
®
and Intel Itanium 9500 Series and are required to be the same frequency at
both ends but may differ by a fixed phase. An Intel QuickPath Interconnect local
®
receiver port receives a forwarded clock from the transmitter side of the remote
port and vice-versa, to maintain timing reference at either end of the link.
®
Intel
QuickPath
5:0
R
P/N
CLK0
Interconnect
Interface Name Port
Receiver
Differential Pair Clock0
Number
Polarity
Positive/
Negative
Example: CSI4RPCLK represents port 5 clock receive signal and positive bit of the
differential pair.
CSI[5:0]T[P/N]CLK
O
These transmit clock signals are driven by the processor and are required to be the
®
same frequency at both ends but may differ by a fixed phase. An Intel QuickPath
Interconnect local port transmit side sends a forwarded clock to the receive side of
the remote port and vice-versa, to maintain timing reference at either end of the
link.
®
Intel
QuickPath
5:0
T
P/N
CLK0
Clock0
Interconnect
Interface Name Port Number Transmitter
Differential
Pair
Polarity
Positive/
Negative
Example: CSI4TPCLK represents port 5 clock transmit signal and positive bit of the
differential pair.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
159
Signal Definitions
Table 7-1.
Signal Definitions for the Intel® Itanium® Processor 9300 Series and Intel®
Itanium® 9500 Series (Sheet 2 of 8)
Name
Type
Description
CSI[3:0]R[P/N]Dat[19:0],
CSI[5:4]R[P/N]Dat[9:0]
I
These input data signals provide means of communication between two ports via
one uni-directional transfer link (In). The RX links, are terminally ground
referenced. The ports [3:0] with [19:0] bit lanes can be configured as a full width
link with all 20 active lanes, a half width link with 10 active lanes or as a quarter
width link with five active lanes.
®
Intel
QuickPath
5:0
R
P/N
DAT[19:0]
Interconnect
Interface Name Port
Receiver
Differential
Pair
Lane
Number
Number
Polarity
Positive/
Negative
Example: CSI4RPDAT[0] represents port 5 Data, lane 0, receive signal and positive
bit of the differential pair.
CSI[3:0]T[P/N]Dat[19:0],
CSI[5:4]T[P/N]Dat[9:0]
O
These output data signals provide means of communication between two ports via
one uni-directional transfer link (Out).The links, Tx, are terminally ground
referenced. The ports [3:0] with [19:0] bit lanes can be configured as a full width
link with 20 active lanes, a half width link with 10 active lanes or as a quarter width
link with five active lanes.
®
Intel
QuickPath
Interconnect
5:0
T
P/N
DAT[19:0]
Interface Name Port
Transmitter Differential
Pair
Lane
Number
Number
Polarity
Positive/
Negative
Example: CSI4TPDAT[0] represents port 5 Data, lane 0, transmit signal and
positive bit of the differential pair.
ERROR[0]_N
ERROR[1]_N
O
O
Side band signaling for system management.
®
®
®
®
Refer to the Intel Itanium Processor 9300 Series and Intel Itanium Processor
9500 Series Platform Design Guide for pin considerations.
Side band signaling for system management. Assertion on this pin indicates that an
error reset response is required from the platform.
®
®
®
®
Refer to the Intel Itanium Processor 9300 Series and Intel Itanium Processor
9500 Series Platform Design Guide for pin considerations.
FBD0NBICLK[A/B][P/N]0
I
These differential pair clock signals generated from the branch zero, channel A and
B of FB-DIMMs are input to the processor.
FB-
DIMM
0
NB
I
CLK
A/B
P/N
Interface Branch
Name
North
Input
Clock
Channel
Differential
Pair
Number Bound
Polarity
Positive/
Negative
Example: FBD0NBICLKAP0 represents FB-DIMM branch 0, northbound clock input
signal of channel A and positive bit of the differential pair.
®
®
160
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Signal Definitions
Table 7-1.
Signal Definitions for the Intel® Itanium® Processor 9300 Series and Intel®
Itanium® 9500 Series (Sheet 3 of 8)
Name
Type
Description
FBD1NBICLK[C/D][P/N]0
I
These differential pair clock signals generated from the branch one, channel C and
D of FB-DIMMs are input to the processor.
FB-
DIMM
1
NB
I
CLK
C/D
P/N
Interface Branch
Name
North
Input
Clock
Channel Differential
Pair
Number Bound
Polarity
Positive/
Negative
Example: FBD1NBICLKDP0 represent FB-DIMM branch 1, northbound clock input
signal of channel D and positive bit of the differential pair.
FBD0SBOCLK[A/B][P/N]0
O
These differential pair output clock signals generated from the processor are inputs
to the branch zero, channel A and B of FB-DIMMs.
FB-
DIMM
0
SB
O
CLK
A/B
P/N
Interface Branch
Name
South
Output
Clock
Channel Differential
Pair
Number Bound
Polarity
Positive/
Negative
Example: FBD0SBICLKAP0 represent FB-DIMM branch 0, southbound clock output
signal of channel A and positive bit of the differential pair.
FBD1SBOCLK[C/D][P/N]0
O
These differential pair output clock signals generated from the processor are inputs
to the branch one, channel C and D of FB-DIMMs.
FB-
DIMM
1
SB
O
CLK
C/D
P/N
Interface Branch
Name
South
Output
Clock
Channel Differential
Pair
Number Bound
Polarity
Positive/
Negative
Example: FBD1SBICLKDP0 represents FB-DIMM branch 1, southbound clock output
signal of channel D and positive bit of the differential pair.
®
®
FBD[0/1]REFSYSCLK[P/N]
FBD0NBI[A/B][P/N][12:0]
I
I
These signals are no longer used by the Intel Itanium Processor 9300 Series and
Intel Itanium 9500 Series.
®
®
These differential pair data signals generated from the branch zero, channel A and
B of FB-DIMMs are input to the processor.
FB-
DIMM
0
NB
I
A/B
P/N
[12:0]
Interface Branch
Name
North
Input
Channel Differential Lane
Number Bound
Pair
Number
Polarity
Positive/
Negative
Example: FBD0NBIAP[0] represent FB-DIMM branch 0, northbound data input lane
0 signal of channel A and positive bit of the differential pair.
FBD0NBI[A/B][P/N][13]
I
These signals are spare lanes, and are intended for Reliability, Availability, and
®
®
Serviceability (RAS) coverage on the Intel Itanium 9500 Processor Series. These
®
®
signals are not used by Intel Itanium 9300 Processor Series.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
161
Signal Definitions
Table 7-1.
Signal Definitions for the Intel® Itanium® Processor 9300 Series and Intel®
Itanium® 9500 Series (Sheet 4 of 8)
Name
Type
Description
FBD1NBI[C/D][P/N][12:0]
I
These differential pair data signals generated from the branch one, channel C and D
of FB-DIMMs are input to the processor.
FB-
DIMM
1
NB
I
C/D
P/N
[12:0]
Interface Branch
Name
North
Input
Channel Differential Lane
Number Bound
Pair
Number
Polarity
Positive/
Negative
Example: FBD1NBICP[0] represents FB-DIMM branch 1, northbound data input lane
0 signal of channel C and positive bit of the differential pair.
FBD1NBI[C/D][P/N][13]
FBD0SBO[A/B][P/N][9:0]
I
These signals are spare lanes, and are intended for Reliability, Availability, and
®
®
Serviceability (RAS) coverage on the Intel Itanium 9500 Processor Series. These
®
®
signals are not used by Intel Itanium 9300 Processor Series.
O
These differential pair output data signals generated from the processor to the
branch zero, channel A and B of FB-DIMMs.
FB-
DIMM
0
SB
O
A/B
P/N
[9:0]
Interface Branch
South
Output
Channel Differential Lane
Name
Number Bound
Pair
Number
Polarity
Positive/
Negative
Example: FBD0SBOAP[0] represents FB-DIMM branch 1, southbound data output
lane 0 signal of channel A and positive bit of the differential pair.
FBD0SBO[A/B][P/N][10]
FBD1SBO[C/D][P/N][9:0]
O
O
These signals are spare lanes, and are intended for Reliability, Availability, and
®
®
Serviceability (RAS) coverage on the Intel Itanium 9500 Processor Series. These
®
®
signals are not used by Intel Itanium 9300 Processor Series.
These differential pair output data signals generated from the processor to the
branch one, channel C and D of FB-DIMMs.
FB-
DIMM
1
NB
O
C/D
P/N
[9:0]
Interface Branch
Name
North
Output
Channel Differential Lane
Number Bound
Pair
Number
Polarity
Positive/
Negative
Example: FBD1SBOCP[0] represents FB-DIMM branch 1, southbound data output
lane 0 signal of channel C and positive bit of the differential pair.
FBD1SBO[C/D][P/N][10]
FLASHROM_CFG[2:0]
O
I
These signals are spare lanes, and are intended for Reliability, Availability, and
®
®
Serviceability (RAS) coverage on the Intel Itanium 9500 Processor Series. These
®
®
signals are not used by Intel Itanium 9300 Processor Series.
These are input signals to the processor that would initialize and map the Flash
ROM upon reset. After reset is deasserted this input would be ignored by the
processor logic. These pins are sampled during all resets except warm-logic reset.
FLASHROM_CLK
O
O
I
The Flash ROM clock.
FLASHROM_CS[3:0]_N
FLASHROM_DATI
FLASHROM_DATO
FLASHROM_WP_N
Flash ROM chip selects. Up to four separate flash ROM parts may be used.
Serial Data Input (from ROM(s) to processor).
Serial Data Output (from processor to ROM(s))
Flash ROM write-protect.
O
O
®
®
162
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Signal Definitions
Table 7-1.
Signal Definitions for the Intel® Itanium® Processor 9300 Series and Intel®
Itanium® 9500 Series (Sheet 5 of 8)
Name
Type
Description
FORCEPR_N
LRGSCLSYS
I
When logic 0, forces processor power reduction.
®
®
®
®
Refer to the Intel Itanium 9300 Series Processor and Intel Itanium Processor
9500 Series Platform Design Guide for a detailed signal description.
I
I
The header mode is selected by the LRGSCLSYS strapping pin value sampled only
during COLD reset. LRGSCLSYS, when tied to VCCIO using a 50 ohm resistor, puts
the processor in extended header mode, and LRGSCLSYS, when tied to GND, puts
the processor in standard header mode.
®
®
MEM_THROTTLE_L
When this pin is asserted on the Intel Itanium Processor 9300 Series, the
internal memory controllers throttle the memory command issue rate to a
configurable fraction of the nominal command rate settings. This pin is not used on
®
®
the Intel Itanium 9500 Processor Series.
PIR_SCL
I
I/O
I
(Processor Information ROM Serial Clock): The PIR_SCL input clock is used to clock
data into and out of the on package PIROM device. This signal applies to the
EEPROM, which is composed of the PIROM and the OEM Scratch PAD.
PIR_SDA
(Processor Information ROM Serial Data): The PIR_SDA pin is a bidirectional signal
for serial data transfer. This signal applies to the EEPROM, which is composed of the
PIROM and the OEM Scratch PAD.
PIR_A0, PIR_A1
SM_WP
(Processor Information ROM Address[0:1]): The PIR_A[0:1] pins are used as the
PIROM memory address selection signals. This bus applies to the EEPROM, which is
composed of the PIROM and the OEM Scratch PAD.
I
WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch
EEPROM is write-protected when this input is pulled high to VCC33_SM.
PRBMODE_REQ_N
PRBMODE_RDY_N
PROCHOT_N
I
Input from Extended Debug Port (XDP) to make a probe mode request.
Output to XDP to acknowledge probe mode request.
O
O
The assertion of PROCHOT_N (processor hot) indicates that the processor die
temperature has reached its thermal limit.
PROCTYPE
O
PROCTYPE output informs the platform the processor type. PROCTYPE is tied to VSS
®
®
internally to indicate the Intel Itanium 9300 Processor Series and VCC33_SM
®
®
internally to indicate the Intel Itanium 9500 Processor Series. This pin does not
require a platform pull-up or pull-down.
PWRGOOD
I
The processor requires this signal to be a clean indication that all the processor
clocks and power supplies are stable and within their specifications. “Clean” implies
that the signal will remain low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor. This signal is used to
protect internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
RESET_N
I
Asserting the RESET_N signal resets the processor to a known state and invalidates
its internal caches without writing back any of their contents. BOOTMODE[0:1]
signals are sampled during all RESET_N assertions for selecting appropriate
BOOTMODE.
RSVD
These pins are reserved and must be left unconnected.
SKTID[2:0]
I
I
Socket ID strapping pins. To pull any of these inputs high, they should be strapped
to VCCIO, and to pull them low, they should be strapped to VSS. SKTID[2:0]
partially determine the node address.
SMBCLK
SMBDAT
The SMBus Clock (SMBCLK) signal is an input clock to the system management
logic which is required for operation of the system management features of the
®
®
®
®
Intel Itanium Processor 9300 Series and Intel Itanium 9500 Series
processors. This clock is driven by the SMBus controller and is asynchronous to
®
®
other clocks in the processor. This is an open drain signal. Intel Itanium
Processor 9300 Series and Intel Itanium 9500 Series are Slave only.
®
®
I/O
The SMBus Data (SMBDAT) signal is the data signal for the SMBus. This signal
provides the single-bit mechanism for transferring data between SMBus devices.
®
®
®
This is an open drain signal. Intel Itanium Processor 9300 Series and Intel
®
Itanium 9500 Series are Slave only.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
163
Signal Definitions
Table 7-1.
Signal Definitions for the Intel® Itanium® Processor 9300 Series and Intel®
Itanium® 9500 Series (Sheet 6 of 8)
Name
Type
Description
SPDCLK
SPDDAT
I/O
This is a bi-directional clock signal between the processor, DRAM SPD registers and
®
external components on the board. This is an open drain signal. The Intel
®
Itanium Processor 9300 Series and 9500 Series Processors are Master only; refer
®
®
to the Intel Itanium Processor 9300 Series External Design Specification or
®
®
Intel Itanium Processor 9500 Series External Design Specification for limitations.
I/O
This is a bi-directional data signal between the processor, DRAM SPD registers and
®
®
external components on the board. This is an open drain signal. Intel Itanium
Processor 9300 Series and 9500 Series Processors are Master only; refer to the
Intel Itanium Processor 9300 Series External Design Specification or Intel
Itanium Processor 9500 Series External Design Specification for limitations.
®
®
®
®
SVID_CLK
O
This a source-synchronous clock used by the processor to transmit voltage ID data
to the Ararat II voltage regulator. This is an open drain signal. See Ararat II Voltage
®
Regulator Module Design Guide for termination requirements for the Intel
®
Itanium 9500 Processor Series.
®
®
SVID_DATIO
I/0
This is a bi-directional data signal between the Intel Itanium 9500 Processor
Series and the Ararat II voltage regulator. This is an open drain signal. See Ararat II
Voltage Regulator Module Design Guide for termination requirements for the Intel
®
®
Itanium 9500 Processor Series.
SVID_ALERT_N
I
I
This is an asynchronous signal driven by the Ararat II voltage regulator to indicate
the need to read the status register. See Ararat II Voltage Regulator Design Guide
®
®
for termination requirements for the Intel Itanium 9500 Processor Series.
SYSCLK/SYSCLK_N
The differential clock pair SYSCLK/SYSCLK_N provides the fundamental clock
source for the processor. All processor link agents must receive these signals to
drive their outputs and latch their inputs. All external timing parameters are
specified with respect to the rising edge of SYSCLK crossing the falling edge of
SYSCLK_N. This differential clock pair should not be asserted until VCCA, VCCIO,
VCC33_SM, and VCC (12 V Ararat) are stabilized.
SYSUTST_REFCLK/
SYSUTST_REFCLK_N
I
These serve as reference clocks for the processor socket logic analyzer interposer
device during debug. It is not used by the processor, and is not connected internally
to the die. Electrical specifications on these clocks are identical to SYSCLK/
SYSCLK_N.
TCK
TDI
I
I
Test Clock (TCK) provides the clock input for the processor TAP.
Test Data In (TDI) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
O
Test Data Out (TDO) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
TESTHI[1]
I
I
This pin must be tied to VCCIO using a 50 ohm resistor.
This pin must be tied to VCCIO using a 50 ohm resistor.
This pin must be tied to VCCIO using a 5k ohm resistor.
TESTHI[2]
TESTHI[4]
I
THERMALERT_N
O
Thermal Alert (THERMALERT_N) is an output signal and is asserted when the on-die
thermal sensors readings exceed a pre-programmed threshold.
THERMTRIP_N
O
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. Thermal Trip will activate at a temperature that is significantly
above the maximum case temperature (TCASE) to ensure that there are no false
trips. Once activated, the processor will stop all execution and the signal remains
latched until RESET_N goes active. There is no hysteresis built into the thermal
sensor itself; as long as the die temperature drops below the trip level, a RESET_N
pulse will reset the processor and execution will continue. If the temperature has
not dropped below the trip level, the processor will continue to drive THERMTRIP_N
and remain stopped.
TMS
I
I
I
Test Mode Select (TMS) is a JTAG specification support signal used by debug tools.
TRIGGER[1:0] pins are needed for XDP connectivity.
TRIGGER[1:0]
TRST_N
Test Reset (TRST_N) resets the TAP logic. TRST_N must be driven electrically low
during power on Reset.
VCC33_SM
I
VCC33_SM is a 3.3 V supply to the processor package, required for the PIROM
interface on the processor package and also Flash device. This pin must be routed
to a 3.3 V supply.
®
®
164
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
Signal Definitions
Table 7-1.
Signal Definitions for the Intel® Itanium® Processor 9300 Series and Intel®
Itanium® 9500 Series (Sheet 7 of 8)
Name
Type
Description
VCCA
I
VCCA provides a +1.8 V isolated power supply to the analog portion of the internal
®
®
®
®
PLL’s. Refer to the Intel Itanium Processor 9300 Series and Intel Itanium
Processor 9500 Series Platform Design Guide for routing/decoupling
recommendations for VCCA.
®
®
VCCCACHE
I
I
I
I
This provides power to the Cache on the Intel Itanium 9300 Processor Series.
This is on the top of the package and is driven by the Ararat Voltage Regulator.
Actual value of the voltage is determined by the settings of VID_VCCCACHE[5:0].
VCCCACHESENSE/
VSSCACHESENSE
Remote sense lines used by the Ararat Voltage Regulator to sense VCCCACHE die
voltage. The Voltage Regulator should not draw more than 0.1mA from these pads.
VCCCORE
This provides power to the Cores on the processor. This is on the top of the package
and is driven by the Ararat Voltage Regulator. Actual value of the voltage is
determined by the settings of VID_VCCCORE[6:0].
VCCCORESENSE/
VSSCORESENSE
Remote sense lines used by the Ararat Voltage Regulator to sense VCCCORE die
voltage. The Voltage Regulator should not draw more than 0.1mA from these pads.
VCCUNCORE
This provides power to the Uncore on the processor. This is on the top of the
package and is driven by the Ararat Voltage Regulator. Actual value of the voltage is
determined by the settings of VID_VCCUNCORE[6:0].
VCCUNCORESENSE/
VSSUNCORESENSE
Remote sense lines used by the Ararat Voltage Regulator to sense VCCUNCORE die
voltage. The Voltage Regulator should not draw more than 0.1mA from these pads.
VCCUNCOREREADY
This signal is sent to the processor from the Ararat. When high, the VCCUNCORE
rail has completed its startup sequence and is at a nominal operating voltage.
VCCIO
I
I
VCCIO provides power to the input/output interface on the processor die.
VCCIO_FBD
VCCIO_FBD provides power to the FBD_DIMM input/output interface on the
processor die.
VFUSERM
I
This pin must be tied to VCCIO or connected to VCCIO via 0 ohm resistor.
VID_VCCCORE[6:0]
VID_VCCUNCORE[6:0]
VID_VCCCACHE[5:0]
O
VCCCORE_VID, VCCUNCORE_VID and VID_VCCCACHE (Voltage ID) pads are used
to support automatic selection of VCCCORE, VCCUNCORE and VCCCACHE by the
®
®
Intel Itanium 9300 Processor Series. The VCCCORE, VCCUNCORE and
VCCCACHE Voltage Regulator (Ararat) outputs must be disabled prior to these pins
becoming invalid. The VID pins are needed to support processor voltage
specification variations. The VCCCORE, VCCUNCORE and VCCCACHE Voltage
Regulator (Ararat) outputs must supply the voltage that is requested by these pins,
or disable itself.
VR_FAN_N
I/O
This signal is open drain/collector driven by Ararat Voltage Regulator into a pad at
the top of the processor package and out through a pin at the bottom of the
processor package. When asserted, it indicates that the temperature on the Ararat
solution is approximately 10% below the VR_THERMTRIP_N limit. The Processor
cores do not monitor or respond to this signal. The Platform could monitor this pin
to implement thermal management, such as controlling fan speed (airflow). See
Ararat 170W Voltage Regulator Module Design Guide and /or Ararat II Voltage
Regulator Module Design Guidefor platform-specific requirements.
VR_PROCTYPE[1:0]
VR_THERMALERT_N
O
VR_PROCTYPE output informs the Ararat Voltage Regulator the processor type.
®
®
®
These pins are ‘00 on Intel Itanium 9300 Processor Series, and ‘01 for the Intel
®
Itanium 9500 Processor Series. These pads are located at the top of the package.
Future processors may use different bit configurations for this bus.
I /O
This signal is open drain/collector driven by Ararat Voltage Regulator into a pad at
the top of the processor package and out through a pin at the bottom of the
processor package. When asserted, it indicates that the temperature on the Ararat
solution is about to exceed the VR_THERMTRIP_N limit. When enabled in the
processor, this signal causes the processor to enter a throttling state to reduce the
power consumption level. The Platform could monitor this pin to implement thermal
management. See Ararat 170W Voltage Regulator Module Design Guide and/or
Ararat II Voltage Regulator Module Design Guide for platform requirements on
driving this signal.
®
®
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
165
Signal Definitions
Table 7-1.
Signal Definitions for the Intel® Itanium® Processor 9300 Series and Intel®
Itanium® 9500 Series (Sheet 8 of 8)
Name
Type
Description
VR_THERMTRIP_N
I/O
This signal is open drain/collector driven by Ararat Voltage Regulator into a pad at
the top of the processor package and out through a pin at the bottom of the
processor package. When asserted, it indicates that the temperature on the Ararat
solution has exceeded a critical threshold and it is required to shut down the Ararat
solution immediately. The Processor cores do not monitor or respond to this signal.
The Platform should immediately de-assert VROUTPUT_ENABLE0. If the Platform
does not respond to this signal, the Ararat Voltage Regulator is permitted to
shutdown, but should latch VR_THERMTRIP_N low, which can be reset by a power
cycle or de-assertion of VROUTPUT_ENABLE0. VR_THERMTRIP_N trip point is
determined by the Ararat Voltage Regulator Module Design and it should be set
such that VR_THERMTRIP_N is asserted prior to permanent damage to the Ararat
voltage regulator. See Ararat 170W Voltage Regulator Module Design Guide and/or
Ararat II Voltage Regulator Module Design Guide for platform requirements on
driving this signal.
VROUTPUT_ENABLE0
I/O
This signal is an input to the processor package (bottom), and drives into the Ararat
voltage regulator from the top of the package. When this signal is asserted, the
VIDs become active and the voltage regulator’s startup sequence begins. When this
signal is pulled down, the Ararat Voltage regulator should shut down VCCCORE,
VCCUNCORE and VCCCACHE (Intel Itanium 9300 Processor Series only). See
Ararat 170W Voltage Regulator Module Design Guide and/or Ararat II Voltage
Regulator Module Design Guide for platform requirements on driving this signal.
®
®
VRPWRGD (Ararat)
/VR_READY (Ararat II)
I /O
This signal is open drain/collector driven by Ararat Voltage Regulator into a pad at
the top of the processor package and out through a pin at the bottom of the
processor package. When pulled up (active high state), it indicates that the supply
voltages to VCCCORE, VCCUNCORE, and VCCCACHE are stable within their voltage
specification, and indicates that the Ararat VR start up sequence is completed. This
signal will transition to a logic low for power off sequencing and/or any Ararat VR
fault condition. See Ararat 170W Voltage Regulator Module Design Guide and/or
Ararat II Voltage Regulator Module Design Guide for platform requirements on pull-
up resistors and filtering.
VSS
I
I/O
I
VSS is the ground plane for the processor.
XDPOCPD[7:0]
XDPOCP_STRB_IN_N
XDPOCP_STRB_OUT_N
XDPOCP_FRAME_N
Bidirectional XDP data.
Input clock center-aligned with XDPOCP_FRAME_N and XDPOCPD[7:0].
Output clock edge-aligned with XDPOCP_FRAME_N and XDPOCPD[7:0].
Bidirectional signal indicating valid data on XDPOCPD[7:0].
O
I/O
§
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
1
Introduction..............................................................................................................9
1.1
1.2
Overview ...........................................................................................................9
Architectural Overview....................................................................................... 15
1.2.1 Intel® Itanium® Processor 9300 Series Overview ....................................... 15
1.2.2 Intel® Itanium® Processor 9500 Series Overview ....................................... 16
Processor Feature Comparison ............................................................................ 19
Processor Abstraction Layer................................................................................ 20
Mixing Processors of Different Frequencies and Cache Sizes .................................... 20
Terminology ..................................................................................................... 20
State of Data.................................................................................................... 21
Reference Documents........................................................................................ 21
1.3
1.4
1.5
1.6
1.7
1.8
2
Electrical Specifications........................................................................................... 23
2.1
Intel® QuickPath Interconnect and Intel® Scalable Memory Interconnect
Differential Signaling ......................................................................................... 23
Signal Groups................................................................................................... 24
Reference Clocking Specifications ........................................................................ 26
Intel® QuickPath Interconnect and Intel® SMI Signaling Specifications..................... 28
2.4.1 Intel® Itanium® Processor 9300 Series
2.2
2.3
2.4
Intel® QuickPath Interconnect and
Intel® SMI Specifications for 4.8 GT/s....................................................... 28
2.4.2 Intel® Itanium® Processor 9500 Series Requirements for
Intel® QuickPath Interconnect for 4.8 and 6.4 GT/s .................................... 32
2.4.3 Intel® Itanium® Processor 9500 Series Processor Requirements for
Intel® SMI Specifications for 6.4 GT/s....................................................... 37
Processor Absolute Maximum Ratings................................................................... 38
2.5.1 Intel® Itanium® Processor 9300 Series Absolute Maximum Ratings............... 39
2.5.2 Intel® Itanium® Processor 9500 Series Absolute Maximum Ratings............... 39
Processor DC Specifications ................................................................................ 39
2.6.1 Flexible Motherboard Guidelines for the Intel® Itanium®
2.5
2.6
Processor 9300 Series............................................................................. 40
2.6.2 Flexible Motherboard Guidelines for the Intel® Itanium®
Processor 9500 Series............................................................................. 43
2.6.3 Intel® Itanium® Processor 9300 Series Uncore, Core, and Cache Tolerances.. 44
2.6.4 Intel® Itanium® Processor 9500 Series Uncore and Core Tolerances ............. 49
2.6.5 Overshoot and Undershoot Guidelines....................................................... 52
2.6.6 Signal DC Specifications.......................................................................... 53
2.6.7 Motherboard-Socket Specification for VR Sense Point .................................. 57
Core and Uncore Voltage Identification................................................................. 57
2.7.1 Core and Uncore Voltage Identification for the
2.7
Intel® Itanium® Processor 9300 Series.................................................... 58
2.7.2 Core and Uncore Voltage Identification for the
Intel® Itanium® Processor 9500 Series ..................................................... 59
Cache Voltage Identification (Intel® Itanium® Processor 9300 Series only) ............... 62
RSVD, Unused, and DEBUG Pins.......................................................................... 63
2.8
2.9
2.10 Mixing Processors.............................................................................................. 64
2.11 Supported Power-up Voltage Sequence ................................................................ 64
2.11.1 Supported Power-up Voltage Sequence for the
Intel® Itanium® Processor 9300 Series.................................................... 66
2.11.2 Supported Power-up Voltage Sequence for the
Intel® Itanium® Processor 9500 Series ..................................................... 67
2.11.3 Power-up Voltage Sequence Timing Requirements ...................................... 68
2.12 Supported Power-down Voltage Sequence ............................................................ 68
2.13 Timing Relationship Between RESET_N and SKTID................................................. 69
2.14 Test Access Port (TAP) Connection....................................................................... 71
3
Pin Listing ............................................................................................................... 73
3.1
Processor Package Bottom Pin Assignments .......................................................... 73
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
167
3.1.1 Package Bottom Pin Listing by Pin Name....................................................73
3.1.2 Pin Listing by Pin Number ........................................................................89
Processor Package Top Pin Assignments..............................................................105
3.2.1 Top-Side J1 Connector Two-Dimensional Table .........................................105
3.2.2 Top-Side J2 Connector Two-Dimensional Table .........................................108
3.2.3 Top-Side J3 Connector Two-Dimensional Table .........................................111
3.2.4 Top-Side J4 Connector Two-Dimensional Table .........................................114
3.2
4
Mechanical Specifications ......................................................................................119
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Package Mechanical Drawing.............................................................................120
Intel® Itanium® Processor 9300 Series...............................................................121
Processor Component Keepout Zones.................................................................129
Package Loading Specifications..........................................................................129
Package Handling Guidelines.............................................................................129
Processor Mass Specifications............................................................................130
Processor Materials ..........................................................................................130
Package Markings............................................................................................130
5
Thermal Specifications...........................................................................................133
5.1
Thermal Features.............................................................................................133
5.1.1 Digital Thermometer .............................................................................134
5.1.2 Thermal Management............................................................................135
5.1.3 Thermal Alert.......................................................................................136
5.1.4 TCONTROL...........................................................................................137
5.1.5 Thermal Warning..................................................................................137
5.1.6 Thermal Trip ........................................................................................137
5.1.7 PROCHOT ............................................................................................138
5.1.8 FORCEPR_N Signal Pin...........................................................................138
5.1.9 Ararat Voltage Regulator Thermal Signals ................................................138
Package Thermal Specifications and Considerations..............................................139
Storage Conditions Specifications.......................................................................140
5.2
5.3
6
System Management Bus Interface........................................................................143
6.1
6.2
Introduction....................................................................................................143
SMBus Memory Component...............................................................................144
6.2.1 Processor Information ROM (PIROM) .......................................................144
6.2.2 Scratch EEPROM...................................................................................149
6.2.3 PIROM and Scratch EEPROM Supported SMBus Transactions.......................150
Memory Component Addressing.........................................................................150
PIROM Field Definitions.....................................................................................152
6.4.1 General...............................................................................................152
6.4.2 Processor Data.....................................................................................152
6.4.3 Processor Core Data..............................................................................152
6.4.4 Processor Uncore Data ..........................................................................153
6.4.5 Cache Data..........................................................................................154
6.4.6 Package Data.......................................................................................155
6.4.7 Part Number Data.................................................................................155
6.4.8 Thermal Reference Data ........................................................................155
6.4.9 Feature Data........................................................................................156
6.4.10 Other Data ..........................................................................................157
6.4.11 Checksums ..........................................................................................157
6.3
6.4
7
Signal Definitions...................................................................................................159
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
Intel® Itanium® Processor 9300 Series Processor Block Diagram............................. 16
Intel® Itanium® Processor 9500 Series Processor Block Diagram............................. 17
Intel® Itanium® Processor 9500 Series Firmware Diagram...................................... 18
Active ODT for a Differential Link Example............................................................ 23
Single-ended Maximum and Minimum Levels and Vcross Levels............................... 27
Vcross-delta Definition....................................................................................... 27
Differential Edge Rate Definition.......................................................................... 28
VRB and TStable Definitions................................................................................ 28
TX Equalization Diagram .................................................................................... 31
TX Return Loss ................................................................................................. 32
RX Return Loss ................................................................................................. 32
Processor ICC_CORE Load Current versus Time........................................................ 42
2-10 VCCUNCORE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series ................................................................ 45
2-11 VCCCORE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series ................................................................ 47
2-12 VCCCACHE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series ................................................................ 48
2-13 VCCUNCORE Static and Transient Tolerance for the
Intel® Itanium® Processor 9500 Series ................................................................ 50
2-14 VCCUNCORE Load Line for the Intel® Itanium® Processor 9500 Series ..................... 50
2-15 VCCCORE Load Line for the Intel® Itanium® Processor 9500 Series ......................... 51
2-16 VR Sense Point (Representation)......................................................................... 57
2-17 Supported Power-up Voltage Sequence Timing Requirements for the
Intel® Itanium® Processor 9300 Series............................................................... 66
2-18 Supported Power-up Sequence Timing Requirements for
Intel® Itanium® Processor 9500 Series............................................................... 67
2-19 Supported Power-down Voltage Sequence Timing Requirements.............................. 69
2-20 RESET_N and SKITID Timing for Warm and Cold Resets ......................................... 70
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
Processor Package Assembly Sketch .................................................................. 119
Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 1 of 4)................. 121
Intel® Itanium® Processor 9300 Series Processor Package Drawing (Sheet 2 of 4)... 122
Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 3 of 4)................. 123
Intel® Itanium® Processor 9300 Series Package Drawing (Sheet 4 of 4)................. 124
Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 1 of 4)................ 125
Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 2 of 4)................. 126
Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 3 of 4)................. 127
Intel® Itanium® Processor 9500 Series Package Drawing (Sheet 4 of 4)................. 128
4-10 Processor Marking Zones.................................................................................. 131
5-1
5-2
6-1
Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series’ Thermal States ....................................... 134
Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series Package Thermocouple Location................. 140
Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series Package................................................. 151
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
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170
Intel Itanium Processor 9300 Series and 9500 Series Datasheet
1-1
Intel® Itanium® Processor 9300 Series and
Intel® Itanium® Processor 9500 Series Feature Comparison ................................... 19
Signals with RTT ............................................................................................... 24
Signal Groups................................................................................................... 24
Intel® QuickPath Interconnect/Intel® Scalable Memory
2-1
2-2
2-3
‘Interconnect Reference Clock Specifications ......................................................... 26
Intel® Itanium® Processor 9300 Series Clock Frequency Table ................................ 29
Intel® Itanium® Processor 9300 Series Transmitter Parameter Values for Intel®
QuickPath Interconnect and Intel SMI Channels @ 4.8 GT/s.................................... 29
Intel® Itanium® Processor 9300 Series Receiver Parameter
2-4
2-5
2-6
Values for Intel® QuickPath Interconnect and Intel® SMI Channels @ 4.8 GT ............ 30
Intel® Itanium® Processor 9500 Series Clock Frequency Table ................................ 33
Intel® Itanium® Processor 9500 Series Link Speed Independent Specifications.......... 33
Intel® Itanium® Processor 9500 Series Transmitter and
2-7
2-8
2-9
Receiver Parameter Values for Intel® QPI Channel at 4.8 GT/s ................................ 34
2-10 Intel® Itanium® Processor 9500 Series Transmitter and
Receiver Parameter Values for Intel® QPI at 6.4 GT/s ............................................ 35
2-11 Intel® Itanium® Processor 9500 Series Transmitter and
Receiver Parameter Values for Intel® SMI at 6.4 GT/s and lower ............................. 37
2-12 PLL Specification for TX and RX........................................................................... 38
2-13 Intel® Itanium® Processor 9300 Series Absolute Maximum Ratings.......................... 39
2-14 Intel® Itanium® Processor 9500 Series Processor Absolute Maximum Ratings ........... 39
2-15 FMB Voltage Specifications for the Intel® Itanium® Processor 9300 Series................ 40
2-16 FMB 130W Current Specifications for the Intel® Itanium® Processor 9300 Series....... 41
2-17 FMB 155W/185W Current Specifications for the
Intel® Itanium® Processor 9300 Series ................................................................ 42
2-18 FMB Voltage Specifications for the Intel® Itanium® Processor 9500 Series................ 43
2-19 FMB 170W and 130W Current Specifications for the
Intel® Itanium® Processor 9500 Series ................................................................ 44
2-20 VCCUNCORE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series ................................................................ 45
2-21 VCCCORE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series ................................................................ 46
2-22 VCCCACHE Static and Transient Tolerance for
Intel® Itanium® Processor 9300 Series ................................................................ 48
2-23 VCCUNCORE Static and Transient Tolerance for the
Intel® Itanium® Processor 9500 Series ................................................................ 49
2-24 VCCCORE Static and Transient Tolerance for the
Intel® Itanium® Processor 9500 Series ................................................................ 51
2-25 Overshoot and Undershoot Specifications For Differential
Intel® QuickPath Interconnect and Intel® SMI and Single-Ended Signals
for the Intel® Itanium® Processor 9300 Series...................................................... 52
2-26 Overshoot and Undershoot Specifications For Differential
Intel® QuickPath Interconnect and Intel® SMI and Single-Ended
Signals for the Intel® Itanium® Processor 9500 Series........................................... 53
2-27 Voltage Regulator Signal Group DC Specifications.................................................. 53
2-28 Voltage Regulator Control Group DC Specification.................................................. 54
2-29 TAP and System Management Group DC Specifications........................................... 54
2-30 Error, FLASHROM, Power-Up, Setup, and Thermal Group DC Specifications ............... 54
2-31 VID_VCCCORE[6:0], VID_VCCUNCORE[6:0] and VID_VCCCACHE[5:0] DC
Specifications for the Intel® Itanium® Processor 9300 Series.................................. 55
2-32 SVID Group DC Specifications for the Intel® Itanium® Processor 9500 Series............ 55
2-33 SMBus and Serial Presence Detect (SPD) Bus Signal Group DC Specifications ............ 55
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
171
2-34 Debug Signal Group DC Specifications ..................................................................56
2-35 PIROM Signal Group DC Specifications..................................................................56
2-36 Intel® Itanium® Processor 9300 Series VCCCORE (VID_VCCCORE) and
VCCUNCORE and (VID_VCCUNCORE) Voltage Identification Definition for Ararat ........58
2-37 Intel® Itanium® Processor 9500 Series VCCCORE (VID_VCCCORE)
and VCCUNCORE and (VID_VCCUNCORE) Voltage Identification
Definition for Ararat II........................................................................................59
2-38 Cache (VID_VCCCACHE) Voltage Identification Definition for Ararat..........................63
2-39 Power-up Voltage Sequence Timing Requirements..................................................68
2-40 RESET_N and SKTID Timing................................................................................70
3-1
3-2
3-3
Pin List by Pin Name ..........................................................................................73
Pin List by Pin Number .......................................................................................89
Top-Side J1 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9300 Series) ............................................................105
Top-Side J1 Connector Two-Dimensional Table
3-4
3-5
3-6
3-7
3-8
3-9
(Intel® Itanium® Processor 9500 Series) ............................................................106
Top-Side J2 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9300 Series) ............................................................108
Top-Side J2 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9500 Series) ............................................................110
Top-Side J3 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9300 Series) ............................................................111
Top-Side J3 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9500 Series) ............................................................113
Top-Side J4 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9300 Series) ............................................................114
3-10 Top-Side J4 Connector Two-Dimensional Table
(Intel® Itanium® Processor 9500 Series) ............................................................116
4-1
4-2
4-3
4-4
4-5
5-1
Processor Loading Specifications........................................................................129
Package Handling Guidelines.............................................................................129
Processor Package Insertion Specification ...........................................................130
Package Materials............................................................................................130
1248 FCLGA Package Marking Zones ..................................................................130
Thermal Sensor Accuracy Distribution for the
Intel® Itanium® Processor 9300 Series...............................................................134
Thermal Sensor Accuracy Distribution for the
5-2
Intel® Itanium® Processor 9500 Series .............................................................135
Thermal Specification for the Intel® Itanium® Processor 9300 Series......................139
Thermal Specification for the Intel® Itanium® Processor 9500 Series Processor .......139
Storage Condition Ratings.................................................................................141
Processor Information ROM Data .......................................................................144
Read Byte SMBus Packet ..................................................................................150
Write Byte SMBus Packet..................................................................................150
Offset 78h/79h Definitions ................................................................................156
128 Byte PIROM Checksum Values.....................................................................157
Signal Definitions for the Intel® Itanium® Processor 9300
5-3
5-4
5-5
6-1
6-2
6-3
6-4
6-5
7-1
Series and Intel® Itanium® 9500 Series .............................................................159
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Intel Itanium Processor 9300 Series and 9500 Series Datasheet
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