N80188 [INTEL]
HIGH-INTEGRATION 16-BIT MICROPROCESSORS; 高集成度16位微处理器
| 型号： | N80188 |
| 厂家： | 
INTEL |
| 描述： | HIGH-INTEGRATION 16-BIT MICROPROCESSORS |
| 文件： | 总33页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
80186/80188
HIGH-INTEGRATION 16-BIT MICROPROCESSORS
Y
Y
Integrated Feature Set
Ð Enhanced 8086-2 CPU
Ð Clock Generator
Ð 2 Independent DMA Channels
Ð Programmable Interrupt Controller
Ð 3 Programmable 16-bit Timers
Ð Programmable Memory and
Peripheral Chip-Select Logic
Ð Programmable Wait State Generator
Ð Local Bus Controller
Direct Addressing Capability to 1 Mbyte
of Memory and 64 Kbyte I/O
Y
Completely Object Code Compatible
with All Existing 8086, 8088 Software
Ð 10 New Instruction Types
Y
Y
Numerics Coprocessing Capability
Through 8087 Interface
Available in 68 Pin:
Ð Plastic Leaded Chip Carrier (PLCC)
Ð Ceramic Pin Grid Array (PGA)
Ð Ceramic Leadless Chip Carrier (LCC)
Y
Y
Available in 10 MHz and 8 MHz
Versions
Y
Available in EXPRESS
Ð Standard Temperature with Burn-In
High-Performance Processor
Ð 4 Mbyte/Sec Bus Bandwidth
Ð Extended Temperature Range
a
40 C to 85 C)
@
Interface
8 MHz (80186)
Ð 5 Mbyte/Sec Bus Bandwidth
b
(
§
§
@
Interface
10 MHz (80186)
272430–1
Figure 1. Block Diagram
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1994
COPYRIGHT INTEL CORPORATION, 1995
Order Number: 272430-002
©
1
80186/80188 High-Integration 16-Bit Microprocessors
CONTENTS
PAGE
CONTENTS
PAGE
FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
ABSOLUTE MAXIMUM RATINGS ÀÀÀÀÀÀÀÀ 15
D.C. CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15
A.C. CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16
Introduction ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
CLOCK GENERATOR ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
Oscillator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
READY Synchronization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
RESET Logic ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
EXPLANATION OF THE AC
SYMBOLS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18
WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19
EXPRESS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25
EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26
INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 27
FOOTNOTES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32
REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33
LOCAL BUS CONTROLLER ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9
Memory/Peripheral Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
Local Bus Arbitration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10
Local Bus Controller and Reset ÀÀÀÀÀÀÀÀÀÀÀÀ 10
PERIPHERAL ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀ 10
Chip-Select/Ready Generation Logic ÀÀÀÀÀÀ 10
DMA Channels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
Timers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11
Interrupt Controller ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12
2
2
80186/80188
Contacts Facing Down
272430–2
Figure 2. Ceramic Leadless Chip Carrier (JEDEC Type A)
Pins Facing Up
Pins Facing Down
272430–3
Figure 3. Ceramic Pin Grid Array
NOTE:
Pin names in parentheses apply to the 80188.
3
3
80186/80188
Leads Facing Up
Leads Facing Down
272430–4
Figure 4. Plastic Leaded Chip Carrier
NOTE:
Pin names in parentheses apply to the 80188.
4
4
80186/80188
Table 1. Pin Descriptions
Name and Function
Pin
No.
Symbol
Type
a
SYSTEM POWER: 5 volt power supply.
V
V
9
I
CC
43
26
60
I
System Ground.
SS
RESET
57
O
Reset Output indicates that the CPU is being reset, and can be used as a system
reset. It is active HIGH, synchronized with the processor clock, and lasts an
integer number of clock periods corresponding to the length of the RES signal.
X1
X2
59
58
I
Crystal Inputs X1 and X2 provide external connections for a fundamental mode
parallel resonant crystal for the internal oscillator. Instead of using a crystal, an
external clock may be applied to X1 while minimizing stray capacitance on X2.
The input or oscillator frequency is internally divided by two to generate the
clock signal (CLKOUT).
O
CLKOUT
RES
56
24
O
I
Clock Output provides the system with a 50% duty cycle waveform. All device
pin timings are specified relative to CLKOUT.
An active RES causes the processor to immediately terminate its present
activity, clear the internal logic, and enter a dormant state. This signal may be
asynchronous to the processor clock. The processor begins fetching
instructions approximately 6(/2 clock cycles after RES is returned HIGH. For
proper initialization, V must be within specifications and the clock signal must
CC
be stable for more than 4 clocks with RES held LOW. RES is internally
synchronized. This input is provided with a Schmitt-trigger to facilitate power-on
RES generation via an RC network.
TEST
47
I/O
TEST is examined by the WAIT instruction. If the TEST input is HIGH when
‘‘WAIT’’ execution begins, instruction execution will suspend. TEST will be
resampled until it goes LOW, at which time execution will resume. If interrupts
are enabled while the processor is waiting for TEST, interrupts will be serviced.
During power-up, active RES is required to configure TEST as an input. This pin
is synchronized internally.
TMR IN 0
TMR IN 1
20
21
I
I
Timer Inputs are used either as clock or control signals, depending upon the
programmed timer mode. These inputs are active HIGH (or LOW-to-HIGH
transitions are counted) and internally synchronized.
TMR OUT 0
TMR OUT 1
22
23
O
O
Timer outputs are used to provide single pulse or continous waveform
generation, depending upon the timer mode selected.
DRQ0
DRQ1
18
19
I
I
DMA Request is asserted HIGH by an external device when it is ready for DMA
Channel 0 or 1 to perform a transfer. These signals are level-triggered and
internally synchronized.
NMI
46
I
The Non-Maskable Interrupt input causes a Type 2 interrupt. An NMI transition
from LOW to HIGH is latched and synchronized internally, and initiates the
interrupt at the next instruction boundary. NMI must be asserted for at least one
clock. The Non-Maskable Interrupt cannot be avoided by programming.
INT0
45
44
42
I
Maskable Interrupt Requests can be requested by activating one of these pins.
When configured as inputs, these pins are active HIGH. Interrupt Requests are
synchronized internally. INT2 and INT3 may be configured to provide active-
LOW interrupt-acknowledge output signals. All interrupt inputs may be
configured to be either edge- or level-triggered. To ensure recognition, all
interrupt requests must remain active until the interrupt is acknowledged. When
Slave Mode is selected, the function of these pins changes (see Interrupt
Controller section of this data sheet).
INT1/SELECT
INT2/INTA0
I
I/O
I/O
INT3/INTA1/IRQ 41
NOTE:
Pin names in parentheses apply to the 80188.
5
5
80186/80188
Table 1. Pin Descriptions (Continued)
Pin
Symbol
Type
Name and Function
No.
A19/S6
A18/S5
A17/S4
A16/S3
65
66
67
68
O
O
O
O
Address Bus Outputs (16–19) and Bus Cycle Status (3–6) indicate the four most
significant address bits during T . These signals are active HIGH. During T , T , T ,
W
and T , the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a
4
DMA-initiated bus cycle. During the same T-states, S3, S4, and S5 are always LOW.
The status pins float during bus HOLD or RESET.
1
2
3
AD15 (A15)
AD14 (A14)
AD13 (A13)
AD12 (A12)
1
3
5
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Address/Data Bus signals constitute the time multiplexed memory or I/O address (T )
1
and data (T , T , T , and T ) bus. The bus is active HIGH. A is analogous to BHE for
2
3
W
4
0
the lower byte of the data bus, pins D through D . It is LOW during T when a byte is
1
7
0
to be transferred onto the lower portion of the bus in memory or I/O operations. BHE
does not exist on the 80188, as the data bus is only 8 bits wide.
AD11 (A11) 10
AD10 (A10) 12
AD9 (A9)
AD8 (A8)
AD7
14
16
2
AD6
4
AD5
6
AD4
8
AD3
11
13
15
17
AD2
AD1
AD0
BHE/S7
(S7)
64
O
During T the Bus High Enable signal should be used to determine if data is to be
1
enabled onto the most significant half of the data bus; pins D –D . BHE is LOW
15
8
during T for read, write, and interrupt acknowledge cycles when a byte is to be
1
transferred on the higher half of the bus. The S status information is available during
7
T , T , and T . S is logically equivalent to BHE. BHE/S7 floats during HOLD. On the
2
3
4
80188, S7 is high during normal operation.
7
BHE and A0 Encodings (80186 Only)
Function
BHE
A0
Value Value
0
0
1
1
0
1
0
1
Word Transfer
Byte Transfer on upper half of data bus (D15–D8)
Byte Transfer on lower half of data bus (D –D )
7
0
Reserved
ALE/QS0
WR/QS1
61
63
O
O
Address Latch Enable/Queue Status 0 is provided by the processor to latch the
address. ALE is active HIGH. Addresses are guaranteed to be valid on the trailing
edge of ALE. The ALE rising edge is generated off the rising edge of the CLKOUT
immediately preceding T of the associated bus cycle, effectively one-half clock cycle
1
earlier than in the 8086. The trailing edge is generated off the CLKOUT rising edge in
T
as in the 8086. Note that ALE is never floated.
1
Write Strobe/Queue Status 1 indicates that the data on the bus is to be written into a
memory or an I/O device. WR is active for T , T , and T of any write cycle. It is active
2
3
W
LOW, and floats during HOLD. When the processor is in queue status mode, the ALE/
QS0 and WR/QS1 pins provide information about processor/instruction queue
interaction.
QS1
QS0
Queue Operation
0
0
1
1
0
1
1
0
No queue operation
First opcode byte fetched from the queue
Subsequent byte fetched from the queue
Empty the queue
NOTE:
Pin names in parentheses apply to the 80188.
6
6
80186/80188
Table 1. Pin Descriptions (Continued)
Name and Function
Pin
No.
Symbol
Type
RD/QSMD
62
I/O
Read Strobe is an active LOW signal which indicates that the processor is
performing a memory or I/O read cycle. It is guaranteed not to go LOW
before the A/D bus is floated. An internal pull-up ensures that RD is HIGH
during RESET. Following RESET the pin is sampled to determine whether
the processor is to provide ALE, RD, and WR, or queue status information.
To enable Queue Status Mode, RD must be connected to GND. RD will
float during bus HOLD.
ARDY
SRDY
55
49
I
I
Asynchronous Ready informs the processor that the addressed memory
space or I/O device will complete a data transfer. The ARDY pin accepts a
rising edge that is asynchronous to CLKOUT, and is active HIGH. The
falling edge of ARDY must be synchronized to the processor clock.
Connecting ARDY HIGH will always assert the ready condition to the CPU.
If this line is unused, it should be tied LOW to yield control to the SRDY pin.
Synchronous Ready informs the processor that the addressed memory
space or I/O device will complete a data transfer. The SRDY pin accepts an
active-HIGH input synchronized to CLKOUT. The use of SRDY allows a
relaxed system timing over ARDY. This is accomplished by elimination of
the one-half clock cycle required to internally synchronize the ARDY input
signal. Connecting SRDY high will always assert the ready condition to the
CPU. If this line is unused, it should be tied LOW to yield control to the
ARDY pin.
LOCK
48
O
LOCK output indicates that other system bus masters are not to gain
control of the system bus while LOCK is active LOW. The LOCK signal is
requested by the LOCK prefix instruction and is activated at the beginning
of the first data cycle associated with the instruction following the LOCK
prefix. It remains active until the completion of that instruction. No
instruction prefetching will occur while LOCK is asserted. When executing
more than one LOCK instruction, always make sure there are 6 bytes of
code between the end of the first LOCK instruction and the start of the
second LOCK instruction. LOCK is driven HIGH for one clock during RESET
and then floated.
S0
S1
S2
52
53
54
O
O
O
Bus cycle status S0–S2 are encoded to provide bus-transaction
information:
Bus Cycle Status Information
S2
S1
S0
Bus Cycle Initiated
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
Write I/O
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)
The status pins float during HOLD.
S2 may be used as a logical M/IO indicator, and S1 as a DT/R indicator.
NOTE:
Pin names in parentheses apply to the 80188.
7
7
80186/80188
Table 1. Pin Descriptions (Continued)
Name and Function
Pin
Symbol
Type
No.
HOLD
HLDA
50
51
I
HOLD indicates that another bus master is requesting the local bus. The
HOLD input is active HIGH. HOLD may be asynchronous with respect to the
processor clock. The processor will issue a HLDA (HIGH) in response to a
O
HOLD request at the end of T or T . Simultaneous with the issuance of
i
4
HLDA, the processor will float the local bus and control lines. After HOLD is
detected as being LOW, the processor will lower HLDA. When the processor
needs to run another bus cycle, it will again drive the local bus and control
lines.
UCS
LCS
34
33
O
O
Upper Memory Chip Select is an active LOW output whenever a memory
reference is made to the defined upper portion (1K–256K block) of memory.
This line is not floated during bus HOLD. The address range activating UCS is
software programmable.
Lower Memory Chip Select is active LOW whenever a memory reference is
made to the defined lower portion (1K–256K) of memory. This line is not
floated during bus HOLD. The address range activating LCS is software
programmable.
MCS0
MCS1
MCS2
MCS3
38
37
36
35
O
O
O
O
Mid-Range Memory Chip Select signals are active LOW when a memory
reference is made to the defined mid-range portion of memory (8K–512K).
These lines are not floated during bus HOLD. The address ranges activating
MCS0–3 are software programmable.
PCS0
PCS1
PCS2
PCS3
PCS4
25
27
28
29
30
O
O
O
O
O
Peripheral Chip Select signals 0–4 are active LOW when a reference is made
to the defined peripheral area (64 Kbyte I/O space). These lines are not
floated during bus HOLD. The address ranges activating PCS0–4 are
software programmable.
PCS5/A1
31
O
Peripheral Chip Select 5 or Latched A1 may be programmed to provide a
sixth peripheral chip select, or to provide an internally latched A1 signal. The
address range activating PCS5 is software-programmable. PCS5/A1 does
not float during bus HOLD. When programmed to provide latched A1, this pin
will retain the previously latched value during HOLD.
PCS6/A2
32
O
Peripheral Chip Select 6 or Latched A2 may be programmed to provide a
seventh peripheral chip select, or to provide an internally latched A2 signal.
The address range activating PCS6 is software programmable. PCS6/A2
does not float during bus HOLD. When programmed to provide latched A2,
this pin will retain the previously latched value during HOLD.
DT/R
DEN
40
39
O
O
Data Transmit/Receive controls the direction of data flow through an
external data bus transceiver. When LOW, data is transferred to the
processsor. When HIGH, the processor places write data on the data bus.
Data Enable is provided as a data bus transceiver output enable. DEN is
active LOW during each memory and I/O access. DEN is HIGH whenever
DT/R changes state. During RESET, DEN is driven HIGH for one clock, then
floated. DEN also floats during HOLD.
NOTE:
Pin names in parentheses apply to the 80188.
8
8
80186/80188
Intel recommends the following values for crystal se-
lection parameters:
FUNCTIONAL DESCRIPTION
Introduction
Temperature Range:
ESR (Equivalent Series Resistance):
0 to 70 C
§
30X max
7.0 pf max
C
C
(Shunt Capacitance of Crystal):
(Load Capacitance):
0
The following Functional Description describes the
base architecture of the 80186. The 80186 is a very
high integration 16-bit microprocessor. It combines
15–20 of the most common microprocessor system
components onto one chip while providing twice the
performance of the standard 8086. The 80186 is ob-
ject code compatible with the 8086/8088 microproc-
essors and adds 10 new instruction types to the
8086/8088 instruction set.
g
20 pf 2 pf
1 mW max
1
Drive Level:
Clock Generator
The clock generator provides the 50% duty cycle
processor clock for the processor. It does this by
dividing the oscillator output by 2 forming the sym-
metrical clock. If an external oscillator is used, the
state of the clock generator will change on the fall-
ing edge of the oscillator signal. The CLKOUT pin
provides the processor clock signal for use outside
the device. This may be used to drive other system
components. All timings are referenced to the output
clock.
For more detailed information on the architecture,
please refer to the 80C186XL/80C188XL User’s
Manual. The 80186 and the 80186XL devices are
functionally and register compatible.
CLOCK GENERATOR
The processor provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divide-
by-two counter, synchronous and asynchronous
ready inputs, and reset circuitry.
READY Synchronization
The processor provides both synchronous and asyn-
chronous ready inputs. In addition, the processor, as
part of the integrated chip-select logic, has the capa-
bility to program WAIT states for memory and
peripheral blocks.
Oscillator
The oscillator circuit is designed to be used with a
parallel resonant fundamental mode crystal. This is
used as the time base for the processor. The crystal
frequency selected will be double the CPU clock fre-
quency. Use of an LC or RC circuit is not recom-
mended with this oscillator. If an external oscillator is
used, it can be connected directly to the input pin X1
in lieu of a crystal. The output of the oscillator is not
directly available outside the processor. The recom-
mended crystal configuration is shown in Figure 5.
RESET Logic
The processor provides both a RES input pin and a
synchronized RESET output pin for use with other
system components. The RES input pin is provided
with hysteresis in order to facilitate power-on Reset
generation via an RC network. RESET output is
guaranteed to remain active for at least five clocks
given a RES input of at least six clocks.
LOCAL BUS CONTROLLER
The processor provides a local bus controller to
generate the local bus control signals. In addition, it
employs a HOLD/HLDA protocol for relinquishing
the local bus to other bus masters. It also provides
outputs that can be used to enable external buffers
and to direct the flow of data on and off the local
bus.
272430–5
x
80186-10 (10 MHz) 20
80186
(8 MHz) 16
Figure 5. Recommended
Crystal Configuration
9
9
80186/80188
either memory or I/O space. Internal logic will recog-
nize control block addresses and respond to bus cy-
cles. During bus cycles to internal registers, the bus
controller will signal the operation externally (i.e., the
RD, WR, status, address, data, etc., lines will be driv-
Memory/Peripheral Control
The processor provides ALE, RD, and WR bus con-
trol signals. The RD and WR signals are used to
strobe data from memory or I/O to the processor or
to strobe data from the processor to memory or I/O.
The ALE line provides a strobe to latch the address
when it is valid. The local bus controller does not
provide a memory/I/O signal. If this is required, use
the S2 signal (which will require external latching),
make the memory and I/O spaces nonoverlapping,
or use only the integrated chip-select circuitry.
en as in a normal bus cycle), but D
(D
7–0
),
15–0
SRDY, and ARDY will be ignored. The base address
of the control block must be on an even 256-byte
boundary (i.e., the lower 8 bits of the base address
are all zeros).
The control block base address is programmed by a
16-bit relocation register contained within the control
block at offset FEH from the base address of the
control block. It provides the upper 12 bits of the
base address of the control block.
Local Bus Arbitration
The processor uses a HOLD/HLDA system of local
bus exchange. This provides an asynchronous bus
exchange mechanism. This means multiple masters
utilizing the same bus can operate at separate clock
In addition to providing relocation information for the
control block, the relocation register contains bits
which place the interrupt controller into Slave Mode,
and cause the CPU to interrupt upon encountering
ESC instructions.
frequencies. The processor provides
a single
HOLD/HLDA pair through which all other bus mas-
ters may gain control of the local bus. External cir-
cuitry must arbitrate which external device will gain
control of the bus when there is more than one alter-
nate local bus master. When the processor relin-
quishes control of the local bus, it floats DEN, RD,
WR, S0–S2, LOCK, AD0–AD15 (AD0–AD7),
A16–A19 (A8–A19), BHE (S7), and DT/R to allow
another master to drive these lines directly.
Chip-Select/Ready Generation Logic
The processor contains logic which provides
programmable chip-select generation for both mem-
ories and peripherals. In addition, it can be pro-
grammed to provide READY (or WAIT state) genera-
tion. It can also provide latched address bits A1 and
A2. The chip-select lines are active for all memory
and I/O cycles in their programmed areas, whether
they be generated by the CPU or by the integrated
DMA unit.
Local Bus Controller and Reset
During RESET the local bus controller will perform
the following action:
Drive DEN, RD, and WR HIGH for one clock cy-
cle, then float.
#
MEMORY CHIP SELECTS
The processor provides 6 memory chip select out-
puts for 3 address areas; upper memory, lower
memory, and midrange memory. One each is provid-
ed for upper memory and lower memory, while four
are provided for midrange memory.
NOTE:
RD is also provided with an internal pull-up de-
vice to prevent the processor from inadvertently
entering Queue Status Mode during RESET.
Drive S0–S2 to the inactive state (all HIGH) and
then float.
#
UPPER MEMORY CS
Drive LOCK HIGH and then float.
#
The processor provides a chip select, called UCS,
for the top of memory. The top of memory is usually
used as the system memory because after reset the
processor begins executing at memory location
FFFF0H.
Float AD0–15 (AD0–AD7), A16–19 (A8–A19),
BHE (S7), DT/R.
#
Drive ALE LOW (ALE is never floated).
#
#
Drive HLDA LOW.
LOWER MEMORY CS
PERIPHERAL ARCHITECTURE
The processor provides a chip select for low memo-
ry called LCS. The bottom of memory contains the
interrupt vector table, starting at location 00000H.
All of the integrated peripherals are controlled by
16-bit registers contained within an internal 256-byte
control block. The control block may be mapped into
10
10
80186/80188
The lower limit of memory defined by this chip select
is always 0H, while the upper limit is programmable.
By programming the upper limit, the size of the
memory block is defined.
Upon leaving RESET, the UCS line will be pro-
grammed to provide chip selects to a 1K block
with the accompanying READY control bits set at
011 to insert 3 wait states in conjunction with ex-
ternal READY (i.e., UMCS resets to FFFBH).
#
#
No other chip select or READY control registers
have any predefined values after RESET. They
will not become active until the CPU accesses
their control registers. Both the PACS and MPCS
registers must be accessed before the PCS lines
will become active.
MID-RANGE MEMORY CS
The processor provides four MCS lines which are
active within a user-locatable memory block. This
block can be located within the 1-Mbyte memory ad-
dress space exclusive of the areas defined by UCS
and LCS. Both the base address and size of this
memory block are programmable.
DMA Channels
PERIPHERAL CHIP SELECTS
The DMA controller provides two independent DMA
channels. Data transfers can occur between memo-
ry and I/O spaces (e.g., Memory to I/O) or within the
same space (e.g., Memory to Memory or I/O to I/O).
Data can be transferred either in bytes or in words
(80186 only) to or from even or odd addresses.
Each DMA channel maintains both a 20-bit source
and destination pointer which can be optionally in-
cremented or decremented after each data transfer
(by one or two depending on byte or word transfers).
Each data transfer consumes 2 bus cycles (a mini-
mum of 8 clocks), one cycle to fetch data and the
other to store data. This provides a maximum data
transfer rate of 1.25 Mword/sec or 2.5 Mbytes/sec
at 10 MHz (half of this rate for the 80188).
The processor can generate chip selects for up to
seven peripheral devices. These chip selects are ac-
tive for seven contiguous blocks of 128 bytes above
a programmable base address. The base address
may be located in either memory or I/O space. Sev-
en CS lines called PCS0–6 are generated by the
processor. PCS5 and PCS6 can also be pro-
grammed to provide latched address bits A1 and A2.
If so programmed, they cannot be used as peripher-
al selects. These outputs can be connected directly
to the A0 and A1 pins used for selecting internal
registers of 8-bit peripheral chips.
READY GENERATION LOGIC
DMA CHANNELS AND RESET
The processor can generate a READY signal inter-
nally for each of the memory or peripheral CS lines.
The number of WAIT states to be inserted for each
peripheral or memory is programmable to provide
0–3 wait states for all accesses to the area for
which the chip select is active. In addition, the proc-
essor may be programmed to either ignore external
READY for each chip-select range individually or to
factor external READY with the integrated ready
generator.
Upon RESET, the DMA channels will perform the
following actions:
The Start/Stop bit for each channel will be reset
to STOP.
#
Any transfer in progress is aborted.
#
Timers
The processor provides three internal 16-bit pro-
grammable timers. Two of these are highly flexible
and are connected to four external pins (2 per timer).
They can be used to count external events, time ex-
ternal events, generate nonrepetitive waveforms,
etc. The third timer is not connected to any external
pins, and is useful for real-time coding and time de-
lay applications. In addition, the third timer can be
used as a prescaler to the other two, or as a DMA
request source.
CHIP SELECT/READY LOGIC AND RESET
Upon RESET, the Chip-Select/Ready Logic will per-
form the following actions:
All chip-select outputs will be driven HIGH.
#
11
11
80186/80188
TIMERS AND RESET
INTERRUPT CONTROLLER AND RESET
Upon RESET, the Timers will perform the following
actions:
Upon RESET, the interrupt controller will perform
the following actions:
All EN (Enable) bits are reset preventing timer
counting.
All SFNM bits reset to 0, implying Fully Nested
Mode.
#
#
For Timers 0 and 1, the RIU bits are reset to zero
and the ALT bits are set to one. This results in the
Timer Out pins going high.
All PR bits in the various control registers set to 1.
This places all sources at lowest priority (level
111).
#
#
All LTM bits reset to 0, resulting in edge-sense
mode.
#
Interrupt Controller
All Interrupt Service bits reset to 0.
#
The processor can receive interrupts from a number
of sources, both internal and external. The internal
interrupt controller serves to merge these requests
on a priority basis, for individual service by the CPU.
All Interrupt Request bits reset to 0.
#
#
#
All MSK (Interrupt Mask) bits set to 1 (mask).
All C (Cascade) bits reset to 0 (non-Cascade).
All PRM (Priority Mask) bits set to 1, implying no
levels masked.
#
Internal interrupt sources (Timers and DMA chan-
nels) can be disabled by their own control registers
or by mask bits within the interrupt controller. The
interrupt controller has its own control register that
sets the mode of operation for the controller.
Initialized to Master Mode.
#
12
12
80186/80188
272430–6
NOTE:
Pin names in parenthesis apply to 80188.
(1) BHE does not exist on the 80188, this is only required for a 16-bit data bus.
Figure 6. Typical 80186/80188 Computer
13
13
80186/80188
272430–7
NOTE:
Pin names in parentheses apply to 80188.
(1) BHE does not exist on the 80188, this is only required for a 16-bit data bus.
Figure 7. Typical 80186/80188 Multi-Master Bus Interface
14
14
80186/80188
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Ambient Temperature under Bias ÀÀÀÀÀÀ0 C to 70 C
§
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
b
a
§
§
Voltage on any Pin with
Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1.0V to 7V
b
a
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3W
e
Applicable to 8 MHz and 10 MHz devices.
a
0 C to 70 C, V
e
CC
g
5V 10%)
D.C. CHARACTERISTICS (T
§
§
A
Symbol
Parameter
Min
Max
Units
Test Conditions
b
a
0.8
V
V
Input Low Voltage
0.5
V
V
IL
a
Input High Voltage
(All except X1 and (RES)
2.0
V
V
0.5
IH
CC
a
V
V
Input High Voltage (RES)
Output Low Voltage
3.0
2.4
0.5
V
V
IH1
OL
CC
e
e
0.45
I
I
2.5 mA for S0–S2
2.0 mA for all other Outputs
a
a
e b
400 mA
V
I
Output High Voltage
Power Supply Current
V
mA
mA
mA
mA
mA
V
I
OH
oa
e b
40 C
600*
550
415
T
T
T
§
CC
A
A
A
e
0 C
§
e a
70 C
§
k
k
g
g
I
I
Input Leakage Current
Output Leakage Current
Clock Output Low
10
10
0V
V
V
CC
LI
LO
IN
k
k
0.45V
V
V
CC
OUT
e
a
V
V
V
V
0.6
I
I
4.0 mA
e b
200 mA
CLO
CHO
CLI
Clock Output High
4.0
V
oa
b
Clock Input Low Voltage
Clock Input High Voltage
Input Capacitance
0.5
0.6
V
a
3.9
V
1.0
V
CHI
CC
C
C
10
20
pF
pF
IN
IO
I/O Capacitance
*For extended temperature parts only.
15
15
80186/80188
e
a
e
5V 10%)
CC
g
A.C. CHARACTERISTICS (T
0 C to 70 C, V
§
§
A
Timing Requirements All Timings Measured At 1.5V Unless Otherwise Noted.
8 MHz
Min
10 MHz
Min
Test
Symbol
Parameter
Units
Conditions
Max
Max
T
Data in Setup (A/D)
Data in Hold (A/D)
20
10
20
15
8
ns
ns
ns
DVCL
T
T
CLDX
Asynchronous Ready
(ARDY) Active Setup
(1)
Time
15
ARYHCH
T
T
T
ARDY Inactive Setup Time
ARDY Hold Time
35
15
15
25
15
15
ns
ns
ns
ARYLCL
CLARX
Asynchronous Ready
Inactive Hold Time
ARYCHL
T
T
Synchronous Ready (SRDY)
(2)
Transition Setup Time
20
15
20
15
ns
ns
SRYCL
CLSRY
SRDY Transition Hold
(2)
Time
(1)
T
T
HOLD Setup
25
25
20
25
ns
ns
HVCL
INTR, NMI, TEST, TIM IN,
(1)
Setup
INVCH
(1)
T
DRQ0, DRQ1, Setup
25
20
ns
INVCL
Master Interface Timing Responses
e
L
T
CLAV
T
CLAX
T
CLAZ
T
CHCZ
T
CHCV
Address Valid Delay
Address Hold
5
55
5
44
ns
ns
ns
ns
ns
C
20 pF–200 pF
all Outputs
(Except T
10
10
@
)
CLTMV
8 MHz and 10 MHz
Address Float Delay
Command Lines Float Delay
T
35
45
55
T
30
40
45
CLAX
CLAX
Command Lines Valid Delay
(after Float)
b
b
b
b
T
T
T
T
ALE Width
T
35
T
30
ns
ns
ns
ns
LHLL
CHLH
CHLL
LLAX
CLCL
CLCL
ALE Active Delay
ALE Inactive Delay
35
35
30
30
Address Hold from ALE
Inactive
T
CHCL
25
T
T
20
CHCL
T
T
T
T
T
T
T
Data Valid Delay
10
10
44
10
10
40
ns
ns
ns
ns
ns
ns
ns
CLDV
Data Hold Time
CLDOX
WHDX
CVCTV
CHCTV
CVCTX
CVDEX
b
b
34
Data Hold after WR
Control Active Delay 1
Control Active Delay 2
Control Inactive Delay
T
40
CLCL
5
CLCL
5
50
55
55
70
40
44
44
56
10
5
10
5
DEN Inactive Delay
(Non-Write Cycle)
10
10
1. To guarantee recognition at next clock.
2. To guarantee proper operation.
16
16
80186/80188
e
Master Interface Timing Responses (Continued)
a
e
CC
g
5V 10%) (Continued)
A.C. CHARACTERISTICS (T
0 C to 70 C, V
§
§
A
8 MHz
Min
10 MHz
Test
Symbol
Parameter
Units
Conditions
Max
Min
0
Max
T
Address Float to RD Active
RD Active Delay
0
ns
ns
ns
ns
AZRL
CLRL
CLRH
RHAV
T
T
T
10
10
70
55
10
10
56
44
RD Inactive Delay
b
b
40
RD Inactive to Address
Active
T
40
T
CLCL
CLCL
T
T
T
T
T
T
T
HLDA Valid Delay
RD Width
5
50
5
40
ns
ns
ns
ns
ns
ns
ns
CLHAV
RLRH
WLWH
AVLL
b
b
2T
2T
50
40
25
2T
2T
46
34
19
CLCL
CLCL
CLCL
b
b
WR Width
CLCL
b
b
CLCH
Address Valid to ALE Low
Status Active Delay
Status Inactive Delay
Timer Output Delay
T
T
CLCH
10
10
55
65
60
10
10
45
50
48
CHSV
CLSH
100 pF max
@
CLTMV
8 & 10 MHz
T
T
T
T
T
Reset Delay
60
35
48
28
ns
ns
ns
ns
ns
CLRO
CHQSV
CHDX
AVCH
CLLV
Queue Status Delay
Status Hold Time
10
10
5
10
10
5
Address Valid to Clock High
LOCK Valid/Invalid Delay
65
66
60
45
Chip-Select Timing Responses
T
T
Chip-Select Active Delay
ns
ns
CLCSV
CXCSX
Chip-Select Hold from
Command Inactive
35
5
35
5
T
Chip-Select Inactive Delay
35
32
ns
CHCSX
CLKIN Requirements
T
T
T
T
T
CLKIN Period
62.5
250
10
50
250
10
ns
ns
ns
ns
ns
CKIN
CLKIN Fall Time
CLKIN Rise Time
CLKIN Low Time
CLKIN High Time
3.5 to 1.0V
1.0 to 3.5V
1.5V
CKHL
CKLH
CLCK
CHCK
10
10
25
25
20
20
1.5V
CLKOUT Timing (200 pF load)
T
T
T
T
T
T
CLKIN to CLKOUT Skew
CLKOUT Period
50
25
ns
ns
ns
ns
ns
ns
CICO
125
500
100
500
CLCL
b
b
CLKOUT Low Time
CLKOUT High Time
CLKOUT Rise Time
CLKOUT Fall Time
(/2 T
(/2 T
7.5
(/2 T
(/2 T
6.0
6.0
1.5V
CLCH
CLCL
CLCL
CLCL
CLCL
b
b
7.5
1.5V
CHCL
15
15
12
12
1.0 to 3.5V
3.5 to 1.0V
CH1CH2
CL2CL1
17
17
80186/80188
IN:
L:
O:
Input (DRQ0, TIM0, . . . )
Logic Level Low or ALE
Output
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has from 5 to 7 characters. The
first character is always a ‘‘T’’ (stands for time). The
other characters, depending on their positions,
stand for the name of a signal or the logical status of
that signal. The following is a list of all the charac-
ters and what they stand for.
QS: Queue Status (QS1, QS2)
R:
S:
RD signal, RESET signal
Status (S0, S1, S2)
SRY: Synchronous Ready Input
V:
W:
X:
Z:
Valid
WR Signal
No Longer a Valid Logic Level
Float
A:
ARY: Asynchronous Ready Input
C: Clock Output
Address
CK: Clock Input
CS: Chip Select
Examples:
T
T
T
Ð Time from Clock low to Address valid
Ð Time from Clock high to ALE high
Ð Time from Clock low to Chip Select valid
CT: Control (DT/R, DEN, . . . )
Data Input
CLAV
D:
DE: DEN
CHLH
CLCSV
H:
Logic Level High
18
18
80186/80188
WAVEFORMS
MAJOR CYCLE TIMING
272430–8
NOTE:
Pin names in parentheses apply to the 80188.
19
19
80186/80188
WAVEFORMS (Continued)
MAJOR CYCLE TIMING (Continued)
NOTES:
1. INTA occurs one clock later in slave mode.
272430–9
2. Status inactive just prior to T .
4
3. If latched A1 and A2 are selected instead of PCS5 and PCS6, only T
4. Pin names in parentheses apply to the 80188.
is applicable.
CLCSV
20
20
80186/80188
WAVEFORMS (Continued)
272430–10
272430–11
272430–12
21
21
80186/80188
WAVEFORMS (Continued)
272430–13
272430–14
22
22
80186/80188
WAVEFORMS (Continued)
READY TIMING
272430–15
23
23
80186/80188
272430–16
NOTE:
Pin names in parentheses apply to the 80188.
24
24
80186/80188
WAVEFORMS (Continued)
272430–17
Package types and EXPRESS versions are identified
by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 2. All A.C. and D.C. speci-
fications not mentioned in this section are the same
for both commercial and EXPRESS parts.
EXPRESS
The Intel EXPRESS system offers enhancements to
the operational specifications of the microprocessor.
EXPRESS products are designed to meet the needs
of those applications whose operating requirements
exceed commercial standards.
Table 2. Prefix Identification
Package
Type
Temperature
Range
The EXPRESS program includes the commercial
standard temperature range with burn-in and an ex-
tended temperature range without burn-in.
Prefix
Burn-In
A
N
PGA
PLCC
LCC
Commercial
Commercial
Commercial
Extended
No
No
With the commercial standard temperature range
operational characteristics are guaranteed over the
R
No
a
tended temperature range option, operational char-
temperature range of 0 C to
70 C. With the ex-
§
§
TA
QA
QR
PGA
PGA
LCC
No
b
acteristics are guaranteed over the range of 40 C
§
Commercial
Commercial
Yes
Yes
a
to 85 C.
§
The optional burn-in is dynamic, for a minimum time
a
e
following guidelines in MIL-STD-883, Method 1015.
NOTE:
Not all package/temperature range/speed combinations
are available.
g
5.5V 0.25V,
of 160 hours at 125 C with V
§
CC
25
25
80186/80188
All instructions which involve memory accesses can
also require one or two additional clocks above the
minimum timings shown due to the asynchronous
handshake between the bus interface unit (BIU) and
execution unit.
EXECUTION TIMINGS
A determination of program execution timing must
consider the bus cycles necessary to prefetch in-
structions as well as the number of execution unit
cycles necessary to execute instructions. The fol-
lowing instruction timings represent the minimum ex-
ecution time in clock cycles for each instruction. The
timings given are based on the following assump-
tions:
All jumps and calls include the time required to fetch
the opcode of the next instruction at the destination
address.
The 80186 has sufficient bus performance to ensure
that an adequate number of prefetched bytes will
reside in the queue (6 bytes) most of the time.
Therefore, actual program execution time will not be
substantially greater than that derived from adding
the instruction timings shown.
The opcode, along with any data or displacement
#
required for execution of a particular instruction,
has been prefetched and resides in the queue at
the time it is needed.
No wait states or bus HOLDS occur.
#
All word-data is located on even-address bound-
aries.
#
The 80188 is noticeably limited in its performance
relative to the execution unit. A sufficient number of
prefetched bytes may not reside in the prefetch
queue (4 bytes) much of the time. Therefore, actual
program execution time may be substantially greater
than that derived from adding the instruction timings
shown.
26
26
80186/80188
INSTRUCTION SET SUMMARY
80186
Clock
Cycles
80188
Function
Format
Clock
Comments
Cycles
DATA TRANSFER
e
MOV
Move:
Register to Register/Memory
Register/memory to register
Immediate to register/memory
Immediate to register
1 0 0 0 1 0 0 w
1 0 0 0 1 0 1 w
1 1 0 0 0 1 1 w
1 0 1 1 w reg
1 0 1 0 0 0 0 w
1 0 1 0 0 0 1 w
1 0 0 0 1 1 1 0
1 0 0 0 1 1 0 0
mod reg r/m
mod reg r/m
mod 000 r/m
data
2/12
2/9
12/13
3/4
8
2/12*
2/9*
12/13
3/4
e
data
data if w
1
8/16-bit
8/16-bit
e
data if w
1
Memory to accumulator
addr-low
addr-high
addr-high
8*
Accumulator to memory
addr-low
9
9*
Register/memory to segment register
Segment register to register/memory
mod 0 reg r/m
mod 0 reg r/m
2/9
2/11
2/13
2/15
e
PUSH
Push:
Memory
Register
1 1 1 1 1 1 1 1
0 1 0 1 0 reg
0 0 0 reg 1 1 0
0 1 1 0 1 0 s 0
mod 1 1 0 r/m
16
10
9
20
14
13
14
Segment register
Immediate
e
data
data if s
0
10
e
PUSHA
Push All
Pop:
Memory
0 1 1 0 0 0 0 0
36
68
e
POP
1 0 0 0 1 1 1 1
0 1 0 1 1 reg
0 0 0 reg 1 1 1
mod 0 0 0 r/m
(regi01)
20
10
8
24
14
12
Register
Segment register
e
e
POPA
Pop All
0 1 1 0 0 0 0 1
51
83
XCHG
Exchange:
Register/memory with register
Register with accumulator
1 0 0 0 0 1 1 w
1 0 0 1 0 reg
mod reg r/m
4/17
3
4/17*
3
e
IN
Input from:
Fixed port
1 1 1 0 0 1 0 w
1 1 1 0 1 1 0 w
port
port
10
8
10*
8*
Variable port
e
OUT
Output to:
Fixed port
1 1 1 0 0 1 1 w
1 1 1 0 1 1 1 w
1 1 0 1 0 1 1 1
1 0 0 0 1 1 0 1
1 1 0 0 0 1 0 1
1 1 0 0 0 1 0 0
1 0 0 1 1 1 1 1
1 0 0 1 1 1 1 0
1 0 0 1 1 1 0 0
1 0 0 1 1 1 0 1
9
7
9*
7*
15
6
Variable port
e
XLAT
Translate byte to AL
11
6
e
LEA
LDS
LES
Load EA to register
Load pointer to DS
Load pointer to ES
mod reg r/m
mod reg r/m
mod reg r/m
(modi11)
(modi11)
18
18
2
26
26
2
e
e
e
LAHF
SAHF
Load AH with flags
Store AH into flags
e
3
3
e
PUSHF
Push flags
9
13
12
e
POPF
Pop flags
8
Shaded areas indicate instructions not available in 8086, 8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.
27
27
80186/80188
INSTRUCTION SET SUMMARY (Continued)
80186
Clock
Cycles
80188
Clock
Cycles
Function
Format
Comments
DATA TRANSFER (Continued)
e
SEGMENT
Segment Override:
CS
0 0 1 0 1 1 1 0
0 0 1 1 0 1 1 0
0 0 1 1 1 1 1 0
0 0 1 0 0 1 1 0
2
2
2
2
2
2
2
2
SS
DS
ES
ARITHMETIC
e
ADD
Add:
Reg/memory with register to either
Immediate to register/memory
Immediate to accumulator
0 0 0 0 0 0 d w
1 0 0 0 0 0 s w
0 0 0 0 0 1 0 w
mod reg r/m
mod 0 0 0 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4
e
data if s w 01
data
e
e
data if w
1
1
8/16-bit
8/16-bit
e
ADC
Add with carry:
Reg/memory with register to either
Immediate to register/memory
Immediate to accumulator
0 0 0 1 0 0 d w
1 0 0 0 0 0 s w
0 0 0 1 0 1 0 w
mod reg r/m
mod 0 1 0 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4
e
data if s w 01
data
data if w
e
INC
Increment:
Register/memory
Register
1 1 1 1 1 1 1 w
0 1 0 0 0 reg
mod 0 0 0 r/m
3/15
3
3/15*
3
e
SUB
Subtract:
Reg/memory and register to either
Immediate from register/memory
Immediate from accumulator
0 0 1 0 1 0 d w
1 0 0 0 0 0 s w
0 0 1 0 1 1 0 w
mod reg r/m
mod 1 0 1 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4
e
data if s w 01
data
e
e
data if w
1
1
8/16-bit
8/16-bit
e
SBB
Subtract with borrow:
Reg/memory and register to either
Immediate from register/memory
Immediate from accumulator
0 0 0 1 1 0 d w
1 0 0 0 0 0 s w
0 0 0 1 1 1 0 w
mod reg r/m
mod 0 1 1 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4
e
data if s w 01
data
data if w
e
DEC
Decrement
Register/memory
Register
1 1 1 1 1 1 1 w
0 1 0 0 1 reg
mod 0 0 1 r/m
3/15
3
3/15*
3
e
CMP
Compare:
Register/memory with register
Register with register/memory
Immediate with register/memory
Immediate with accumulator
0 0 1 1 1 0 1 w
0 0 1 1 1 0 0 w
1 0 0 0 0 0 s w
0 0 1 1 1 1 0 w
1 1 1 1 0 1 1 w
0 0 1 1 0 1 1 1
0 0 1 0 0 1 1 1
0 0 1 1 1 1 1 1
0 0 1 0 1 1 1 1
mod reg r/m
mod reg r/m
mod 1 1 1 r/m
data
3/10
3/10
3/10
3/4
3/10
8
3/10*
3/10*
3/10*
3/4
3/10*
8
e
data if s w 01
data
e
data if w
1
8/16-bit
e
e
e
e
e
NEG
AAA
DAA
AAS
DAS
Change sign register/memory
ASCII adjust for add
mod 0 1 1 r/m
Decimal adjust for add
4
4
ASCII adjust for subtract
Decimal adjust for subtract
7
7
4
4
e
MUL
Multiply (unsigned):
1 1 1 1 0 1 1 w
mod 100 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
26–28
35–37
32–34
41–43
26–28
35–37
32–34
41–43*
Shaded areas indicate instructions not available in 8086, 8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.
28
28
80186/80188
INSTRUCTION SET SUMMARY (Continued)
80186
Clock
Cycles
80188
Function
Format
Clock
Comments
Cycles
ARITHMETIC (Continued)
e
IMUL
Integer multiply (signed):
1 1 1 1 0 1 1 w
mod 1 0 1 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
25–28
34–37
31–34
40–43
25–28
34–37
31–34
40–43*
e
(signed)
e
0
IMUL
Integer Immediate multiply
0 1 1 0 1 0 s 1
1 1 1 1 0 1 1 w
mod reg r/m
data
data if s
22–25/
29–32
22–25/
29–32
e
DIV
Divide (unsigned):
mod 1 1 0 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
29
38
35
44
29
38
35
44*
e
IDIV
Integer divide (signed):
1 1 1 1 0 1 1 w
mod 1 1 1 r/m
Register-Byte
Register-Word
Memory-Byte
Memory-Word
44–52
53–61
50–58
59–67
44–52
53–61
50–58
59–67*
e
e
e
e
AAM
AAD
CBW
CWD
ASCII adjust for multiply
ASCII adjust for divide
Convert byte to word
1 1 0 1 0 1 0 0
1 1 0 1 0 1 0 1
1 0 0 1 1 0 0 0
1 0 0 1 1 0 0 1
0 0 0 0 1 0 1 0
0 0 0 0 1 0 1 0
19
15
2
19
15
2
Convert word to double word
4
4
LOGIC
Shift/Rotate Instructions:
Register/Memory by 1
1 1 0 1 0 0 0 w
1 1 0 1 0 0 1 w
1 1 0 0 0 0 0 w
mod TTT r/m
mod TTT r/m
2/15
2/15
a
a
a
a
a
a
Register/Memory by CL
5
5
n/17
n/17
n
n
5
5
n/17
n/17
n
n
a
a
Register/Memory by Count
mod TTT r/m
count
TTT Instruction
0 0 0
0 0 1
0 1 0
0 1 1
ROL
ROR
RCL
RCR
1 0 0 SHL/SAL
1 0 1
1 1 1
SHR
SAR
e
AND
And:
Reg/memory and register to either
Immediate to register/memory
Immediate to accumulator
0 0 1 0 0 0 d w
1 0 0 0 0 0 0 w
0 0 1 0 0 1 0 w
mod reg r/m
mod 1 0 0 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4
e
e
e
data
data if w
data if w
data if w
1
1
1
e
data if w
1
1
1
8/16-bit
8/16-bit
8/16-bit
e
TEST And function to flags, no result:
Register/memory and register
1 0 0 0 0 1 0 w
1 1 1 1 0 1 1 w
1 0 1 0 1 0 0 w
mod reg r/m
mod 0 0 0 r/m
data
3/10
4/10
3/4
3/10*
4/10*
3/4
Immediate data and register/memory
Immediate data and accumulator
data
e
data if w
e
OR Or:
Reg/memory and register to either
Immediate to register/memory
Immediate to accumulator
0 0 0 0 1 0 d w
1 0 0 0 0 0 0 w
0 0 0 0 1 1 0 w
mod reg r/m
mod 0 0 1 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4
data
e
data if w
Shaded areas indicate instructions not available in 8086, 8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.
29
29
80186/80188
INSTRUCTION SET SUMMARY (Continued)
80186
Clock
Cycles
80188
Clock
Cycles
Function
Format
Comments
LOGIC (Continued)
e
XOR
Exclusive or:
Reg/memory and register to either
Immediate to register/memory
Immediate to accumulator
0 0 1 1 0 0 d w
1 0 0 0 0 0 0 w
0 0 1 1 0 1 0 w
1 1 1 1 0 1 1 w
mod reg r/m
mod 1 1 0 r/m
data
3/10
4/16
3/4
3/10*
4/16*
3/4
e
1
data
data if w
e
data if w
1
8/16-bit
e
NOT
Invert register/memory
mod 0 1 0 r/m
3/10
3/10*
STRING MANIPULATION
e
e
e
e
e
MOVS
CMPS
SCAS
LODS
STOS
Move byte/word
1 0 1 0 0 1 0 w
1 0 1 0 0 1 1 w
1 0 1 0 1 1 1 w
1 0 1 0 1 1 0 w
1 0 1 0 1 0 1 w
0 1 1 0 1 1 0 w
0 1 1 0 1 1 1 w
14
22
15
12
10
14
14
14*
22*
15*
12*
10*
14
Compare byte/word
Scan byte/word
Load byte/wd to AL/AX
Store byte/wd from AL/AX
e
INS
Input byte/wd from DX port
e
OUTS
Output byte/wd to DX port
14
Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)
e
e
e
e
e
a
a
8 8n*
MOVS
CMPS
SCAS
LODS
STOS
Move string
Compare string
Scan string
Load string
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 z
1 1 1 1 0 0 1 z
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 0
1 1 1 1 0 0 1 0
1 0 1 0 0 1 0 w
1 0 1 0 0 1 1 w
1 0 1 0 1 1 1 w
1 0 1 0 1 1 0 w
1 0 1 0 1 0 1 w
0 1 1 0 1 1 0 w
8
8n
a
a
5
5
6
22n
15n
11n
5
5
6
22n*
15n*
11n*
a
a
a
a
a
a
Store string
6
9n
8n
6
9n*
8n*
e
a
a
a
a
INS
OUTS
CONTROL TRANSFER
Input string
8
8
8
8
e
Output string
1 1 1 1 0 0 1 0
0 1 1 0 1 1 1 w
8n
8n*
e
CALL
Call:
Direct within segment
1 1 1 0 1 0 0 0
1 1 1 1 1 1 1 1
disp-low
disp-high
15
19
Register/memory
mod 0 1 0 r/m
13/19
17/27
indirect within segment
Direct intersegment
1 0 0 1 1 0 1 0
1 1 1 1 1 1 1 1
segment offset
segment selector
23
31
i
(mod 11)
Indirect intersegment
mod 0 1 1 r/m
38
54
e
JMP
Unconditional jump:
Short/long
1 1 1 0 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 1 1 1
disp-low
disp-low
14
14
14
14
Direct within segment
disp-high
Register/memory
mod 1 0 0 r/m
11/17
11/21
indirect within segment
Direct intersegment
Indirect intersegment
1 1 1 0 1 0 1 0
segment offset
segment selector
14
26
14
34
i
(mod 11)
1 1 1 1 1 1 1 1
mod 1 0 1 r/m
Shaded areas indicate instructions not available in 8086, 8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.
30
30
80186/80188
INSTRUCTION SET SUMMARY (Continued)
80186
Clock
Cycles
80188
Function
Format
Clock
Comments
Cycles
CONTROL TRANSFER (Continued)
e
RET
Return from CALL:
Within segment
1 1 0 0 0 0 1 1
1 1 0 0 0 0 1 0
1 1 0 0 1 0 1 1
1 1 0 0 1 0 1 0
0 1 1 1 0 1 0 0
0 1 1 1 1 1 0 0
0 1 1 1 1 1 1 0
0 1 1 1 0 0 1 0
0 1 1 1 0 1 1 0
0 1 1 1 1 0 1 0
0 1 1 1 0 0 0 0
0 1 1 1 1 0 0 0
0 1 1 1 0 1 0 1
0 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1
0 1 1 1 0 0 1 1
0 1 1 1 0 1 1 1
0 1 1 1 1 0 1 1
0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 1
1 1 1 0 0 0 1 1
1 1 1 0 0 0 1 0
1 1 1 0 0 0 0 1
1 1 1 0 0 0 0 0
16
20
Within seg adding immed to SP
Intersegment
data-low
data-high
data-high
18
22
22
30
Intersegment adding immediate to SP
data-low
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
25
33
e
JE/JZ
Jump on equal/zero
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
5/15
6/16
6/16
6/16
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
4/13
5/15
6/16
6/16
6/16
JMP not
taken/JMP
taken
e
e
e
e
JL/JNGE
JLE/JNG
JB/JNAE
JBE/JNA
Jump on less/not greater or equal
Jump on less or equal/not greater
Jump on below/not above or equal
Jump on below or equal/not above
e
JP/JPE
Jump on parity/parity even
Jump on overflow
Jump on sign
e
e
JO
JS
e
e
e
e
e
e
JNE/JNZ
JNL/JGE
JNLE/JG
JNB/JAE
JNBE/JA
JNP/JPO
Jump on not equal/not zero
Jump on not less/greater or equal
Jump on not less or equal/greater
Jump on not below/above or equal
Jump on not below or equal/above
Jump on not par/par odd
e
e
JNO
JNS
Jump on not overflow
Jump on not sign
e
JCXZ
LOOP
Jump on CX zero
Loop CX times
e
LOOP not
taken/LOOP
taken
e
LOOPZ/LOOPE
LOOPNZ/LOOPNE
Loop while zero/equal
e
Loop while not zero/equal
e
ENTER
Enter Procedure
1 1 0 0 1 0 0 0
data-low
data-high
L
e
e
l
L
L
L
0
1
1
15
25
19
29
a
b
a
b
22 16(n 1)
26 20(n 1)
e
LEAVE
Leave Procedure
1 1 0 0 1 0 0 1
8
8
e
INT
Interrupt:
Type specified
Type 3
1 1 0 0 1 1 0 1
1 1 0 0 1 1 0 0
1 1 0 0 1 1 1 0
type
47
45
47
45
if INT. taken/
if INT. not
taken
e
INTO
Interrupt on overflow
48/4
48/4
e
IRET
Interrupt return
1 1 0 0 1 1 1 1
28
28
e
BOUND
Detect value out of range
0 1 1 0 0 0 1 0 mod reg r/m
33–35
33–35
Shaded areas indicate instructions not available in 8086, 8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.
31
31
80186/80188
INSTRUCTION SET SUMMARY (Continued)
80186
Clock
Cycles
80188
Clock
Cycles
Function
Format
Comments
PROCESSOR CONTROL
e
e
e
e
e
CLC
CMC
STC
CLD
STD
Clear carry
1 1 1 1 1 0 0 0
1 1 1 1 0 1 0 1
1 1 1 1 1 0 0 1
1 1 1 1 1 1 0 0
1 1 1 1 1 1 0 1
1 1 1 1 1 0 1 0
1 1 1 1 1 0 1 1
1 1 1 1 0 1 0 0
1 0 0 1 1 0 1 1
1 1 1 1 0 0 0 0
1 1 0 1 1 T T T
2
2
2
2
2
2
2
2
6
2
6
2
2
2
2
2
2
2
2
6
3
6
Complement carry
Set carry
Clear direction
Set direction
e
CLI
STI
Clear interrupt
Set interrupt
e
e
HLT
Halt
e
e
0
WAIT
LOCK
Wait
if TEST
e
Bus lock prefix
e
ESC
Processor Extension Escape
mod LLL r/m
(TTT LLL are opcode to processor extension)
1 0 0 1 0 0 0 0
e
NOP
No Operation
3
3
Shaded areas indicate instructions not available in 8086, 8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers, for word operations, add 4 clock cycles for each memory transfer.
reg is assigned according to the following:
FOOTNOTES
Segment
The Effective Address (EA) of the memory operand
is computed according to the mod and r/m fields:
reg
Register
00
01
10
11
ES
CS
SS
DS
e
e
e
if mod
if mod
if mod
11 then r/m is treated as REG field
e
00 then DISP
01 then DISP
0*, disp-low and disp-high are absent
disp-low sign-extended to 16-bits, disp-high
e
is absent
e
e
e
disp-high: disp-low
if mod
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
if r/m
10 then DISP
e
e
a
a
a
a
a
a
a
a
a
a
000 then EA
001 then EA
010 then EA
011 then EA
100 then EA
101 then EA
110 then EA
111 then EA
(BX)
(BX)
(BP)
(BP)
(SI)
(DI)
(BP)
(BX)
(SI)
(DI)
(SI)
(DI)
DISP
DISP
DISP
DISP
DISP
DISP
e
e
e
e
e
e
e
e
e
e
e
e
e
REG is assigned according to the following table:
e
e
0)
16-Bit (w
1)
8-Bit (w
a
a
DISP*
DISP
000 AX
001 CX
010 DX
011 BX
100 SP
101 BP
110 SI
000 AL
001 CL
010 DL
011 BL
100 AH
101 CH
110 DH
111 BH
DISP follows 2nd byte of instruction (before data if
required)
e
e
e
110 then EA
*except if mod
disp-high: disp-low.
00 and r/m
111 DI
EA calculation time is 4 clock cycles for all modes,
and is included in the execution times given whenev-
er appropriate.
The physical addresses of all operands addressed
by the BP register are computed using the SS seg-
ment register. The physical addresses of the desti-
nation operands of the string primitive operations
(those addressed by the DI register) are computed
using the ES segment, which may not be overridden.
Segment Override Prefix
0
0
1
reg
1
1
0
32
32
80186/80188
REVISION HISTORY
This data sheet replaces the following data sheets:
210706-011 80188
210451-011 80186
33
33
相关型号：
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