N80931AAX [INTEL]
USB Bus Controller, CMOS, PQCC68, PLASTIC, LCC-68;
| 型号： | N80931AAX |
| 厂家： | 
INTEL |
| 描述： | USB Bus Controller, CMOS, PQCC68, PLASTIC, LCC-68 |
| 文件： | 总26页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8x931AA/8x931HA Universal Serial Bus
Peripheral Controller
Advanced Information Datasheet
Product Features
■ 8x931AA Hubless USB Peripheral
■ 8x931HA Includes all 8x931AA Features
Controller
■ 8x931HA USB Hub has One Internal
Downstream, and Four External
Downstream Ports
■ On-chip USB Transceivers
■ On-chip Phase-locked loop
■ FIFO Data Buffers
—Universal Serial Bus Specification 1.0
Compliant
—Two Pairs of 8-byte Transmit and
Receive FIFOs
—Serves as both USB Hub and USB
Embedded Function (Internal Port)
—One Pair of 16-byte Transmit and
Receive FIFOs
■ USB Hub
—Connectivity Management
—Supports Isochronous and
Non-isochronous Data
—Downstream Device Connect/
Disconnect Detection
■ Automatic FIFO Management
■ Three USB Interrupt Vectors
—Endpoint Transmit/Receive Done
—Start of Frame
—Power Management, Including Suspend
and Resume
—Bus Fault Detection and Recovery
—Full and Low Speed Downstream
Device Support
—Global Suspend/Resume/USB Reset
■ Regulated 3V Output for Root Port Pullup
Resistor
■ On-chip ROM Options
■ Hub Endpoint Done Interrupt
■ Output Pin for Port Power Switching
■ Input Pin for Overcurrent Detection
■ Hub FIFO Data Buffers
—0 or 8 Kbytes
■ 256 bytes On-chip Data RAM
■ Four Input/Output Ports
■ MCS® 51 UART
■ Three 16-bit Timer/Counters
■ Keyboard Control Interface
■ Four Dedicated LED Driver Outputs
■ 6- or 12-MHz Crystal Operation
—Low Clock Mode (3MHz)
—One Pair of 8-byte Transmit and
Receive FIFOs
—One 1-byte Transmit Register
■ Embedded Function FIFO Data Buffers
—Same as the 8x931AA
■ 12-MHz Crystal Operation
—Low Clock Mode (3MHz)
The 8x931AA and 8x931HA USB peripheral controllers are based on the MCS®51
microcontroller. They consist of standard 8XC51Fx peripherals plus a USB module. The
8x931HA USB module provides both USB hub and USB embedded function capabilities. The
8x931HA supports USB hub functionality, embedded function, suspend/resume modes,
isochronous/non-isochronous transfers, and is USB rev 1.0 specification compliant. The USB
Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 273108-003
March 1998
module contains one internal and 4 external downstream ports and integrates the USB
transceivers, serial bus interface engine (SIE), hub interface unit (HIU), function interface unit
(FIU), and transmit/receive FIFOs. The 8x931AA is a hubless USB peripheral controller which
contains the same feature set as the 8x931HA hub controller except for the hub module. The
8x931AA/8x931HA Universal Serial Bus Peripheral Controller uses the standard instruction set
of the MCS®51 architecture.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 8x931AA/8x931HA Universal Serial Bus Peripheral Controller may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
Advance Information Datasheet
8x931AA/8x931HA
Contents
1.0
About This Document ..............................................................................................5
1.1
1.2
1.3
Additional Information Sources .............................................................................5
Electronic Information............................................................................................5
Product Summary..................................................................................................6
2.0
3.0
Nomenclature Overview..........................................................................................8
Pinout..............................................................................................................................9
3.1
3.2
8x931HA 68-pin PLCC Package...........................................................................9
8x931AA 68-pin PLCC Package .........................................................................10
4.0
5.0
Signals..........................................................................................................................13
Electrical Characteristics......................................................................................16
5.1
5.2
5.3
5.4
Operating Frequencies........................................................................................17
DC Characteristics ..............................................................................................18
Explanation of Timing Symbols...........................................................................19
System Bus AC Characteristics ..........................................................................20
5.4.1 System Bus Timing Diagrams................................................................21
AC Characteristics — Synchronous Mode 0.......................................................22
External Clock Drive............................................................................................23
Testing Waveforms .............................................................................................23
5.5
5.6
5.7
6.0
7.0
Thermal Characteristics........................................................................................24
Design Considerations ..........................................................................................24
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Low Clock Mode Frequency................................................................................24
Setting RXFFRC Bit Clears Only the Oldest Packet in the FIFO ........................25
Series Resistor Requirement for Impedance Matching.......................................25
Pullup Resistor Requirement for 8x931 devices .................................................25
Powerdown Mode Cannot Be Invoked Before USB Suspend.............................25
Unused Downstream Ports .................................................................................25
ECAP Usage to Supply 3.0 to 3.1 Volts for 1.5K Ohm Pullup.............................25
8.0
9.0
8x931 Errata................................................................................................................26
Datasheet Revision History .................................................................................26
Advance Information Datasheet
3
8x931AA/8x931HA
Figures
1
2
3
4
5
6
7
8
8x931 Functional Block Diagram ..........................................................................6
8x931HA USB Module Block Diagram..................................................................7
Product Nomenclature ..........................................................................................8
8x931HA 68-pin PLCC Package...........................................................................9
8x931AA 68-pin PLCC Package.........................................................................10
8x931 External Program Memory Read..............................................................21
8x931 External Data Memory Read ....................................................................21
8x931 External Data Memory Write ....................................................................22
Serial Port Waveform — Synchronous Mode 0 ..................................................22
External Clock Drive Waveforms ........................................................................23
AC Testing Input, Output Waveforms .................................................................23
Float Waveforms.................................................................................................24
9
10
11
12
Tables
1
2
3
4
5
6
7
8
Related Documentation.........................................................................................5
Electronic Information ...........................................................................................6
Description of Product Nomenclature ...................................................................8
8x931HA Proliferation Options..............................................................................8
8x931AA Proliferation Options..............................................................................9
68-pin PLCC Pin Assignment..............................................................................11
68-pin PLCC Signal Assignments Arranged by Functional Category .................12
Signal Descriptions .............................................................................................13
Absolute Maximum Ratings† ..............................................................................16
Operating Conditions† ........................................................................................16
8x931AA/8x931HA Supply Voltages...................................................................16
8x931HA Operating Frequency...........................................................................17
8x931AA Operating Frequency...........................................................................17
DC Characteristics at Operating Conditions .......................................................18
AC Timing Symbol Definitions.............................................................................19
External Bus Characteristics ...............................................................................20
Serial Port Timing — Synchronous Mode 0 ........................................................22
External Clock Drive............................................................................................23
Thermal Characteristics ......................................................................................24
9
10
11
12
13
14
15
16
17
18
19
4
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
1.0
About This Document
This data sheet contains advance information about Intel’s 8x931AA and 8x931HA Universal
Serial Bus peripheral controllers, based on the MCS®51 architecture, which includes a functional
overview, mechanical data, targeted electrical specifications (simulated), and bus functional
waveforms. A detailed functional description, other than parametric performance, is published in
the 8x931AA, 8x931HA Universal Serial Bus Peripheral Controller User’s Manual (273102-001).
1.1
Additional Information Sources
Intel documentation is available from your local Intel Sales Representative or Intel Literature
Sales.
Intel Corporation
Literature Sales
PO Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
1.2
Electronic Information
We offer a variety of technical and product information through the World Wide Web (see Table
for URL) and through FaxBack service which is an on-demand publishing system that sends
documents to your fax machine. You can get product announcements, change notifications,
product literature, device characteristics, design recommendations, and quality and reliability
information 24 hours a day, 7 days a week. Just dial the telephone number and respond to the
system prompts.
Table 1. Related Documentation
Document Title
Order/Contact
8x931AA, 8x931HA Universal Serial Bus Peripheral
Controller User’s Manual
Intel Order #273102-001
Intel Order #272904
Universal Serial Bus Specification, Rev. 1.0
Advance Information Datasheet
5
8x931AA, 8x931HA USB Peripheral Controller
Table 2. Electronic Information
Document Title
Order/Contact
Intel’s World-Wide Web (WWW) Location:
Customer Support (US and Canada):
FaxBack Service:
http://www.intel.com/design/usb/
800-628-8686
US and Canada
800-628-2283
+44(0)793-496646
916-356-3105
Europe
worldwide
Application Bulletin Board Service:
up to 14.4-Kbaud line, worldwide
dedicated 2400-baud line, worldwide
Europe
916-356-3600
916-356-7209
+44(0)793-496340
1.3
Product Summary
Figure 1. 8x931 Functional Block Diagram
Data
Address
Register
Program
Address
Register
Program
Counter
Upstream
Port
RAM
ROM
USB
Module
B
ACC
Stack
Pointer
Downstream
Ports
ALU
HA only
Data
Pointer
On-chip
Peripherals
Instruction
Sequencer
Parallel
Ports
Clock
and
Reset
A4518-01
6
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
Figure 2. 8x931HA USB Module Block Diagram
USB External
Downstream Ports
DM2
DP2
Transceiver
USB Upstream Port
(Hub Root Port)
DM3
DP3
Transceiver
DM0
Repeater
Transceiver
DP0
DM4
Transceiver
DP4
DM5
Transceiver
DP5
Serial Bus Interface Engine
(SIE)
Hub
Interface
Unit
Function
Interface
Unit
(HIU)
(FIU)
Control
Transmit/Receive Bus
To
CPU
Data Bus
Control
FIFOs
A5247-01
Advance Information Datasheet
7
8x931AA, 8x931HA USB Peripheral Controller
2.0
Nomenclature Overview
Figure 3. Product Nomenclature
X
X
8
X
X
XXXXX
X
A2815-02
Table 3. Description of Product Nomenclature
Parameter
Options
Description
Commercial operating temperature range (0oC to 70oC) with
Intel standard burn-in
Temperature and Burn-in
Packaging Options
no mark
N
Plastic Leaded Chip Carrier (PLCC)
Without ROM
0
3
Program Memory Options
With ROM
Process and Voltage Information
no mark
CHMOS
Advanced 8-bit microcontroller architecture with on-chip
Universal Serial Bus Hub and Function capability. Indicates
ROM size, RAM size, and quantity of external downstream
ports (see Table ).
931Hx
931Ax
Product Family
Advanced 8-bit microcontroller architecture with on-chip
Universal Serial Bus Function capability. Indicates ROM
size, RAM size, and quantity of external downstream ports
(see Table ).
see spec
update
Stepping Information
Identification for product stepping revisions.
Table 4. 8x931HA Proliferation Options
Part Name
ROM Size
RAM Size
Package
N80931HA
N83931HA
0
256 bytes
256 bytes
68-pin PLCC
68-pin PLCC
8 Kbytes
8
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
Table 5. 8x931AA Proliferation Options
Part Name
ROM Size
RAM Size
Package
N80931AA
N83931AA
0
256 bytes
256 bytes
68-pin PLCC
68-pin PLCC
8 Kbytes
3.0
Pinout
3.1
8x931HA 68-pin PLCC Package
Figure 4 illustrates a diagram of the 8x931HA PLCC package. Table 6 and Table contain indexes
of the pin arrangement. Table 8 contains the signal descriptions for all pins.
Figure 4. 8x931HA 68-pin PLCC Package
D
D
D
D
V
AD7 / P0.7 / KSI7
AD6 / P0.6 / KSI6
AD5 / P0.5 / KSI5
AD4 / P0.4 / KSI4
AD3 / P0.3 / KSI3
AD2 / P0.2 / KSI2
AD1 / P0.1 / KSI1
AD0 / P0.0 / KSI0
10
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
P4
M4
P5
M5
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CC
D
P0
D
8x931Hx
M0
ECAP
V
V
SS
SS
V
V
CC
CC
V
P3.0 / OVRI#
P3.1 / SOF#
P3.2 / INT0#
SS
View of component as
mounted on PC board
D
P3
D
M3
V
P3.3 / INT1#
SS
D
P3.4 / T0 / KSO16
P3.5 / T1 / KSO17
P3.6 / WR# / KSO18
P2
D
M2
LED0
Note:
Reserved pins must be left unconnected.
A5340-02
Advance Information Datasheet
9
8x931AA, 8x931HA USB Peripheral Controller
3.2
8x931AA 68-pin PLCC Package
Figure 5 illustrates a diagram of the 8x931AA PLCC package. Table 6 and Table 7 contain indexes
of the pin arrangement. Table 8 contains the signal descriptions for all pins.
Figure 5. 8x931AA 68-pin PLCC Package
Reserved (NC)
Reserved (NC)
Reserved (NC)
Reserved (NC)
AD7 / P0.7 / KSI7
AD6 / P0.6 / KSI6
AD5 / P0.5 / KSI5
AD4 / P0.4 / KSI4
AD3 / P0.3 / KSI3
AD2 / P0.2 / KSI2
AD1 / P0.1 / KSI1
AD0 / P0.0 / KSI0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
CC
D
P0
D
8x931Ax
M0
ECAP
V
V
SS
SS
V
V
CC
CC
V
P3.0
P3.1 / SOF#
P3.2 / INT0#
SS
View of component as
mounted on PC board
Reserved (NC)
Reserved (NC)
V
P3.3 / INT1#
SS
Reserved (NC)
Reserved (NC)
LED0
P3.4 / T0 / KSO16
P3.5 / T1 / KSO17
P3.6 / WR# / KSO18
Note:
Reserved pins must be left unconnected.
A5348-02
10
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
Table 6. 68-pin PLCC Pin Assignment
Pin
Name
Pin
Name
Pin
Name
1
2
VSS
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
P3.4/T0/KSO16
P3.5/T1/KSO17
P3.6/WR#/KSO18
P3.7/RD#/KSO19
P1.0/T2/KSO0
P1.1/T2EX/KSO1
P1.2/KSO2
P1.3/KSO3
P1.4/KSO4
P1.5/KSO5
P1.6/KSO6/RXD
P1.7/KSO7/TXD
LED3
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
VSS
A15/P2.7/KSO15
A14/P2.6/KSO14
A13/P2.5/KSO13
A12/P2.4/KSO12
A11/P2.3/KSO11
A10/P2.2/KSO10
A9/P2.1/KSO9
A8/P2.0/KSO8
AD7/P0.7/KSI7
AD6/P0.6/KSI6
AD5/P0.5/KSI5
AD4/P0.4/KSI4
AD3/P0.3/KSI3
AD2/P0.2/KSI2
AD1/P0.1/KSI1
AD0/P0.0/KSI0
VSS
Reserved†/ DM3††
3
Reserved†/ DP3††
4
VSS
5
VCC
6
VSS
7
ECAP
8
DM0
9
DP0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
VCC
Reserved†/ DM5††
Reserved†/ DP5††
Reserved†/ DM4††
Reserved†/ DP4††
Reserved (NC)
Reserved (NC)
VSS
LED2
XTAL1
XTAL2
AVCC
RST
FSSEL†/ UPWEN#††
PSEN#
VCC
PLLSEL
P3.0/ OVRI#††
P3.1/SOF#
LED1
ALE
LED0
EA#
P3.2/INT0#
Reserved†/ DM2††
Reserved†/ DP2††
VCC
P3.3/INT1#
† Specific to the 8x931AA
†† Specific to the 8x931HA
Advance Information Datasheet
11
8x931AA, 8x931HA USB Peripheral Controller
Table 7. 68-pin PLCC Signal Assignments Arranged by Functional Category
Address & Data
Name
Input/Output
Name
USB
Name
Pin
Pin
Pin
A15/P2.7/KSO15
2
3
4
5
6
7
8
P1.0/T2/KSO0
28
29
30
31
32
33
34
PLLSEL
DM0
42
54
55
57
58
45
46
A14/P2.6/KSO14
A13/P2.5/KSO13
A12/P2.4/KSO12
A11/P2.3/KSO11
A10/P2.2/KSO10
A9/P2.1/KSO9
P1.1/T2EX/KSO1
P1.2/KSO2
P1.3/KSO3
P1.4/KSO4
P1.5/KSO5
P1.6/KSO6
DP0
Reserved†/ DM5††
Reserved†/ DP5††
Reserved†/ DM2††
Reserved†/ DP2††
Address & Data
Input/Output
Name
P1.7/KSO7
USB
Name
Pin
Pin
Name
Pin
A8/P2.0/KSO8
AD7/P0.7/KSI7
AD6/P0.6/KSI6
AD5/P0.5/KSI5
AD4/P0.4/KSI4
AD3/P0.3/KSI3
AD2/P0.2/KSI2
AD1/P0.1/KSI1
AD0/P0.0/KSI0
9
35
20
21
22
23
24
25
26
27
Reserved†/ DM3††
Reserved†/ DP3††
ECAP
48
49
53
59
60
64
20
10
11
12
13
14
15
16
17
P3.0/ OVRI#††
P3.1/SOF#
P3.2/INT0#
Reserved†/ DM4††
Reserved†/ DP4††
FSSEL†/UPWEN#††
OVRI#††
P3.3/INT1#
P3.4/T0/KSO16
P3.5/T1/KSO17
P3.6/WR#/KSO18
P3.7/RD#/KSO19
Processor Control
Name
P3.2/INT0#
Power & Ground
Name
Bus Control & Status
Pin
Pin
Name
Pin
19,51,5
6,68
22
23
VCC
P3.6/WR#/KSO18
P3.7/RD#/KSO19
26
27
P3.3/INT1#
RST
AVCC
40
1,18,
47,50,
52,63
41
VSS
PSEN#
65
XTAL1
XTAL2
38
39
ALE
EA#
66
67
† Specific to the 8x931AA
†† Specific to the 8x931HA
12
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
4.0
Signals
Table 8. Signal Descriptions (Sheet 1 of 3)
Signal
Type
Alternate
Description
Function
Name
A15:8
AD7:0
O
Address Lines. Upper byte of external memory address.
P2.7:0/KS08:15
P0.7:0/KSI0:7
I/O
Address/Data Lines. Lower byte of external memory address
multiplexed with data
ALE
O
Address Latch Enable. ALE signals the start of an external
bus cycle and indicates that valid address information is
available on lines A15:8 and AD7:0. An external latch can use
ALE to demultiplex the address from the address/data bus.
—
AVCC
PWR Analog VCC. A separate VCC input for the phase-locked loop
—
—
circuitry.
D
M0, DP0
I/O
USB Port 0. Root port. Upstream port to the host PC. DP0 and
M0 are the differential data plus and data minus signals of USB
D
port 0. These lines do not have internal pullup resistors. Provide
an external 1.5 KΩ pullup resistor at DP0 so the device indicates
to the host that it is a full-speed device; or provide an external
1.5 KΩ pullup resistor at DM0 so the device indicates to the host
that it is a low-speed device.
NOTE:
D
P0 low AND DM0 low signals an SE0 (USB reset),
causing the 8x931 to stay in reset.
D
D
D
D
M2, DP2
M3, DP3
M4, DP4
M5, DP5
I/O
USB External Downstream Ports 2, 3, 4,5. These pins are the
differential data plus and data minus lines for the four USB
external downstream ports. These lines do not have internal
pulldown resistors. Provide an external 15 KΩ pulldown resistor
at each of these pins. See Design Considerations on page 24.
—
—
EA#
I
External Access. Directs program memory accesses to on-
chip or off-chip code memory. For EA# strapped to ground, all
program memory accesses are off-chip. For EA# strapped to
V
CC, program accesses on-chip ROM if the address is within the
range of the on-chip ROM; otherwise the access is off-chip. The
value of EA# is latched at reset. For devices without on-chip
ROM, EA# must be strapped to ground.
ECAP
I
External Capacitor. Connect a 1 µF or larger capacitor
between this pin and VSS to ensure proper operation of the
differential line drivers. May be used to supply 3.0v to 3.1v for
1.5K pullup resistor connected to USB Port 0. See “Design
Considerations” on page 24.
—
FSSEL
Full Speed Select. Applies to the 8x931AA only. If this pin is
high, full speed USB data rate is selected (12Mbps). If pin is
low, low speed USB data rate is selected (1.5 Mbps). Refer to
Table 11.
—
INT1:0#
I
I
External Interrupts 0 and 1. These inputs set the IE1:0
interrupt flags in the TCON register. Bits IT1:0 in TCON select
the triggering method: edge-triggered (high-to-low) or level
triggered (active low). INT1:0 also serves as external run
control for timer1:0 when selected by GATE1:0# in TCON.
P3.3:2
KSI7:0
Keyboard Scan Input. Schmitt-trigger inputs with firmware-
enabled internal pullup resistors used for the input side of the
keyboard scan matrix.
AD7:0/P0.7:0
Advance Information Datasheet
13
8x931AA, 8x931HA USB Peripheral Controller
Table 8. Signal Descriptions (Sheet 2 of 3)
Signal
Type
Alternate
Function
Description
Name
KSO19
O
Keyboard Scan Output. Quasi-bidirectional ports with weak
P3.7/RD#
KSO18
internal pullup resistors used for the output side of the keyboard P3.6/WR#
KSO17:16
KSO15:8
KSO7:0
scan matrix.
P3.5:4/T1:0
A15:8/P2.7:0
P1.7:0
LED3:0
O
LED Drivers. Designed to drive LEDs connected directly to
—
V
V
CC. The current each driver is capable of sinking is given as
OL2 in the datasheet.
OVRI#
I
Overcurrent Sense. Sense input to indicate an overcurrent
condition on an external down-stream port. Active low with an
internal pullup.
P3.0
P0.7:0
P1.7:0
P2.7:0
I/O
I/O
I/O
I/O
Port 0. Eight-bit, open-drain, bidirectional I/O port. Port 0 pins
have Schmitt trigger inputs.
AD7:0/KSI7:0
KSO7:0
Port 1. Eight-bit quasi-bidirectional I/O port with internal
pullups.
Port 2. Eight-bit quasi-bidirectional I/O port with internal
pullups.
A15:8/KSO15:8
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 3. Eight-bit quasi-bidirectional I/O port with internal
pullups.
OVRI#
SOF#
INT0#
INT1#
T0/KSO16
T1/KSO17
WR#/KSO18
RD#/KSO19
PLLSEL
I
Phase-locked Loop Select. For normal operation using the
8x931HA, connect PLLSEL to logic high. PLLSEL = 0 is used
for factory test only. (See Table 10). For 8x931AA operation,
see Table 11.
—
PSEN#
RD#
O
O
Program Store Enable. Read signal output. Asserted for read
accesses to external program memory.
—
Read. Read signal output. Asserted for read accesses to
P3.7/KSO19
external data memory.
RXD
I/O
I
Receive Serial Data. RXD sends and receives data in serial
I/O mode 0 and receives data in serial I/O modes 1, 2, and 3.
P1.6
—
RST
Reset. Reset input to the chip. Holding this pin high for two
machine cycles while the oscillator is running resets the device.
The port pins are driven to their reset conditions when a voltage
greater than VIH1 is applied, whether or not the oscillator is
running. This pin has an internal pulldown resistor which allows
the device to be reset by connecting a capacitor between this
pin and VCC
.
Asserting RST when the chip is in idle mode or powerdown
mode returns the chip to normal operation.
SOF#
O
Start of Frame. Start of frame pulse. Active low. Asserted for 8 P3.1
states when frame timer is locked to USB frame timing and
SOF token or artificial SOF is detected.
T1:0
T2
I
Timer 1:0 External Clock Input. When timer 1:0 operates as a P3.5:4/KSO17:16
counter, a falling edge on the T1:0 pin increments the count.
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode,
this signal is the external clock input. For the clock-out mode, it
is the timer 2 clock output.
P1.0
14
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
Table 8. Signal Descriptions (Sheet 3 of 3)
Signal
Type
Alternate
Description
Function
Name
T2EX
I
Timer 2 External Input. In timer 2 capture mode, a falling edge P1.1
initiates a capture of the timer 2 registers. In auto-reload mode,
a falling edge causes the timer 2 registers to be reloaded. In the
up-down counter mode, this signal determines the count
direction: 1 = up, 0 = down.
TXD
O
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O
mode 0 and transmits serial data in serial I/O modes 1, 2, and
3.
P1.7
UPWEN#
USB Power Enable. A low signal on this pin applies power to
the external downstream ports.
—
—
VCC
PWR Supply Voltage. Connect this pin to the +5v supply voltage.
Use a 0.1µf decoupling capacitor for each Vcc pin.
VSS
GND Circuit Ground. Connect this pin to ground.
—
WR#
XTAL1
O
I
Write. Write signal output to external memory.
P3.6/KSO19
—
Oscillator Amplifier Input. When implementing the on-chip
oscillator, connect the external crystal or ceramic resonator
across XTAL1 and XTAL2. If an external clock source is used,
connect it to this pin.
XTAL2
O
Oscillator Amplifier Output. When implementing the on-chip
oscillator, connect the external crystal or ceramic resonator
across XTAL1 and XTAL2. If an external oscillator is used,
leave XTAL2 unconnected.
—
Advance Information Datasheet
15
8x931AA, 8x931HA USB Peripheral Controller
5.0
Electrical Characteristics
Note: This document contains information on products in the sampling and initial production phases of
development. The specifications are subject to change without notice.Verify with your local Intel
sales office that you have the latest datasheet before finalizing a design.
Table 9. Absolute Maximum Ratings†
Parameter
Maximum Rating
Ambient Temperature Under Bias
Storage Temperature
Voltage on Any Pins to VSS
IOL per I/O Pin
–40°C to +85°C
–65°C to +150°C
–0.5 V to +6.5 V
15 mA
Power Dissipationa
1.5 W
a. Maximum power dissipation is based on package heat-transfer limitations, not device power consumption.
† Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extended exposure beyond the “Operating Conditions” may affect device reliability.
Table 10. Operating Conditions†
Symbol
Parameter
Min
Max
TA
Ambient Temperature Under Bias
Digital Supply Voltage
Digital Supply Voltage
Analog Supply Voltage
XTAL1 Frequency
–0°C
+70°C
5.25 V
VCC
4.40 V
VSS
0V
AVCC
FOSC
4.40 V
5.25 V
12 MHz ± 0.25%
Table 11. 8x931AA/8x931HA Supply Voltages
Parameter
Condition
Symbol
Min
Max
8x931HA Vcc/Vbus
8x931AA Vcc/Vbus
4.40V
5.25V
5.25V
Supply Voltage
4.15V†
†For bus-powered device, voltage droop during hot plug may cause the supply voltage to drop to 4V
worst case. The functionality of the device is supported at this voltage.
16
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
5.1
Operating Frequencies
Table 12. 8x931HA Operating Frequency
XTAL1
Internal
XTAL1
Frequency
Clocks per
USB Rate
(1)
Frequency
PLLSEL
State
(TOSC/state)
(3)
Comments
(FCLK
)
(FOSC
)
(2)
0 (4)
–
–
–
–
2
–
12 Mbps (Full
Speed)
1
12 MHz
6 MHz (3)
PLL On
NOTES:
1. The sampling rate is 4 times the USB rate.
2. The internal frequency, FCLK = 1/TCLK, is the clock signal distributed to the CPU and the on-chip
peripherals,
3. Following device reset, the CPU and on-chip peripherals operate in low-clock mode (FCLK = 3
MHz) until the LC bit in the PCON register is cleared. In low clock mode, there are four TOSC
periods per state. Low-clock mode does not affect the USB rate.
4. PLLSEL = 0 is used during factory test only.
Table 13. 8x931AA Operating Frequency
Core
Frequency
FCLK
XTAL1
Frequency
(MHz)
USB Rate
(FS/LS)
(2)
PLLSEL FSSEL
LC Bit
(1)
Comment
Pin
Pin
(Mhz)
0
0
0
0
0
1
1
0
1
0
1
0
1
6
LS
LS
LS
LS
FS
FS
3
3
6
3
6
3
PLL Off
PLL Off
PLL Off
PLL Off
PLL On
PLL On
0
6
1
12
12
12
12
1
1
1
NOTES:
1. Reset and power up routines set the LC bit in PCON to put the 8x931AA in low-clock mode (core
frequency = 3 MHz) for lower ICC prior to device enumeration. Following completion of device
enumeration, firmware should clear the LC bit to exit the low-clock mode. The user may switch the
core frequency back and forth at any time, as needed.
2. USB rates: Low speed = 1.5 Mbps; Full speed = 12 Mbps. The USB sample rate is 4X the USB rate.
Advance Information Datasheet
17
8x931AA, 8x931HA USB Peripheral Controller
5.2
DC Characteristics
Table 14. DC Characteristics at Operating Conditions (Sheet 1 of 2)
Typical
(1)
Symbol
Parameter
Min
Max
Units
Test Conditions
Input Low Voltage
(except EA#)
VIL
–0.5
0
0.2 VCC – 0.1
0.2 VCC – 0.3
VCC + 0.5
V
V
V
V
Input Low Voltage
(EA#)
VIL1
VIH
Input High Voltage
(except XTAL1, RST)
0.2 VCC + 0.9
0.7 VCC
Input High Voltage
(XTAL1, RST)
VIH1
VCC + 0.5
0.3
0.45
1.0
I
OL = 100 µA
Output Low Voltage
(port 1, 2, 3)
(2)
VOL
V
IOL = 1.6 mA
IOL = 3.5 mA
Output Low Voltage
(port 0, ALE, PSEN#,
SOF#)
0.3
0.45
1.0
IOL = 200 µA
VOL1
VOL2
VOH
V
V
V
IOL = 3.2 mA
IOL = 7.0 mA
(2)
2.0
3.0
IOL = 6 mA
Output Low Voltage
(LED 0, 1, 2, 3)
IOL = 22 mA
Output High Voltage
(port 1, 2, 3, ALE,
PSEN#, SOF#)
(3)
V
CC – 0.3
CC – 0.7
IOH = –10 µA
V
I
OH = –30 µA
VCC – 1.5
IOH = –60 µA
Output High Voltage
(port 0 in external
address space)
(3)
V
CC – 0.3
VCC – 0.7
CC – 1.5
IOH = –200 µA
IOH = –3.2 mA
VOH1
V
V
IOH = –7.0 mA
Logical 0 Input
Current
(port 1,2,3)
IIL
–50
±10
µA
µA
µA
V
V
V
IN = 0.45 V
IN = VIL or VIH
IN = 2.0 V
Input Leakage Current
(port 0)
ILI
Logical 1-to-0
Transition Current
(Port 1, 2,3)
ITL
–650
100
RST Pulldown
Resistor
RRST
40
KΩ
FOSC = 12 MHz
TA = 25°C
CIO
Pin Capacitance
10
pF
NOTES:
1. Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE
or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the VCC
specification when the address lines are stabilizing.
18
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
Table 14. DC Characteristics at Operating Conditions (Sheet 2 of 2)
Typical
(1)
Symbol
IPD
Parameter
Min
Max
Units
µA
Test Conditions
Powerdown Current
USB suspend
145
175
40
30
F
F
CLK =6 MHz
CLK =3 MHz
IDL
Idle Mode ICC
mA
70
F
CLK = 6 MHz
ICC
Active ICC
mA
50
25
FCLK = 3MHz
UZDRV
USB Drivers Output
10
KΩ
NOTES:
1. Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE
or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the VCC
specification when the address lines are stabilizing.
5.3
Explanation of Timing Symbols
Table defines the timing symbols used in Tables 14 through and the associated timing diagrams.
They have the form Txxyy, where the character pairs represent a signal and its condition. Timing
symbols represent the time between two signal / condition points.
Table 15. AC Timing Symbol Definitions
Symbol
Definition
A
C
D
L
Address: A15:8, A7:0
External Clock (XTAL1)
Data In: D7:0
ALE: Address Latch Enable
Program Store Enable (PSEN#)
Data Out: D7:0
P
Q
R
W
Read: RD#
Write: WR#
Character
Condition
H
L
High
Low
V
X
Z
Valid, Setup
No Longer Valid, Hold
Floating (low impedance)
Advance Information Datasheet
19
8x931AA, 8x931HA USB Peripheral Controller
5.4
System Bus AC Characteristics
Test Conditions: Fosc = 12 MHz. Rise and fall times = 10 ns. Capacitive loading on ALE,
PSEN#, and port P0 = 100 pF. Capacitive loading on all other outputs = 80 pF.
Table 16. External Bus Characteristics (Sheet 1 of 2)
F
F
OSC = 12 MHz,
CLK = 6 MHz
Variable FCLK
Symbol
Parameter
Units
Min
Max
Min
Max
FOSC
TCLK
XTAL1 Frequency
1/FCLK = 1/CPU Frequency
ALE Pulse Width
12 ± 0.25%
MHz
ns
166.67 (Typical)
TLHLL
TAVLL
127
43
TCLK – 40
0.5TCLK – 40
0.5TCLK – 30
ns
Address Valid to ALE Low
ns
Address Hold after ALE
Low
TLLAX
53
ns
PSEN# Low to Address
Float
TPLAZ
TLLIV
10
10
ns
ns
ALE Low to Instruction In
Valid
259
2TCLK – 75
TLLPL
TPLPH
ALE Low to PSEN# Low
PSEN# Pulse Width
53
0.5TCLK – 30
1.5TCLK – 45
ns
ns
205
PSEN# Low to Instruction
In Valid
TPLIV
TPHIX
TPHIZ
TAVIV
77
T
CLK – 90
ns
ns
ns
ns
Instruction Hold after
PSEN# High
0
0
Instruction Float after
PSEN# High
63
312
0.5TCLK – 20
Address Valid to
Instruction Valid
2.5TCLK – 105
1.5TCLK + 50
ALE Low to RD# or WR#
Low
T
LLRL, TLLWL
200
400
300
1.5TCLK – 50
3TCLK – 100
ns
ns
RD# and WR# Pulse
Width
T
RLRH, TWLWH
TLLDV
TRLDV
TRLAZ
TRHDX
TRHDz
ALE Low to Data In Valid
RD# Low to Data In Valid
RD# Low to Address Float
Data Hold After RD# High
Data Float After RD# High
578
322
0
4TCLK – 90
2.5TCLK – 95
0
ns
ns
ns
ns
ns
0
0
23
0.5TCLK – 60
2TCLK – 90
Address Valid to RD# or
WR# Low
TAVRL, TAVWL
244
ns
4.5TCLK – 90
0.5TCLK + 40
Address Valid to Data In
Valid
TAVDV
661
123
ns
ns
RD# or WR# High to ALE
High
TRHLH, TWHLH
43
0.5TCLK – 40
20
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
Table 16. External Bus Characteristics (Sheet 2 of 2)
F
F
OSC = 12 MHz,
CLK = 6 MHz
Variable FCLK
Symbol
Parameter
Units
Min
Max
Min
Max
Data Valid to WR#
Transition
TQVWX
48
0.5TCLK – 35
ns
TQVWH
TWHQX
Data Valid to WR# High
514
43
3.5TCLK – 70
0.5TCLK – 40
ns
ns
Data Hold After WR# High
5.4.1
System Bus Timing Diagrams
Figure 6. 8x931 External Program Memory Read
TLHLL
ALE
TLLIV
TLLPL
TAVLL
TPLPH
TPLIV
TPLAZ
PSEN#
TPHIZ
TLLAX
A7:0
TPHIX
Port 0
Port 2
INSTR IN
A7:0
TAVIV
A15:8
A15:8
A5280-02
Figure 7. 8x931 External Data Memory Read
ALE
TLHLL
TRHLH
PSEN#
TLLDV
TLLRL
TRLRH
RD#
Port 0
Port 2
TAVLL
TLLAX
TRLDV
TRLAZ
TRHDZ
TRHDX
A7:0 from PCL
A7:0 from RI or DPL
Data In
Inst. In
TAVRL
TAVDV
P2.7:0 or A15:8 from DPH
A15:8 from PCH
A5275-02
Advance Information Datasheet
21
8x931AA, 8x931HA USB Peripheral Controller
Figure 8. 8x931 External Data Memory Write
ALE
TLHLL
TWHLH
PSEN#
TLLWL
TWLWH
WR#
TAVLL
TLLAX
TQVWX
TWHQX
A7:0 from PCL
TQVWH
Data Out
Port 0
Port 2
A7:0 from RI or DPL
TAVWL
Inst. In
P2.7:0 or A15:8 from DPH
A15:8 from PCH
A5276-01
5.5
AC Characteristics — Synchronous Mode 0
Figure 9. Serial Port Waveform — Synchronous Mode 0
T
XLXL
TXD
T
XHQX
†
†
Set TI
T
QVXH
RXD
(Out)
0
1
2
7
4
6
3
5
T
T
XHDV
XHDX
Set RI
RXD
(In)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
†
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
A2592-02
Table 17. Serial Port Timing — Synchronous Mode 0
Symbol
Txlxl
Parameter
Min
Max
Units
Serial Port Clock Cycle Time
12 Tosc
10 TOSC – 133
2 Tosc – 50
0
ns
ns
ns
ns
ns
Tqvxh
Txhqx
Txhdx
Txhdv
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
10 TOSC – 133
22
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
5.6
External Clock Drive
Figure 10. External Clock Drive Waveforms
TCLCH
TCHCX
VCC – 0.5
0.7 VCC
TCLCX
0.2 VCC – 0.1
0.45 V
TCHCL
TCLCL
A4119-01
Table 18. External Clock Drive
Symbol
1/TOSC
TCHCX
TCLCX
Parameter
Oscillator Frequency (FOSC
High Time
Min
6
Max
Units
)
12
MHz
ns
20
20
Low Time
ns
TCLCH
Rise Time
20
20
ns
TCHCL
Fall Time
ns
5.7
Testing Waveforms
Figure 11. AC Testing Input, Output Waveforms
Outputs
Inputs
VCC – 0.5
0.2 VCC + 0.9
0.2 VCC – 0.1
VIH MIN
VOL MAX
0.45 V
AC inputs during testing are driven at VCC – 0.5V for a logic 1
and 0.45 V for a logic 0. Timing measurements are made at
a min of VIH for a logic 1 and VOL for a logic 0.
A4118-01
Advance Information Datasheet
23
8x931AA, 8x931HA USB Peripheral Controller
Figure 12. Float Waveforms
VLOAD + 0.1 V
VLOAD
VOH – 0.1 V
Timing Reference
Points
V
OL + 0.1 V
VLOAD – 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading VOH/VOL level occurs
with IOL/IOH = ± 1 mA.
A4117-01
6.0
Thermal Characteristics
The microcontroller operates over the commercial temperature range from 0oC to 70oC. All
thermal impedance data (see Table 17) is approximate for static air conditions at 1 watt of power
dissipation. Values change depending on operating conditions and application requirements. The
Intel Packaging Handbook (order number 240800) describes Intel’s thermal impedance test
methodology. The Components Quality and Reliability Handbook (order number 210997) provides
quality and reliability information.
Table 19. Thermal Characteristics
Package Type
68-pin PLCC
θJA†
θJC†
N/A
N/A
† Data unavailable at time of publication.
7.0
Design Considerations
7.1
Low Clock Mode Frequency
During low clock mode, the internal clock FCLK distributed to the CPU and peripherals is 3 MHz.
Peripheral timing and external bus accesses (including instruction fetch and data read/write) are
affected. Refer to Table 10 and Table 11 for clock rates.
24
Advance Information Datasheet
8x931AA, 8x931HA USB Peripheral Controller
7.2
7.3
Setting RXFFRC Bit Clears Only the Oldest Packet in the
FIFO
If the receive FIFO is set as a dual packet mode, then it can receive two packets. Setting RXFFRC
(in RXCON registers) to indicate FIFO Read Complete will not flush the entire FIFO; it will flush
only the oldest packet. The read marker will be advanced to the location of the read pointer.
Series Resistor Requirement for Impedance Matching
Per USB rev. 1.0 specification (page 111, section 7.1.1.1), the impedance of the differential driver
must be between 29Ω and 44Ω. To match the cable impedance, a series resistor of 27Ω to 33Ω
should be connected to each USB line; i.e., on DP0 and on DM0. If the USB line is improperly
terminated or not matched, then signal fidelity will suffer. This condition can be seen on the
oscilloscopes as excessive overshoot and undershoot. This condition can potentially introduce bit
errors.
7.4
Pullup Resistor Requirement for 8x931 devices
The USB specification requires a pullup resistor to allow the host to identify which devices are low
speed and which are full speed in order to communicate at the appropriate data rate. For 8x931HA
hub devices (12 Mbps), use a 1.5KΩ pullup resistor (to 3.0 V – 3.6 V; may use the ECAP pin.) on
the DP0 line. 8x931AA devices can be either full speed or low speed; add a 1.5KΩ pullup to the
appropriate USB line.
7.5
7.6
Powerdown Mode Cannot Be Invoked Before USB Suspend
If the 8x931 is put into powerdown mode before receiving a USB suspend signal from the host,
then a USB resume will not properly wake up the 8x931 from powerdown mode.
Unused Downstream Ports
If the USB downstream ports are not used, it is still required that the two data lines be pulled low
externally (similar to a disconnect) so that the inputs are not floating. This will eliminate the
possibility of induced system noise. All USB data lines require 15KΩ external pulldown resistors.
Do not leave unused port(s) disconnected.
7.7
ECAP Usage to Supply 3.0 to 3.1 Volts for 1.5K Ohm Pullup
For a self-powered or bus-powered device, the voltage at ECAP pin is maintained at 3.0v – 3.1v.
The capability for this pin to supply the 3.0v to 3.1v voltage to the 1.5KΩ USB pullup terminator is
not dependent upon the VCC voltage level.
Advance Information Datasheet
25
8x931AA, 8x931HA USB Peripheral Controller
8.0
9.0
8x931 Errata
The 8x931 may contain design defects or errors known as errata. Characterized errata that may
cause the 8x931’s operational behavior to deviate from published specifications are documented in
a specification update. Specification updates can be obtained from your local Intel sales office or
from the World Wide Web (www.intel.com).
Datasheet Revision History
Datasheets are changed as new device information becomes available. Verify with your local Intel
sales office that you have the latest version before finalizing a design or ordering devices.
This (-002) revision of the 8x931 datasheet replaces earlier product information. The following
changes were made in this version:
1. Changed product nomenclature parameter information in Figure 3 and Table on page 8.
Changed the Device Speed parameter to Stepping Identifier and changed the description.
2. Changed ECAP voltage range to 3.0 – 3.1 on page 25.
3. Changed Figure 12 “Float Waveforms” on page 24 to reflect a reduction to theIOL/IOH load
value from +/- 20mA to +/- 1mA.
26
Advance Information Datasheet
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