N80C251SB-16 [INTEL]
Microcontroller, 8-Bit, 80251 CPU, 16MHz, CMOS, PQCC44, PLASTIC, LCC-44;
| 型号： | N80C251SB-16 |
| 厂家： | 
INTEL |
| 描述： | Microcontroller, 8-Bit, 80251 CPU, 16MHz, CMOS, PQCC44, PLASTIC, LCC-44 时钟 微控制器 外围集成电路 |
| 文件： | 总35页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
8XC251SB
HIGH-PERFORMANCE
CHMOS SINGLE-CHIP MICROCONTROLLER
Commercial
■ Binary-code Compatible with MCS® 51
■ User-selectable Configurations:
— External Wait State
— Address Range
Microcontrollers
■ Pin Compatible with 44-lead PLCC
— Page Mode
MCS 51 Microcontrollers
■ 32 Programmable I/O Lines
■ Register-based MCS 251 Architecture
— 40-byte Register File
■ Seven Maskable Interrupt Sources with
— Registers Accessible as Bytes, Words,
and Double Words
Four Programmable Priority Levels
■ Three Flexible 16-bit Timer/counters
■ Hardware Watchdog Timer
■ Enriched Instruction Set
— 16-bit and 32-bit Arithmetic and Logic
Instructions
■ Programmable Counter Array
— High-speed Output
— Compare and Conditional Jump
Instructions
— Expanded Set of Move Instructions
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
■ Linear Addressing
■ Programmable Serial I/O Port
— Framing Error Detection
■ 128-Kbyte External Code/Data Memory
Space
— Automatic Address Recognition
■ 16-Kbyte On-chip OTPROM/ROM
■ Power-saving Idle and Powerdown
(Optional device without ROM available)
Modes
■ 16-bit Internal Code Fetch
■ 64-Kbyte Extended Stack Space
■ 1-Kbyte On-chip Data RAM
■ High-performance CHMOS Technology
■ 0–16 MHz Operation
■ Complete System Development Support
— Compatible with Existing Tools
— New Tools Available: Compiler,
Assembler, Debugger, ICE
■ 8-bit, 2-clock External Code Fetch in
Page Mode
■ Instruction Pipeline
A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SB is binary-code compatible with
MCS 51 microcontrollers and pin compatible with 44-lead PLCC MCS 51 microcontrollers. MCS 251 micro-
controllers feature an enriched instruction set, linear addressing, and efficient C-language support. The
8XC251SB has 1 Kbyte of on-chip RAM and is available with 16 Kbytes of on-chip OTPROM (87C251SB),
with 16 Kbytes of ROM (83C251SB), or without ROM (80C251SB). A variety of features can be selected by
user-programmed OTPROM configuration (87C251SB) or factory-programmed ROM configuration
(83C251SB).
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringe-
ment of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such
products. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
September 1995
Order Number: 272616-003
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
System Bus and I/O Ports
Peripheral Signals and I/O Ports
P0.7:0
P1.7:0
P2.7:0
P3.7:0
Data RAM
(1 Kbyte)
Code
OTPROM/ROM
(16 Kbytes)
Port 0
Drivers
Port 2
Drivers
Port 1
Drivers
Port 3
Drivers
Memory Data (16)
Watchdog
Timer
Memory Address (16)
Peripheral
Interface
Bus Interface
Timer/
Counters
Code Bus (16)
Code Address (24)
Interrupt
Handler
Instruction Sequencer
PCA
SRC1 (8)
SRC2 (8)
Serial I/O
Clock
&
Reset
Data
Memory
Interface
Register
File
ALU
Peripherals
DST (16)
®
MCS 251 Microcontroller Core
Clock & Reset
A4109-02
Figure 1. 8XC251SB Block Diagram
2
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
COMMERCIAL TEMPERATURE RANGE
PROCESS INFORMATION
With the commercial (standard) temperature option,
the device operates over the temperature range 0°C
to +70°C.
This device is manufactured on a complimentary
high performance metal-oxide semiconductor
(CHMOS) process. Additional process and
reliability information is available in Intel’s
Components Quality and Reliability Handbook
(order number 210997).
PROLIFERATION OPTIONS
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
change dependent upon operating conditions and
application requirements. The Intel Packaging
Handbook (order number 240800) describes Intel’s
thermal impedance test methodology.
Table 1. Proliferation Options
8XC251SB (1)
8XC251SB-16 (1)
(0 – 12 MHz; 5 V ±10%) (0 – 16 MHz; 5 V ±10%)
80C251SB (2)
83C251SB
87C251SB
NOTES:
80C251SB-16 (3)
83C251SB-16
87C251SB-16
Table 2. Thermal Characteristics
Package Type
θ
θ
JC
1. The 8XC251SB and 8XC251SB-16 are
binary-code compatible with MCS 51 micro-
controllers.
JA
44-pin PLCC
46°C/W
16°C/W
2. Configurations available for 80C251SB:
a. Nonpage mode and no wait states
(Table 13)
b. User-defined configurations
3. Configurations available for 80C251SB-16:
a. Nonpage mode and one wait state
(Table 13)
b. User-defined configurations
NOTE:
Data for the 8XC251SB also applies to the
8XC251SB-16 unless otherwise noted.
3
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
X
XX
8
X
X
XXXXX XX
A2815-01
Figure 2. The 8XC251SB Family Nomenclature
Table 3. Description of Product Nomenclature
Parameter
Options
Description
Temperature and Burn-in Options
no mark
Commercial operating temperature range (0°C to 70°C)
with Intel standard burn-in.
Packaging Options
N
Plastic Leaded Chip Carrier (PLCC)
Program Memory Options
0
Without ROM
With ROM
3
7
With OTPROM
CHMOS
Process Information
Product Family
Device Speed
C
251SB
no mark
-16
Advanced 8-bit control architecture
12 MHz
16 MHz
4
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Table 4. 8XC251SB Memory Map
Address
(Note 1, 2)
Description
Notes
FF:FFFFH
FF:4000H
External Memory
3
FF:3FFFH
87C251SB/83C251SB: 16-Kbyte Internal OTPROM/ROM or External Memory, as
determined by EA# pin (Table 7)
3, 4, 5
FF:0000H
80C251SB: External Memory
FE:FFFFH
FE:0000H
External Memory
3
6
3
FD FFFFH
02:0000H
Reserved
01:FFFFH
01:0000H
External Memory
00:FFFFH
00:E000H
87C251SB/83C251SB: External Memory or redirected to OTPROM/ROM
80C251SB: External Memory
5, 7
00:DFFFH
00:0420H
External Memory
7
7
8
9
00:041FH
00:0080H
On-chip RAM
00:007FH
00:0020H
On-chip RAM
00:001FH
00:0000H
Storage for R0–R7 of Register File
NOTES:
1. Only 16/17 address lines are bonded out (A15:0 or A16:0 as selected during chip configuration).
2. The special function registers (SFRs) and the register file have separate address spaces.
3. Data is accessible by indirect addressing only.
4. The 8XC251SB resets to location FF:0000H.
5. The 87C251SB/83C251SB can be configured so that locations FF:2000H–FF:3FFFH in internal
OTPROM/ROM are also mapped to locations 00:E000H–00:FFFFH. In this case, if EA# = 1, a data
read to 00:E000H–00:FFFFH is redirected to internal OTPROM/ROM (see bit 1 in CONFIG0).
6. This reserved area of memory is unavailable for use. Reading a location in this area returns an
unspecified value. A write to this area does execute, but nothing is actually written.
7. Data is accessible by direct and indirect addressing.
8. Data is accessible by direct, indirect, and bit addressing.
9. Data is accessible by direct, indirect, and register addressing.
5
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
P1.5 / CEX2
P1.6 / CEX3
P1.7 / CEX4
RST
7
8
9
39
38
37
36
35
34
33
32
31
30
29
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
10
11
12
13
14
15
16
17
8XC251SB
P3.0 / RXD
EA# / V
PP
V
V
CC2
SS2
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
ALE / PROG#
PSEN#
A15 / P2.7
A14 / P2.6
A13 / P2.5
View of component as
mounted on PC board
P3.5 / T1
A4108-04
Figure 3. 8XC251SB 44 Lead PLCC Package
6
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Table 5. 44-pin PLCC Pin Assignment
Pin
1
Name
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
VSS1
VSS2
2
T2/P1.0
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
A12/P2.4
A13/P2.5
A14/P2.6
A15/P2.7
PSEN#
3
T2EX/P1.1
ECI/P1.2
CEX0/P1.3
CEX1/P1.4
CEX2/P1.5
CEX3/P1.6
CEX4/P1.7
RST
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RXD/P3.0
VCC2
ALE/PROG#
VSS2
TXD/P3.1
INT0#/P3.2
INT1#/P3.3
T0/P3.4
EA#/VPP
AD7/P0.7
AD6/P0.6
AD5/P0.5
AD4/P0.4
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
VCC
T1/P3.5
WR#/P3.6
RD#/P3.7
XTAL2
XTAL1
VSS
7
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Table 6. 44-pin PLCC Pin Assignment Arranged by Functional Categories
Address & Data
Name Pin
AD0/P0.0
Input/Output
Name
Pin
2
43
42
41
40
39
38
37
36
24
25
26
27
28
29
30
31
T2/P1.0
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
A8/P2.0
T2EX/P1.1
ECI/P1.2
3
4
CEX0/P1.3
CEX1/P1.4
CEX2/P1.5
CEX3/P1.6
CEX4/P1.7
RXD/P3.0
TXD/P3.1
T0/P3.4
5
6
7
8
9
11
13
16
17
A9/P2.1
A10/P2.2
A11/P2.3
A12/P2.4
A13/P2.5
A14/P2.6
A15/P2.7
T1/P3.5
Power & Ground
Name
VCC
Pin
44
VCC2
12
Processor Control
Name
VSS
22
Pin
14
15
35
10
21
20
VSS1
1
INT0#/P3.2
INT1#/P3.3
EA#/VPP
RST
VSS2
23, 34
Bus Control & Status
Name Pin
WR#/P3.6 18
XTAL1
XTAL2
RD#/P3.7
ALE/PROG#
PSEN#
19
33
32
8
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
PIN DESCRIPTIONS
Table 7. Pin Descriptions
Signal
Type
Multiplexed
Description
With
Name
A16
O
O
Address Line 16. See RD#.
N.A.
A15:8†
AD7:0†
Address Lines. Upper address lines for the external bus.
P2.7:0
P0.7:0
I/O
Address/Data Lines. Multiplexed lower address lines and data lines
for external memory.
ALE
O
Address Latch Enable. ALE signals the start of an external bus cycle PROG#
and indicates that valid address information is available on lines A15:8
and AD7:0. An external latch can use ALE to demultiplex the address
from the address/data bus.
CEX4:0
EA#
I/O
I
Programmable Counter Array (PCA) Input/Output Pins. These are P1.7:3
input signals for the PCA capture mode and output signals for the PCA
compare mode and PCA PWM mode.
External Access. Directs program memory accesses to on-chip or off- VPP
chip code memory. For EA# = 0, all program memory accesses are off-
chip. For EA# = 1, an access is to on-chip OTPROM/ROM if the
address is within the range of the on-chip OTPROM/ROM; otherwise
the access is off-chip. The value of EA# is latched at reset. For devices
without ROM on-chip, EA# must be strapped to ground.
ECI
I
I
PCA External Clock Input. External clock input to the 16-bit PCA
timer.
P1.2
INT1:0#
External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON P3.3:2
register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by
a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are
set by a low level on INT1:0#.
P0.7:0
I/O
I/O
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
AD7:0
P1.0
Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.
T2
P1.1
P1.2
T2EX
ECI
P1.7:3
CEX4:0
P2.7:0
I/O
I/O
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.
Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.
A15:8
P3.0
P3.1
RXD
TXD
P3.3:2
P3.5:4
P3.6
INT1:0#
T1:0
WR#
RD#
P3.7
PROG#
I
Programming Pulse. The programming pulse is applied to this pin for ALE
programming the on-chip OTPROM.
NOTE:
†The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration
(compatible with 44-lead PLCC MCS 51 microcontrollers). If the chip is configured for page-mode
operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
9
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Table 7. Pin Descriptions (Continued)
Signal
Multiplexed
With
Type
Description
Name
PSEN#
O
Program Store Enable. Read signal output. This output is asserted
for a memory address range that depends on bits RD0 and RD1 in
configuration byte CONFIG1 (see also RD#):
—
RD1 RD0 Address Range for Assertion
0
0
1
1
0
1
0
1
Reserved
All addresses
All addresses
All addresses ≥ 80:0000H
RD#
O
Read or 17th Address Bit (A16). Read signal output to external data P3.7
memory or 17th external address bit (A16), depending on the values of
bits RD0 and RD1 in configuration byte CONFIG1. (See also PSEN#):
RD1 RD0 Function
0
0
1
1
0
1
0
1
Reserved
The pin functions as A16 only.
The pin functions as P3.7 only.
RD#: asserted for reads at all addresses ≤ 7F:FFFFH
RST
I
Reset. Reset input to the chip. Holding this pin high for 64 oscillator
—
periods while the oscillator is running resets the device. The port pins
are driven to their reset conditions when a voltage greater than V is
IH1
applied, whether or not the oscillator is running. This pin has an
internal pulldown resistor, which allows the device to be reset by
connecting a capacitor between this pin and V
.
CC
Asserting RST when the chip is in idle mode or powerdown mode
returns the chip to normal operation.
RXD
T1:0
T2
I/O
I
Receive Serial Data. RXD sends and receives data in serial I/O mode P3.0
0 and receives data in serial I/O modes 1, 2, and 3.
Timer 1:0 External Clock Inputs. When timer 1:0 operates as a
P3.5:4
counter, a falling edge on the T1:0 pin increments the count.
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal P1.0
is the external clock input. For the clock-out mode, it is the timer 2
clock output.
T2EX
TXD
I
Timer 2 External Input. In timer 2 capture mode, a falling edge
initiates a capture of the timer 2 registers. In auto-reload mode, a
falling edge causes the timer 2 registers to be reloaded. In the up-
down counter mode, this signal determines the count direction: 1 = up,
0 = down.
P1.1
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 P3.1
and transmits serial data in serial I/O modes 1, 2, and 3.
VCC
PWR Supply Voltage. Connect this pin to the +5V supply voltage.
—
NOTE:
†The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration
(compatible with 44-lead PLCC MCS 51 microcontrollers). If the chip is configured for page-mode
operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
10
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Table 7. Pin Descriptions (Continued)
Signal
Name
Multiplexed
Type
Description
With
VCC2
PWR Secondary Supply Voltage 2. This supply voltage connection is
provided to reduce power supply noise. Connection of this pin to the
+5V supply voltage is recommended. However, when using the
8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can be
unconnected without loss of compatibility.
—
VPP
I
Programming Supply Voltage. The programming supply voltage is
EA#
applied to this pin for programming the on-chip OTPROM.
VSS
GND Circuit Ground. Connect this pin to ground.
—
—
VSS1
GND Secondary Ground. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground
is recommended. However, when using the 8XC251SB as a pin-for-pin
replacement for the 8XC51BH, VSS1 can be unconnected without loss
of compatibility.
VSS2
GND Secondary Ground 2. This ground is provided to reduce ground
bounce and improve power supply bypassing. Connection of this pin to
ground is recommended. However, when using the 8XC251SB as a
pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected
without loss of compatibility.
—
WR#
O
Write. Write signal output to external memory. For configuration bits
RD1 = RD0 = 1, WR# is strobed only for writes to locations 00:0000H–
01:FFFFH. For other values of RD1:0, WR# is strobed for writes to all
memory locations.
P3.6
—
XTAL1
I
Input to the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, its output is connected to this pin. XTAL1
is the clock source for internal timing.
XTAL2
O
Output of the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, leave XTAL2 unconnected.
—
NOTE:
†The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration
(compatible with 44-lead PLCC MCS 51 microcontrollers). If the chip is configured for page-mode
operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
11
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS†
NOTICE: This datasheet contains information on prod-
ucts in the sampling and initial production phases of
development. It is valid for the devices indicated in the
revision history. The specifications are subject to change
without notice. Verify with your local Intel Sales office that
you have the latest datasheet before finalizing a design.
Ambient Temperature Under Bias ............... 0°C to +70°C
Storage Temperature .............................-65°C to +150°C
Voltage on EA#/VPP Pin to VSS ................. 0 V to +13.0 V
Voltage on any other Pin to VSS .............. -0.5 V to +6.5 V
IOL Per I/O Pin .........................................................15 mA
Power Dissipation ................................................... 1.5 W
†WARNING: Stressing the device beyond the “Absolute Maximum
Ratings” may cause permanent damage. These are stress ratings
only. Operation beyond the “Operating Conditions” is not recom-
mended and extended exposure beyond the “Operating Conditions”
may affect device reliability.
NOTE:
Maximum power dissipation is based on
package heat-transfer limitations, not
device power consumption.
OPERATING CONDITIONS†
TA (Ambient Temperature Under Bias):
Commercial ............................................. 0°C to +70°C
V
CC (Digital Supply Voltage) ...................... 4.5 V to 5.5 V
VSS ............................................................................. 0 V
12
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
DC Characteristics
Parameter values apply to all devices unless otherwise indicated.
Table 8. DC Characteristics at VCC = 4.5 – 5.5 V
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
VIL
Input Low Voltage
(except EA#)
-0.5
0.2VCC – 0.1
V
VIL1
VIH
Input Low Voltage
(EA#)
0
0.2VCC – 0.3
VCC + 0.5
V
V
V
V
Input High Voltage
(except XTAL1, RST)
0.2VCC + 0.9
0.7VCC
VIH1
VOL
Input High Voltage
(XTAL1, RST)
VCC + 0.5
Output Low Voltage
(Port 1, 2, 3)
0.3
0.45
1.0
I
OL = 100 µA
OL = 1.6 mA
OL = 3.5 mA
I
I
(Note 1, Note 2)
IOL = 200 µA
VOL1
Output Low Voltage
(Port 0, ALE, PSEN#)
0.3
0.45
1.0
V
V
I
I
OL = 3.2 mA
OL = 7.0 mA
(Note 1, Note 2)
VOH
Output High Voltage
(Port 1, 2, 3, ALE,
PSEN#)
V
CC – 0.3
I
I
I
OH = -10 µA
OH = -30 µA
OH = -60 µA
VCC – 0.7
VCC – 1.5
(Note 3)
NOTES:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
port 0
ports 1–3
26 mA
15 mA
Maximum Total IOL for All
Output Pins
71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into
the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive
loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to
qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
4. Typical values are obtained using VCC = 5.0, TA = 25° C and are not guaranteed.
13
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Table 8. DC Characteristics at VCC = 4.5 – 5.5 V (Continued)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
VOH1
Output High Voltage
(Port 0 in External
Address)
V
CC – 0.3
V
I
OH = -200 µA
OH = -3.2 mA
OH = -7.0 mA
VCC – 0.7
VCC – 1.5
I
I
VOH2
Output High Voltage
(Port 2 in External
Address during Page
Mode)
V
CC – 0.3
V
I
I
I
OH = -200 µA
OH = -3.2 mA
OH = -7.0 mA
VCC – 0.7
VCC – 1.5
IIL
ILI
ITL
Logical 0 Input
Current (Port 1, 2, 3)
-50
µA
µA
µA
VIN = 0.45 V
0.45 < VIN < VCC
VIN = 2.0 V
Input Leakage
Current (Port 0)
+/-10
-650
Logical 1–to–0
Transition Current
(Port 1, 2, 3)
RRST
CIO
RST Pulldown
Resistor
40
225
kΩ
Pin Capacitance
10
pF
FOSC = 16 MHz
(Note 4)
T
= 25 °C
A
IPD
Powerdown Current
Idle Mode Current
Operating Current
10
75
20
80
µA
mA
mA
(Note 4)
IDL
10
FOSC = 16 MHz
FOSC = 16 MHz
(Note 4)
ICC
45
(Note 4)
NOTES:
1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
port 0
ports 1–3
26 mA
15 mA
Maximum Total IOL for All
Output Pins
71 mA
If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into
the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive
loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to
qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-
tion when the address lines are stabilizing.
4. Typical values are obtained using VCC = 5.0, TA = 25° C and are not guaranteed.
14
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
VCC
IPD
VCC
P0
VCC
EA#
RST
8XC251SB
(NC)
XTAL2
XTAL1
VSS
All other pins are unconnected.
A4150-03
Figure 4. I Test Condition, Powerdown Mode, VCC = 2.0 – 5.5V.
PD
15
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
table, Notes 3 and 5 mark parameters affected by an
AC Characteristics
ALE wait state, and Notes 4 and 5 mark parameters
affected by a PSEN#/RD#/WR# wait state.
Table
9 lists AC timing parameters for the
8XC251SB and 8XC251SB-16 with no wait states.
External wait states can be added by extending
PSEN#/RD#/WR# and/or by extending ALE. In the
Figures 5–10 show the bus cycles with the timing
parameters.
Table 9. AC Characteristics (Capacitive Loading = 50 pF)
@ Max F
Min
(1)
F
Variable
osc
osc
Symbol
Parameter
XTAL1 Frequency
8XC251SB
8XC251SB-16
Units
Max
N/A
Min
Max
FOSC
N/A
MHz
0
0
12
16
TOSC
TLHLL
TAVLL
TLLAX
1/FOSC
N/A
N/A
ns
83.3
62.5
8XC251SB
8XC251SB-16
ALE Pulse Width
8XC251SB
T
T
T
T
T
T
OSC – 10
OSC – 20
OSC – 20
OSC – 18
OSC – 18
OSC – 10
ns
73.3
52.5
(3)
8XC251SB-16
Address Valid to ALE Low
8XC251SB
ns
63.3
42.5
(3)
8XC251SB-16
Address Hold after ALE Low
8XC251SB
ns
63.3
42.5
8XC251SB-16
T
RLRH (2) RD# or PSEN# Pulse Width
ns
8XC251SB
8XC251SB-16
65.3
44.5
(4)
TWLWH
WR# Pulse Width
8XC251SB
ns
65.3
44.5
(4)
8XC251SB-16
TLLRL (2) ALE Low to RD# or PSEN# Low
8XC251SB
ns
73.3
52.5
8XC251SB-16
TLHAX
ALE High to Address Hold
8XC251SB
2TOSC – 20
ns
146.6
105
(3)
8XC251SB-16
TRLDV (2) RD# or PSEN# Low to Valid Data/Instruct. In
TOSC – 50
ns
8XC251SB
8XC251SB-16
33.3
12.5
(4)
NOTES:
1. 12 MHz for 8XC251SB and 16 MHz for 8XC251SB-16.
2. Specifications for PSEN# are identical to those for RD#.
3. If a wait state is added by extending ALE, add 2TOSC
.
4. If a wait state is added by extending RD#/PSEN#/WR#, add 2TOSC
.
5. If wait states are added as described in both Note 4 and Note 3, add a total of 4TOSC
.
6. “Typical” specifications are untested and not guaranteed.
16
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Table 9. AC Characteristics (Capacitive Loading = 50 pF) (Continued)
@ Max F
(1)
F
Variable
osc
osc
Symbol
Parameter
Units
Min
Max
Min
Max
TRHDX (2) Data/Instruct. Hold After RD# or PSEN# High
TRLAZ (2) RD#/PSEN# Low to Address Float
0
0
ns
ns
Typ.=0 2
(6)
Typ. = 0
(6)
2
TRHDZ (2) Data/Instruct. Float After RD# or PSEN# High
T
OSC – 20
ns
ns
8XC251SB
8XC251SB-16
63.3
42.5
TRHLH1
RD#/PSEN# High to ALE High (Instruction)
TOSC – 15
8XC251SB
8XC251SB-16
68.3
47.5
TRHLH2
RD#/PSEN# High to ALE High (Data)
3T
– 15
ns
ns
osc
8XC251SB
8XC251SB-16
234.9
172.5
TWHLH
TAVDV1
TAVDV2
TAVDV3
WR# High to ALE High
8XC251SB
3TOSC – 15
234.9
172.5
8XC251SB-16
Address (P0) Valid to Valid Data/Instruction In
8XC251SB (3)
3TOSC – 60
4TOSC – 60
2TOSC – 60
ns
189.9
127.5
(3,4,5)
8XC251SB-16 (3)
Address (P2) Valid to Valid Data/Instruction In
8XC251SB (3)
ns
273.2
190
(3,4,5)
8XC251SB-16 (3)
Address (P0) Valid to Valid Instruction In
8XC251SB
ns
106.6
65
8XC251SB-16
T
AVRL (2) Address Valid to RD#/PSEN# Low
2TOSC– 24
2TOSC – 24
3TOSC – 30
ns
8XC251SB
8XC251SB-16
142.6
101
(3)
TAVWL1
TAVWL2
NOTES:
Address (P0) Valid to WR# Low
8XC251SB
ns
142.6
101
(3)
8XC251SB-16
Address (P2) Valid to WR# Low
8XC251SB
ns
219.9
157.5
(3)
8XC251SB-16
1. 12 MHz for 8XC251SB and 16 MHz for 8XC251SB-16.
2. Specifications for PSEN# are identical to those for RD#.
3. If a wait state is added by extending ALE, add 2TOSC
.
4. If a wait state is added by extending RD#/PSEN#/WR#, add 2TOSC
.
5. If wait states are added as described in both Note 4 and Note 3, add a total of 4TOSC
6. “Typical” specifications are untested and not guaranteed.
.
17
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Table 9. AC Characteristics (Capacitive Loading = 50 pF) (Continued)
@ Max F
Min
(1)
F
Variable
osc
osc
Symbol
Parameter
Units
Max
Min
Max
TWHQX
Data Hold after WR# High
8XC251SB
T
OSC – 20
OSC – 25
ns
63.3
42.5
8XC251SB-16
TQVWH
TWHAX
NOTES:
Data Valid to WR# High
8XC251SB
T
ns
58.3
37.5
(4)
8XC251SB-16
WR# High to Address Hold
8XC251SB
2TOSC – 20
ns
146.6
105
8XC251SB-16
1. 12 MHz for 8XC251SB and 16 MHz for 8XC251SB-16.
2. Specifications for PSEN# are identical to those for RD#.
3. If a wait state is added by extending ALE, add 2TOSC
.
4. If a wait state is added by extending RD#/PSEN#/WR#, add 2TOSC
.
5. If wait states are added as described in both Note 4 and Note 3, add a total of 4TOSC
.
6. “Typical” specifications are untested and not guaranteed.
18
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
SYSTEM BUS TIMINGS
T
OSC
XTAL1
ALE
†
T
LHLL
†
†
T
T
RLRH
LLRL
T
RHLH2
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
LHAX
T
T
RHDZ
†
T
AVLL
T
LLAX
RHDX
D7:0
P0
A7:0
†
Data In
T
AVRL
†
†
T
AVDV1
T
AVDV2
P2
A15:8
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4178-01
Figure 5. External Read Data Bus Cycle in Nonpage Mode
19
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
†
T
T
T
RHLH1
LLRL
RLRH
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
LHAX
T
RHDZ
†
T
AVLL
T
T
LLAX
RHDX
P0
A7:0
D7:0
†
Instruction In
T
AVRL
†
†
T
AVDV1
T
AVDV2
P2
A15:8
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4180-01
Figure 6. External Instruction Bus Cycle in Nonpage Mode
20
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
WLWH
T
WHLH
WR#
†
T
LHAX
†
T
QVWH
T
T
AVLL
LLAX
T
WHQX
P0
A7:0
D7:0
†
Data Out
T
AVWL1
†
T
T
AVWL2
WHAX
P2
A15:8
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4179-01
Figure 7. External Write Data Bus Cycle in Nonpage Mode
21
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
†
T
T
RLRH
LLRL
T
RHLH2
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
LHAX
T
T
RHDZ
†
T
AVLL
T
LLAX
RHDX
D7:0
P2
A15:8
†
Data In
T
AVRL
†
†
T
AVDV1
T
AVDV2
P0
A7:0
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4181-01
Figure 8. External Read Data Bus Cycle in Page Mode
22
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
T
WLWH
T
WHLH
WR#
†
T
LHAX
†
T
T
QVWH
AVLL
T
LLAX
T
WHQX
P2
A15:8
D7:0
†
Data Out
T
AVWL1
†
T
T
AVWL2
WHAX
P0
A7:0
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A4182-01
Figure 9. External Write Data Bus Cycle in Page Mode
23
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
T
OSC
XTAL1
ALE
†
T
LHLL
†
†
T
T
RLRH
T
LLRL
RHLH1
RD#/PSEN#
†
T
RLDV
T
RLAZ
†
T
LHAX
T
RHDZ
†
T
AVLL
T
T
LLAX
RHDX
P2
A15:8
D7:0
D7:0
†
Instruction In
Instruction In
T
AVRL
†
†
T
T
AVDV1
AVDV3
T
AVDV2
P0
A7:0
A7:0
††
††
Page Miss
Page Hit
†
The value of this parameter depends on wait states. See the table of AC characteristics.
A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one
state (2TOSC); a page miss requires two states (4TOSC).
††
A4183-01
Figure 10. External Instruction Bus Cycle in Page Mode
24
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
AC Characteristics — Serial Port, Shift Register Mode
Table 10. Serial Port Timing — Shift Register Mode
Symbol
TXLXL
Parameter
Min
12TOSC
Max
Units
ns
Serial Port Clock Cycle Time
TQVSH
TXHQX
TXHDX
TXHDV
Output Data Setup to Clock Rising Edge
Output Data hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
10TOSC – 133
2TOSC – 117
0
ns
ns
ns
10TOSC – 133
ns
T
XLXL
TXD
T
XHQX
†
†
Set TI
T
QVXH
RXD
(Out)
0
1
2
7
4
6
3
5
†
T
AV
T
T
XHDV
XHDX
Set RI
RXD
(In)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
†
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
A2592-02
Figure 11. Serial Port Waveform — Shift Register Mode
25
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
External Clock Drive
Table 11. External Clock Drive
Symbol
1/TCLCL
TCHCX
Parameter
Oscillator Frequency (FOSC
High Time
Min
Max
Units
MHz
ns
)
16
20
20
TCLCX
Low Time
ns
TCLCH
Rise Time
10
10
ns
TCHCL
Fall Time
ns
TCLCH
TCHCX
VCC – 0.5
0.45 V
0.7 VCC
TCLCX
0.2 VCC – 0.1
TCHCL
TCLCL
A4119-01
Figure 12. External Clock Drive Waveforms
Outputs
Inputs
VCC – 0.5
0.45 V
0.2 VCC + 0.9
0.2 VCC – 0.1
VIH MIN
VOL MAX
AC inputs during testing are driven at VCC – 0.5V for a logic 1
and 0.45 V for a logic 0. Timing measurements are made at
a min of VIH for a logic 1 and VOL for a logic 0.
A4118-01
Figure 13. AC Testing Input, Output Waveforms
26
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
VLOAD + 0.1 V
VLOAD
VOH – 0.1 V
Timing Reference
Points
VOL + 0.1 V
VLOAD – 0.1 V
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loading VOH/VOL level occurs
with IOL/IOH = ± 20 mA.
A4117-01
Figure 14. Float Waveforms
Configuration bytes CONFIG0 and CONFIG1
(Figures 16 and 17) define the configuration bits.
Table 13 lists values of configuration bits for the
80C251SB.
PROGRAMMING AND VERIFYING
NONVOLATILE MEMORY
The 8XC251SB has several areas of nonvolatile
memory that can be programmed and/or verified:
on-chip code memory (16 Kbytes), configuration
bytes (2 bytes), lock bits (3 bits), encryption array
(128 bytes), and signature bytes (3 bytes). The
8XC251SB User’s Manual (Order Number: 272617)
provides procedures for programming and verifying
the nonvolatile memory.
Figure shows the waveforms for the programming
and verification cycles, and Table 13 lists the timing
specifications. The signature bytes of the
83C251SB
and
87C251SB
are
factory
programmed. Table 14 lists the addresses and the
contents of the signature bytes.
NOTE
Figure 15 shows the setup for programming and/or
verifying the nonvolatile memory. Table 12 lists the
programming and verification operations and
indicates which operations apply to the three
versions of the 8XC251SB. It also specifies the
signals on the programming input (PROG#) and the
ports. The OTPROM/ROM mode (port 0) specifies
the operation (program or verify) and the base
address of the memory area. The addresses (ports
1 and 3) are relative to the base address. (The on-
chip memory is at locations FF:0000H–FF:3FFFH of
the memory address space. The other areas of the
OTPROM/ROM are outside the memory address
space and are accessible only during programming
and verification.)
The VPP source in Figure 15 must be well
regulated and free of glitches. The volt-
age on the VPP pin must not exceed the
specified maximum, even under transient
conditions.
27
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
VCC
8XC251SB
VCC
P3
P1
A0 - A7
RST
Address
(16 Bits)
Data
(8 Bits)
P2
A8 - A15
EA#/V
Programming
Signals
pp
XTAL1
ALE/PROG#
PSEN#
4 MHz
to
6 MHz
XTAL2
VSS
Program/Verify Mode
(8 Bits)
P0
A4122-01
Figure 15. Setup for Programming and Verifying Nonvolatile Memory
28
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Table 12. Programming and Verification Modes
8XC251SB
Addresses
Mode
PROG#
P0
P2
Notes
P1 (high), P3 (low)
X = 7 X = 3 X = 0
Program on-chip code
memory
Y
5 Pulses
68H Data
28H Data
69H Data
29H Data
0000H–3FFFH
1
Verify on-chip code
memory
Y
Y
Y
Y
High
5 Pulses
High
0000H–3FFFH
0080H–0083H
0080H–0083H
Program configuration
bytes
1, 2
Verify configuration
bytes
Y
Y
Y
Y
Program lock bits
Verify lock bits
Y
Y
Y
25 Pulses 6BH
High 2BH Data
25 Pulses 6CH Data
XX
0001H–0003H
0000H
1, 3
4
Program encryption
array
0000H–007FH
1
Verify signature bytes
Y
High
29H Data
0030H, 0031H,
0060H
NOTES:
1. The PROG# pulse waveform is shown in Figure .
2. The 8XC251SB uses only 2 bytes: 0080H and 0081H.
3. When programming the lock bits, the data bits on port 2 are don’t care. Identify the lock bits with the
address as follows: LB3 - 0003H, LB2 - 0002H, LB1 - 0001H
4. The three lock bits are verified in a single operation. The states of the lock bits appear simultaneously
at port 2 as follows: LB3 - P2.3, LB2 - P2.2. LB1 - P2.1. High = programmed.
29
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
CONFIG0
7
0
—
—
WSA
XALE
RD1
RD0
PAGE
SRC
Bit
Number
Bit
Mnemonic
Function
7:6
5
—
Reserved; set these bits when writing to CONFIG0.
Wait State A:
WSA
Clear this bit to generate one external wait state for memory regions 00:,
FE:, and FF:. Set this bit for no wait states for these regions.
4
XALE
Extend Ale:
If this bit is set, the time of the ALE pulse is TOSC. Clearing this bit
extends the time of the ALE pulse from TOSC to 3TOSC, which adds one
external wait state.
3:2
RD1, RD0
RD# and PSEN# Function Select:
RD1 RD0 RD# Range PSEN# Range Features
0
0
0
1
Reserved
RD# = A16 All addresses
Reserved
Reserved
128-Kbyte External
Address Space
1
1
0
1
P3.7 only
≤ 7F:FFFFH ≥ 80:0000H
All addresses
One additional port pin
Compatible with MCS 51
microcontrollers
1
0
PAGE
SRC
Page Mode Select:
Clear this bit for page-mode (A15:8/D7:0 on P2, and A7:0 on P0). Set
this bit for nonpage-mode (A15:8 on P2, and A7:0/D7:0 on P0
(compatible with 44-lead PLCC MCS 51 microcontrollers)).
Source Mode/Binary Mode Select:
Set this bit for source mode. Clear this bit for binary mode (binary-code
compatible with MCS 51 microcontrollers).
Figure 16. Configuration Byte 0
30
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
.
CONFIG1
7
0
—
—
—
INTR
WSB
—
—
EMAP
Bit
Number
Bit
Mnemonic
Function
7:5
4
—
Reserved; set these bits when writing to CONFIG1.
Interrupt Mode:
INTR
If this bit is set, interrupts push 4 bytes onto the stack (the 3 bytes of the
PC register and the PSW1 register). If this byte is clear, interrupts push 2
bytes onto the stack (the 2 lower bytes of the PC register).
3
WSB
Wait State B:
Clear this bit to generate one external wait state for memory region 01:.
Set this bit for no wait states for region 01:.
2:1
0
Reserved; set these bits when writing to CONFIG1.
EPROM MAP:
EMAP
Clearing this bit maps the upper 8 Kbytes of on-chip code memory
(FF:2000H–FF:3FFFH) to 00:E000H–00:FFFFH. If this bit is set, the
upper 8 Kbytes of on-chip code memory are mapped only to FF:2000H–
FF:3FFFH.
Figure 17. Configuration Byte 1
31
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Programming Cycle
Verification Cycle
P1, P3
P2
Address (16 Bits)
Address
T
AVQV
Data In (8 Bits)
T
Data Out
T
1
DVGL
GHDX
T
T
GHAX
AVGL
T
2
GHGL
3
PROG#
4
5
T
GHSL
T
GLGH
T
SHGL
12.75V
EA#/V
PP
5V
T
T
ELQV
EHQZ
T
EHSH
P0
Mode (8 Bits)
Mode
A4128-01
Figure 18. Timing for Programming and Verification of Nonvolatile Memory
32
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
Table 13. Nonvolatile Memory Programming and Verification Characteristics at
TA = 21 – 27 °C, VCC = 5 V, and VSS = 0 V
Symbol
VPP
Definition
Programming Supply Voltage
Programming Supply Current
Oscillator Frequency
Min
Max
13.0
75
Units
V
12.5
IPP
mA
FOSC
4.0
48TOSC
48TOSC
48TOSC
48TOSC
48TOSC
10
6.0
MHz
TAVGL
TGHAX
TDVGL
TGHDX
TEHSH
TSHGL
TGHSL
TGLGH
TAVQV
TELQV
TEHQZ
TGHGL
NOTE:
Address Setup to PROG# Low
Address Hold after PROG#
Data Setup to PROG# Low
Data Hold after PROG#
ENABLE High to VPP
VPP Setup to PROG# Low
VPP Hold after PROG#
µs
µs
µs
10
PROG# Width
90
110
Address to Data Valid
48TOSC
48TOSC
48TOSC
ENABLE Low to Data Valid
Data Float after ENABLE
PROG# High to PROG# Low
Notation for timing parameters:
0
10
µs
A = Address
Q = Data out
D = Data
E = Enable
V = Valid
G = PROG#
X = No Longer Valid
H = High
L = Low
S = Supply (VPP
)
Z = Floating
Table 14. Contents of the Signature Bytes
Address
Device
30H
89H
89H
31H
40H
40H
60H
7BH
FBH
83C251SB
87C251SB
33
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
DATASHEET REVISION HISTORY
The following differences exist between the -001 revision and this -002 revision of the 8XC251SB datasheet:
1. All EXPRESS temperature information is removed.
2. The term “EC1” (PCA External Clock Input) in Table 7 is correctly stated as “ECI”.
3. The description of bits RD0 and RD1 in configuration byte CONFIG1 (Table 7) correctly identifies states
for 00 and 11 and matches other datasheet and user manual information.
4. The WR# (Write) bus control signal description is added to Table 7.
5. The V
description is included in Table 8.
OH2
6. The RST (reset) resistor is correctly stated as a “pulldown“ in Table 8.
7. The I , I , I , T , T , T , T Maximum specifications are revised.
PD DL CC RLDV AVDV1 AVDV2 AVDV3
8. An I test condition replaces the I test condition in Figure 4 and its caption.
PD
CC
9.
T
, T
, T
, T
T
Minumum specifications are revised.
RLRH WLWH LHAX AVRL, QVWH
10. T
11. T
12. T
13. T
, T
are deleted.
LHRL RHLH
, T
, T
are new.
LLRL RHLH1 RHLH2
is revised.
RLAZ
is revised.
AVWL1
14. All timing diagrams relative to the foregoing changes are redrawn.
15. The Serial Port Waveform — Shift Register Mode figure is redrawn to indicate Set TI and Set RI.
16. Table 13, “Configuration Bit Values for 80C251SB and 80C251SB-16,” is deleted.
17. The 12 MHz test condition for C is now 16 MHz.
IO
34
ADVANCED INFORMATION
8XC251SB HIGH-PERFORMANCE CHMOS SINGLE-CHIP MICROCONTROLLER
FUNCTIONAL DEVIATIONS
This section describes the functional deviations associated with the 8XC251SB -002 datasheet.
1. Certain instructions (listed below) result in register values incorrectly affecting the Negative Flag (N) of
PSW1. These register values should set or clear the Negative Flag based on the value of result bit 15. The
8XC251SB ALU currently sets and clears the Negative Flag based on result bit seven when using these
specific instructions. Follow affected instructions with an ANL WRj,WRj operation. This forces the ALU
Negative Flag to operate on the value of result bit 15. The net impact is the additional ANL instruction time to
gain correct Negative Flag results. The following Instructions are affected by this deviation:
SRL WRj
SRA WRj
SLL WRj
INC WRj,#short
DEC WRj,#short
2. WSb in the CONFIG1 configuration register controls the number of wait states for MOVX instructions in
memory locations 01:0000H through 01:FFFFH. This includes both MOVX @DPTR as well as the MOVX @Ri
instruction. The device currently uses WSa in the CONFIG0 configuration register for the MOVX @Ri
instruction. If possible, configure both WSa and WSb to the same value. This results in identical wait-state
operation for both MOVX @DPTR and MOVX @Ri. If the two CONFIGx bits must be configured differently,
restrict the use of MOVX commands to the MOVX @DPTR format.
3. Use of EJMP instructions for extended jumps between 64-Kbyte regions do not result in the correct desti-
nation. Do not use the EJMP instruction.
4. Jump instructions with an address range of +127/-128 do not jump across the FF:XXXXH to FE:XXXXH 64-
Kbyte region boundary. Issuing a jump instruction within range of this boundary results in a destination within
the same FF:XXXXH region. Do not use jump instructions to cross this memory boundary. All +127/-128 jump
instructions issued across other 64-Kbyte region boundaries operate as described. The affected instructions
for the FF:XXXXH to FE:XXXXH region jump deviation are SJMP, CJNE, DJNZ, JB, JBC, JC, JE, JG, JLE,
JNB, JNC, JNE, JNZ, JSG, JSGE, JSL, JSLE, and JZ.
35
ADVANCED INFORMATION
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