NLXT361PEA2 [INTEL]
PCM Transceiver, 1-Func, PQCC28, PLASTIC, LCC-28;
| 型号： | NLXT361PEA2 |
| 厂家： | 
INTEL |
| 描述： | PCM Transceiver, 1-Func, PQCC28, PLASTIC, LCC-28 PC 电信 电信集成电路 |
| 文件： | 总55页 (文件大小：1015K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LXT361
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Datasheet
Applications
■ ISDN PRI
■ CSU/NTU interface to T1/E1 Service
■ Wireless Base Station interface
■ T1/E1 LAN/WAN bridge/routers
■ T1/E1 Mux; Channel Banks
■ Digital Loop Carrier - Subscriber Carrier
Systems
Product Features
■ Fully integrated transceiver for Long or
■ Four Line Build-Outs for T1 Long-Haul
Short-Haul T1, or E1 interfaces
applications from 0 dB to -22.5 dB
■ Crystal-less digital jitter attenuation
■ Transmit/receive performance monitors
with Driver Fail Monitor Open and Loss Of
Signal (lOS) outputs
—Select either transmit or receive path
—No crystal or high speed external clock
required
■ Selectable unipolar or bipolar data I/O and
B8ZS/HDB3 encoding/decoding
■ Meets or exceeds specifications in ANSI
T1.102, T1.403 and T1.408; ITU I.431,
G.703, G.736, G.775 and G.823; ETSI 300-
166 and 300-233; and AT&T Pub 62411
■ Supports 75 Ω (E1 coax), 100 Ω (T1
twisted-pair) and 120 Ω (E1 twisted-pair)
applications
■ Selectable receiver sensitivity – fully
restores the received signal after
transmission through a cable with
attenuation of either 0 to 26 dB, or 0 to
36 dB @ 772 kHz and 0 to 43 dB @
1024 kHz
■ Line attenuation indication output in 2.9 dB
steps
■ QRSS generator/detector for testing or
monitoring
■ Output short circuit current limit protection
■ Local, remote, and analog loopback, plus
in-band network loopback code generation
and detection
■ Intel/Motorola compatible 8-bit parallel
interface for microprocessor control
■ Available in 28-pin PLCC, 44-pin PQFP
and 44-pin LQFP packages
■ Five Pulse Equalization Settings for T1
Short-Haul applications
As of January 15, 2001, this document replaces the Level One document
Order Number: 249032-002
known as LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications. 04-Jan-2006
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT361 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Contents
1.0
2.0
General Description ..................................................................................................7
Pin Assignments and Signal Descriptions......................................................8
2.1
Mode Dependent Signals......................................................................................9
3.0
Functional Description...........................................................................................13
3.1
3.2
Initialization..........................................................................................................13
3.1.1 Reset Operation .....................................................................................13
Transmitter ..........................................................................................................13
3.2.1 Transmit Digital Data Interface...............................................................13
3.2.2 Transmit Monitoring................................................................................14
3.2.3 Transmit Drivers.....................................................................................14
3.2.4 Transmit Idle Mode.................................................................................14
3.2.5 Transmit Pulse Shape ............................................................................14
Receiver ..............................................................................................................15
3.3.1 Receive Equalizer ..................................................................................15
3.3.2 Receive Data Recovery..........................................................................15
3.3.3 Receiver Monitor Mode ..........................................................................15
Jitter Attenuation .................................................................................................16
Diagnostic Mode Operation.................................................................................16
3.5.1 Loopback Modes....................................................................................16
3.5.2 Internal Pattern Generation and Detection.............................................20
3.5.3 Error Insertion and Detection .................................................................22
3.5.4 Alarm Condition Monitoring....................................................................23
3.5.5 Other Diagnostic Reports.......................................................................24
Parallel Microprocessor Interface........................................................................24
3.6.1 Interrupt Handling...................................................................................24
3.3
3.4
3.5
3.6
4.0
5.0
Register Definitions.................................................................................................26
Application Information.........................................................................................32
5.1
5.2
5.3
Transmit Return Loss..........................................................................................32
Transformer Data ................................................................................................32
Application Circuit................................................................................................32
6.0
7.0
Test Specifications..................................................................................................36
Mechanical Specifications....................................................................................49
7.1
Top Label Markings.............................................................................................52
8.0
Product Ordering Information.............................................................................54
Datasheet
3
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figures
1
2
3
4
5
6
7
8
LXT361 Block Diagram .........................................................................................7
LXT361 Pin Assignments and Markings ............................................................... 8
50% Duty Cycle Coding ......................................................................................14
TAOS with LLOOP ..............................................................................................18
Local Loopback ...................................................................................................18
Analog Loopback ................................................................................................19
Remote Loopback...............................................................................................19
Dual Loopback ....................................................................................................20
TAOS Data Path .................................................................................................20
QRSS Mode ........................................................................................................21
Typical T1/E1 LXT361 Application ......................................................................35
2.048 MHz E1 Pulse (See Table 27)...................................................................39
1.544 MHz T1 Pulse (DS1 and DSX-1) (See Table 28) ......................................40
Transmit Clock Timing ........................................................................................41
Receive Clock Timing .........................................................................................42
LXT361 I/O Timing Diagram for Intel Address/Data Bus ....................................44
LXT361 I/O Timing Diagram for Motorola Address/Data Bus .............................45
Typical T1 Jitter Tolerance at 36 dB ...................................................................45
Typical E1 Jitter Tolerance at 43 dB ...................................................................46
Typical E1 Jitter Attenuation ...............................................................................47
\T1 Jitter Attenuation...........................................................................................48
Plastic Leaded Chip Carrier (PLCC) Package Specifications .............................49
Plastic Quad Flat Package (PQFP) Specifications .............................................50
Low-Profile Quad Flat Package (LQFP) Specifications ......................................51
Sample PLCC Package – Intel® DJLXT361LE Transceiver ...............................52
Sample Pb-Free (RoHS-Compliant) LQFP Package – Intel® WJLXT361LE Trans-
ceiver52
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Sample PLCC Package – Intel® NLXT361PE Transceiver.................................53
Sample Pb-Free (RoHS-Compliant) PLCC Package – Intel® EELXT361PE Trans-
ceiver53
29
Ordering Information Matrix – Sample ................................................................55
4
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Tables
1
2
3
4
5
6
7
8
9
LXT361 Clock and Data Pin Assignments by Mode1............................................9
LXT361 Processor Interface Pins..........................................................................9
LXT361 Signal Descriptions................................................................................10
Diagnostic Mode Summary .................................................................................16
Register Addresses.............................................................................................26
Register and Bit Summary ..................................................................................26
Control Register #1 Read/Write, Address (A7-A0) = x010000x ..........................27
Equalizer Control Bit Settings..............................................................................27
Control Register #2 Read/Write, Address (A7-A0) = x010001x ..........................28
10
11
12
13
14
15
16
17
18
Control Register #3 Read/Write, Address (A7-A0) = x010010x ..........................28
Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x....................29
Transition Status Register Read Only, Address (A7-A0) = x010100x.................29
Performance Status Register Read Only, Address (A7-A0) = x010101x............30
Equalizer Status Register Read Only, Address (A7-A0) = x010110x .................30
Control Register #4 Read/Write, Address (A7-A0) = x010111x ..........................30
E1 Transmit Return Loss Requirements .............................................................32
Transmit Return Loss (2.048 Mbit/s–Short-Haul)................................................32
Transmit Return Loss (2.048 Mbit/s–Long-Haul) High Return
Loss Configuration ..............................................................................................33
Transmit Return Loss (2.048 Mbit/s–Long-Haul) ................................................33
Transmit Return Loss (1.544 Mbit/s–Long- or Short-Haul) .................................33
Transformer Specifications for LXT361...............................................................33
Recommended Transformers for LXT361...........................................................34
Absolute Maximum Ratings.................................................................................36
Recommended Operating Conditions .................................................................36
Digital Characteristics..........................................................................................37
Analog Characteristics ........................................................................................37
2.048 MHz E1 Pulse Mask Specifications...........................................................39
1.544 MHz T1 Pulse Mask Corner Point Specifications......................................40
Master and Transmit Clock Timing Characteristics for T1 Operation
19
20
21
22
23
24
25
26
27
28
29
(See Figure 14) ...................................................................................................40
30
Master and Transmit Clock Timing Characteristics for E1 Operation
(See Figure 14) ...................................................................................................41
Receive Timing Characteristics for T1 Operation (See Figure 15)......................42
Receive Timing Characteristics for E1 Operation (See Figure 15) .....................42
LXT361 20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 16)..43
LXT361 16.78 MHz Motorola Bus Parallel I/O Timing Characteristics
31
32
33
34
(See Figure 17) ...................................................................................................44
35
Product Ordering Information..............................................................................54
Datasheet
5
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Revision History
Revision
Date
Description
002
04-Jan-2006
Modified Figure 1 “LXT351 Block Diagram” on page 7.
Added RoHS information as follows:
•
•
Section 6.1, “Top Label Markings” on page 47.
Section 7.0, “Product Ordering Information” on page 48.
001
Jan 2001
Initial release.
6
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
1.0
General Description
The LXT361 is a fully integrated, combination transceiver for T1/E1 ISDN Primary Rate Interface
(ISDN PRI) and general T1/E1 Long and Short Hual applications. The device operates over 0.63
mm (22 AWG) twisted-pair cables for 0 to 2 km (6 kft) and offers Line Build Outs (LBO) and pulse
equalization settings for all T1 and E1 Line Interface Unit (LIU) applications.
The LXT361 features an Intel or Motorola compatible parallel port for microprocessor control. The
LXT361 incorporates advanced crystal-less digital jitter attenuation in either the transmit or
receive data path starting at 3 Hz. B8ZS/HDB3 encoding/decoding and unipolar or bipolar data I/O
are available. The LIU provides loss of signal monitoring and a variety of diagnostic loopback
modes.
The parallel port is ideal for applications with multiple T1/E1 interfaces.
Figure 1. LXT361 Block Diagram
Datasheet
7
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.0
Pin Assignments and Signal Descriptions
Figure 2. LXT361 Pin Assignments and Markings
4
3
2
1
28 27
26
ALE / A S
25
24
23
22
21
20
19
A D2
A D1
A D0
G ND
5
6
R N EG / BP V
R PO S / R D ATA
R CLK
7
8
LXT361PE XX
XXXXXXXX
RD / DS
A D6
9
V C C
R R IN G
R TIP
10
11
BSMC
A D7
15
12
13
14
16 17 18
43
39
37
38 36 35 34
44
42
41
40
n/c
1
2
3
33
n/c
32
31
30
29
28
27
AD1
AD0
n/c
ALE / AS
RNEG / BPV
RPOS / RDATA
RCLK
4
LXT361LE XX
5
6
GND
n/c
XXXXXXXX
BSMC
n/c
VCC
n/c
7
8
RD / DS
n/c
26
25
24
AD6
RRING
RTIP
n/c
9
AD7
n/c
10
11
23
12 13 14 15 16 17 18 19 20 21 22
8
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
2.1
Mode Dependent Signals
As shown in Figure 2, the LXT361 has several pins that change function (and signal name)
according to the selected mode(s) of operation. These pins, associated signal names, and operating
modes are summarized in Table 1 and Table 2. LXT361 signals are described in Table 3.
Table 1. LXT361 Clock and Data Pin Assignments by Mode1
Pin #
PLCC
External Data Modes
QRSS Modes
Unipolar Mode
QFP
Bipolar Mode
Unipolar Mode
Bipolar Mode
1
2
39
41
42
43
3
MCLK
TCLK
3
TPOS
TNEG
RNEG
RPOS
TDATA
INSBPV
BPV
INSLER
INSBPV
4
6
RNEG
RPOS
BPV
7
4
RDATA
RDATA
8
5
RCLK
TTIP
13
16
19
20
15
19
24
25
TRING
RTIP
RRING
1. Data pins change based on whether external data or internal QRSS mode is active.
Table 2. LXT361 Processor Interface Pins
Pin #
PLCC
Address/Data Bus Type
Pin #
PLCC
Address/Data Bus Type
Intel Motorola
QFP
Intel
Motorola
QFP
5
2
ALE
RD
AS
DS
25
26
27
28
10
11
-
35
36
37
38
9
AD2
AD3
AD4
AD5
AD6
AD7
-
9
7
12
17
18
23
24
13
20
21
31
32
WR
R/W
CS
INT
AD0
AD1
10
-
Datasheet
9
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 3. LXT361 Signal Descriptions
Pin #
Symbol
I/O1
Description
PLCC
QFP
Master Clock. External, independent clock signal required to generate
internal clocks. For T1 applications, a 1.544 MHz clock is required; for E1,
a 2.048 MHz clock. MCLK must be jitter-free and have an accuracy better
than ± 50 ppm with a typical duty cycle of 50%. Upon Loss of Signal (LOS),
RCLK is derived from MCLK.
1
39
MCLK
TCLK
DI
DI
Transmit Clock. For T1 applications, a 1.544 MHz clock is required; for
E1, a 2.048 MHz clock. The transceiver samples TPOS and TNEG on the
falling edge of TCLK (or MCLK, if TCLK is not present).
2
41
BIPOLAR MODES:
Transmit – Positive and Negative. TPOS and TNEG are the positive and
negative sides of a bipolar input pair. Data to be transmitted onto the
twisted-pair line is input at these pins. TPOS/TNEG are sampled on the
falling edge of TCLK (or MCLK, if TCLK is not present).
UNIPOLAR MODES:
Transmit Data. TDATA carries unipolar data to be transmitted onto the
3
4
42
43
DI
DI
twisted-pair line and is sampled on the falling edge of TCLK.
TPOS/TDATA/
INSLER
Transmit Insert Logic Error. In QRSS mode, a Low-to-High transition on
INSLER inserts a logic error into the transmitted QRSS data pattern. The
error follows the data flow of the active loopback mode. The LXT361
samples this pin on the falling edge of TCLK (or MCLK, if TCLK is not
present).
TNEG/INSBPV
Transmit Insert Bipolar Violation. INSBPV is sampled on the falling edge
of TCLK (or MCLK, if TCLK is not present) to control Bipolar Violation
(BPV) insertions in the transmit data stream. A Low-to-High transition is
required to insert each BPV. In QRSS mode, the BPV is inserted into the
transmitted QRSS pattern.
Address Latch Enable. Connect to ALE signal of Intel microprocessor
Address Strobe Connect to AS signal of Motorola microprocessor.
5
2
ALE/AS
DI
Note that leaving this pin floating forces all output pins to a high impedance
state.
BIPOLAR MODES:
Receive – Negative and Positive. RPOS and RNEG are the positive and
negative sides of a bipolar output pair. Data recovered from the line
interface is output on these pins. A signal on RNEG corresponds to receipt
of a negative pulse on RTIP/RRING. A signal on RPOS corresponds to
receipt of a positive pulse on RTIP/RRING. RNEG/RPOS are Non-Return-
to-Zero (NRZ). The PLCKE bit in register CR3 selects the RCLK clock
edge when RPOS /RNEG are stable and valid.
6
7
3
4
RNEG/BPV
DO
DO
RPOS/RDATA
UNIPOLAR MODES:
Receive Bipolar Violation. BPV goes High to indicate detection of a
bipolar violation from the line. This is an NRZ output, valid on the rising
edge of RCLK.
Receive Data. RDATA is the unipolar NRZ output of data recovered from
the line interface. The PLCKE bit in register CR3 selects the RCLK clock
edge when RDATA is stable and valid.
Receive Recovered Clock. The clock recovered from the line input signal
is output on this pin. Under LOS conditions, there is a smooth transition
from the RCLK signal (derived from the recovered data) to the MCLK
signal at the RCLK pin.
8
5
RCLK
DO
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
10
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Table 3. LXT361 Signal Descriptions (Continued)
Pin #
Symbol
I/O1
Description
PLCC
QFP
Read. On an Intel bus, driving RD Low commands a LXT361 register read
operation.
9
7
RD/DS
DI
Data Strobe. On a Motorola bus, DS goes Low when data is being driven
on the address/data bus. Data is valid on the rising edge of DS.
Address/Data Bus 6 and 7. Used with AD0 - AD5 to form the address/
DI/O data bus. Conforms to Intel and Motorola multiplexed address/data bus
specifications.
10
11
9
AD6
AD7
10
Write. On an Intel bus, driving WR Low commands a LXT361 register write
operation.
12
13
WR / R/W
DI
Read/Write. On a Motorola bus, driving R/W High commands a LXT361
register read operation; driving it Low commands a write operation.
Transmit Tip and Ring. Differential driver output pair designed to drive a
50 - 200 Ω load. The transformer and line matching resistors should be
selected to give the desired pulse height and return loss performance. See
13
16
15
19
TTIP
AO
TRING
“Application Information” on page 32.
14
15
16
18
TGND
TVCC
-
-
Ground return for the transmit driver power supply TVCC.
+5 VDC Power Supply for the transmit drivers. TVCC must not vary from
VCC by more than ± 0.3 V.
Chip Select. During a read or write operation, CS must remain Low. See
Figure 16 and Figure 17 for timing requirements.
17
18
20
21
CS
DI
In the case of a single processor controlling several chips, this line is used
to select a specific transceiver.
Interrupt. INT goes Low to flag the host when LOS, AIS, NLOOP, QRSS,
DFMS or DFMO bits changes state, or when an elastic store overflow or
underflow occurs. To identify the specific interrupt, read the Performance
Status Register (PSR). To clear or mask an interrupt, write a one to the
appropriate bit in the Interrupt Clear Register (ICR). To re-enable the
interrupt, write a zero. INT is an open drain output that must be
connected to VCC through a pull-up resistor.
INT
DO
Receive Tip and Ring. The Alternate Mark Inversion (AMI) signal received
from the line is applied at these pins. A 1:1 transformer is required. Data
and clock recovered from RTIP/RRING are output on the RPOS/RNEG (or
RDATA in Unipolar mode), and RCLK pins.
19
20
24
25
RTIP
AI
-
RRING
+5 VDC Power Supply for all circuits except the transmit drivers. Transmit
drivers are supplied by TVCC.
21
27
VCC
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
Datasheet
11
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 3. LXT361 Signal Descriptions (Continued)
Pin #
Symbol
I/O1
Description
PLCC
QFP
22
29
GND
-
Ground return for VCC.
23
24
25
26
27
28
31
32
35
36
37
38
AD0
AD1
AD2
AD3
AD4
AD5
Address/Data Bus 0 - 5. Used with AD6 and AD7 to form the address/
DI/O data bus. Conforms to Intel and Motorola multiplexed address/data bus
specifications.
8, 11,
12, 14,
17, 22,
23, 26,
28, 30,
33, 34,
40, 44
-
n/c
-
Not Connected
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
12
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
3.0
Functional Description
The LXT361 is a fully integrated, PCM transceiver for Long- or Short-Hual, 1.544 Mbps (T1) or
2.048 Mbps (E1) applications allowing full-duplex transmission of digital data over existing
twisted-pair installations. The device interfaces with two twisted-pair lines (one pair each for
transmit and receive) through standard pulse transformers and appropriate resistors.
The figure on the front page of this data sheet shows a block diagram of the LXT361. Control of
the chip is via the 8-bit parallel microprocessor port. Stand-alone operation is not supported.
The LXT361 provides a high-precision, crystal-less Jitter Attenuator (JA). The user may place the
JA in the transmit or receive path, or bypass it completely.
The transceiver meets or exceeds FCC, ANSI, and AT&T specifications for CSU and DSX-1
applications, as well as ITU and ETSI requirements for E1 ISDN PRI applications.
3.1
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 3 V.
Upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the Phase Lock
Loops (PLL). The transceiver uses a reference clock to calibrate the PLLs: the transmitter reference
is TCLK, and the receiver reference clock is MCLK. MCLK is mandatory for chip operation and
must be independent, free running, and jitter free.
3.1.1
Reset Operation
A reset operation initializes the status and state machines for the LOS, AIS, NLOOP, and QRSS
blocks. Writing a 1 to the bit CR2.RESET commands a reset which clears all registers to 0. Allow
32 ms for the device to settle.
3.2
Transmitter
3.2.1
Transmit Digital Data Interface
Input data for transmission onto the line is clocked serially into the device at the TCLK rate. TPOS
and TNEG are the bipolar data inputs. In Unipolar mode, the TDATA pin accepts unipolar data.
Input data may pass through either the Jitter Attenuator or B8ZS/HDB3 encoder or both. Setting
CR1.ENCENB = 1 enables B8ZS/HDB3 encoding. With zero suppression enabled, Control
Register #1 (CR1) bits EC1 through EC4 determine the coding scheme as listed in Table 8 on
page 27.
TCLK supplies input synchronization. See the Figure 14 on page 41 for the transmit timing
requirements for TCLK and the Master Clock (MCLK).
Datasheet
13
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
3.2.2
Transmit Monitoring
The transmitter includes a short circuit limiter that limits the current sourced into a low impedance
load. The limiter automatically resets when the load current drops below the limit. The current is
determined by the interface circuitry (total resistance on transmit side).
The Performance Status Register (PSR) flags open circuits in bit PSR.DFMO. A transition of
DFMO can provide an interrupt, and its transition sets bit TSR.DFMO = 1. Writing a 1 in bit
ICR.CDFMO clears the interrupt; leaving a 1 in the bit masks that interrupt.
3.2.3
Transmit Drivers
The transceiver transmits data as a 50% line code as shown in Figure 3. To reduce power
consumption, the line driver is active only during transmission of marks, and is disabled during
transmission of spaces. Biasing of the transmit DC level is on-chip.
Figure 3. 50% Duty Cycle Coding
Bit Cell
1
0
1
3.2.4
3.2.5
Transmit Idle Mode
Transmit Idle mode allows multiple transceivers to be connected to a single line for redundant
applications. When TCLK is not present, Transmit Idle mode becomes active, and TTIP and
TRING change to the high impedance state. Remote loopback, Dual loopback, TAOS, or detection
of Network Loop Up code in the receive direction, temporarily disable the high impedance state.
Transmit Pulse Shape
As shown in Table 8 on page 27, the transmitted pulse shape is established by bits EC1 through
EC4 of Control Register #1 (CR1).
Shaped pulses meeting the various T1, DS1, DSX-1 and E1 specifications are applied to the AMI
line driver for transmission onto the line at TTIP and TRING. The transceiver produces DSX-1
pulses for Short-Hual T1 applications (settings from 0 dB to +6.0 dB of cable), DS1 pulses for
Long-Hual T1 applications (settings from 0 dB to -22.5 dB), and a G.703 pulse for E1 applications.
Refer to the Test Specifications section for pulse mask specifications.
14
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
3.3
Receiver
A 1:1 transformer provides the interface to the twisted-pair line. Recovered data is output at RPOS/
RNEG (RDATA in Unipolar mode), and the recovered clock is output at RCLK. Refer to Table 31
on page 42 for receiver timing specifications.
3.3.1
Receive Equalizer
The receive equalizer processes the signal received at RTIP and RRING. The equalizer gain is up to
43 dB in E1 Long-Hual applications and up to 36 dB in T1 applications. In T1 Long-Hual
applications, bits EC1 through EC4 in Control Register #1 determine the maximum gain applied at
the equalizer. When EC1 = 0, up to 36 dB of gain may be applied. When EC1 = 1, 26 dB is the gain
limit to provide an increased noise margin in shorter loop operations.
3.3.2
Receive Data Recovery
The transceiver filters the equalized signal and applies it to the peak detector and data slicers. The
peak detector samples the inputs and determines the maximum value of the received signal. The
data slicers are set at 50% of the peak value to ensure optimum signal-to-noise performance.
After processing through the data slicers, the received signal goes to the data and timing recovery
section, then to the B8ZS/HDB3 decoder (if selected) and to the receive monitor. The data and
timing recovery circuits provide input jitter tolerance significantly better than required by AT&T
Pub 62411 and ITU G.823. See the “Test Specifications” section for details.
Recovered data is routed to the Loss of Signal (LOS) Monitor and through the Alarm Indication
Signal (AIS, Blue Alarm) Monitor. The jitter attenuator (JA) may be enabled or disabled in the
receive data path or the transmit path. Received data may be routed to either the B8ZS or HDB3
decoder or neither. Finally, the device may send the digital data to the framer as either unipolar or
bipolar data.
When transmitting unipolar data to the framer, the device reports reception of bipolar violations by
driving the BPV pin High. During E1 operation, the device can report HDB3 code violations and
Zero Substitution Violations on the BPV pin.
3.3.3
Receiver Monitor Mode
The LXT361 receive equalizer can be used in Monitor mode applications. Monitor mode
applications require 20 dB to 30 dB resistive attenuation of the signal, plus a small amount of cable
attenuation (less than 6 dB). Setting bit CR3.EQZMON = 1 configures the device to operate in
Monitor mode. The device must be in T1/E1 Long-Hual receiver mode (set bits CR1.EC4:1 = 0xx0
or 1001 or 1010) for Monitor mode.
In Monitor mode, the receive equalizer will handle signals attenuated resistively by 20 to 30 dB,
along with 0 to 6 dB of cable attenuation for both E1 and T1 applications.
Datasheet
15
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
3.4
Jitter Attenuation
A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides jitter attenuation as shown in
the Test Specifications section. The JAL requires no special circuitry, such as an external quartz
crystal or high-frequency clock (higher than the line rate). Its timing reference is MCLK.
Bit CR1.JASEL0 enables or disables the JA circuit. With bit CR1.JASEL0 = 1, bit CR1.JASEL1
controls the JA circuit placement (see Table 7 on page 27). The ES can be either a 32 x 2-bit or 64
x 2-bit register depending on the value of bit CR3.ES64 (see Table 10 on page 28.)
The device clocks data into the ES using either TCLK or RCLK depending on whether the JA
circuitry is in the transmit or receive data path, respectively. Data is shifted out of the elastic store
using the dejittered clock from the JAL. When the FIFO is within two bits of overflowing or
underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average
delay of 16 bits (or 32 bits, with the 64-bit ES option selected) in the associated data path. When
the Jitter Attenuator is in the receive path, the output RCLK transitions smoothly to MCLK in the
event of a LOS condition.
The Transition Status Register bits TSR.ESOVR and TSR.ESUNF indicate an elastic store
overflow or underflow, respectively. Note that these are sticky bits that once set to 1, remain set
until the host reads the register. The ES can also provide a maskable interrupt on either overflow or
underflow.
3.5
Diagnostic Mode Operation
The LXT361 offers multiple diagnostic modes as listed in Table 4. The diagnostic modes are
selected by setting the appropriate register bits as described in the following paragraphs.
3.5.1
Loopback Modes
Local Loopback
3.5.1.1
See Figure 4 and Figure 5. Local loopback is selected by setting CR2.ELLOOP to 1. LLOOP
inhibits the receiver circuits. The transmit clock and data inputs (TCLK and TPOS/TNEG or
TDATA) loop back through the jitter attenuator (if enabled) and show up at RCLK and RPOS/
RNEG or RDATA. Note that during LLOOP, the JASEL input is strictly an Enable/Disable control;
it does not affect the placement of the JAL. If JA is enabled, it is active in the loopback circuit. If
JA is bypassed, it is not active in the loopback circuit.
The transmitter circuits are unaffected by LLOOP. LXT361 transmits the TPOS/TNEG or TDATA
inputs (or a stream of 1s if TAOS is asserted) normally. When used in this mode, the transceiver
can function as a stand-alone jitter attenuator.
Table 4. Diagnostic Mode Summary
Interrupt
Maskable
Diagnostic Mode
Loopback Modes
Local Loopback (LLOOP)
Analog Loopback (ALOOP)
No
No
16
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Table 4. Diagnostic Mode Summary
Interrupt
Maskable
Diagnostic Mode
Remote Loopback (RLOOP)
No
Yes
No
In-band Network Loopback (NLOOP)
Dual Loopback (DLOOP)
Internal Data Pattern Generation and Detection
Transmit All Ones (TAOS)
No
Yes
No
Quasi-Random Signal Source (QRSS)
In-band Loop Up/Down Code Generator
Error Insertion and Detection
Bipolar Violation Insertion (INSBPV)
Logic Error Insertion (INSLER)
No
No
No
No
No
Bipolar Violation Detection (BPV)
HDB3 Code Violation Detection (CODEV)
HDB3 Zero violation Detection (ZEROV)
Alarm Condition Monitoring
Receive Loss of Signal (LOS) Monitoring
Yes
Yes
Receive Alarm Indication Signal (AIS)
Monitoring
Transmit Driver Failure Monitoring Open
(DFMO)
Yes
Yes
Elastic Store Overflow and Underflow
Monitoring
Other Diagnostic Reports
Receive Line Attenuation Indicator (LATN)
Built-In Self Test (BIST)
No
Yes
Datasheet
17
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figure 4. TAOS with LLOOP
Figure 5. Local Loopback
3.5.1.2
Analog Loopback
See Figure 6. Analog loopback (ALOOP) exercises the maximum number of functional blocks.
ALOOP operation disconnects the RTIP/RRING inputs from the line and routes the transmit
outputs back into the receive inputs. This tests the encoders/decoders, jitter attenuator, transmitter,
receiver and timing recovery sections. Writing a 1 to bit CR2.EALOOP enables the ALOOP mode.
Note that ALOOP will override all other loopback modes.
18
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Figure 6. Analog Loopback
3.5.1.3
Remote Loopback
See Figure 7. In Remote loopback (RLOOP) mode, the device ignores the transmit data and clock
inputs (TCLK and TPOS/TNEG or TDATA), and bypasses the in-line encoders/decoders. The
RPOS/RNEG or RDATA outputs loop back through the transmit circuits to TTIP and TRING at the
RCLK frequency. The RLOOP command does not affect the receiver circuits which continue to
output the RCLK and RPOS/RNEG or RDATA signals received from the twisted-pair line.
RLOOP is selected by writing a 1 to bit CR2.ERLOOP.
Figure 7. Remote Loopback
3.5.1.4
Network Loopback
Network loopback (NLOOP) can be initiated only when the Network loopback detect function is
enabled. Writing a 1 to CR2.ENLOOP enables NLOOP detection.
Datasheet
19
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
With NLOOP detection enabled, the receiver looks for the NLOOP data patterns (00001 = enable,
001 = disable) in the input data stream. When the receiver detects an NLOOP enable data pattern
repeated for a minimum of five seconds, the device enables RLOOP. The device responds to both
framed and unframed NLOOP patterns. Once NLOOP detection is enabled at the chip and
activated by the appropriate data pattern, it is identical to Remote loopback (RLOOP). NLOOP is
disabled by receiving the 001 pattern for five seconds, or by activating RLOOP or ALOOP, or by
disabling NLOOP detection. The device goes into Dual loopback mode (DLOOP) in the case
where it detects both the NLOOP and LLOOP functions.
3.5.1.5
Dual Loopback
See Figure 8. To select Dual loopback (DLOOP) set bits CR2.ERLOOP and CR2.ELLOOP to 1. In
DLOOP mode, the transmit clock and data inputs (TCLK and TPOS/TNEG or TDATA) loop back
through the Jitter Attenuator (unless disabled) to RCLK and RPOS/RNEG or RDATA. The data
and clock recovered from the twisted-pair line loop back through the transmit circuits to TTIP and
TRING without jitter attenuation.
Figure 8. Dual Loopback
3.5.2
Internal Pattern Generation and Detection
Transmit All Ones
3.5.2.1
See Figure 9. In Transmit All Ones (TAOS) mode the transceiver ignores the TPOS and TNEG
inputs and transmits a continuous stream of 1s at the TCLK frequency. (With no TCLK, the TAOS
output clock is MCLK.) This can be used as the Alarm Indication Signal (AIS–also called the Blue
Alarm). TAOS is commanded by writing a 1 to bit CR2.ETAOS. Both TAOS and Local loopback
can occur simultaneously as shown in Figure 4, however, Remote loopback inhibits TAOS. When
both TAOS and LLOOP are active, TCLK and TPOS/TNEG loop back to RCLK and RPOS/RNEG
through the jitter attenuator (if enabled), and an all ones pattern goes to TTIP/TRING.
Figure 9. TAOS Data Path
20
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
3.5.2.2
Quasi-Random Signal Source (QRSS)
See Figure 10. For T1 operation, the Quasi-Random Signal Source (QRSS) is a 220-1 pseudo-
random bit sequence (PRBS) with no more than 14 consecutive zeros. For E1 operation, QRSS is
215-1 PRBS with inverted output. Setting bits CR2.EPAT0 = 0 and CR2.EPAT1 = 1 enables this
function.
The QRSS pattern is normally locked to TCLK; but if there is no TCLK, MCLK is the clock
source. Bellcore Pub 62411 defines the T1 QRSS transmit format and ITU G.703 defines the E1
format.
Figure 10. QRSS Mode
* If Enabled
With QRSS transmission enabled, it is possible to insert a logic error into the transmit data stream
by causing a Low-to-High transition on INSLER. However, if no logic or bit errors are to be
inserted into the QRSS pattern, INSLER must remain Low. Logic Error insertion waits until the
next bit if the current bit is “jammed”. When there are more than 14 consecutive 0s, the output is
jammed to a 1.
Furthermore, a bipolar violation in the QRSS pattern is possible by causing a Low-to-High
transition on the INSBPV pin, regardless of whether the device is in Bipolar or Unipolar mode.
Choosing QRSS mode also enables the QRSS Pattern Detection in the receive path. The QRSS
pattern is synchronized when there are fewer than four errors in 128 bits. The PSR.QRSS bit
provides an indication of QRSS pattern synchronization. This bit goes Low when no QRSS pattern
detected (i.e., when there are more than four errors in 128 bits). The TQRSS bit in the Transition
Status Register indicates that QRSS status has changed since the last QRSS Interrupt Clear
command.
The LXT361 can generate an interrupt to indicate that QRSS detection has occurred, or that
synchronization is lost. The interrupt is enabled when ICR.CQRSS = 0.
3.5.2.3
In-Band Network Loop Up or Down Code Generator
The LXT361 can transmit in-band Network Loop Up or Loop Down code. The Loop Up code is
00001; Loop Down code is 001. A Loop Up code transmission occurs when Control Register #2
bits EPAT0 = 1 and EPAT1 = 0. A Loop Down code transmission requires that both EPAT0 and
EPAT1 = 1.
With this mode enabled, logic errors and bipolar violations can be inserted into the transmit data
stream. Inserting a logic error requires a Low-to-High transition in INSLER (pin 3). If no logic or
bit errors are to be inserted, INSLER must remain Low. Inserting a bipolar violation requires a
Low-to-High transition on the INSBPV pin, regardless of unipolar or bipolar operation.
Datasheet
21
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
3.5.3
Error Insertion and Detection
3.5.3.1
Bipolar Violation Insertion (INSBPV)
Bipolar violation insertion is available In Unipolar mode. Choosing Unipolar mode configures the
INSBPV pin. To insert bipolar violation (BPV), a Low-to-High transition on the INSBPV is
required. Sampling occurs on the falling edge of TCLK. When INSBPV goes High a BPV is
inserted on the next available mark except in the four following situations:
• Zero suppression (HDB3 or B8ZS) is not violated
• If LLOOP and TAOS are both active, the BPV is looped back to RNEG/BPV indicator and the
line driver transmits all ones with no violation
• BPV insertion is disabled with RLOOP active
• BPV insertion is disabled when NLOOP is active
With the LXT361 configured to transmit internally generated data patterns (QRSS or NLOOP), a
BPV can be inserted into the transmit pattern regardless of whether the device is in the Unipolar or
Bipolar mode of operation.
3.5.3.2
Logic Error Insertion (INSLER)
When configured to transmit internally generated data patterns (QRSS or NLOOP Up/Down
codes), a logic error is inserted into the transmit data pattern when the INSLER pin transitions
Low-to-High. Note that in QRSS mode, there is no logic error insertion on a jammed bit (i.e., a bit
forced to one to suppress transmission of more than 14 consecutive zeros). The transceiver routes
data patterns the same way it routes data applied to TPOS/TNEG. Therefore, the inserted logic
error will follow the data flow path of the active loopback mode.
3.5.3.3
3.5.3.4
Bipolar Violation Detection (BPV)
When the internal encoders/decoders are disabled or when configured in Unipolar mode, bipolar
violations are reported at the BPV pin. BPV goes High for a full clock cycle to indicate receipt of a
BPV. When the encoders/decoders are enabled, the LXT361 does not report bipolar violations due
to the line coding scheme.
HDB3 Code Violation Detection (CODEV)
An HDB3 code violation (CODEV) occurs when two consecutive bipolar violations of the same
polarity are received (refer to ITU O.161). When CODEV detection is enabled, the BPV pin goes
High for a full RCLK cycle to report a CODEV violation. Note that bipolar violations and zero
substitution violations will also be reported on the BPV pin if these options are enabled.
HDB3 code violation detection is enabled when the HDB3 encoders/decoders are enabled. This
requires that CR1.ENCENB = 1, also CR1.EC4:1 = 100x or 1010, which establishes E1 operation.
To select CODEV detection, set bit CR4.CODEV = 1.
3.5.3.5
HDB3 Zero Substitution Violation Detection (ZEROV)
An HDB3 ZEROV is the receipt of four or more consecutive zeros. This does not occur with
correctly encoded HDB3 data unless there are transmission errors. The BPV pin goes High for a
full RCLK cycle to report a ZEROV. Note that when ZEROV detection enabled, the BPV pin will
also indicate received BPVs and CODEVs, if these detection options are enabled.
22
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
ZEROV detection is enabled when the HDB3 encoders/decoders are enabled. This requires
CR1.ENCENB = 1, also CR1.EC4:1 = 100x or 1010, which establishes E1 operation. To select
ZEROV detection, set bit CR4.ZEROV = 1.
3.5.4
Alarm Condition Monitoring
Loss of Signal
3.5.4.1
The LXT361 Loss of Signal (LOS) monitor function is compatible with ITU G.775 and ETSI
300233. The receiver LOS monitor loads a digital counter at the RCLK frequency. The count
increments with each received 0 and the counter resets to 0 on receipt of a 1. When the count
reaches “n” 0s, bit PSR.LOS is set to ‘1’, and the MCLK replaces the recovered clock at the RCLK
output in a smooth transition. For T1 operations, the number of 0s, n = 175, and for E1 operations,
n = 32. For both T1 and E1 operation, “n” can be set to 2048 by setting bit CR4.LOS2048 = 1.
For T1 operation, when the received signal has 12.5% 1s (16 marks in a sliding 128-bit period, with
fewer than 100 consecutive 0s), bit PSR.LOS = 0 and the recovered clock replaces MCLK at the
RCLK output in another smooth transition.
For E1 operation, the LOS condition is cleared when the received signal has 12.5% 1s density (four
1s in a sliding 32-bit window with fewer than 16 consecutive 0s). In E1 operation, the out-of-LOS
criterion can be modified from 12.5% marks density to 32 consecutive marks by setting bit
CR4.COL32CM = 1.
During LOS, the device sends received data to the RPOS/RNEG pins (or RDATA in Unipolar
mode). Bit PSR.LOS = 1 to indicate LOS condition, and can generate an interrupt to the host
controller if so programmed.
3.5.4.2
Alarm Indication Signal Detection
The receiver detects an AIS pattern when it receives fewer than three 0s in any string of 2048 bits.
The device clears the AIS condition when it receives three or more 0s in a string of 2048 bits.
The AIS bit in the Performance Status Register indicates AIS detection. Whenever the AIS status
changes, bit TSR.TAIS =1. Unless masked, a change of AIS status generates an interrupt.
3.5.4.3
3.5.4.4
Driver Failure Open Mode
The DFM Open (DFMO) bit is available in the Performance Status Register to indicate an open
condition on the lines. DFMO can generate an INT to the host controller. The Transition Status
Register bit TDFMO indicates a transition in the status of the bit. Writing a 1 to ICR.CDFMO will
clear or mask the interrupt.
Elastic Store Overflow/Underflow
When the bit count in the Elastic Store (ES) is within two bits of overflowing or underflowing the
ES adjusts the output clock by 1/ of a bit period. The ES provides an indication of overflow and
8
underflow via bits TRS.ESOVR and TSR.ESUNF. These are sticky bits and will stay set to 1 until
the host controller reads the register. These interrupts can be cleared or masked by writing a 1 to the
bits ICR.CESO and ICR.CESU, respectively.
Datasheet
23
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
3.5.5
Other Diagnostic Reports
3.5.5.1
Receive Line Attenuation Indication
The Equalizer Status Register (ESR) provides an approximation of the line attenuation encountered
by the device. The four most significant bits of the register (ESR.LATN7:4) indicate line
attenuation in approximately 2.9 dB steps for both T1 and E1 operation of the receive equalizer.
For instance, if ESR.LATN7:4 is 10 (decimal), then the receiver is seeing a signal attenuated by
approximately 29 dB (2.9 dB x 10) of cable loss.
3.5.5.2
Built-In Self Test
LXT361 provides a Built-In Self Test (BIST) capability. The BIST exercises the internal circuits by
providing an internal QRSS pattern, running it through the encoders and the transmit drivers then
looping it back through the receive equalizer, jitter attenuator and decoders to the QRSS pattern
detection circuitry. If all the blocks in this data path function correctly, the receive pattern detector
locks onto the pattern. It then pulls INT Low and sets the following bits:
• TSR.TQRSS = 1
• PSR.QRSS = 1
• PSR.BIST = 1
Note that during BIST, the TPOS/TNEG inputs must remain at logic level = 0
The most reliable test will result when a separate TCLK and MCLK are applied and the Line
Build-Out (LBO) is set to -22.5 dB (CR1.EC4:1 = 011x).
3.6
Parallel Microprocessor Interface
The LXT361 multiplexed address/data bus and timing/control signals are compatible with both the
Intel and Motorola microprocessors. See Figure 16 and Figure 17 for the I/O timing diagram for
each bus. The LXT361 detects and distinguishes between Intel and Motorola timing and then
automatically selects the appropriate bus timing. The maximum recommended processor speed for
an Intel device is 20 MHz; for a Motorola device, 16.78 MHz. See “Test Specifications” on
page 36 for microprocessor interface timing details.
The LXT361 contains five read/write and three read-only registers for control and status purposes.
Table 6 on page 26 is a summary of the registers. Table 7 through Table 15 identify and explain the
function of the register bits.
3.6.1
Interrupt Handling
The LXT361 provides a latched interrupt output pin (INT). When enabled, a change in any of the
Performance Status Register bits will generate an interrupt. An interrupt can also be generated
when the elastic store overflows (TSR.ESOVR) or underflows (TSR.ESUNF). When an interrupt
occurs, the INT output pin is pulled Low. Note that the output stage of the INT pin has internal
pull-down only. Therefore, each device that shares the INT line requires an external pull-up
resistor.
24
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
The interrupt is cleared when the interrupt condition no longer exists, and the host processor writes
a 1 to the respective interrupt causing bit(s) in the Interrupt Clear Register (ICR). Leaving a 1 in
any of the ICR bits masks that interrupt. To re-enable an interrupt bit, write a 0.
Datasheet
25
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
4.0
Register Definitions
The LXT361 contains five read/write and three read-only registers. Table 5 lists the LXT361
register addresses. Note that only bits A6 through A1 of the address byte are valid; the address
decoder ignores bits A7 and A0. Table 6 identifies the name of each register bit. Table 7 through
Table 15 describe the function of the bits in each register.
Note: upon power-up or reset, all registers are cleared to 0.
Table 5. Register Addresses
Register
Name
Address1
A7 - A0
Abbr
Control #1
Control #2
CR1
CR2
CR3
ICR
x010000x
x010001x
x010010x
x010011x
x010100x
x010101x
x010110x
x010111x
Control #3
Interrupt Clear
Transition Status
Performance Status
Equalizer Status
Control #4
TSR
PSR
ESR
CR4
1. x = don’t care.
Table 6. Register and Bit Summary
Register
Bit
Name
Type
7
6
5
4
3
2
1
0
Control #1
Control #2
Control #3
CR1 R/W
CR2 R/W
CR3 R/W
JASEL1
RESET
JA6HZ
CESU
JASEL0
EPAT1
PCLKE
CESO
ENCENB
EPAT0
UNIENB
ETAOS
EC4
EC3
EC2
EC1
ENLOOP EALOOP ELLOOP ERLOOP
SBIST
EQZMON reserved1
ES64
CAIS
ESCEN
ESJAM
CLOS
Interrupt Clear ICR R/W
CDFMO
reserved2
CQRSS
TQRSS
CNLOOP
Transition
Status
TSR
PSR
ESR
R
R
R
ESUNF
reserved1
LATN7
ESOVR
BIST
TDFMO
DFMO
LATN5
reserved1
TAIS
AIS
TNLOOP
NLOOP
TLOS
LOS
Performance
Status
reserved1
QRSS
Equalizer
Status
LATN6
LATN4
reserved1 reserved1 reserved1 reserved1
ZEROV CODEV
Control #4
CR4 R/W reserved1 reserved1 reserved1 reserved1 COL32CM LOS2048
1. In writable registers, bits labeled reserved should be set to 0 (except as in note 2 below) for normal operation and ignored in
read only registers.
2. Write a 1 to this bit for normal operation.
26
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Table 7. Control Register #1 Read/Write, Address (A7-A0) = x010000x
Jitter Attenuator
Bit
Name
Function
JASEL0 JASEL1 Position
0
1
2
3
EC1
EC2
EC3
EC4
1
1
0
0
1
Transmit
Receive
Disabled
Sets mode (T1 or E1) and equalizer
(see Table 8 below for control codes).
X
1 = Enable Unipolar I/O mode and allow insertion/detection of BPVs.
0 = Enable Bipolar I/O mode
4
5
UNIENB
1 = Enable B8ZS/HDB3 encoders/decoders and force Unipolar I/O
mode.
ENCENB
0 = Disable B8ZS/HDB3 encoders/decoders
6
7
JASEL0
JASEL1
Select jitter attenuation circuitry position in data path or disables the JA.
See right hand section of table for codes.
Table 8. Equalizer Control Bit Settings
Control Register #1
Function
Pulse
Cable
Gain
Coding2
EC4
EC3
EC2
EC11
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
T1 Long Haul
T1 Long Haul
T1 Long Haul
T1 Long Haul
T1 Long Haul
T1 Long Haul
T1 Long Haul
T1 Long Haul
E1 Short Haul
E1 Long Haul
E1 Long Haul
T1 Short Haul
T1 Short Haul
T1 Short Haul
T1 Short Haul
T1 Short Haul
0.0 dB pulse
-7.5 dB pulse
-15.0 dB pulse
-22.5 dB pulse
0.0 dB pulse
100 Ω TP
100 Ω TP
100 Ω TP
100 Ω TP
100 Ω TP
100 Ω TP
100 Ω TP
100 Ω TP
36 dB
36 dB
36 dB
36 dB
26 dB
26 dB
26 dB
26 dB
12 dB
43 dB
43 dB
12 dB
12 dB
12 dB
12 dB
12 dB
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
HDB3
HDB3
HDB3
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
-7.5 dB pulse
-15.0 dB pulse
-22.5 dB pulse
ITU G.703
120 Ω TP/75 Ω Coax
120 Ω TP
ITU G.703
ITU G.703
120 Ω TP/75 Ω Coax
100 Ω TP
0-133 ft / 0.6 dB
133-266 ft / 1.2 dB
266-399 ft / 1.8 dB
399-533 ft / 2.4 dB
533-655 ft / 3.0 dB
100 Ω TP
100 Ω TP
100 Ω TP
100 Ω TP
1. EC1 sets the receive equalizer gain (EGL) during T1 Long-Hual operation.
2. When enabled.
Datasheet
27
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 9. Control Register #2 Read/Write, Address (A7-A0) = x010001x
Pattern
Bit
Name
Function
EPAT0
EPAT1
Selected
1 = Enable Remote loopback mode
0 = Disable Remote loopback mode
0
1
2
3
4
ERLOOP1
ELLOOP1
EALOOP
ENLOOP
ETAOS
0
0
Transmit TPOS/TNEG
1 = Enable Local loopback mode
0 = Disable Local loopback mode
0
1
1
1
0
1
Detect and transmit QRSS
1 = Enable Analog loopback mode
0 = Disable Analog loopback mode
In-band Loop Up Code
00001
1 = Enable Network loopback detection
0 = Disable Network loopback detection
In-band Loop Down Code
001
1 = Enable Transmit All Ones
0 = Disable Transmit All Ones
5
6
EPAT0
EPAT1
Selects internal data pattern transmission. See right
hand section of table for codes.
1 = Reset device states and clear all registers.
0 = Reset complete.
7
RESET
1. To enable Dual loopback (DLOOP), set both ERLOOP = 1 and ELLOOP = 1.
Table 10. Control Register #3 Read/Write, Address (A7-A0) = x010010x
Bit
Name
Description
1 = Disable jamming of Elastic Store read out clock (1/8 bit-time adjustment for over/underflow).
0 = Enable jamming of Elastic Store read out clock
0
ESJAM
1 = Center ES pointer for a difference of 16 or 32, depending on depth (clears automatically).
0 = Centering completed
1
ESCEN
1 = Set elastic store depth to 64 bits.
0 = Set elastic store depth to 32 bits.
2
3
4
ES64
-
reserved–set to 0 for normal operation.
1 = Configure receiver equalizer for monitor mode application (DSX-1 monitor).
0 = Configure receiver equalizer for normal mode application
EQZMON
1 = Start Built-In Self Test.
5
6
7
SBIST
PLCKE
JA6HZ
0 = Built-In Self Test complete.
0 = RPOS/RNEG valid on the rising edge of RCLK.
1 = RPOS/RNEG valid on the falling edge of RCLK.
1 = Set bandwidth of jitter attenuation loop to 6 Hz.
0 = Set bandwidth of jitter attenuation loop to 3 Hz.
28
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Table 11. Interrupt Clear Register Read/Write, Address (A7-A0) = x010011x
Bit
Name
Function1
1 = Clear/Mask Loss of Signal interrupt.
0 = Enable Loss of Signal interrupt.
0
CLOS
1 = Clear/Mask Network loopback interrupt.
0 = Enable Network loopback interrupt.
1
2
CNLOOP
CAIS
1 = Clear/Mask Alarm Indication Signal interrupt.
0 = Enable Alarm Indication Signal interrupt.
1 = Clear/Mask Quasi-Random Signal Source interrupt.
0 = Enable Quasi-Random Signal Source interrupt.
3
4
5
CQRSS
-
reserved–set to 1 for normal operation.
1 = Clear/Mask Driver Failure Monitor Open interrupt.
0 = Enable Driver Failure Monitor Open interrupt.
CDFMO
1 = Clear/Mask Elastic Store Overflow interrupt.
0 = Enable Elastic Store Overflow interrupt.
6
7
CESO
CESU
1 = Clear/Mask Elastic Store Underflow interrupt.
0 = Enable Elastic Store Underflow interrupt.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
Table 12. Transition Status Register Read Only, Address (A7-A0) = x010100x
Bit
Name
Function
1 = Loss of Signal (LOS) has changed since last clear LOS interrupt occurred.
0 = No change in status.
0
TLOS
1 = NLOOP has changed since last clear NLOOP interrupt occurred.
0 = No change in status.
1
2
TNLOOP
TAIS
1 = AIS has changed since last clear AIS interrupt occurred.
0 = No change in status.
1 = QRSS has changed since last clear QRSS interrupt occurred1.
0 = No change in status.
3
4
5
TQRSS
-
reserved-ignore.
1 = DFMO has changed since last clear DFMS interrupt occurred.
0 = No change in status.
TDFMO
1 = ES overflow status sticky bit2.
0 = No change in status.
6
7
ESOVR
ESUNF
1 = ES underflow status sticky bit2.
0 = No change in status.
1. A QRSS transition indicates receive QRSS pattern sync or loss. A simple error in QRSS pattern is not reported as a
transition.
2. Tripping the overflow or underflow indicator in the ES sets the ESOVR/ESUNF status bit(s). Reading the Transition Status
Register clears these bits. Setting CESO and CESU in the Interrupt Clear Register masks these interrupts.
Datasheet
29
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 13. Performance Status Register Read Only, Address (A7-A0) = x010101x
Bit
Name
Function
1 = Loss of Signal occurred.
0
LOS
0 = Loss of Signal did not occur.
1 = Network loopback active.
1
2
NLOOP
AIS
0 = Network loopback not active.
1 = Alarm Indicator Signal detected.
0 = Alarm Indicator Signal not detected.
1 = Quasi-Random Signal Source pattern detected.
0 = Quasi-Random Signal Source pattern not detected.
3
4
5
QRSS
-
reserved–ignore.
1 = Driver Failure Monitor Open detected.
0 = Driver Failure Monitor Open not detected.
DFMO
1 = Built-In Self Test passed.
6
7
BIST
-
0 = Built-In Self Test did not pass (or was not run).
reserved–ignore.
Table 14. Equalizer Status Register Read Only, Address (A7-A0) = x010110x
Bit
Name
Function
0
1
2
3
4
5
6
7
-
reserved–ignore (Least Significant Bit)
reserved–ignore
-
-
reserved–ignore
-
reserved–ignore
LATN4
LATN5
LATN6
LATN7
Receive Line Attenuation Indicators. Convert this binary output to a decimal number and multiply
by 2.9 dB to determine the approximate cable attenuation as seen by the receiver.
For example, if LATN7-4 = 1010 BIN (= 10 DEC), then the receiver is seeing a signal attenuated by
approximately 29 dB (2.9 dB x 10) of cable. This approximation assumes that a 3 V pulse was
transmitted.
Table 15. Control Register #4 Read/Write, Address (A7-A0) = x010111x
Bit
Name
Function
1 = Enable detection of HDB3 code violations at the BPV pin along with bipolar violations and Zero
Substitution Violations (if enabled).
0
CODEV
0 = Disable detection of HDB3 code violations
1 = Enable detection of HDB3 Zero Substitution Violations (four consecutive zeros). Note that Zero
Substitution Violations are reported at the BPV pin.
1
ZEROV
0 = Disable detection of HDB3 Zero Substitution Violations.
1 = Set LOS detection threshold to 2048 consecutive zeros.
2
3
LOS2048
0 = Set LOS detection threshold to 32 consecutive zeros (for E1 operation) or to 175 consecutive
zeros (for T1 operation).
1 = Set LOS clear condition criterion to receipt of 32 consecutive marks (E1 operation).
0 = Set LOS clear condition criterion to 12.5% mark density (E1 operation).
COL32CM
30
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Table 15. Control Register #4 Read/Write, Address (A7-A0) = x010111x
Bit
Name
Function
4
5
6
7
-
-
-
-
reserved–set to 0 for normal operation; ignore when reading.
reserved–set to 0 for normal operation; ignore when reading.
reserved–set to 0 for normal operation; ignore when reading.
reserved–set to 0 for normal operation; ignore when reading.
Datasheet
31
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
5.0
Application Information
5.1
Transmit Return Loss
Table 16 shows the specification for transmit return loss in E1 applications. The G.703/CH PTT
specification is a Swiss Telecommunications Ministry specification.
Table 17 through Table 20 show the transmit return loss values for E1 Short- and Long-Hual and
T1 applications. Table 26 shows the receive return loss values.
5.2
5.3
Transformer Data
Specifications for transformers are listed in Table 21. A list of transformers recommended for use
with the LXT361 are specified in Table 22.
Application Circuit
Figure 11 shows a typical LXT361 application circuit.
Table 16. E1 Transmit Return Loss Requirements
Return Loss
Frequency
Band
ETS 300 166
G.703/CH PTT
51-102 kHz
6 dB
8 dB
8 dB
8 dB
14 dB
10 dB
102-2048 kHz
2048 - 3072 kHz
Table 17. Transmit Return Loss (2.048 Mbit/s–Short-Haul)
EC4-1
Xfrmr/Rt
RL (Ω)
CL (pF) Return Loss (dB)
0
470
0
14
16
12
13
13
16
75
1:2/
9.1 Ω
1000
120
120
470
0
1:2.3/9.1 Ω
470
32
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Table 18. Transmit Return Loss (2.048 Mbit/s–Long-Haul) High Return
Loss Configuration
EC4-1
Xfrmr/Rt
RL (Ω)
CL (pF)
Return Loss (dB)
0
19
28
18
28
1:2/
120
15 Ω
470
0
1001
1:1.53/15
75
Ω
470
Table 19. Transmit Return Loss (2.048 Mbit/s–Long-Haul)
EC4-1
Xfrmr/Rt
RL (Ω)
CL (pF)
Return Loss (dB)
0
12
13
16
18
120
470
0
1:2/
1010
9.1 Ω
75
470
Table 20. Transmit Return Loss (1.544 Mbit/s–Long- or Short-Haul)
EC4-1
Xfrmr/Rt
RL (Ω)
CL (pF) Return Loss (dB)
0
16
17
2
1:2/9.1 Ω
100
470
0
Refer to
Table 8
1:1.151/
0 Ω
100
470
2
1. A 1:1.15 transmit transformer keeps the total transceiver power
dissipation at a low level, a 0.47 μF DC blocking capacitor must
be placed on TTIP or TRING.
Table 21. Transformer Specifications for LXT361
Leakage
Inductance
μH
Interwinding
Capacitance
Dielectric1
Breakdown
V
Primary
Inductance
μH (minimum)
DCR
Ω
(maximum)
Frequency
MHz
Turns
Ratio
Tx/Rx
pF
(max)
(max)
(minimum)
1.544
2.048
1:1.15
1:2.3
1:2
600
600
600
600
0.80
0.80
0.80
1.10
60
60
60
60
0.90 pri, 1.70 sec
0.70 pri, 1.20 sec
0.70 pri, 1.20 sec
1.10 pri, 1.10 sec
1500 VRMS
2
Tx
1500 VRMS
2
1.544/2.048
1.544/2.048
1500 VRMS
2
Rx
1:1
1500 VRMS
1. Some ETSI applications may require a 2.3 kV dielectric breakdown voltage.
2. Some applications require transformers with center tap (Long-Haul applications with DC current in the E1/T1 loop).
Datasheet
33
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 22. Recommended Transformers for LXT361
Tx/Rx
Turns Ratio
Part Number
Manufacturer
1:1.53
PE-68663
PE-65388
PE-65770
16Z5952
Pulse Engineering
1:1.15
Vitec
PE-65351
PE-65771
0553-5006-IC
66Z-1308
671-5832
Pulse Engineering
Bell-Fuse
Fil-Mag
Tx
Midcom
67127370
67130850
TD61-1205D
1:2
Schott Corp
HALO (combination Tx/Rx set)
HALO (surface mount dual transformer 1CT:2CT &
1CT:2CT)
TG26-1205NI
TG48-1205NI
16Z5946
HALO (surface mount dual transformer 1CT:2CT & 1:1)
Vitec
1:2.3
PE-65558
FE 8006-155
671-5792
Pulse Engineering
Fil-Mag
Midcom
PE-64936
PE-65778
67130840
67109510
TD61-1205D
16Z5936
Pulse Engineering
Rx
1:1
Schott Corp
HALO (combination Tx/Rx set)
Vitec
16Z5934
Figure 11 shows a typical LXT361 application in either a T1 or E1 environment. See Table 17
through Table 22 to select the transformers (T1 and T2), resistors (Rt and RL) and capacitor (CL)
needed for this application.
Note that if the application includes surge protection, such as a varistor or sidactor on the TTIP/
TRING lines, it may be necessary to reduce the value of the capacitor CL or eliminate it
completely. Excessive capacitance at CL will distort the transmitted signals.
34
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Figure 11. Typical T1/E1 LXT361 Application
VCC
22 kΩ
2.048 MHz/
1.544 MHz
MCLK
INT
ALE/AS
RD/DS
WR/R/W
CS
μP
TCLK
TPOS
TNEG
TCLK
TPOS
TNEG
(Intel or
Motorola)
T1/E1
AD0-7
Framer
RCLK
RPOS
RNEG
RCLK
RPOS
RNEG
0.47 μF3
T11
LXT361
TTIP
Rt1
1
CL
Rt1
TVCC
VCC
TRING
RTIP
68 μF
0.1 μF
TGND
GND
2
RL
RRING
1:1
NOTES:
1. See Table 17 through Table 22 for CL & Rt/Transformer selection.
2. RL =100 Ω for T-1
RL = 120 Ω forE-1 / 120 Ω twisted pair
RL = 75 Ω for E-1 / 75 Ω coax
3. Optional for power savings.
Datasheet
35
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
6.0
Test Specifications
Note: Table 23 through Table 34 and Figure 12 through Figure 21 represent the performance
specifications of the LXT361 and are guaranteed by test except, where noted, by design. The
minimum and maximum values listed in Table 25 through Table 34 are guaranteed over the
recommended operating conditions specified in Table 24.
Table 23. Absolute Maximum Ratings
Parameter
Sym
Min
Max
Unit
DC supply (reference to GND)
Input voltage, any pin 1
Input current, any pin 2
Storage Temperature
VCC, TVCC
VIN
–
GND - 0.3 V
- 10
6.0
VCC + 0.3 V
10
V
V
IIN
mA
° C
TSTG
-65
150
Caution: Exceeding these values may cause permanent damage.
Caution: Functional operation under these conditions is not implied.
Caution: Exposure to maximum rating conditions for extended periods may affect device reliability.
1. TVCC and VCC must not differ by more than 0.3 V during operation. TGND and GND must not differ by more than 0.3 V
during operation.
2. Transient currents of up to 100 mA will not cause SCR latch-up. TTIP, TRING, TVCC, and TGND can withstand continuous
currents of up to 100 mA.
Table 24. Recommended Operating Conditions
Parameter
Sym
Min
Typ1
Max
Unit
Test Conditions
DC supply 2
Ambient operating temperature
VCC, TVCC
TA
4.75
-40
5.0
–
5.25
85
V
° C
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. TVCC and VCC must not differ by more than 0.3 V.
3. Power dissipation while driving 100 Ω load coupled through 1:1.15 transformer and 0 Ω resistor on TTIP/TRING. Includes
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacity load.
4. Power dissipation while driving 100 Ω load coupled through 1:2 transformer and 9.1 Ω resistor on TTIP/TRING. Includes
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacity load. This implementation has better return loss performance and is less sensitive to changes in impedances
variations.
5. Power dissipation while driving 120 Ω load coupled through 1:2 transformer and 9.1 Ω resistor on TTIP/TRING. Includes
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacity load.
36
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Table 24. Recommended Operating Conditions (Continued)
Parameter
Sym
Min
Typ1
Max
Unit
Test Conditions
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
–
–
–
–
–
–
–
–
–
–
310
225
245
195
470
320
350
260
275
215
380
295
325
265
560
380
420
310
330
270
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
100% mark density
50% mark density
100% mark density
50% mark density
100% mark density
50% mark density
100% mark density
50% mark density
100% mark density
50% mark density
Short Haul
Long Haul
Short Haul
Long Haul
T13
low power
Total
power
dissipation
T14
standard
power
Short Haul/
Long Haul
E15
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. TVCC and VCC must not differ by more than 0.3 V.
3. Power dissipation while driving 100 Ω load coupled through 1:1.15 transformer and 0 Ω resistor on TTIP/TRING. Includes
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacity load.
4. Power dissipation while driving 100 Ω load coupled through 1:2 transformer and 9.1 Ω resistor on TTIP/TRING. Includes
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacity load. This implementation has better return loss performance and is less sensitive to changes in impedances
variations.
5. Power dissipation while driving 120 Ω load coupled through 1:2 transformer and 9.1 Ω resistor on TTIP/TRING. Includes
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacity load.
Table 25. Digital Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Conditions
High level input voltage (pins 1-5, 9-12, 17, 23-28)2
Low level input voltage (pins 1-5, 9-12, 17, 23-28)2
High level output voltage1 (pins 6-8, 10, 11,23, 28)2
Low level output voltage1 (pins 6-8, 10, 11,23, 28)2
Input leakage current
VIH
VIL
2.0
–
–
–
–
–
–
–
V
V
0.8
–
VOH
VOL
ILL
2.4
–
V
IOUT = 400 μA
0.4
±50
V
IOUT = 1.6 mA
–
μA
1. Output drivers will output CMOS logic levels into CMOS loads.
2. Referenced pin numbers are for the PLCC package. Refer to Figure 2 on page 8 for the corresponding QFP pins.
Table 26. Analog Characteristics
Parameter
Min
Typ1
Max
Unit
Test Conditions
Recommended output load on TTIP/TRING
50
2.4
2.7
–
200
3.6
3.3
Ω
V
V
DSX-1, DS1
CEPT (ITU)
3.0
3.0
RL = 100 Ω
RL = 120 Ω
AMI Output Pulse Amplitudes
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Input signal to TCLK is jitter-free. The Jitter Attenuator is in the receive path or disabled.
3. Guaranteed by characterization; not subject to production testing.
4. Circuit attenuates jitter at 20 dB/decade above the corner frequency.
Datasheet
37
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 26. Analog Characteristics (Continued)
Parameter
10 Hz - 8 kHz 3
Min
Typ1
Max
Unit
Test Conditions
–
–
–
–
–
–
–
–
0.02
0.025
0.025
0.05
UI
UI
UI
UI
8 kHz - 40 kHz 3
10 Hz - 40 kHz3
Broad Band
Jitter added by the transmitter2
Mode 1 (EC1 = 1)
(T1 Long-Haul)
See Table 8 for
Gain Setting
0
0
0
0
–
–
–
–
26
36
dB
dB
dB
dB
Mode 2 (EC1 = 0)
(T1 Long-Haul)
Receiver sensitivity
@ 772 kHz (T1)
Mode 3 (EC4 = 1)
(T1 Short-Haul)
13.6
13.6
Mode 1 (EC4-1 = 1000)
(E1 Short-Haul/12 dB)
Receiver sensitivity
@ 1024 kHz (E1 line loss)
Mode 2 (EC4-1 = 1001 or
EC4-1 = 1010)
0
–
43
dB
(E1 Long-Haul/43 dB)
Allowable consecutive zeros before LOS (T1)
Allowable consecutive zeros before LOS (E1)
160
–
175
32
–
190
–
–
–
10 kHz - 100 kHz
0.4
138
0.2
37
–
UI
UI
UI
UI
0 dB line
AT&T Pub 62411
Input jitter tolerance (T1)
Input jitter tolerance (E1)
1 Hz 3
–
–
10 kHz - 100 kHz
1 Hz 3
–
–
0 dB line
ITU (G.823)
–
–
selectable in data
port
Jitter attenuation curve corner frequency 4
51 kHz - 102 kHz
–
3
–
Hz
–
–
–
22
28
30
–
–
–
dB
dB
dB
Receive Return Loss (E1)
102 kHz - 2.048 MHz
2.048 MHz - 3.072 MHz
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Input signal to TCLK is jitter-free. The Jitter Attenuator is in the receive path or disabled.
3. Guaranteed by characterization; not subject to production testing.
4. Circuit attenuates jitter at 20 dB/decade above the corner frequency.
38
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Figure 12. 2.048 MHz E1 Pulse (See Table 27)
269 ns
(244+25)
V = 100%
194 ns
(244- 50)
NOMINAL PULSE
50%
244 ns
219 ns
(244-25)
0%
20%
488 ns
(244+244)
Table 27. 2.048 MHz E1 Pulse Mask Specifications
Parameter
TWP
Coax
Unit
Test load impedance
120
3.0
75
2.37
Ω
V
Nominal peak mark voltage
Nominal peak space voltage
0 ±0.30
244
0 ±0.237
244
V
Nominal pulse width
ns
%
%
Ratio of positive and negative pulse amplitudes at center of pulse
Ratio of positive and negative pulse amplitudes at nominal half amplitude
95-105
95-105
95-105
95-105
Datasheet
39
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figure 13. 1.544 MHz T1 Pulse (DS1 and DSX-1) (See Table 28)
1.5
1.0
0.5
0.0
-0.5
1.5
Normalized Amplitude
Normalized Amplitude
1.0
0.5
0.5
1.0
1.5
-0.5
0.5
1.0
1.5
-0.5
0.0
Time
(in Unit Intervals)
Time
(in Unit Intervals)
-0.5
Table 28. 1.544 MHz T1 Pulse Mask Corner Point Specifications
DS1 Template (per ANSI T1. 403-1995)
Minimum Curve Maximum Curve
DSX-1 Template (per ANSI T1. 102-1993)
Minimum Curve Maximum Curve
Time (UI) Amplitude
Time (UI)
Amplitude
Time (UI)
Amplitude
Time (UI)
Amplitude
-0.77
-0.23
-0.23
-0.15
0.0
-0.05
-0.05
0.50
0.90
0.95
0.90
0.50
-0.77
-0.39
-0.27
-0.27
-0.12
0.0
0.05
0.05
0.80
1.20
1.20
1.05
1.05
-0.05
0.05
0.05
-0.77
-0.23
-0.23
-0.15
0.0
-0.05
-0.05
0.50
-0.77
-0.39
-0.27
-0.27
-0.12
0.0
0.05
0.05
0.80
1.15
1.15
1.05
1.05
-0.07
0.05
0.05
0.95
0.95
0.15
0.23
0.23
0.46
0.61
0.93
1.16
0.15
0.23
0.23
0.46
0.66
0.93
1.16
0.90
0.27
0.34
0.77
1.16
0.50
0.27
0.35
0.93
1.16
-0.45
-0.45
-0.26
-0.05
-0.05
-0.45
-0.45
-0.20
-0.05
-0.05
Table 29. Master and Transmit Clock Timing Characteristics for T1 Operation
(See Figure 14)
Parameter
Sym
Min
Typ1
Max
Unit
Notes
must be supplied
Master clock frequency
Master clock tolerance
Master clock duty cycle
Transmit clock frequency
MCLK
MCLKt
MCLKd
TCLK
–
–
1.544
±50
–
–
–
MHz
ppm
%
40
–
60
–
1.544
MHz
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
40
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Table 29. Master and Transmit Clock Timing Characteristics for T1 Operation
(See Figure 14)
Parameter
Sym
Min
Typ1
Max
Unit
Notes
Transmit clock tolerance
TCLKt
TCLKd
tSUT
–
–
–
–
–
±100
90
–
ppm
%
Transmit clock duty cycle
10
50
50
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
ns
tHT
–
ns
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 30. Master and Transmit Clock Timing Characteristics for E1 Operation
(See Figure 14)
Parameter
Sym
Min
Typ1
Max
Unit
Notes
Master clock frequency
MCLK
MCLKt
MCLKd
TCLK
TCLKt
TCLKd
tSUT
–
–
2.048
–
–
MHz
ppm
%
must be supplied
Master clock tolerance
±50
Master clock duty cycle
40
–
–
60
–
Transmit clock frequency
Transmit clock tolerance
Transmit clock duty cycle
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
2.048
MHz
ppm
%
–
–
–
–
–
±100
90
–
10
50
50
ns
tHT
–
ns
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Figure 14. Transmit Clock Timing
Datasheet
41
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Table 31. Receive Timing Characteristics for T1 Operation (See Figure 15)
Parameter
Receive clock duty cycle 2, 3
Sym
Min
Typ1
Max
Unit
RLCKd
tPW
40
–
50
60
–
%
ns
ns
ns
ns
ns
Receive clock pulse width 2, 3
648
324
324
274
274
Receive clock pulse width high
Receive clock pulse width low1,3
RPOS/RNEG to RCLK rising time
RCLK rising to RPOS/RNEG hold time
tPWH
tPWL
tSUR
tHR
–
–
260
–
388
–
–
–
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles are
for worst case jitter conditions.
3. Worst case conditions guaranteed by design only.
Table 32. Receive Timing Characteristics for E1 Operation (See Figure 15)
Parameter
Receive clock duty cycle 2, 3
Sym
Min
Typ1
Max
Unit
RLCKd
tPW
40
–
50
60
–
%
ns
ns
ns
ns
ns
Receive clock pulse width 2, 3
488
244
244
194
194
Receive clock pulse width high
Receive clock pulse width low1,3
RPOS/RNEG to RCLK rising time
RCLK rising to RPOS/RNEG hold time
tPWH
tPWL
tSUR
tHR
–
–
195
–
293
–
–
–
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions (0.4 UI clock displacement for 1.544 MHz.)
3. Worst case conditions guaranteed by design only.
Figure 15. Receive Clock Timing
42
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Table 33. LXT361 20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 16)
Parameter
Sym
Min
Max
Unit
Test Conditions
ALE pulse width
TLHLL
TAVLL
35
10
10
10
10
10
10
95
10
5
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to ALE falling edge
ALE falling edge to address hold time
ALE falling edge to RD falling edge
ALE falling edge to WR falling edge
CS falling edge to RD falling edge
CS falling edge to WR falling edge
RD low pulse width
TLLAX
TLLRL
–
–
TLLWL
TCLRL
TCLWL
TRLRH
TRLDV
TRHDX
TRHLH
TRHAV
TRHCH
TWLWH
TDVWH
TWHDX
TWHLH
TWHCH
–
–
–
–
RD falling edge to data valid
55
35
–
Data hold time after RD rising edge
RD rising edge to ALE rising edge
RD rising edge to address valid
CS low hold time after RD rising edge
WR low pulse width
15
35
0
–
–
95
40
30
15
15
–
Data setup time before WR rising edge
Data hold time after WR rising edge
WR rising edge to ALE rising edge
CS low hold time after WR rising edge
–
–
–
–
Datasheet
43
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figure 16. LXT361 I/O Timing Diagram for Intel Address/Data Bus
TCLWL
TCLRL
TWHCH
TRHCH
CS
TLLRL
TLLWL
TLHLL
TLLAX
TRHLH
TWHLH
ALE
RD
TAVLL
TRLRH
TRHAV
TRHDX
TRLDV
AD0-7_R
TWLWH
TDVWH
TWHDX
WR
AD0-7_W
Table 34. LXT361 16.78 MHz Motorola Bus Parallel I/O Timing Characteristics
(See Figure 17)
Parameter
Symbol
Min
Max
Units
Test Conditions
DS rising edge to AS rising edge
AS high pulse width
TDSHASH
TASHASL
TAVASL
15
35
10
10
20
10
95
10
5
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid setup time at AS falling edge
AS falling edge to Address valid hold time
AS falling edge to DS falling edge
CS falling edge to DS falling edge
DS low pulse width
–
Taslax
–
TASLDSL
TCSLDSL
TDSLDSH
TDSLDV
TDSHDX
TRWLDSL
TDVDSH
Tdxdsh
TDSHRWH
TDSHCSH
–
–
–
DS falling edge to data valid
55
35
–
Data hold time after DS rising edge
R/W falling edge to DS falling edge
Data setup time before DS rising edge
Data hold time after DS rising edge
R/W low hold time after DS rising edge
CS low hold time after DS rising edge
10
40
30
15
15
–
–
–
–
44
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Figure 17. LXT361 I/O Timing Diagram for Motorola Address/Data Bus
TCSLDSL
TDSHCSH
TDSHASH
CS
AS
TASHASL
TAVASL
TASLDSL
TASLAX
TDXDSH
TDSHRWH
TDSLDSH
TRWLDSL
TDVDSH
DS
R/W_Read
TDSHDX
TDSLDV
AD0-7_Read
R/W_Write
AD0-7_Write
Figure 18. Typical T1 Jitter Tolerance at 36 dB
1000 UI
500 UI
@ 10 Hz
Jitter
LXT361 Device
Typical Jitter Tolerance
Loop Mode
138 UI
100 UI
Pub 62411
28 UI
Dec 1990
10 UI
0.6 UI
@ 10 kHz
1 UI
0.4 UI
.1 UI
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
Datasheet
45
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figure 19. Typical E1 Jitter Tolerance at 43 dB
46
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Figure 20. Typical E1 Jitter Attenuation
Datasheet
47
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figure 21. \T1 Jitter Attenuation
48
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
7.0
Mechanical Specifications
Figure 22. Plastic Leaded Chip Carrier (PLCC) Package Specifications
28-Pin PLCC
• Part Number LXT361PE
• Extended Temperature Range (-40 °C to 85 °C)
C
L
C
B
D1
D
D
A2
A
A1
F
Inches
Millimeters
Dim
Min
Max
Min
Max
A
A1
A2
B
0.165
0.090
0.062
0.180
0.120
0.083
4.191
2.286
1.575
4.572
3.048
2.108
1
1
.050 BSC (nominal)
1.27 BSC (nominal)
C
0.026
0.485
0.450
0.013
0.032
0.495
0.456
0.021
0.660
12.319
11.430
0.330
0.813
12.573
11.582
0.533
D
D1
F
1. BSC—Basic Spacing between Centers.
Datasheet
49
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Figure 23. Plastic Quad Flat Package (PQFP) Specifications
44-Pin PQFP
• Part Number LXT361QE
• Extended Temperature Range (-40 °C to 85 °C)
D
D1
D3
e
E1
E
E3
θ
3
L1
A2
A
θ
A1
θ
3
B
L
Inches
Millimeters
Dim
Min
Max
Min
Max
A
A1
A2
B
–
0.096
–
–
2.45
–
0.010
0.077
0.012
0.510
0.390
0.25
1.95
0.30
12.95
9.90
0.083
0.018
0.530
0.398
2.10
0.45
13.45
10.10
D
D1
D3
E
0.315 BSC1 (nominal)
8.00 BSC1 (nominal)
0.510
0.530
12.95
13.45
E1
E3
e
0.390
0.398
9.90
10.10
0.315 BSC1 (nominal)
0.031 BSC1 (nominal)
8.00 BSC1 (nominal)
0.80 BSC1 (nominal)
L
0.029
0.041
0.73
1.03
L1
q3
q
0.063 BSC1 (nominal)
1.60 BSC1 (nominal)
5°
0°
16°
7°
5°
0°
16°
7°
1. BSC—Basic Spacing between Centers.
50
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Figure 24. Low-Profile Quad Flat Package (LQFP) Specifications
44-Pin LQFP
• Part Number LXT361LE
• Extended Temperature Range (-40 °C to 85 °C)
D
NOTE: All dimensions in millimeters.
D/2
b
E/2
e
E1/2
e/2
M
E1
E
0 DEG. MIN.
A2
0.08 / 0.20 R.
D1/2
A1
D1
0.08 R. MIN.
L
A
0 - 7 DEG.
0.20 MIN.
1.00
REF.
Millimeters
Nominal
Dimension1
Minimum
Maximum
A
A1
A2
b
-
-
1.60
0.15
1.45
0.45
0.05
1.35
0.30
0.10
1.40
0.37
D
12.00 (basic spacing between centers)
10.00 (basic spacing between centers)
12.00 (basic spacing between centers)
10.00 (basic spacing between centers)
0.80 (basic spacing between centers)
0.60
D1
E
E1
e
L
0.45
0.15
0.75
-
M
-
1. See JEDEC Publication for additional specifications.
Datasheet
51
7.1
Top Label Markings
Figure 25 shows a sample LQFP package for the LXT361 Transceiver.
Notes:
1. In contrast to the Pb-Free (RoHS-compliant) LQFP package, the non-RoHS-compliant
package does not have the “e3” symbol in the last line of the package label.
2. Further information regarding RoHS and lead-free components can be obtained from your
local Intel representative.
For general information, see http://www.intel.com/technology/silicon/leadfree.htm.
Figure 25.
Sample PLCC Package – Intel® DJLXT361LE Transceiver
Pin 1
LXT361LE A2
XXXXXXXX
Revision #
Part #
FPO#
BSMC
B5572-01
Figure 26 shows a sample Pb-Free (RoHS-compliant) LQFP package for the LXT361 Transceiver.
Figure 26.
Sample Pb-Free (RoHS-Compliant) LQFP Package – Intel® WJLXT361LE
Transceiver
Pin 1
WJLXT361E A2
XXXXXXXX
Revision #
Part #
FPO#
Pb-Free
Designation
e3
BSMC
B5574-01
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Figure 25 shows a sample PLCC package for the LXT361 Transceiver.
Notes:
1. In contrast to the Pb-Free (RoHS-compliant) PLCC package, the non-RoHS-compliant
package does not have the “e3” symbol in the last line of the package label.
Figure 27.
Sample PLCC Package – Intel® NLXT361PE Transceiver
Pin 1
LXT361PE A2
XXXXXXXX
Revision #
Part #
FPO#
BSMC
B5573-01
Figure 26 shows a sample Pb-Free (RoHS-compliant) PLCC package for the LXT361 Transceiver.
Figure 28.
Sample Pb-Free (RoHS-Compliant) PLCC Package – Intel® EELXT361PE
Transceiver
Pin 1
EELXT361E A2
XXXXXXXX
Revision #
Part #
FPO#
Pb-Free
Designation
e3
BSMC
B5575-01
Datasheet
53
LXT361 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
8.0
Product Ordering Information
Table 35 provides LXT361 Transceiver product ordering information.
Table 35.
Product Ordering Information
Product Number
Revision
Package Type
Pin Count
RoHS Compliant
DJLXT361LE.A2
WJLXT361LE.A2
NLXT361PE.A2
EELXT361PE.A2
A2
A2
A2
A2
LQFP
LQFP
PLCC
PLCC
44
44
28
28
No
Yes
No
Yes
54
Datasheet
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT361
Figure 29.
Ordering Information Matrix – Sample
DJ
LXT
361
L
E
A2
Product Revision
xn = 2 Alphanumeric characters
Temperature Range
A = Ambient (0 – 550 C)
C = Commercial (0 – 700 C)
E = Extended (-40 – 850 C)
Internal Package Designator
L = LQFP
P = PLCC
N = DIP
Q = PQFP
H = QFP
T = TQFP
B = BGA
C = CBGA
E = TBGA
K = HSBGA (BGA with heat slug
Product Code
xxxxx = 3-5 Digit alphanumeric
IXA Product Prefix
LXT = PHY layer device
IXE = Switching engine
IXF = Formatting device (MAC/Framer)
IXP = Network processor
Intel Package Designator
Pb-Free
Package
Leaded
WB
WJ
HQFP
LQFP
TQFP
HB
DJ
FA
BJ
JA
TQFP
FA
WD
QU
EG
PQFP
PQFP
PQFP
QFN
HD
KU
S
WG
HG
LB
PD
PA
N
UB
UC
EP
EE
RU
PC
EL
PR
QFN
PDIP
SSOP
PLCC
MMAP
MMAP
PBGA
PBGA
PBGA
PBGA
CBGA
FCBGA
TBGA
HZ
RC
FL
FW
GD
GW
HF
HL
TL
LU
EW
WF
JP
SC
B5571-01
Datasheet
55
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