NLXT908PC.A4SE000 [INTEL]
Ethernet Transceiver, 1-Trnsvr, CMOS, PQCC44,;
| 型号： | NLXT908PC.A4SE000 |
| 厂家： | 
INTEL |
| 描述： | Ethernet Transceiver, 1-Trnsvr, CMOS, PQCC44, 以太网：16GBASE-T 电信 电信集成电路 |
| 文件： | 总44页 (文件大小：601K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LXT908
Universal 3.3V 10BASE-T and AUI Transceiver
Datasheet
The LXT908 Universal 10BASE-T and AUI Transceiver is designed for IEEE 802.3 physical
layer applications. It provides all the active circuitry to interface most standard 802.3 controllers
to either the 10BASE-T media or Attachment Unit Interface (AUI). In addition to standard 10
Mbps Ethernet, the LXT908 also supports full-duplex operation at 20 Mbps.
LXT908 functions include Manchester encoding/decoding, receiver squelch and transmit pulse
shaping, jabber, link testing and reversed polarity detection/correction. The LXT908 can be used
to drive either the AUI drop cable or the 10BASE-T twisted-pair cable with only a simple
isolation transformer. Integrated filters simplify the design work required for FCC-compliant
EMI performance.
The LXT908 is fabricated with an advanced CMOS process and requires only a single 3.3V
power supply.
Applications
■ Access devices (DSL, Cable Modems, and ■ Telecom Backplane
Set-top Boxes)
■ Routers/Bridges/Switches/Hubs
■ USB to Ethernet Converters
Product Features
Functional Features
Convenience Features
■ Automatic/Manual AUI/RJ-45 Selection
■ Automatic Polarity Correction
■ SQE Disable/Enable function
■ Power Down Mode with tri-stated outputs
■ Four loopback modes
■ Improved Filters - Simplifies FCC
Compliance
■ Integrated Manchester Encoder/Decoder
■ 10BASE-T compliant Transceiver
■ AUI Transceiver
■ Supports Standard and Full-Duplex
■ Single 3.3V operation
Ethernet
■ Available in 64-pin LQFP and 44-pin
PLCC package
Diagnostic Features
■ Four LED Drivers
■ AUI/RJ-45 Loopback
■ Commercial (0 to +70°C) and
Extended (-40 to +85°C) temperature range
For technical assistance on this product, please call 1-800-628-8686, or
send an e-mail to support@mailbox.intel.com.
Order Number: 249049-002
June 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT908 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
2
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Contents
Contents
1.0
2.0
Pin Assignments and Signal Descriptions......................................................8
Functional Description...........................................................................................11
2.1
Introduction..........................................................................................................11
2.1.1 Controller Compatibility Modes ..............................................................11
2.1.2 Transmit Function...................................................................................12
2.1.3 Jabber Control Function.........................................................................12
2.1.4 Receive Function....................................................................................13
2.1.5 SQE Function.........................................................................................13
2.1.6 Polarity Reverse Function ......................................................................14
2.1.7 Loopback Function.................................................................................14
2.1.8 Collision Detection Function...................................................................15
2.1.9 Link Pulse Transmission ........................................................................16
2.1.10 Link Integrity Test Function ....................................................................16
3.0
Application Information.........................................................................................18
3.1
External Components..........................................................................................18
3.1.1 Crystal Information .................................................................................18
3.1.2 Magnetic Information..............................................................................18
Layout Requirements ..........................................................................................18
3.2.1 Auto Port Select with External Loopback Control...................................18
3.2.2 Full Duplex Support................................................................................20
3.2.3 Dual Network Support-10Base T and Token Ring .................................21
3.2.4 Manual Port Select & Link Test Function ...............................................22
3.2.5 Three Media Application.........................................................................24
3.2.6 AUI Encoder/Decoder Only....................................................................25
3.2
4.0
Test Specifications..................................................................................................26
4.1
4.2
4.3
4.4
4.5
Timing Diagrams for Mode 1 (MD2, 1, 0 = Low, Low, Low) Figures 16 - 21.......30
Timing Diagrams for Mode 2 (MD2, 1, 0 = Low, Low, High) Figures 22 - 27......32
Timing Diagrams for Mode 3 (MD2, 1, 0 = Low, High, Low) Figures 28 - 33......34
Timing Diagrams for Mode 4 (MD2, 1, 0 = Low, High, High) Figures 34 - 39 .....36
Timing Diagrams for Mode 5 (MD2, 1, 0 = High, High, Low) Figures 40 - 45 .....38
5.0
A
Mechanical Specifications....................................................................................40
Ordering Information..............................................................................................43
Datasheet
3
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Contents
Figures
1
2
3
4
5
6
7
8
LXT908 Block Diagram .........................................................................................7
LXT908 Pin Assignments......................................................................................8
LXT908 TPO Output Waveform .........................................................................12
Jabber Control Function......................................................................................13
SQE Function .....................................................................................................14
Collision Detection Function ...............................................................................15
Transmitted Link Integrity Pulse Timing .............................................................16
Link Integrity Test Function ................................................................................17
LAN Adapter Board - Auto Port Select with External Loopback Control ............19
Full-Duplex Operation ........................................................................................20
LXT908/380C26 Interface for Dual Network Support of 10BASE-T and
9
10
11
Token Ring
21
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
LAN Adapter Board - Manual Port Select with Link Test Function .....................22
Manual Port Select with Seeq 8005 Controller ..................................................23
Three Media Application ....................................................................................24
AUI Encoder/Decoder Only Application .............................................................25
Mode 1 RCLK/Start-of-Frame Timing ................................................................30
Mode 1 RCLK/End-of-Frame Timing ..................................................................30
Mode 1 Transmit Timing ....................................................................................31
Mode 1 Collision Detect Timing .........................................................................31
Mode 1 COL/SQE Output Timing/CI Output Timing ..........................................31
Mode 1 Loopback Timing ...................................................................................31
Mode 2 RCLK/Start-of-Frame Timing ................................................................32
Mode 2 RCLK/End-of-Frame Timing ..................................................................32
Mode 2 Transmit Timing ....................................................................................33
Mode 2 Collision Detect Timing .........................................................................33
Mode 2 COL/SQE Output Timing .......................................................................33
Mode 2 Loopback Timing ...................................................................................33
Mode 3 RCLK/Start-of-Frame Timing ................................................................34
Mode 3 RCLK/End-of-Frame Timing ..................................................................34
Mode 3 Transmit Timing ....................................................................................35
Mode 3 Collision Detect Timing .........................................................................35
Mode 3 COL/SQE Output Timing .......................................................................35
Mode 3 Loopback Timing ...................................................................................35
Mode 4 RCLK/Start-of-Frame Timing ................................................................36
Mode 4 RCLK/End-of-Frame Timing ..................................................................36
Mode 4 Transmit Timing ....................................................................................37
Mode 4 Collision Detect Timing .........................................................................37
Mode 4 COL/SQE Output Timing .......................................................................37
Mode 4 Loopback Timing ...................................................................................37
Mode 5 RCLK/Start-of-Frame Timing ................................................................38
Mode 5 RCLK/End-of-Frame Timing ..................................................................38
Mode 5 Transmit Timing ....................................................................................39
Mode 5 Collision Detect Timing .........................................................................39
Mode 5 COL/SQE Output Timing ......................................................................39
Mode 5 Loopback Timing ...................................................................................39
44-Pin PLCC Package Specifications ................................................................40
64-Pin LQFP Package Specifications ................................................................41
Ordering Information - Sample............................................................................43
Datasheet
4
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Contents
Tables
1
2
3
4
5
6
7
8
LXT908 Signal Descriptions..................................................................................9
Controller Compatibility Mode Options................................................................12
Suitable Crystals ................................................................................................18
Absolute Maximum Values.................................................................................26
Recommended Operating Conditions ................................................................26
I/O Electrical Characteristics ..............................................................................26
AUI Electrical Characteristics.............................................................................27
Twisted-Pair Electrical Characteristics...............................................................27
Switching Characteristics ...................................................................................28
RCLK/Start-of-Frame Timing..............................................................................28
RCLK/End-of-Frame Timing...............................................................................29
Transmit Timing...................................................................................................29
Collision, COL/CI Output and Loopback Timing.................................................29
Product Information.............................................................................................43
9
10
11
12
13
14
Datasheet
5
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Contents
Revision History
Date
Revision
Page
Description
Added new set of applications
1
19
20
21
22
23
Added 01. µF label to capacitor at bottom of Figure 9
Added 01. µF label to capacitor at bottom of Figure 10
Added 01. µF label to capacitor at bottom of Figure 11
Added 01. µF label to capacitor at bottom of Figure 12
Added 01. µF label to capacitor at bottom of Figure 13
June 2001
2001
Added second para. under “Test Specifications” regarding Quality
and Reliability issues
26
Removed “Ambient operating temperature” from Absolute Maximum
Ratings table.
26
43
Added Appendix: Product Ordering Information
6
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Figure 1. LXT908 Block Diagram
MD0
MD1
MD2
AUTOSEL
MODE SELECT LOGIC Controller
PAUI
LBK
LI
Compatibility/
Port Select /
Loopback /
Link test
TWISTED PAIR
Select:
PLS Only
or
RC
RC
INTERFACE
TPOPB
TPOPA
TPONA
TPONB
PLS / MAU
CMOS
TX
AMP
PULSE SHAPER
AND FILTER
TCLK
CLKI
DO
WATCHDOG
TIMER
COLLISION/
POLARITY
DETECT
XTAL
OSC
TPIP
TPIN
RX
SLICER
CLKO
TEN
MANCHESTER
ENCODER
CORRECT
TXD
DROP CABLE
INTERFACE
+
ECL
TX
AMP
CD
DOP
DON
SQUELCH / LINK
DETECT
LEDL
-
LPBK
RXD
DI
CI
DIP
DIN
MANCHESTER
DECODER
RCLK
RX SLICER
CIP
CIN
COLLISION
RECEIVER
COLLISION LOGIC
COL
DSQE
LEDR LEDT/PDN
LEDC/FDE
NTH JAB
PLR
Datasheet
7
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
1.0
Pin Assignments and Signal Descriptions
Figure 2. LXT908 Pin Assignments
39
38
TPIN
TPIP
7
8
9
n/c
LI
37 DSQE
JAB
36
35
34
TPONB
TPONA
VCC2
TEST 10
Rev #
11
12
TCLK
TXD
LXT908PC/PE XX
XXXXXX
Part #
LOT #
FPO #
33 GND2
TEN 13
XXXXXXXX
32
31
30
TPOPA
TPOPB
PLR
CLKO 14
15
16
17
CLKI
COL
29 n/c
AUTOSEL
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
n/c
RCLK
CD
RXD
MD2
n/c
RBIAS
n/c
GNDA
GND1
LBK
LEDC/FDE
LEDL
LEDT/PDN
LEDR
n/c
n/c
n/c
PAUI
DIP
DIN
n/c
DOP
DON
VCCA
VCC1
CIP
1
2
3
4
5
6
7
8
Rev #
LXT908LC/LE XX
XXXXXX
Part #
LOT #
FPO #
9
XXXXXXXX
10
11
12
13
14
15
16
CIN
NTH
MD0
MD1
n/c
8
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Table 1. LXT908 Signal Descriptions
Pin#
Symbol
I/O
Description
PLCC
LQFP
1
34
10
56
VCC1
VCC2
–
–
Power 1 and 2. Connect to positive power supply terminal (+3.3V
DC).
–
9
VCCA
–
Analog Supply. (+3.3V)
2
3
11
12
CIP
CIN
I
I
AUI Collision Pair. Differential input pair connected to the AUI
transceiver CI circuit. The input is collision signaling or SQE.
Normal Threshold. When NTH is High, the normal TP squelch
threshold is in effect. When NTH is Low, the normal TP squelch
threshold is reduced by 4.5 dB.
4
13
NTH
I
5
6
25
14
15
44
MD0
MD1
MD2
I
I
I
Mode Select 0 (MD0), Mode Select 1 (MD1) and Mode Select 2
(MD2). Mode select pins determine the controller compatibility
mode as specified in Table 2 on page 12.
1, 2, 6,
16, 17,
18, 20,
30, 31,
32, 33,
41, 43,
48, 49,
50, 51,
60, 63,
64
7, 29
N/C
–
No Connect. These pins may be left unconnected or tied to ground.
Link Test Enable. Controls Link Integrity Test; enabled when High,
disabled when Low.
8
19
LI
I
9
21
22
JAB
O
I
Jabber Indicator. Output goes High to indicate Jabber state.
Test. This pin must be tied High.
10
TEST
Transmit Clock. A 10 MHz clock output. This clock signal should
be directly connected to the transmit clock input of the controller.
TCLK goes to high impedance (tri-state) when LEDT/PDN is pulled
Low externally.
11
23
TCLK
O
Transmit Data. Input signal containing NRZ data to be transmitted
on the network. TXD is connected directly to the transmit data
output of the controller.
12
13
24
25
TXD
TEN
I
I
Transmit Enable. Enables data transmission and starts the Watch-
Dog Timer. Synchronous to TCLK (see Test Specifications for
details).
14
15
26
27
CLKO
CLKI
O
I
Crystal Oscillator. A 20 MHz crystal must be connected across
these pins, or a 20 MHz clock applied at CLKI, with CLKO left open.
Collision Detect. Output driving the collision detect input of the
controller. COL goes to high impedance (tri-state) when LEDT/PDN
is pulled Low externally.
16
17
28
29
COL
O
I
Automatic Port Select. When High, automatic port selection is
enabled (the LXT908 defaults to the AUI port only if TP link
integrity = Fail). When Low, manual port selection is enabled (the
PAUI pin determines the active port).
AUTOSEL
Receive LED. Open drain driver for the receive indicator LED.
Output is pulled Low during receive, except when data is being
looped back to DIN/DIP from a remote transceiver (external MAU).
LED “On” time (Low output) is extended by approximately 100 ms.
18
34
LEDR
O
Datasheet
9
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
Table 1. LXT908 Signal Descriptions (Continued)
Pin#
Symbol
I/O
Description
PLCC
LQFP
Transmit LED (LEDT)/Power Down (PDN). Open drain driver for
the transmit indicator LED. Output is pulled Low during transmit. Do
not allow this pin to float. If unused, tie High. LED “On” time
(Low output) is extended by approximately 100 ms. If externally tied
Low, the LXT908 goes to power-down state. In power-down state,
TCLK, COL, RXD, CD, and RCLK (pins 11, 16, 26, 27, and 28,
respectively) are tri-stated.
LEDT/
PDN
O
I
19
35
Link LED. Open drain driver for link integrity indicator LED. Output
is pulled Low during link test pass. If externally tied Low, internal
circuitry is forced to “Link Pass” state and the LXT908 will continue
to transmit link test pulses.
O
I
20
36
LEDL
Collision LED (LEDC)/Full Duplex Enable (FDE). Open drain
driver for the collision indicator LED pulls Low during collision. LED
“On” time (Low output) is extended by approximately 100 ms. If
externally tied Low, the LXT908 disables the internal TP loopback
and collision detection circuits to allow full-duplex operation or
external twisted-pair loopback.
LEDC/
FDE
O
I
21
22
37
38
Loopback. Enables internal loopback mode. Refer to Functional
Description and Test Specifications for details.
LBK
I
23
33
39
55
GND1
GND2
–
–
Ground Returns 1 and 2. Connect to negative power supply
terminal (ground).
–
40
42
GNDA
RBIAS
–
Analog Ground. Ground for analog plane.
Bias Control. A 12.4 kΩ 1% resistor to ground at this pin controls
operating circuit bias.
24
I
Receive Data. Output signal connected directly to the receive data
input of the controller. RXD goes to high impedance (tri-state) when
LEDT/PDN is pulled Low externally.
26
27
45
46
RXD
CD
O
O
Carrier Detect. An output to notify the controller of activity on the
network. CD goes to high impedance (tri-state) when LEDT/PDN is
pulled Low externally.
Receive Clock. A recovered 10 MHz clock that is synchronous to
the received data and connected to the controller receive clock
input. RCLK goes to high impedance (tri-state) when LEDT/PDN is
pulled Low externally.
28
30
47
52
RCLK
PLR
O
O
Polarity Reverse. Output goes High to indicate reversed polarity at
the TP input.
32
35
31
36
54
57
53
58
TPOPA
TPONA
TPOPB
TPONB
O
O
O
O
Twisted-Pair Transmit Pairs A & B. Two differential driver pair
outputs (A and B) to the twisted-pair cable. The outputs are pre-
equalized. Each pair must be shorted together with an 11.5 Ω 1%
resistor to match an impedance of 100Ω.
Disable SQE. When DSQE is High, the SQE function is disabled.
When DSQE is Low, the SQE function is enabled. SQE must be
disabled for normal operation in Hub/Switch applications.
37
59
DSQE
I
Twisted-Pair Receive Pair. A differential input pair from the TP
cable. Receive filter is integrated on chip. No external filters are
required.
61
62
TPIP
TPIN
I
I
3839
10
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Table 1. LXT908 Signal Descriptions (Continued)
Pin#
Symbol
I/O
Description
PLCC
LQFP
Port/AUI Select. In Manual Port Select mode (AUTOSEL Low),
PAUI selects the active port. When PAUI is High, the AUI port is
selected. When PAUI is Low, the TP port is selected. In Auto Port
Select mode, PAUI must be tied to ground.
40
3
PAUI
I
41
42
4
5
DIP
DIN
I
I
AUI Receive Pair. Differential input pair from the AUI transceiver DI
circuit. The input is Manchester encoded.
43
44
7
8
DOP
DON
O
O
AUI Transmit Pair. A differential output driver pair for the AUI
transceiver cable. The output is Manchester encoded.
2.0
Functional Description
2.1
Introduction
The LXT908 Universal 10BASE-T and AUI Transceiver performs the physical layer signaling
(PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. It
functions as an AUI (PLS-Only device) for use with 10BASE-2 or 10BASE-5 coaxial cable
networks, or as an Integrated PLS/MAU for use with 10BASE-T twisted-pair (TP) networks. In
addition to standard 10 Mbps operation, the LXT908 also supports full-duplex 20 Mbps operation.
The LXT908 interfaces a back-end controller to either an AUI drop cable or a twisted-pair cable.
The controller interface includes transmit and receive clock and NRZ data channels, as well as
mode control logic and signaling. The AUI interface comprises three circuits: Data Output (DO),
Data Input (DI), and Collision (CI). The twisted-pair interface comprises two circuits: Twisted-Pair
Input (TPI) and Twisted-Pair Output (TPO). In addition to the three basic interfaces, the LXT908
contains an internal crystal oscillator and four LED drivers for visual status reporting.
Functions are defined from the back end controller side of the interface. The LXT908 Transmit
function refers to data transmitted by the back end to the AUI cable (PLS-Only mode) or to the
twisted-pair network (Integrated PLS/MAU mode). The LXT908 Receive function refers to data
received by the back end from the AUI cable (PLS-Only) or from the twisted-pair network
(Integrated PLS/MAU mode). In the integrated PLS/MAU mode, the LXT908 performs all
required MAU functions defined by the IEEE 802.3 10BASE–T specification, such as collision
detection, link integrity testing, signal quality error messaging, jabber control, and loopback. In the
PLS-Only mode, the LXT908 receives incoming signals from the AUI DI circuit with
±18 ns of jitter and drives the AUI DO circuit.
2.1.1
Controller Compatibility Modes
The LXT908 is compatible with most industry-standard controllers including devices produced by
Advanced Micro Devices (AMD), Motorola, Intel, Fujitsu, National Semiconductor, Seeq, and
Texas Instruments, as well as custom controllers. Five different control signal timing and polarity
schemes (Modes 1 through 5) are required to achieve this compatibility. Mode select pins (MD2:0)
determine Controller compatibility modes as listed in Table 2 on page 12. Refer to Test
Specifications for a complete set of timing diagrams for each mode.
Datasheet
11
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
2.1.2
Transmit Function
The LXT908 receives NRZ data from the controller at the TXD input as shown in Figure 1,
“LXT908 Block Diagram” on page 7, and passes it through a Manchester encoder. The encoded
data is then transferred to either the AUI cable (the DO circuit) or the twisted-pair network (the
TPO circuit). The advanced integrated pulse shaping and filtering network produces the output
signal on TPON and TPOP, shown in Figure 3. The TPO output is pre-distorted and pre-filtered to
meet the 10BASE-T jitter template. An internal continuous resistor-capacitor filter is used to
remove any high-frequency clocking noise from the pulse shaping circuitry. Integrated filters
simplify the design work required for FCC-compliant EMI performance. During idle periods, the
LXT908 transmits link integrity test pulses on the TPO circuit (if LI is enabled and integrated PLS/
MAU mode is selected). External resistors control the termination impedance.
Figure 3. LXT908 TPO Output Waveform
4V
2V
0V
-2V
-4V
Table 2. Controller Compatibility Mode Options
Controller Mode
MD2
MD1
MD0
Mode 1 - For AMD AM7990, Motorola 68EN360, MPC860 or compatible
controllers
Low
Low
Low
Low
Low
High
Low
High
Low
Mode 2 - For Intel 82596 or compatible controllers
Mode 3 - For Fujitsu MB86950, MB86960 or compatible controllers (Seeq
1
8005)
Mode 4 - For National Semiconductor 8390 or compatible controllers (TI
TMS380C26)
Low
High
High
High
Low
Mode 5 - For custom controllers (Mode 3 with TCLK, RCLK and COL
inverted)
High
1. SEEQ controllers require inverters on CLKI, LBK, RCLK, and COL in Mode 3; or on CLKI, LBK, and TCLK
in Mode 5.
2.1.3
Jabber Control Function
Figure 4 on page 13 is a state diagram of the LXT908 Jabber control function. The LXT908 on-
chip Watch-Dog Timer prevents the DTE from locking into a continuous transmit mode. When a
transmission exceeds the time limit, the Watch-Dog Timer disables the transmit and loopback
functions, and activates the JAB pin. Once the LXT908 is in the jabber state, the TXD circuit must
remain idle for a period of 0.25 to 0.75 seconds before it will exit the jabber state.
12
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Figure 4. Jabber Control Function
Power On
No Output
DO=Active
Nonjabber Output
Start_XMIT_MAX_Timer
DO=Idle
DO=Active
XMIT_Max_Timer_Done
Jab
XMIT=Disable
LPBK=Disable
CI=SQE
DO=Idle
Unjab Wait
Start_Unjab_Timer
XMIT=Disable
LPBK=Disable
CI=SQE
Unjab_ Timer_Done
DO=Active
Unjab_Timer_Not_Done
2.1.4
Receive Function
The LXT908 receive function acquires timing and data from the twisted-pair network (TPI circuit)
or from the AUI (DI circuit). Valid received signals are passed through the on-chip filters and
Manchester decoder then output as decoded NRZ data and recovered clock on the RXD and RCLK
pins, respectively.
An internal RC filter and an intelligent squelch function discriminate noise from link test pulses
and valid data streams. The receive function is activated only by valid data streams above the
squelch level and with proper timing. If the differential signal at the TPI or the DI circuit inputs
falls below 75 percent of the threshold level (unsquelched) for 8 bit times (typical), the LXT908
receive function enters the idle state. If the polarity of the TPI circuit is reversed, LXT908 detects
the polarity reverse and reports it via the PLR output. The LXT908 automatically corrects reversed
polarity.
2.1.5
SQE Function
In the integrated PLS/MAU mode, the LXT908 supports the signal quality error (SQE) function as
shown in Figure 5 on page 14, although the SQE function can be disabled. After every successful
transmission on the 10BASE-T network when SQE is enabled, the LXT908 transmits the SQE
signal for 10BT ± 5BT over the internal CI circuit, which is indicated on the COL pin of the device.
Datasheet
13
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
SQE must be disabled for normal operation in hub and switch applications. In twisted-pair
applications, the SQE function is disabled when DSQE is set High, and enabled when DSQE is
Low. When using the 10BASE-2 port of the LXT908, the SQE function is determined by the
external MAU attached.
Figure 5. SQE Function
Power On
Output Idle
DO=Active
Output Detected
DO=Idle
SQE Wait Test
Start_SQE_Test__Wait_Timer
XMIT=Disable
SQE_Test__Wait_Timer_Done
XMIT=Enable
SQE Test
Start_SQE_Test_Timer
CI=SQE
SQE_Test_Timer_Done
2.1.6
Polarity Reverse Function
The LXT908 polarity reverse function uses both link pulses and end-of-frame data to determine
polarity of the received signal. A reversed polarity condition is detected when eight opposite
receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed
polarity is also detected if four frames are received with a reversed start-of-idle. Whenever a
correct polarity frame or a correct link pulse is received, these two counters are reset to zero. If the
LXT908 enters the link fail state and no valid data or link pulses are received within 96 to 128 ms,
the polarity is reset to the default non-flipped condition. If Link Integrity Testing is disabled,
polarity detection is based only on received data. Polarity correction is always enabled.
2.1.7
Loopback Function
The LXT908 provides the normal loopback function specified by the 10BASE-T standard for the
twisted-pair port. The loopback function operates in conjunction with the transmit function. Data
transmitted by the back-end is internally looped back within the LXT908 from the TXD pin
through the Manchester encoder/decoder to the RXD pin and returned to the back-end. This
“normal” loopback function is disabled when a data collision occurs, clearing the RXD circuit for
the TPI data. Normal loopback is also disabled during link fail and jabber states.
14
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
The LXT908 also provides three additional loopback functions. An external loopback mode, useful
for system-level testing, is controlled by pin 21 (LEDC). When LEDC is tied Low, the LXT908
disables the collision detection and internal loopback circuits, to allow external loopback or full-
duplex operation.
“Normal” twisted-pair loopback is controlled by pin 22 (LBK). When the twisted-pair port is
selected and LBK is High, twisted-pair loopback is “forced”, overriding collisions on the twisted-
pair circuit. When LBK is Low, normal loopback is in effect.
AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High,
data transmitted by the back-end is internally looped back from the TXD pin through the
Manchester encoder/decoder to the RXD pin. When LBK is Low, no AUI loopback occurs.
2.1.8
Collision Detection Function
The collision detection function operates on the twisted-pair side of the interface. For standard
(half-duplex) 10BASE-T operation, a collision is defined as the simultaneous presence of valid
signals on both the TPI circuit and the TPO circuit. The LXT908 reports collisions to the back-end
via the COL pin. If the TPI circuit becomes active while there is activity on the TPO circuit, the
TPI data is passed to the back-end over the RXD circuit, disabling normal loopback. Figure 6 is a
state diagram of the LXT908 collision detection function. Refer to Test Specifications for collision
detection and COL/CI output timing.
Note: For full-duplex operation, the collision detection circuitry must be disabled.
Figure 6. Collision Detection Function
A
Power On
DO=Active
TPI=Idle
XMIT=Enable
Idle
TPI=Active
Input
Output
DI=TPI
TPO=DO
DI=DO
DO=Active
TPI=Active
DO=Active
TPI=Active
XMIT=Enable
XMIT=Enable
Collision
TPO=DO
DI=TPI
CI=SQE
A
A
DO=Idle +
XMIT=Disable
TPI=Idle
DO=Active
TPI=Idle
DO=Idle
Datasheet
15
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
2.1.9
Link Pulse Transmission
The LXT908 transmits standard link pulses which meet the 10BASE-T specifications. Figure 7
shows the link integrity pulse timing.
Figure 7. Transmitted Link Integrity Pulse Timing
10-20 ms
10-20 ms
10-20 ms
10-20 ms
10-20 ms 10-20 ms
10-20 ms
10-20 ms
10-20 ms
2.1.10
Link Integrity Test Function
Figure 8 on page 17 is a state diagram of the LXT908 Link Integrity test function. The link
integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity
testing is enabled when pin 8 (LI) is tied High. When enabled, the receiver recognizes link integrity
pulses which are transmitted in the absence of receive traffic.
If no serial data stream or link integrity pulses are detected within 50 - 150 ms, the chip enters a
link fail state and disables the transmit and normal loopback functions. The LXT908 ignores any
link integrity pulse with interval less than 2 - 7 ms. The LXT908 will remain in the link fail state
until it detects either a serial data packet or two or more link integrity pulses.
16
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Figure 8. Link Integrity Test Function
Power On
Idle Test
Start_Link_Loss_Timer
TPI=Active +
Start_Link_Test_Min_Timer
(Link_Test_Rcvd=True
Link_Test_Min_Timer_Done)
Link_Loss_Timer_Done
TPI=Idle
Link_Test_Rcvd=False
Link Test Fail Reset
Link Test Fail Wait
Link_Count=0
XMIT=Disable
RCVR=Disable
LPBK=Disable
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Count=Link_Count + 1
TPI=Active
Link_Test_Rcvd=False
TPI=Idle
TPI=Active
Link_Test_Rcvd=Idle
TPI=Idle
Link Test Fail
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active +
Link_Count=LC_Max
Link_Test_Min_Timer_Done
Link_Test_Rcvd=True
Link Test Fail Extended
XMIT=Disable
RCVR=Disable
LPBK=Disable
(TPI=Idle Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done
Link_Test_Rcvd=True)
TPI=Idle
DO=Idle
Datasheet
17
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
3.0
Application Information
Figure 9 on page 19 through Figure 15 on page 25 show typical LXT908 applications.
3.1
External Components
3.1.1
Crystal Information
Suitable crystals are available from various manufacturers. Table 3 lists suitable crystals based on a
limited evaluation. Designers should test and validate all crystals before using them in production.
Table 3. Suitable Crystals
Manufacturer
Part Number
MP-1
MP-2
MTRON
3.1.2
Magnetic Information
The twisted-pair interface requires a 1:1 ratio for the receive transformer, and a 1:2 ratio for the
transmit transformer. The AUI interface requires a 1:1 ratio for data-in, data-out, and collision-pair
transformers. A cross-reference list of suitable magnetics and part numbers is available in
Application Note 73, Magnetic Manufacturers (248991-001), that can be found on the Intel website
(www.intel.com). Designers should test and validate all magnetics before committing to a specific
component.
3.2
Layout Requirements
3.2.1
Auto Port Select with External Loopback Control
Figure 9 on page 19 is a typical LXT908 application. The diagram groups similar pins together, but
does not represent the actual LXT908 pin-out. The controller interface pins (TXD, RXD, TEN,
TCLK, RCLK, CD, COL, and LBK) are shown at the top left of the diagram.
Programmable option pins are grouped at the center left of the diagram. The PAUI pin is tied Low
and all other option pins are tied High. This setup selects the following options:
• Automatic Port Selection
(PAUI Low and AUTOSEL High)
• Normal Receive Threshold (NTH High)
• Mode 4, compatible with National NS8390 controllers (MD2:0 = Low, High, High)
• SQE Disabled (DSQE High)
• Link Testing Enabled (LI High)
18
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Status outputs are grouped at the lower left of the diagram. Line status outputs drive LED
indicators and the Jabber and Polarity status indicators are available, as required.
Power and ground pins are shown at the bottom of the diagram. A single-power supply is used for
both VCC1 and VCC2, with a decoupling capacitor installed between the power and ground
busses.
An additional power and ground pin (VCCA and GNDA) is supported in designs using the 64-pin
LQFP package. A single-power supply is used for all three power and ground pins (VCC1, VCC2,
VCCA) and (GND1, GND2, GNDA). Please install a decoupling capacitor between each power
and ground buss.
The twisted-pair and AUI interfaces are shown at the upper and lower right of the diagram,
respectively. Impedance matching resistors for 100 UTP are installed in each I/O pair, but no
external filters are required.
Figure 9. LAN Adapter Board - Auto Port Select with External Loopback Control
20 pF
20 pF
20 MHz
CLKI
TXD
CLKO
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
RJ45
6
1
1 : 1 16
TPIN
TPIP
TEN
TCLK
RCLK
RXD
CD
NS8390 BACK-END
CONTROLLER
INTERFACE
100 Ω
5
4
3
2
1
3
14
COL
LBK
LOOPBACK
ENABLE
TPONB
TPONA
1 : 2
11.5 Ω 1%
11
6
8
220pF
PAUI
9
11.5 Ω 1%
AUTOSEL
NTH
TPOPB
TPOPA
PROGRAMMING
OPTIONS
DSQE
LI
MD2
MD1
MD0
1
78 Ω
1
16
MODE SELECT
LINE STATUS
9
CIN
2
3
4
5
6
7
8
10
11
12
13
14
15
JAB
PLR
2
4
15
13
CIP
78 Ω
78 Ω
330
330 330 330
DON
LEDC/FDE
LEDR
LEDT/PDN
LEDL
Green
Red Red Red
5
12
10
DOP
DIN
7
Fuse
8
9
TEST
DIP
12.4 kΩ
+3.3V
VCC1
VCC2
RBIAS
1 %
1
+ 12 V
Chassis
Gnd
GND1 GND2
0.1 µF
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
1
Datasheet
19
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
3.2.2
Full Duplex Support
Figure 10 shows the LXT908 with a Texas Instruments 380C24 CommProcessor. The 380C24 is
compatible with Mode 4 (MD2:0 = Low, High, High). When used with the 380C24 or other full-
duplex-capable controllers, the LXT908 supports full-duplex Ethernet, effectively doubling the
available bandwidth of the network. In this application, the SQE function is enabled (DSQE tied
Low), and the LXT908 AUI port is not used.
Figure 10. Full-Duplex Operation
20 pF
20 pF
CLKO
TMS380C24
20 MHz
CLKI
TXD
3
RJ45
6
TXD
1
1 : 1 16
TPIN
TPIP
TXEN
TXC
TEN
TCLK
RCLK
RXD
CD
100 Ω
RXC
5
4
3
2
1
3
14
RXD
CSN
COLL
COL
LBK
LPBK
TPONB
TPONA
1N914
1
1 : 2
11.5 Ω 1%
11
*TEST0
OUTSEL0
6
8
LEDC/FDE
10 KΩ
220pF
9
11.5 Ω 1%
TPOPB
TPOPA
AUTOSEL
NTH
*Open Collector
Driver
4.7 KΩ
PROGRAMMING
LI
OPTIONS
DSQE
PAUI
CIN
CIP
Half/Full Duplex Selection controlled by TMS380C24 Pins
Test0 and OUTSEL0.
MD2
MD1
MD0
JAB
PLR
1
2
MODE
SELECT
Bias resistor RBIAS should be located close to the pin
and isolated from other signals.
LINE STATUS
The TMS380C26 may be substituted for dual network
support of 10BASE-T and Token Ring.
DON
DOP
3
330 330
330
PAUI
LEDR
LEDT/PDN
LEDL
Red Red
Green
DIN
DIP
TEST
2
12.4 kΩ
+3.3 V
VCC1
VCC2
RBIAS
GND2
1 %
GND1
0.1 µF
20
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
3.2.3
Dual Network Support-10Base T and Token Ring
Figure 11 shows the LXT908 with a Texas Instruments 380C26 CommProcessor. The 380C26 is
compatible with Mode 4 (MD2:0 = Low, High, High).
When used with the 380C26, both the LXT908 and a TMS38054 Token Ring transceiver can be
tied to a single RJ-45, allowing dual network support from a single connector. The LXT908 AUI
port is not used.
Figure 11. LXT908/380C26 Interface for Dual Network Support of 10BASE-T and
Token Ring
From TI TMS38054 Token
Ring Transceiver
To TI TMS38054 Token Ring
Transceiver
20 pF
20 pF
CLKO
20 MHz
CLKI
TXD
380C26
TXD
RJ45
6
2
1
1 : 1 16
TPIN
TPIP
TXE
TEN
TCLK
RCLK
RXD
CD
TXC
100 Ω
RXC
5
4
3
2
1
3
14
RXD
CRS
COL
COL
LBK
LBK
TPONB
TPONA
1 : 2
11.5 Ω 1%
11
6
8
AUTOSEL
NTH
DSQE
220pF
9
PROGRAMMING
OPTIONS
11.5 Ω 1%
PAUI
LI
TPOPA
TPOPB
18 pF
MD2
MD1
MD0
MODE SELECT
LINE STATUS
JAB
PLR
CIN
CIP
330
330 330 330
Bias resistor RBIAS should be located close to the pin
and isolated from other signals.
1
LEDC/FDE
LEDR
LEDT/PDN
LEDL
Red Red Red
Green
DON
DOP
Additional magnetics and switching logic (not shown)
is required to implement the dual network solution.
2
DIN
DIP
TEST
12.4 kΩ
+3.3 V
VCC1
VCC2
RBIAS
GND2
1 %
1
GND1
0.1 µF
Datasheet
21
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
3.2.4
Manual Port Select & Link Test Function
When MD2:0 = Low, High, Low, the LXT908 logic and framing are set to Mode 3 (compatible
with Fujitsu MB86950 and MB86960, and Seeq 8005 controllers). Figure 12 shows the setup for
Fujitsu controllers. Figure 13 on page 23 shows the four inverters required to interface with the
Seeq 8005 controller. As in Figure 9 on page 19, both these Mode 3 applications show the LI pin
tied High, enabling Link Testing; and the NTH and DSQE pins are both tied High, selecting the
standard receiver threshold and disabling SQE. However, in these applications, AUTOSEL is tied
Low, allowing external port selection through the PAUI pin.
Figure 12. LAN Adapter Board - Manual Port Select with Link Test Function
20 pF
20 pF
20 MHz
CLKI
TXD
CLKO
RJ45
6
TXD
TEN
1
1 : 1 16
TPIN
TPIP
TEN
TCLK
RCLK
RXD
CD
TCKN
RCKN
RXD
MB86950 or MB86960
BACK-END/
CONTROLLER
INTERFACE
100 Ω
5
4
3
2
1
3
14
XCD
XCOL
LBC
COL
LBK
TPONB
TPONA
1 : 2
11.5 Ω 1%
11
Port Selection
6
8
PAUI
AUTOSEL
220pF
NTH
DSQE
LI
PROGRAMMING
OPTIONS
9
11.5 Ω 1%
TPOPA
TPOPB
MD2
MD1
MD0
MODE
SELECT
1
78 Ω
16
1
JAB
PLR
9
CIN
LINE STATUS
2
3
4
5
6
7
8
10
11
12
13
14
15
330
330
330
330
2
4
15
13
CIP
LEDC/FDE
LEDR
LEDT/PDN
78 Ω
Green
Red
Red
Red
DON
LEDL
5
12
10
DOP
DIN
78 Ω
7
Fuse
8
9
TEST
DIP
12.4 kΩ
+3.3 V
VCC1
VCC2
RBIAS
+ 12 V
1 %
1
Chassis
Gnd
GND1 GND2
0.1 µF
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
1
22
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Figure 13. Manual Port Select with Seeq 8005 Controller
External
20 MHz
Source
Left Open
CLKO
CLKI
LPBK
CSN
RxD
CLKI
LBK
RJ45
6
1
1 : 1 16
TPIN
TPIP
CD
RXD
RCLK
COL
TEN
TCLK
TXD
PAUI
8005
100 Ω
RxC
5
4
3
2
1
3
14
COLL
TxEN
TxC
TxD
TPONB
TPONA
1 : 2
11.5 Ω 1%
11
6
8
Port Selection
AUTOSEL
NTH
DSQE
LI
220pF
PROGRAMMING
OPTIONS
9
11.5 Ω 1%
TPOPA
TPOPB
MD2
MD1
MD0
MODE SELECT
LINE STATUS
1
78 Ω
16
1
JAB
PLR
CIN
9
2
3
4
5
6
7
8
10
11
12
13
14
15
330
330
330
330
2
4
15
13
CIP
LEDC/FDE
LEDR
LEDT/PDN
LEDL
78 Ω
Green
Red
Red
Red
DON
5
12
10
TEST
DOP
DIN
78
7
Fuse
8
9
DIP
+3.3V
VCC1
VCC2
12.4 kΩ
RBIAS
+ 12 V
1 %
1
Chassis
Gnd
GND1 GND2
0.1 µF
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
1
Datasheet
23
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
3.2.5
Three Media Application
Figure 14 shows the LXT908 in Mode 2 (compatible with Intel 82596 controllers) with additional
media options for the AUI port.
Two transformers are used to couple the AUI port to either a D-connector or a BNC connector. (A
DP8392 coax transceiver with PM6044 power supply are required to drive the thin coax network
through the BNC.
Figure 14. Three Media Application
LXT908
24
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
3.2.6
AUI Encoder/Decoder Only
In the application shown in Figure 15, the DTE is connected to a coaxial network through the AUI.
AUTOSEL is tied Low and PAUI is tied High, manually selecting the AUI port. The twisted-pair
port is not used. With MD2:0 all tied Low, the LXT908 logic and framing are set to Mode 1
(compatible with AMD and Motorola controllers). The LI pin is tied Low, disabling the link test
function. The DSQE pin is also Low, enabling the SQE function. The LBK input controls
loopback. A 20 MHz system clock is supplied at CLKI, with CLKO left open.
Figure 15. AUI Encoder/Decoder Only Application
SYSTEM
CLOCK
Left Open
CLKO
20 MHz
CLKI
TX
TENA
TXD
TEN
TCLK
RCLK
RXD
CD
TCLK
RCLK
AM7990 BACK-END/
CONTROLLER
INTERFACE
RX
RENA
CLSN
LBK
COL
LBK
LOOPBACK
CONTROL
AUTOSEL
PAUI
1
2
3
4
5
6
7
8
78 Ω
1
16
9
CIN
NTH
DSQE
LI
10
11
12
13
14
15
PROGRAMMING
OPTIONS
2
4
15
13
CIP
78 Ω
DON
MD2
MD1
MD0
MODE SELECT
5
12
10
DOP
DIN
JAB
PLR
78 Ω
LINE STATUS
7
330
330 330 330
Fuse
8
9
LEDC/FDE
LEDR
DIP
GREEN
Red Red Red
LEDT/PDN
LEDL
+ 12 V
Chassis
Gnd
TEST
1
+3.3 V
12.4 kΩ
VCC1
VCC2
RBIAS
1 %
GND1 GND2
1
Bias resistor RBIAS should be located close to the pin and isolated from the other signals
Datasheet
25
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
4.0
Test Specifications
Note: Table 4 through Table 13 on page 29 and Figure 16 on page 30 through Figure 45 on page 39
represent the performance specifications of the LXT908. These specifications are guaranteed by
test except where noted “by design.” Minimum and maximum values listed in Table 6 through
Table 13 on page 29 apply over the recommended operating conditions specified in Table 5.
For all Quality and Reliability issues (for example, parts packaging and thermal specifications),
please send your questions to Intel at the following e-mail address: www.qr.requests@intel.com.
.
Table 4. Absolute Maximum Values
Parameter
Symbol
Min
Max
Units
Supply voltage
VCC
-0.3
-65
6
V
Storage temperature
TSTG
+150
ºC
Caution: Exceeding these values may cause permanent damage. Functional operation
under these conditions is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
Table 5. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Recommended supply voltage1
VCC
TOP
TOP
3.13
0
3.3
–
3.47
+70
+85
V
Recommended operating temperature (Commercial)
Recommended operating temperature (Extended)
1. Voltages with respect to ground unless otherwise specified.
ºC
ºC
-40
–
Table 6. I/O Electrical Characteristics
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Input Low voltage2
Input High voltage2
VIL
VIH
–
2.0
–
–
–
–
–
0.8
–
V
V
VOL
VOL
0.4
10
V
IOL = 1.6 mA
Output Low voltage
µ
A
–
%VCC
IOL < 10
Output Low voltage
(Open drain LED driver)
VOLL
–
–
0.7
V
IOLL = 10 mA
µ
µ
VOH
VOH
–
2.4
90
–
–
–
3
2
–
–
V
%VCC
ns
IOH = 40
IOH < 10
A
Output High voltage
A
CMOS
TTL
12
8
CLOAD = 20 pF
Output rise time
TCLK & RCLK
–
–
ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
26
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Table 6. I/O Electrical Characteristics (Continued)
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
CMOS
TTL
–
–
–
–
–
–
–
3
2
–
12
8
ns
ns
ns
%
CLOAD= 20 pF
Output fall time
TCLK & RCLK
CLKI rise time (externally driven)
CLKI duty cycle (externally driven)
–
10
–
40/60
85
ICC
65
95
mA
Idle Mode
Transmitting on
TP
ICC
ICC
ICC
–
–
–
120
120
2
mA
mA
mA
Normal Mode
Supply current
Transmitting on
AUI
90
Power Down
Mode
0.75
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
Table 7. AUI Electrical Characteristics
1
Parameter
Input Low current
Symbol
Min
Typ
Max
Units
Test Conditions
µ
µ
IIL
IIH
–
–
–
–
–
-700
500
A
A
–
–
–
Input High current
Differential output voltage
VOD
±550
±1200
mV
mV
5 MHz square
wave input
Differential squelch threshold
VDS
150
260
350
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 8. Twisted-Pair Electrical Characteristics
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Transmit output impedance
ZOUT
–
5
–
Ω
0 line length for
internal MAU
2
Transmit timing jitter addition
–
–
±6.4
±10
ns
After line model
specified by IEEE
802.3 for 10BASE-T
internal MAU
Transmit timing jitter added by the
MAU and PLS sections
–
–
±3.5
±5.5
ns
2, 3
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5
ns from the MAU.
Datasheet
27
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
Table 8. Twisted-Pair Electrical Characteristics (Continued)
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Between TPIP/TPIN,
CIP/CIN & DIP/DIN
Receive input impedance
ZIN
–
20
–
kΩ
Normal
Threshold
NTH = High
5 MHz square wave
input
VDS
VDS
300
180
395
250
585
345
mV
mV
Differential Squelch
Threshold
Reduced
Threshold
NTH = Low
5 MHz square wave
input
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5
ns from the MAU.
Table 9. Switching Characteristics
1
Parameter
Symbol
Minimum
Typical
Maximum
Units
Maximum transmit time
Unjab time
–
–
–
–
–
–
20
250
50
2
–
150
750
150
7
ms
ms
ms
ms
ms
ms
Jabber Timing
–
Time link loss receive
Link min receive
–
–
Link Integrity
Timing
Link max receive
Link transmit period
50
8
–
150
24
10/20
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 10. RCLK/Start-of-Frame Timing
1
Parameter
Symbol
Minimum
Typical
Maximum
Units
AUI
tDATA
tDATA
tCD
–
–
900
1200
25
1100
1500
200
550
–
ns
ns
ns
ns
ns
ns
ns
ns
Decoder acquisition time
CD turn-on delay
TP
AUI
–
TP
tCD
–
420
70
Mode 1
tRDS
tRDS
tRDH
tRDH
60
30
10
30
Receive data setup from
RCLK
Modes 2 through 5
Mode 1
45
–
20
–
Receive data hold from
RCLK
Modes 2 through 5
45
–
RCLK shut off delay from CD assert (Mode 3
and Mode 5)
tsws
–
±100
–
ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
28
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Table 11. RCLK/End-of-Frame Timing
Mode
1
Mode
2
Mode
3
Mode
4
Mode
5
Parameter
Type
Sym
Units
RCLK after CD off
Min
Max
Max
Typ1
tRC
tRD
5
1
–
5
–
BT
ns
RXD throughput delay
400
500
5
375
475
50
375
475
–
375
475
–
375
475
–
2
CD turn off delay
tCDOFF
tIFG
ns
Receive block out after TEN off
BT
RCLK switching delay after CD
off (Mode 3 and 5)
120(±8
0)
120(±8
0)
Typ1
tSWE
–
–
–
ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. CD turn-off delay measured from middle of last bit: timing specification is unaffected by the value of the last
bit.
Table 12. Transmit Timing
1
Parameter
Symbol
Minimum
Typical
Maximum
Units
TEN setup from TCLK
tEHCH
tDSCH
tCHEL
tCHDU
tSTUD
tSTUD
tTPD
22
22
5
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
TXD setup from TCLK
TEN hold after TCLK
–
–
TXD hold after TCLK
5
–
–
Transmit start-up delay - AUI
Transmit start-up delay - TP
Transmit through-put delay - AUI
Transmit through-put delay - TP
–
220
430
–
450
450
300
350
–
–
tTPD
–
305
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 13. Collision, COL/CI Output and Loopback Timing
1
Parameter
COL turn-on delay
Symbol
Minimum
Typical
Maximum
Units
tCOLD
tCOLOFF
tSQED
tSQEP
tKHEH
tKHEL
–
–
40
420
1.2
1000
25
500
500
1.6
1500
–
ns
ns
µs
ns
ns
ns
COL turn-off delay
COL (SQE) Delay after TEN off
COL (SQE) Pulse Duration
LBK setup from TEN
0.65
500
10
LBK hold after TEN
10
0
–
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Datasheet
29
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
4.1
Timing Diagrams for Mode 1 (MD2, 1, 0 = Low, Low, Low)
Figures 16 - 21
Figure 16. Mode 1 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
Note: RXD changes 25 ns after the rising edge of RCLK.
Figure 17. Mode 1 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
tRC
RCLK
RXD
1
0
1
0
1
0
1
0
0
Note: RXD changes 25 ns after the rising edge of RCLK.
30
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Figure 18. Mode 1 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
TXD
tDSCH
tCHDU
tSTUD
tTPD
TPO
Figure 19. Mode 1 Collision Detect Timing
CI
tCOLOFF
tCOLD
COL
Figure 20. Mode 1 COL/SQE Output Timing/CI Output Timing
TEN
tSQED
COL
tSQEP
Figure 21. Mode 1 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
31
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
4.2
Timing Diagrams for Mode 2 (MD2, 1, 0 = Low, Low, High)
Figures 22 - 27
Figure 22. Mode 2 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
TPIP/TPIN
or DIP/DIN
CD
tCD
RCLK
tRDS
tRDH
1
tDATA
RXD
1
0
1
0
0
1
0
1
1
1
0
1
Note: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge.
Figure 23. Mode 2 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
CD
tCDOFF
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
Note: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge.
32
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Figure 24. Mode 2 Transmit Timing
TEN
tEHCH
TCLK
tCHEL
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
Figure 25. Mode 2 Collision Detect Timing
CI
tCOLD
tCOLOFF
COL
Figure 26. Mode 2 COL/SQE Output Timing
tIFG
TEN
tSQED
COL
tSQEP
Figure 27. Mode 2 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
33
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
4.3
Timing Diagrams for Mode 3 (MD2, 1, 0 = Low, High, Low)
Figures 28 - 33
Figure 28. Mode 3 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
or DIP/DIN
tCD
CD
tSWS
Recovered from Input Data Stream
RCLK
tRDS
Generated from TCLK
tDATA
tRDH
1
RXD
1
0
1
0
0
1
0
1
1
1
0
1
Note: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge.
Figure 29. Mode 3 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
tSWE
RCLK
Recovered Clock
Generated from TCLK
RXD
1
0
1
0
1
0
1
0
0
Note: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge.
34
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Figure 30. Mode 3 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tCHDU
tDSCH
TXD
tSTUD
TPO
tTPD
Figure 31. Mode 3 Collision Detect Timing
CI
tCOLOFF
tCOLD
COL
Figure 32. Mode 3 COL/SQE Output Timing
TEN
tSQED
tSQEP
COL
Figure 33. Mode 3 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
35
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
4.4
Timing Diagrams for Mode 4 (MD2, 1, 0 = Low, High, High)
Figures 34 - 39
Figure 34. Mode 4 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
Note: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge.
Figure 35. Mode 4 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
Note: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge.
36
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Figure 36. Mode 4 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
TXD
tDSCH
tCHDU
tTPD
tSTUD
TPO
Figure 37. Mode 4 Collision Detect Timing
CI
tCOLOFF
tCOLD
COL
Figure 38. Mode 4 COL/SQE Output Timing
TEN
tSQED
COL
tSQEP
Figure 39. Mode 4 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
37
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
4.5
Timing Diagrams for Mode 5 (MD2, 1, 0 = High, High, Low)
Figures 40 - 45
Figure 40. Mode 5 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/
TPIN
tCD
CD
tSWS
Recovered from Input Data Stream
RCLK
tRDS
1
Generated from TCLK
tDATA
tRDH
1
RXD
0
1
0
0
1
0
1
1
1
0
1
Note: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge.
Figure 41. Mode 5 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/
TPIN
tCDOFF
CD
tRD
tSWE
RCLK
Recovered Clock
Generated from TCLK
RXD
1
0
1
0
1
0
1
0
0
Note: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge.
38
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Figure 42. Mode 5 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tCHDU
tDSCH
TXD
TPO
tSTUD
tTPD
Figure 43. Mode 5 Collision Detect Timing
CI
tCOLOFF
tCOLD
COL
Figure 44. Mode 5 COL/SQE Output Timing
TEN
tSQED
tSQEP
COL
Figure 45. Mode 5 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
39
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
LXT908 — Universal 3.3V 10BASE-T and AUI Transceiver
5.0
Mechanical Specifications
Figure 46. 44-Pin PLCC Package Specifications
44-Pin Plastic Leaded Chip Carrier
• Part Number LXT908PC - Commercial temperature range (0°C to +70°C)
• Part Number LXT908PE - Extended temperature range (-40°C to +85°C)
C
L
Inches
Millimeters
Dim
Min
Max
Min
Max
C
B
A
A1
A2
B
0.165
0.090
0.062
0.050
0.026
0.685
0.650
0.013
0.180
0.120
0.083
–
4.191
2.286
1.575
1.270
0.660
17.399
16.510
0.330
4.572
3.048
2.108
–
C
0.032
0.695
0.656
0.021
0.813
17.653
16.662
0.533
D
D1
F
D1
D
D
A2
A
A1
F
40
Datasheet
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Figure 47. 64-Pin LQFP Package Specifications
64-Pin Low-Profile Quad Flat Package
• Part Number LXT908LC (Commercial Temperature Range)
• Part Number LXT908LE (Extended Temperature Range)
D
D1
Inches
Millimeters
Dim
Min
Max
Min
Max
A
A1
A2
B
–
0.063
0.006
0.057
.011
–
1.60
0.15
1.45
0.27
0.002
0.053
0.007
0.05
1.35
0.17
E1
E
D
0.472 BSC
12.00 BSC
D1
E
0.394 BSC
0.472 BSC
0.394 BSC
0.020 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.50 BSC
E1
e
L
0.018
0.030
0.45
0.75
e
e
/
2
L1
θ3
θ
0.039 REF
1.00 REF
11o
0o
13o
7o
11o
0o
13o
7o
θ3
L1
A2
A
θ
A1
B
θ3
L
Datasheet
41
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
Universal 3.3V 10BASE-T and AUI Transceiver — LXT908
Appendix A Ordering Information
Table 14. Product Information
Number
Revision
Qualification
Tray MM
Tape & Reel MM
DJLXT908LC.A4
DJLXT908LE.A4
NLXT908PC.A4
NLXT908PE.A4
A4
A4
A4
A4
S
S
S
S
831651
831652
831668
831669
831809
831810
831824
831825
Figure 48. Ordering Information - Sample
908
L
C
A4
S
E001
DJ
LXT
Build Format
= Tray
= Tape and reel
E000
E001
Qualification
= Pre-production material
= Production material
Q
S
Product Revision
= 2 Alphanumeric characters
xn
Temperature Range
= Ambient (0 - 55° C)
= Commercial (0 - 70° C)
= Extended (-40 - +85° C)
A
C
E
Internal Package Designator
= LQFP
L
= PLCC
= DIP
= PQFP
= QFP with heat spreader
P
N
Q
H
T
= TQFP
= BGA
= TBGA
= HSBGA (BGA with heat slug)
B
E
K
xxxx
= 3-5 Digit Alphanumeric Product Code
IXA Product Prefix
= PHY layer device
= Switching engine
= Formatting device (MAC)
= Network processor
LXT
IXE
IXF
IXP
Intel Package Designator
DJ
FA
FL
FW
HB
HD
HG
S
= LQFP
= TQFP
= PBGA (<1.0 mm pitch)
= PBGA (1.27 mm pitch)
= QFP with heat spreader
= QFP with heat slug
= SOIC
= QFP
GC
N
= TBGA
= PLCC
Datasheet
43
Document #: 249049
Revision #: 002
Rev. Date: June 19, 2001
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