PA28F200BL-B150_技术文档

2-MBIT (128K x 16, 256K x 8)

LOW-POWER BOOT BLOCK

FLASH MEMORY FAMILY

28F200BL-T/B, 28F002BL-T/B

Y

Low Voltage Operation for Very Low

Power Portable Applications

SRAM-Compatible Write Interface

Automatic Power Savings Feature

Y

e

Ð V

3.0V–3.6V

CC

Ð 0.8 mA Typical I

Static Operation

Active Current in

CC

Y

Expanded Temperature Range

a

20 C to 70 C

b

Ð

§

x8/x16 Input/Output Architecture

Very High-Performance Read

Ð 150 ns Maximum Access Time

Ð 65 ns Maximum Output Enable Time

Ð 28F200BL-T, 28F200BL-B

Ð For High Performance and High

Integration 16-bit and 32-bit CPUs

Y

Low Power Consumption

Ð 15 mA Typical Active Read Current

Y

x8-only Input/Output Architecture

Ð 28F002BL-T, 28F002BL-B

Ð For Space Constrained 8-bit

Applications

Reset/Deep Power-Down Input

Ð 0.2 mA I

Typical

Ð Acts as Reset for Boot Operations

CC

Y

Write Protection for Boot Block

Y

Upgradeable to Intel’s SmartVoltage

Products

Hardware Data Protection Feature

Ð Erase/Write Lockout during Power

Transitions

Optimized High-Density Blocked

Architecture

Ð One 16-KB Protected Boot Block

Ð Two 8-KB Parameter Blocks

Ð One 96-KB Main Block

Y

Industry Standard Surface Mount

Packaging

Ð 28F200BL: JEDEC ROM Compatible

44-Lead PSOP

56-Lead TSOP

Ð One 128-KB Main Block

Ð Top or Bottom Boot Locations

Ð 28F002BL: 40-Lead TSOP

Y

Extended Cycling Capability

Ð 10,000 Block Erase Cycles

Y

12V Word/Byte Write and Block Erase

e

g

12V 5% Standard

Ð V

PP

Automated Word/Byte Write and Block

Erase

Ð Command User Interface

Ð Status Registers

Ð Erase Suspend Capability

ETOX^TMIII Flash Technology

Ð 3.3V Read

Independent Software Vendor Support

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

©

COPYRIGHT INTEL CORPORATION, 1995

December 1995

Order Number: 290449-006

28F200BL-T/B, 28F002BL-T/B

Intel’s 2-Mbit Low Power Flash Memory Family is an extension of the Boot Block Architecture which includes

block-selective erasure, automated write and erase operations and standard microprocessor interface. The

2-Mbit Flash Memory Family enhances the Boot Block Architecture by adding more density and blocks,

x8/x16 input/output control, very low power, very high speed, an industry standard ROM compatible pinout

and surface mount packaging. The 2-Mbit Low Power Flash Family opens a new capability for 3V battery-oper-

ated portable systems and allows for an easy upgrade to Intel’s 4-Mbit Low Power Boot Block Flash Memory

Family.

The Intel 28F200BL-T/B are 16-bit wide flash memory offerings. These high density flash memories provide

user selectable bus operation for either 8-bit or 16-bit applications. The 28F200BL-T and 28F200BL-B are

2,097,152-bit non-volatile memories organized as either 262,144 bytes or 131,072 words of information. They

are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry

standard ROM/EPROM pinout.

The Intel 28F002BL-T/B are 8-bit wide flash memories with 2,097,152 bits organized as 262,144 bytes of

information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable

systems.

These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified

word/byte write and block erasure. The 28F200BL-T/28F002BL-T provide block locations compatible with

Intel’s low voltage MCS-186 family, i386^TM, i486^TMmicroprocessors. The 28F200BL-B/28F002BL-B provide

compatibility with Intel’s 80960KX and 80960SX families as well as other low voltage embedded microproces-

sors.

The boot block includes a data protection feature to protect the boot code in critical applications. With a

maximum access time of 150 ns, these 2-Mbit flash devices are very high performance low power memories

which interface to a wide range of low power microprocessors and microcontrollers. A deep power-down mode

lowers the total V power consumption to 0.66 mW. This is critical in handheld battery powered systems such

CC

as Handy Phones. For very high speed applications using a 5V supply, refer to the Intel 28F200BX-T/B,

28F002BX-T/B 2-Mbit Boot Block Flash Memory Family datasheet.

Manufactured on Intel’s 0.8 micron ETOX III process, the 2-Mbit low power flash memory family provides world

class quality, reliability and cost-effectiveness at the 2-Mbit density level.

2

28F200BL-T/B, 28F002BL-T/B

Follow these guidelines to ensure compatibility:

1.0 PRODUCT FAMILY OVERVIEW

Ý

1. Connect DU (WP on SmartVoltage products) to

a control signal or to V or GND.

Throughout this datasheet 28F200BL refers to both

the 28F200BL-T and 28F200BL-B devices and

28F002BL refers to both the 28F002BL-T and

28F002BL-B devices. The 2-Mbit flash family refers

to both the 28F200BL and 28F002BL products. This

datasheet comprises the specifications for four sep-

arate products in the 2-Mbit flash memory family.

Section 1 provides an overview of the 2-Mbit flash

memory family including applications, pinouts and

pin descriptions. Sections 2 and 3 describe in detail

the specific memory organizations for the 28F200BL

CC

2. If adding a switch on V for write protection,

PP

switch to GND for complete write protection.

3. Allow for connecting 5V to V and disconnect

PP

12V from line V line, if desired.

PP

1.2 Main Features

The 28F200BL/28F002BL low power boot block

flash memory family is a very low power and very

high performance 2-Mbit (2,097,152 bit) memory

family organized as either 128 Kwords (131,072

words) of 16 bits each or 256 Kbytes (262,144

bytes) of 8 bits each.

and 28F002BL products respectively. Section

4

combines a description of the family’s principles of

operations. Finally, section 5 describes the family’s

operating specifications.

PRODUCT FAMILY

Five Separately Erasable Blocks including a Hard-

ware-Lockable boot block (16,384 Bytes), two pa-

rameter blocks (8,192 Bytes each) and two main

blocks (1 block of 98,304 Bytes and 1 block of

131,072 Bytes) are included on the 2-Mbit family. An

erase operation erases one of the 5 blocks in typi-

cally 3.4 seconds and the boot or parameter blocks

in typically 2.0 seconds, independent of the remain-

ing blocks. Each block can be independently erased

and programmed 10,000 times.

x8/x16 Products

x8-Only Products

28F200BL-T

28F200BL-B

28F002BL-T

28F002BL-B

1.1 Designing for Upgrade to

SmartVoltage Products

Today’s high volume boot block products are up-

gradable to Intel’s SmartVoltage boot block prod-

ucts that provide program and erase operation at 5V

The Boot Block is located at either the top

(28F200BL-T, 28F002BL-T) or the bottom

(28F200BL-B, 28F002BL-B) of the address map in

order to accommodate different microprocessor pro-

tocols for boot code location. The hardware locka-

ble boot block provides the most secure code stor-

age. The boot block is intended to store the kernel

code required for booting-up a system. When the

or 12V V

and read operation at 3V or 5V V

.

PP

CC

Intel’s SmartVoltage boot block products provide the

following enhancements to the boot block products

described in this data sheet:

Ý

1. DU pin is replaced by WP to provide a means

to lock and unlock the boot block with logic sig-

nals.

Ý

RP pin is between 11.4V and 12.6V the boot block

is unlocked and program and erase operations can

Ý

be performed. When the RP pin is at or below 4.1V

2. 5V Program/Erase operation uses proven pro-

g

the boot block is locked and program and erase op-

erations to the boot block are ignored.

gram and erase techniques with 5V 10% ap-

plied to V

.

PP

3. Enhanced circuits optimize performance at 3.3V

.

The 28F200BL products are available in the

ROM/EPROM compatible pinout and housed in the

44-Lead PSOP (Plastic Small Outline) package and

the 56-Lead TSOP (Thin Small Outline, 1.2 mm

thick) package as shown in Figures 3 and 4. The

28F002BL products are available in the 40-Lead

TSOP (1.2 mm thick) package as shown in Figure 5.

V

CC

Refer to the 2, 4 or 8 Mbit SmartVoltage Boot Block

Flash Memory Data Sheets for complete specifica-

tions.

When you design with 12V V boot block products

PP

you should provide the capability in your board de-

sign to upgrade to SmartVoltage products.

The Command User Interface (CUI) serves as the

interface between the microprocessor or microcon-

troller and the internal operation of the 28F200BL

and 28F002BL flash memory products.

3

28F200BL-T/B, 28F002BL-T/B

Program and Erase Automation allow program

and erase operations to be executed using a two-

write command sequence to the CUI. The internal

Write State Machine (WSM) automatically executes

the algorithms and timings necessary for program

and erase operations, including verifications, there-

by unburdening the microprocessor or microcontrol-

ler. Writing of memory data is performed in word or

byte increments for the 28F200BL family and in byte

increments for the 28F002BL family typically within

11 ms.

mal read mode upon activation of the Reset pin.

When the CPU enters reset mode, it expects to read

the contents of a memory location. Furthermore,

with on-chip program/erase automation in the

Ý

2-Mbit family and the RP functionality for data pro-

tection, after the CPU is reset and even if a program

or erase command is issued, the device will not rec-

Ý

ognize any operation until RP returns to its normal

state.

For the 28F200BL, Byte-wide or Word-wide In-

put/Output Control is possible by controlling the

Ý

The Status Register (SR) indicates the status of the

WSM and whether the WSM successfully completed

the desired program or erase operation.

BYTE pin. When the BYTE pin is at a logic low

the device is in the byte-wide mode (x8) and data is

[

]

read and written through DQ 0:7 . During the byte-

wide mode, DQ 8:14 are tri-stated and DQ /A

becomes the lowest order address pin. When the

Ý

BYTE pin is at a logic high the device is in the

word-wide mode (x16) and data is read and written

]

through DQ 0:15 .

[

]

b

15

1

Maximum Access Time of 150 ns (t

over the commercial temperature range (0 C to

) is achieved

§

ACC

a

3.6V, 4.5V to 5.5V) and 50 pF output load.

70 C), over V

supply voltage range (3.0V to

§

CC

[

I

Program current is 40 mA for x16 operation

and 30 mA for x8 operation. I Erase current is

PP

1.3 Applications

PP

erase and programming

30 mA maximum. V

PP

voltage is 11.4V to 12.6V (V

der all operating conditions.

e

The 2-Mbit low power boot block flash memory fami-

ly combines high density, 3V operation, high per-

formance, cost-effective flash memories with block-

ing and hardware protection capabilities. Its flexibility

and versatility will reduce costs throughout the prod-

uct life cycle. Flash memory is ideal for Just-In-Time

production flow, reducing system inventory and

costs, and eliminating component handling during

the production phase. During the product life cycle,

when code updates or feature enhancements be-

come necessary, flash memory will reduce the up-

date costs by allowing either a user-performed code

change via floppy disk or a remote code change via

a serial link. The 2-Mbit boot block flash memory

family provides full function, blocked flash memories

suitable for a wide range of applications. These ap-

plications include Extended PC BIOS, Handy Digi-

tal Cellular Phone program and data storage and

various other portable embedded applications where

both program and data storage are required.

g

12V 5%) un-

PP

Typical I Active Current of 15 mA is achieved

CC

for the x16 products and the x8 products.

The 2-Mbit flash family is also designed with an Au-

tomatic Power Savings (APS) feature to minimize

system battery current drain and allow for extremely

low power designs. Once the device is accessed to

read the array data, APS mode will immediately put

the memory in static mode of operation where I

CC

active current is typically 0.8 mA until the next read

is initiated.

Ý

When the CE and RP pins are at V

BYTE pin (28F200BL-only) is at either V or GND

and the

CC

Ý

CC

the CMOS Standby mode is enabled where I

typically 40 mA.

is

CC

A Deep Power-down Mode is enabled when the

Reprogrammable systems such as Notebook and

Palmtop computers, are ideal applications for the

2-Mbit low power flash products. Portable and han-

dheld personal computer applications are becoming

more complex with the addition of power manage-

ment software to take advantage of the latest micro-

processor technology, the availability of ROM-based

application software, pen tablet code for electronic

handwriting, and diagnostic code. Figure 1 shows an

example of a 28F200BL-T application.

Ý

RP pin is at ground minimizing power consumption

and providing write protection during power-up con-

ditions. I

current during deep power-down mode

CC

is 0.20 mA typical. An initial maximum access time

Ý

or Reset Time of 600 ns is required from RP

switching until outputs are valid. Equivalently, the

device has a maximum wake-up time of 1 ms until

writes to the Command User Interface are recog-

Ý

nized. When RP is at ground the WSM is reset, the

Status Register is cleared and the entire device is

protected from being written to. This feature pre-

vents data corruption and protects the code stored

in the device during system reset. The system Reset

This increase in software sophistication augments

the probability that a code update will be required

after the PC is shipped. The 2-Mbit low power flash

memory products provide an inexpensive update so-

Ý

pin can be tied to RP to reset the memory to nor-

4

28F200BL-T/B, 28F002BL-T/B

lution for the notebook and handheld personal com-

puters while extending their product lifetime. Fur-

thermore, the 2-Mbit flash memory products’ deep

power-down mode provides added flexibility for

these battery-operated portable designs which re-

quire operation at extremely low power levels.

Blocks of program code and 2 Parameter Blocks of

8 Kbytes each for frequently updatable data storage

and diagnostic messages (e.g., phone numbers, au-

thorization codes). Figure 2 is an example of such an

application with the 28F002BL-T.

These are a few actual examples of the wide range

of applications for the 2-Mbit Low Power Boot Block

flash memory family which enables system design-

ers to achieve the best possible product design.

Only your imagination limits the applicability of such

a versatile low power product family.

The 2-Mbit low power flash products also provide

excellent design solutions for Handy Digital Cellular

Phone applications requiring high density storage,

high performance capabilities coupled with low volt-

age operation, and a small form factor package (x8-

only bus). The 2-Mbit’s blocking scheme allows for

an easy segmentation of the embedded code with:

16 Kbytes of Hardware-Protected Boot code, 2 Main

290449–6

Figure 1. 28F200BL-T Interface to Intel386^TMEX Embedded Processor

290449–22

Figure 2. 28F002BL-T Interface to INTEL 80L188EB, Low Voltage 8-Bit Embedded Microprocessor

5

28F200BL-T/B, 28F002BL-T/B

1.4 Pinouts

Figure 4 provides density upgrades to the 28F400BL

and to future higher density boot block memories.

The 28F200BL 44-Lead PSOP pinout follows the in-

dustry standard ROM/EPROM pinout as shown in

The 28F002BL 40-Lead TSOP pinout shown in Fig-

ure 5 is 100% compatible and has a density up-

grade to the 28F004BL 4-Mbit Low Power Boot

Block flash memory.

Figure

3 with an upgrade to the 28F400BL

(4-Mbit low power flash family). Furthermore,

the 28F200BL 56-Lead TSOP pinout shown in

290449–24

Figure 3. PSOP Lead Configuration for x8/x16 28F200BL

6

28F200BL-T/B, 28F002BL-T/B

290449–4

Figure 4. TSOP Lead Configuration for x8/x16 28F200BL

290449–5

Figure 5. TSOP Lead Configuration for x8 28F002BL

7

28F200BL-T/B, 28F002BL-T/B

1.5 Pin Descriptions for x8/x16 28F200BL

Symbol

A –A

Type

Name and Function

I

ADDRESS INPUTS for memory addresses. Addresses are internally latched

during a write cycle.

0

16

A

I

ADDRESS INPUT: When A is at 12V the signature mode is accessed. During this

9

Ý

mode A decodes between the manufacturer and device ID’s. When BYTE is at

b

0

a logic low only the lower byte of the signatures are read. DQ /A

Ý

care in the signature mode when BYTE is low.

is a don’t

1

15

Ý

DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle

during a program command. Inputs commands to the command user interface

DQ –DQ

0

I/O

7

Ý

when CE and WE are active. Data is internally latched during the write and

program cycles. Outputs array, Intelligent Identifier and Status Register data. The

data pins float to tri-state when the chip is deselected or the outputs are disabled.

Ý

DQ –DQ

8

I/O

DATA INPUT/OUTPUTS: Inputs array data on the second CE and WE cycle

during a program command. Data is internally latched during the write and program

cycles. Outputs array data. The data pins float to tri-state when the chip is

15

e

In the byte-wide mode DQ /A becomes the lowest order address for data

Ý

deselected or the outputs are disabled as in the byte-wide mode (BYTE

b

‘‘0’’).

15

1

output on DQ -DQ .

7

0

Ý

CE

RP

I

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

Ý

sense amplifiers. CE is active low; CE high deselects the memory device and

Ý

reduces power consumption to standby levels. If CE and RP are high, but not

at a CMOS high level, the standby current will increase due to current flow through

Ý

the CE and RP input stages.

RESET/DEEP POWER-DOWN: Provides Three-State control. Puts the device in

deep power-down mode. Locks the boot block from program/erase.

Ý

When RP is at logic high level and equals 4.1V maximum the boot block is

locked and cannot be programmed or erased.

e

Ý

When RP

or erased.

11.4V minimum the boot block is unlocked and can be programmed

Ý

When RP is at a logic low level the boot block is locked, the deep power-down

mode is enabled and the WSM is reset preventing any blocks from being

programmed or erased, therefore providing data protection during power

Ý

transitions. When RP transitions from logic low to logic high, the flash memory

enters the read-array mode.

Ý

OE

I

OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

Ý

read cycle. OE is active low.

Ý

WE

WRITE ENABLE: Controls writes to the Command Register and array blocks.

Ý

WE is active low. Addresses and data are latched on the rising edge of the WE

pulse.

Ý

8

28F200BL-T/B, 28F002BL-T/B

1.5 Pin Descriptions for x8/x16 28F200BL (Continued)

Symbol

Type

Name and Function

Ý

BYTE

I

BYTE ENABLE: Controls whether the device operates in the byte-wide mode (x8) or

e

Ý

the word-wide mode (x16). BYTE

read and programmed on DQ –DQ and DQ /A

b

1

‘‘0’’ enables the byte-wide mode, where data is

becomes the lowest order

0

7

15

address that decodes between the upper and lower byte. DQ –DQ are tri-stated

8

14

‘‘1’’ enables the word-wide mode where data is

e

Ý

during the byte-wide mode. BYTE

read and programmed on DQ –DQ

.

15

0

V

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or

programming data in each block.

PP

CC

k

Note: V

V

memory contents cannot be altered.

PP

PPLMAX

g

DEVICE POWER SUPPLY (3.3V 0.3V, 5V 10%)

GROUND: For all internal circuitry.

GND

NC

NO CONNECT: Pin may be driven or left floating.

DON’T USE PIN: Pin should not be connected to anything.

DU

9

28F200BL-T/B, 28F002BL-T/B

1.6 Pin Descriptions for x8 28F002BL

Symbol

A –A

Type

Name and Function

I

ADDRESS INPUTS for memory addresses. Addresses are internally latched during

a write cycle.

0

17

A

I

ADDRESS INPUT: When A is at 12V the signature mode is accessed. During this

9

mode A decodes between the manufacturer and device ID’s.

9

0

Ý

DATA INPUTS/OUTPUTS: Inputs array data on the second CE and WE cycle

during a program command. Inputs commands to the command user interface

DQ –DQ

0

I/O

7

Ý

when CE and WE are active. Data is internally latched during the write and

program cycles. Outputs array Intelligent Identifier and status register data. The

data pins float to tri-state when the chip is deselected or the outputs are disabled.

Ý

CE

RP

I

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

Ý

sense amplifiers. CE is active low; CE high deselects the memory device and

reduces power consumption to standby levels.

RESET/DEEP POWER-DOWN: Provides Three-State control. Puts the device in

deep power-down mode. Locks the Boot Block from program/erase.

Ý

When RP is at logic high level and equals 4.1V maximum the Boot Block is locked

and cannot be programmed or erased.

e

Ý

When RP

or erased.

11.4V minimum the Boot Block is unlocked and can be programmed

Ý

When RP is at a logic low level the Boot Block is locked, the deep power-down

mode is enabled and the WSM is reset preventing any blocks from being

programmed or erased, therefore providing data protection during power

Ý

transitions. When RP transitions from logic low to logic high, the flash memory

enters the read-array mode.

Ý

OE

I

OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

Ý

read cycle. OE is active low.

Ý

WE

WRITE ENABLE: Controls writes to the Command Register and array blocks. WE

Ý

is active low. Addresses and data are latched on the rising edge of the WE pulse.

V

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or

programming data in each block.

PP

k

Note: V

V

memory contents cannot be altered.

PPLMAX

PP

g

V

DEVICE POWER SUPPLY (3.3V 0.3V, 5V 10%)

GROUND: For all internal circuitry

CC

GND

NC

NO CONNECT: Pin may be driven or left floating

DON’T USE PIN: Pin should not be connected to anything

DU

10

28F200BL-T/B, 28F002BL-T/B

2.0 28F200BL PRODUCTS DESCRIPTION

Figure 6. 28F200BL Word/Byte-Wide Block Diagram

11

28F200BL-T/B, 28F002BL-T/B

2.1.1.3 Main Block Operation

2.1 28F200BL Memory Organization

Two main blocks of memory exist on the 28F200BL

(1 x 128-Kbyte block and 1 x 96-Kbyte blocks). See

the following section on Block Memory Map for the

address location of these blocks for the 28F200BL-T

and 28F200BL-B products.

2.1.1 BLOCKlNG

The 28F200BL uses a blocked array architecture to

provide independent erasure of memory blocks. A

block is erased independently of other blocks in the

array when an address is given within the block ad-

dress range and the Erase Setup and Erase Confirm

commands are written to the CUI. The 28F200BL is

a random read/write memory, only erasure is per-

formed by block.

2.1.2 BLOCK MEMORY MAP

Two versions of the 28F200BL product exist to sup-

port two different memory maps of the array blocks

in order to accommodate different micropro- cessor

protocols for boot code location. The 28F200BL-T

memory map is inverted from the 28F200BL-B mem-

ory map.

2.1.1.1 Boot Block Operation and Data

Protection

The 16-Kbyte boot block provides a lock feature for

secure code storage. The intent of the boot block is

to provide a secure storage area for the kernel code

that is required to boot a system in the event of pow-

er failure or other disruption during code update.

This lock feature ensures absolute data integrity by

preventing the boot block from being written or

2.1.2.1 28F200BL-B Memory Map

The 28F200BL-B device has the 16-Kbyte boot

block located from 00000H to 01FFFH to accom-

modate those microprocessors that boot from the

bottom of the address map at 00000H. In the

28F200BL-B the first 8-Kbyte parameter block re-

sides in memory space from 02000H to 02FFFH.

The second 8-Kbyte parameter block resides in

memory space from 03000H to 03FFFH. The

96-Kbyte main block resides in memory space from

04000H to 0FFFFH. The 128-Kbyte main block re-

sides in memory space from 10000H to 1FFFFH

(word locations). See Figure 7.

Ý

erased when RP is not at 12V. The boot block can

be erased and written when RP is held at 12V for

Ý

the duration of the erase or program operation. This

allows customers to change the boot code when

necessary while providing security when needed.

See the Block Memory Map section for address lo-

cations of the boot block for the 28F200BL-T and

28F200BL-B.

(Word Addresses)

1FFFFH

2.1.1.2 Parameter Block Operation

The 28F200BL has 2 parameter blocks (8 Kbytes

each). The parameter blocks are intended to pro-

vide storage for frequently updated system parame-

ters and configuration or diagnostic information. The

parameter blocks can also be used to store addition-

al boot or main code. The parameter blocks howev-

er, do not have the hardware write protection feature

that the boot block has. The parameter blocks pro-

vide for more efficient memory utilization when deal-

ing with parameter changes versus regularly blocked

devices. See the Block Memory Map section for ad-

dress locations of the parameter blocks for the

28F200BL-T and 28F200BL-B.

128-Kbyte MAIN BLOCK

10000H

0FFFFH

96-Kbyte MAIN BLOCK

04000H

03FFFH

8-Kbyte PARAMETER BLOCK

03000H

02FFFH

8-Kbyte PARAMETER BLOCK

02000H

01FFFH

16-Kbyte BOOT BLOCK

00000H

Figure 7. 28F200BL-B Memory Map

12

28F200BL-T/B, 28F002BL-T/B

2.1.2.2 28F200BL-T Memory Map

(Word Addresses)

1FFFFH

The 28F200BL-T device has the 16-Kbyte boot

block located from 1E000H to 1FFFFH to accommo-

date those microprocessors that boot from the top

of the address map. In the 28F200BL-T the first

8-Kbyte parameter block resides in memory space

from 1D000H to 1DFFFH. The second 8-Kbyte pa-

rameter block resides in memory space from

1C000H to 1CFFFH. The 96-Kbyte main block re-

sides in memory space from 10000H to 1BFFFH.

The 128-Kbyte main block resides in memory space

from 00000H to 0FFFFH as shown below in Figure

8.

16-Kbyte BOOT BLOCK

1E000H

1DFFFH

8-Kbyte PARAMETER BLOCK

1D000H

1CFFFH

1C000H

1BFFFH

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

10000H

0FFFFH

00000H

Figure 8. 28F200BL-T Memory Map

13

28F200BL-T/B, 28F002BL-T/B

3.0 28F002BL PRODUCTS DESCRIPTION

Figure 9. 28F002BL Byte-Wide Block Diagram

14

28F200BL-T/B, 28F002BL-T/B

See the following section on Block Memory Map for

the address location of these blocks for the

28F002BL-T and 28F002BL-B.

3.1 28F002BL Memory Organization

3.1.1 BLOCKING

The 28F002BL uses a blocked array architecture to

provide independent erasure of memory blocks. A

block is erased independently of other blocks in the

array when an address is given within the block ad-

dress range and the Erase Setup and Erase Confirm

commands are written to the CUI. The 28F002BL is

a random read/write memory, only erasure is per-

formed by block.

3.1.2 BLOCK MEMORY MAP

Two versions of the 28F002BL product exist to sup-

port two different memory maps of the array blocks

in order to accommodate different microprocessor

protocols for boot code location. The 28F002BL-T

memory map is inverted from the 28F002BL-B mem-

ory map.

3.1.2.1 28F002BL-B Memory Map

3.1.1.1 Boot Block Operation and Data

Protection

The 28F002BL-B device has the 16-Kbyte boot

block located from 00000H to 03FFFH to accommo-

date those microprocessors that boot from the bot-

tom of the address map at 00000H. In the

28F002BL-B the first 8-Kbyte parameter block re-

sides in memory from 04000H to 05FFFH. The sec-

ond 8-Kbyte parameter block resides in memory

space from 06000H to 07FFFH. The 96-Kbyte main

block resides in memory space from 08000H to

1FFFFH. The 128-Kbyte main block resides in mem-

ory space from 20000H to 3FFFFH. See Figure 10.

The 16-Kbyte boot block provides a lock feature for

secure code storage. The intent of the boot block is

to provide a secure storage area for the kernel code

that is required to boot a system in the event of pow-

er failure or other disruption during code update.

This lock feature ensures absolute data integrity by

preventing the boot block from being programmed

Ý

or erased when RP is not at 12V. The boot block

can be erased and programmed when RP is held

Ý

at 12V for the duration of the erase or program oper-

ation. This allows customers to change the boot

code when necessary while still providing security

when needed. See the Block Memory Map section

for address locations of the boot block for the

28F002BL-T and 28F002BL-B.

3FFFFH

128-Kbyte MAIN BLOCK

20000H

1FFFFH

3.1.1.2 Parameter Block Operation

The 28F002BL has 2 parameter blocks (8 Kbytes

each). The parameter blocks are intended to pro-

vide storage for frequently updated system parame-

ters and configuration or diagnostic information. The

parameter blocks can also be used to store addition-

al boot or main code. The parameter blocks howev-

er, do not have the hardware write protection feature

that the boot block has. Parameter blocks provide

for more efficient memory utilization when dealing

with small parameter changes versus regularly

blocked devices. See the Block Memory Map sec-

tion for address locations of the parameter blocks

for the 28F002BL-T and 28F002BL-B.

96-Kbyte MAIN BLOCK

08000H

07FFFH

8-Kbyte PARAMETER BLOCK

06000H

05FFFH

8-Kbyte PARAMETER BLOCK

04000H

03FFFH

16-Kbyte BOOT BLOCK

00000H

Figure 10. 28F002BL-B Memory Map

3.1.1.3 Main Block Operation

Two main blocks of memory exist on the 28F002BL

(1 x 128-Kbyte block and 1 x 96-Kbyte block).

15

28F200BL-T/B, 28F002BL-T/B

3.1.2.2 28F002BL-T Memory Map

The CUI allows for fixed power supplies during era-

sure and programming, and maximum EPROM com-

patibility.

The 28F002BL-T device has the 16-Kbyte boot

block located trom 3C000H to 3FFFFH to accom-

modate those microprocessors that boot from the

top of the address map. In the 28F002BL-T the first

8-Kbyte parameter block resides in memory space

from 3A000H to 3BFFFH. The second 8-Kbyte pa-

rameter block resides in memory space from

38000H to 39FFFH. The 96-Kbyte main block re-

sides in memory space from 20000H to 37FFFH.

The 128-Kbyte main block resides in memory space

from 00000H to 1FFFFH.

In the absence of high voltage on the V pin, the

PP

2-Mbit flash family will only successfully execute the

following commands: Read Array, Read Status Reg-

ister, Clear Status Register and Intelligent ldentifier

mode. The device provides standard EPROM read,

standby and output disable operations. Manufactur-

er Identification and Device Identification data can

be accessed through the CUI or through the stan-

dard EPROM A9 high voltage access (V ) (for

ID

PROM programmer equipment).

3FFFFH

The same EPROM read, standby and output disable

functions are available when high voltage is applied

to the V pin. In addition, high voltage on V al-

lows write and erase of the device. All functions as-

sociated with altering memory contents: write and

erase, Intelligent Identifier read and Read Status are

accessed via the CUI.

16-Kbyte BOOT BLOCK

PP

3C000H

3BFFFH

8-Kbyte PARAMETER BLOCK

3A000H

39FFFH

8-Kbyte PARAMETER BLOCK

38000H

37FFFH

The purpose of the Write State Machine (WSM) is to

completely automate the write and erasure of the

device. The WSM will begin operation upon receipt

of a signal from the CUI and will report status back

through a Status Register. The CUI will handle the

96-Kbyte MAIN BLOCK

20000H

1FFFFH

Ý

WE interface to the data and address latches, as

128-Kbyte MAIN BLOCK

well as system software requests for status while the

WSM is in operation.

00000H

Figure 11. 28F002BL-T Memory Map

4.1 28F200BL Bus Operations

Flash memory reads, erases and writes in-system

via the local CPU. All bus cycles to or from the flash

memory conform to standard microprocessor bus

cycles.

4.0 PRODUCT FAMILY PRINCIPLES

OF OPERATION

Flash memory augments EPROM functionality with

in-circuit electrical write and erase. The 2-Mbit flash

family utilizes a Command User Interface (CUI) and

internally generated and timed algorithms to simplify

write and erase operations.

16

28F200BL-T/B, 28F002BL-T/B

e

Ý

Table 1. Bus Operations for WORD-WIDE Mode (BYTE

V

)

IH

Ý

WE

Mode

Notes

RP

CE

OE

A

0

V

PP

DQ

0–15

9

Read

1, 2

V

X

D

OUT

IH

IL

IH

Output Disable

V

IH

X

High Z

0089H

IH

IL

IH

Standby

V

IH

X

Deep Power-Down

Intelligent Identifier (Mfr)

Intelligent Identifier (Device)

9

V

X

IL

IH

3, 4

V

IL

V

IL

V

IL

IH

ID

IL

3, 4, 5,

10

V

2274H

2275H

ID

IH

Write

6, 7, 8

V

IL

V

IL

X

D

IN

IH

e

Ý

Table 2. Bus Operations for BYTE-WIDE Mode (BYTE

V

)

IL

Ý

WE

Mode

Notes RP

CE

OE

A

V

DQ

8–14

b

X

9

0

1

PP

0–7

Read

1, 2, 3

V

X

D

OUT

High Z

IH

IL

IH

Output Disable

Standby

V

IH

X

High Z High Z

IH

IL

V

X

IH

Deep Power-Down

9

V

X

IL

Intelligent Identifier

(Mfr)

3, 4

V

89H

High Z

IH

IL

IH

ID

IL

Intelligent Identifier 3, 4, 5

(Device)

V

X

74H

75H

IH

ID

IH

Write

6, 7, 8

V

IL

X

D

IN

NOTES:

1. Refer to DC Characteristics.

2. X can be V or V for control pins and addresses, V

IL IH

or V

for V

.

PP

PPL

PPH

3. See DC characteristics for V

, V

, V , V voltages.

4. Manufacturer and Device codes may also be accessed via a CPU write sequence. A –A

PPL PPH HH ID

e

V .

IL

1

16

e

6. Refer to Table 4 for valid D during a write operation.

5. Device ID

2274H for 28F200BL-T and 2275H for 28F200BL-B.

IN

7. Command writes for Block Erase or Word/Byte Write are only executed when V

e

V

.

PP

PPH

Ý

8. To write or erase the boot block, hold RP at V

.

HH

9. RP must be at GND 0.2V to meet the 1.2 mA maximum deep power-down current.

10. The device ID codes are identical to those of the 28F200BX 5V versions and SmartVoltage equivalents.

Ý

g

17

28F200BL-T/B, 28F002BL-T/B

4.2 28F002BL Bus Operations

Table 3. Bus Operations

Ý

WE

Mode

Notes

RP

CE

OE

A

0

V

DQ

0–7

9

PP

Read

1, 2

V

X

D

OUT

IH

IL

IH

Output Disable

V

IH

X

High Z

89H

IH

IL

IH

Standby

V

X

IH

Deep Power-Down

Intelligent Identifier (Mfr)

Intelligent Identifier (Device)

9

V

X

IL

IH

3, 4

V

IL

IH

ID

IL

3, 4, 5

V

7CH

7DH

IH

Write

6, 7, 8

V

IH

V

IH

V

IL

X

D

IN

IL

NOTES:

1. Refer to DC Characteristics.

2. X can be V or V for control pins and addresses, V

, V

or V

for V

.

PP

IL IH

3. See DC characteristics for V

PPL

, V , V voltages.

PPH

PPL PPH HH ID

4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A –A

e

V .

IL

1

17

e

6. Refer to Table 4 for valid D during a write operation.

5. Device ID

7CH for 28F002BL-T and 7DH for 28F002BL-B.

IN

7. Command writes for Block erase or byte program are only executed when V

e

V

PPH

.

PP

Ý

8. Program or erase the Boot block by holding RP at V

.

HH

9. RP must be at GND 0.2V to meet the 1.2 mA maximum deep power-down current.

10. The device ID codes are identical to those of the 28F002BX 5V versions and SmartVoltage equivalents.

Ý

g

4.3.1.2 Input Control

4.3 Read Operations

Ý

With WE at logic-high level (V ), input to the de-

vice is disabled. Data Input/Output pins (DQ 0:15

The 2-Mbit flash family has three user read modes;

Array, Intelligent Identifier, and Status Register.

Status Register read mode will be discussed in detail

in the ‘‘Write Operations’’ section.

IH

[

]

[

]

Ý

or DQ 0:7 ) are controlled by OE .

4.3.2 INTELLIGENT lDENTlFlERS

28F200BL Products

During power-up conditions (V supply ramping), it

at 3.0V mini-

CC

takes a maximum of 600 ns from V

CC

mum to obtain valid data on the outputs.

The manufacturer and device codes are read via the

CUI or by taking the A pin to 12V. Writing 90H to

4.3.1 READ ARRAY

9

the CUI places the device into Intelligent Identifier

read mode. A read of location 00000H outputs the

manufacturer’s identification code, 0089H, and loca-

tion 00001H outputs the device code; 2274H for

If the memory is not in the Read Array mode, it is

necessary to write the appropriate read mode com-

mand to the CUI. The 2-Mbit flash family has three

control functions, all of which must be logically ac-

Ý

28F200BL-T, 2275H for 28F200BL-B. When BYTE

is at a Iogic low only the lower byte of the above

signatures is read and DQ /A is a ‘‘don’t care’’

Ý

is the device selection control. Power-Down RP is

tive, to obtain data at the outputs. Chip-Enable CE

Ý

the device power control. Output-Enable OE is the

b

15

1

Ý

during Intelligent Identifier mode. A read array com-

mand must be written to the CUI to return to the

read array mode.

[

]

[

]

DATA INPUT/OUTPUT (DQ 0:15 or DQ 0:7 ) direc-

tion control and when active is used to drive data

from the selected memory on to the I/O bus.

4.3.1.1 Output Control

Ý

With OE at logic-high level (V ), the output from

the device is disabled and data input/output pins

IH

[

]

[

(DQ 0:15 or DQ 0:7 ) are tri-stated. Data input is

then controlled by WE

]

Ý

.

18

28F200BL-T/B, 28F002BL-T/B

28F002BL Products

4.4.1 BOOT BLOCK WRITE OPERATIONS

The manufacturer and device codes are also read

via the CUI or by taking the A pin to 12V. Writing

In the case of Boot Block modifications (write and

Ý

e

erase), RP is set to V

12V typically, in addi-

9

HH

Ý

tion to V at high voltage. However, if RP is not at

PP

90H to the CUI places the device into Intelligent

Identifier read mode. A read of location 00000H

outputs the manufacturer’s identification code, 89H,

and location 00001H outputs the device code; 7CH

for 28F002BL-T, 7DH for 28F002BL-B.

V

HH

when a program or erase operation of the boot

block is attempted, the corresponding status register

bit (Bit 4 for Program and Bit 5 for Erase, refer to

Table 5 for Status Register Definitions) is set to indi-

cate the failure to complete the operation.

4.4 Write Operations

4.4.2 COMMAND USER INTERFACE (CUI)

Commands are written to the CUI using standard mi-

croprocessor write timings. The CUI serves as the

interface between the microprocessor and the inter-

nal chip operation. The CUI can decipher Read Ar-

ray, Read Intelligent Identifier, Read Status Register,

Clear Status Register, Erase and Program com-

mands. In the event of a read command, the CUI

simply points the read path at either the array, the

Intelligent Identifier, or the status register depending

on the specific read command given. For a program

or erase cycle, the CUI informs the write state ma-

chine that a write or erase has been requested. Dur-

ing a program cycle, the Write State Machine will

control the program sequences and the CUI will only

respond to status reads. During an erase cycle, the

CUI will respond to status reads and erase suspend.

After the Write State Machine has completed its

task, it will allow the CUI to respond to its full com-

mand set. The CUI will stay in the current command

state until the microprocessor issues another com-

mand.

The Command User Interface (CUI) serves as the

interface to the microprocessor. The CUI points the

read/write path to the appropriate circuit block as

described in the previous section. After the WSM

has completed its task, it will set the WSM Status bit

to a ‘‘1’’, which will also allow the CUI to respond to

its full command set. Note that after the WSM has

returned control to the CUI, the CUI will remain in its

current state.

4.4.2.1 Command Set

Command

Device Mode

Codes

00

10

20

40

50

70

90

B0

D0

FF

Invalid/Reserved

Alternate Program Setup

Erase Setup

Program Setup

Clear Status Register

Read Status Register

Intelligent Identifier

Erase Suspend

The CUI will successfully initiate an erase or write

operation only when V is within its voltage range.

PP

Depending upon the application, the system design-

Erase Resume/Erase Confirm

Read Array

er may choose to make the V

power supply

PP

switchable, available only when memory updates

are desired. The system designer can also choose

to ‘‘hard-wire’’ V to 12V. The 2-Mbit flash family is

PP

4.4.2.2 Command Function Descriptions

designed to accommodate either design practice. It

Ý

is recommended that RP be tied to logical Reset

Device operations are selected by writing specific

commands into the CUI. Table 4 defines the 2-Mbit

flash family commands.

for data protection during unstable CPU reset func-

tion as described in the ‘‘Product Family Overview’’

section.

19

28F200BL-T/B, 28F002BL-T/B

Table 4. Command Definitions

Bus

Notes

First Bus Cycle

Second Bus Cycle

Command

Cycles

Req’d

8

1

Operation Address Data Operation Address Data

Read Array

1

3

2

1

2

Write

X

FFH

90H

70H

50H

20H

40H

Intelligent Identifier

2, 4

3

Read

IA

X

IID

Read Status Register

Clear Status Register

Erase Setup/Erase Confirm

X

SRD

X

5

BA

WA

Write

BA

D0H

WD

Word/Byte Write

Setup/Write

6, 7

WA

Erase Suspend/Erase Resume

2

Write

X

B0H

10H

Write

X

D0H

WD

Alternate Word/Byte Write

Setup/Write

2, 3, 7

WA

NOTES:

1. Bus operations are defined in Tables 1, 2, 3.

e

2. IA

Identifier Address: 00H for manufacturer code, 01H for device code.

e

3. SRD

Data read from Status Register.

Intelligent Identifier Data.

Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.

e

4. IID

e

5. BA

6. WA

WD

Address within the block being erased.

Address to be written.

Data to be written at location WA.

e

7. Either 40H or 10H commands is valid.

8. When writing commands to the device, the upper data bus DQ –DQ

to avoid burning additional current.

e

]

[

X (28F200BL-only) which is either V or V

CC SS

8

15

Invalid/Reserved

Read Status Register (70H)

These are unassigned commands. It is not recom-

mended that the customer use any command other

than the valid commands specified above. Intel re-

serves the right to redefine these codes for future

functions.

This is one of the two commands that is executable

while the state machine is operating. After this com-

mand is written, a read of the device will output the

contents of the status register, regardless of the ad-

dress presented to the device.

The device automatically enters this mode after pro-

gram or erase has completed.

Read Array (FFH)

This single write command points the read path at

Ý

the array. If the host CPU performs a CE /OE

Clear Status Register (50H)

controlled read immediately following a two-write se-

quence that started the WSM, then the device will

output status register contents. If the Read Array

command is given after Erase Setup the device is

reset to read the array. A two Read Array command

sequence (FFH) is required to reset to Read Array

after Program Setup.

The WSM can only set the Program Status and

Erase Status bits in the status register, it can not

clear them. Two reasons exist for operating the

status register in this fashion. The first is a synchro-

nization. The WSM does not know when the host

CPU has read the status register, therefore it would

not know when to clear the status bits. Secondly, if

the CPU is programming a string of bytes, it may be

more efficient to query the status register after pro-

gramming the string. Thus, if any errors exist while

programming the string, the status register will return

the accumulated error status.

Intelligent ldentifier (90H)

After this command is executed, the CUI points the

output path to the Intelligent Identifier circuits. Only

Intelligent Identifier values at addresses 0 and 1 can

be read (only address A0 is used in this mode, all

other address inputs are ignored).

20

28F200BL-T/B, 28F002BL-T/B

set the WSM Status bit to a ‘‘1’’. The WSM will con-

tinue to run, idling in the SUSPEND state, regardless

of the state of all input control pins, with the exclu-

Program Setup (40H or 10H)

This command simply sets the CUI into a state such

that the next write will load the address and data

registers. Either 40H or 10H can be used for Pro-

gram Setup. Both commands are included to ac-

commodate efforts to achieve an industry standard

command code set.

Ý

sion of RP . RP low will immediately shut down

the WSM and the remainder of the chip.

Erase Resume (D0H)

This command will cause the CUI to clear the Sus-

pend state and set the WSM Status bit to a ‘‘0’’, but

only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions.

Program

The second write after the program setup command,

will latch addresses and data. Also, the CUI initiates

the WSM to begin execution of the program algo-

rithm. While the WSM finishes the algorithm, the de-

vice will output Status Register contents. Note that

the WSM cannot be suspended during program-

ming.

4.4.3 STATUS REGlSTER

The 2-Mbit flash family contains a status register

which may be read to determine when a program or

erase operation is complete, and whether that oper-

ation completed successfully. The status register

may be read at any time by writing the Read Status

command to the CUI. After writing this command, all

subsequent Read operations output data from the

status register until another command is written to

the CUI. A Read Array command must be written to

the CUI to return to the Read Array mode.

Erase Setup (20H)

Prepares the CUI for the Erase Confirm command.

No other action is taken. If the next command is not

an Erase Confirm command then the CUI will set

both the Program Status and Erase Status bits of the

Status Register to a ‘‘1’’, place the device into the

Read Status Register state, and wait for another

command.

[

]

The status register bits are output on DQ 0:7

whether the device is in the byte-wide (x8) or word-

wide (x16) mode for the 28F200BL. In the word-wide

Erase Confirm (D0H)

[

]

mode the upper byte, DQ 8:15 is set to 00H during

a Read Status command. In the byte-wide mode,

If the previous command was an Erase Setup com-

mand, then the CUI will enable the WSM to erase, at

the same time closing the address and data latches,

and respond only to the Read Status Register and

Erase Suspend commands. While the WSM is exe-

cuting, the device will output Status Register data

[

]

DQ 8:14 are tri-stated and DQ /A

low order address function.

retains the

b

15

1

It should be noted that the contents of the status

Ý

register are latched on the falling edge of OE or

CE whichever occurs last in the read cycle. This

Ý

when OE is toggled low. Status Register data can

only be updated by toggling either OE or CE low.

prevents possible bus errors which might occur if the

contents of the status register change while reading

Ý

the status register. CE or OE must be toggled

with each subsequent status read, or the completion

of a program or erase operation will not be evident.

Erase Suspend (B0H)

This command only has meaning while the WSM is

executing an Erase operation, and therefore will only

be responded to during an erase operation. After

this command has been executed, the CUI will initi-

ate the WSM to suspend Erase operations, and then

return to responding to only Read Status Register or

to the Erase Resume commands. Once the WSM

has reached the Suspend state, it will set an output

into the CUI which allows the CUI to respond to the

Read Array, Read Status Register, and Erase Re-

sume commands. In this mode, the CUI will not re-

spond to any other commands. The WSM will also

The Status Register is the interface between the mi-

croprocessor and the Write State Machine (WSM).

When the WSM is active, this register will indicate

the status of the WSM, and will also hold the bits

indicating whether or not the WSM was successful in

performing the desired operation. The WSM sets

status bits ‘‘Three’’ through ‘‘Seven’’ and clears bits

‘‘Six’’ and ‘‘Seven’’, but cannot clear status bits

‘‘Three’’ through ‘‘Five’’. These bits can only be

cleared by the controlling CPU through the use of

the Clear Status Register command.

21

28F200BL-T/B, 28F002BL-T/B

4.4.3.1 Status Register Bit Definition

Table 5. Status Register Definitions

WSMS

7

ESS

6

ES

5

PS

4

VPPS

R

2

R

1

R

0

3

NOTES:

Write State Machine Status bit must first be checked to

determine byte/word program or block erase completion,

before the Program or Erase Status bits are checked for

success.

e

SR.7

WRITE STATE MACHINE STATUS

Ready

Busy

1

0

e

SR.6

ERASE SUSPEND STATUS

Erase Suspended

Erase in Progress/Completed

When Erase Suspend is issued, WSM halts execution

and sets both WSMS and ESS bits to ‘‘1’’. ESS bit re-

mains set to ‘‘1’’ until an Erase Resume command is is-

sued.

1

0

e

SR.5

ERASE STATUS

Error in Block Erasure

Successful Block Erase

When this bit is set to ‘‘1’’. WSM has applied the maxi-

mum number of erase pulses to the block and is still un-

able to successfully perform an erase verify.

1

0

e

SR.4

PROGRAM STATUS

Error in Byte/Word Program

Successful Byte/Word Program

When this bit is set to ‘‘1’’, WSM has attempted but failed

to Program a byte or word.

1

0

e

SR.3

V

PP

V

PP

V

PP

STATUS

Low Detect; Operation Abort

OK

The V Status bit unlike an A/D converter, does not

PP

provide continuous indication of V level. The WSM in-

terrogates the V level only after the byte write or block

PP

erase command sequences have been entered and in-

1

0

PP

forms the system if V has not been switched on. The

V

PP

Status bit is not guaranteed to report accurate feed-

PP

back between V

and V

.

PPH

PPL

e

These bits are reserved for future use and should be masked out when polling the Status Register.

SR.2–SR.0

RESERVED FOR FUTURE ENHANCEMENTS

4.4.3.2 Clearing the Status Register

4.4.4 PROGRAM MODE

Certain bits in the status register are set by the write

state machine, and can only be reset by the system

software. These bits can indicate various failure con-

ditions. By allowing the system software to control

the resetting of these bits, several operations may

be performed (such as cumulatively programming

several bytes or erasing multiple blocks in se-

quence). The status register may then be read to

determine if an error occurred during that program-

ming or erasure series. This adds flexibility to the

way the device may be programmed or erased. To

clear the status register, the Clear Status Register

command is written to the CUl. Then, any other com-

mand may be issued to the CUI. Note again that

before a read cycle can be initiated, a Read Array

command must be written to the CUI to specify

whether the read data is to come from the array,

status register, or Intelligent Identifier.

Program is executed by a two-write sequence. The

Program Setup command is written to the CUI fol-

lowed by a second write which specifies the address

and data to be programmed. The write state ma-

chine will execute a sequence of internally timed

events to:

1. program the desired bits of the addressed memo-

ry word (byte), and

2. verify that the desired bits are sufficiently pro-

grammed.

Programming of the memory results in specific bits

within a byte or word being changed to a ‘‘0’’.

If the user attempts to program ‘‘1’’s, there will be no

change of the memory cell content and no error oc-

curs.

22

28F200BL-T/B, 28F002BL-T/B

Similar to erasure, the status register indicates

whether programming is complete. While the pro-

gram sequence is executing, bit 7 of the status regis-

ter is a ‘‘0’’. The status register can be polled by

If the erasure operation was unsuccessful, Bit 5 of

the status register is set to a ‘‘1’’ to indicate an

Erase Failure. If V was not within acceptable limits

after the Erase Confirm command is issued, the

WSM will not execute an erase sequence; instead,

Bit 5 of the status register is set to a ‘‘1’’ to indicate

an Erase Failure, and Bit 3 is set to a ‘‘1’’ to identify

PP

Ý

toggling either CE or OE to determine when the

program sequence is complete. Only the Read

Status Register command is valid while program-

ming is active.

that V

limits.

supply voltage was not within acceptable

PP

When programming is complete, the status bits,

which indicate whether the program operation was

successful, should be checked. If the programming

operation was unsuccessful, Bit 4 of the status regis-

ter is set to a ‘‘1’’ to indicate a Program Failure. If

Bit 3 is set then V was not within acceptable limits,

PP

and the WSM will not execute the programming se-

quence.

The status register should be cleared before at-

tempting the next operation. Any CUI instruction can

follow after erasure is completed; however, it must

be recognized that reads from the memory array,

status register, or Intelligent Identifier can not be ac-

complished until the CUI is given the appropriate

command. A Read Array command must first be giv-

en before memory contents can be read.

The status register should be cleared before at-

tempting the next operation. Any CUI instruction can

follow after programming is completed; however, it

must be recognized that reads from the memory,

status register, or Intelligent Identifier cannot be ac-

complished until the CUI is given the appropriate

command. A Read Array command must first be giv-

en before memory contents can be read.

Figure 14 shows a system software flowchart for

Block Erase operation.

4.4.5.1 Suspending and Resuming Erase

Since an erase operation typically requires 2 to 5

seconds to complete, an Erase Suspend command

is provided. This allows erase-sequence interruption

in order to read data from another block of the mem-

ory. Once the erase sequence is started, writing the

Erase Suspend command to the CUI requests that

the Write State Machine (WSM) pause the erase se-

quence at a predetermined point in the erase algo-

rithm. The status register must be read to determine

when the erase operation has been suspended.

Figure 12 shows a system software flowchart for de-

vice byte programming operation. Figure 13 shows a

similar flowchart for device word programming oper-

ation (28F200BL-only).

4.4.5 ERASE MODE

Erasure of a single block is initiated by writing the

Erase Setup and Erase Confirm commands to the

At this point, a Read Array command can be written

to the CUI in order to read data from blocks other

than that which is being suspended. The only other

valid command at this time is the Erase Resume

command or Read Status Register operation.

[

]

CUI, along with the addresses, A 12:16 for the

[

]

28F200BL or A 12:17 for the 28F002BL, identifying

the block to be erased. These addresses are latched

internally when the Erase Confirm command is is-

sued. Block erasure results in all bits within the block

being set to ‘‘1’’.

Figure 15 shows a system software flowchart detail-

ing the operation.

The WSM will execute a sequence of internally

timed events to:

During Erase Suspend mode, the chip can go into a

Ý

pseudo-standby mode by taking CE to V and the

active current is now a maximum of 6 mA. If the chip

IH

1. program all bits within the block

2. verify that all bits within the block are sufficiently

programmed

Ý

is enabled while in this mode by taking CE to V

,

IL

the Erase Resume command can be issued to re-

sume the erase operation.

3. erase all bits within the block and

4. verify that all bits within the block are sufficiently

erased

Upon completion of reads from any block other than

the block being erased, the Erase Resume com-

mand must be issued. When the Erase Resume

command is given, the WSM will continue with the

erase sequence and complete erasing the block. As

with the end of erase, the status register must be

read, cleared, and the next instruction issued in or-

der to continue.

While the erase sequence is executing, Bit 7 of the

status register is a ‘‘0’’.

When the status register indicates that erasure is

complete, the status bits, which indicate whether the

erase operation was successful, should be checked.

23

28F200BL-T/B, 28F002BL-T/B

4.4.6 EXTENDED CYCLlNG

gram/erase cycles on each of the five blocks. The

combination of low electric fields, clean oxide pro-

cessing and minimized oxide area per memory cell

subjected to the tunneling electric field, results in

very high cycling capability.

Intel has designed extended cycling capability into

its ETOX Ill flash memory technology. The 2-Mbit

low voltage flash family is designed for 10,000 pro-

Bus

Command

Comments

Operation

e

40H

Write

Setup

Data

e

programmed

Program

Address

Byte to be

Write

Program

Data to be programmed

e

programmed

Address

Byte to be

Read

Status Register Data.

Ý

Toggle OE or CE to update

Status Register

Standby

Check SR.7

e

Busy

1

Ready, 0

Repeat for subsequent bytes.

Full status check can be done after each byte or after a

sequence of bytes.

Write FFH after the last byte programming operation to

reset the device to Read Array Mode.

290449–8

Full Status Check Procedure

Bus

Operation

Command

Comments

Standby

Check SR.3

e

1

V

Low Detect

PP

Standby

Check SR.4

e

1

Byte Program Error

SR.3 MUST be cleared, if set during a program attempt,

before further attempts are allowed by the Write State

Machine.

SR.4 is only cleared by the Clear Status Register

Command, in cases where multiple bytes are programmed

before full status is checked.

290449–9

If error is detected, clear the Status Register before

attempting retry or other error recovery.

Figure 12. Automated Byte Programming Flowchart

24

28F200BL-T/B, 28F002BL-T/B

Bus

Command

Comments

Operation

e

40H

Write

Setup

Data

e

programmed

Program

Address

Word to be

Program

Data to be programmed

e

programmed

Address

Word to be

Read

Status Register Data.

Ý

Toggle OE or CE to update

Status Register

Standby

Check SR.7

e

Busy

1

Ready, 0

Repeat for subsequent words.

Full status check can be done after each word or after a

sequence of words.

Write FFH after the last word programming operation to

reset the device to Read Array Mode.

290449–10

Full Status Check Procedure

Bus

Command

Comments

Operation

Standby

Check SR.3

e

1

V

Low Detect

PP

Standby

Check SR.4

e

1

Word Program Error

SR.3 MUST be cleared, if set during a program attempt,

before further attempts are allowed by the Write State

Machine.

290449–11

SR.4 is only cleared by the Clear Status Register

Command, in cases where multiple words are programmed

before full status is checked.

If error is detected, clear the Status Register before

attempting retry or other error recovery.

Figure 13. Automated Word Programming Flowchart

25

28F200BL-T/B, 28F002BL-T/B

Bus

Command

Comments

Operation

e

20H

Write

Setup

Erase

Data

e

Address

erased

Within block to be

e

D0H

Erase

Data

e

Address

erased

Within block to be

Read

Status Register Data.

Ý

Toggle OE or CE to update

Status Register

Standby

Check SR.7

e

Busy

1

Ready, 0

Repeat for subsequent blocks.

Full status check can be done after each block or after a

sequence of blocks.

Write FFH after the last block erase operation to reset the

device to Read Array Mode.

290449–12

Full Status Check Procedure

Bus

Command

Comments

Operation

Standby

Check SR.3

e

1

V

Low Detect

PP

Standby

Check SR.4,5

e

Both 1

Error

Command Sequence

Check SR.5

e

1

Block Erase Error

SR.3 MUST be cleared, if set during an erase attempt,

before further attempts are allowed by the Write State

Machine.

290449–13

SR.5 is only cleared by the Clear Status Register

Command, in cases where multiple blocks are erased

before full status is checked.

If error is detected, clear the Status Register before

attempting retry or other error recovery.

Figure 14. Automated Block Erase Flowchart

26

28F200BL-T/B, 28F002BL-T/B

Bus

Command

Comments

Operation

e

Write

Read

Erase

Data

B0H

Suspend

Status Register Data.

Ý

Toggle OE or CE to

update Status Register

Standby

Check SR.7

e

1

Ready

Standby

Write

Check SR.6

e

1

Suspended

e

FFH

Read Array

Data

Read

Write

Read array data from block

other than that being

erased.

e

Erase Resume Data

D0H

290449–14

Figure 15. Erase Suspend/Resume Flowchart

memory array, PRC logic controls the device’s pow-

er consumption by entering the APS mode where

4.5 Power Consumption

typical I

current is 0.8 mA and maximum I

cur-

CC

4.5.1 ACTlVE POWER

rent is 2 mA. The device stays in this static state with

outputs valid until a new memory location is read.

Ý

With CE at a logic-low level and RP at a logic-

high level, the device is placed in the active mode.

The device I

5 MHz.

current is a maximum of 22 mA at

4.5.3 STANDBY POWER

CC

Ý

With CE at a logic-high level (V ), and the CUI in

read mode, the memory is placed in standby mode

IH

4.5.2 AUTOMATlC POWER SAVlNGS

where the maximum I

standby current is 120 mA

CC

with CMOS input signals. The standby operation dis-

ables much of the device’s circuitry and substantially

reduces device power consumption. The outputs

Automatic Power Savings (APS) is a low power fea-

ture during active mode of operation. The 2-Mbit

flash family of products incorporate Power Reduc-

tion Control (PRC) circuitry which basically allows

the device to put itself into a low current state when

it is not being accessed. After data is read from the

[

]

[

(DQ 0:15 or DQ 0:7 ) are placed in a high-imped-

ance state independent of the status of the OE

]

Ý

signal. When the 2-Mbit flash family is deselected

during erase or program functions, the devices will

27

28F200BL-T/B, 28F002BL-T/B

continue to perform the erase or program function

and consume program or erase active power until

program or erase is completed.

A system designer must guard against spurious

writes for V voltages above V when V is

CC

LKO

PP

active. Since both WE and CE must be low for a

Ý

command write, driving either signal to V will inhibit

IH

writes to the device. The CUI architecture provides

an added level of protection since alteration of mem-

ory contents can only occur after successful com-

pletion of the two-step command sequences. Finally

4.5.4 RESET/DEEP POWER-DOWN

The 2-Mbit flash family supports a typical I

of

CC

0.2 mA in deep power-down mode. One of the target

markets for these devices is in portable equipment

where the power consumption of the machine is of

prime importance. The 2-Mbit flash family has a

Ý

the device is disabled until RP is brought to V

,

IH

regardless of the state of its control inputs. This fea-

ture provides yet another level of memory protec-

tion.

Ý

RP pin which places the device in the deep power-

down mode. When RP is at a logic-low (GND

Ý

g

0.2V), all circuits are turned off and the device typ-

ically draws 0.2 mA of V current.

4.7 Power Supply Decoupling

CC

Flash memory’s power switching characteristics re-

quire careful device decoupling methods. System

designers are interested in 3 supply current issues:

Ý

During read modes, the RP pin going low dese-

lects the memory and places the output drivers in a

high impedance state. Recovery from the deep pow-

er-down state, requires a maximum of 600 ns to ac-

Standby current levels (I

Active current levels (I

)

#

CCS

)

cess valid data (t

).

CCR

PHQV

Transient peaks produced by falling and rising

Ý

During erase or program modes, RP low will abort

either erase or program operation. The contents of

the memory are no longer valid as the data has been

Ý

corrupted by the RP function. As in the read mode

above, all internal circuitry is turned off to achieve

edges of CE

.

Transient current magnitudes depend on the device

outputs’ capacitive and inductive loading. Two-line

control and proper decoupling capacitor selection

will suppress these transient voltage peaks. Each

flash device should have a 0.1 mF ceramic capacitor

the 0.2 mA current level.

Ý

RP transitions to V or turning power off to the

device will clear the status register.

IL

connected between each V

and GND, and be-

tween its V and GND. These high frequency, low-

CC

PP

inherent inductance capacitors should be placed as

close as possible to the package leads.

Ý

The use of RP during system reset is important

with automated write/erase devices. When the sys-

tem comes out of reset, it expects to read from the

flash memory. Automated flash memories provide

status information when accessed during write/

erase modes. If a CPU reset occurs with no flash

memory reset, proper CPU initialization would not

occur because the flash memory would be providing

the status information instead of array data. Intel’s

Flash Memories allow proper CPU initialization fol-

4.7.1

V TRACE ON PRINTED CIRCUIT

PP

BOARDS

Writing to flash memories while they reside in the

target system, requires special consideration of the

V

PP

designer. The V

power supply trace by the printed circuit board

pin supplies the flash memory

PP

cell’s current for programming and erasing. One

should use similar trace widths and layout consider-

Ý

lowing a system reset through the use of RP input.

In this application, RP is controlled by the same

Ý

RESET signal that resets the system CPU.

Ý

ations given to the V

quate V

power supply trace. Ade-

supply traces and decoupling will de-

CC

PP

crease spikes and overshoots.

4.6 Power-Up Operation

Ý

V , V AND RP TRANSITIONS

CC PP

4.7.2

The 2-Mbit flash family is designed to offer protec-

tion against accidental block erasure or program-

ming during power transitions. Upon power-up the

2-Mbit flash family is indifferent as to which power

The CUI latches commands as issued by system

Ý

or CE tran-

software and is not altered by V

PP

sitions or WSM actions. Its state upon power-up, af-

ter exit from deep power-down mode or after V

supply, V

or V , powers-up first. Power supply

PP CC

sequencing is not required.

CC

(Lockout voltage), is Read

LKO

transitions below V

Array mode.

The 2-Mbit flash family ensures the CUI is reset to

the read mode on power-up.

After any word/byte write or block erase operation is

complete and even after V transitions down to

PP

, the CUI must be reset to Read Array mode via

In addition, on power-up the user must either drop

V

PPL

Ý

CE low or present a new address to ensure valid

data at the outputs.

the Read Array command when accesses to the

flash memory are desired.

28

28F200BL-T/B, 28F002BL-T/B

V

Program Voltage with Respect

to GND during Block Erase

PP

5.0 OPERATING SPECIFICATIONS

(2, 3)

(2)

b

a

and Word/Byte Write ÀÀÀÀÀ 2.0V to 14.0V

Absolute Maximum Ratings

Supply Voltage

CC

b

a

with Respect to GND ÀÀÀÀÀÀÀÀ 2.0V to 7.0V

Operating Temperature

During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20 C to 70 C

(4)

Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA

(1)

b

a

§

During Block Erase and

Word/Byte WriteÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice.

§

Temperature Under BiasÀÀÀÀÀÀÀÀÀ 20 C to 80 C

§

b

a

§

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 125 C

*WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

b

a

§

Voltage on Any Pin

(except V , V , A and RP

with Respect to GND ÀÀÀÀÀÀÀÀ 2.0V to 7.0V

Ý

b

)

CC PP

9

(2)

a

Ý

Voltage on Pin RP or Pin A

with Respect to GND ÀÀÀÀÀÀÀ 2.0V to 13.5V

9

(2, 3)

b

OPERATING CONDITIONS

Symbol

Parameter

Notes

Min

Max

Unit

b

a

70

T

A

Operating Temperature

20

C

§

V

Supply Voltage

3.00

4.50

3.60

5.50

V

CC

5

V

NOTES:

1. Operating temperature is for commercial product defined by this specification.

b

2. Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods

a

k

20 ns. Maximum DC voltage on input/output pins is V

2.0V for periods 20 ns.

a

0.5V which, during transitions, may overshoot to V

CC

k

3. Maximum DC voltage on V may overshoot to 14.0V for periods 20 ns. Maximum DC voltage on RP or A may

k

a

Ý

PP

overshoot to 13.5V for periods 20 ns.

9

k

4. Output shorted for no more than one second. No more than one output shorted at a time.

5. AC Specifications are valid at both voltage ranges. See DC Characteristics table for voltage range-specific specifications.

DC CHARACTERISTICS

e

g

3.3V 0.3V

V

CC

Symbol

Parameter

Notes Min Typ Max Unit

Test Condition

e

g

I

Input Load Current

1

1.0 mA

V

Max

or GND

LI

CC

e

V

IN

CC

e

g

Output Leakage Current

1

10 mA

V

CC

Max

LO

CCS

CC

e

V

or GND

OUT

CC

e

V

Standby Current

1, 3

45

120

mA

V

CC

CE

V

CC

Max

e

CC

e

Ý

g

0.2V

RP

V

CC

IH

e

V

CC

CE

V

Max

CC

e

Ý

e

Ý

RP

e

Ý

g

GND 0.2V

I

V

Deep Power-down Current

Read Current for

1

0.20 1.2

mA RP

CCD

CC

e

5 MHz, I

e

Ý

1, 5,

6

15

25

mA

V

Max, CE

GND

CCR

CC

e

CC

28F200BL Word-Wide and

Byte-Wide Mode and

28F002BL Byte-Wide Mode

e

0 mA

OUT

f

CMOS Inputs

e

5 MHz, I

e

V

Ý

15

25

mA

V

Max, CE

CC

IL

e

TTL Inputs

e

0 mA

f

OUT

29

28F200BL-T/B, 28F002BL-T/B

DC CHARACTERISTICS (Continued)

e

g

3.3V 0.3V

V

CC

Symbol

Parameter

Notes

1, 4

Min

Typ

Max

30

20

6

Unit

Test Condition

I

V

CC

V

CC

V

CC

Word/Byte Write Current

Block Erase Current

Erase Suspend Current

mA Word/Byte Write in Progress

mA Block Erase in Progress

CCW

CCE

1, 4

e

V

IH

Ý

1, 2

3

mA CE

CCES

Block Erase Suspended

s

g

I

V

Standby Current

Deep

1

15

mA

V

CC

PPS

PPD

PP

e

Ý

g

5.0

mA RP

GND 0.2V

l

V

CC

PP

Power-down Current

I

V

PP

V

PP

Read Current

1

200

40

mA

V

PP

PPR

e

V

PPH

Word Write Current

1, 4

mA V

PPW

PP

Word Write in Progress

e

V

PPH

I

V

Byte Write Current

1, 4

1

30

mA V

PPW

PPE

PP

Byte Write in Progress

e

V

PPH

Block Erase Current

Erase Suspend Current

mA V

PP

Block Erase in Progress

e

V

PPH

200

500

mA

V

PPES

PP

Block Erase Suspended

e

V

HH

Ý

RP Boot Block

Unlock Current

Ý

1, 4

mA RP

Ý

RP

ID

e

A

Intelligent Identifier Current 1, 4

Intelligent Identifier Voltage

500

13.0

0.6

mA

V

A

V

ID

9

V

11.4

12.0

ID

b

0.5

2.0

Input Low Voltage

Input High Voltage

Output Low Voltage

V

IL

a

CC

V

0.5

V

IH

OL

e

0.4

V

CC

2 mA

Min

CC

I

OL

e

V

Output High Voltage (TTL)

2.4

V

OH1

OH2

CC

e b

I

2 mA

OH

e

Output High Voltage

(CMOS)

0.85 V

V

Min

CC

e b

I

2.5 mA

OH

b

e

V

CC

0.4

V

Min

2.5 mA

CC

e b

I

OH

V

during Normal Operations

during Erase/Write

3

0.0

4.1

V

PPL

PPH

PP

11.4

12.0

12.6

PP

Operations

V

CC

Erase/Write Lock Voltage

1.7

V

LKO

HH

Ý

RP Unlock Voltage

11.4

13.0

Boot Block Write/Erase

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

are valid for all product versions (packages and speeds).

e

12.0V, T 25 C. These currents

3.3V, V

§

CC

PP

2. I

is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum

.

CCR

CCES

of I

and I

CCES

3. Block Erases and Word/Byte Writes are inhibited when V

e

V

PPL

and not guaranteed in the range between V and

PPH

PP

V

4. Sampled, not 100% tested.

.

PPL

5. Automatic Power Savings (APS) reduces I

g

to less than 1 mA in static operation.

CCR

g

6. CMOS Inputs are either V

0.2V or GND 0.2V. TTL Inputs are either V or V .

IL IH

CC

30

28F200BL-T/B, 28F002BL-T/B

(1)

e

1 MHz

CAPACITANCE

T

A

25 C, f

§

Symbol

Parameter

Input Capacitance

Output Capacitance

Typ

6

Max

8

Unit

pF

Condition

e

C

V

0V

IN

e

10

12

pF

0V

OUT

NOTE:

1. Sampled, not 100% tested.

DC CHARACTERISTICS

(4)

e

g

5.0V 10%

V

CC

Symbol

Parameter

Notes Min Typ Max Unit

Test Condition

e

g

I

Input Load Current

1

1.0 mA

V

Max

CC

or GND

LI

CC

e

V

IN

CC

e

g

Output Leakage Current

1

10 mA

V

Max

CC

or GND

CC

LO

CCS

CC

e

V

OUT

e

V

CC

Standby Current

1.5

mA

V

CC

CE

V

Max

CC

e

Ý

RP

V

IH

e

100

1.2

40

mA

V

CC

CE

V

Max

CC

e

Ý

e

Ý

g

RP

0.2V

CC

e

Ý

g

GND 0.2V

I

V Deep Power-down

CC

Current

1

mA RP

CCD

e

5 MHz, I

e

Ý

V

CC

Read Current for

mA

V

CC

V Max, CE

CC

GND

CCR

28F200BL Word-Wide and

Byte-Wide Mode and

28F002BL

e

0 mA

OUT

f

CMOS Inputs

e

5 MHz, I

e

V

Ý

40

V

CC

V

Max, CE

CC

IL

e

TTL Inputs

e

0 mA

f

OUT

I

V

CC

V

CC

V

CC

Word-Byte Write Current

Block Erase Current

1, 4

1, 2

70

30

10

mA Word or Byte Write in Progress

mA Block Erase in Progress

CCW

CCE

e

V

IH

Ý

Erase Suspend Current

mA CE

CCES

Block Erase Suspended

s

g

I

V

Standby Current

1

15 mA

V

CC

PPS

PP

e

Ý

g

GND 0.2V

Deep Power-down

5.0 mA RP

PPD

PP

Current

31

28F200BL-T/B, 28F002BL-T/B

DC CHARACTERISTICS (Continued)

e

g

5.0V 10%

V

CC

Symbol

Parameter

Read Current

Notes

1

Min

Typ

Max

200

40

Unit

mA

Test Condition

l

I

V

CC

PPR

PP

e

Word Write Current

1, 4

mA

V

PPH

PPW

PP

Word Write in Progress

e

V

PPH

I

V

PP

V

PP

V

PP

Byte Write Current

1, 4

1

30

mA

V

PPW

PPE

PP

Byte Write in Progress

e

V

PPH

Block Erase Current

Erase Suspend Current

mA

V

PP

Block Erase in Progress

e

V

PPH

200

mA

V

PP

PPES

Block Erase Suspended

e

V

HH

Ý

RP Boot Block Unlock Current 1, 4

Ý

I

500

13.0

0.8

mA RP

Ý

RP

ID

e

A

Intelligent Identifier Current

Intelligent Identifier Voltage

1, 4

mA

V

A

9

V

ID

9

V

11.4

12.0

ID

b

Input Low Voltage

Input High Voltage

Output Low Voltage

0.5

V

IL

a

CC

2.0

V

0.5

V

IH

OL

e

0.45

V

Min

CC

5.8 mA

I

OL

e

V

OH1

V

OH2

Output High Voltage (TTL)

2.4

V

I

V

Min

CC

OH

CC

e b

2.5 mA

e

V Min

Output High Voltage

(CMOS)

0.85 V

V

CC

OH

CC

e b

I

2.5 mA

b

e

V

0.4

V

I

Min

100 mA

CC

OH

CC

e b

V

during Normal Operations

during Erase/Write

3

0.0

6.5

V

PPL

PP

11.4

12.0

12.6

PPH

PP

Operations

V

CC

Erase/Write Lock Voltage

2.2

V

LKO

Ý

RP Unlock Voltage

11.4

13.0

Boot Block Write/Erase

HH

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

are valid for all product versions (packages and speeds).

e

12.0V, T 25 C. These currents

5.0V, V

PP

§

CC

2. I

is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum

.

CCR

CCES

of I

and I

CCES

3. Block Erase/Byte Writes are inhibited when V

e

V

PPL

and not guaranteed in the range between V

and V

.

PPL

PP

4. All parameters are sampled, not 100% tested.

PPH

32

28F200BL-T/B, 28F002BL-T/B

AC TESTING LOAD CIRCUIT

AC INPUT/OUTPUT REFERENCE WAVEFORM

290449–15

AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and 0.0V for a logic ‘‘0’’.

Input timing begins, and output timing ends, at 1.5V. Input rise and fall times

k

(10% to 90%)

10 ns.

290449–16

e

C

L

C

L

50 pF

Includes Jig Capacitance

e

R

L

3.3 KX

(1)

AC CHARACTERISTICSÐRead-Only Operations

(3)

e

g

3.3V 0.3V, 5.0V 10%

V

CC

28F200BL-150

28F002BL-150

Versions

Unit

Symbol

Parameter

Read Cycle Time

Address to Output Delay

Notes

Min

Max

t

150

ns

AVAV

AVQV

ELQV

PHQV

GLQV

ELQX

EHQZ

GLQX

GHQZ

RC

150

600

65

ACC

CE

Ý

CE to Output Delay

2

Ý

RP High to Output Delay

PWH

OE

Ý

OE to Output Delay

2

3

Ý

CE to Output Low Z

0

LZ

Ý

CE High to Output High Z

55

45

HZ

Ý

OE to Output Low Z

OLZ

DF

Ý

OE High to Output High Z

Output Hold from Addresses,

OH

Ý

CE or OE Change,

Whichever is First

t

Input Rise Time

Input Fall Time

10

5

ns

IR

IF

Ý

CE to BYTE Switching

t

3

3, 4

3

ELFL

ELFH

Low to High

Ý

BYTE Switching High

to Valid Output Delay

t

150

45

ns

FHQV

Ý

BYTE Switching Low

to Output High Z

t

FLQZ

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

Ý

2. OE may be delayed up to t –t

3. Sampled, not 100% tested.

Ý

after the falling edge of CE without impact on t

.

CE OE

CE

Ý

, BYTE switching low to valid output delay will be equal to t

4. t

, measured from the time DQ /A

15

becomes

33

b

FLQV AVQV

valid.

1

28F200BL-T/B, 28F002BL-T/B

Figure 16. AC Waveforms for Read Operations

34

28F200BL-T/B, 28F002BL-T/B

290449–23

Ý

Figure 17. BYTE Timing Diagram for Both Read and Write Operations for 28F200BL

35

28F200BL-T/B, 28F002BL-T/B

(1)

Ý

AC CHARACTERISTICS FOR WE CONTROLLED WRITE OPERATIONS

e

g

3.0V–3.6V, 5.0V 10%

V

CC

28F200BL-150

28F002BL-150

(4)

Versions

Unit

Symbol

Parameter

Notes

Min

150

1

Max

t

Write Cycle Time

ns

ms

ns

ms

s

AVAV

WC

PS

Ý Ý

RP High Recovery to WE Going Low

t

PHWL

ELWL

Ý

CE Setup to WE Going Low

t

0

CS

Ý

V Setup to WE Going High

RP

6, 8

5, 8

3

200

95

100

0

PHHWH

VPWH

AVWH

DVWH

WLWH

WHDX

WHAX

WHEH

WHWL

WHQV1

WHQV2

PHS

VPS

AS

HH

Ý

Setup to WE Going High

V

PP

Ý

Address Setup to WE Going High

Ý

Data Setup to WE Going High

4

DS

Ý

WE Pulse Width

WP

DH

Ý

Data Hold from WE High

4

3

Ý

Address Hold from WE High

10

50

6

AH

Ý

CE Hold from WE High

CH

Ý

WE Pulse Width High

WPH

Duration of Programming Operation (Boot)

2, 5, 6

Duration of Word/Byte

Programming Operation

0.3

t

Duration of Erase Operation

(Parameter)

2, 5, 6

0.3

s

WHQV3

t

Duration of Erase Operation (Main)

2, 5, 6

5, 8

0.6

0

s

WHQV4

QVVL

t

V

Hold from Valid SRD

PP

ns

VPH

PHH

Ý

RP

V

Hold from Valid SRD

HH

6, 8

0

QVPH

PHBR

Boot-Block Relock Delay

Input Rise Time

7, 8

200

10

t

IR

IF

Input Fall Time

10

NOTES:

1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC

characteristics during Read Mode.

2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled inter-

nally which includes verify and margining operations.

3. Refer to command definition table for valid A

4. Refer to command definition table for valid D

.

IN

.

5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 1).

IN

e

until operation completes successfully.

Ý

6. For Boot Block Program/Erase, RP should be held at V

HH

is required for successful relocking of the Boot Block.

7. Time t

PHBR

8. Sampled but not 100% tested.

36

28F200BL-T/B, 28F002BL-T/B

BLOCK ERASE AND BYTE/WORD WRITE PERFORMANCE

e

g

3.0V–3.6V, 5.0V 10%

V

CC

28F200BL-150

28F002BL-150

Parameter

Notes

Unit

(1)

Min

Typ

Max

8.6

Boot/Parameter Block Erase Time

Main Block Erase Time

2

2.0

3.4

1.4

0.7

s

17.0

5.3

Main Block Byte Program Time

Main Block Word Program Time

2.7

NOTES:

1. 25 C, 12.0V V

.

§

PP

2. Excludes System-Level Overhead.

37

28F200BL-T/B, 28F002BL-T/B

Ý

Figure 18. AC Waveforms for a Write and Erase Operations (WE -Controlled Writes)

38

28F200BL-T/B, 28F002BL-T/B

Ý

AC CHARACTERISTICS FOR CE -CONTROLLED WRITE OPERATIONS

e

g

3.0V–3.6V, 5.0V 10%

V

CC

28F200BL-150

28F002BL-150

Versions

Parameter

Unit

Symbol

Notes

Min

150

1

Max

t

Write Cycle Time

ns

ms

ns

ms

AVAV

PHEL

WLEL

PHHEH

VPEH

AVEH

DVEH

ELEH

EHDX

EHAX

EHWH

EHEL

EHQV1

WC

Ý

RP High Recovery to CE Going Low

PS

Ý

WE Setup to CE Going Low

0

WS

PHS

VPS

AS

Ý

Setup to CE Going High

RP

V

HH

6, 8

5, 8

3

200

95

100

0

Ý

Setup to CE Going High

V

PP

Ý

Address Setup to CE Going High

Ý

Data Setup to CE Going High

4

DS

Ý

CE Pulse Width

CP

Ý

Data Hold from CE High

4

3

DH

Ý

Address Hold from CE High

10

50

6

AH

Ý

WE Hold from CE High

WH

CPH

Ý

CE Pulse Width High

Duration of Word/Byte Programming

Operation (Boot)

2, 5, 6

t

Duration of Erase Operation (Boot)

Duration of Erase Operation (Parameter)

Duration of Erase Operation (Main)

2, 5, 6

5, 8

0.3

0.6

0

s

EHQV2

EHQV3

EHQV4

QVVL

s

t

V

PP

Hold from Valid SRD

ns

VPH

Ý

RP

V

HH

Hold from Valid SRD

6, 8

0

QVPH

PHBR

PPH

Boot-Block Relock Delay

Input Rise Time

7

200

10

t

IR

Input Fall Time

10

IF

NOTES:

1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE and WE in systems where

Ý

CE defines the write pulse-width (within a longer WE timing waveform), all set-up, hold and inactive WE time should

Ý

be measured relative to the CE waveforms.

Ý

2, 3, 4, 5, 6, 7, 8: Refer to AC characteristics for WE -controlled write operations.

9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC

characteristics during read mode.

39

28F200BL-T/B, 28F002BL-T/B

Ý

Figure 19. Alternate AC Waveforms for Write and Erase Operations (CE -Controlled Writes)

40

28F200BL-T/B, 28F002BL-T/B

ORDERING INFORMATION

290449–20

290449–21

VALID COMBINATIONS:

E28F200BL-T150 PA28F200BL-T150

E28F200BL-B150 PA28F200BL-B150

VALID COMBINATIONS:

E28F002BL-T150

E28F002BL-B150

References

Order

Document

Number

290448

290450

290451

290531

290530

290539

292098

292148

292161

292163

292169

292178

292130

292154

28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet

28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet

28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet

2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

AP-363 ‘‘Extended Flash BIOS Concepts for Portable Computers’’

AP-604 ‘‘Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM’’

AP-608 ‘‘Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory’’

AP-610 Flash Memory In-System Code and Data Update Technique

AP-615 Accommodating Industry Trends in Boot Code Flash Memory

AP-623 ‘‘Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory’’

AB-57 ‘‘Boot Block Architecture for Safe Firmware Updates’’

AB-60 ‘‘2/4/8- Mbit SmartVoltage Boot Block Flash Memory Family’’

41

28F200BL-T/B, 28F002BL-T/B

Revision History

Number

Description

-001

-002

Original Version

Ý

Modified BYTE AC Timings

Modified t parameter for AC Characteristics for Write Operations

DVWH

Ý

PWD renamed to RP for JEDEC standardization compatibility.

-003

Combined V Read Current for 28F200BX-L Word-Wide and Byte-Wide Mode and

CC

28F002BX-L Byte-Wide Mode in DC Characteristics tables.

g g

current spec from 10 mA to 15 mA in DC Characteristics table.

Added Boot Block Unlock current spec in DC Characteristics tables.

Changed I

PPS

Improved t

Changed I

spec to 600 ns (was 700 ns)

current spec from 20 mA maximum to 25 mA maximum and added typical spec

PWH

CCR

to DC Characteristics table.

-004

Added I CMOS Specification.

OH

Expanded temperature operating range, from 0 C–70 C to 20 – 70 C.

Product naming changed:

b

a

§

28F200BX-TL/BL changed to 28F200BL-T/B

28F002BX-TL/BL changed to 28F002BL-T/B

Typographical errors corrected.

Added 28F400BX interface to Intel386^TMEX Embedded Processor Block Diagram.

Added upgrade considerations for SmartVoltage Boot Block products.

Previously specified V tolerance of 3.0V to 3.6V for Read, Program and Erase has been

CC

changed to 3.15V to 3.6V for Program and Erase operation, while the Read operation remains

3.0V to 3.6V.

-005

-006

Typographical errors corrected.

Lockout voltage changed from 2.0V to 1.7V.

V

CC

Added input rise/fall time specifications.

42


型号：	PA28F200BL-B150
厂家：	INTEL
描述：	2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY 2兆位（ 128K ×16 ， 256K ×8 ）低功耗BOOT BLOCK闪存系列闪存存储内存集成电路光电二极管
文件：	总42页 (文件大小：497K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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