QB25F160S33B8 [INTEL]
Flash, 16MX1, PDSO16, SOIC-16;
| 型号： | QB25F160S33B8 |
| 厂家： | 
INTEL |
| 描述： | Flash, 16MX1, PDSO16, SOIC-16 光电二极管 |
| 文件： | 总42页 (文件大小：819K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Security
64
64
...
64
64
64
...
64
64
64
...
64
64
64
...
64
64
64
64
8
127
126
...
7F0000 - 7FFFFF
7E0000 - 7EFFFF
...
64
63
62
...
400000 - 40FFFF
3F0000 - 3FFFFF
3E0000 - 3EFFFF
...
3F0000 - 3FFFFF
3E0000 - 3EFFFF
...
32
31
30
...
200000 - 20FFFF
1F0000- 1FFFFF
1E0000 - 1EFFFF
...
200000 - 20FFFF
1F0000- 1FFFFF
1F0000- 1FFFFF
1E0000 - 1EFFFF 1E0000 - 1EFFFF
...
...
16
15
14
...
100000 - 10FFFF
F0000 - FFFFF
E0000 - EFFFF
...
100000 - 10FFFF
F0000 - FFFFF
E0000 - EFFFF
...
100000 - 10FFFF
F0000 - FFFFF
E0000 - EFFFF
...
4
40000 - 4FFFF
30000 - 3FFFF
20000 - 2FFFF
10000 - 1FFFF
E000 - FFFF
C000 - DFFF
A000 - BFFF
8000 - 9FFF
6000 - 7FFF
4000 - 5FFF
2000 - 3FFF
0 - 1FFF
40000 - 4FFFF
30000 - 3FFFF
20000 - 2FFFF
10000 - 1FFFF
E000 - FFFF
C000 - DFFF
A000 - BFFF
8000 - 9FFF
6000 - 7FFF
4000 - 5FFF
2000 - 3FFF
0 - 1FFF
40000 - 4FFFF
30000 - 3FFFF
20000 - 2FFFF
10000 - 1FFFF
E000 - FFFF
C000 - DFFF
A000 - BFFF
8000 - 9FFF
6000 - 7FFF
4000 - 5FFF
2000 - 3FFF
0 - 1FFF
3
2
1
0-H
0-G
0-F
0-E
0-D
0-C
0-B
0-A
8
8
8
8
8
8
8
≤
μ
μ
μ
μ
Device
Under Test
Out
CL
tCHSL
tCHSH
tSHCH
tSHSL
tSLCH
tDVCH
C
S#
tCHDX
D
Q
MSB
LSB
C
S#
tWHSL
tSHWL
W#
tCL
tCH
C
S#
tCLQX
tCLQV
tCLQX
tCLQV
tSHQZ
Q
LSB OUT
tCHHL
tHLCH
tCHHH
tHHCH
C
S#
Q
tHLQZ
tHHQX
HOLD#
tCHHL
tHLCH
tCHHH
tHHCH
C
S#
tHLQZ
THHQX
Q
HOLD#
μ
μ
μ
d
VCC
VCC(max)
Chip Selection Not Allowed
VCC(min)
TVSL
time
When S# is high and the internal algorithms are completed, the device will go into standby
mode.
S#
C - Mode 0
C - Mode 3
Address
Instruction
A23 A22 A21
A2
A1
A0
D
Q
Data
D7
D6
D1
D0
S#
C
Hold State
Standard Usage
HOLD#
S#
Hold State
Non-standard Usage
C
Hold State Inactive
Delay
Hold State Active
Delay
HOLD#
01h
02h
–
3
–
–
1
1 to 256
1 to
infinite
03h
04h
05h
06h
0Bh
3
–
–
–
3
–
–
–
–
1
-
1 to
infinite
-
1 to
infinite
30h
40h
42h
4Bh
–
3
3
3
–
–
–
1
–
–
1
1 to
infinite
9Fh
–
–
–
–
1 to 3
–
ABh
Puts device in DPD mode, whereby all
commands are ignored except the Release
from DPD command (ABh).
B9h
C7h
D8h
—
—
3
—
—
—
—
—
—
Serially erases all main memory Sectors
including the eight parameter blocks.
Erases a 64 KB Memory Sector; when
addressing a parameter block, it will erase
all eight 8 KB parameter blocks.
S#
C
1/Fc
0
1
2
3
4
5
6
7
29 30 31
Address
Instruction
A23 A22 A21 A2 A1 A0
D
Q
S#
C
Dummy Byte
D
Q
Data Byte
D7 D6 D5 D4 D3 D2 D1 D0 D7
D
S#
C
D
Data Byte (Addr+1)
Data Byte (Addr+2)
D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7
Q
S#
C
1/Fc
0
1
2
3
4
5
6
7
29 30 31 32
Address
Instruction
A23 A22 A21 A2 A1 A0 D7
D
D
Q
S#
1/Fc
40
48
C
Data Byte 1
Data Byte 2
D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7
D
D
Q
S#
C
1/Fc
2072
Data Byte 3
Data Byte 256
D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D
Q
S#
C
1/Fc
0
1
2
3
4
5
6
7
Instruction
D
Q
0x2FF
Locked with
PR-LOCK3B,
bit 6
10 Bytes
(80 bits)
{
0x2F6
0x2F5
Locked with
PR-LOCK3B,
bit 5
16 Bytes
(128 bits)
{
0x2E6
0x225
Locked with
PR-LOCK3A,
bit 0
16 Bytes
(128 bits)
{
0x216
PR-LOCK3B Register: 0x215
PR-LOCK3A Register: 0x214
0x213
Locked with
PR-LOCK2B,
bit 7
16 Bytes
(128 bits)
{
0x204
0x123
Locked with
PR-LOCK2A,
bit 0
16 Bytes
(128 bits)
{
0x114
PR-LOCK2B Register: 0x113
PR-LOCK2A Register: 0x112
0x111
8 Bytes (64 bits)
8 Bytes (64 bits)
Locked with bit 1
{
0x10A
0x109
Locked with bit 0
{
0x102
Reserved: 0x101
PR-LOCK1 Register 0x100
Q B 2 5 F 3 2 0 S 3 3 B 8
Access Speed
Package Designator
QB = SOIC-8/SOIC-16, leaded
QH = SOIC-8/SOIC-15, lead free
8 nS (tCLQV
)
Parameter Location
B = Bottom Parameter
Product Line Designator
T = Top Parameter
25F = Intel® S33
Product Family
Intel® S33
VCC = 2.7 – 3.6 V
Device Density
016 = 16 Mbit, SOIC-8
160 = 16 Mbit, SOIC-16
320 = 32 Mbit
640 = 64 Mbit
FPG_A0019-01
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