QE82527 [INTEL]
Micro Peripheral IC, CMOS, PQFP44;
| 型号： | QE82527 |
| 厂家： | 
INTEL |
| 描述： | Micro Peripheral IC, CMOS, PQFP44 |
| 文件： | 总22页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
82527 SERIAL COMMUNICATIONS
CONTROLLER AREA NETWORK
PROTOCOL
Express
Advance Information Datasheet
Product Features
■ Supports CAN Specification 2.0
—Standard Data and Remote Frames
—Extended Data and Remote Frames
■ Programmable Global Mask
—Standard Message ldentifier
—Extended Message ldentifier
■ 15 Message Objects of 8-Byte Data Length
—14 Tx/Rx Buffers
■ Programmable Bit Rate
■ Programmable Clock Output
■ Flexible Interrupt Structure
■ Flexible Status Interface
■ Configurable Output Driver
■ Configurable Input Comparator
■ Two 8-Bit Bidirectional I/O Ports
■ 44-Lead PLCC Package
■ Pinout Compatibility with the 82526
—1 Rx Buffer with Programmable Mask
■ Flexible CPU Interface
—8-Bit Multiplexed
—16-Bit Multiplexed
—8-Bit Non-Multiplexed (Synchronous/
Asynchronous)
—Serial Interface
Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order No: 273150-002
August 2004
82527 - Express
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82527 - Express may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
PO Box 5937
Denver CO 80217-9808
call 1-800-548-4725
Copyright © Intel Corporation 1997, 2004
*Third-party brands and names are the property of their respective owners.
ii
Advance Information
Datasheet
82527 - Express
Contents
1.0
2.0
3.0
INTRODUCTION.....................................................................................................1
PIN DESCRIPTIONS.............................................................................................3
ELECTRICAL CHARACTERISTICS .................................................................5
3.1
3.2
3.3
3.4
DC CHARACTERISTICS ................................................................................ 5
PHYSICAL LAYER SPECIFICATIONS........................................................... 6
CLOCKOUT SPECIFICATIONS ..................................................................... 6
AC CHARACTERISTICS ................................................................................ 7
3.4.1 8/16-Bit Multiplexed Intel Modes (Modes 0, 1)................................... 7
3.4.2 8-Bit Multiplexed Non-Intel Mode (Mode 2)...................................... 10
3.4.3 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3)...................... 12
3.4.4 8-Bit Non-Multiplexed Synchronous Mode (Mode 3)........................ 14
3.4.5 Serial Interface Mode ....................................................................... 16
3.4.6 AC Testing Input............................................................................... 18
4.0
DATASHEET REVISION HISTORY................................................................18
Advance Information Datasheet
iii
82527 - Express
Figures
1
2
3
4
xx82527 Block Diagram ..................................................................................2
xx82527 44-Pin PLCC Package .....................................................................2
82527 System Timings (Modes 0, 1) ...............................................................8
Ready Output Timing for a Write Cycle if No Previous Write
is Pending (Modes 0, 1) ...................................................................................9
5
Ready Output Timing for Write Cycle if Previous Write Cycle
is Active (Modes 0, 1........................................................................................9
Ready Output Timing for Read Cycle (Modes 0, 1) .........................................9
82527 System Bus Timing (Mode 2)..............................................................11
Timing of the Asynchronous Mode Read Cycle (Mode 3)..............................13
Timing of the Asynchronous Mode Write Cycle (Mode 3)..............................13
Timing of the Synchronous Read Cycle (Mode 3) .........................................15
Timing of the Synchronous Write Cycle (Mode 3)..........................................15
Serial Interface Mode (Priority = 0, Phase = 0)..............................................17
Serial Interface Mode (Priority = 1, Phase = 1)..............................................17
6
7
8
9
10
11
12
13
Tables
1
2
3
4
5
6
7
8
Pin Type Legend ..............................................................................................3
Pin Descriptions ...............................................................................................3
DC Characteristics ...........................................................................................5
DC Characteristics ...........................................................................................6
Clockout Specifications....................................................................................6
AC Characteristics 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) ..................7
AC Characteristics 8-Bit Multiplexed Non-Intel Mode (Mode 2).....................10
AC Characteristics 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3).....12
AC Characteristics 8-Bit Non-Multiplexed Synchronous Mode (Mode 3).......14
AC Characteristics for Serial Interface Mode.................................................16
9
10
iv
Advance Information Datasheet
82527 - Express
1.0
INTRODUCTION
The 82527 serial communications controller is a highly integrated device that performs serial
communication according to the CAN protocol. It performs all serial communication functions
such as transmission and reception of messages, message filtering, transmit search, and interrupt
search with minimal interaction from the host microcontroller, or CPU.
The 82527 is Intel’s first device to support the standard and extended message frames in CAN
Specification 2.0 Part B. It has the capability to transmit, receive, and perform message filtering on
extended message frames. Due to the backwardly compatible nature of CAN Specification 2.0, the
82527 also fully supports the standard message frames in CAN Specification 2.0 Part A.
The 82527 features a powerful CPU interface that offers flexibility to directly interface to many
different CPUs. It can be configured to interface with CPUs using an 8-bit multiplexed, 16-bit
multiplexed, or 8-bit non-multiplexed address/data bus for Intel and non-Intel architectures. A
flexible serial interface (SPI) is also available when a parallel CPU interface is not required.
The 82527 provides storage for 15 message objects of 8-byte data length. Each message object can
be configured as either transmit or receive except for the last message object. The last message
object is a receive-only buffer with a special mask design to allow select groups of different
message identifiers to be received.
The 82527 also implements a global masking feature for message filtering. This feature allows the
user to globally mask any identifier bits of the incoming message. The programmable global mask
can be used for both standard and extended messages.
The 82527 PLCC offers hardware, or pinout, compatibility with the 82526. It is pin-to-pin
compatible with the 82526 except for pins 9, 30, and 44. These pins are used as chip selects on the
82526 and are used as CPU interface mode selection pins on the 82527.
The 82527 is fabricated using Intel’s reliable CHMOS III 5V technology and is available in 44-lead
PLCC for the express temperature range (–40°C to +85°C).
ADVANCE INFORMATION Datasheet
1
82527 - Express
Figure 1. xx82527 -Express Block Diagram
Port 1
Port 2
Port 2
Port 1
TX0
TX1
Address/
Data Bus
CAN
Controller
CPU
Interface
Logic
RAM
RX0
RX1
Control Bus
CLKOUT
CLKOUT
Mode 0
Mode 1
A4577-01
Figure 2. xx82527 44-Pin PLCC Package
(WR# / WRL#)/(R/W#)
7
8
9
39
38
37
36
35
34
33
32
31
30
29
AD7
CS#
DSACK0
P2.7 / WRH#
P2.6 / INT#
P2.5
P1.0 / AD8
P1.1 / AD9
P1.2 / AD10
P1.3 / AD11
P1.4 / AD12
P1.5 / AD13
P1.6 / AD14
P1.7 / AD15
MODE1
10
11
12
13
14
15
16
17
xx82527
P2.4
P2.3
P2.2
P2.1
View of component as
mounted on PC board
P2.0
RESET#
A4578-01
2
ADVANCE INFORMATION Datasheet
82527 - Express
2.0
PIN DESCRIPTIONS
The 82527 - Express pins are described in this section. Table 1 presents the legend for interpreting the
pin types.
Table 1. Pin Type Legend
Symbol
Description
I
Input Only Pin
O
Output Only Pin
I/O
Pin can be either Input or Output
Table 2. Pin Descriptions (Sheet 1 of 2)
Name
Type
Description
GROUND connection must be connected externally to a VSS board
plane. Provides digital ground.
VSS1
VSS2
VCC
Ground
GROUND connection must be connected externally to a VSS board
plane. Provides ground for analog comparator.
Ground
Power
I
POWER connection must be connected externally to +5 V DC. Provides
power for entire device.
Input for an external clock. XTAL1 (along with XTAL2) are the crystal
connections to an internal oscillator.
XTAL1
Push-pull output from the internal oscillator. XTAL2 (along with XTAL1)
are the crystal connections to an internal oscillator. If an external
oscillator is used, XTAL2 must be floated, or not be connected. XTAL2
must not be used as a clock output to drive other CPUs.
XTAL2
O
O
Programmable clock output. This output may be used to drive the
oscillator of the host microcontroller.
CLKOUT
Warm Reset: (VCC remains valid while RESET# is asserted), RESET#
must be driven to a valid low level for 1 ms minimum.
RESET#
CS##
I
I
Cold Reset: (VCC is driven to a valid level while RESET# is asserted),
RESET# must be driven low for 1 ms minimum measured from a valid VCC
level. No falling edge on the reset pin is required during a cold reset event.
A low level on this pin enables CPU access to the 82527 device.
The interrupt pin is an open-drain output to the host microcontroller.
VCC/2 is the power supply for the ISO low speed physical layer. The
function of this pin is determined by the MUX bit in the CPU Interface
Register (Address 02H) as follows:
INT#
O
O
(VCC/2)
MUX e 1: pin 24 (PLCC) = VCC/2, pin 11 = INT#
MUX e 0: pin 24 (PLCC) = INT#
Inputs from the CAN bus line(s) to the input comparator. A recessive level
is read when RX0 > RX1. A dominant level is read when RX1 > RX0.
When the CoBy bit (Bus Configuration register) is programmed as a “1”,
the input comparator is bypassed and RX0 is the CAN bus line input.
RX0
RX1
I
I
TX0
TX1
O
O
Serial data push-pull output to the CAN bus line. During a recessive bit TX0
is high and TX1 is low. During a dominant bit TX0 is low and TX1 is high.
ADVANCE INFORMATION Datasheet
3
82527 - Express
Table 2. Pin Descriptions (Sheet 2 of 2)
Name
Type
Description
Address/Data bus in 8-bit multiplexed mode.
Address bus in 8-bit non-multiplexed mode.
AD0/A0/ICP
AD1/A1/CP
AD2/A2/CSAS
AD3/A3/STE
AD4/A4/MOSI
AD5/A5
I/O-I-I
I/O-I-I
I/O-I-I
I/O-I
I/O-I-I
I/O-I
Low byte of A/D bus in 16-bit multiplexed mode.
In Serial Interface mode, the following pins have the following meaning:
AD0:
AD1:
AD2:
AD3:
AD6:
AD4:
ICP
CP
CSAS
STE
SCLK
MOSI
Idle Clock Polarity
Clock Phase
Chip Select Active State
Sync Transmit Enable
Serial Clock Input
Serial Data Input
AD6/A6/SCLK
AD7/A7
I/O-I-I
I/O-I
AD8/D0/P1.0
AD9/D1/P1.1
AD10/D2/P1.2
AD11/D3/P1.3
AD12/D4/P1.4
AD13/D5/P1.5
AD14/D6/P1.6
AD15/D7/P1.7
I/O-O-I/O
I/O-O-I/O
I/O-O-I/O
I/O-O-I/O
I/O-O-I/O
I/O-O-I/O
I/O-O-I/O
I/O-O-I/O
High byte of A/D bus in 16-bit multiplexed mode.
Data bus in 8-bit non-multiplexed mode.
Low speed I/O port. P1 pins in 8-bit multiplexed mode and serial mode.
Port pins have weak pullups until the port is configured by writing to 9FH
and AFH.
P2.0
P2.1
I/O
I/O
P2.2
P2.3
P2.4
P2.5
I/O
I/O
I/O
I/O
P2 in all modes.
P2.6 is INT# when MUX = 1 and is open-drain.
P2.7 is WRH# in 16-bit multiplexed mode.
P2.6/INT#
I/O-O
P2.7/WRH#
I/O-I
These pins select one of the four parallel interfaces. These pins are
weakly held low during reset.
Mode1
Mode0
0
0
0
0
8-bit multiplexed — Intel
Serial Interface mode entered when RD# = 0,
WR# = 0 upon reset.
Mode0
Mode1
I
I
0
1
1
1
0
1
16-bit multiplexed — Intel
8-bit multiplexed — non-Intel
8-bit non-multiplexed
ALE used for Intel modes.
ALE/AS
I-I
AS used for non-Intel modes, except Mode 3 this pin must be tied high.
RD#used for Intel modes.
RD#
E
I
I
E used for non-Intel modes, except Mode 3 Asynchronous this pin must
be tied high.
WR#in 8-bit Intel mode and WRL# in 16-bit Intel mode.
R/W# used for non-Intel modes.
WR#/WRL#
R/W#
I
I
READY is an output to synchronize accesses from the host
microcontroller to the 82527. READY is an open-drain output to the host
microcontroller. MISO is the serial data output for the serial interface
mode.
READY
MISO
O
O
DSACK0# is an open-drain output to synchronize accesses from the host
microcontroller to the 82527.
DSACK0#
O
4
ADVANCE INFORMATION Datasheet
82527 - Express
3.0
ELECTRICAL CHARACTERISTICS
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice. Verify with
your local Intel sales office that you have the latest
datasheet before finalizing a design.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
–60°C to +150°C
Voltage from Any Pin to
VSS ................................................. –0.5 V to +7.0 V
*WARNING: Stressing the device beyond the
Laboratory testing shows the 82527 will withstand up to 10 “Absolute Maximum Ratings” may cause
mA of injected current into both RX0 and RX1 pins for a permanent damage. These are stress ratings
total of 20 days without sustaining permanent damage. This only. Operation beyond the “Operating
high current condition may be the result of shorted signal
lines. The 82527 will not function properly if the RX0/RX1
input voltage exceeds VCC+0.5 V.
Conditions” is not recommended and extended
exposure beyond the “Operating Conditions”
may affect device reliability.
3.1
DC CHARACTERISTICS
Operating Conditions:
• V = 5 V ±10%
CC
• T = –40°C to +85°C
A
Table 3. DC Characteristics
Sym
VIL
Parameter
Min
–0.5
–0.5
Max
0.8 V
0.5 V
0.5 V
Conditions
Input Low Voltage (All except RX0, RX1, AD0±AD7
in Mode 3)
VIL1
VIL2
Input Low Voltage for AD00–D7 in Mode 3
Input Low Voltage (RX0) for Comparator Bypass
Mode
Input Low Voltage for Port 1 and Port 2 Pins Not
Used for Interface to Host CPU
VIL3
VIH
0.3 VCC
Input High Voltage (All except RX0, RX1, RESET#)
3.0 V
VCC + 0.5 V
VCC + 0.5 V
Input High Voltage (RESET#) Hysteresis on
RESET#
3.0 V
200 mV
VIH1
Input High Voltage (RX0) for Comparator Bypass
Mode
VIH2
4.0 V
Input High Voltage for Port 1 and Port 2 Pins Not
Used for Interface to Host CPU
VIH3
VOL
VOH
0.7 VCC
Output Low Voltage (All Outputs except TX0, TX1)
0.45 V
IOL = 1.6 mA
IOH = –200 µA
IOH = –80 µA
Output High Voltage (All Outputs except TX0, TX1,
CLOCKOUT)
V
CC – 0.8 V
VOHR1 Output High Voltage (CLOCKOUT)
0.8 V
ILK
Input Leakage Current
PIN Capacitance**
Supply Current
±10 µA
10 pF
VSS < VIN < VCC
CIN
ICC
FXTAL = 1 KHz
FXTAL = 16 KHz(1)
50 mA
Sleep Current
ISLEEP with VCC/2 Output Enabled, No Load
with VCC/2 Output Disabled
(1)
700 µA
100 µA
IPD
Powerdown Current
25 µA
XTAL1 Clocked(1)
NOTES:
**Typical value based on characterization data. Port pins are weakly held after reset until the port
configuration registers are written (9FH, AFH).
1. All pins are driven to VSS or VCC including RX0 and RX1.
ADVANCE INFORMATION Datasheet
5
82527 - Express
3.2
PHYSICAL LAYER SPECIFICATIONS
Operating Conditions:
• Load = 100 pF
• V = 5 V ±10%
CC
• T = –40°C to +85°C
A
Table 4. DC Characteristics
RX0/RX1 and TX0/TX1
Min
Max
Conditions
Input Voltage
–0.5 V
VCC + 0.5 V
VCC – 1 V
Common Mode Range
Differential Input Threshold
V
SS + 1 V
±100 mV
Internal Delay 1: Sum of the Comparator
Input Delay and the TX0/TX1 Output Driver
Delay
Load on TX0, TX1 = 100 pF,
+100 mV to –100 mV RX0/RX1
differential
60 ns
50 ns
Internal Delay 2: Sum of the RX0 Pin Delay
(if the Comparator is Bypassed) and the
TX0/TX1 Output Driver Delay
Load on TX0, TX1 = 100 pF
Source Current on Each TX0, TX1
Sink Current on Each TX0, TX1
Input Hysteresis for RX0/RX12
–10 mA
10 mA
0 V
V
V
OUT = VCC – 1 V
OUT = 1 V
VCC/2
VCC/2
2.38 V
2.62 V
I
OUT ≤ 75 µA, VCC = 5 V
3.3
CLOCKOUT SPECIFICATIONS
Operating Conditions:
• Load = 50 pF
Table 5. Clockout Specifications
Parameter
Min
XTAL/15
Max
CLOCKOUT Frequency
XTAL
6
ADVANCE INFORMATION Datasheet
82527 - Express
3.4
AC CHARACTERISTICS
3.4.1
8/16-Bit Multiplexed Intel Modes (Modes 0, 1)
Operating Conditions:
•
VCC = 5 V ±10%
•
VSS = 0 V
•
TA = –40°C to +85ºC
•
CL = 100 pF
Table 6. AC Characteristics 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) (Sheet 1 of 2)
Symbol
Parameter
Oscillator Frequency
System Clock Frequency
Min
Max
Conditions
1/TXTAL
1/TSCLK
8 MHZ
4 MHZ
2 MHZ
7.5 ns
10 ns
30 ns
20 ns
10 ns
27 ns
10 ns
30 ns
8 ns
16 MHz
10 MHZ
8 MHZ
1/TMCLK Memory Clock Frequency
Address Valid to ALE Low
Address Hold after ALE Low
ALE High Time
TAVLL
TLLAX
TLHLL
TLLRL
ALE Low to RD# Low
CS# Low to ALE Low
Data Setup to WR# High
Input Data Hold after WR# High
WR# Pulse Width
TCLLL
TQVWH
TWHQX
TWLWH
TWHLH
TWHCH
WR# High to Next ALE High
WR# High to CS# High
RD# Pulse Width
0 ns
40 ns
This time is long enough to initiate a double
read cycle by loading the High Speed
Registers (04H, 05H), but is too short to
READ from 04H and 05H (See t RLDV )
TRLRH
RD# Low to Data Valid (Only for Registers
02H, 04H, 05H)
0 ns
0 ns
55 ns
TRLDV
RD# Low Data to Data Valid (for Registers
except 02H, 04H, 05H)
for Read Cycle without a Previous Write (1)
for Read Cycle with a Previous Write (1)
1.5 TMCLK + 100 ns
3.5 TMCLK + 100 ns
TRLDV1
Data Float after RD# High
TRHDZ
TCLYV
45 ns
CS# Low to READY Setup Condition:
Load Capacitance on the READY Output: 50
pF
32 ns
40 ns
V
OL=1 V
VOL=0.45 V
WR# Low to READY Float for a Write Cycle if
No Previous Write is Pending (2)
145 ns
TWLYZ
2 TMCLK + 100 ns
End of Last Write to READY Float for a Write
Cycle if a Previous Write Cycle is Active (2)
TWHYZ
NOTES:
References to WR# also pertain to WRH#.
1. Definition of “read cycle without a previous write”: The time between the rising edge of WR#/WRH# (for the
previous write cycle) and the falling edge of RD# (for the current read cycle) is greater than 2 TMCLK
2. Definition of “write cycle with a previous write'”. The time between the rising edge of WR#/WRH# (for the
.
previous write cycle) and the rising edge of WR#/WRH# (for the current write cycle) is less than 2 TMCLK
3. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor.
.
ADVANCE INFORMATION Datasheet
7
82527 - Express
Table 6. AC Characteristics 8/16-Bit Multiplexed Intel Modes (Modes 0, 1) (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Conditions
RD# Low to READY Float
2 TMCLK + 100 ns
4 TMCLK + 100 ns
(for registers except 02H, 04H, 05H)
for Read Cycle without a Previous Write (1)
for Read Cycle with a Previous Write (1)
TRLYZ
TMCLK
2 TMCLK + 100 ns
WR# High ti Output Data Valid on Port 1/2
CLKOUT Period
TWHDV
(CDV+1) * TOSC (3)
(CDV+1) * ½TOSC –10 (CDV+1) * ½TOSC –15
TCOPO
TCHCL
CLKOUT High Period
NOTES:
References to WR# also pertain to WRH#.
1. Definition of “read cycle without a previous write”: The time between the rising edge of WR#/WRH# (for the
previous write cycle) and the falling edge of RD# (for the current read cycle) is greater than 2 TMCLK
2. Definition of “write cycle with a previous write'”. The time between the rising edge of WR#/WRH# (for the
.
previous write cycle) and the rising edge of WR#/WRH# (for the current write cycle) is less than 2 TMCLK
3. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor.
.
Figure 3. 82527 - Express System Timings (Modes 0, 1)
tLHLL
ALE
tLLAX
Address
tAVLL
BUS
RD#
Data Out
tRHDZ
tRLDV
tLLRL
tRLRH
tCLLL
tWHCH
CS#
tWLWH
tWHLH
WR#
tQVWH
tWHQX
Address
Data In
BUS
tWHDV
PORT 1 / 2
A4580-01
8
ADVANCE INFORMATION Datasheet
82527 - Express
Figure 4. Ready Output Timing for a Write Cycle if No Previous Write is Pending (Modes 0, 1)
CS#
WR#
Ready
t
CLYV
t
WLYZ
Figure 5. Ready Output Timing for Write Cycle if Previous Write Cycle is Active (Modes 0, 1)
CS#
WR#
Ready
t
WHYZ
Figure 6. Ready Output Timing for Read Cycle (Modes 0, 1)
t
CLYV
CS#
ALE
RD#
Ready
t
RLYZ
ADVANCE INFORMATION Datasheet
9
82527 - Express
3.4.2
8-Bit Multiplexed Non-Intel Mode (Mode 2)
Operating Conditions::
•
VCC = 5 V ±10%
•
VSS = 0 V
•
TA = –40°C to +85ºC
• CL = 100 pF
Table 7. AC Characteristics 8-Bit Multiplexed Non-Intel Mode (Mode 2)
Symbol
Parameter
Min
Max
Oscillator Frequency
1/TXTAL
1/TSCLK
1/TMCLK
TAVLL
8 MHZ
4 MHZ
2 MHZ
7.5 ns
10 ns
0 ns
16 MHz
10 MHZ
8 MHZ
System Clock Frequency
Memory Clock Frequency
Address Valid to AS Low
Address Hold after AS Low
Data Float after E Low
TSLAX
TELDZ
45 ns
45 ns
E High to Data Valid for Registers 02H, 04H, 05H
0 ns
for Read Cycle without a Previous Write (1)
for Read Cycle with a Previous Write (for Registers except for
02H, 04H, 05H)
TEHDV
1.5 TMCLK + 100 ns
3.5 TMCLK + 100 ns
TQVEL
TELQX
TELDV
TEHEL
TELEL
TSHSL
TRSEH
TSLEH
TCLSL
TELCH
TCOPD
TCHCL
NOTES:
Data Setup to E Low
30 ns
20 ns
TMCLK
Input Data Hold after E Low
E Low to Output Data Valid on Port 1/2
E High Time
2 TMCLK + 500 ns
45 ns
2 TMCLK
End of Previous Write (Last E Low) to E Low for a Write Cycle
AS High Time
30 ns
30 ns
20 ns
20 ns
0 ns
Setup Time of R/W# to E High
AS Low to E High
CS# Low to AS Low
E Low to CS# High
(CDV+1) * TOSC (3)
CLKOUT Period
(CDV+1) * ½TOSC – 10 (CDV+1) * ½TOSC + 15
CLKOUT High Period
1. Definition of “Read Cycle without a Previous Write”: The time between the falling edge of E (for the
previous write cycle) and the rising edge of E (for the current read cycle) is greater than 2 TMCLK
2. Definition of “Write Cycle with a Previous Write'”. The time between the falling edge of E (for the previous
write cycle) and the falling edge of E (for the current write cycle) is less than 2 TMCLK
.
.
3. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor.
10
ADVANCE INFORMATION Datasheet
82527 - Express
Figure 7. 82527 - Express System Bus Timing (Mode 2)
t
SHSL
AS
t
AVSL
t
SLAX
Data Out
t
ELDZ
Address
Bus
t
t
EHDV
SLEH
E
t
EHEL
R/W#
t
RSEH
t
t
ELCH
CLSL
CS#
R/W#
Bus
t
t
ELQX
QVEL
t
Data In
Address
ELDV
Port 1/2
A4588-01
ADVANCE INFORMATION Datasheet
11
82527 - Express
3.4.3
8-Bit Non-Multiplexed Asynchronous Mode (Mode 3)
Operating Conditions:
•
VCC = 5 V ±10%
•
VSS = 0 V
•
TA = –40°C to +85ºC
• CL = 100 pF
Table 8. AC Characteristics 8-Bit Non-Multiplexed Asynchronous Mode (Mode 3)
Sym
Parameter
Min
Max
1/TXTAL Oscillator Frequency
1/TSCLK System Clock Frequency
1/TMCLK Memory Clock Frequency
8 MHZ
4 MHZ
2 MHZ
3 ns
16 MHz
10 MHZ
8 MHZ
TAVLL
Address or R/W# Valid to CS# Low Setup
CS# Low to Data Valid for High Speed Registers (02H, 04H, 05H)
For Low Speed Registers (Read Cycle without Previous Write) (1)
For Low Speed Registers (Read Cycle with Previous Write) (1)
0 ns
55 ns
0 ns
1.5 TMCLK + 100 ns
TCLDV
0 ns
3.5 TMCLK + 100 ns
23 ns
DSACK0# Low to Output Data Valid for High Speed Read
Register
TKLDV
For Low Speed Read Register
82527 Input Data Hold after CS# High
82527 Output Data Hold after CS# High
CS# High to Output Data Float
CS# High to DSACK0# = 2.4V (3)
CS# High to DSACK0# = 2.8V
CS# High to DSACK0# Float
CS# Width between Successive Cycles
CS# High to Address Invalid
< 0 ns
15 ns
0 ns
TCHDV
TCHDH
TCHDZ
TCHKH1
TCHKH2
TCHKZ
TCHCL
TCHAI
35 ns
55 ns
0 ns
150 ns
100 ns
0 ns
25 ns
7 ns
TCHRI
CS# High to R/W# Invalid
5 ns
TCLCH
TDVCH
CS# Width Low
65 ns
20 ns
0 ns
CPU Write Data Valid to CS# High
CS# Low to DSACK0# Low for High Speed Registers and Low
Speed Registers Write Access without Previous Write (2)
67 ns
TCLKL
End of Previous Write (CS# High) to DSACK0# Low for a Write
Cycle with a Previous Write (2)
0 ns
2 TMCLK + 145 ns
TCHKL
(CDV+1) * TOSC (4)
(CDV+1) * ½TOSC–10 (CDV+1) * ½TOSC+15
TCOPD
CLKOUT Period
TCHCL
CLKOUT High Period
NOTES:
E and AS must be tied high in this mode.
1. Definition of “Read Cycle without a Previous Write”: The time between the rising edge of CS# (for the
previous write cycle) and the falling edge of CS# (for the current read cycle) is greater than 2 TMCLK
2. Definition of “Write Cycle with a Previous Write'”. The time between the rising edge of CS# (for the previous
write cycle) and the rising edge of CS# (for the current write cycle) is less than 2 TMCLK
.
.
3. An on-chip pullup will drive DSACK0# to approximately 2.4 V. An external pullup is required to drive this
signal to a higher voltage.
4. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor.
12
ADVANCE INFORMATION Datasheet
82527 - Express
Figure 8. Timing of the Asynchronous Mode Read Cycle (Mode 3)
Address
R/W#
t
CHAI
t
t
AVCL
CHCL
t
CLCH
CS#
t
CHDZ
t
t
CLDV
CHDH
Data
t
t
CHKZ
KLDV
t
t
CHKH
CLKL
DSACK0#
A4589-01
Figure 9. Timing of the Asynchronous Mode Write Cycle (Mode 3)
Address
R/W#
t
CHAI
t
t
AVCL
CHCL
t
CLCH
CS#
t
CHDV
t
DVCH
Data
t
CHKZ
t
CLKL
t
CHKH
DSACK0#
A4590-01
ADVANCE INFORMATION Datasheet
13
82527 - Express
3.4.4
8-Bit Non-Multiplexed Synchronous Mode (Mode 3)
Operating Conditions:
•
VCC = 5 V ±10%
•
VSS = 0 V
•
TA = –40°C to +85ºC
• CL = 100 pF
Table 9. AC Characteristics 8-Bit Non-Multiplexed Synchronous Mode (Mode 3)
Sym
Parameter
Min
Max
1/TXTAL Oscillator Frequency
1/TSCLK System Clock Frequency
1/TMCLK Memory Clock Frequency
8 MHZ
4 MHZ
2 MHZ
16 MHz
10 MHZ
8 MHZ
E High to Data Valid out of High Speed Register (02H, 04H, 05H)
Read Cycle without Previous Write for Low Speed Registers(1)
55 ns
1.5 TMCLK + 100 ns
TEHDV
Read Cycle with Previous Write for Low Speed Registers(1)
Data Hold after E Low for a Read Cycle
Data Float after E Low
3.5 TMCLK + 100 ns
TELDH
TELDZ
TELDV
TAVEH
TELAV
TCVEH
TELCV
TDVEL
TEHEL
TAVAV
TAVCL
TCHAI
TCOPD
5 ns
35 ns
Data Hold after E Low for a Write Cycle
Address and R/W# to E Setup
Address and R/W# Valid after E Falls
CS# Valid to E High
15 ns
25 ns
15 ns
0 ns
CS# Valid after E Low
0 ns
Data Setup to E Low
55 ns
100 ns
2 TMCLK
E Active Width
Start of a Write Cycle after a Previous Write Access
Address or R/W# to CS# Low Setup
CS# High to Address Invalid
3 ns
7 ns
(CDV+1) * TOSC (2)
(CDV+1) * ½TOSC–10 (CDV+1) * ½TOSC+15
CLKOUT Period
TCHCL
CLKOUT High Period
NOTES:
1. Definition of “Read Cycle without a Previous Write”: The time between the falling edge of E (for the previous
write cycle) and the rising edge of E (for the current read cycle) is greater than 2 TMCLK
.
2. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor.
14
ADVANCE INFORMATION Datasheet
82527 - Express
Figure 10. Timing of the Synchronous Read Cycle (Mode 3)
t
AVAV
Address
R/W#
t
t
ELAV
t
AVEH
ELCV
t
t
AVCL
CHAI
t
CVEH
CS#
t
EHEL
E
t
t
ELDV
DVEL
Data
A4592-01
Figure 11. Timing of the Synchronous Write Cycle (Mode 3)
t
AVAV
Address
R/W#
t
ELAV
t
t
AVEH
ELCV
t
t
AVCL
CHAI
t
CVEH
CS#
t
EHEL
E
t
t
ELDV
DVEL
Data
A4591-01
ADVANCE INFORMATION Datasheet
15
82527 - Express
3.4.5
Serial Interface Mode
Operating Conditions:
• V = 5.0 V ±10%
CC
• V = 0 V
SS
• T = –40°C +85°C
A
• C = 100 pF
L
Table 10. AC Characteristics for Serial Interface Mode
Sym
Parameter
Min
Max
1/TMCLK SPI Clock
0.5 MHZ
125 ns
84 ns
8 MHZ
TELDH
TELDZ
TELDV
TAVEH
TELAV
TCVEH
TELCV
TDVEL
TEHEL
TAVAV
TAVCL
TCHAI
TCHAI
TCHAI
1/SCLK
2000 ns
Minimum Clock High Time
Minimum Clock Low Time
ENABLE Lead Time
Enable Lag Time
Access Time
84 ns
70 ns
109 ns
60 ns
59 ns
Maximum Data Out Delay Time
Minimum Data Out Hold Time
0 ns
Maximum Data Out Disable Time
665 ns
Minimum Data Setup Time
35 ns
84 ns
Minimum Data Hold Time
Maximum Time for Input to go from VOL to VOH
Maximum Time for Input to go from VOH to VOL
Minimum Time between Consecutive CS# Assertions
100 ns
100 ns
670 ns
(1)
TCOPD
TCHCL
CLKOUT Period
(CDV+1) * TOSC
(CDV+1) * ½TOSC–10 (CDV+1) * ½TOSC+15
CLKOUT High Period
NOTE:
1. Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor.
16
ADVANCE INFORMATION Datasheet
82527 - Express
Figure 12. Serial Interface Mode (Priority = 0, Phase = 0)
t
CS
t
t
LAG
LEAD
CS#
t
t
SKHI
t
FALL
SKL0
t
CYC
t
RISE
SCLK
MIS0
t
t
t
PD0
ACC
t
DIS
H0
t
t
HOLD
SETUP
MOSI
NOTE: Polarity = 0, Phase = 0
A4593-01
Figure 13. Serial Interface Mode (Priority = 1, Phase = 1)
t
CS
t
t
LAG
LEAD
CS#
t
t
RISE
SKLO
t
SKHI
t
CYC
t
FALL
SCLK
MIS0
t
DIS
t
t
t
PD0
ACC
H0
t
t
SETUP
HOLD
MOSI
NOTE: Polarity = 1, Phase = 1
A4594-01
ADVANCE INFORMATION Datasheet
17
82527 - Express
3.4.6
AC Testing Input
Figure 1. Input, Output Waveforms
VCC – 0.5
0.1 V
VCC – 0.8V
0.45V
NOTE:
AC inputs during testing are driven at
V
– 0.5V for a Logic "1" and 0.1V for a Logic "0".
CC
Min for a Logic "1" and
V
V
Timing measurements are made at
Max for a Logic "0".
OH
OL
A4598-01
4.0
DATASHEET REVISION HISTORY
Package prefix variables in this document are now indicated with an "x".
18
ADVANCE INFORMATION Datasheet
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