QG5000XSL9TH [INTEL]
Intel 5000X Chipset Memory Controller Hub (MCH); 英特尔5000X芯片组内存控制器中枢（ MCH ）
| 型号： | QG5000XSL9TH |
| 厂家： | 
INTEL |
| 描述： | Intel 5000X Chipset Memory Controller Hub (MCH) |
| 文件： | 总458页 (文件大小：3558K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Intel 5000X Chipset Memory
Controller Hub (MCH)
Datasheet
September 2006
Document Number: 313070-003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or
life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
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®
The Intel 5000 Series Chipsets, Dual Core Intel Xeon Processor 5000 sequence and Intel 631xESB/632xESB I/O Controller
Hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
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64-bit Intel Xeon processors with Intel EM64T requires a computer system with a processor, chipset, BIOS, OS, device drivers
and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled
BIOS. Performance will vary depending on your hardware and software configurations. Intel EM64T-enabled OS, BIOS, device
drivers and applications may not be available. Check with your vendor for more information.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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2
I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed
2
by Intel. Implementations of the I C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
Intel, Pentium, and Xeon are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
*Other brands and names are the property of their respective owners.
Copyright © 2005-2006, Intel Corporation.
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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
Contents
1
Introduction............................................................................................................ 13
1.1
1.2
1.3
Terminology ..................................................................................................... 13
Related Documents ........................................................................................... 19
Intel® 5000X Chipset Overview .......................................................................... 19
2
Signal Description ................................................................................................... 23
2.1
2.2
2.3
Processor Front Side Bus Signals......................................................................... 25
2.1.1 Processor Front Side Bus 0 ...................................................................... 25
2.1.2 Processor Front Side Bus 1 ...................................................................... 27
Fully Buffered DIMM Memory Channels................................................................. 29
2.2.1 FB-DIMM Branch 0 ................................................................................. 29
2.2.2 FB-DIMM Branch 1 ................................................................................. 30
PCI Express* Signal List..................................................................................... 30
2.3.1 PCI Express* Common Signals................................................................. 30
2.3.2 PCI Express Port 0, Enterprise South Bridge Interface (ESI)......................... 31
2.3.3 PCI Express Port 2.................................................................................. 31
2.3.4 PCI Express Port 3.................................................................................. 31
2.3.5 PCI Express* Graphics Port...................................................................... 32
System Management Bus Interfaces .................................................................... 33
XD Port Signal List............................................................................................. 33
JTAG Bus Signal List .......................................................................................... 33
Clocks, Reset and Miscellaneous.......................................................................... 34
Power and Ground Signals.................................................................................. 34
MCH Sequencing Requirements........................................................................... 34
2.4
2.5
2.6
2.7
2.8
2.9
2.10 Reset Requirements........................................................................................... 36
2.10.1 Timing Diagrams.................................................................................... 36
2.10.2 Reset Timing Requirements ..................................................................... 38
2.10.3 Miscellaneous Requirements and Limitations .............................................. 39
2.11 Intel® 5000P Chipset Platform Signal Routing Topology Diagrams ........................... 40
2.11.1 Intel® 5000P Customer Reference Platform (SRP) Reset Topology................ 41
2.12 Signals Used as Straps....................................................................................... 41
2.12.1 Functional Straps ................................................................................... 41
3
Register Description................................................................................................ 43
3.1
3.2
3.3
Register Terminology......................................................................................... 43
Platform Configuration Structure ......................................................................... 44
Routing Configuration Accesses........................................................................... 47
3.3.1 Standard PCI Bus Configuration Mechanism ............................................... 47
3.3.2 PCI Bus 0 Configuration Mechanism.......................................................... 47
3.3.3 Primary PCI and Downstream Configuration Mechanism............................... 48
Device Mapping................................................................................................. 48
3.4.1 Device Identification for Intel 5000P Chipset, Intel 5000Z Chipset,
and Intel 5000V Chipset Components........................................................ 49
3.4.2 Special Device and Function Routing......................................................... 50
I/O Mapped Registers ........................................................................................ 51
3.5.1 CFGADR: Configuration Address Register................................................... 51
3.5.2 CFGDAT: Configuration Data Register ....................................................... 52
MCH Fixed Memory Mapped Registers .................................................................. 52
Detailed Configuration Space Maps ...................................................................... 53
Register Definitions ........................................................................................... 72
3.8.1 PCI Standard Registers ........................................................................... 72
3.8.2 Address Mapping Registers...................................................................... 81
3.8.3 AMB Memory Mapped Registers................................................................ 90
3.4
3.5
3.6
3.7
3.8
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
3
3.8.4 Interrupt Redirection Registers.................................................................93
3.8.5 Boot and Reset Registers.........................................................................94
3.8.6 Control and Interrupt Registers ................................................................98
3.8.7 PCI Express Device Configuration Registers..............................................100
3.8.8 PCI Express Header ..............................................................................102
3.8.9 PCI Express Power Management Capability Structure.................................131
3.8.10 PCI Express Message Signaled Interrupts (MSI) Capability Structure............134
3.8.11 PCI Express Capability Structure.............................................................138
3.8.12 PCI Express Advanced Error Reporting Capability ......................................160
3.8.13 Error Registers .....................................................................................182
Memory Control Registers.................................................................................194
3.9.1 MC - Memory Control Settings................................................................194
3.9.2 GBLACT - Global Activation Throttle Register ............................................196
3.9.3 THRTSTS[1:0] - Thermal Throttling Status Register...................................197
3.9.4 THRTLOW - Thermal Throttling Low Register ............................................198
3.9.5 THRTMID - Thermal Throttle Mid Register ................................................198
3.9.6 THRTHI - Thermal Throttle High Register .................................................199
3.9.7 THRTCTRL - Thermal Throttling Control Register .......................................199
3.9.8 MCA - Memory Control Settings A ...........................................................199
3.9.9 DDRFRQ - DDR Frequency Ratio .............................................................200
3.9.10 FBDTOHOSTGRCFG0: FB-DIMM to Host Gear Ratio Configuration 0..............200
3.9.11 FBDTOHOSTGRCFG1: FB-DIMM to Host Gear Ratio Configuration 1..............201
3.9.12 HOSTTOFBDGRCFG: Host to FB-DIMM Gear Ratio Configuration..................202
3.9.13 GRFBDVLDCFG: FB-DIMM Valid Configuration...........................................202
3.9.14 GRHOSTFULLCFG: Host Full Flow Control Configuration..............................204
3.9.15 GRBUBBLECFG: FB-DIMM Host Bubble Configuration .................................204
3.9.16 GRFBDTOHOSTDBLCFG: FB-DIMM To Host Double Configuration.................205
3.9.17 Summary of Memory Gearing Register operating modes ............................205
3.9.18 DRTA - DRAM Timing Register A .............................................................205
3.9.19 DRTB - DDR Timing Register B ...............................................................207
3.9.20 ERRPER - Error Period ...........................................................................208
3.9.21 Memory Map Registers ..........................................................................208
3.9.22 FB-DIMM Error Registers........................................................................210
3.9.23 FB-DIMM Branch Registers.....................................................................225
3.9.24 FB-DIMM RAS Registers.........................................................................234
3.9.25 FB-DIMM Intel IBIST Registers ...............................................................237
3.9.26 Serial Presence Detect Registers.............................................................252
3.9
3.10 DMA Engine Configuration Registers...................................................................253
3.10.1 PCICMD: PCI Command Register ............................................................253
3.10.2 PCISTS: PCI Status Register ..................................................................255
3.10.3 CCR: Class Code Register ......................................................................256
3.10.4 CB_BAR: DMA Engine Base Address Register............................................256
3.10.5 CAPPTR: Capability Pointer Register ........................................................257
3.10.6 INTL: Interrupt Line Register..................................................................257
3.10.7 INTP: Interrupt Pin Register...................................................................257
3.10.8 Power Management Capability Structure ..................................................257
3.10.9 MSICAPID - Message Signalled Interrupt Capability ID Register...................260
3.10.10MSINXPTR - Message Signalled Interrupt Next Pointer Register...................260
3.10.11MSICTRL - Message Signalled Interrupt Control Register ............................260
3.10.12MSIAR: Message Signalled Interrupt Address Register ...............................262
3.10.13MSIDR: Message Signalled Interrupt Data Register....................................262
3.10.14PEXCAPID: PCI Express Capability ID Register..........................................263
3.10.15PEXNPTR: PCI Express Next Pointer Register ............................................263
3.10.16PEXCAPS - PCI Express Capabilities Register ............................................264
3.10.17PEXDEVCAP - Device Capabilities Register................................................264
3.10.18PEXDEVCTRL - Device Control Register....................................................265
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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
3.10.19PEXDEVSTS - PCI Express Device Status Register..................................... 266
3.11 PCI Express Intel IBIST Registers...................................................................... 267
3.11.1 DIOIBSTR: PCI Express Intel IBIST Global Start/Status Register................. 267
3.11.2 DIO0IBSTAT: PCI Express Intel IBIST Completion Status Register............... 268
3.11.3 DIO0IBERR: PCI Express Intel IBIST Error Register................................... 268
3.11.4 PEX[7:2,0]IBCTL: PEX Intel IBIST Control Register................................... 269
3.11.5 PEX[7:2,0]IBSYMBUF: PEX Intel IBIST Symbol Buffer ............................... 270
3.11.6 PEX[7:2,0]IBEXTCTL: PEX Intel IBIST Extended Control Register................ 271
3.11.7 PEX[7:2,0]IBDLYSYM: PEX Intel IBIST Delay Symbol ................................ 273
3.11.8 PEX[7:2,0]IBLOOPCNT: PEX Intel IBIST Loop Counter............................... 273
3.11.9 PEX[7:2,0]IBLNS[3:0]: PEX Intel IBIST Lane Status ................................. 274
3.11.10DIO[1:0]SQUELCH_CNT: PCIe Cluster Squelch Count................................ 275
4
System Address Map ............................................................................................. 277
4.1
System Memory Address Ranges....................................................................... 278
4.1.1 32/64-bit addressing ............................................................................ 278
Compatibility Area........................................................................................... 280
4.2.1 MS-DOS Area (0 0000h–9 FFFFh)........................................................... 280
4.2.2 Legacy VGA Ranges (A 0000h–B FFFFh) .................................................. 281
4.2.3 Expansion Card BIOS Area (C 0000h–D FFFFh)......................................... 282
4.2.4 Lower System BIOS Area (E 0000h–E FFFFh)........................................... 282
4.2.5 Upper System BIOS Area (F 0000h–F FFFFh) ........................................... 283
System Memory Area....................................................................................... 283
4.3.1 System Memory................................................................................... 283
4.3.2 15 MB - 16 MB Window (ISA Hole).......................................................... 283
4.3.3 Extended SMRAM Space (TSEG)............................................................. 283
4.3.4 Memory Mapped Configuration (MMCFG) Region....................................... 284
4.3.5 Low Memory Mapped I/O (MMIO) ........................................................... 285
4.3.6 Chipset Specific Range.......................................................................... 286
4.3.7 Interrupt/SMM Region........................................................................... 286
4.3.8 High Extended Memory ......................................................................... 288
4.3.9 Main Memory Region ............................................................................ 289
Memory Address Disposition ............................................................................. 289
4.4.1 Registers Used for Address Routing......................................................... 289
4.4.2 Address Disposition for Processor ........................................................... 290
4.4.3 Inbound Transactions ........................................................................... 293
I/O Address Map ............................................................................................. 295
4.5.1 Special I/O Addresses........................................................................... 295
4.5.2 Outbound I/O Access............................................................................ 295
Configuration Space ........................................................................................ 297
I/O Address Map ............................................................................................. 297
4.7.1 Special I/O Addresses........................................................................... 297
4.7.2 Outbound I/O Access............................................................................ 298
Configuration Space ........................................................................................ 298
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5
Functional Description........................................................................................... 299
5.1
Processor Front Side Buses............................................................................... 299
5.1.1 FSB Overview ...................................................................................... 299
5.1.2 FSB Dynamic Bus Inversion ................................................................... 300
5.1.3 FSB Interrupt Overview......................................................................... 300
Snoop Filter.................................................................................................... 301
5.2.1 Snoop Filter Address Bit Mapping............................................................ 304
5.2.2 Operations and Interfaces ..................................................................... 304
System Memory Controller ............................................................................... 305
5.3.1 Memory Population Rules ...................................................................... 307
5.3.2 Fully Buffered DIMM Technology and Organization .................................... 310
5.3.3 FB-DIMM Memory Operating Modes ........................................................ 312
5.2
5.3
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
5
5.3.4 Data Poisoning in Memory......................................................................314
5.3.5 Patrol Scrubbing...................................................................................314
5.3.6 Demand Scrubbing ...............................................................................315
5.3.7 x8 Correction .......................................................................................315
5.3.8 Single Device Data Correction (SDDC) Support.........................................316
5.3.9 FB-DIMM Memory Configuration Mechanism .............................................316
5.3.10 FB-DIMM Memory Failure Isolation Mechanisms ........................................318
5.3.11 DDR2 Protocol......................................................................................322
5.3.12 Memory Thermal Management................................................................322
5.3.13 Electrical Throttling...............................................................................333
Behavior on Overtemp State in AMB...................................................................333
Interrupts.......................................................................................................334
XAPIC Interrupt Message Delivery......................................................................334
5.6.1 XAPIC Interrupt Message Format ............................................................334
5.6.2 XAPIC Destination Modes.......................................................................335
5.6.3 Interrupt Redirection.............................................................................336
5.6.4 EOI.....................................................................................................338
I/O Interrupts .................................................................................................338
5.7.1 Ordering..............................................................................................338
5.7.2 Hardware IRQ IOxAPIC Interrupts...........................................................339
5.7.3 Message Signalled Interrupts .................................................................339
5.7.4 Non-MSI Interrupts - “Fake MSI” ............................................................339
Interprocessor Interrupts (IPIs).........................................................................340
Chipset Generated Interrupts ............................................................................342
5.9.1 Intel 5000X Chipset Generation of MSIs..................................................344
5.4
5.5
5.6
5.7
5.8
5.9
5.10 Legacy/8259 Interrupts....................................................................................346
5.11 Interrupt Error Handling ...................................................................................346
5.12 Enterprise South Bridge Interface (ESI) ..............................................................347
5.12.1 Power Management Support...................................................................348
5.12.2 Special Interrupt Support.......................................................................348
5.12.3 Inbound Interrupts ...............................................................................348
5.12.4 Legacy Interrupt Messages ....................................................................349
5.12.5 End-of-Interrupt (EOI) Support ..............................................................349
5.12.6 Error Handling......................................................................................349
5.13 PCI Express Ports ............................................................................................349
5.13.1 Intel 5000X Chipset MCH PCI Express Port Overview ................................350
5.13.2 Enterprise South Bridge Interface (ESI) ...................................................351
5.13.3 PCI Express Ports 2 and 3......................................................................351
5.13.4 PCI Express General Purpose Ports..........................................................352
5.13.5 Supported Length Width Port Partitioning.................................................353
5.13.6 PCI Express Port Support Summary ........................................................354
5.13.7 PCI Express Port Physical Layer Characteristics.........................................355
5.13.8 Link Layer............................................................................................357
5.13.9 Flow Control.........................................................................................359
5.13.10Transaction Layer .................................................................................361
5.14 Power Management..........................................................................................361
5.14.1 Supported ACPI States ..........................................................................361
5.14.2 FB-DIMM Thermal Management..............................................................362
5.14.3 FB-DIMM Thermal Diode Overview ..........................................................362
5.15 System Reset..................................................................................................362
5.15.1 MCH Power Sequencing .........................................................................362
5.15.2 MCH Reset Types..................................................................................363
5.15.3 Targeted Reset Mechanism ....................................................................364
5.15.4 BINIT# Mechanism ...............................................................................365
5.15.5 Reset Sequencing .................................................................................365
5.16 SMBus Interfaces Description ............................................................................366
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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
5.16.1 Internal Access Mechanism.................................................................... 367
5.16.2 SMBus Transaction Field Definitions ........................................................ 368
5.16.3 SMB Transaction Pictographs ................................................................. 371
5.16.4 Slave SM Bus, SM Bus 0........................................................................ 373
5.16.5 FB-DIMM SPD Interface, SM Buses 1, 2, 3 and 4 ...................................... 378
5.16.6 PCI Express Hot-Plug Support, SM Bus 6 ................................................. 379
5.16.7 Hot-Plug Controller............................................................................... 380
5.16.8 PCI Express Hot-Plug Usage Model.......................................................... 380
5.16.9 Virtual Pin Ports ................................................................................... 381
5.17 Clocking......................................................................................................... 384
5.17.1 Reference Clocks.................................................................................. 384
5.17.2 JTAG .................................................................................................. 386
5.17.3 SMBus Clock........................................................................................ 386
5.17.4 GPIO Serial Bus Clock........................................................................... 386
5.17.5 Clock Pins ........................................................................................... 386
5.17.6 High Frequency Clocking Support ........................................................... 387
5.18 Error List........................................................................................................ 388
6
Testability ............................................................................................................. 395
6.1
JTAG Port....................................................................................................... 395
6.1.1 JTAG Access to Configuration Space........................................................ 395
6.1.2 TAP Signals ......................................................................................... 395
6.1.3 Accessing the TAP Logic ........................................................................ 396
6.1.4 Reset Behavior of the TAP ..................................................................... 398
6.1.5 Clocking the TAP.................................................................................. 398
6.1.6 Accessing the Instruction Register .......................................................... 398
6.1.7 Accessing the Data Registers ................................................................. 400
6.1.8 Public TAP Instructions.......................................................................... 400
6.1.9 Public Data Instructions ........................................................................ 401
6.1.10 Public Data Register Control................................................................... 402
6.1.11 Bypass Register ................................................................................... 402
6.1.12 Device ID Register................................................................................ 402
6.1.13 Boundary Scan Register ........................................................................ 403
Extended Debug Port (XDP).............................................................................. 404
6.2
7
Electrical Characteristics ....................................................................................... 405
7.1
Absolute Maximum Ratings............................................................................... 405
7.1.1 Thermal Characteristics......................................................................... 405
7.1.2 Power Characteristics............................................................................ 405
DC Characteristics........................................................................................... 406
7.2.1 Clock DC Characteristics........................................................................ 407
7.2.2 FSB Interface DC Characteristics ............................................................ 408
7.2.3 FB-DIMM DC Characteristics .................................................................. 409
7.2.4 PCI Express/ ESI Interface DC Characteristics .......................................... 410
7.2.5 Miscellaneous DC Characteristics............................................................ 411
7.2
8
Ballout and Package Information........................................................................... 413
8.1
8.2
Intel 5000X Chipset MCH Ballout ....................................................................... 413
Package Information........................................................................................ 455
Figures
1-1
2-1
2-2
2-3
2-4
2-5
Intel® 5000X Chipset System Block Diagram........................................................ 21
Intel 5000X Chipset Clock and Reset Requirements.............................................. 35
Power-Up......................................................................................................... 36
PWRGOOD ....................................................................................................... 36
Hard Reset....................................................................................................... 37
RESETI# Retriggering Limitations........................................................................ 37
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
7
2-6
2-7
2-8
3-1
3-2
3-3
3-4
3-5
3-6
3-7
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
Simplest Power Good Distribution ........................................................................40
Basic System Reset Distribution...........................................................................40
Basic INIT# Distribution .....................................................................................40
Conceptual Intel® 5000X chipset MCH PCI Configuration Diagram...........................46
Type 1 Configuration Address to PCI Address Mapping............................................48
Intel 5000P Chipset MCH implementation of SRID and CRID Registers ......................77
PCI Express Configuration Space........................................................................102
PCI Express Hot-Plug Interrupt Flow...................................................................157
FB-DIMM Reset Timing .....................................................................................228
Intel 5000P Chipset DMA Error/Channel Completion Interrupt Handling Flow............261
System Memory Address Map............................................................................278
Detailed Memory System Address Map ...............................................................279
Interrupt /SMM Region .....................................................................................286
System I/O Address Space................................................................................296
System I/O Address Space................................................................................298
Snoop Filter ....................................................................................................302
Minimum Two DIMM Configuration .....................................................................308
Next Two DIMM Upgrade Positions .....................................................................308
Single DIMM Operation Mode.............................................................................309
Minimum Mirrored Mode Memory Configuration....................................................309
Mirrored Mode Next Upgrade.............................................................................310
FB-DIMM Channel Schematic.............................................................................311
Connection of DIMM Serial I/O Signals................................................................317
Code Layout for Single-Channel Branches ...........................................................320
5-10 Code Layout for Dual-Channel Branches .............................................................321
5-11 Thermal Throttling with THRMHUNT=1................................................................326
5-12 Thermal Throttling with THRMHUNT=0................................................................326
5-13 Thermal Throttling Activation Algorithm..............................................................328
5-14 XAPIC Address Encoding...................................................................................335
5-15 PCI Express Hot-Plug Interrupt Flow...................................................................343
5-16 MCH to Intel 631xESB/632xESB I/O Controller Hub Enterprise South Bridge Interface....
347
5-17 x4 PCI Express Bit Lane....................................................................................350
5-18 ESI and PCI Express Ports 2 and 3.....................................................................351
5-19 MCH to Intel 631xESB/632xESB I/O Controller Hub Port Configurations ..................352
5-20 Intel 5000X Chipset PCI Express* High Performance x16 Port...............................353
5-21 PCI Express Packet Visibility By Physical Layer.....................................................355
5-22 PCI Express Elastic Buffer (x4 Example)..............................................................356
5-23 PCI Express Deskew Buffer (4X Example) ...........................................................357
5-24 PCI Express Packet Visibility By Link Layer ..........................................................358
5-25 PCI Express Packet Visibility By Transaction Layer................................................361
5-26 Intel 5000P Chipset Power Sequencing ...............................................................362
5-27 Power-On Reset Sequence ................................................................................366
5-28 MCH SM Bus Interfaces ....................................................................................367
5-29 DWORD Configuration Read Protocol (SMBus Block Write / Block Read,
PEC Disabled) .................................................................................................371
5-30 DWORD Configuration Write Protocol (SMBus Block Write, PEC Disabled) ................371
5-31 DWORD Memory Read Protocol (SMBus Block Write / Bock Read, PEC Disabled).......372
5-32 DWORD Memory Write Protocol .........................................................................372
5-33 DWORD Configuration Read Protocol (SMBus Word Write / Word Read,
PEC Disabled) .................................................................................................372
5-34 DWORD Configuration Write Protocol (SMBus Word Write, PEC Disabled).................372
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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
5-35 DWORD Memory Read Protocol (SMBus Word Write / Word Read, PEC Disabled)...... 373
5-36 WORD Configuration Wrote Protocol (SMBus Byte Write, PEC Disabled) .................. 373
5-37 SMBus Configuration Read (Block Write / Block Read, PEC Enabled)....................... 375
5-38 SMBus Configuration Read (Word Writes / Word Reads, PEC Enabled) .................... 376
5-39 SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled) ...................... 376
5-40 SMBus Configuration Write (Block Write, PEC Enabled)......................................... 376
5-41 SMBus Configuration Write (Word Writes, PEC Enabled)........................................ 377
5-42 SMBus Configuration Write (Write Bytes, PEC Enabled)......................................... 377
5-43 Random Byte Read Timing................................................................................ 378
5-44 Byte Write Register Timing ............................................................................... 379
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
PCI Express Hot-Plug/VPP Block Diagram............................................................ 382
Simplified TAP Controller Block Diagram............................................................. 396
TAP Controller State Machine............................................................................ 397
TAP Instruction Register................................................................................... 399
TAP Instruction Register Operation .................................................................... 399
TAP Instruction Register Access......................................................................... 400
TAP Data Register ........................................................................................... 401
Bypass Register Implementation ....................................................................... 402
Intel 5000X Chipset Quadrant Map .................................................................... 413
Intel 5000X Chipset MCH Ballout Left Side (Top View).......................................... 414
Intel 5000X Chipset MCH Ballout Center (Top View)............................................. 415
Intel 5000X Chipset MCH Ballout Right Side (Top View)........................................ 416
Bottom View................................................................................................... 455
Top View........................................................................................................ 456
Package Stackup............................................................................................. 457
Notes ............................................................................................................ 458
Tables
1-1
General Terminology.......................................................................................... 13
Signal Naming Conventions ................................................................................ 24
Buffer Signal Types ........................................................................................... 24
Power Up and Hard Reset Timings ....................................................................... 38
Critical Intel® 5000P Initialization Timings ........................................................... 39
Configuration Address Bit Mapping....................................................................... 49
Memory Control Hub ESI Device Identification....................................................... 49
Functions Specially Handled by the MCH............................................................... 50
Access to “Non-Existent” Register Bits.................................................................. 51
I/O Address: CF8h............................................................................................. 51
I/O Address: CFCh ............................................................................................ 52
Mapping for Fixed Memory Mapped Registers ........................................................ 52
Device 0, Function 0: PCI Express PCI Space ........................................................ 53
Device 0, Function 0: PCI Express Extended Registers............................................ 54
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10 Device 0, Function 0: PCI Express Intel® Interconnect BIST
(Intel® IBIST) Registers .................................................................................... 55
3-11 Device 2-3, Function 0: PCI Express PCI Space ..................................................... 56
3-12 Device 2-3, Function 0: PCI Express Extended Registers......................................... 57
3-13 Device 2-3, Function 0: PCI Express Intel IBIST Registers....................................... 58
3-14 Device 4, Function 0: PCI Express PCI Space ........................................................ 59
3-15 Device 4, Function 0: PCI Express Extended Registers............................................ 60
3-16 Device 4, Function 0: PCI Express Intel IBIST Registers.......................................... 61
3-17 Device 5-7, Function 0: PCI Express PCI Space ..................................................... 62
3-18 Device 5-7, Function 0: PCI Express Extended Registers......................................... 63
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
9
3-19 Device 5-7, Function 0: PCI Express Intel IBIST Registers.......................................64
3-20 Device 9, Function 0: AMB Switching Window Registers ..........................................64
3-21 Device 16, Function 0: Processor Bus, Boot, and Interrupt ......................................65
3-22 Device 16, Function 1: Memory Branch Map, Control, Errors....................................66
3-23 Device 16, Function 2: RAS.................................................................................67
3-24 Device 21, 22, Function 0: FB-DIMM Map, Control, RAS ..........................................68
3-25 Device 21, Function 0: FB-DIMM 0 Intel IBIST Registers .........................................69
3-26 Device 21, Function 0: FB-DIMM 1 IBST Registers.................................................70
3-27 Device 22, Function 0: FB-DIMM 2 IBST Registers..................................................71
3-28 Device 22, Function 0: FB-DIMM 3 Intel IBIST Registers .........................................72
3-29 Address Mapping Registers .................................................................................81
3-30 Register Offsets in AMB Memory Mapped Registers Region ......................................92
3-31 XTPR Index.......................................................................................................99
3-32 When will an Intel 5000X Chipset PCI Express* Device be Accessible? ....................100
3-33 Intel 5000P Chipset MCH PCISTS and SECSTS Master/Data
Parity Error RAS Handling .................................................................................113
3-1
GIO Port Mode Selection...................................................................................125
3-34 IV Handling and Processing by MCH ...................................................................137
3-35 Maximum Link Width Default Value for Different PCI Express Ports.........................147
3-36 Negotiated Link Width For Different PCI Express Ports After Training ......................150
3-37 Global Activation Throttling as a Function of Global Activation Throttling Limit
(GBLACTM) and Global Throttling Window Mode (GTW_MODE) Register Fields..........196
3-38 FB-DIMM to Host Gear Ratio Mux.......................................................................201
3-39 FB-DIMM to Host Gear Ratio Mux.......................................................................201
3-40 Host to FB-DIMM Gear Ratio Mux Select..............................................................202
3-41 FB-DIMM Host Data Cycle Valid Mux Select .........................................................203
3-42 FB-DIMM to Host Flow Control Mux Select...........................................................204
3-43 FB-DIMM Bubble Mux Select..............................................................................204
3-44 FB-DIMM to Host Double Config Mux Select.........................................................205
3-45 Optimum TREF values as a function of core: FBD gear ratios (in FBD Super frames) .207
3-46 Timing Characteristics of ERRPER.......................................................................208
3-47 Interleaving of an address is governed by MIR[i]..................................................209
3-48 NRECFBD Mapping Information..........................................................................220
3-49 ECC Locator Mapping Information ......................................................................222
3-50 IV Vector Table for DMA Errors and Interrupts .....................................................263
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
Memory Segments and Their Attributes ..............................................................280
PAM Settings...................................................................................................282
Low Memory Mapped I/O1 ................................................................................285
I/O APIC Address Mapping ................................................................................287
Intel 5000X chipset MCH Memory Mapping Registers ............................................289
Address Disposition for Processor.......................................................................290
Enabled SMM Ranges .......................................................................................292
SMM Memory Region Access Control from Processor.............................................292
Decoding Processor Requests to SMM and VGA Spaces .........................................293
4-10 Address Disposition for Inbound Transactions ......................................................294
5-1
5-1
5-2
5-3
5-2
5-3
5-4
DBI[3:0]# / Data Bit Correspondence.................................................................300
Snoop Filter Physical Address Partitioning ...........................................................304
FSB transaction encoding qualification for SF look up............................................304
Snoop Filter Entry............................................................................................304
Minimum System Memory Configurations & Upgrade Increments............................306
Maximum 16 DIMM System Memory Configurations..............................................307
Maximum 16 DIMM System Memory Configurations..............................................307
10
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
5-5
5-6
5-7
5-8
5-9
Memory Poisoning Table................................................................................... 314
x8 Double Device Detection Characteristics......................................................... 316
SPD Addressing............................................................................................... 317
AMB Thermal Status Bit Definitions.................................................................... 323
FB_DIMM Bandwidth as a Function of Closed Loop Thermal Throttling .................... 329
5-10 Global Activation Throttling BW allocation as a function of GBLACTLM for a
16384**1344 window with MC.GTW_Mode=0 (normal)........................................ 332
5-11 Electrical Throttle Window as a Function of DIMM Technology................................ 333
5-12 XAPIC Data Encoding....................................................................................... 335
5-13 Intel 5000X Chipset XAPIC Interrupt Message Routing and Delivery ...................... 336
5-14 Chipset Generated Interrupts............................................................................ 344
5-4
PCI Express Link Width Strapping Options for Port CPCI Configuration in MCH ......... 354
5-15 Options and Limitations.................................................................................... 354
5-16 PCI Express Credit Mapping for Inbound Transactions .......................................... 359
5-17 PCI Express Credit Mapping for Outbound Transactions ........................................ 360
5-18 MCH Reset Classes .......................................................................................... 363
5-19 Reset Sequences and Durations ........................................................................ 366
5-20 SMBus Transaction Field Summary .................................................................... 368
5-21 SMBus Address for Product Name Platform ......................................................... 374
5-22 SMBus Command Encoding............................................................................... 374
5-23 Status Field Encoding for SMBus Reads .............................................................. 375
5-24 MCH Supported SPD Protocols........................................................................... 379
5-25 I/O Port Registers in I/O Extender supported by Intel 5000X Chipset MCH ............. 383
5-26 Hot-Plug Signals on a Virtual Pin Port................................................................. 384
5-27 Intel 5000X Chipset MCH Frequencies for Processors and Core ............................. 385
5-28 Intel 5000X Chipset MCH Frequencies for Memory .............................................. 385
5-29 Intel 5000X Chipset MCH Frequencies for PCI Express......................................... 386
5-30 Clock Pins ...................................................................................................... 386
5-31 Intel 5000X chipset Error List.......................................................................... 388
6-1
6-2
6-3
6-4
6-5
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
TAP Signal Definitions...................................................................................... 395
TAP Reset Actions ........................................................................................... 398
Public TAP Instructions..................................................................................... 401
Actions of Public TAP Instructions During Various TAP States................................. 402
Intel® 5000P chipset Device ID Codes ............................................................... 403
Absolute Maximum Ratings............................................................................... 405
Operating Condition Power Supply Rails ............................................................. 405
Analog and Bandgap Voltage and Current Specifications ....................................... 406
Clock DC Characteristics................................................................................... 407
FSB Interface DC Characteristics ....................................................................... 408
FB-DIMM Transmitter (Tx) Output DC Characteristics........................................... 409
FB-DIMM Receiver (Rx) Output DC Characteristics ............................................... 409
PCI Express/ ESI Differential Transmitter (Tx) Output DC Characteristics................ 410
PCI Express/ ESI Differential Receiver (Rx) Input DC Characteristics ...................... 410
7-10 SMBus DC Characteristics................................................................................. 411
7-11 JTAG DC Characteristics................................................................................... 411
7-12 1.5 V CMOS DC Characteristics ......................................................................... 411
7-13 3.3 V CMOS DC Characteristics ......................................................................... 411
8-1
8-2
Intel 5000X Chipset MCH Signals (by Ball Number).............................................. 417
Intel 5000X Chipset MCH Signals (by Signal Name) ............................................. 436
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
11
Revision History
Revision
Number
Description
Date
0.5
001
002
003
Initial release
January 2004
May 2006
Final document release
®
®
Added support for Dual-Core Intel Xeon 5100 series
DMA section updated
June 2006
August 2006
§
12
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
Introduction
1 Introduction
The Intel® 5000X chipset is designed for systems based on the Dual-Core Intel®
Xeon® 5000 sequence and supports a FSB frequency up to 1333 MTS. The Intel 5000X
chipset contains two main components: Memory Controller Hub (MCH) for the host
bridge and the I/O controller hub for the I/O subsystem. The Intel 5000X chipset uses
the Intel® 631xESB/632xESB I/O Controller Hub for the I/O Controller Hub. This
document is the datasheet for the Intel 5000X chipset Memory Controller Hub (MCH)
components.
The Intel 5000X chipset is packaged in a 1432 pin FCBGA package with pins on
1.092 mm (37 mil) centers. The overall package dimensions are 42.5 mm by 42.5 mm.
The Intel 5000 Series chipset platform supports the Dual-Core Intel® Xeon® 5000
series (1066 MHz with 2 MB L2 cache on 65nm process in a 771-land, FC-LGA4 (Flip
Chip Land Grid Array 4) package and the Dual-Core Intel® Xeon® 5100 series
(1333 MHz with 4 MB shared L2 cache) on 65nm process in a 771-land, FC-LGA4 (Flip
Chip Land Grid Array 4) package. This package uses the matching LGA771 socket. The
surface mount, LGA771 socket supports Direct Socket Loading (DSL). The Dual-Core
Intel Xeon 5000 sequence (1066/1333 MHz) returns a processor signature of 0F5xh
where x is the stepping number when the CPUID instruction is executed with EAX=1.
Note:
Unless otherwise specified, the term processor in this document refers to the
Dual-Core Intel Xeon 5000 sequence processors at both 1066 MHz with 2 MB L2 cache
and 1333 MHz with 4 MB shared L2 cache on 65nm process in the 771-pin FC-LGA4
package.
1.1
Terminology
This section provides the definitions of some of the terms used in this document.
Table 1-1.
General Terminology (Sheet 1 of 7)
Terminology
Agent
Description
A logical device connected to a bus or shared interconnect that can either initiate
accesses or be the target of accesses. Each thread executing within a processor is a
unique agent.
aka
also known as
Asserted
Asserted Signal is set to a level that represents logical true. For signals that end with
“#” this means driving a low voltage. For other signals, it is a high voltage.
Atomic operation
AGP
A series of operations, any one of which cannot be observed to complete unless all are
observed to complete.
Accelerated Graphics Port. In this document AGP refers to the AGP/PCI interface that
is in the MCH. The MCH AGP interface supports only 0.8 V/1.5 V AGP 2.0/AGP 3.0
compliant devices using PCI (66 MHz), AGP 1X (66 MHz), 4X (266 MHz), and 8X (533
MHz) transfers. MCH does not support any 3.3 V devices. For AGP 2.0, PIPE# and SBA
addressing cycles and their associated data phases are generally referred to as AGP
transactions. FRAME# cycles are generally referred to as AGP/PCI transactions
Bank
DRAM chips are divided into multiple banks internally. Commodity parts are all 4 bank,
which is the only type the MCH supports. Each bank acts somewhat like a separate
DRAM, opening and closing pages independently, allowing different pages to be open
in each. Most commands to a DRAM target a specific bank, but some commands (that
is, Precharge All) are targeted at all banks. Multiple banks allows higher performance
by interleaving the banks and reducing page miss cycles.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
13
Introduction
Table 1-1.
General Terminology (Sheet 2 of 7)
Terminology
Description
Buffer
1.
2.
A random access memory structure.
The term I/O buffer is also used to describe a low level input receiver and output
driver combination.
Cache Line
CDM
The unit of memory that is copied to and individually tracked in a cache. Specifically,
64 bytes of data or instructions aligned on a 64-byte physical address boundary.
Central Data Manager. A custom array within the Intel 5000X chipset that acts as a
temporary repository for system data in flight between the various ports: FSB’s,
FBD’s, ESI, and PCI Express*.
Cfg, Config
Channel
Abbreviation for “Configuration”.
In the MCH a FBD DRAM channel is the set of signals that connects to one set of FBD
DIMMs. The MCH has up to four DRAM channels.
Character
The raw data byte in an encoded system (for example, the 8b value in a 8b/10b
encoding scheme). This is the meaningful quantum of information to be transmitted or
that is received across an encoded transmission path.
Chipset Core
Coherent
The MCH internal base logic.
Transactions that ensure that the processor's view of memory through the cache is
consistent with that obtained through the I/O subsystem.
Command
The distinct phases, cycles, or packets that make up a transaction. Requests and
completions are referred to generically as Commands.
Completion
A packet, phase, or cycle used to terminate a transaction on a interface, or within a
component. A Completion will always refer to a preceding request and may or may not
include data and/or other information.
Core
CRC
The internal base logic in the Intel 5000X chipset.
Cyclic Redundancy Check; A number derived from, and stored or transmitted with, a
block of data in order to detect corruption. By recalculating the CRC and comparing it
to the value originally transmitted, the receiver can detect some types of transmission
errors.
Critical Word First
DDR
On the DRAM, Processor, and Memory interfaces, the requestor may specify a
particular word to be delivered first. This is done using address bits of lower
significance than those required to specify the cache line to be accessed. The
remaining data is then returned in a standardized specified order.
Double Data Rate SDRAM. DDR describes the type of DRAMs that transfers two data
items per clock on each pin. This is the only type of DRAM supported by the MCH.
Deasserted
Signal is set to a level that represents logical false.
Deferred Transaction
A processor bus Split Transaction. On the processor bus, the requesting agent
receives a Deferred Response which allows other transactions to occur on the bus.
Later, the response agent completes the original request with a separate Deferred
Reply transaction or by Deferred Phase.
Delayed Transaction
A transaction where the target retries an initial request, but without notification to the
initiator, forwards or services the request on behalf of the initiator and stores the
completion or the result of the request. The original initiator subsequently re-issues
the request and receives the stored completion
DFx (DFD, DFM, DFT, DFD=Design for Debug
DFV)
DFM=Design for Manufacturing
DFT=Design for Testability
DFV=Design for Validation
DIMM
Dual-in-Line Memory Module. A packaging arrangement of memory devices on a
socketable substrate.
Double-Sided DIMM
Terminology often used to describe a DIMM that contain two DRAM rows. Generally a
Double-sided DIMM contains two rows, with the exception noted above. This
terminology is not used within this document.
Downstream
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound”
DRAM Page (Row)
The DRAM cells selected by the Row Address.
®
14
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Introduction
Table 1-1.
General Terminology (Sheet 3 of 7)
Terminology
Description
Dword
A reference to 32 bits of data on a naturally aligned four-byte boundary (that is, the
least significant two bits of the address are 00b).
ECC
Error Correcting Code
®
ESB2
Intel 631xESB/632xESB I/O Controller Hub
FBD
Fully Buffered DDRII
FBD Channel
FSB
One electrical interface to one or more Fully Buffered DDRII DIMM.
Processor Front-Side Bus. This is the bus that connects the processor to the MCH.
Full Duplex
A connection or channel that allows data or messages to be transmitted in opposite
directions simultaneously.
GART
Graphics Aperture Re-map Table. GART is a table in memory containing the page re-
map information used during AGP aperture address translations.
9
GB/s
Gb/s
GTLB
Gigabytes per second (10 bytes per second).
9
Gigabits per second (10 bits per second).
Graphics Translation Look-aside Buffer. A cache used to store frequently used GART
entries.
Hardwired
A parameter that has a fixed value.
Half Duplex
A connection or channel that allows data or messages to be transmitted in either
direction, but not simultaneously.
Host
I/O
This term is used synonymously with processor.
1.
2.
Input/Output.
When used as a qualifier to a transaction type, specifies that transaction targets
Intel architecture-specific I/O space. (for example, I/O read)
®
Intel 631xESB/
6th Generation I/O Controller Hub. The IO Controller Hub component that contains
the legacy I/O functions.
632xESB I/O
Controller Hub
Implicit Writeback
A snoop initiated data transfer from the bus agent with the modified Cache Line to the
memory controller due to an access to that line.
Inband
Communication that is multiplexed on the standard lines of an interface, rather than
requiring a dedicated signal.
Inbound
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound.”
Incoming
A transaction or data that enters the Intel 5000X chipset.
Inbound (IB)/
Outbound (OB), AKA
Upstream/
Up, North, or Inbound is in the direction of the processor, Down, South, or Outbound
is in the direction of IO (SDRAM, SMBus).
DownStream,
Northbound/
Southbound,
Upbound/Downbound
Initiator
The source of requests. An agent sending a request packet on PCI Express is referred
to as the Initiator for that transaction. The Initiator may receive a completion for the
request.
Isochronous
Layer
A classification of transactions or a stream of transactions that require service within a
fixed time interval.
A level of abstraction commonly used in interface specifications as a tool to group
elements related to a basic function of the interface within a layer and to identify key
interactions between layers.
Legacy
Functional requirements handed down from previous chipsets or PC compatibility
requirements from the past.
Line
Link
Lock
Cache line.
The layer of an interface that handles flow control and often error correction by retry.
A sequence of transactions that must be completed atomically.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
15
Introduction
Table 1-1.
General Terminology (Sheet 4 of 7)
Terminology
Description
LSb
Least Significant Bit
Least Significant Byte
LSB
Master
A device or logical entity that is capable of initiating transactions. A Master is any
potential Initiator.
Master Abort
MB/s
A response to an illegal request. Reads receive all ones. Writes have no effect.
6
Megabytes per second (10 bytes per second)
MCH
The Memory Controller Hub component that contains the processor interface, DRAM
controller, PCI Express interface, and AGP interface. It communicates with the I/O
controller hub (Intel 631xESB/632xESB I/O Controller Hub) over a proprietary
interconnect called the Enterprise South Bridge Interface (ESI).
Mem
Used as a qualifier for transactions that target memory space. (for example, A Mem
read to I/O).
Memory Issue
Mesochronous
Metastability
Committing a request to DDR or, in the case of a read, returning the read header.
Distributed or common referenced clock.
A characteristic of flip flops that describes the state where the output becomes non-
deterministic. Most commonly caused by a setup or hold time violation.
Mirroring
MMIO
RAID-1. Please see RAID for detail descriptions.
Memory Mapped IO. Any memory access to PCI Express or 3GIOC ports.
MMCFG
Memory Mapped Configuration. A memory transaction that accesses configuration
space.
MSb
Most Significant Bit.
MSB
Most Significant Byte.
Mean Time Between Failure.
MTBF
Non-Coherent
Transactions that may cause the processor's view of memory through the cache to be
different with that obtained through the I/O subsystem.
Outbound
Outgoing
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound.”
A transaction or completion that exits the Intel 5000X chipset. Peer-to-Peer
Transactions that occur between two devices below the PCI Express or ESI ports.
Packet
The indivisible unit of data transfer and routing, consisting of a header, data, and CRC.
Page Hit.
An access to an open page, or DRAM row. The data can be supplied from the sense
amps at low latency.
Page Miss (Empty
Page)
An access to a page that is not buffered in sense amps and must be fetched from
DRAM array. Address Bit Permuting Address bits are distributed among channel
selects, DRAM selects, bank selects to so that a linear address stream accesses these
resources in a certain sequence.
Page Replace Aka
Page Miss, Row Hit/
Page Miss.
An access to a row that has another page open. The page must be transferred back
from the sense amps to the array, and the bank must be precharged.
PCI
Peripheral Component Interconnect Local Bus. A 32-bit or 64-bit bus with multiplexed
address and data lines that is primarily intended for use as an interconnect
mechanism within a system between processor/memory and peripheral components
or add-in cards.
PCI 2.3 compliant
Plesiochronous
Refers to compliance to the PCI Local Bus Specification, Revision 2.3.
Each end of a link uses an independent clock reference. Support of this operational
mode places restrictions on the absolute frequency difference, as specified by PCI
Express, which can be tolerated between the two independent clock references.
Posted
A transaction that is considered complete by the initiating agent or source before it
actually completes at the target of the request or destination. All agents or devices
handling the request on behalf of the original Initiator must then treat the transaction
as being system visible from the initiating interface all the way to the final destination.
Commonly refers to memory writes.
®
16
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Introduction
Table 1-1.
General Terminology (Sheet 5 of 7)
Terminology
Description
Primary PCI
The physical PCI bus that is driven directly by the Intel® 631xESB/632xESB I/O
Controller Hub component. Communication between PCI and the MCH occurs over
ESI. Note that even though the Primary PCI bus is referred to as PCI it is not PCI Bus
0 from a configuration standpoint.
Push Model
Queue
Method of messaging or data transfer that predominately uses writes instead of reads.
A storage structure for information. Anything that enters a queue will exit eventually.
The most common policy to select an entry to read from the queue is FIFO (First In
First Out).
RAID
Redundant Array of Independent Disks. RAID improves performance by disk striping,
which interleaves bytes or groups of bytes across multiple drives, so more than one
disk is reading and writing simultaneously. Fault tolerance is achieved by mirroring or
parity. Mirroring is 100% duplication of the data on two drives (RAID-1), and parity is
used (RAID-3 and 5) to calculate the data in two drives and store the results on a
third: a bit from drive 1 is XOR'd with a bit from drive 2, and the result bit is stored on
drive 3 (see OR for an explanation of XOR). A failed drive can be hot swapped with a
new one, and the RAID controller automatically rebuilds the lost data. RAID can be
classified into the following categories:
RAID-0
•
RAID-0 is disk striping only, which interleaves data across multiple disks for
better performance. It does not provide safeguards against failure.
RAID-1
Uses disk mirroring, which provides 100% duplication of data. Offers highest
reliability, but doubles storage cost.
RAID-2
Bits (rather than bytes or groups of bytes) are interleaved across multiple disks.
The Connection Machine used this technique, but this is a rare method.
RAID-3
Data are striped across three or more drives. Used to achieve the highest data
•
•
•
transfer, because all drives operate in parallel. Parity bits are stored on separate,
dedicated drives.
RAID-4
Similar to RAID-3, but manages disks independently rather than in unison. Not
often used.
RAID-5
Most widely used. Data are striped across three or more drives for performance,
•
•
and parity bits are used for fault tolerance. The parity bits from two drives are
stored on a third drive.
RAID-6
Highest reliability, but not widely used. Similar to RAID-5, but does two different
parity computations or the same computation on overlapping subsets of the data.
RAID-10
•
•
Actually RAID-1,0. A combination of RAID-1 and RAID-0 (mirroring and striping).
Above definitions can be extended to DRAM memory system as well. To avoid
confusion, the RAID scheme for memory is referred as memory-RAID.
Memory mirroring scheme is actually memory-RAID-1.
RASUM
Reliability, Availability, Serviceability, Usability, and Manageability, which are all
important characteristics of servers.
Receiver, Rcvr
1.
2.
The Agent that receives a packet across an interface regardless of whether it is
the ultimate destination of the packet.
More narrowly, the circuitry required to convert incoming signals from the
physical medium to more perceptible forms.
Request
A packet, phase, or cycle used to initiate a transaction on a interface, or within a
component.
Reserved
The contents or undefined states or information are not defined at this time.
Using any reserved area is not permitted.
RMW
Row
Read-Modify-Write operation.
A group of DRAM chips that fill out the data bus width of the system and are accessed
in parallel by each DRAM command.
Row Address
The row address is presented to the DRAMs during an activate command, and
indicates which page to open within the specified bank (the bank number is presented
also).
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
17
Introduction
Table 1-1.
General Terminology (Sheet 6 of 7)
Terminology
Description
Scalable Bus
Processor-to-MCH interface. The compatible mode of the Scalable Bus is the P6 Bus.
The enhanced mode of the Scalable Bus is the P6 Bus plus enhancements primarily
consisting of source synchronous transfers for address and data, and FSB interrupt
delivery. The Intel Pentium 4 processor implements a subset of the enhanced
mode.
®
®
SDDC
Single Device Disable Code; aka x4 or x8 chip-disable Hamming code to protect single
DRAM device (x4 or x8 data width) failure.
SDR
Single Data Rate SDRAM.
SDRAM
Synchronous Dynamic Random Access Memory.
Single-bit Error Correct / Double-symbol Error Detect
SEC/DED
Secondary PCI
The physical PCI interface that is a subset of the AGP bus driven directly by the MCH.
It supports a subset of 32-bit, 66 MHz PCI 2.0 compliant components, but only at
1.5 V (not 3.3 V or 5 V).
Serial Presence
Detect (SPD)
A two-signal serial bus used to read and write Control registers in the SDRAMs via the
SMBus protocol.
Single-Sided DIMM
Terminology often used to describe a DIMM that contains one DRAM row. Usually one
row fits on a single side of the DIMM allowing the backside to be empty.
Simplex
A connection or channel that allows data or messages to be transmitted in one
direction only.
SMBus
System Management Bus. Mastered by a system management controller to read and
write configuration registers. Signaling and protocol are loosely based on I2C, limited
to 100 KHz.
Snooping
A means of ensuring cache coherency by monitoring all coherent accesses on a
common multi-drop bus to determine if an access is to information resident within a
cache. The Intel 5000X chipset MCH ensures coherency by initiating snoops on the
processor busses with the address of any line that might appear in a cache on that
bus.
Split Lock Sequence
Split Transaction
A sequence of transactions that occurs when the target of a lock operation is split
across a processor bus data alignment or Cache Line boundary, resulting in two read
transactions and two write transactions to accomplish a read-modify-write operation.
A transaction that consists of distinct Request and Completion phases or packets that
allow use of bus, or interconnect, by other transactions while the Target is servicing
the Request.
SSTL
Stub-Series Terminated Logic
SSTL_2
Symbol
Stub Series Terminated Logic for 2.6 Volts (DDR)
An expanded and encoded representation of a data Byte in an encoded system (for
example, the 10-bit value in a 8-bit/10-bit encoding scheme). This is the value that is
transmitted over the physical medium.
Symbol Time
System Bus
The amount of time required to transmit a symbol.
Processor-to-Intel 5000X chipset interface. The system bus in this document refers to
operation at 266/533/1066 MHz (Bus Clock/Address/Data). The system bus is not
compatible with the P6 system bus.
Target
A device that responds to bus Transactions. The agent receiving a request packet is
referred to as the Target for that Transaction.
Tenured Transaction
TID
A transaction that holds the bus, or interconnect, until complete, effectively blocking
all other transactions while the Target is servicing the Request.
Transaction Identifier: A multi-bit field used to uniquely identify a transaction.
Commonly used to relate a Completion with its originating Request in a Split
Transaction system.
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18
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Introduction
Table 1-1.
General Terminology (Sheet 7 of 7)
Terminology
Description
Transaction, Txn
Transmitter
An overloaded term that represents an operation between two or more agents that
can be comprised of multiple phases, cycles, or packets.
1.
2.
The Agent that sends a Packet across an interface regardless of whether it was
the original generator of the packet.
More narrowly, the circuitry required to drive signals onto the physical medium.
Upstream
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound”
1.2
Related Documents
Document
Document Number/ Location
®
®
Dual-Core Intel Xeon Processor-Based Servers Platform Design
Guide
http://developer.intel.com/design/
®
®
Dual-Core Intel Xeon Processor 5000 Sequence Thermal/Mechanical
Design Guideline
http://developer.intel.com/design/
®
Intel 6402/6400 Advanced Memory Buffer Component External Design http://developer.intel.com/design/
Specification
®
Intel 631xESB/632xESB I/O Controller Hub Datasheet
http://developer.intel.com/design/
http://developer.intel.com/design
®
®
Dual-Core Intel Xeon Processor 5000 Sequence Electrical,
Mechanical, and Thermal Specifications (EMTS).
®
Intel 5000 Series Chipsets MCH BIOS Specification
http://developer.intel.com/design
www.jedec.org
JEDEC FB-DIMM Memory Specification
PCI Local Bus Specification, Rev 2.3.
PCI Express Interface Specification, Rev 1.0a
www.pcisig.org
www.pcisig.org
1.3
Intel® 5000X Chipset Overview
Figure 1-1 shows an example block diagram of an Intel 5000X chipset-based platform.
The Intel 5000X chipset is designed for use in high performance workstations based on
the Dual-Core Intel Xeon Processor 5000 sequence. The Intel 5000X chipset supports
two processors on dual independent point to point system buses operating at 266 MHz
(1066 MTS) or two processors on dual independent point to point system buses
operating at 333 MHz (1333 MTS). The theoretical bandwidth of the two processor
busses is 17 GB/s for Dual-Core Intel Xeon 5000 series and 21GB/s for Dual-Core Intel
Xeon 5100 series.
Intel 5000X chipset features a high performance PCI Express* graphics port capable of
through puts of 4 GB/s. This graphics port contains several architectural enhancements
designed to optimize graphics performance in demanding video applications. One of the
architectural enhancements in Intel 5000X chipset is the inclusion of a Snoop Filter to
eliminate snoop traffic to the graphics port. Reduction of this traffic results in significant
performance increases in graphics intensive applications.
The Dual-Core Intel Xeon 5000 Series has a 2 MB L2 cache, a 266 MHz (1066 MTS)
system bus and Dual-Core Intel Xeon 5100 Series has a 4MB shared L2 cache, a
333MHz (1333 MTS) system bus. They are fabricated using a 65nm process in a
771-pin LGA package.
In a Intel 5000X chipset-based platform, the MCH provides the processor interface,
fully buffered DIMM memory interfaces, PCI Express bus interfaces, ESI interface, and
SM Bus interfaces.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
19
Introduction
The MCH provides four channels of Fully Buffered DIMM (FB-DIMM) memory. Each
channel can support up to 4 Dual Ranked FB-DIMM DDR2 DIMMs. FB-DIMM memory
channels are organized in to two branches for support of RAID 1 (mirroring). The MCH
can support up to 16 DIMMs or a maximum memory size of 64 GB physical memory in
non-mirrored mode and 32 GB physical memory in mirrored configuration. The read
bandwidth for each FB-DIMM channel is 4.25 GB/s for DDR2 533 FB-DIMM memory
which gives a total read bandwidth of 17GB/s for four FB-DIMM channels. Thus this
provides 8.5 GB/s of write memory bandwith for four FB-DIMM channels. The read
bandwidth for each FB-DIMM channel is 5.325 GB/s for DDR2 667FB-DIMM memory
which gives a total read bandwidth of 21.3 GB/s for four FB-DIMM channels. Thus this
provides 10.7GB/s of write memory bandwith for four FB-DIMM channels. The total
bandwidth is based on read bandwidth therefore the total bandwidth is 17 GB/s for 533
and 21.3 GB/s for 667.
The Intel 631xESB/632xESB I/O Controller Hub integrates an Ultra ATA 100 controller,
six Serial ATA host controller ports, one EHCI host controller, and four UHCI host
controllers supporting eight external USB 2.0 ports, LPC interface controller, flash BIOS
interface controller, PCI interface controller, Azalia / AC’97 digital controller, integrated
LAN controller, an ASF controller and a ESI for communication with the MCH. The
Intel 631xESB/632xESB I/O Controller Hub component provides the data buffering and
interface arbitration required to ensure that system interfaces operate efficiently and
provide the bandwidth necessary to enable the system to obtain peak performance.
The Intel 631xESB/632xESB I/O Controller Hub elevates Serial ATA storage
performance to the next level with Intel® RAID.
The ACPI compliant Intel 631xESB/632xESB I/O Controller Hub platform can support
the Full-on, Stop Grant, Suspend to RAM, Suspend to Disk, and Soft-Off power
management states. Through the use of the integrated LAN functions, the Intel
631xESB/632xESB I/O Controller Hub also supports Alert Standard Format for remote
management.
®
20
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Introduction
Figure 1-1. Intel® 5000X Chipset System Block Diagram
P1
P2
1066/1333
MTS System
Bus
1066/1333 MTS System
Bus
F
F
F
B
D
D
R
F
4 PCI-E
X4 4GB/s
B
D
D
R
B
D
D
R
B
D
D
R
Channel0
5.3GB/s
F
F
F
B
D
D
R
F
B
D
D
R
PCI-E X16
Graphics Port
Channel1
GB/s
B
D
D
R
B
D
D
R
5.3
F
F
F
B
D
D
R
Intel®5000X Chipset MCH
F
B
D
D
R
B
D
D
R
Channel2
5.3 GB s
/
B
D
D
R
F
F
SM Buses
Channel3
F
B
D
D
R
F
B
D
D
R
5.3
.
GB/s
B
D
D
R
B
D
D
R
Note: FBD Bandwidth
numbers are for FBD
4.0GHz/667MHz.
Note: All PCI- Express
bandwidth numbers are
bi- directional
PCI-E x4
2 GB/s
PCI-E x4
2GB/s
ESI
2GB/s
Power
Management
8 USB Ports
GPIO
Clock
Generator
PCI-E x4 Bus
Azalia or AC’97
3 codec
support
Intel®631xESB/632 xESB
I/ O Controller Hub
PCI-E x4 Bus
PCI- X 133Bus
PCI32/ 33 Bus
6 SATA Ports
1 PATA Port
Intel®82563EB
SIO
Network Connection
( Dual Port) PHY
Flash BIOS
RJ45
RJ45
§
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
21
Introduction
®
22
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Signal Description
2 Signal Description
This section provides a detailed description of MCH signals. The signals are arranged in
functional groups according to their associated interface. The signals presented in this
section may not be present in all Intel 5000 Series Chipsets. To determine if a signal is
in a particular version, consult Chapter 8. Throughout this section the following
conventions are used:
The terms assertion and deassertion are to avoid confusion when working with a mix of
active-high and active-low signals. The terms assert, or assertion, indicates that the
signal is active, independent of whether the active level is represented by a high or low
voltage. The terms deassert, or deassertion, indicates that the signal is inactive.
Signal names may or may not have a “#” appended to them. The “#” symbol at the
end of a signal name indicates that the active, or asserted state occurs when the signal
is at a low voltage level. When “#” is not present after the signal name, the signal is
asserted when at the high voltage level.
Differential signal pairs adopt a “{P/N}” suffix to indicate the “positive” (P) or
“negative” (N) signal in the pair. If a “#” is appended, it is appended to the positive and
negative signals in a pair.
Typical frequencies of operation for the fastest operating modes are indicated. No
frequency is specified for asynchronous or analog signals.
Some signals or groups of signals have multiple versions. These signal groups may
represent distinct but similar ports or interfaces, or may represent identical copies of
the signal used to reduce loading effects.
Curly-bracketed non-trailing numerical indices, for example, “{X/Y}”, represent
replications of major buses. Square-bracketed numerical indices, for example, “[n:m]”
represent functionally similar but logically distinct bus signals; each signal provides an
independent control, and may or may not be asserted at the same time as the other
signals in the grouping. In contrast, trailing curly-bracketed numerical indices, e.g.,
“{x/y}” typically represent identical duplicates of a signal; such duplicates are provided
for electrical reasons.
The following notations are used to describe the signal type:
I
Input pin
O
Output pin
I/O
Bi-directional Input/Output pin
s/t/s Sustained Tri-state. This pin is driven to its inactive state prior to tri-stating.
The signal description also includes the type of buffer used for the particular signal:
AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The MCH integrates AGTL+ termination resistors, and
supports VTT from 1.15 V to 1.55 V.
LVTTL Low Voltage TTL 3.3 V compatible signals
SSTL_2 Stub Series Terminated Logic 2.6 V compatible signals
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
23
Signal Description
2.6 VGPIO 2.6 V buffers used for miscellaneous GPIO signals
CMOS CMOS buffers
Host Interface signals that perform multiple transfers per clock cycle may be marked as
either “4X” (for signals that are “quad-pumped”) or 2X (for signals that are “double-
pumped”).
Note:
Processor address and data bus signals are logically inverted signals. In other words,
the actual values are inverted of what appears on the processor bus. This must be
taken into account and the addresses and data bus signals must be inverted inside the
MCH host bridge. All processor control signals follow normal convention. A 0 indicates
an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an
active level (high voltage) if the signal has no # suffix.
Table 2-1.
Signal Naming Conventions
Convention
Expands to
RR{0/1/2}XX
Expands to: RR0XX, RR1XX, and RR2XX. This denotes similar signals
on replicated buses.
RR[2:0]
Expands to: RR[2], RR[1], and RR[0]. This denotes a bus.
RR{0/1/2}
Expands to: RR2, RR1, and RR0. This denotes electrical duplicates.
RR# or RR[2:0]# Denotes an active low signal or bus.
Table 2-2 lists the reference terminology used for signal types.
Buffer Signal Types
Table 2-2.
Buffer
Description
Direction
I
Input signal
O
Output signal
A
Analog
I/O
Bidirectional (input/output) signal
®
24
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Signal Description
2.1
Processor Front Side Bus Signals
2.1.1
Processor Front Side Bus 0
Signal Name
Type
I/O
Description
FSB0A[35:3]#
Processor 0 Address Bus: FSB0A[35:3]# connect to the processor address
bus. During processor cycles, FSB0A[35:3]# are inputs. The MCH drives
FSB0A[35:3]# during snoop cycles on behalf of ESI and AGP/Secondary PCI
initiators. FSB0A[35:3]# are transferred at 2X rate. Note that the address is
inverted on the processor bus.
The MCH drives the FSB0A7# signal, which is then sampled by the processor
and the MCH on the active-to-inactive transition of FSB0RESET#. The
minimum setup time for this signal is 4 FSB0CLKs. The minimum hold time is
2 clocks and the maximum hold time is 20 FSB0CLKs.
FSB0ADS#
I/O
I/O
Processor 0 Address Strobe: The processor bus owner asserts FSB0ADS#
to indicate the first of two cycles of a request phase. The MCH can assert this
signal for snoop cycles and interrupt messages.
FSB0ADSTB[1:0]#
Processor 0 Address Strobe: FSB0ADSTB[1:0]# are source synchronous
strobes used to transfer FSB0A[35:3]# and FSB0REQ[4:0]# at the 2X
transfer rate.
StrobeAddress Bits
FSB0ADSTB0#FSB0A[16:3]#, FSB0REQ[4:0]#
FSB0ADSTB1#FSB0A[35:17]#
FSB0AP[1:0]#
FSB0BINIT#
FSB0BNR#
I/O
I/O
I/O
Processor 0 Address Parity: FSB0AP[1:0]# provide parity protection on
the address bus.
Processor 0 Bus Initialization: This signal causes a reset of the bus state
machines.
Processor 0 Block Next Request: This signal is used to block the current
request bus owner from issuing a new request. This signal is used to
dynamically control the processor bus pipeline depth.
FSB0BPM[5:4]
FSB0BPRI#
I/O
O
Breakpoint /Debug Bus: These signals are breakpoint and performance
monitor signals. These are output from the processor to indicate the status
of breakpoints and programmable counters used for monitoring processor
performance.
Processor 0 Priority Agent Bus Request: The MCH is the only Priority
Agent on the processor bus. It asserts this signal to obtain ownership of the
address bus. This signal has priority over symmetric bus requests and cause
the current symmetric owner to stop issuing new transactions unless the
FSB0LOCK# signal was asserted.
FSB0BREQ[1:0]#
I/O
Processor 0 Bus Requests: The MCH pulls the FSB0BREQ0# signal low
during RESET#. The signal is sampled by the processor on the active-to-
inactive transition of FSB0RESET#. The minimum setup time for this signal is
4 FSB0CLKs. The minimum hold time is 2 clocks and the maximum hold time
is 20 FSB0CLKs.
FSB0D[63:0]#
FSB0DBI[3:0]#
I/O
I/O
Processor 0 Data Bus: These signals are connected to the processor data
bus. Data on FSB0D[63:0]# is transferred at a 4X rate. Note that the data
signals may be inverted on the processor bus, depending on the P0DBI[3:0]
signals.
Processor 0 Dynamic Bus Inversion: These signals are driven along with
the FSB0D[63:0]# signals. They indicate if the associated signals are
inverted. FSB0DBI[3:0]# are asserted such that the number of data bits
driven electrically low (low voFSB0ltage) within the corresponding 16-bit
group never exceeds 8.
FSB0DBI[x]#Data Bits
FSB0DBI3#FSB0D[63:48]#
FSB0DBI2#FSB0D[47:32]#
FSB0DBI1#FSB0D[31:16]#
FSB0DBI0#FSB0D[15:0]#
FSB0DBSY#
FSB0DEFER#
I/O
O
Processor 0 Data Bus Busy: This signal is used by the data bus owner to
hold the data bus for transfers requiring more than one cycle.
Processor 0 Data Bus Defer: Defer indicates that the MCH will terminate
the transaction currently being snooped with either a deferred response or
with a retry response.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
25
Signal Description
Signal Name
Type
I/O
Description
FSB0DP[3:0]#
Processor 0 Data Bus Parity: FSB0DP[3:0]# provide parity protection on
the data bus.
FSB0DRDY#
I/O
I/O
Processor 0 Data Ready: This signal is asserted for each cycle that data is
transferred.
FSB0DSTBP[3:0]#
FSB0DSTBN[3:0]#
Processor 0 Differential Host Data Strobes: The differential source
synchronous strobes used to transfer FSB0D[63:0]# and FSB0DBI[3:0]# at
the 4X transfer rate.
StrobeData Bits
FSB0DSTBP3#, FSB0DSTBN3#FSB0D[63:48]#, FSB0DBI3#
FSB0DSTBP2#, FSB0DSTBN2#FSB0D[47:32]#, FSB0DBI2#
FSB0DSTBP1#, FSB0DSTBN1#FSB0D[31:16]#, FSB0DBI1#
FSB0DSTBP0#, FSB0DSTBN0#FSB0D[15:0]#, FSB0DBI0#
FSB0HIT#
I/O
I/O
Processor 0 Cache Hit: This signal indicates that a caching agent holds an
unmodified version of the requested line. FSB0HIT# is also driven in
conjunction with FSB0HITM# by the target to extend the snoop window.
FSB0HITM#
Processor 0 Cache Hit Modified: This signal indicates that a caching agent
holds a modified version of the requested line and that this agent assumes
responsibility for providing the line. FSB0HITM# is also driven in conjunction
with FSB0HIT# to extend the snoop window.
FSB0LOCK#
I/O
Processor 0 Lock: This signal indicates to the system that a transaction
must occur atomically. This signal must connect the appropriate pins of all
processor FSB agents. For a locked sequence of transactions, LOCK# is
asserted from the beginning of the first transaction to the end of the last
transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor FSB, it will wait until it observes LOCK# deasserted. This enables
symmetric agents to retain ownership of the processor FSB throughout the
bus locked operation and ensure the atomicity of lock.
FSB0MCERR#
I/O
I/O
Processor 0 Machine Check Error: Machine check error
FSB0REQ[4:0]#
Processor Bus 0 Request Command: These signals define the attributes
of the request. FSB0REQ[4:0]# are transferred at 2X rate. They are asserted
by the requesting agent during both halves of request phase. In the first half
the signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second half the signals carry additional
information to define the complete transaction type.
FSB0RESET#
O
O
Processor 0 Reset: The FSB0RESET# pin is an output from the MCH. The
MCH asserts FSB0RESET# while RSTIN# (PCIRST# from Intel® 631xESB/
632xESB I/O Controller Hub) is asserted and for approximately 1 ms after
RSTIN# is deasserted. The FSB0RESET# allows the processors to begin
execution in a known state.
FSB0RS[2:0]#
Processor 0 Response Status Signals: These signals indicate the type of
response according to the following:
Encoding Response Type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by MCH)
100 Hard Failure (not driven by MCH)
101 No data response
110 Implicit Writeback
111 Normal data response
FSB0RSP#
O
O
Processor 0 Response Status Parity:
FSB0TRDY#
Processor Bus 0 Target Ready: This signal indicates that the target of the
processor transaction is able to enter the data transfer phase.
FSB0VREF
Analog
Processor 0 Voltage Reference: Processor 0 voltage reference.
®
26
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Signal Description
2.1.2
Processor Front Side Bus 1
Signal Name
Type
I/O
Description
FSB1A[35:3]#
Processor 1 Address Bus: FSB1A[35:3]# connect to the processor address
bus. During processor cycles, FSB1A[35:3]# are inputs. The MCH drives
FSB1A[35:3]# during snoop cycles on behalf of ESI and AGP/Secondary PCI
initiators. FSB1A[35:3]# are transferred at 2X rate. Note that the address is
inverted on the processor bus.
Note: The MCH drives the FSB1A7# signal, which is then sampled by the
processor and the MCH on the active-to-inactive transition of
FSB1RESET#. The minimum setup time for this signal is 4
FSB0CLKs. The minimum hold time is 2 clocks and the maximum
hold time is 20 FSB1CLKs.
FSB1ADS#
I/O
I/O
Processor 1 Address Strobe: The processor bus owner asserts FSB1ADS#
to indicate the first of two cycles of a request phase. The MCH can assert this
signal for snoop cycles and interrupt messages.
FSB1ADSTB[1:0]#
Processor 1 Address Strobe: FSB1ADSTB[1:0]# are source synchronous
strobes used to transfer FSB1A[35:3]# and FSB1REQ[4:0]# at the 2X
transfer rate.
StrobeAddress Bits
FSB1ADSTB0#FSB1A[16:3]#, FSB1REQ[4:0]#
FSB1ADSTB1#FSB1A[35:17]#
FSB1AP[1:0]#
FSB1BINIT#
FSB1BNR#
I/O
I/O
I/O
Processor 1 Address Parity: FSB0AP[1:0]# provide parity protection on
the address bus
Processor 1 Bus Initialization: This signal causes a reset of the bus state
machines.
Processor 1 Block Next Request: This signal is used to block the current
request bus owner from issuing a new request. This signal is used to
dynamically control the processor bus pipeline depth.
FSB1BPM[5:4]
FSB1BPRI#
I/O
O
Breakpoint /Debug Bus: These signals are breakpoint and performance
monitor signals. These are output from the processor to indicate the status
of breakpoints and programmable counters used for monitoring processor
performance.
Processor 1 Priority Agent Bus Request: The MCH is the only Priority
Agent on the processor bus. It asserts this signal to obtain ownership of the
address bus. This signal has priority over symmetric bus requests and cause
the current symmetric owner to stop issuing new transactions unless the
FSB1LOCK# signal was asserted.
FSB1BREQ[1:0]#
I/O
Processor 1 Bus Requests: The MCH pulls the FSB1BREQ1# &
FSB1BREQ0# signals low during RESET#. The signal is sampled by the
processor on the active-to-inactive transition of FSB1RESET#. The minimum
setup time for this signal is 4 FSB1CLKs. The minimum hold time is 2 clocks
and the maximum hold time is 20 FSB1CLKs.
FSB1D[63:0]#
FSB1DBI[3:0]#
I/O
I/O
Processor 1 Data Bus: These signals are connected to the processor data
bus. Data on FSB1D[63:0]# is transferred at a 4X rate. Note that the data
signals may be inverted on the processor bus, depending on the
FSB1DBI[3:0] signals.
Processor 1 Dynamic Bus Inversion: These signals are driven along with
the FSB1D[63:0]# signals. They indicate if the associated signals are
inverted. FSB1DBI[3:0]# are asserted such that the number of data bits
driven electrically low (low voltage) within the corresponding 16-bit group
never exceeds 8.
FSB1DBI[x]#Data Bits
FSB1DBI3#FSB1D[63:48]#
FSB1DBI2#FSB1D[47:32]#
FSB1DBI1#FSB1D[31:16]#
FSB1DBI0#FSB1D[15:0]#
FSB1DBSY#
FSB1DEFER#
I/O
O
Processor 1 Data Bus Busy: This signal is used by the data bus owner to
hold the data bus for transfers requiring more than one cycle.
Processor 1 Data Bus Defer: Defer indicates that the MCH will terminate
the transaction currently being snooped with either a deferred response or
with a retry response.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
27
Signal Description
Signal Name
Type
I/O
Description
FSB1DP[3:0]#
Processor 1 Data Bus Parity: FSB1DP[3:0]# provide parity protection on
the data bus.
FSB1DRDY#
I/O
I/O
Processor 1 Data Ready: This signal is asserted for each cycle that data is
transferred.
FSB1DSTBP[3:0]#
FSB1DSTBN[3:0]#
Processor 1 Differential Host Data Strobes: The differential source
synchronous strobes used to transfer FSB1D[63:0]# and FSB1DBI[3:0]# at
the 4X transfer rate.
StrobeData Bits
FSB1DSTBP3#, FSB10DSTBN3#FSB1D[63:48]#, FSB1DBI3#
FSB1DSTBP2#, FSB1DSTBN2#FSB1D[47:32]#, FSB1DBI2#
FSB1DSTBP1#, FSB1DSTBN1#FSB1D[31:16]#, FSB1DBI1#
FSB1DSTBP0#, FSB1DSTBN0#FSB1D[15:0]#, FSB1DBI0#
FSB1HIT#
I/O
I/O
Processor 1 Cache Hit: This signal indicates that a caching agent holds an
unmodified version of the requested line. FSB1HIT# is also driven in
conjunction with FSB1HITM# by the target to extend the snoop window.
FSB1HITM#
Processor 1 Cache Hit Modified: This signal indicates that a caching agent
holds a modified version of the requested line and that this agent assumes
responsibility for providing the line. FSB1HITM# is also driven in conjunction
with FSB1HIT# to extend the snoop window.
FSB1LOCK#
I/O
Processor 1 Lock: This signal indicates to the system that a transaction
must occur atomically. This signal must connect the appropriate pins of all
processor FSB agents. For a locked sequence of transactions, LOCK# is
asserted from the beginning of the first transaction to the end of the last
transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor FSB, it will wait until it observes LOCK# deasserted. This enables
symmetric agents to retain ownership of the processor FSB throughout the
bus locked operation and ensure the atomicity of lock.
FSB1MCERR#
I/O
I/O
Processor 1 Machine Check Error: Machine check error
FSB1REQ[4:0]#
Processor Bus 1 Request Command: These signals define the attributes
of the request. FSB1REQ[4:0]# are transferred at 2X rate. They are asserted
by the requesting agent during both halves of request phase. In the first half
the signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second half the signals carry additional
information to define the complete transaction type.
FSB1RESET#
O
O
Processor 1 Reset: The FSB1RESET# pin is an output from the MCH. The
MCH asserts FSB1RESET# while RSTIN# (PCIRST# from Intel® 631xESB/
632xESB I/O Controller Hub) is asserted and for approximately 1 ms after
RSTIN# is deasserted. The FSB1RESET# allows the processors to begin
execution in a known state.
FSB1RS[2:0]#
Processor 1 Response Status Signals: These signals indicates type of
response according to the following:
EncodingResponse Type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by MCH)
100 Hard Failure (not driven by MCH)
101 No data response
110 Implicit Writeback
111 Normal data response
FSB1RSP#
O
O
Processor 1 Response Status Parity:
FSB1TRDY#
Processor Bus 1 Target Ready: This signal indicates that the target of the
processor transaction is able to enter the data transfer phase.
FSB1VREF
Analog
Processor 1 Voltage Reference: Processor 1 voltage reference.
®
28
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Signal Description
2.2
Fully Buffered DIMM Memory Channels
The following reference and compensation signals are common to all Fully Buffered
DIMM (FB-DIMM) channels.
Signal Name
Type
Description
FBDBGBIASEXT
FBDICOMPBIAS
FBDRESIN
Analog
Analog
Analog
FB-DIMM Bypass Bias Input for Band Gap Circuit:
FB-DIMM Transmitter Swing Bias:
FB-DIMM On-die Impedance Compensation:
2.2.1
FB-DIMM Branch 0
FB-DIMM branch 0 contains FB-DIMM channels 0 and 1. The following signals are
common to both FB-DIMM channels.
Signal Name
Type
Description
FBD01CLKN
FBD01CLKP
FBD01VCCA
FBD01VSSA
Analog
Analog
Analog
Analog
FB-DIMM Clock Negative: Core Clock Negative Phase
FB-DIMM Clock Positive: Core Clock Positive Phase
FB-DIMM VCC: Analog Voltage for the PLL
FB-DIMM VSS: Analog Voltage for PLL
2.2.1.1
FB-DIMM Channel 0
Signal Name
Type
Description
FBD0NBIN[13:0]
I
FB-DIMM Channel 0 Northbound Input Data Negative Phase: NOTE:
FBD0NBIN[13] is not an active signal carrying signal but must be
connected to properly terminate the FB DIMM component.
FBD0NBIP[13:0]
I
FB-DIMM Channel 0 Northbound Input Data Positive Phase: NOTE:
FBD0NBIP[13] is not an active signal carrying signal but must be
connected to properly terminate the FB DIMM component.
FBD0SBON[9:0]
FBD0SBOP[9:0]
O
O
FB-DIMM Channel 0 Southbound Output Negative Phase:
FB-DIMM Channel 0 Southbound Output Positive Phase:
2.2.1.2
FB-DIMM Channel 1
Signal Name
Type
Description
FBD1NBIN[13:0]
I
FB-DIMM Channel 1 Northbound Input Data Negative Phase: NOTE:
FBD1NBIN[13] is not an active signal carrying signal but must be
connected to properly terminate the FB DIMM component.
FBD1NBIP[13:0]
I
FB-DIMM Channel 1 Northbound Input Data Positive Phase: NOTE:
FBD1NBIP[13] is not an active signal carrying signal but must be
connected to properly terminate the FB DIMM component.
FBD1SBON[9:0]
FBD1SBOP[9:0]
O
O
FB-DIMM Channel 1 Southbound Output Negative Phase:
FB-DIMM Channel 1 Southbound Output Positive Phase:
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
29
Signal Description
2.2.2
2.2.2.1
2.2.2.2
FB-DIMM Branch 1
FB-DIMM branch 1 contains FB-DIMM channels 2 and 3. The following signals are
common to both FB-DIMM channels.
Signal Name
Type
Description
FBD23CLKN
FBD23CLKP
FBD23VCCA
FBD23VSSA
Analog
Analog
Analog
Analog
FB-DIMM Clock Negative: Core Clock Negative Phase
FB-DIMM Clock Positive: Core Clock Positive Phase
FB-DIMM VCC: Analog Voltage for the PLL
FB-DIMM VSS: Analog Voltage for PLL
FB-DIMM Channel 2
Signal Name
Type
Description
FBD2NBIN[13:0]
I
FB-DIMM Channel 2 Northbound Input Data Negative Phase: NOTE:
FBD2NBIN[13] is not an active signal carrying signal but must be
connected to properly terminate the FB DIMM component.
FBD2NBIP[13:0]
I
FB-DIMM Channel 2 Northbound Input Data Positive Phase: NOTE:
FBD2NBIP[13] is not an active signal carrying signal but must be
connected to properly terminate the FB DIMM component.
FBD2SBON[9:0]
FBD2SBOP[9:0]
O
O
FB-DIMM Channel 2 Southbound Output Negative Phase:
FB-DIMM Channel 2 Southbound Output Positive Phase:
FB-DIMM Channel 3
Signal Name
Type
Description
FBD3NBIN[13:0]
I
FB-DIMM Channel 3 Northbound Input Data Negative Phase: NOTE:
FBD3NBIN[13] is not an active signal carrying signal but must be
connected to properly terminate the FB DIMM component.
FBD3NBIP[13:0]
I
FB-DIMM Channel 3 Northbound Input Data Positive Phase: NOTE:
FBD3NBIP[13] is not an active signal carrying signal but must be
connected to properly terminate the FB DIMM component.
FBD3SBON[9:0]
FBD3SBOP[9:0]
O
O
FB-DIMM Channel 3 Southbound Output Negative Phase:
FB-DIMM Channel 3 Southbound Output Positive Phase:
2.3
PCI Express* Signal List
2.3.1
PCI Express* Common Signals
Signal Name
Type
Description
PECLKN
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
PCI Express* Common Clock Negative Phase:
PCI Express Common Clock Positive Phase:
PCI Express Impedance Compensation:
PECLKP
PEICOMPI
PEICOMPO
PEVCCA
PCI Express Impedance Compensation:
PCI Express VCC: Analog Voltage for the PCI Express PLL:
PCI Express Band Gap VCC: Band Gap Voltage
PCI Express VSS: Analog Voltage for PCI Express PLL:
PCI Express Band Gap VSS: Band Gap Voltage
PEVCCBG
PEVSSA
PEVSSBG
PEWIDTH[3:0]
Power/Other PCI Express Port Width Strapping Pins:
®
30
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Signal Description
2.3.2
PCI Express Port 0, Enterprise South Bridge Interface
(ESI)
PCI Express port 0 is a x4 port dedicated to providing the ESI link between the Intel
5000X chipset MCH and the Intel 631xESB/632xESB I/O Controller Hub.
Signal Name
Type
Description Reference
PE0RP[3:0]
PE0RN[3:0]
PE0TP[3:0]
PE0TN[3:0]
I
I
PCI Express Port 0 (ESI) Positive Phase Inbound: (Receive) Signals
PCI Express Port 0 (ESI) Negative Phase Inbound: (Receive) Signals
PCI Express Port 0 (ESI) Positive Phase Outbound: (Transmit) Signals
PCI Express Port 0 (ESI) Negative Phase Outbound: (Transmit) Signals
O
O
2.3.3
PCI Express Port 2
PCI Express port 2 is a x4 port. PCI Express port 2 is combinable with PCI Express port
3 to form a single PCI Express x8 port. Normally port 2 and port 3 are used to increase
the bandwidth between the Intel 5000X chipset MCH and the Intel 631xESB/632xESB
I/O Controller Hub.
Signal Name
Type
Description
PE2RP[3:0]
PE2RN[3:0]
PE2TP[3:0]
PE2TN[3:0]
I
I
PCI Express Port 2 Positive Phase Inbound: (Receive) Signals
PCI Express Port 2 Negative Phase Inbound: (Receive) Signals
PCI Express Port 2 Positive Phase Outbound: (Transmit) Signals
PCI Express Port 2 Negative Phase Outbound: (Transmit) Signals
O
O
2.3.4
PCI Express Port 3
PCI Express port 3 is combinable with PCI Express port 2 to form a single PCI Express
x8 port. Normally port 2 and port 3 are used to increase the bandwidth between the
Intel 5000X chipset MCH and the Intel 631xESB/632xESB I/O Controller Hub.
Signal Name
Type
Description
PE3RP[3:0]
PE3RN[3:0]
PE3TP[3:0]
PE3TN[3:0]
I
I
PCI Express Port 3 Positive Phase: Inbound (Receive) Signals
PCI Express Port 3 Negative Phase: Inbound (Receive) Signals
PCI Express Port 3 Positive Phase: Outbound (Transmit) Signals
PCI Express Port 3 Negative Phase: Outbound (Transmit) Signals
O
O
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
31
Signal Description
2.3.5
PCI Express* Graphics Port
In the Intel 5000X chipset MCH PCI Express ports 4, 5, 6, and 7 are combined to form
a single high performance x16 graphics port.
Signal Name
Type
Description
PE4RP[3:0]
PE4RN[3:0]
PE4TP[3:0]
PE4TN[3:0]
PE5RP[3:0]
PE5RN[3:0]
PE5TP[3:0]
PE5TN[3:0]
PE6RP[3:0]
PE6RN[3:0]
PE6TP[3:0]
PE6TN[3:0]
PE7RP[3:0]
PE7RN[3:0]
PE7TP[3:0]
PE7TN[3:0]
I
I
PCI Express* Graphics Port First x4, Positive Phase Inbound (Receive) Signals:
PCI Express Graphics Port First x4, Negative Phase Inbound (Receive) Signals:
PCI Express Graphics Port First x4, Positive Phase Outbound (Transmit) Signals:
PCI Express Graphics Port First x4, Negative Phase Outbound (Transmit) Signals:
PCI Express Graphics Port Second x4, Positive Phase Inbound (Receive) Signals:
PCI Express Graphics Port Second x4, Negative Phase Inbound (Receive) Signals:
PCI Express Graphics Port Second x4, Positive Phase Outbound (Transmit) Signals:
PCI Express Graphics Port Second x4, Negative Phase Outbound (Transmit) Signals:
PCI Express Graphics Port Third x4, Positive Phase Inbound (Receive) Signals:
PCI Express Graphics Port Third x4, Negative Phase Inbound (Receive) Signals:
PCI Express Graphics Port Third x4, Positive Phase Outbound (Transmit) Signals:
PCI Express Graphics Port Third x4, Negative Phase Outbound (Transmit) Signals:
PCI Express Graphics Port Fourth x4, Positive Phase Inbound (Receive) Signals:
PCI Express Graphics Port Fourth x4, Negative Phase Inbound (Receive) Signals:
PCI Express Graphics Port Fourth x4, Positive Phase Outbound (Transmit) Signals:
PCI Express Graphics Port Fourth x4, Negative Phase Outbound (Transmit) Signals:
O
O
I
I
O
O
I
I
O
O
I
I
O
O
®
32
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Signal Description
2.4
System Management Bus Interfaces
There are seven SM Bus interfaces dedicated to specific functions. These functions are:
• System Management
• Four buses dedicated to FB-DIMM serial presents detect, one for each channel
• PCI hot-plug
Signal Name
Type
Description
CFGSMBCLK
CFGSMBDATA
GPIOSMBCLK
GPIOSMBDATA
SPD0SMBCLK
I/O
I/O
I/O
I/O
I/O
Slave SMB Clock: System Management Bus Clock
Slave SMB Data: SMB Address/Data
PCI SMB Clock: PCI Hot-Plug Master VPI, System Management Bus Clock
PCI SMB Data: PCI Hot-Plug Master VPI, SMB Address/Data
FB-DIMM Channel 0 SMB Clock: FB-DIMM Memory Serial Presents Detect 0,
System Management Bus Clock
SPD0SMBDATA
SPD1SMBCLK
SPD1SMBDATA
SPD2SMBCLK
SPD2SMBDATA
SPD3SMBCLK
SPD3SMBDATA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FB-DIMM Channel 0 SMB Data: FB-DIMM Memory Serial Presents Detect 0,
SMB Address/Data
FB-DIMM Channel 1 SMB Clock: FB-DIMM Memory Serial Presents Detect 1,
System Management Bus Clock
FB-DIMM Channel 1 SMB Data: FB-DIMM Memory Serial Presents Detect 1,
SMB Address/Data
FB-DIMM Channel 2 SMB Clock: FB-DIMM Memory Serial Presents Detect 2,
System Management Bus Clock
FB-DIMM Channel 2 SMB Data: FB-DIMM Memory Serial Presents Detect 2,
SMB Address/Data
FB-DIMM Channel 3 SMB Clock: FB-DIMM Memory Serial Presents Detect 3,
System Management Bus Clock
FB-DIMM Channel 3 SMB Data: FB-DIMM Memory Serial Presents Detect 3,
SMB Address/Data
2.5
XD Port Signal List
Signal Name
Type
Description
XDPCOMCRES
XDPD[15:0]#
Analog
I/O
XDP Bus Compensation:
Data Bus:.
XDPSTBN#
XDPSTBP#
I/O
Data Bus Strobe Negative and Positive Phases:
XDPODTCRES
XDPRDY#
Analog
I/O
XDP Bus Compensation:
Data Bus Ready:
XDPSLWCRES
Analog
XDP Bus Slew Rate Compensation:.
2.6
JTAG Bus Signal List
Signal Name
Type
Description
TCK
I
I
Clock: Clock pin of the JTAG.
TDI
Data Input: Serial chain input of the JTAG.
Data Output: Serial chain output of the JTAG.
State Machine: JTAG State machine control
Reset: Asynchronous reset of the JTAG.
TDO
TMS
O
I
TRST#
I
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
33
Signal Description
2.7
Clocks, Reset and Miscellaneous
Signal Name
Type
Description
CORECLKN
Analog
Differential Processor Core Clock Negative Phase: These pins receive a
low-voltage differential host clock from the external clock synthesizer. This
clock is used by all of the MCH logic that is in the Host clock domain.
CORECLKP
Analog
Differential Processor Core Clock Positive Phase: These pins receive a
low-voltage differential host clock from the external clock synthesizer. This
clock is used by all of the MCH logic that is in the Host clock domain.
COREVCCA
COREVSSA
ERR[2:0]#
Analog
Analog
O
Core VCC: Analog Voltage for the PLL
Core VSS: Analog Voltage for PLL
Error Output: Error output signal:
ERR[0] = Correctable and recoverable error from the memory subsystem
ERR[1] = Uncorrectable error from the Intel 5000X chipset MCH
ERR[2] = Fatal error from the Intel 5000X chipset MCH
FSBCRES
Analog
Analog
Analog
Processor Bus Compensation:
ODTCRES
Processor Bus Compensation:
FSBSLWCRES
FSBSLWCTRL
FSBVCCA
Processor Bus Slew Rate Compensation:
Power/Other Processor Bus Slew Rate Control:
Analog
I
FSB VCC: Analog Voltage for the FB-DIMM channel PLL
PWRGOOD
Power OK: When asserted, this signal indicates that all power supplies are
in specification.
PSEL[2:0]
RESETI#
I
I
Processor Speed Select:
MCH Reset: This is the hard reset
RSVD
No Connect Reserved Pin:
TDIOANODE
TDIOCATHODE
TESTHI
Analog
Analog
Power
Thermal Diode Anode: This is the anode of the thermal diode
Thermal Diode Cathode: This is the cathode of the thermal diode
1.5 Volt Pullup:
TESTHI_V3REF
VSSQUIET
VSSSEN
Power/Other 3.3 Volt Pullup:
Analog
Analog
Analog
Quiet VSS: Quiet VSS for ODDD
Quiet VSS: Quiet VSS for Thermal Sensor
Quiet VCC: Quiet VCC for Thermal Sensor
VCCSEN
2.8
Power and Ground Signals
Signal Name
Description
V3REF
VCC
SMB VCC: Common 3.3 for SMB buses
VCC Supply: This is the 1.5 V core voltage.
VCCSF
VCC Snoop Filter Supply: This is the 1.5 V core voltage on a separate plane for the snoop
filter.
VSS
Ground Return: Common return for power supplies
VTT Supply: VTT is a 1.2 V FSB supply
VTT
VCCFBD
VCCPE
VCC for System Memory: VCCFBD is 1.8 V for DDR2 power.
VCC for PCI Express ports.
2.9
MCH Sequencing Requirements
Power Plane and Sequencing Requirements:
• Clock Valid Timing:
®
34
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Signal Description
• BUSCLK must be valid at least 2ms prior to rising edge of PWRGOOD.
Figure 2-1. Intel 5000X Chipset Clock and Reset Requirements
~100ms
Power Rails
2ms
PWRGOOD
1ms
RESET#
BUSCLK
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
35
Signal Description
2.10
Reset Requirements
2.10.1
Timing Diagrams
2.10.1.1
Power-Up
The power-up sequence is illustrated in Figure 2-2.
Figure 2-2. Power-Up
Power Rails
PWRGOOD
T1
T9
T10
RESETI#
T11
Synchronized RESETI#
processor RESET#
POC
T13
T8
T7
T14
T15
Non-FBD Analog
compensation
completed
Straps
sampled
Straps
inactive downloaded
Fuses
Array Init
Done
T17
DMI handshake done
Events
FBD
Internal power detect
Reset
Init
Level
T12
initialization
PCI-Express
PCI-Express Compatibility
full operation
BUSCLK
PLL's
2.10.1.2
Power Good
The PWRGOOD reset sequence is illustrated in Figure 2-3.
Figure 2-3. PWRGOOD
T3
T9
PWRGOOD
RESETI#
T10
T11
Synchronized RESETI#
processor RESET#
POC
T13
T8
T7
T14
T15
Straps
active
Straps
sampled
Straps
inactive downloaded
Fuses
Array Init
Done
T2
T17
DMI handshake done
Events
Reset
Init
Level
FBD
PCI-
T12
initialization
full operation
Express
PCI-Express Compatibility
BUSCLK
PLL's
Sticky Bits
2.10.1.3
Hard Reset
The Hard Reset sequence is illustrated in Figure 2-4.
®
36
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Signal Description
Figure 2-4. Hard Reset
T6
ICHRST#
RESETI#
T9
T11
Synchronized RESETI#
processor RESET#
POC
T10
T13
T4
T14
T15
INITIN#
Array Init
Done
T17
DMI handshake done
Events
Reset
Init
Level
FBD
PCI-
T12
initialization
full operation
Express
PCI-Express Compatibility
BUSCLK
PLL's
Sticky Bit Enable
SYRE.SAVCFG
2.10.1.4
RESETI# Retriggering Limitations
Figure 2-5 shows the timing for a RESETI# retrigger.
Figure 2-5. RESETI# Retriggering Limitations
T16
T9
T5
RESETI#
Incomplete
Initialization
Complete Initialization
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
37
Signal Description
2.10.2
Reset Timing Requirements
Table 2-3 specifies the timings drawn in Figure 2-2, Figure 2-3, Figure 2-4, and
Figure 2-5. Nominal clock frequencies are described. Specifications still hold for derated
clock frequencies.
Table 2-3.
Power Up and Hard Reset Timings
Timing
Description
Min
Max
Comments
Power and master clocks stable to
PWRGOOD signal assertion
T1
T2
2ms
3GIO PLL specification
PWRGOOD de-assertion to straps active
40ns
Minimum PWRGOOD de-assertion
time while power and platform
clocks are stable.
T3
PWRGOOD de-assertion
80ns
T4
T5
POC after RESET# assertion delay
1 BUSCLK
Platform reset de-assertion to platform
reset assertion
Minimum re-trigger time on
RESETI# de-assertion.
50 BUSCLK’s
POC turn-on delay after strap
disable
T7
T8
T9
PWRGOOD assertion to POC active
2 BUSCLK’s
12ns
PWRGOOD assertion to straps inactive
18ns
Strap Hold Time
RESETI# signal assertion during PWRGOOD
/ PWROK signal assertion
This delay can be provided by the
ICH6 or by system logic
1ms
RESET# assertion during processor
PWRGOOD assertion
T10
T11
T12
1ms
10ms
Processor EMTS specification.
Note: This is a special Dual-Core
Intel Xeon 5100 series requirement
to have a longer POC assertion
setup time on the FSB and the
Intel® 5000P chipset has added a
fix in B0 RTL to increase this time
period from 160us to 480us.
RESETI# signal de-assertion to processor
RESET# signal de-assertion
1
480us
RESETI# signal de-assertion to completion
of PCI-Express initialization sequence
1,250,000
PECLK’s
PCI-Express clock is 100MHz
T13
T14
Array Initialization duration
200 cycles
POC hold time after RESET# de-assertion
2 BUSCLK’s
19 BUSCLK’s
Processor EMTS specification
ICH6 specification
Initiation of DMI reset sequence to
processor RESET# signal de-assertion
10,000 PECLK’s
+ T17
T15
T16
T17
RESETI# re-trigger delay
T5 + T9
CPU_RESET_DONE capture timer
2,000 BUSCLK’s
Notes:
®
1. In the Intel 5000P chipset B0 RTL, the T11 duration is implemented through a counter with max value of 162,000 core clocks.
For 333 Mhz, this gives a period of 486 us for the POC setup time while @266 Mhz, the period is 607.5 us.
®
38
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Signal Description
Table 2-4 summarizes the Product Name Initialization timings.
Critical Intel® 5000P Initialization Timings
Table 2-4.
Covered by
Timing
Sequence
Started by
Maximum Length
parameter
®
Intel 5000P chipset Core,
FSB, FB-DIMM PLL lock
Stable power and master clock
666,667 333 MHz cycles
200,000 100 MHz cycles
200 cycles
T
1
Intel® 5000P MCH PCI Express Stable power and master clock
PLL lock
Array initialization
Synchronized RESETI#
Deassertion
T
T
17
Fuse download
PWRGOOD Assertion
333,333 333 MHz cycles
9
2.10.3
Miscellaneous Requirements and Limitations
• Power rails and stable BUSCLK, FBD{0/1}CLK, and PECLK master clocks remain
within specifications through all but power-up reset.
• Frequencies (for example, 266 MHz) described in this chapter are nominal. The
Intel® 5000P chipset MCH reset sequences must work for the frequency of
operation range specified in the Clocking chapter.
• Hard Reset can be initiated by code running on a processor, JTAG, SMBus, or PCI
agents.
• Hard Reset is not guaranteed to correct all illegal configurations or malfunctions.
Software can configure sticky bits in the Intel 5000P chipset MCH to disable
interfaces that will not be accessible after Hard Reset. Signaling errors or protocol
violations prior to reset (from processor bus, FB-DIMM, or PCI Express) may hang
interfaces that are not cleared by Hard Reset.
• System activity is initiated by a request from a processor bus. No I/O devices will
initiate requests until configured by a processor to do so.
• The FB-DIMM channels will be enabled for packet levelization (Intel 5000P
MCH.FBDST.STATE=“Ready” or “RecoveryReady” state) upon completion of a hard
reset. Software should inspect the Intel 5000P chipset MCH.FBDST.STATE
configuration bits to determine which FB-DIMM channels are available.
• The default values of the POC configuration register bits do not require any
processor request signals to be asserted when PWRGOOD is first asserted.
Software sets these configuration registers to define these values, then initiates a
hard reset that causes them to be driven during processor RESET# signal
assertion.
• Cleanly aborting an in-progress SPD command during a PWRGOOD deassertion is
problematic. No guarantee can be issued as to the final state of the EEPROM in this
situation. The Intel® 5000P MCH cannot meet the SPD data tSU,STO timing
specification. Since the Intel® 5000P MCH floats the data output into a pull-up on
the platform, a read will not degrade to a write. However, if the PWRGOOD
deassertion occurs after the EEPROM has received the write bit, the data will be
corrupted. The platform pull-up must be strong enough to complete a low-to-high
transition on the clock signal within tR = 1 microsecond (ATMEL AT24C01 timing
specification) after deassertion of PWRGOOD to prevent clock glitches. Within these
constraints, an in-progress write address will not be corrupted.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
39
Signal Description
2.11
Intel® 5000P Chipset Platform Signal Routing
Topology Diagrams
Figure 2-6. Simplest Power Good Distribution
Intel® 5000P
chipset
Processors
PWRGOOD
PWRGOOD
Other Resets
SYS_ RESET
Intel® 631xESB/
632xESB I/O
Controller Hub
Power Good
Logic
Figure 2-7. Basic System Reset Distribution
Processor
Processor
RESET#
RESET#
RESET#'s
RESETI#
Intel® 5000P
chipset
PLTRST#
Intel
Figure 2-8. Basic INIT# Distribution
Processor
Processor
INIT#
INIT#
Intel® 631xESB/
632xESB I/O Controller
Hub
®
40
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Signal Description
®
2.11.1
Intel 5000P Customer Reference Platform (SRP) Reset
Topology
Typical platform level reset implementation is described in the Dual-Core Intel® Xeon®
Processor 5000 series (1066 MHz) and Intel® 5000 Sequence Chipsets Platform Design
Guide (PDG).
2.12
Signals Used as Straps
2.12.1
Functional Straps
The PEWIDTH signals are used to determine the widths of the 7 PCI Express ports.
Signal Name
Type
Description
PEWIDTH[3:0]
Power/
Other
PCI Express Port Width Strapping Pins:
§
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
41
Signal Description
®
42
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3 Register Description
The Intel 5000X chipset MCH contains three sets of software accessible registers,
accessed via the host processor I/O address space:
• Control registers I/O mapped into the processor I/O space that controls access to
PCI and AGP configuration spaces.
• Internal configuration registers residing within the MCH are partitioned into logical
device register sets (“logical” since they reside within a single physical device). The
first register set is dedicated to MCH functionality (controls PCI bus 0, that is,
DRAM configuration, other chipset operating parameters, and optional features).
The second register block is dedicated to host-AGP bridge functions (controls AGP
interface configurations and operating parameters). The third register set is
dedicated to ESI control.
The MCH supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism 1 in the PCI specification as defined in the PCI Local Bus
Specification, Revision 2.3. All the registers are organized by bus, device, function, and
so forth, as defined in the PCI Express Base Specification, Revision 1.0a. The MCH
supports registers in PCI Express extended space. All MCH registers in the Intel 5000X
chipset appear on PCI Bus #0.
In addition, the MCH registers can be accessed by a memory mapped register access
mechanism (as MMIO), a PCI configuration access mechanism (only PCI space
registers), and register access mechanisms through JTAG and SMBus. The memory
mapped access mechanism is further broken down into different ranges. The internal
registers of this chip set can be accessed in 8-bit, 16-bit, or 32-bit quantities, with the
exception of CFGADR which can only be accessed as a 32-bit. All multi-byte numeric
fields use “little-endian” ordering (that is, lower addresses contain the least significant
parts of the field).
In addition, the MCH can forward accesses to all PCI/PCI Express configuration
registers south of the MCH through the same mechanisms.
3.1
Register Terminology
Registers and register bits are assigned one or more of the following attributes. These
attributes define the behavior of register and the bit(s) that are contained with in. All
bits are set to default values by hard reset. Sticky bits retain their states between hard
resets.
i
Term
Description
RO
Read Only. If a register bit is read only, the hardware sets its state. The bit may be read
by software. Writes to this bit have no effect.
WO
Write Only. The register bit is not implemented as a bit. The write causes some
hardware event to take place.
RW
RC
Read/Write. A register bit with this attribute can be read and written by software.
Read Clear: The bit or bits can be read by software, but the act of reading causes the
value to be cleared.
RCW
Read Clear/Write: A register bit with this attribute, will get cleared after the read. The
register bit can be written.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
43
Register Description
Term
Description
RWC
RWS
Read/Write Clear. A register bit with this attribute, can be read or cleared by software.
In order to clear this bit, a one must be written to it. Writing a zero will have no effect.
Read/Write/Set: A register bit can be either read or set by software. In order to set
this bit, a one must be written to it. Writing a zero to this bit has no effect. Hardware will
clear this bit.
RWL
Read/Write/Lock. A register bit with this attribute can be read or written by software.
Hardware or a configuration bit can lock bit and prevent it from updated.
RWO
Read/Write Once. A register bit with this attribute can be written to only once after
power up. After the first write, the bit becomes read only. This attribute is applied on a bit
by bit basis. For example, if the RWO attribute is applied to a 2 bit field, and only one bit
is written, then the written bit cannot be rewritten (unless reset). The unwritten bit, of
the field, may still be written once. This is special case of RWL.
RRW
Read/Restricted Write. This bit can be read and written by software. However, only
supported values will be written. Writes of non supported values will have no effect.
L
Lock. A register bit with this attribute becomes Read Only after a lock bit is set.
RV
Reserved Bit. This bit is reserved for future expansion and must not be written. The PCI
Local Bus Specification, Revision 2.2 requires that reserved bits must be preserved. Any
software that modifies a register that contains a reserved bit is responsible for reading
the register, modifying the desired bits, and writing back the result.
Reserved Bits
Some of the MCH registers described in this section contain reserved bits. These bits are
labeled “Reserved”. Software must deal correctly with fields that are reserved. On reads,
software must use appropriate masks to extract the defined bits and not rely on reserved
bits being any particular value. On writes, software must ensure that the values of
reserved bit positions are preserved. That is, the values of reserved bit positions must
first be read, merged with the new values for other bit positions and then written back.
Note that software does not need to perform a read-merge-write operation for the
Configuration Address (CONFIG_ADDRESS) register.
Reserved
Registers
In addition to reserved bits within a register, the MCH contains address locations in the
configuration space of the Host-ESI bridge entity that are marked either “Reserved” or
“Intel Reserved”. The MCH responds to accesses to “Reserved” address locations by
completing the host cycle. When a “Reserved” register location is read, a zero value is
returned. (“Reserved” registers can be 8, 16, or 32 bits in size). Writes to “Reserved”
registers have no effect on the MCH. Registers that are marked as “Intel Reserved” must
not be modified by system software. Writes to “Intel Reserved” registers may cause
system failure. Reads to “Intel Reserved” registers may return a non-zero value.
Default Value
upon a Reset
Upon a reset, the MCH sets all of its internal configuration registers to predetermined
default states. Some register values at reset are determined by external strapping
options. The default state represents the minimum functionality feature set required to
successfully bring up the system. Hence, it does not represent the optimal system
configuration. It is the responsibility of the system initialization software (usually BIOS)
to properly determine the DRAM configurations, operating parameters and optional
system features that are applicable, and to program the MCH registers accordingly.
“ST” appended to The bit is “sticky” or unchanged by a hard reset. These bits can only be cleared by a
the end of a bit
name
PWRGOOD reset.
3.2
Platform Configuration Structure
In some previous chipsets, the MCH and the South Bridge were physically connected by
PCI bus 0. From a configuration standpoint, both components appeared to be on PCI
bus 0 which was also the system’s primary PCI expansion bus. The MCH contained two
PCI devices while the south bridge was considered one PCI device with multiple
functions.
In the Intel 5000X chipset-based platform, the configuration structure is significantly
different. The MCH and the Intel 631xESB/632xESB I/O Controller Hub are physically
connected by the ESI interface; thus, from a configuration standpoint, the ESI interface
is logically PCI bus 0. As a result, all devices internal to the MCH and Intel 631xESB/
632xESB I/O Controller Hub appear to be on PCI bus 0. The system’s primary PCI
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
expansion bus is physically attached to the Intel 631xESB/632xESB I/O Controller Hub
and, from a configuration perspective, appears to be a hierarchical PCI bus behind a
PCI-to-PCI bridge; therefore, it has a programmable PCI Bus number.
The MCH contains 14 PCI devices within a single physical component. The configuration
registers for these devices are mapped as devices residing on PCI bus 0.
• Device 0: ESI bridge/PCI Express Port 0. Logically, this appears as a PCI device
that resides on PCI bus 0. Physically Device 0, Function 0 contains the PCI Express
configuration registers for the ESI port, and other MCH specific registers.
• Device 2: PCI Express 2. Logically this appears as a PCI device residing on bus 0.
Device 2, Function 0 is routed to the PCI Express configuration registers for PCI
Express port 2. When PCI Express ports 2 and 3 are combined into a single x8 port,
controlled by port 2 registers, Device 3, Function 0 (port 3) configuration registers
are inactive. PCI Express port 2 resides at DID of 25E2h(x4) or 25F7h(x8).
• Device 3: PCI Express 3. Logically this appears as a PCI device that resides on bus
0. Device 3, Function 0 contains the PCI Express configuration registers for PCI
Express port 3. When PCI Express ports 2 and 3 are combined into a single x8 port,
controlled by port 2 registers, these configuration registers are inactive. PCI
Express port 3 resides at DID of 25E3h.
• Device 4: PCI Express 4. Logically this appears as a PCI device that resides on bus
0. Device 4, Function 0 contains the PCI Express configuration registers for PCI
Express port 4. When PCI Express ports 4, 5, 6, and 7 are combined into a single
x16 graphics port, Device 4, Function 0 contains the configuration registers and
Device 5, Function 0 (port 5), Device 6, Function 0 (port 6), and Device 7, Function
0 (port 7), configuration registers are inactive. PCI Express port 4 resides at DID of
25E4h(x4) or 25F8h(x8) or 25FAh(x16).
• Device 5: PCI Express 5. Logically this appears as a PCI device that resides on bus
0. Device 5, Function 0 contains the PCI Express configuration registers for PCI
Express port 5. When PCI Express ports 4, 5, 6 and 7 are combined into a single
x16 graphics port Device 4, Function 0 contains the configuration registers, and
these configuration registers are inactive. PCI Express port 5 resides at DID of
25E5h.
• Device 6: PCI Express 6. Logically this appears as a PCI device residing on bus 0.
Device 6, Function 0 contains the PCI Express configuration registers for PCI
Express port 6. When PCI Express ports 4, 5, 6 and 7 are combined into a single
x16 graphics port Device 4, Function 0 contains the configuration registers, and
these configuration registers are inactive. PCI Express port 6 resides at DID of
25E6h(x4) or 25F9(x8).
• Device 7: PCI Express 7. Logically this appears as a PCI device residing on bus 0.
Device 7, Function 0 contains the PCI Express configuration registers for PCI
Express port 7. When PCI Express ports 4, 5, 6 and 7 are combined into a single
x16 graphics port Device 4, Function 0 contains the configuration registers, and
these configuration registers are inactive. PCI Express port 2 resides at DID of
25E7h.
• Device 9: Device 9, Function 0 is routed to the Advanced Memory Buffer memory
map. This interface is supported through the JTAG and SMBus interfaces and
AMBSELECT register only.
• Device 16: Device 16, Function 0 is routed to the Frontside Bus (FSB) Controller,
Interrupt and System Address registers. Function 1 is routed to the Frontside Bus
Address Mapping, Memory Control, and Error registers. Function 2 is routed to FSB
Error Registers. These devices reside at DID 25F0h.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
45
Register Description
• Device 17: Device 17, Function 0 is routed to the Coherency Engine and Data
Manager registers. These devices reside at DID 25F1h.
• Device 19: Device 19, Function 0 is routed to the Debug and Miscellaneous
registers. These devices reside at DID 25F3h.
• Device 21: Device 21, Function 0, FBD Branch 0 Memory Map, Error Flag/Mask,
and Channel Control registers. These devices reside at DID 25F5h.
• Device 22: Device 22, Function 0, FBD Branch 1 Memory Map, Error Flag/Mask,
and Channel Control registers. These devices reside at DID 25F6h.
Figure 3-1. Conceptual Intel® 5000X chipset MCH PCI Configuration Diagram
Processor 0
Processor 1
PCI Config Window in I/O Space
4 bit
PCI Express
Port 4
PCI Express Port 4
Bridge Bus 0, Dev 4
4 bit
PCI Express
Port 5
PCI Express Port 5
Bridge Bus 0, Dev 5
4 bit
PCI Express
Port 2
4 bit
PCI Express
Port 6
PCI Express Port 2
Bridge Bus 0, Dev 2
PCI Express Port 6
Bridge Bus 0, Dev 6
4 bit
PCI Express
Port 7
4 bit
PCI Express
Port 3
PCI Express Port 7
Bridge Bus 0, Dev 7
PCI Express Port 3
Bridge Bus 0, Dev 3
DMI
Intel® 5000X
Chipset
(PCI Express Bridge Bus 0,
Dev 0)
DMI Interface (logical PCI Bus 0)
DMI
(PCI Express Bridge Bus 0,
Dev X)
4 bit
PCI Express
Port 0
PCI Express Port 0
Bridge Bus 0, Dev Y
4 bit
PCI Express
Port 0
PCI Express Port 1
Bridge Bus 0, Dev Z
LPC Device
Bus 0, Dev 31, Func 0
USB Controllers
Bus 0, Dev 29,
Func 0,1,2,7
IDE Controller
Bus 0, Dev 31, Func 1
Primary PCI
Programmable
Bus #
HI-PCI Bridge
Bus 0, Dev 30, Func 0
SMBus Controller
Bus 0, Dev 31, Func 3
LAN Controller
Bus n, Dev 8, Func 0
AC97 Controller
Bus 0, Dev 31, Func 5,6
Intel® 631xESB/632xESB I/O Controller Hub
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.3
Routing Configuration Accesses
Intel® 5000X chipset MCH supports both PCI Type 0 and Type 1 configuration access
mechanisms as defined in the PCI Local Bus Specification, Revision 2.3. PCI Revision
2.3 defines hierarchical PCI busses. Type 0 configuration access are used for registers
located within a PCI device that resides on the local PCI bus. That is, the PCI bus the
transaction is initiated on. Type 0 configuration transactions are not propagated beyond
the local PCI bus. Type 0 configuration transactions must be claimed by a local device
or master aborted.
Type 1 configuration accesses are used for devices residing on subordinate PCI buses.
i.e Devices that are connected via PCI-to-PCI bridges. All targets except PCI-to-PCI
bridges ignore Type 1 configuration transactions. PCI-to-PCI bridges decode the bus
number information in Type 1 transactions. It the transaction is targeted to a device
local to the PCI-to-PCI bridge it is translated into a Type 0 transaction and issued to the
device. If the transaction is targeted to a bus subordinate (behind) to PCI-to-PCI
bridge, it passed through unchanged. Otherwise the Type 1 transaction is dropped.
Accesses to non operational or non existent devices are master aborted. This means
that writes are dropped and reads return all 1’s.
3.3.1
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that supports up to 32 devices.
Each device is allowed to contain up to eight functions with each function containing up
to 256, 8-bit configuration registers. The PCI specification defines two bus cycles to
access the PCI configuration space: Configuration Read and Configuration Write.
Memory and I/O spaces are supported directly by the processor. Configuration space is
supported by a mapping mechanism implemented within the MCH. The PCI 2.3
specification defines the configuration mechanism to access configuration space. The
configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O
address 0CF8h through 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh
through 0CFFh). To reference a configuration register a DWord I/O write cycle is used
to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that
bus, the function within the device, and a specific configuration register of the device
function being accessed. CONFIG_ADDRESS[31] must be set to 1b, to enable a
configuration cycle. CONFIG_DATA then becomes a window into the four bytes of
configuration space specified by the contents of CONFIG_ADDRESS. Any read or write
to CONFIG_DATA will result in the MCH translating the CONFIG_ADDRESS into the
appropriate configuration cycle.
The MCH is responsible for translating and routing the processor’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration
registers.
3.3.2
PCI Bus 0 Configuration Mechanism
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the
configuration cycle is targeting a device on PCI Bus 0.
The ESI bridge entity within the MCH is hardwired as Device 0 on PCI Bus 0. The ESI
bridge passes PCI south bridge configuration requests to the south bridge.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
47
Register Description
3.3.3
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, the MCH will generate a Type
1 PCI configuration cycle. A[1:0] of the ESI request packet for the Type 1 configuration
cycle will be 01. Bits 31:2 of the CONFIG_ADDRESS register will be translated to the
A[31:2] field of the ESI request packet of the configuration cycle as shown in
Figure 3-2. This configuration cycle will be sent over the ESI to Intel 631xESB/632xESB
I/O Controller Hub.
If the cycle is forwarded to the Intel 631xESB/632xESB I/O Controller Hub via ESI, the
Intel 631xESB/632xESB I/O Controller Hub compares the non-zero Bus Number with
the Secondary Bus Number and Subordinate Bus Number Registers of its PCI-to-PCI
bridges to determine if the configuration cycle is meant for primary PCI bus, one of the
Intel 631xESB/632xESB I/O Controller Hub’s PCI Express ports, or a downstream PCI
bus.
Figure 3-2. Type 1 Configuration Address to PCI Address Mapping
3
1
3
0
2
4
2
3
1
0
16 15
11
8 7
2 1
0
CONFIG_ADDRESS
Reserved
Bus Number Device Number
Function Number
X X
Reg. Index
1
Device
Number
Bus
Number
Reg.
Index
PCI Address
AD[31:0]
0
Function Number
0 1
0
2
4
2
3
1 1
1 0
31
16 15
8 7
2 1
3.4
Device Mapping
Each component in a Intel® 5000X chipset system is uniquely identified by a PCI bus
address consisting of; Bus Number, Device Number and Function Number. Device
configuration is based on the PCI Type 0 configuration conventions. All PCI devices
within a Intel® 5000X chipset platform must support Type 0 configuration accesses. All
MCH registers in the Intel® 5000X chipset MCH appear on Bus #0.
All Intel® 5000X chipset MCH configuration registers reside in the configuration space
defined by Bus, Device, Function, Register address. Some registers do not appear in all
portions of this space and some mechanisms do not access all portions of this space. In
general the configuration space is sparsely populated. The following table defines
where the various fields of configuration register addresses appear. Each row defines a
different access mechanism, register, interface, or decoder. Each column defines a
different field of the configuration address.
®
48
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
.
Table 3-1.
Configuration Address Bit Mapping
Dword
Offset
Source/
Destination
Byte in
Dword
Bus
Bus[7:0]
A[27:20]
Device
Function
Type
[11:8]
[5:0]
PCI Express Config Destination
Device[4:0] Function[2:0 Extended
Register
[5:0]
1st DW
BE[3:0]
Fmt,
Type
Txns (including
ESI)
]
Register
Addr[3:0]
PCI Express
MMCFG
on FSB
Source
A[19:15]
A[14:12]
A[11:8]
A[7:3]
BE[7:4]
BE[7:0]
n/a
PCI Express
MMCFG
Not permitted to access MCH or FB-DIMM regs and will be master aborted.
from ESI or PCI
Express
CPU/Inbound
CB_BAR MMIO
Access
Source
Source
Source
0
8
1
A[11:8]
A[7:3]
BE[7:4]
BE[7:0]
n/a
CFGADR Register
Bus Number DeviceID
[7:0] [4:0]
Function
Number[2:0]
not present Register
Address
Not present n/a
[5:0]
CFC on
FSB
CFGADR Register, see row above
BE[7:4]
Register
n/a
n/a
JTAG Config Access Source
Bus Number DeviceID
[7:0] [4:0]
Function
Extended
Number[2:0] Register
Addr[3:0]
Register
Address[7:2 Address
]
[1:0]
SMBus Config
Access
Source
Bus Number Dev[4:0]
[7:0]
Func[2:0]
Reg
Number
[11:8]
Reg[7:2]
command,
Register
Number
n/a
Fixed MCH Memory Source
Mapped on FSB
0
16
0
cannot
access
A[15:10]
All accesses n/a
are 4 byte
MCH Register
Decoding
Destination
00000000
See Table
14-4
Function[2:0 Dword
Offset[9:6]
Dword
Offset[5:0]
Byte[3:0]
n/a
]
1
FB-DIMM Config
Cmds
Destination
A[23:15]
always 0
See Note
Cannot
access
A[7:3]
BE[7:4]
BE[7:0]
n/a
Notes:
1. These accesses are used to select channel/DIMM based on the AMBASE register.
3.4.1
Device Identification for Intel 5000P Chipset, Intel 5000Z
Chipset, and Intel 5000V Chipset Components
All devices in the Intel® 5000X chipset MCH reside on Bus 0. The following table
describes the root device ID for different MCH versions.
Table 3-2.
Memory Control Hub ESI Device Identification
Functio
Component
Register Group
DID
Device
n
Intel 5000P Chipset
Intel 5000Z Chipset
Intel 5000V Chipset
Enterprise South Bridge Interface
Enterprise South Bridge Interface
Enterprise South Bridge Interface
25C8h
25D0h
25D4h
0
0
0
0
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
49
Register Description
3.4.2
Special Device and Function Routing
All devices in the Intel® 5000X chipset MCH reside on Bus 0. The following table
describes the devices and functions that the MCH implements or routes specially. The
DIMM component designator consists of a three-digit code: the first digit is the branch,
the second digit is the channel on the branch, and the third digit is the DIMM (FB-DIMM
command “DS” field) on the channel.
Table 3-3.
Functions Specially Handled by the MCH
Functio
Component
Register Group
DID
Device
Comment
n
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
PCI Express Port 2
25E2h
25E3h
25E4h
25E5h
25E6h
25E7h
1A38h
N/A
2
0
0
0
0
0
0
0
1
0
Depending on what is
connected to these
ports, some may not be
accessible.
PCI Express Port 3
PCI Express Port 4
PCI Express Port 5
PCI Express Port 6
PCI Express Port 7
DMA Engine
3
4
5
6
7
8
New device mapping for
DMA Engine
DMA Engine MMIO Space
8
Memory Map, Error Flag/Mask,
RAS, Channel Control for FB-
DIMM Branch 0
25F5h
21
Debug and DFT in
higher address offsets.
MCH
Memory Map, Error Flag/Mask,
RAS, Channel Control for FB-
DIMM Branch 1
25F6h
22
0
Debug and DFT in
higher address offsets.
MCH
Processor Bus, Boot, Interrupt,
System Address
25F0h
N/A
16
9
0
0
Debug and DFT in
higher address offsets.
DIMM
AMB Memory Mapped registers
Route out to AMB per
AMBSELECT register
only for JTAG/SMBus.
MCH
Address Mapping, Memory
Control, Error Logs
25F0h
16
1
Debug and DFT in
higher address offsets.
MCH
MCH
FSB Error Registers
PCI Express Port 2-3
25F0h
25F7h
16
2
2
0
x8 mode. Only port 2 is
active
MCH
MCH
MCH
PCI Express Port 4-5
PCI Express Port 6-7
PCI Express Port 4-7
25F8h
25F9h
25FAh
4
6
4
0
0
0
x8 mode. Only port 4 is
active
x8 mode. Only port 6 is
active
x16 mode. Only port 4
is active
To comply with the PCI specification, accesses to non-existent functions, registers, and
bits will be master aborted. This behavior is defined in the following table:
®
50
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-4.
Access to “Non-Existent” Register Bits
Access to
Writes
Have no effect
Reads
Devices listed in Table 3-2, “Memory Control Hub
ESI Device Identification” on page 49 but to
functions not listed
MCH returns all ones
Devices listed in Table 3-2, “Memory Control Hub
ESI Device Identification” on page 49, but to
registers not listed in SSection 3.8, “Register
Definitions.”
Have no effect
MCH returns all zeroes
MCH returns all zeroes
Reserved bits in registers
Software must read-
modify-write to preserve
the value
3.5
I/O Mapped Registers
There are only two I/O addresses that affect the Intel 5000X MCH state. The first
address is the DWORD location (CF8h) references a read/write register that is named
CONFIG_ADDRESS. The second DWORD address (CFCh) references a read/write
register named CONFIG_DATA. These two addresses are used for the PCI CFCh / CF8h
configuration access mechanism.
3.5.1
CFGADR: Configuration Address Register
CFGADR is written only when a processor I/O transaction to I/O location CF8h is
referenced as a DWord; a Byte or Word reference will not access this register, but will
generate an I/O space access. Therefor the only I/O space taken up by this register is
the DWORD at location CF8h. I/O devices that share the same address but use BYTE or
WORD registers are not affected because their transactions will pass through the host
bridge unchanged.
The CFGADR register contains the Bus Number, Device Number, Function Number, and
Register Offset for which a subsequent CFGDAT access is intended. The mapping
between fields in this register and PCI Express configuration transactions is defined by
Table 3-1.
Table 3-5.
I/O Address: CF8h
Bit
Attr
Default
Description
31
RW
0h
CFGE: Configuration Enable
Unless this bit is set, accesses to the CFGDAT register will not produce a
configuration access, but will be treated as other I/O accesses. This bit is
strictly an enable for the CFC/CF8 access mechanism and is not forwarded to
ESI or PCI Express.
30:24
23:16
RV
00h
00h
Reserved.
RW
Bus Number
If 0, the MCH examines device to determine where to route. If non-zero, route
as per PBUSN and SBUSN registers.
15:11
10:8
7:2
RW
RW
RW
0h
0h
Device Number
This field is used to select one of the 32 possible devices per bus.
Function Number
This field is used to select the function of a locally addressed register.
00h
Register Offset
If this register specifies an access to MCH registers, this field specifies a group
of four bytes to be addressed. The bytes accessed are defined by the Byte
enables of the CFGDAT register access
1:0
RW
0h
Writes to these bits have no effect, reads return 0
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
51
Register Description
3.5.2
Table 3-6.
3.6
CFGDAT: Configuration Data Register
CFGDAT provides data for the 4 bytes of configuration space defined by CFGADR. This
register is only accessed if there is an access to I/O address, CFCh on the processor bus
and CFGADR.CFGE (configuration enable) bit is set. The byte enables with the I/O
access define how many configuration bytes are accessed.
I/O Address: CFCh
Bit
Attr
Default
Description
31:0
RW
0
Configuration Data Window
The data written or read to the configuration register (if any) specified by
CFGADR
MCH Fixed Memory Mapped Registers
These registers are mapped into the fixed chipset specific range located from FE60
0000h - FE6F FFFFh.These appear at fixed addresses to support the boot process.
These registers also appear in the regular PCI Express configuration space.
The following table defines the memory address of the registers in this region.
Table 3-7.
Mapping for Fixed Memory Mapped Registers
Register
BOFL0
Memory Address
FE60_C000
BOFL1
FE60_C400
FE60_C800
FE60_CC00
FE60_D000
FE60_D400
FE60_D800
FE60_DC00
FE60_E000
FE60_E400
FE60_E800
FE60_EC00
FE61_4800
FE61_4C00
FE61_6400
BOFL2
BOFL3
SPAD0
SPAD1
SPAD2
SPAD3
SPADS0
SPADS1
SPADS2
SPADS3
AMBASE[31:0]
AMBASE[63:32]
HECBASE
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52
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.7
Detailed Configuration Space Maps
Table 3-8.
Device 0, Function 0: PCI Express PCI Space
DID
PCISTS
VID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
PEXSLOTCAP
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
PCICMD
PEXSLOTSTS
PEXSLOTCTRL
PEXRTCTRL
CCR
HDR
RID
CLS
BIST
PRI_LT
PEXRTSTS
SID
SVID
CAPPTR
INTL
INTP
PEXLWSTPCTRL
CBPRES
SSCTRL
PEXCTRL
PEXCTRL3
INTXSWZ
CTRL
PEXCTRL2
PMCAP
PMCSR
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
ESICTRL
MSICTRL
MSINXPTR
MSICAPID
MSIAR
MSIDR
PEXCAP
PEXCAPL
PEXDEVCAP
PEXLNKCAP
PEXDEVSTS
PEXLNKSTS
PEXDEVCTRL
PEXLNKCTRL
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
53
Register Description
Table 3-9.
Device 0, Function 0: PCI Express Extended Registers
PEXENHCAP
UNCERRSTS
UNCERRMSK
UNCERRSEV
CORERRSTS
CORERRMSK
AERRCAPCTRL
HDRLOG0
100h
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h
128h
12Ch
130h
134h
138h
13Ch
140h
144h
148h
14Ch
150h
154h
158h
15Ch
160h
164h
168h
16Ch
170h
180h
184h
188h
18Ch
190h
194h
198h
19Ch
1A0h
1A4h
1A8h
1ACh
1B0h
1B4h
1B8h
1BCh
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
1DCh
1E0h
1E4h
1E8h
1ECh
1F0h
HDRLOG1
HDRLOG2
HDRLOG3
RPERRCMD
RPERRSTS
RPERRSID
Intel 5000P Sequence chipset MCHSPCAPID
PEX_ERR_DOCMD
EMASK_UNCOR_PEX
EMASK_COR_PEX
EMASK_RP_PEX
PEX_FAT_FERR
PEX_NF_COR_FERR
PEX_FAT_NERR
PEX_NF_COR_NERR
PEX_SSER
R
174h
178h
17Ch
1F4h
1F8h
1FCh
®
54
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-10. Device 0, Function 0: PCI Express Intel® Interconnect BIST (Intel® IBIST)
Registers
300h
304h
308h
30Ch
PEX0IBCTL
PEX0IBSYMBUF
PEX0IBEXTCTL
380h
384h
388h
38Ch
PEX0IBLOOPCNT
PEX0IBLN PEX0IBLN
PEX0IBDLYSYM
PEX0IBLN PEX0IBLN
310h
314h
390h
394h
S3 S2
S1
S0
DIO0IBER
R
DIO0IBST
AT
318h
31Ch
320h
324h
328h
32Ch
330h
334h
338h
33Ch
340h
344h
348h
34Ch
350h
354h
358h
35Ch
360h
364h
368h
36Ch
370h
374h
378h
37Ch
DIOIBSTR
398h
39Ch
3A0h
3A4h
3A8h
3ACh
3B0h
3B4h
3B8h
3BCh
3C0h
3C4h
3C8h
3CCh
3D0h
3D4h
3D8h
3DCh
3E0h
3E4h
3E8h
3ECh
3F0h
3F4h
3F8h
3FCh
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
55
Register Description
Table 3-11. Device 2-3, Function 0: PCI Express PCI Space
DID
VID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
PEXSLOTCAP
PEXRTSTS
80h
PCISTS
PCICMD
PEXSLOTSTS
PEXSLOTCTRL
PEXRTCTRL
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
CCR
HDR
RID
CLS
BIST
PRI_LT
SEC_LT
SUBUSN
SBUSN
IOLIM
PBUSN
SECSTS
IOBASE
MBASE
PMBASE
MLIM
PMLIM
PMBU
PMLU
CAPPTR
BCTRL
INTP
INTL
SSCTRL
PEXCTRL
CBCTRL PEXCTRL3
INTXSWZ
CTRL
PEXCTRL2
MSICAPID
PMCAP
PMCSR
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
MSICTRL
MSINXPTR
MSIAR
MSIDR
PEXCAP
PEXCAPL
PEXDEVCAP
PEXLNKCAP
PEXDEVSTS
PEXLNKSTS
PEXDEVCTRL
PEXLNKCTRL
®
56
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-12. Device 2-3, Function 0: PCI Express Extended Registers
PEXENHCAP
UNCERRSTS
UNCERRMSK
UNCERRSEV
CORERRSTS
CORERRMSK
AERRCAPCTRL
HDRLOG0
100h
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h
128h
12Ch
130h
134h
138h
13Ch
140h
144h
148h
14Ch
150h
154h
158h
15Ch
160h
164h
168h
16Ch
170h
180h
184h
188h
18Ch
190h
194h
198h
19Ch
1A0h
1A4h
1A8h
1ACh
1B0h
1B4h
1B8h
1BCh
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
1DCh
1E0h
1E4h
1E8h
1ECh
1F0h
HDRLOG1
HDRLOG2
HDRLOG3
RPERRCMD
RPERRSTS
RPERRSID
Intel 5000P Sequence chipset MCHSPCAPID
PEX_ERR_DOCMD
EMASK_UNCOR_PEX
EMASK_COR_PEX
EMASK_RP_PEX
PEX_FAT_FERR
PEX_NF_COR_FERR
PEX_FAT_NERR
PEX_NF_COR_NERR
PEX_UNIT_FERR
PEX_UNIT_NERR
PEX_SSER
R
174h
178h
17Ch
1F4h
1F8h
1FCh
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
57
Register Description
Table 3-13. Device 2-3, Function 0: PCI Express Intel IBIST Registers
300h
304h
308h
30Ch
PEX[3:2]IBCTL
PEX[3:2]IBSYMBUF
PEX[3:2]IBEXTCTL
380h
384h
388h
PEX[3:2]IBLOOPCNT
PEX[3:2]IBDLYSYM
38Ch
390h
PEX[3:2]I
BLNS3
PEX[3:2]I
BLNS2
PEX[3:2]I
BLNS1
PEX[3:2]I
BLNS0
310h
314h
318h
31Ch
320h
324h
328h
32Ch
330h
334h
338h
33Ch
340h
344h
348h
34Ch
350h
354h
358h
35Ch
360h
364h
368h
36Ch
370h
374h
378h
37Ch
394h
398h
39Ch
3A0h
3A4h
3A8h
3ACh
3B0h
3B4h
3B8h
3BCh
3C0h
3C4h
3C8h
3CCh
3D0h
3D4h
3D8h
3DCh
3E0h
3E4h
3E8h
3ECh
3F0h
3F4h
3F8h
3FCh
®
58
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-14. Device 4, Function 0: PCI Express PCI Space
DID
VID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
PEXSLOTCAP
PEXRTSTS
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
PCISTS
PCICMD
PEXSLOTSTS
PEXSLOTCTRL
PEXRTCTRL
CCR
HDR
RID
CLS
BIST
PRI_LT
SEC_LT
SUBUSN
SBUSN
IOLIM
PBUSN
SECSTS
IOBASE
MBASE
PMBASE
MLIM
PMLIM
PMBU
PMLU
CAPPTR
BCTRL
INTP
INTL
SSCTRL
PEXCTRL
INTXSWZ
CTRL
PEXCTRL3
PEXCTRL2
MSICAPID
PMCAP
PMCSR
MSINXPTR
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
MSICTRL
MSIAR
MSIDR
PEXCAP
PEXCAPL
PEXDEVCAP
PEXLNKCAP
PEXDEVSTS
PEXLNKSTS
PEXDEVCTRL
PEXLNKCTRL
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
59
Register Description
Table 3-15. Device 4, Function 0: PCI Express Extended Registers
PEXENHCAP
UNCERRSTS
UNCERRMSK
UNCERRSEV
CORERRSTS
CORERRMSK
AERRCAPCTRL
HDRLOG0
100h
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h
128h
12Ch
130h
134h
138h
13Ch
140h
144h
148h
14Ch
150h
154h
158h
15Ch
160h
164h
168h
16Ch
170h
180h
184h
188h
18Ch
190h
194h
198h
19Ch
1A0h
1A4h
1A8h
1ACh
1B0h
1B4h
1B8h
1BCh
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
1DCh
1E0h
1E4h
1E8h
1ECh
1F0h
HDRLOG1
HDRLOG2
HDRLOG3
RPERRCMD
RPERRSTS
RPERRSID
Intel 5000P Chipset MCHSPCAPID
PEX_ERR_DOCMD
EMASK_UNCOR_PEX
EMASK_COR_PEX
EMASK_RP_PEX
PEX_FAT_FERR
PEX_NF_COR_FERR
PEX_FAT_NERR
PEX_NF_COR_NERR
PEX_UNIT_FERR
PEX_UNIT_NERR
PEX_SSER
R
174h
178h
17Ch
1F4h
1F8h
1FCh
®
60
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-16. Device 4, Function 0: PCI Express Intel IBIST Registers
300h
304h
308h
30Ch
PEX4IBCTL
PEX4IBSYMBUF
PEX4IBEXTCTL
380h
384h
388h
38Ch
PEX4IBLOOPCNT
PEX4IBDLYSYM
PEX4IBLN PEX4IBLN
PEX4IBLN PEX4IBLN
310h
390h
S3 S2
S1 S0
314h
318h
31Ch
320h
324h
328h
32Ch
330h
334h
338h
33Ch
340h
344h
348h
34Ch
350h
354h
358h
35Ch
360h
364h
368h
36Ch
370h
374h
378h
37Ch
394h
398h
39Ch
3A0h
3A4h
3A8h
3ACh
3B0h
3B4h
3B8h
3BCh
3C0h
3C4h
3C8h
3CCh
3D0h
3D4h
3D8h
3DCh
3E0h
3E4h
3E8h
3ECh
3F0h
3F4h
3F8h
3FCh
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
61
Register Description
Table 3-17. Device 5-7, Function 0: PCI Express PCI Space
DID
VID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
PEXSLOTCAP
PEXRTSTS
80h
PCISTS
PCICMD
PEXSLOTSTS
PEXSLOTCTRL
PEXRTCTRL
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
CCR
HDR
RID
CLS
BIST
PRI_LT
SEC_LT
SUBUSN
SBUSN
IOLIM
PBUSN
SECSTS
IOBASE
MBASE
PMBASE
MLIM
PMLIM
PMBU
PMLU
CAPPTR
BCTRL
INTP
INTL
SSCTRL
PEXCTRL
PEXCTRL3
INTXSWZ
CTRL
PEXCTRL2
MSICAPID
PMCAP
PMCSR
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
MSICTRL
MSINXPTR
MSIAR
MSIDR
PEXCAP
PEXCAPL
PEXDEVCAP
PEXLNKCAP
PEXDEVSTS
PEXLNKSTS
PEXDEVCTRL
PEXLNKCTRL
®
62
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-18. Device 5-7, Function 0: PCI Express Extended Registers
PEXENHCAP
UNCERRSTS
UNCERRMSK
UNCERRSEV
CORERRSTS
CORERRMSK
AERRCAPCTRL
HDRLOG0
100h
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h
128h
12Ch
130h
134h
138h
13Ch
140h
144h
148h
14Ch
150h
154h
158h
15Ch
160h
164h
168h
16Ch
170h
180h
184h
188h
18Ch
190h
194h
198h
19Ch
1A0h
1A4h
1A8h
1ACh
1B0h
1B4h
1B8h
1BCh
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
1DCh
1E0h
1E4h
1E8h
1ECh
1F0h
HDRLOG1
HDRLOG2
HDRLOG3
RPERRCMD
RPERRSTS
RPERRSID
Intel 5000P Chipset MCHSPCAPID
PEX_ERR_DOCMD
EMASK_UNCOR_PEX
EMASK_COR_PEX
EMASK_RP_PEX
PEX_FAT_FERR
PEX_NF_COR_FERR
PEX_FAT_NERR
PEX_NF_COR_NERR
PEX_UNIT_FERR
PEX_UNIT_NERR
PEX_SSER
R
174h
178h
17Ch
1F4h
1F8h
1FCh
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
63
Register Description
Table 3-19. Device 5-7, Function 0: PCI Express Intel IBIST Registers
300h
304h
308h
30Ch
PEX[7:5]IBCTL
PEX[7:5]IBSYMBUF
PEX[7:5]IBEXTCTL
380h
384h
388h
PEX[7:5]IBLOOPCNT
PE[7:5]IBDLYSYM
38Ch
390h
PEX[7:5]I
BLNS3
PEX[7:5]I
BLNS2
PEX[7:5]I
BLNS1
PEX[7:5]I
BLNS0
310h
314h
318h
31Ch
320h
324h
328h
32Ch
330h
334h
338h
33Ch
340h
344h
348h
34Ch
350h
354h
358h
35Ch
360h
364h
368h
36Ch
370h
374h
378h
37Ch
394h
398h
39Ch
3A0h
3A4h
3A8h
3ACh
3B0h
3B4h
3B8h
3BCh
3C0h
3C4h
3C8h
3CCh
3D0h
3D4h
3D8h
3DCh
3E0h
3E4h
3E8h
3ECh
3F0h
3F4h
3F8h
3FCh
Table 3-20. Device 9, Function 0: AMB Switching Window Registers
Route out AMB as per AMBSELECT register
0h - 255h
This function is only accessible by SMBus or JTAG. Other accesses will be routed to ESI
and get master aborted.
Accessing to this function is routed out to FB-DIMM channel as per AMBSELECT register
subject to AMBPRESENT register settings.
®
64
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-21. Device 16, Function 0: Processor Bus, Boot, and Interrupt
DID
VID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h
54h
XTPR0
XTPR1
XTPR2
XTPR3
XTPR4
XTPR5
XTPR6
XTPR7
XTPR8
XTPR9
XTPR10
XTPR11
XTPR12
XTPR13
XTPR14
XTPR15
BOFL0
BOFL1
BOFL2
BOFL3
SPAD0
SPAD1
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
D0h
D4h
CCR
HDR
RID
SID
SVID
SYRE
CPURSTCAPTMR
POC
AMBASE
AMR
MAXAMB
MAXCH
AMBSELECT
PERCH
PAM2
PAM1
PAM5
PAM0
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
SPAD2
SPAD3
D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
PAM6
PAM4
PAM3
EXSMRTOP
EXSMRC
SMRAMC
EXSMRAMC
SPADS0
HECBASE
REDIRBUCKETS
SPADS1
SPADS2
REDIRCTL
SPADS3
PROCENABLE
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
65
Register Description
Table 3-22. Device 16, Function 1: Memory Branch Map, Control, Errors
DID
VID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
MIR0
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
MIR1
MIR2
CCR
HDR
RID
AMIR0
AMIR1
AMIR2
FERR_FAT_FBD
NERR_FAT_FBD
FERR_NF_FBD
NERR_NF_FBD
EMASK_FBD
ERR0_FBD
SID
SVID
ERR1_FBD
ERR2_FBD
MCERR_FBD
NRECMEMA
MC
NRECMEMB
NRECFGLOG
NRECFBDA
NRECFBDB
NRECFBDC
NRECFBDD
NRECFBDE
RESERVED
DRTA
DRTB
ERRPER
DDRFRQ
MCA
GBLACT
RECMEMA
THRTCTRL
THRTSTS1
THRTHI
THRTMID
THRTLOW
RECMEMB
RECFGLOG
RECFBDA
RECFBDB
RECFBDC
RECFBDD
RECFBDE
THRTSTS0
TOLM
REDMEMB
®
66
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-23. Device 16, Function 2: RAS
DID
VID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
CCR
HDR
RID
SID
SVID
NRECSF
RECSF
FERR_Global
NERR_Global
NERR_NF_I
NT
NERR_FAT_
INT
FERR_NF_I FERR_FAT_I
NT
NT
44h
48h
4Ch
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
NRECINT
RECINT
C4h
C8h
CCh
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
F0h
F4h
F8h
FCh
EMASK_INT
ERR0_INT
MCERR_INT
ERR2_INT
ERR1_INT
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
67
Register Description
Table 3-24. Device 21, 22, Function 0: FB-DIMM Map, Control, RAS
DID
VID
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
MTR0
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
MTR1
MTR2
MTR3
CCR
HDR
RID
DMIR0
DMIR1
DMIR2
DMIR3
DMIR4
UERRCNT
CERRCNT
BADRAMA
SID
SVID
BADRAMB
BADCNT
SPCPS
SPCPC
FBDSBTXCF FBDSBTXCF
G1 G0
FBDICMD1
FBDST
FBDICMD0
FBDLVL1
HPST0
FBDLVL0
44h
48h
4Ch
50h
54h
58h
5Ch
C4h
C8h
CCh
D0h
D4h
D8h
DCh
FBDHPC
HPHPC0
HPST1
HPCTL1
FBDISTS1
FBDISTS0
60h
E0h
AMBPRESENT1
AMBPRESENT0
64h
68h
6Ch
70h
74h
78h
7Ch
E4h
E8h
ECh
F0h
F4h
F8h
FCh
SPD1
SPD0
SPDCMD0
SPDCMD1
®
68
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-25. Device 21, Function 0: FB-DIMM 0 Intel IBIST Registers
100h
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h
128h
12Ch
130h
134h
138h
13Ch
140h
144h
148h
14Ch
150h
154h
158h
15Ch
160h
164h
168h
16Ch
170h
174h
178h
17Ch
FBD0IBPORTCTL
FBD0IBTXPGCTL
FBD0IBPATBUF1
FBD0IBTXMSK
180h
184h
188h
18Ch
190h
194h
198h
19Ch
1A0h
1A4h
1A8h
1ACh
1B0h
1B4h
1B8h
1BCh
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
1DCh
1E0h
1E4h
1E8h
1ECh
1F0h
1F4h
1F8h
1FCh
FBD0IBRXMSK
FBD0IBTXSHFT
FBD0IBRXSHFT
FBD0RXLNERR
FBD0IBRXPGCTL
FBD0IBPATBUF2
FBD0IBTXPAT2EN
FBD0IBRXPAT2EN
FBD0TS1PARM
FBDPLLCTRL
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Register Description
Table 3-26. Device 21, Function 0: FB-DIMM 1 IBST Registers
200h
204h
208h
20Ch
210h
214h
218h
21Ch
220h
224h
228h
22Ch
230h
234h
238h
23Ch
240h
244h
248h
24Ch
250h
254h
258h
25Ch
260h
264h
268h
26Ch
270h
274h
278h
27Ch
FBD1IBPORTCTL
280h
284h
288h
28Ch
290h
294h
298h
29Ch
2A0h
2A4h
2A8h
2ACh
2B0h
2B4h
2B8h
2BCh
2C0h
2C4h
2C8h
2CCh
2D0h
2D4h
2D8h
2DCh
2E0h
2E4h
2E8h
2ECh
2F0h
2F4h
2F8h
2FCh
FBD1IBTXPGCTL
FBD1IBPATBUF
FBD1IBTXMSK
FBD1IBRXMSK
FBD1IBTXSHFT
FBD1IBRXSHFT
FBD1RXLNERR
FBD1IBRXPGCTL
FBD1IBPATBUF2
FBD1IBTXPAT2EN
FBD1IBRXPAT2EN
FBD1TS1PARM
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Register Description
Table 3-27. Device 22, Function 0: FB-DIMM 2 IBST Registers
100h
104h
108h
10Ch
110h
114h
118h
11Ch
120h
124h
128h
12Ch
130h
134h
138h
13Ch
140h
144h
148h
14Ch
150h
154h
158h
15Ch
160h
164h
168h
16Ch
170h
174h
178h
17Ch
FBD2IBPORTCTL
180h
184h
188h
18Ch
190h
194h
198h
19Ch
1A0h
1A4h
1A8h
1ACh
1B0h
1B4h
1B8h
1BCh
1C0h
1C4h
1C8h
1CCh
1D0h
1D4h
1D8h
1DCh
1E0h
1E4h
1E8h
1ECh
1F0h
1F4h
1F8h
1FCh
FBD2IBPGCTL
FBD2IBPATBUF
FBD2IBTXMSK
FBD2IBRXMSK
FBD2IBTXSHFT
FBD2IBRXSHFT
FBD2RXLNERR
FBD2IBRXPGCTL
FBD2IBPATBUF2
FBD2IBTXPAT2EN
FBD2IBRXPAT2EN
FBD2TS1PARM
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Register Description
Table 3-28. Device 22, Function 0: FB-DIMM 3 Intel IBIST Registers
200h
204h
208h
20Ch
210h
214h
218h
21Ch
220h
224h
228h
22Ch
230h
234h
238h
23Ch
240h
244h
248h
24Ch
250h
254h
258h
25Ch
260h
264h
268h
26Ch
270h
274h
278h
27Ch
FBD3IBPORTCTL
FBD3IBPGCTL
280h
284h
288h
28Ch
290h
294h
298h
29Ch
2A0h
2A4h
2A8h
2ACh
2B0h
2B4h
2B8h
2BCh
2C0h
2C4h
2C8h
2CCh
2D0h
2D4h
2D8h
2DCh
2E0h
2E4h
2E8h
2ECh
2F0h
2F4h
2F8h
2FCh
FBD3IBPATBUF
FBD3IBTXMSK
FBD3IBRXMSK
FBD3IBTXSHFT
FBD3IBRXSHFT
FBD3RXLNERR
FBD3IBRXPGCTL
FBD3IBPATBUF2
FBD3IBTXPAT2EN
FBD3IBRXPAT2EN
FBD3TS1PARM
3.8
Register Definitions
3.8.1
PCI Standard Registers
These registers appear in every function for every device.
3.8.1.1
VID - Vendor Identification Register
The VID Register contains the vendor identification number. This 16-bit register,
combined with the Device Identification Register uniquely identifies the manufacturer
of the function with in the MCH. Writes to this register have no effect.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3, 8, 9
Function:
Offset:
0
00h
Version:
Intel 5000P Chipset ,Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
00h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
00h
Version:
Intel 5000P Chipset
Device:
Function:
Offset:
16
0, 2
00h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
17
0
00h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
21
0
00h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
00h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:0
RO
8086h
Vendor Identification Number
The value assigned to Intel.
3.8.1.2
DID - Device Identification Register
This 16-bit register combined with the Vendor Identification register uniquely identifies
the Function with in the MCH. Writes to this register have no effect. See Table 3-3 for
the DID of each MCH function.
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73
Register Description
Device:
Function:
Offset:
0, 2-3, 8, 9
0
02h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
00h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
02h
Version:
Intel 5000P Chipset
Device:
Function:
Offset:
16
0, 2
02h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
17
0
02h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
21
0
02h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
020h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:0
RWO
*See
Table 3-2
Device Identification Number
Identifies each function of the MCH
3.8.1.3
RID - Revision Identification Register
This register contains the revision number of the MCH. The Revision ID (RID) is a
traditional 8-bit Read Only (RO) register located at offset 08h in the standard PCI
header of every PCI/PCI Express compatible device and function. Previously, a new
value for RID was assigned for Intel chipsets for every . There is a a need to provide an
alternative value for software compatibility when a particular driver or patch unique to
that stepping or an earlier stepping is required, for instance, to prevent Windows
software from flagging differences in RID during device enumeration. The solution is to
implement a mechanism to read one of two possible values from the RID register:
1. Stepping Revision ID (SRID): This is the default power on value for mask/metal
steppings.
2. Compatible Revision ID (CRID): The CRID functionality gives BIOS the flexibility
to load OS drivers optimized for a previous revision of the silicon instead of the
current revision of the silicon in order to reduce drivers updates and minimize
changes to the OS image for minor optimizations to the silicon for yield
improvement, or feature enhancement reasons that do not negatively impact the
OS driver functionality.
Reading the RID in the Intel 5000P Chipset MCH returns either the SRID or CRID
depending on the state of a register select flip-flop. Following reset, the register select
flip flop is reset and the SRID is returned when the RID is read at offset 08h. The SRID
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
value reflects the actual product stepping. To select the CRID value, BIOS/configuration
software writes a key value of 79h to Bus 0, Device 0, Function 0 (ESI port) of the Intel
5000P Chipset MCH’s RID register at offset 08h. This sets the SRID/CRID register
select flip-flop and causes the CRID to be returned when the RID is read at offset 08h.
The RID register in the ESI port (Bus 0 device 0 Function 0) is a “write-once” sticky
register and gets locked after the first write. This causes the CRID to be returned on all
subsequent RID register reads. Software should read and save all device SRID values
by reading Intel 5000P Chipset MCH device RID registers before setting the SRID/CRID
register select flip flop.
The RID values for all devices and functions in Intel 5000P Chipset MCH are controlled
by the SRID/CRID register select flip flop, thus writing the key value (79h) to the RID
register in Bus 0, Device 0, Function 0 sets all Intel 5000P Chipset MCH device RID
registers to return the CRID. Writing to the RID register of other devices has no effect
on the SRID/CRID register select flip-flop. Only a power good reset can change the RID
selection back to SRID.
Device:
Function:
Offset:
0, 2-3, 8, 9
0
08h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
08h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
08h
Version:
Intel 5000P Chipset
Device:
Function:
Offset:
16
0, 2
08h
Version:
Device:
Function:
Offset:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset,
17
0
08h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
21
0
08h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
08h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:4
if (DEV 0)
{RWOST}
else
{RO}
0h
Major Revision
1
Steppings which require all masks to be regenerated .
0000: A stepping for Intel 5000 Series Chipset with SF
0001: B stepping for Intel 5000 Series Chipset with SF
0010: C stepping for Intel 5000 Series Chipset with SF
endif
1000: A stepping with Intel 5000 Series Chipset without SF
1001: B Stepping with Intel 5000 Series Chipset without SF
1010: C Stepping with Intel 5000 Series Chipset without SF
Others: Reserved
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Register Description
Device:
Function:
Offset:
0, 2-3, 8, 9
0
08h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
08h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
08h
Version:
Intel 5000P Chipset
Device:
Function:
Offset:
16
0, 2
08h
Version:
Device:
Function:
Offset:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset,
17
0
08h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
21
0
08h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
08h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
3:0
if (DEV 0)
{RWOST}
else
{RO}
0h
Minor Revision
Incremented for each stepping which does not modify all masks. Reset for
each major revision.
0x0: M0 stepping
0x1: M1 stepping
0x2: M2 stepping
Others: Reserved
endif
Note: The Metal steppings indicated are a subset of the Major revision. For
example, an A stepping with M0 as minor revision typically means A0.
Notes:
1. Even though the contents of the RID have an attribute as “RO”, it is ultimately dictated by the comparator flop
(attribute “RWOST” in Device 0, function 0) that selects between the CRID/SRID outputs. The comparator is
set by BIOS/SW writing a specific value to offset 08h in dev0, fn 0 based on Figure 3-3.
3.8.1.3.1
3.8.1.3.2
Stepping Revision ID (SRID)
The SRID is a 4-bit hardwired value assigned by Intel, based on product’s stepping. The
SRID is not a directly addressable PCI register. The SRID value is reflected through the
RID register when appropriately addressed. The 4 bits of the SRID are reflected as the
two least significant bits of the major and minor revision field respectively. See
Figure 3-3
Compatible Revision ID (CRID)
The CRID is an 4-bit hardwired value assigned by Intel during manufacturing process.
Normally, the value assigned as the CRID will be identical to the SRID value of a
previous stepping of the product with which the new product is deemed “compatible”.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
The CRID is not a directly addressable PCI register. The CRID value is reflected through
the RID register when appropriately addressed.The 4 bits of the CRID are reflected as
the two least significant bits of the major and minor revision field respectively. See
Figure 3-3.
Figure 3-3. Intel 5000P Chipset MCH implementation of SRID and CRID Registers
7
6
5
4
3
2
1
0
Major Rev Id Minor Rev Id
3.8.1.4
CCR - Class Code Register
This register contains the Class Code for the device. Writes to this register have
no effect.
1
Device :0, 2-3, 9
Function:
Offset:
0
09h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
09h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
09h
Version:
Intel 5000P Chipset
Device:
Function:
Offset:
16
0, 2
09h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
17
0
09h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
21
0
09h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
09h
Version:
Intel 5000P Chipset
Bit
Attr
RO
Default
Description
23:16
06h
Base Class.
This field indicates the general device category. For the MCH, this field is hardwired
to 06h, indicating it is a “Bridge Device”.
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Register Description
1
Device :0, 2-3, 9
Function:
Offset:
0
09h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
09h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
09h
Version:
Intel 5000P Chipset
Device:
Function:
Offset:
16
0, 2
09h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
17
0
09h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
21
0
09h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
09h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:8
RO
if
Sub-Class.
(DEV2-7)
{04h}
This field qualifies the Base Class, providing a more detailed specification of the
device function.
else
{00h}
For PCI Express Devices 2,3,4,5,6,7 default is 040h, indicating “PCI to PCI Bridge”
For all other Devices: 0,9,10,12,14,16,17,18,19 default is 00h, indicating “Host
Bridge”. See footnote a, for DMA Engine device CCR.
7:0
RO
00h
Register-Level Programming Interface.
This field identifies a specific programming interface (if any), that device
independent software can use to interact with the device. There are no such
interfaces defined for “Host Bridge” types, and this field is hardwired to 00h.
Notes:
1. The DMA Engine CCR for device 8 is defined separately in Section 3.10.3.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.1.5
HDR - Header Type Register
This register identifies the header layout of the configuration space.
Device:
Function:
Offset:
0, 2-3, 8, 9
0
0Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
0Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
0Eh
Version:
Intel 5000P Chipset
Device:
Function:
Offset:
16
0, 2
0Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
17
0
0Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
21
0
0Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
0Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7
RO
if
Multi-function Device.
(DEV16)
{1h}
Selects whether this is a multi-function device, that may have alternative
configuration layouts. This bit is hardwired to ‘0’ for devices for the MCH with the
exception of device 16 fn 0-2, which it is set to ‘1’.
else
{0h}
endif
6:0
RO
Configuration Layout.
if
This field identifies the format of the configuration header layout for a PCI-to-PCI
bridge from bytes 10h through 3Fh.
(DEV2-7)
{01h}
else
{00h}
For PCI Express Devices 2,3,4,5,6,7 default is 01h, indicating “PCI to PCI Bridge”
For all other Devices: 0,8,9,16,17,21,22 default is 00h, indicating a conventional
type 00h PCI header
endif
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Register Description
3.8.1.6
SVID - Subsystem Vendor Identification Register
This register identifies the manufacturer of the system. This 16-bit register combined
with the Device Identification Register uniquely identify any PCI device. They appear in
every function except the PCI Express functions.
Device:
Function:
Offset:
0, 8
0
2Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
16
0, 2
2Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
17
0
2Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
21
0
2Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
2Ch
Version:
Intel 5000P Chipset
Bit
Attr Default
Description
15:0 RWO
8086h Vendor Identification Number.
The default value specifies Intel. Each byte of this register will be writable once.
Second and successive writes to a byte will have no effect.
A write to any of the above registers on the MCH will write to all of them.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.1.7
SID - Subsystem Identity
This register identifies the system. They appear in every function except the PCI
Express functions.
Device:
Function:
Offset:
0, 8
0
2Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
16
0, 2
2Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
17
0
2Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
21
0
2Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
2Eh
Version:
Intel 5000P Chipset
Bit
Attr
RWO
Default
Description
Subsystem Identification Number:
15:0
8086h
The default value specifies Intel. Each byte of this register will be writable once.
Second and successive writes to a byte will have no effect.
3.8.2
Address Mapping Registers
These registers control transaction routing to one of the three interface types (Memory,
PCI Express, or ESI) based on transaction addresses. The memory mapping registers in
this section are made read-only by the LT.LOCK-MEMCONFIG command. Routing to
particular ports of a given interface type are defined by the following registers:
Table 3-29. Address Mapping Registers
Interface
type
Address Routing Registers
Memory
MIR, AMIR, PAM, SMRAM, EXSMRC, EXSMRAMC, TOLM, EXSMRTOP, AMBASE, AMR
MBASE/MLIM (devices 2-7)
PCI Express
PMBASE/PMLIM (devices 2-7)
PMBU/PMBL (devices 2-7)
IOBASE/IOLIM (devices 2-7)
SBUSN,SUBUSN (devices 2-7)
BCTRL, HECBASE, PCICMD (devices 2-7)
1
ESI
Subtractive decode (device 0)
Notes:
1. Any request not falling in the above ranges will be subtractively decoded and sent to Intel 631xESB/632xESB
I/O Controller Hub via the ESI
The MCH allows programmable memory attributes on 13 Legacy memory segments of
various sizes in the 640 Kilobytes to 1 Megabytes address range. Seven Programmable
Attribute Map (PAM) Registers are used to support these features.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
81
Register Description
Each PAM Register controls one or two regions, typically 16 Kilobytes in size
3.8.2.1
PAM0 - Programmable Attribute Map Register 0
This register controls the read, write, and shadowing attributes of the BIOS area which
extends from 0F 0000h - 0F FFFFh.
Two bits are used to specify memory attributes for each memory segment. These bits
apply to both host accesses and PCI initiator accesses to the PAM areas. These
attributes are:
RE - Read Enable. When RE = 1, the CPU read accesses to the corresponding memory
segment are claimed by the MCH and directed to main memory. Conversely, when RE =
0, the host read accesses are directed to ESI (Intel 631xESB/632xESB I/O Controller
Hub) to be directed to the PCI bus.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding
memory segment are claimed by the MCH and directed to main memory. Conversely,
when WE = 0, the host write accesses are directed to ESI (Intel 631xESB/632xESB I/O
Controller Hub) to be directed to the PCI bus.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only.
Device:
Function:
Offset:
16
0
59h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
5:4
RV
00
00
Reserved
RW
ESIENABLE0: 0F0000-0FFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0F0000 to 0FFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
3:0
RV
0h
Reserved
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.2.2
3.8.2.3
®
PAM1 - Programmable Attribute Map Register 1
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0C 0000h-0C 7FFFh.
Device:
Function:
Offset:
16
0
5Ah
Version:
Intel 5000P Chipset, Intel 5000V Chipset
Bit
Attr
Default
Description
7:6
5:4
RV
00
00
Reserved
RW
ESIENABLE1: 0C4000-0C7FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C4000 to 0C7FFF
Bit5 = Write enable, Bit4 = Read enable.
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
3:2
1:0
RV
00
00
Reserved
RW
LOENABLE1: 0C0000-0C3FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C0000 to 0C3FFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
PAM2 - Programmable Attribute Map Register 2
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0C 8000h -0C FFFF h.
Device:
Function:
Offset:
16
0
5Bh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
5:4
RV
00
00
Reserved
RW
ESIENABLE2: 0CC000-0CFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0CC000-0CFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
3:2
RV
00
Reserved
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
83
Register Description
Device:
Function:
Offset:
16
0
5Bh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
1:0
RW
00
LOENABLE2: 0C8000-0CBFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0C8000-0CBFFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
3.8.2.4
PAM3 - Programmable Attribute Map Register 3
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0D 0000h - 0D 7FFFh.
Device:
Function:
Offset:
16
0
5Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
5:4
RV
00
00
Reserved
RW
ESIENABLE3: 0D 4000h - 0D 7FFFh Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0D 4000h -0D 7FFFh.
Bit5 = Write enable, Bit4 = Read enable.
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
3:2
1:0
RV
00
00
Reserved
RW
LOENABLE3: 0D 0000h - 0D 3FFFh Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0D 0000h -0D 3FFFh.
Bit1 = Write enable, Bit0 = Read enable
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
®
84
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.2.5
3.8.2.6
®
PAM4 - Programmable Attribute Map Registers 4
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0D 8000h - 0D FFFFh.
Device:
Function:
Offset:
16
0
5Dh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
5:4
RV
00
00
Reserved
RW
ESIENABLE4: 0DC000-0DFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0DC000-0DFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
3:2
1:0
RV
00
00
Reserved
RW
LOENABLE4: 0D8000-0DBFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0D8000-0DBFFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
PAM5 - Programmable Attribute Map Register 5
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0E 0000h -0E 7FFFh.
Device:
Function:
Offset:
16
0
5Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
5:4
RV
00
00
Reserved
RW
ESIENABLE5: 0E4000-0E7FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E4000-0E7FFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
3:2
RV
00
Reserved
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
85
Register Description
Device:
Function:
Offset:
16
0
5Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
1:0
RW
00
LOENABLE5: 0E0000-0E3FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E0000-0E3FFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
3.8.2.7
PAM6 - Programmable Attribute Map Register 6
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0E 8000h -0E FFFFh.
Device:
Function:
Offset:
16
0
5Fh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
5:4
RV
00
00
Reserved
RW
ESIENABLE6: 0EC000-0DFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0EC000-0DFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
3:2
1:0
RV
00
00
Reserved
RW
LOENABLE6: 0E8000-0EBFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E8000-0EBFFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding
Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
®
86
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.2.8
SMRAMC - System Management RAM Control Register
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when
EXSMRC.G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK
bit is set.
Device:
Function:
Offset:
16
0
61h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7
6
RV
0
0
Reserved
RWL
D_OPEN: SMM Space Open
When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even
when SMM decode is not active. This is intended to help BIOS initialize SMM
space. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at
the same time. This register can be locked by D_LCK.
5
4
RW
0
0
D_CLS: SMM Space Closed
When D_CLS = 1 SMM space DRAM is not accessible to data references, even
if SMM decode is active. Code references may still access SMM space DRAM.
This will allow SMM software to reference through SMM space to update the
display even when SMM is mapped over the VGA range. Software should
ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. Note that
the D_CLS bit only applies to Compatible SMM space.
RWL
D_LCK: SMM Space Locked
When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK, D_OPEN,
C_BASE_SEG, H_SMRAME, G_SMRAME, all LT.MSEG.BASE, all LT.MSEG.SIZE,
ESMMTOP, TSEG_SZ and T_EN become read only. D_LCK can be set to 1 via a
normal configuration space write but can only be cleared by a Full Reset. The
combination of D_LCK and D_OPEN provide convenience with security. The
BIOS can use the D_OPEN function to initialize SMM space and then use
D_LCK to “lock down” SMM space in the future so that no application software
(or BIOS itself) can violate the integrity of SMM space, even if the program
has knowledge of the D_OPEN function.
3
RV
RO
0
Reserved
2:0
010
C_BASE_SEG: Compatible SMM Space Base Segment
This field indicates the location of legacy SMM space. SMM DRAM is not
remapped. It is simply made visible if the conditions are right to access SMM
space, otherwise the access is forwarded to ESI/VGA. Since the MCH supports
only the SMM space between A 0000h and B FFFFh, this field is hardwired to
010.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
87
Register Description
3.8.2.9
EXSMRC - Extended System Management RAM Control Register
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MByte.
Device:
Function:
Offset:
16
0
62h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
H_SMRAME: Enable High SMRAM
7
RWL
0
Controls the SMM memory space location (that is, above 1 MByte or below 1
MByte) When G_SMRAME is 1 and H_SMRAME is set to 1, the high SMRAM
memory space is enabled. SMRAM accesses within the range FEDA_0000h to
FEDB FFFFh are remapped to DRAM addresses within the range 000A_0000h
to 000B_FFFFh. Once D_LCK has been set, this bit becomes read only.
6
5
RO
RV
0
0
MDAP: MDA Present
Since the MCH does not support MDA, this bit has no meaning.
Reserved
4
3
RV
0
0
Reserved
RWL
G_SMRAME: Global SMRAM Enable
If set to a 1, then Compatible SMRAM functions are enabled, providing 128 KB
of DRAM accessible at the A0000h address while in SMM (ADS# with SMM
decode). To enable Extended SMRAM function this bit has be set to 1. Refer to
the section on SMM for more details. Once D_LCK is set, this bit becomes read
only. (Moved from SMRAM bit3)
2:1
RWL
00
TSEG_SZ: TSEG Size
Selects the size of the TSEG memory block if enabled. Memory from
(ESMMTOP - TSEG_SZ) to ESMMTOP - 1 is partitioned away so that it may only
be accessed by the processor interface and only then when the SMM bit
(SMMEM#) is set in the request packet. Non-SMM accesses to this memory
region are sent to ESI when the TSEG memory block is enabled. Note that
once D_LCK is set, these bits become read only.
00: 512kB
01: 1MB
10: 2MB
11: 4MB
0
RWL
0
T_EN: TSEG Enable
Enabling of SMRAM memory for Extended SMRAM space only. When
G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the
appropriate physical address space. Note that once D_LCK is set, this bit
becomes read only.
3.8.2.10
EXSMRTOP - Extended System Management RAM Top Register
This register defines the location of the Extended (TSEG) SMM range by defining the
top of the TSEG SMM range (ESMMTOP).
Device:
Function:
Offset:
16
0
63h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:4
RV
0h
Reserved
®
88
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
16
Function:
Offset:
0
63h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
3:0
RWL
1h
ESMMTOP: Top of Extended SMM Space (TSEG)
This field contains the address that corresponds to address bits 31 to 28. This
field points to the top (+1) of extended SMM space below 4 GB. Addresses
below 4 GB (A[39:32] must be 0) that fall in this range are decoded to be in
the extended SMM space and should be routed according to Section 4.3.3:
ESMMTOP-TSEG_SZ <= Address < ESMMTOP
TSEG_SZ can be 512 KB, 1 MB, 2 MB, or 4 MB, depending on the value of
EXSMRC.TSEG_SZ.
ESMMTOP is relocatable to accommodate software that wishes to configure the
TSEG SMM space before MMIO space is known.
This field defaults to point to the same address as TOLM. Note that ESMMTOP
cannot be greater than TOLM otherwise the chipset will not function
deterministically.
Note that once D_LCK is set, this field becomes read only.
3.8.2.11
EXSMRAMC - Expansion System Management RAM Control Register
Device:
Function:
Offset:
16
2
60h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
E_SMERR: Invalid SMRAM Access
7
RWC
0
This bit is set when CPU has accessed the defined memory ranges in High SMM
Memory and Extended SMRAM (T-segment) while not in SMM space and with
the D-OPEN bit = 0. The MCH will set this bit if any In-Bound access from I/O
device targeting SMM range that gets routed to the ESI port (master abort).
Refer to Section 4.4.3 for details. The MCH will not set this bit when processor
does a cache line eviction (EWB or IWB) to SMM ranges regardless of
SMMEM# on FSB.
It is software's responsibility to clear this bit. The software must write a 1 to
this bit to clear it.
6:0
RV
0h
Reserved
Other address mapping registers such as BCTRL (VGAEN), MBASE/LIMIT, PMBASE/
LIMIT, and so forth, are included with the PCI Express registers described in this
chapter.
3.8.2.12
HECBASE - PCI Express Extended Configuration Base Address Register
This register defines the base address of the enhanced PCI Express configuration
memory.
Device:
Function:
Offset:
16
0
64h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:24
RV
0h
Reserved
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
89
Register Description
Device:
Function:
Offset:
16
0
64h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
23:12
RW
001h
HECBASE: PCI Express Extended Configuration Base
This register contains the address that corresponds to bits 39 to 28 of the base
address for PCI Express extended configuration space. Configuration software
will read this register to determine where the 256MB range of addresses
resides for this particular host bridge. This register defaults to the same
address as the default value for TOLM.
11:0
RV
0h
Reserved
3.8.3
AMB Memory Mapped Registers
The MCH supports four FB-DIMM channels. The MCH supports up to 16 FB-DIMM (each
with its Advanced Memory Buffer [AMB]) on four channels. Software needs to program
AMBPRESENT for each AMB on the platform. There are up to eight functions per AMB
component with 256 B of register space per function.
The MCH supports memory mapped register regions for software to access individual
AMB configuration registers. Memory mapped access to AMB register regions are
converted by the MCH to FB-DIMM channel command encodings subject to
AMBPRESENT register settings (see Section 3.9.23.11). This region is relocatable by
programming the AMBASE register. Software is required to program the AMR for the
size of AMB register regions. The size of this region is 128KB. It is mapped to each AMB
addressing slot in 2 KB blocks. If the corresponding AMBPRESENT bit is not set, then
MCH will not send configuration transaction to that AMB addressing slot.
To support SMBus and JTAG access using traditional PCI configuration mechanism, MCH
provides a “switching window” using a dedicated PCI device/function and AMBSELECT
register. AMBSELECT register can be programmed to select an AMB. Bus 0, device 9,
function 0 is mapped to the selected AMB’s configuration registers.
Access to bus 0, device 9, function 0 is limited to SMBus and JTAG only, FSB access to
this function will be mastered aborted by MCH as non-existent PCI function. AMB
register spaces are accessible through the SMBus by the programming of the
AMBSELECT Function_Select field. This field is used select one of the AMB 8
register spaces.
3.8.3.1
AMBASE: AMB Memory Mapped Register Region Base Register
Device:
Function:
Offset:
16
0
48h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
63:40 RV
39:17 RW
0h
007F00h
Reserved
AMBASE:
This marks the 128KB memory-mapped registers region used for
accessing AMB registers. It can be placed as MMIO region within the
physical limits of the system. Since the MCH uses only 40-bit
addressable space, hence only bits 39:17 are valid. The default base
address is at: 0xFE00_0000. This field could be relocated by software.
16:0
RV
0h
Reserved
®
90
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.3.2
AMR - AMB Memory Mapped Registers Region Range Register
Device:
Function:
Offset:
16
0
50h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
RW
Default
Description
31:0
0002_0000h AMBASE_Region_Size:
The size of AMB memory mapped register region in bytes. For MCH, the value
is 128 KB: 2 KB per AMB for a total of 16 AMB per channel, 32 KB per FB-DIMM
channel for a total of four channels.
3.8.3.3
AMBSELECT - AMB Switching Window Select Register
Device:
Function:
Offset:
16
0
54h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
0h
Description
15:9
8:7
RV
Reserved
RW
0h
0h
0h
Channel_Select:
Specify the FB-DIMM channel being accessed via bus 0, device 9, function 0 for
SM Bus and JTAG only.
6:3
2:0
RW
RW
AMB_Select:
Specify the AMB slot being accessed via bus 0, device 9, function 0 for SM Bus
and JTAG only.
Function_Select:
Specify the function being accessed via bus 0, device 9, function 0 for SM Bus
and JTAG only.
3.8.3.4
MAXCH - Maximum Channel Number Register
Device:
Function:
Offset:
16
0
56h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset,
Bit
Attr
Default
Description
7:0
RO
04h
Maximum_number_channels:
Set by hardware to indicate the maximum number of FB-DIMM channels that
MCH supports.
3.8.3.5
MAXDIMMPERCH - Maximum DIMM PER Channel Number Register
This register controls the maximum number of AMB DIMMs per FB-DIMM channel that
MCH supports for AMB configuration register access. This register applies only to DIMM
modules in the FB-DIMM channel, that is, those AMB with DS[3:0] encoding from 0h
to 7h.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
91
Register Description
Device:
Function:
Offset:
16
0
57h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:0
RO
04h
Maximum_number_DIMM_per_channel:
Set by hardware to indicate the maximum number of FB-DIMM AMBs per
channel that the MCH supports.
3.8.3.6
Map to AMB Registers
In Table 3-30, each 2 KB range is mapped to individual AMB registers by address
translation of MCH. The address of this relocatable register area is specified in the
AMBASE register. Configuration transactions targeting these ranges are converted to
FB-DIMM commands by the MCH and sent to the FB-DIMM channel subject to
AMBPRESENT register settings.
The AMB register’s PCI function (3 bits) and offset (8 bits) are used as the offset (11
bits) from the base of each 2 KB range for the specific AMB register space.
Table 3-30. Register Offsets in AMB Memory Mapped Registers Region (Sheet 1 of 2)
7FFh-0h
map to channel_0, AMB_0 registers
map to channel_0, AMB_1 registers
map to channel_0, AMB_2 registers
map to channel_0, AMB_3 registers
map to channel_0, AMB_4 registers
map to channel_0, AMB_5 registers
map to channel_0, AMB_6 registers
map to channel_0, AMB_7 registers
map to channel_0, AMB_8 registers
map to channel_0, AMB_9 registers
map to channel_0, AMB_A registers
map to channel_0, AMB_B registers
map to channel_0, AMB_C registers
map to channel_0, AMB_D registers
map to channel_0, AMB_E registers
map to channel_0, AMB_F registers
map to channel_1, AMB_0 registers
map to channel_1, AMB_1 registers
map to channel_1, AMB_2 registers
map to channel_1, AMB_3 registers
map to channel_1, AMB_4 registers
map to channel_1, AMB_5 registers
map to channel_1, AMB_6 registers
map to channel_1, AMB_7 registers
map to channel_1, AMB_8 registers
map to channel_1, AMB_9 registers
map to channel_1, AMB_A registers
map to channel_1, AMB_B registers
map to channel_1, AMB_C registers
map to channel_1, AMB_D registers
FFFh-800h
17FFh-1000h
1FFFh-1800h
27FFh-2000h
2FFFh-2800h
37FFh-3000h
3FFFh-3800h
47FFh-4000h
4FFFh-4800h
57FFh-5000h
5FFFh-5800h
67FFh-6000h
6FFFh-6800h
77FFh-7000h
7FFFh-7800h
87FFh-8000h
8FFFh-8800h
97FFh-9000h
9FFFh-9800h
A7FFh-A000h
AFFFh-A800h
B7FFh-B000h
BFFFh-B800h
C7FFh-C000h
CFFFh-C800h
D7FFh-D000h
DFFFh-D800h
E7FFh-E000h
EFFFh-E800h
®
92
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-30. Register Offsets in AMB Memory Mapped Registers Region (Sheet 2 of 2)
F7FFh-F000h
map to channel_1, AMB_E registers
map to channel_1, AMB_F registers
map to channel_2, AMB_0 registers
map to channel_2, AMB_1 registers
map to channel_2, AMB_2 registers
map to channel_2, AMB_3 registers
map to channel_2, AMB_4 registers
map to channel_2, AMB_5 registers
map to channel_2, AMB_6 registers
map to channel_2, AMB_7 registers
map to channel_2, AMB_8 registers
map to channel_2, AMB_9 registers
map to channel_2, AMB_A registers
map to channel_2, AMB_B registers
map to channel_2, AMB_C registers
map to channel_2, AMB_D registers
map to channel_2, AMB_E registers
map to channel_2, AMB_F registers
map to channel_3, AMB_0 registers
map to channel_3, AMB_1 registers
map to channel_3, AMB_2 registers
map to channel_3, AMB_3 registers
map to channel_3, AMB_4 registers
map to channel_3, AMB_5 registers
map to channel_3, AMB_6 registers
map to channel_3, AMB_7 registers
map to channel_3, AMB_8 registers
map to channel_3, AMB_9 registers
map to channel_3, AMB_A registers
map to channel_3, AMB_B registers
map to channel_3, AMB_C registers
map to channel_3, AMB_D registers
map to channel_3, AMB_E registers
map to channel_3, AMB_F registers
FFFFh-F800h
107FFh-10000h
10FFFh-10800h
117FFh-11000h
11FFFh-11800h
127FFh-12000h
12FFFh-12800h
137FFh-13000h
13FFFh-13800h
147FFh-14000h
14FFFh-14800h
157FFh-15000h
15FFFh-15800h
167FFh-16000h
16FFFh-16800h
177FFh-17000h
17FFFh-17800h
187FFh-18000h
18FFFh-18800h
197FFh-19000h
19FFFh-19800h
1A7FFh-1A000h
1AFFFh-1A800h
1B7FFh-1B000h
1BFFFh-1B800h
1C7FFh-1C000h
1CFFFh-1C800h
1D7FFh-1D000h
1DFFFh-1D800h
1E7FFh-1E000h
1EFFFh-1E800h
1F7FFh-1F000h
1FFFFh-1F800h
3.8.4
Interrupt Redirection Registers
3.8.4.1
REDIRCTL - Redirection Control Register
This register controls the priority algorithm of the XTPR interrupt redirection
mechanism.
.
Device:
Function:
Offset:
16
0
6Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:14
13
RV
RV
RV
0
0
0
Reserved
Reserved
Reserved
12
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
93
Register Description
Device:
Function:
Offset:
16
0
6Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
11:8
RW
0h
BUCKET2: First priority number not in BUCKET0, BUCKET1, or
BUCKET2.
Must be programmed with a larger value than BUCKET1. A suggested value
is Ch.
7:4
3:0
RW
RW
0h
0h
BUCKET1: First priority number not in BUCKET0 or BUCKET1.
Must be programmed with a larger value than BUCKET0. A suggested
value is 8h.
BUCKET0: First priority number not in BUCKET0. A suggested value is 0h.
3.8.4.2
REDIRBUCKETS - Redirection Bucket Number Register
This register allows software to read the current hardware bucket number assigned to
each XTPR register.
.
Device:
Function:
Offset:
16
0
68h
Version:
Intel 5000P Chipset, Intel 5000V Chipset
Bit
Attr
Default
Description
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BUCKET15: Redirection bucket number for XTPR[15].
BUCKET14: Redirection bucket number for XTPR[14].
BUCKET13: Redirection bucket number for XTPR[13].
BUCKET12: Redirection bucket number for XTPR[12].
BUCKET11: Redirection bucket number for XTPR[11].
BUCKET10: Redirection bucket number for XTPR[10].
BUCKET9: Redirection bucket number for XTPR[9].
BUCKET8: Redirection bucket number for XTPR[8].
BUCKET7: Redirection bucket number for XTPR[7].
BUCKET6: Redirection bucket number for XTPR[6].
BUCKET5: Redirection bucket number for XTPR[5].
BUCKET4: Redirection bucket number for XTPR[4].
BUCKET3: Redirection bucket number for XTPR[3].
BUCKET2: Redirection bucket number for XTPR[2].
BUCKET1: Redirection bucket number for XTPR[1].
BUCKET0: Redirection bucket number for XTPR[0].
7:6
5:4
3:2
1:0
3.8.5
Boot and Reset Registers
3.8.5.1
SYRE - System Reset Register
This register controls MCH reset behavior. Any resets produced by a write to this
register must be delayed until the configuration write is completed on the initiating
interface (PCI Express, ESI, processor bus, SMBus, JTAG).
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
There is no “SOFT RESET” bit in this register. That function is invoked through the ESI.
There are no CORE:FBD gear ratio definitions in this register. Those are located in the
DDRFRQ register.
Device:
Function:
Offset:
16
0
40h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
SAVCFG: Preserve Configuration
15
RW
0
When this bit is set, MCH configuration register contents (except for this bit)
are not cleared by hard reset. As this bit is cleared by reset, software must
set it after each reset if this behavior is desired for the next reset. If this bit
is set, BOFL will not be cleared by reset. Software should use the Boot Flag
Reset bit to re-enable the BOFL mechanism.
14
RW
0
CPURST: Processor Reset
If set, the MCH will assert processor RESET# on both buses as soon as the
MCH has no pending transactions. The chipset will then deassert RESET#
following the timing rules described in the Reset Chapter.
The MCH does not have any mechanism to drain transactions before effecting
the CPU RESET#. It is the responsibility of software to ensure that the
system is quiet before sending the configuration write (last command) to set
this field in the MCH in order to drive the CPU RESET# signal. Any violation of
this usage pattern would render the system unstable and potentially
catastrophic.
13
RV
0
CPUBIST: Processor Built-In-Self-Test
If set, A[3]# is asserted during Power-On-Configuration (POC), and the
processor will run BIST before engaging processor bus protocol.
12:11
10
RV
0
0
Reserved1
ROST
S3: S3 Sleep State
The MCH sets this bit when it sends an Ack-S3 message to the ESI port.
The MCH clears this bit after it has placed appropriate FB-DIMM channels into
the FB-DIMM.Calibrate state in response to deassertion of the RESETI#
signal.
9
8
RW
0
0
ROR: Processor Reset on Refresh
If set, the MCH will assert processor RESET# on both busses when a refresh
cycle completes.
RWST
BNR_INDP_BINIT_MODE: BNR independent of BINIT Mode
0: The Chipset associates BNR with BINIT and for CPUs that do NOT follow
the “BNR independent of BINIT” feature set.
1: Enables the Chipset to use the “BNR independent of BINIT” feature set. i.e
no dependency is required between BNR and BINIT.
Refer to the BNR#, BINIT# sampling rules in the Intel® Pentium® 4 and
Intel® Xeon® Processor External Hardware Specification, Rev 2.5,
Ref#14035
7:0
RV
0h
Reserved
3.8.5.2
CPURSTCAPTMR: CPU Reset Done Cap Latency Timer
This register implements the cap latency method for the CPU_RST_DONE/
CPU_RST_DONE_ACK using a 12-bit variable timer.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
95
Register Description
Device:
16
Function: 0
Offset:
Bit
42h
Attr
Default
Description
15:12
11:0
RV
0h
Reserved
RWST
7FFh
DCRT: ESI CPU Reset Done Ack Determinism Timer
This field provides the determinism timer threshold for the Intel 5000P
Chipset MCH for handling the CPU_RESET_DONE/CPU_RESET_DONE_ACK
message before deasserting the CPU_RESET#. It uses this 12-bit counter to
schedule the CPU_RESET_DONE message on the DMI and then waits for the
CPU_RESET_DONE_ACK message to come back and waits for the timer
expiry before deasserting CPU_RESET#.
Cap_latency = Max(CPU_RST_DONE_ACK_round trip_latency, DCRT).
It is expected that the DCRT field is set larger than the expected round trip
latency. This provides the necessary leeway for absorbing clock
synchronization, jitter, deskew and other variations that will affect the
determinism on the DMI port. Hence the data is always sent back only after
the expiry of the DCRT field at the heartbeat boundary.
It is sticky through reset to permit to allow different types of BIOS flows that
may require a hard reset of the Intel 5000P Chipset MCH.
Maximum value is 4095 core clocks
A default of 2047 clocks (7FFh) is used.
3.8.5.3
POC - Power-On Configuration Register
Contrary to its name, this register defines configuration values driven at reset. At
power-on, no bits in this register are active as PWRGOOD clears them all. This register
only activates configuration on subsequent resets.
The MCH drives the contents of this register on A[35:4]# whenever it asserts processor
RESET#. These values are driven during processor RESET# assertion, and for two host
clocks past the trailing edge of processor RESET#.
This register is sticky through reset; that is, the contents of the register remain
unchanged during and following a Hard Reset. This allows system configuration
software to modify the default values and reset the system to pass those values to all
host bus devices.
The POC bits do not affect MCH operation except for driving A[35:4]#.
Read after write to POC register will read updated value but the architectural behavior
will not be affected until hard-reset deassertion. A warm reset (CPU reset) will not
cause the contents of the POC register to be altered.
There are other power-on configuration bits in the SYRE register.
Device:
Function:
Offset:
16
0
44h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:28
27
RV
0h
0
Reserved
RWST
MTDIS: Disable Multi-Threading
If set, A[31]# is asserted, and the processor will disable Multi-threading.
26:12
RV
0h
Reserved
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
16
Function:
Offset:
0
44h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
11
RWST
1
BUSPARK: Request Bus Parking Disable
If set, A[15]# is asserted and the processor may not park on the system
bus. Default is to disable busparking
10:0
RV
0h
Reserved
3.8.5.4
SPAD[3:0] - Scratch Pad Registers
These scratch pad registers each provide 32 read/writable bits that can be used by
software. They are also aliased to fixed memory addresses.
Device:
Function:
Offset:
16
0
DCh, D8h, D4h, D0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset
Bit
Attr
RW
Default
Description
31:0
00000000h Scratch Pad value. These bits have no effect on the hardware.
3.8.5.5
SPADS[3:0] - Sticky Scratch Pad
These sticky scratch pad registers each provide 32 read/writable bits that can be used
by software. They are also aliased to fixed memory addresses.
Device:
Function:
Offset:
16
0
ECh, E8h, E4h, E0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:0
RWST
00000000h Scratch Pad value. These sticky bits have no effect on the hardware.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
97
Register Description
3.8.5.6
BOFL[3:0] - Boot Flag Register
These registers can be used to select the system boot strap processor or for other cross
processor communication purposes. When this register is read, the contents of the
register is cleared. Therefore, a processor that reads a non-zero value owns the
semaphore. Any value can be written to this register at any time.
An example of usage would be for all processors to read the register. The first one that
gets a non-zero value owns the semaphore. Since the read clears the value of the
register, all other processors will see a zero value and will spin until they receive further
notification. After the winning processor is done, it writes a non-zero value of its choice
into the register, arming it for subsequent uses. These registers are also aliased to fixed
memory I/O addresses.
Device:
Function:
Offset:
16
0
C0h, C4h, C8h, CCh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:0
RCW
A5A5A5A5h SemaVal: Semaphore Value
Can be written to any value. Value is cleared when there is a read.
3.8.6
Control and Interrupt Registers
3.8.6.1
PROCENABLE: Processor Enable Global Control
The two FSBEN bits are used to enable or disable frontside bus arbitration. When
frontside bus arbitration is disabled the processor is effectively disabled.
Device:
16
Function: 0
Offset:
Bit
F0h
Attr
Default
Description
31:5
4:3
RV
3fAh
11
Reserved.
RWST
FSBEN: FSB1 and FSB0 Enable
The field is defined as the following:
00: reserved
01: FSB1 is disabled. FSB0 is enabled.
10: FSB1 is enabled. FSB0 is disabled.
11: FSB1 is enabled. FSB0 is enabled. (default)
Hard-reset is needed after changing value in this register.
2
RWST
0
SFBYPASS: Snoop Filter Bypass
0: SF is enabled
1: SF is disabled
Note: The output of the fuse “SF CHOP” is gated appropriately with this
register field viz. SFBYPASS for further internal decoding by Intel 5000X
Chipset MCH. The fuse has overriding effect.
1:0
RV
0h
Reserved.
3.8.6.2
FSBS[1:0] - Processor Bus Status Register
This register holds status from the Processor Busses.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
16
Function:
Offset:
0
7Ch, 74h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:2
1
RV
RO
0h
0
Reserved.
2SOCKET: 2 Sockets present on this FSB
Set when Intel 5000P Chipset MCH has seen Ab[22] asserted, indicating there
are more than 1 processors present on this FSB.
0
RO
0
2CORE: 2 Cores present
Set when Intel 5000P Chipset MCH has seen Ab[30] asserted, indicating there
is more than 1 core in a processor.
Note: Mixing single core with dual-core processors will be recognized as dual-
core processor on this FSB.
3.8.6.3
XTPR[7:0] - External Task Priority Register
These registers control redirectable interrupt priority for xAPIC agents connected to the
MCH. Up to four agents on each bus are supported. These agents may be two dual core
processors each with two threads or four single core processors. The xAPIC
architecture provides for lowest priority delivery through interrupt redirection by the
MCH. If the redirectable “hint bit” is set in the xAPIC message, the chipset may redirect
the interrupt to another agent. Redirection of interrupts can be applied to both I/O
interrupts and IPIs.
Each register contains the following fields:
1. Agent priority (Task Priority)
2. APIC enable bit (TPR Enable)
3. Logical APIC ID (LOGID)
4. Processor physical APIC ID (PHYSID)
The XTPR registers are modified by a front side bus xTPR_Update transaction. In
addition, the XTPR registers can be modified by software.
Table 3-31. XTPR Index
Index
Value
3
2
1
0
0 for FSB0, 1 for FSB1
Ab[29]
Ab[30] OR Ab[22]
Ab[21]
These registers are used for lowest priority delivery through interrupt redirection by the
chipset.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
99
Register Description
Device:
Function:
Offset:
16
0
BCh, B8h, B4h, B0h, ACh, A8h, A4h, A0h, 9Ch, 98h, 94h, 90h, 8Ch, 88h, 84h, 80h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Version:
Bit
Attr
Default
Description
31
if (XTPR0)
{RW}
else {RV}
endif
0
CLUSTER: Global Cluster Mode (XTPR[0] only)
Used in interrupt redirection for lowest priority delivery. Updated by every
xTPR_Update transaction on either bus (Aa[3]).
0: flat
Note: Cluster Mode not Supported
30:24
23
RV
00h
0
Reserved.
RW
TPREN: TPR Enable
This bit reflects the value of Ab[31]#. When Ab[31]# is asserted, the value
of this bit will be 0.
22:20
19:16
RV
0h
0h
Reserved.
RW
PRIORITY: Task Priority
The processor with the lowest enabled value will be assigned the
redirectable interrupt. This field is updated with Ab[27:24] of the
xTPR_Update transaction.
15:8
7:0
RW
RW
0h
0h
PHYSID: Physical APIC ID
The physical ID of the APIC agent associated with the XTPR entry. This field
is updated with Aa[19:12] of the xTPR_Update transaction.
LOGID: Logical APIC ID
The logical ID of the APIC agent associated with the XTPR entry. This field
is updated with Aa[11:4] of the xTPR_Update transaction.
3.8.7
PCI Express Device Configuration Registers
This section describes the registers associated with the PCI Express Interface.
The PCI Express register structure is exposed to the operating system and requires a
separate device per port. Ports 2-7 will be assigned devices 2 through 7 while Port 0 is
the ESI interconnect to the Intel 631xESB/632xESB I/O Controller Hub. The PCI
Express ports determine at reset the maximum width of the devices to which they are
connected through link training. All ports will be made visible to OS even if
unconnected. If Ports are combined to form larger widths (for example, x8 or x16 from
a x4 link), then the unused ports will Master Abort (reads return all ones, writes
dropped) any accesses to it. Note that configuration accesses to the unconnected port
will still be allowed to permit device remapping, hot-plug and so forth.
Table 3-32. When will an Intel 5000X Chipset PCI Express* Device be Accessible?
PCI
Express
Port
Device
x16
Registers may be accessed if:
7
6
5
4
3
2
0
7
6
5
4
3
2
0
High Performance
Graphics Port
Port 4 is connected to x16 device
Possible
Combination
Port3 is connected to a 4x device
Port2 is connected to a x4 or x8 device
ESI - Not
combinable
Port0 is connected to a x4 ESB2 port through ESI and cannot be
combined with any other port
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Figure 3-4 illustrates how each PCI Express port’s configuration space appears to
software. Each PCI Express port’s configuration space has four regions:
• Standard PCI Header - This region closely resembles a standard PCI-to-PCI
bridge header.
• PCI Device Dependent Region - The region is also part of standard PCI
configuration space and contains the PCI capability structures. For the Intel 5000P
Chipset MCH, the supported capabilities are:
— Message Signalled Interrupts
— Hot-plug
— PCI Express Capability
• PCI Express Extended Configuration Space - This space is an enhancement
beyond standard PCI and only accessible with PCI Express aware software. The
MCH supports the Enhanced Error Signalling capability.
• Capability Working Register Sets - These ranges are indirectly accessed
through Data and Select registers in the capability structures. For the MCH,
working register sets exist for the Standard hot-plug Controller and Power
Management capabilities.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
101
Register Description
Figure 3-4. PCI Express Configuration Space
0xFFF
Intel® 5000P
Chipset Advanced Error
Reporting
0x140
0x100
PCI-Express Advanced
Error Reporting
PCI-Express Capability
MSI Capability
PM Capability
0x40
0x00
CAP_PTR
P2P
Figure 3-3 shows the configuration register offset addresses for each of the PCI
Express ports as defined in the PCI Express Base Specification, Revision 1.0a. It is also
compatible with the standard PCI 2.3 capability structure and comprises of a linked list
where each capability has a pointer to the next capability in the list. For PCI Express
extended capabilities, the first structure is required to start at 0x100 offset.
3.8.8
PCI Express Header
The following registers define the standard PCI 2.3 compatible and extended PCI
Express configuration space for each of the PCI Express x4 links in the MCH. Unless
otherwise specified, the registers are enumerated as a vector [2:7] mapping to each of
the six PCI Express ports uniquely while the ESI port is referred by index 0.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.8.1
PCICMD[7:2, 0]- Command Register
This register defines the PCI 2.3 compatible command register values applicable to PCI
Express space.
Device:
Function:
Offset:
0, 2-3
0
04h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
04h
Version: Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
04h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:11
10
RV
0h
0
Reserved. (by PCI SIG)
RW
INTxDisable: Interrupt Disable
Controls the ability of the PCI Express port to generate INTx messages.
This bit does not affect the ability of the GNB to route interrupt messages
received at the PCI Express port. However, this bit controls the generation
of legacy interrupts to the DMI for PCI Express errors detected internally in
this port (for example, Malformed TLP, CRC error, completion time out, and
so forth) or when receiving root port error messages or interrupts due to
HP/PM events generated in legacy mode within the Intel 5000P Chipset
MCH. Refer to the INTP register in Section 3.8.8.27, “INTP[7:2,0] -
Interrupt Pin Register” on page 119 for interrupt routing to DMI.
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
9
8
RO
0
0
FB2B: Fast Back-to-Back Enable
Not applicable to PCI Express and is hardwired to 0
RW
SERRE: SERR Message Enable
his field handles the reporting of fatal and non-fatal errors by enabling the
error pins ERR[2:0].
1: The GNB is enabled to send fatal/non-fatal errors.
0: TheGNB is disabled from generating fatal/non-fatal errors.
The errors are also enabled by the PEXDEVCTRL register in
Section 3.8.11.4.
In addition, for Type 1 configuration space header devices, for example,
Virtual P2P bridge), this bit, when set, enables transmission of
1
ERR_NONFATAL and ERR_FATAL error messages forwarded from the PCI
Express interface. This bit does not affect the transmission of forwarded
ERR_COR messages. Refer to the Intel 5000P Chipset MCH RAS Error
Model.
7
6
RO
0
0
IDSELWCC: IDSEL Stepping/Wait Cycle Control
Not applicable to PCI Express. Hardwired to 0.
RW
PERRE: Parity Error Response Enable
When set, this field enables parity checking.
5
4
3
RO
RO
RO
0
0
0
VGAPSE: VGA palette snoop Enable
Not applicable to PCI Express. Hardwired to 0.
MWIEN: Memory Write and Invalidate Enable
Not applicable to PCI Express. Hardwired to 0.
SCE: Special Cycle Enable
Not applicable to PCI Express. Hardwired to 0.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
103
Register Description
Device:
Function:
Offset:
0, 2-3
0
04h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
04h
Version: Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
04h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
2
RW
0
BME: Bus Master Enable
Controls the ability of the PCI Express port to forward memory or I/O
transactions.
1: Enables the PCI Express port to successfully complete the memory or I/
O read/write requests.
0: The Bus Master is disabled. The MCH will treat upstream memory writes/
reads, I/O writes/reads, and MSIs as illegal cycles and return Unsupported
Request Status (equivalent to Master abort) in PCI Express
When the BME is disabled, the MCH will treat upstream memory writes/
reads, I/O writes/reads, and MSIs as illegal cycles and return Unsupported
Request Status (equivalent to Master abort) in PCI Express
Requests other than inbound memory or I/O (for example, configuration,
outbound) are not controlled by this bit.
The BME is typically used by the system software for operations such as
hot-plug, device configuration.
When the CPURESET# signal is asserted during a power good or hard reset
and after the DMI completes its training, the LPC device in the Intel
631xESB/632xESB I/O Controller Hub (or other NIC/SIO4 cards could
potentially send inbound requests even before the CPURESET# is
deassserted. This corner case is handled by the BME filtration in the Intel
5000P Chipset MCH’s PCI Express port using the above rules since BME is
reset. However, in general, it is illegal for a an I/O device to issue inbound
requests until the CPURESET# has been deasserted to prevent any possible
malfunction in the Intel 5000P Chipset MCH logic.
1
if (port
7-2)
{RW}
elseif
(port 0)
{RO}
endif
0
MSE: Memory Space Enable
Controls the bridge’s response as a target to memory accesses on the
primary interface that address a device that resides behind the bridge in
both the non-prefetchable and prefetchable memory ranges (high/low) or
targets a memory-mapped location within the bridge itself
1: Enables the Memory and Prefetchable memory address ranges (MMIO)
defined in the MBASE/MLIM, PMBASE/PMLIM, PMBU/PMLU registers.
0: Disables the entire memory space seen by the PCI Express port on the
primary side (MCH). Requests will then be subtractively claimed by Intel
631xESB/632xESB I/O Controller Hub. For port 0, this bit is hardwired to 0
since the ESI is not a P2P bridge.
0
if (port
7-2)
{RW}
elseif
0
IOAE: Access Enable
1: Enables the I/O address range defined in the IOBASE and IOLIM
registers.
(port 0)
{RO}
endif
0: Disables the entire I/O space seen by the PCI Express port on the
primary. Requests will be then be subtractively claimed by Intel 631xESB/
632xESB I/O Controller Hub.
For port 0, this bit is hardwired to 0 since the ESI is not a P2P bridge.
Notes:
1. In addition, BCCTRL.BCSERRE also gates the transmission of ERR_FATAL, NON_FATAL and ERR_COR messages
received from the PCI Express interface. See Section 3.8.8.28.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.8.2
PCISTS[7:2, 0] - Status Register
The PCISTS is a 16-bit status register that reports the occurrence of error conditions
associated with the primary side of the “virtual” PCI-PCI bridge embedded in the
selected PCI Express cluster of the MCH.
Device:
Function:
Offset:
0, 2-3
0
06h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
06h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
06h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15
RWC
0
DPE: Detected Parity Error
This bit is set when the PCI Express port receives an uncorrectable data error
or Address/Control parity errors regardless of the Parity Error Response
Enable bit (PERRE). This applies only to parity errors that target the PCI
Express port interface (inbound/outbound direction). The detected parity error
maps to B1, F6, M2 and M4 (uncorrectable data error from FSB, Memory or
internal sources) of the Intel 5000P Chipset MCH.
14
13
RWC
RWC
0
0
SSE: Signaled System Error
1: The PCI Express port generated internal FATAL/NON FATAL errors (IO0-
IO17) through the ERR[2:0] pins with SERRE bit enabled. Software clears this
bit by writing a ‘1’ to it.
0: No internal PCI Express port errors are signaled.
RMA: Received Master Abort
This bit is set when a requestor (primary side for Type 1 header configuration
space header device) receives a completion with Unsupported Request
Completion Status.
1: Assert this RMA bit when the primary side performs operations for an
unsupported transaction. These apply to inbound configs, I/O accesses, locks,
bogus memory reads and any other request that is master aborted internally.
These are terminated on the PCI Express link with a UR completion status, but
only if a completion is required. Software clears this bit by writing a 1 to it.
PEXDEVSTS.URD is set and UNCERRSTS[20].IO2Err is set in addition.
0: No Master Abort is generated
12
RWC
0
RTA: Received Target Abort
This bit is set when a requestor (primary side for Type 1 header configuration
space header device) receives a completion with Completer Abort Completion
Status. For example, for supported requests that cannot be completed
because of address decoding problems or other errors. These are terminated
on the PCI Express link with a CA completion status, but only if a completion is
required. Software clears this bit by writing a 1 to it.
11
RO
RO
0
STA: Signaled Target Abort
Target Abort does not exist on the primary side of the PCI Express port.
Hardwired to 0.
10:9
0h
DEVSELT: DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
105
Register Description
Device:
Function:
Offset:
0, 2-3
0
06h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
06h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
06h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
8
RWC
0
MDPERR: Master Data Parity Error
This bit is set by the PCI Express port if the Parity Error Response Enable bit
(PERRE) is set and it receives error B1, F2, F6, M2 and M4 (uncorrectable
data error or Address/Control parity errors or an internal failure). If the Parity
Error Enable bit (PERRE) is cleared, this bit is never set.
7
RO
0
FB2B: Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
6
5
RV
RO
0
0
Reserved. (by PCI SIG)
66MHZCAP: 66 MHz capable.
Not applicable to PCI Express. Hardwired to 0.
4
3
RO
RO
1
0
CAPL: Capabilities List
This bit indicates the presence of PCI Express capabilities list structure in the
PCI Express port. Hardwired to 1. (Mandatory)
INTxSTAT: INTx Status
Indicates that an INTx interrupt message is pending internally in the PCI
Express port.
The INTx status bit should be rescinded when all the relevant events via RAS
errors/HP/PM internal to the port that requires legacy interrupts are cleared by
software.
2:0
RV
0h
Reserved. (by PCI SIG)
3.8.8.3
CLS[7:2, 0] - Cache Line Size
This register contains the Cache Line Size and is set by BIOS/Operating system. It does
not affect the PCI Express port functionality in the MCH.
®
106
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3, 0
Function:
Offset:
0
0Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
0Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
0Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RW
00h
CLS: Cache Line Size
This is an 8-bit value that indicates the size of the cache line and is specified in
DWORDs. It does not affect the MCH.
3.8.8.4
PRI_LT[7:2, 0] - Primary Latency Timer
This register denotes the maximum time slice for a burst transaction in legacy PCI 2.3
on the primary interface. It does not affect/influence PCI Express functionality.
Device:
Function:
Offset:
0, 2-3
0
0Dh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
0Dh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
0Dh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
00h
Prim_Lat_timer: Primary Latency Timer
Not applicable to PCI Express. Hardwired to 00h.
3.8.8.5
BIST[7:2,0] - Built-In Self Test
This register is used for reporting control and status information of BIST checks within
a PCI Express port. It is not supported in the Intel 5000P Chipset MCH.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
107
Register Description
Device:
Function:
Offset:
0, 3-2
0
0Fh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
0Fh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
7-4
0
0Fh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
00h
BIST_TST: BIST Tests
Not supported. Hardwired to 00h
3.8.8.6
BAR0[7:2,0] - Base Address Register 0
Base address registers are used for mapping internal registers to an MMIO or I/O
space. It does not affect the MCH. The base address register 0 is not supported/defined
in the PCI Express port of the MCH.
3.8.8.7
3.8.8.8
BAR1[7:2,0] - Base Address Register 1
The base address register 1 is not supported/defined in the MCH.
EXP_ROM[0]: Expansion ROM Registers
The ESI port (device 0, function 0) does not implement any Base address registers in
the Intel 5000P Chipset MCH from offset 10h to 24h. Similarly no Expansion ROM base
address register is defined in offset 30h. Also no Cardbus CIS pointer is defined in
offset 28h. The MIN_GNT (offset 3Eh) and MAX_LAT (3Fh) registers are also not
implemented as they are not applicable to the ESI interface.
3.8.8.9
PBUSN[7:2] - Primary Bus Number
This register identifies the bus number on the on the primary side (MCH) of the PCI
Express port.
®
108
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
2-3
Function:
Offset:
0
18h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
18h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
18h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
00h
PBUBSNUM: Primary Bus Number
Configuration software typically programs this field with the number of the bus
on the primary side of the bridge. Since the PCI Express virtual PCI-PCI bridge
is an internal device and its primary bus is consistently 0, these bits are read
only and are hardwired to 0.
3.8.8.10
SBUSN[7:2] - Secondary Bus Number
This register identifies the bus number assigned to the secondary side (PCI Express) of
the “virtual” PCI-PCI bridge. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to devices connected to PCI Express.
Device:2-3
Function:
Offset:
0
19h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
19h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
19h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RW
00h
SECBUSNUM: Secondary Bus Number
This field is programmed by configuration software with the lowest bus number
of the busses connected to PCI Express. Since both bus 0, device 1 and the
PCI to PCI bridge on the other end are considered by configuration software to
be PCI-PCI bridges, this bus number will consistently correspond to the bus
number assigned to the PCI Express port.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
109
Register Description
3.8.8.11
SUBUSN[7:2] - Subordinate Bus Number
This register identifies the subordinate bus (if any) that resides at the level below the
secondary PCI Express interface. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to devices subordinate to the
secondary PCI Express port.
Device:
Function:
Offset:
2-3
0
1Ah
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
1Ah
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
1Ah
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RW
00h
SUBBUSNUM: Subordinate Bus Number
This register is programmed by configuration software with the number of the
highest subordinate bus that is behind the PCI Express port.
3.8.8.12
SEC_LT[7:2] - Secondary Latency Timer
This register denotes the maximum time slice for a burst transaction in legacy PCI 2.3
on the secondary interface. It does not affect/influence PCI Express functionality.
Device:
Function:
Offset:
2-3
0
1Bh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
1Bh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
1Bh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
00h
Slat_tmr: Secondary Latency Timer
Not applicable to PCI Express. Hardwired to 00h.
3.8.8.13
IOBASE[7:2] - I/O Base Register
The I/O Base and I/O Limit registers (see Section 3.8.8.14) define an address range
that is used by the PCI Express port to determine when to forward I/O transactions
from one interface to the other using the following formula:
IO_BASE <= A[15:12]<=IO_LIMIT
®
110
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Only the upper 4 bits are programmable. For the purpose of address decode, address
bits A[11:0] are treated as 0. The bottom of the defined I/O address range will be
aligned to a 4 KB boundary while the top of the region specified by IO_LIMIT will be one
less than a 4 KB multiple. Refer to Section 4.5.1 and Section 4.5.3 in the Intel 5000P
Chipset Platform Specification.
Device:
Function:
Offset:
2-3
0
1Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
1Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
1Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:4
RW
0h
IOBASE: I/O Base Address
Corresponds to A[15:12] of the I/O addresses at the PCI Express port.
3:0
RO
0h
IOCAP: I/O Address capability
0h – 16 bit I/O addressing, (supported)
1h – 32 bit I/O addressing,
Others - Reserved.
The MCH does not support 32 bit addressing, so these bits are hardwired to 0.
3.8.8.14
IOLIM[7:2] - I/O Limit Register
The I/O Base and I/O Limit registers define an address range that is used by the PCI
Express bridge to determine when to forward I/O transactions from one interface to the
other using the following formula:
IO_BASE <= A[15:12] <=IO_LIMIT
Only the upper 4 bits of this register are programmable. For the purpose of address
decode, address bits A[11:0] of the I/O limit register is treated as FFFh.
Device:
Function:
Offset:
2-3
0
1Dh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
1Dh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
1Dh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:4
RW
0h
IOLIMIT: I/O Address Limit
Corresponds to A[15:12] of the I/O addresses at the PCI Express port.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
111
Register Description
Device:
Function:
Offset:
2-3
0
1Dh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
1Dh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
1Dh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
3:0
RO
0h
IOLCAP: I/O Address Limit Capability
0h – 16 bit I/O addressing, (supported)
1h – 32 bit I/O addressing,
others - Reserved.
The MCH does not support 32 bit I/O addressing, so these bits are hardwired to
0.
3.8.8.15
SECSTS[7:2] - Secondary Status
SECSTS is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (that is, PCI Express side) of the “virtual” PCI-PCI
bridge embedded within MCH.
K
Device:
Function:
Offset:
2-3
0
1Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
1Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
1Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15
RWC
0
SDPE: Detected Parity Error
This bit is set by the Intel 5000P Chipset MCH whenever it receives a poisoned
TLP in the PCI Express port regardless of the state the Parity Error Response
bit (in the BCTRL.PRSPEN register).
BCTRL.PRSPEN register). This corresponds to IO4 as defined in Table 5-31,
“Intel 5000X chipset Error List” on page 388.
14
13
RWC
RWC
0
0
SRSE: Received System Error
This bit is set by the MCH when it receives a ERR_FATAL or ERR_NONFATAL
message. Section 3.8.8.28. (Note that BCTRL.BCSERRE is not a gating item
for the recording of this error on the secondary side).
SRMAS: Received Master Abort Status
This bit is set when the PCI Express port receives a Completion with
“Unsupported Request Completion” Status.
®
112
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
2-3
Function:
Offset:
0
1Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
1Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
1Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
12
RWC
0
SRTAS: Received Target Abort Status
This bit is set when the PCI Express port receives a Completion with
“Completer Abort” Status.
11
RWC
0
SSTAS: Signaled Target Abort
This bit is set when the PCI Express port completes a request with “Completer
Abort” Status when the PEXSTS.RTA is set since the MCH acts as a virtual
PCI bridge and passes the completion abort from the primary to the secondary
side.
Note however that the MCH will not set the SSTAS field directly on the
secondary side since all requests are passed upstream through the primary
side to the internal core logic for decoding.
10:9
8
RO
00
0
SDEVT: DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0
RWC
SMDPERR: Master Data Parity Error
This bit is set by the PCI Express port on the secondary side (PCI Express
link) if the Parity Error Response Enable bit (PRSPEN) in the Section 3.8.8.28
is set and either of the following two conditions occurs:
•The PCI Express port receives a Completion marked poisoned
•The PCI Express port poisons a write Request
If the Parity Error Response Enable bit is cleared, this bit is never set. Refer to
Table 3-33 for details on the data parity error handling matrix in the Intel 5000P
Chipset MCH.
7
RO
0
SFB2BTC: Fast Back-to-Back Transactions Capable
Not applicable to PCI Express. Hardwired to 0.
6
5
RV
RO
0
0
Reserved. (by PCI SIG)
S66MHCAP: 66 MHz capability
Not applicable to PCI Express. Hardwired to 0.
4:0
RV
0h
Reserved. (by PCI SIG)
Table 3-33. Intel 5000P Chipset MCH PCISTS and SECSTS Master/Data Parity Error RAS
Handling
Register Name
OB Post OB Compl IN Post
IB Compl
PCISTS[15].DPE1
PCISTS[8].MDPERR
SECSTS[15].SDPE
SECSTS[8].SMDPERR
yes
no
no
no
yes
yes
no
no
no
no
no
yes
no
yes
yes
no
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
113
Register Description
Notes:
1. In general, the DPE field is the superset of the MDPERR from a virtual PCI-PCI bridge perspective
but there may be cases where a PCISTS[8].MDPERR may not be logged in the PCISTS[15].DPE
field in the Intel 5000P Chipset MCH on the primary side.
3.8.8.16
MBASE[7:2] - Memory Base
The Memory Base and Memory Limit registers define a memory mapped I/O non-
prefetchable address range (32-bit addresses) and the MCH directs accesses in this
range to the PCI Express port based on the following formula:
MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT
The upper 12 bits of both the Memory Base and Memory Limit registers are read/write
and corresponds to the upper 12 address bits, AD[31:20], of 32-bit addresses. For the
purpose of address decoding, the bridge assumes that the lower 20 address bits,
AD[19:0], of the memory base address are zero. Similarly, the bridge assumes that the
lower 20 address bits, AD[19:0], of the memory limit address (not implemented in the
Memory Limit register) are FFFFFh. Thus, the bottom of the defined memory address
range will be aligned to a 1 MB boundary and the top of the defined memory address
range will be one less than a 1 MB boundary. Refer to Section 4.3.9, Section 4.4.2 and
Section 4.4.3 in the Intel 5000P Chipset programmer’s guide for further details on
address mapping.
Device:
Function:
Offset:
2-3
0
20h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
20h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
20h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:4
RW
0h
MBASE: Memory Base Address
Corresponds to A[31:20] of the memory address on the PCI Express port.
3:0
RO
0h
Reserved. (by PCI SIG)
3.8.8.17
MLIM[7:2]: Memory Limit
This register controls the processor to PCI Express non-prefetchable memory access
routing based on the following formula as described above:
MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh.
®
114
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Memory range covered by MBASE and MLIM registers, are used to map non-
prefetchable PCI Express address ranges (typically where control/status memory-
mapped I/O data structures reside) and PMBASE and PMLIM are used to map
prefetchable address ranges. This segregation allows application of USWC space
attribute to be performed in a true plug-and-play manner to the prefetchable address
range for improved PCI Express memory access performance.
Note also that configuration software is responsible for programming all address range
registers such as MIR, MLIM, MBASE, IOLIM, IOBASE, PMBASE, PMLIM, PMBU, PMLU
(coherent, MMIO, prefetchable, non-prefetchable, I/O) with the values that provide
exclusive address ranges, that is, prevent overlap with each other and/or with the
ranges covered with the main memory. There is no provision in the MCH hardware to
enforce prevention of overlap and operations of the system in the case of overlap are
not guaranteed.
Device:
Function:
Offset:
2-3
0
22h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
22h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
22h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:4
RW
0h
MLIMIT: Memory Limit Address
Corresponds to A[31:20] of the memory address that corresponds to the upper
limit of the range of memory accesses that will be passed by the PCI Express
bridge
3:0
RO
0h
Reserved. (by PCI SIG)
3.8.8.18
PMBASE[7:2] - Prefetchable Memory Base
The Prefetchable Memory Base and Memory Limit registers define a memory mapped
I/O prefetchable address range (32-bit addresses) which is used by the PCI Express
bridge to determine when to forward memory transactions based on the
following formula:
PREFETCH_MEMORY_BASE <= A[31:20] <= PREFETCH_MEMORY_LIMIT
The upper 12 bits of both the Prefetchable Memory Base and Memory Limit registers
are read/write and corresponds to the upper 12 address bits, A[31:20], of 32-bit
addresses. For the purpose of address decoding, the bridge assumes that the lower 20
address bits, A[19:0], of the memory base address are zero. Similarly, the bridge
assumes that the lower 20 address bits, A[19:0], of the memory limit address (not
implemented in the Memory Limit register) are F FFFFh. Thus, the bottom of the
defined memory address range will be aligned to a 1 MB boundary and the top of the
defined memory address range will be one less than a 1 MB boundary.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
115
Register Description
Device:
Function:
Offset:
2-3
0
24h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
24h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
24h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:4
RW
0h
PMBASE: Prefetchable Memory Base Address
Corresponds to A[31:20] of the prefetchable memory address on the PCI
Express port.
3:0
RO
1h
PMBASE_CAP: Prefetchable Memory Base Address Capability
0h – 32 bit Prefetchable Memory addressing
1h – 64bit Prefetchable Memory addressing,
others - Reserved.
The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory
Limit registers are read-only, contain the same value, and encode whether or not the
bridge supports 64-bit addresses. If these four bits have the value 0h, then the bridge
supports only 32 bit addresses. If these four bits have the value 01h, then the bridge
supports 64-bit addresses and the Prefetchable Base Upper 32 bits and Prefetchable
Limit Upper 32 bits registers hold the rest of the 64-bit prefetchable base and limit
addresses respectively.
3.8.8.19
PMLIM[7:2] - Prefetchable Memory Limit
This register controls the processor to PCI Express prefetchable memory access routing
based on the following formula as described above:
PREFETCH_MEMORY_BASE <= A[31:20] <= PREFTCH_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. This register must be initialized by the
configuration software. For the purpose of address decode address bits A[19:0] are
assumed to be F FFFFh.
Device:
Function:
Offset:
2-3
0
26h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
26h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:4
RW
0h
PMLIMIT: Prefetchable Memory Limit Address
Corresponds to A[31:20] of the memory address on the PCI Express bridge
®
116
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
2-3
Function:
Offset:
0
26h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
26h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
3:0
RO
1h
PMLIMIT_CAP: Prefetchable Memory Limit Address Capability
0h – 32 bit Prefetchable Memory addressing
1h – 64 bit Prefetchable Memory addressing,
others - Reserved.
3.8.8.20
PMBU[7:2] - Prefetchable Memory Base (Upper 32 bits)
The Prefetchable Base Upper 32 bits and Prefetchable Limit Upper 32 bits registers are
extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers.
If the Prefetchable Memory Base and Prefetchable Memory Limit registers indicate
support for 32-bit addressing, then the Prefetchable Base Upper 32 bits and
Prefetchable Limit Upper 32 bits registers should return zero when read. If the
Prefetchable Memory Base and Prefetchable Memory Limit registers indicate support for
64-bit addressing, then the Prefetchable Base Upper 32 bits and Prefetchable Limit
Upper 32 bits registers are implemented as read/write registers.
If a 64-bit prefetchable memory address range is supported, the Prefetchable Base
Upper 32 bits and Prefetchable Limit Upper 32 bits registers specify the upper 32 bits,
corresponding to A[63:32], of the 64-bit base and limit addresses which specify the
prefetchable memory address range.
Device:
Function:
Offset:
2-3
0
28h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
28h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
28h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:0
RW
0h
PUMBASE: Prefetchable Upper 32-bit Memory Base Address
Corresponds to A[63:32] of the memory address that maps to the upper base
of the prefetchable range of memory accesses that will be passed by the PCI
Express bridge. OS should program these bits based on the available physical
limits of the system.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
117
Register Description
3.8.8.21
PMLU[7:2] - Prefetchable Memory Limit (Upper 32 bits)
Device:
Function:
Offset:
2-3
0
2Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
2Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
2Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:0
RW
0h
PUMLIM: Prefetchable Upper 32-bit Memory Limit Address
Corresponds to A[63:32] of the memory address that maps to the upper limit of
the prefetchable range of memory accesses that will be passed by the PCI
Express bridge. OS should program these bits based on the available physical
limits of the system.
3.8.8.22
3.8.8.23
3.8.8.24
IOB[7:2] - I/O Base Register (Upper 16 bits)
Not used since MCH does not support upper 16-bit I/O addressing.
IOL[7:2] - I/O Limit Register (Upper 16 bits)
Not used since MCH does not support upper 16-bit I/O addressing.
CAPPTR[7:2, 0]- Capability Pointer
The CAPPTR is used to point to a linked list of additional capabilities implemented by
this device.
It provides the offset to the first set of capabilities registers located in the PCI
compatible space from 40h. Currently the first structure is located 50h to provide room
for other registers.
Device:
Function:
Offset:
0, 2-3
0
34h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
34h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
34h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
50h
CAPPTR: Capability Pointer
Points to the first capability structure (PM) in PCI 2.3 compatible space at 50h
®
118
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.8.25
3.8.8.26
RBAR[7:2] - ROM Base Address Register
Not implemented in MCH, since the MCH is a virtual PCI-PCI bridge.
INTL[7:2,0] - Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between the initialization code and the device driver. The MCH does not have a
dedicated interrupt line. This register RO and is provided for backwards compatibility.
Device:
Function:
Offset:
0, 2-3
0
3Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
3Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
3Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
00h
INTL: Interrupt Line
BIOS writes the interrupt routing information to this register to indicate which
input of the interrupt controller this PCI Express Port is connected to. Not used
in MCH since the PCI Express port does not have interrupt lines.
3.8.8.27
INTP[7:2,0] - Interrupt Pin Register
The INTP register identifies legacy interrupts for INTA, INTB, INTC and INTD as
determined by BIOS/firmware. These are emulated over the ESI port using the
appropriate Assert_Intx commands.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
119
Register Description
Device:
Function:
Offset:
0, 2-3
0
3Dh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
3Dh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
3Dh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RWO
01h
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI Express port.
001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
BIOS/configuration Software has the ability to program this register once
during boot to set up the correct interrupt for the port.
3.8.8.28
BCTRL[7:2] - Bridge Control Register
This register provides extensions to the PCICMD register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (that is, PCI
Express) as well as some bits that affect the overall behavior of the “virtual”
PCI-PCI bridge embedded within the MCH, for example, VGA compatible address
range mapping.
Device:
Function:
Offset:
2-3
0
3Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
3Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
3Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:12
11
RV
RO
0h
0
Reserved. (by PCI SIG)
DTSS: Discard Timer SERR Status
Not applicable to PCI Express. This bit is hardwired to 0.
10
9
RO
RO
0
0
DTS: Discard Timer Status
Not applicable to PCI Express. This bit is hardwired to 0.
SDT: Secondary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
®
120
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
2-3
Function:
Offset:
0
3Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
3Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
3Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
8
RO
0
PDT: Primary Discard Timer
Not applicable to PCI Express. This bit is hardwired to 0.
7
6
RO
0
0
FB2BEN: Fast Back-to-Back Enable
Not applicable to PCI Express. This bit is hardwired to 0.
RW
SBUSRESET: Secondary Bus Reset
1: Setting this bit causes a hot reset on the link for the corresponding PCI
Express port and the PCI Express hierarchy domain subordinate to the port.
This sends the LTSSM into the Hot-Reset state, which necessarily implies a
reset to the downstream device and all subordinate devices.
The mechanism to reset the downstream device is utilizing the TS1/TS2 “link
reset” bit (bit number 0 of symbol 5). It is recommended for software/BIOS
that the SBUSRESET field be held asserted for a minimum of 2 ms to ensure
that the Link enters the Hot-Reset state from L0 or L1/L2.
Software can also poll the PEXLNKSTS.LNKTRG bit for a deasserted condition
to determine if the hot-reset state has been entered at which point it can clear
the SBUSRESET field to train the link.
When this SBUSRESET bit is cleared after the MCH enters the “hot-reset”
state, the Intel 5000P Chipset MCH will initiate operations to move to “detect”
state and then train the link (polling, configuration, L0 (link-up)) after sending
at least 2 TS1 and receiving 1 TS1 with the HotReset bit set in the training
control field of TS1 and waiting for 2ms in the Hot-reset state. The 2ms stay in
the Hot-reset state is enforced by the chipset LTSSM for the PCI Express
hierarchy to reset.
If the SBUSRESET is held asserted even after the 2ms time-out has expired,
the Intel 5000P Chipset MCH will continue to maintain the hot-reset state.
Hence it is necessary for software to clear this register appropriately to bring
the link back in training.
Note also that a secondary bus reset will not in general reset the primary side
configuration registers of the targeted PCI Express port. This is necessary to
allow software to specify special training configuration, such as entry into
loopback mode.
0: No reset happens on the PCI Express port.
5
4
RO
0
0
MAMODE: Master Abort Mode
Not applicable to PCI Express. This bit is hardwired to 0.
RW
VGA16bdecode: VGA 16-bit decode
This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of
VGA I/O address precluding the decoding of alias addresses every 1 KB. The
I/O addresses decoded is in the range of 03B0h to 03BBh or 03C0h to 03DFh
within the first 1KB I/O space.
0: execute 10-bit address decodes on VGA I/O accesses.
1: execute 16-bit address decodes on VGA I/O accesses.
This bit only has meaning if bit 3 (VGAEN) of this register is also set to 1,
enabling VGA I/O decoding and forwarding by the bridge.
This read/write bit enables system configuration software to select between
10- and 16-bit I/O address decoding for all VGA I/O register accesses that are
forwarded from the primary to secondary whenever the VGAEN is set to 1.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
121
Register Description
Device:
Function:
Offset:
2-3
0
3Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
3Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
3Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
3
RW
0
VGAEN: VGA Enable
Controls the routing of CPU initiated transactions targeting VGA compatible I/
O and memory address ranges. This bit may only be set for one PCI Express
port.
2
RW
0
ISAEN: ISA Enable
Modifies the response by the Intel 5000P Chipset MCH to an I/O access issued
by the CPU that target ISA I/O addresses. This applies only to I/O addresses
that are enabled by the IOBASE and IOLIM registers.
1: The Intel 5000P Chipset MCH will not forward to PCI Express any I/O
transactions addressing the last 768 bytes in each 1KB block even if the
addresses are within the range defined by the IOBASE and IOLIM registers.
See Section 4.5.2. Instead of going to PCI Express these cycles will be
forwarded to ESI where they can be subtractively or positively claimed by the
ISA bridge.
0: All addresses defined by the IOBASE and IOLIM for CPU I/O transactions
will be mapped to PCI Express.
1
RW
0
BCSERRE: SERR Enable
This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
messages from the PCI Express port to the primary side.
1: Enables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL
messages.
0: Disables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL.
Note that BCSERRE is no longer a gating item for the recording of the
SESCSTS.SRSE error.
0
RW
0
PRSPEN: Parity Error Response Enable
This bit controls the response to poisoned TLPs in the PCI Express port
1: Enables reporting of poisoned TLP errors.
0: Disables reporting of poisoned TLP errors
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122
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.8.29
PEXLWSTPCTRL: PCI Express Link Width Strap Control Register
This register provides the ability to change the PCI Express link width through software
control. Normally, the Intel 5000P Chipset MCH will use the PEWIDTH[3:0] pins to train
the links. However, if BIOS needs the ability to circumvent the pin strappings and
enforce a specific setting for a given platform, it must perform a soft initialization
sequence through the following actions in this register:
1. Set PEXLWSTPCTRL.LWOEN to ‘1’.
2. Write the desired link width to PEXLWSTPCTRL.GPMNXT0(1) fields for IOU0 and
IOU1 clusters.
3. Perform a hard reset to the Intel 5000P Chipset MCH.
The chipset will then use the values initialized in the PEXLWSTPCTRL.GPMNXT0(1)
fields and train the links appropriately following the hard reset. The Intel 5000P Chipset
MCH will also provide status information to the software as to what link width it is
currently using to train the link via PEXLWSTPCTRL.GPMCUR0(1) fields and the
appropriate training mode, PEXLWSTPCTRL.LWTM. (pins strap vs. software
enabled mode).
Device:
0
Function: 0
Offset:
Bit
40h
Attr
Default
Description
15:14 RV
13:11 RO
0h
Reserved
000
GPMCUR1: IOU1 max width Current Configuration Now (ports 4-7)
This field is updated by the hardware to indicate the current link width of IOU1
ports that is used for training. This field is set before training gets underway.
000: x4,x4,x4,x4
001: x8,--,x4,x4
010: x4,x4, x8,--
011: x8,--,x8,--
100: x16,--,--,--,--
others: Reserved
10:8
RO
000
GPMCUR0: IOU0 max width Current Configuration (ports 2-3 only, port 0,
ESI, is always x4)
This field is updated by the hardware to indicate the current link width of IOU1
ports that is used for training. This field is set before training gets underway.
000: x4,x4
001: Reserved
010: x8,--
Others: Reserved
7
RO
0
LWTM: Link Width Training Mode
This field is updated by the hardware to provide feedback to software on the
training mode it is using following reset. That is, link strap or soft initialization of
link widths.
0: IOU clusters trained the links using the PEWIDTH[3:0] pins (external strapping)
[default]
1: IOU clusters trained the links using the soft initialization mechanism in this
register viz. GPMNXT1 and GPMNXT0 following a hard reset.
6:4
RWST 000
GPMNXT1: IOU1 max width Configuration Next (ports 4-7)
The IOU1 cluster will use this field to train the link after a hard reset provided
LWOEN is set.
Refer to Table 3.8.8.30, “PEXCTRL[7,2:0]: PCI EXPRESS Control Register” on
page 126.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
123
Register Description
Device:
0
Function: 0
Offset:
40h
Attr
RWST 000
Bit
Default
Description
3:1
GPMNXT0: IOU0 max width Configuration Next (ports 2-3)
The IOU0 cluster will use this field to train the links after a hard reset provided
LWOEN is set.
Refer to Table 3.8.8.30, “PEXCTRL[7,2:0]: PCI EXPRESS Control Register” on
page 126
0
RWST
0
LWOEN: Link Width override Enable
0: Disables software from setting the PCI Express link width through this register
and the Link width is controlled by the external pins PEWIDTH[3:0]. (default).
1. Enables BIOS/Software to set the required link width through this register. When
this bit is set, the IOU cluster will ignore the external pin strap (PEWIDTH[3:0] and
use the described table for configuring the link width. The values will take effect
after a hard reset.
®
124
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-1.
GIO Port Mode Selection
GIO Port (IOU0)
GIO Port (IOU1)
GPMNXT1
[2:0]
(IOU0)
GPMNXT0
[2:0]
(IOU1)
Port0
(ESI) (RSVD)
Port1
Port2
Port3
Port4
Port5
Port6
Port7
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
x4
RSVD
RSVD
x4
x4
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
x4
x4
x4
x4
x4
invalid
x4
x8
N/A
x4
x4
x8
N/A
x4
x8
N/A
N/A
N/A
invalid
invalid
invalid
invalid
x4
x8
N/A
N/A
x8
x16
invalid
invalid
RSVD
N/A
RSVD
RSVD
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
125
Register Description
3.8.8.30
PEXCTRL[7,2:0]: PCI EXPRESS Control Register
Device:
7-2,0
Function: 0
Offset:
48h
Bit
Attr
RW
Default
0h
Description
31:26
25:24
Reserved
RW
00
COALESCE_MODE: Used to increase the amount of combining for
completions.
00: No restriction on coalescing_hint. The IOU will try to maximize
completion combining. Since Intel 5000P Chipset MCH issues requests
in order, it does not make sense to restrict the coalesce hint because
there are few resources available at the time of fetch. By the time the hint
is used, resources could be freed up and reused for the following
requests.
Note: This mode of “00” is the preferred setting for Intel 5000P
Chipset MCH if COALESCE_EN=1 for software/BIOS
01: #CPL_ENTRIES_FREE will restrict coalesce_hint
10: if set then #PF_PEND will restrict coalesce hint
11: Minimum of coalesce_hint obtained from settings “01” and “10”
23
RW
0
TIMEOUT_ENABLE_CFG: Timeout enable for configuration
transactions
1: Config transactions can time out.
0: Config transactions cannot time out.
Suggested value: 0
Note: In general, configuration timeouts on the PCI-Express port
should not be enabled. This is necessary to permit slow devices
nested deep in the PCI hierarchy that may take longer to
complete requests than the maximum timeout specified in the
Intel 5000P. Software/BIOS should set this field based on the
context and usage/platform configuration. For e.g. compliance
testing with a known broken card should have this field set.
Note: For the configuration timeout to take effect, (due to Intel 5000P
RTL implementation) the PEXCTRL.TIMEOUT_ENABLE (bit 22)
has to be set.
Note: Due to recently discovered RTL bug in B3 and later stepping, the
IOU will log a completion error (IO6) for any outstanding
configuration transaction that crosses the counter limit even if
this register field is cleared or bit 22 of this register is cleared
(Example, either timeout is disabled. However, it does not affect
the functionality and the config transaction will be outstanding
indefinitely until the completion is returned except for the
unnecessary error log. Software should be aware of this
limitation when the field is cleared.)
22
RW
0
TIMEOUT_ENABLE: Timeout enable for non-configuration
transactions
1: Non config transactions can time out.
0: Non config transactions cannot time out.
Suggested value: 1
Note: When both TIMEOUT_ENABLE_CFG and TIMEOUT_ENABLE fields
are set to 0, the Intel 5000P will assume an infinite completion
time for the respective transactions. Hence the system is
dependent on the end device returning the completion response
at some point in time, else it will result in a hang.
Note: Due to recently discovered RTL bug in B3 and later stepping, the
IOU will log a completion error (IO6) for any outstanding
configuration transaction that crosses the counter limit even if
this register field is cleared or bit 22 of this register is cleared
(Example, either timeout is disabled. However, it does not affect
the functionality and the config transaction will be outstanding
indefinitely until the completion is returned except for the
unnecessary error log. Software should be aware of this
limitation when the field is cleared.)
®
126
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
7-2,0
Function: 0
Offset:
48h
Bit
Attr
Default
Description
21
RW
0
MALTLP_EN:
1: Check for certain malformed TLP types.
0: Do not check for certain malformed TLP types.
Suggested value: 1
When this bit is set, it enables the following conditions to mark a packet
as malformed:
•
4DW header MEM_RD or MEM_WR and the address is less than 32
bits (address[39:32] = 0)
•
Byte enable check for mem/io/cfg requests. Length > 1 DW and
(first dword byte enables = 0 or last dword byte enables = 0) Length
= 1 DW and last dword byte enables != 0
•
•
IO{rd,wr}/cfg{rd,wr}{0,1} and (traffic class != 0 or attributes != 0
or length != 1)
A configuration retry completion response (CRS) received for a non-
cfg outbound request
20:13
12
RV
0h
0
Reserved
RW
Max_rdcmp_lmt_EN: Maximum Read completion combining limit
Enable
1: Up to 256 B return and COALESCE_EN = 1.
0: Up to 128 B return if COALESCE_EN = 1
Note: It is strongly recommended that this field should not be set to 1
(256 B completion combining) due an MCH B2 silicon issue, especially
when MPS is configured to 256 B.
11
RW
0
COALESCE_FORCE: Force coalescing of accesses.
When 1, forces Intel 5000P Chipset MCH to wait for all coalescable data
before sending the transaction as opposed to forwarding as much as
possible.
0: Normal operation
1: wait to coalesce data
Note: It is strongly recommended that COALESCE_FORCE should not be
set to ‘1’ due to an MCH B2 silicon erratum.
10
RW
RW
0
0
COALESCE_EN: Read completion coalescing enable
When 1, enables read return of >64 B.
1: Returns of >64 B enabled. (See Max_rdcmp_lmt_EN above).
0: Returns are 64 B or less.
NOTE: For optimal read completion combining, this field should be set to
‘1’ along with Max_rdcmp_lmt_EN as ‘0’ for 128B completion
combining.
9
PMEGPEEN: PME GPE Enable
1: Enables “assert_pmegpe” (deassert_pmegpe) messages to be sent
over the DMI from the root complex for PM interrupts.
0: Disables “assert_pmegpe” (deassert_pmegpe) messages for PM
events to the root complex.
This has an overriding effect to generate ACPI PM interrupts over
traditional interrupts (MSI/intx).
8
RW
0
HPGPEEN: Hotplug GPE Enable
1: Enables “assert_hpgpe” (deassert_hpgpe) messages to be sent from
the root complex for Hot-plug events.
0: Disables “assert_hpgpe” (deassert_hpgpe) messages for Hot-plug
events from the root complex.
This has an overriding effect to generate ACPI HP events over traditional
interrupts.
7
RV
1
Reserved
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
127
Register Description
Device:
7-2,0
Function: 0
Offset:
48h
Bit
Attr
Default
Description
6:3
RW
0000
VPP: Virtual Pin Port
[6:4] = SMBus Address, [3] =IO Port
defines the 8-bit IO port that is used for routing power, attention,
Hotplug, presence, MRL and other events defined in Section 3.8.11.10.
2
RW
1
DIS_VPP: Disable VPP
The Intel 5000P Chipset MCH will use this bit to decide whether the VPP
is valid or not for the given PCI Express port as set by configuration
software. For example, to distinguish HP events for a legacy card or PCI
Express port module, this bit can be used.
1: VPP is disabled for this PCI Express port.
0: VPP is enabled for this PCI Express port.
Default value is to disable vpp for the PCI Express port
1
RW
0
DIS_APIC_EOI; Disable APIC EOI
The Intel 5000X MCH will use this bit to decide whether end of interrupts
(EOI) need to be sent to an APIC controller/bridge (for example, Intel
6700PXH 64 bit PCI Hub) through this PCI Express device.
1: no EOIs are sent (disabled).
0: EOIs are dispatched to the APIC Controller.
Note: In the case of slave (secondary) ports, the BIOS has to disable
EOI for that port by setting this register field. For example, x8
device connected on port 2-3 should have the
PEXCTRL.DIS_APIC_EOI of the slave port (viz. #3) set to
prevent EOIs from causing deadlocks. This is a micro-
architectural requirement due to the internal handshake
between IOU-CE for EOI slave handling.
0
if (port 7-
2) {RWO}
elsif (port
0) {RV}
endif
0
DEVHIDE: Device_hide
The device hide bit is used to enable the Intel 5000X MCH to hide the PCI
Express device from the Operating system and is applicable only to ports
7-2. Typically, an external I/O processor acts as its proxy by configuring it
and claiming resources on behalf of it and then unhides. The hiding is
done by changing the class code (CCR register) for this port to 0x0600.
This will prevent the OS from attempting to probe or modify anything
related to this device.
1: The PCI Express port CCR register has a value of 0600.
0: The PCI Express port CCR register has a value of 0604 (bridge)
The default value is ‘0’ (to make the device a bridge).
The device hide bit does not apply to the DMI interface (port 0) and has
no effect on its operation.
This 32-bit register implements chipset specific operations for general control/
accessibility such as device hiding, selective configuration cycles and interrupt signaling
®
128
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.8.31
PEXCTRL2[7:2,0]: PCI Express Control Register 2
This is an auxiliary control register for PCI Express port specific debug/defeature
operations.
Device:
Function:
Offset:
0, 2-3
0
4Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
4Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
4Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:1
0
RV
0
0
Reserved.
RW
NO_COMPLIANCE:
Set by software to enable link operation in the presence of single wire failures
on the link. If clear, then specified link behavior in the presence of a wire failure
will be Polling.Compliance.
3.8.8.32
PEXCTRL3[7:2,0] - PCI Express Control Register 3
Device:
Function:
Offset:
0, 2-3
0
4Dh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
4Dh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
4Dh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:5
4
RV
0
1
Reserved.
RWO
PORTENABLE: PCI Express port enable control
1: The PCI Express port can be enabled by software and is available for
use.
0: The PCI Express port is disabled and not available. This setting disables
the underlying port logic and associated PCI Express x4 lanes, completely
removing the port from register configuration space.
3:0
RV
0
Reserved
This is an additional control register for PCI Express port specific debug/defeature
operations for RAS.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
129
Register Description
3.8.8.33
PEXGCTRL - PCI Express Global Control Register
This 32-bit global register in the MCH implements chipset specific operations for
generalized control of all PCI Express events and activity such as Power Management,
hot-plug. There is only one register for all PCI Express ports and DMA Engine device
that controls related I/O operations.
Device:19
Function:0
Offset:17Ch
Version:Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
Timeout: Completion Time out
Internal timer for handling Outbound NP completion timeouts. This varies
based on the core clock frequency and the time at which the completion
structure is loaded relative to the timeout timer which is free-running. The
bounds of this roll over can be approximated as a Minimum of 6 or Max of 7
± few cycles) since there is a 3 bit counter whose roll over is tied to the
timeout timer
For 333 Mhz, the granularity of this timer viz. each increment is in the range
(9216 ns, 10,752 ns) giving a min/max value for a full face value of this
register field as (150.99 ms, 176.15 ms)
For 266 Mhz, the granularity of this timer viz. each increment is in the range
(11520 ns, 13440 ns) giving a min/max value for a full face value of this
register field as (188.73 ms, 220.19 ms)
BIOS/Software needs to set this field as appropriate for handling various
timeout conditions required by the system.
31:18
RV
3FFFh
Note: For example with BNB running at 333 Mhz, for SMBUS protocols, the
maximum value recommended for this field is 0x744 (or 1860
decimal) to achieve a 20 ms timeout threshold (that is, 20 ms =~
10,752 * 1860) such that it provides headroom to the chipset for
the global SMBUS timeout of 25ms.
Example: With 0x744 as default and 333 MHz core clock,
1.
Max timeout value: If bits 31:28 were set to 0x744 (1860d), the
timeout delay is calculated as follows:
1860*7 (for the rollovers)*512(lower 9 bits)*3.0ns (for 333 MHz) =
1860*107542=19.998ms=~20 ms
2.
Min timeout value: If bits 31:28 were set to 0x744 (1860d), the delay
calculation would be like this:
1860*6 (too close to the limit, so missed full count for one rollover)*512
(lower 9 bits)*3.0 ns (for 333 MHz)= 17.141 ms=~17 ms
17:2
RV
1385
Reserved.
1
RWST
0
PME_TURN_OFF: Send PME Turn Off Message
When set, the Intel 5000 Chipset MCH will issue a PME Turn Off Message to
all enabled PCI Express ports excluding the ESI port. The Intel 5000 Chipset
MCH will clear this bit once the Message is sent.
•
NOTE: In the Intel 5000 Chipset MCH implementation, an end device
that is D3 PM state and the Link being in L2 will not respond to any
transaction to the device until it is woken up by the WAKE# signal in the
platform. Under these conditions, if software sets the PME_Turn_OFF (bit
1) of this register, the Intel 5000 Chipset MCH will not send the message
until the Link is brought back into L0. i.e. PME_TURN_OFF bit will remain
set until the message is dispatched. Furthermore, a surprise link Down
error is logged.
† Expected Usage: Software should not set this bit if the link is already in
L2 prior.
0
RWC
0
PME_TO_ACK: Received PME Time Out Acknowledge Message
The Intel 5000P Chipset MCH sets this bit when it receives a PME_TO_ACK
Message from all enabled PCI Express ports excluding the ESI port. Software
will clear this bit when it handles the Acknowledge. Note that the ESI2 will
not generate a PME_TO_Ack based on the flow described in the ESI spec.
However, if a PME_TO_Ack is received at the Intel 5000P Chipset MCH ESI
port, it will be Master Aborted.
®
130
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.8.34
INTXSWZCTRL[7:2,0]: PCI Express Interrupt Swizzle Control Register
Device:
7-2,0
Function: 0
Offset:
4Fh
Bit
7:2
1:0
Attr
RO
Default
0h
Description
Reserved
RWO
00
INTxSWZ: INTx Swizzle
The encoding below defines the target Intx type to which the incoming Intx
message is mapped to for that port. (4 combinations using the Barber-pole
slide mechanism)
00: INTA=>INTA, INTB=>INTB, INTC=>INTC, INTD=>INTD (default 1:1)
01: INTA=>INTB, INTB=>INTC, INTC=>INTD, INTD=>INTA
10: INTA=>INTC, INTB=>INTD, INTC=>INTA, INTD=>INTB
11: INTA=>INTD, INTB=>INTA, INTC=>INTB, INTD=>INTC
This register provides software the ability to swizzle the legacy interrupts (intx) from
each port and remap them to a different interrupt type (IntA,B,C,D) for the purposes of
interrupt rebalancing to optimize system performance. This swizzling only applies to
inbound intx messages that arrive at the various ports (including ESI). The default
setting is to have one-to-one map of the same interrupt types, that is (INTA => INTA,
and so forth). BIOS can program this register during boot time (before enabling
interrupts) to swizzle the intx types for the various ports within the combinations
described in this register. MCH will use the transformed intx messages from the various
ports and track them using the bit vector as a wired-or logic for sending assert/
deassert intx messages on the ESI. Please refer to the Interrupt Swizzling Solution for
Intel 5000 Chipset Series-based Platforms - Application Note, document #314337
available on developer.intel.com for more detailed information on this feature.
3.8.9
PCI Express Power Management Capability Structure
The Intel 5000P Chipset MCH PCI Express port provides basic power management
capabilities to handle PM events for compatibility. The PCI Express ports can be placed
in a pseudo D3 hot state but it does have real power savings and works as if it were in
the D0 mode.
3.8.9.1
PMCAP[7:2,0] - Power Management Capabilities Register
The PM Capabilities Register defines the capability ID, next pointer and other power
management related support. The following PM registers /capabilities are added for
software compliance.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
131
Register Description
Device:
Function:
Offset:
0, 2-3
0
50h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
50h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
50h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:27
RO
11001
PMES: PME Support
Identifies power states in the Intel 5000P Chipset MCH which can send an
“Assert_PMEGPE/Deassert PMEGPE” message. Bits 31, 30 and 27 must be set
to '1' for PCI-PCI bridge structures representing ports on root complexes. The
definition of these bits is taken from the PCI Bus Power Management Interface
Specification Revision 1.1.
XXXX1b - Assert_PMEGPE/Deassert PMEGPE can be sent from D0
XXX1Xb - Assert_PMEGPE/Deassert PMEGPE can be sent from D1 (Not
supported by Intel 5000P Chipset MCH)
XX1XXb - Assert_PMEGPE/Deassert PMEGPE can be sent from D2 (Not
supported by Intel 5000P Chipset MCH)
X1XXXb - Assert_PMEGPE/Deassert PMEGPE can be sent from D3 hot
(Supported by Intel 5000P Chipset MCH)
1XXXXb - Assert_PMEGPE/Deassert PMEGPE can be sent from D3 cold
(Not supported by Intel 5000P Chipset MCH)
26
25
RO
RO
0
0
D2S: D2 Support
Intel 5000P Chipset MCH does not support power management state D2.
D1S: D1 Support
Intel 5000P Chipset MCH does not support power management state D1.
24:22
21
RO
RO
RV
RO
0h
0
AUXCUR: AUX Current
DSI: Device Specific Initialization
Reserved.
20
0
19
0
PMECLK: PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
18:16
15:8
RO
RO
010
58h
VER: Version
This field is set to 2h as version number from the PCI Express Base
Specification, Revision 1.0a specification.
NXTCAPPTR: Next Capability Pointer
This field is set to offset 58h for the next capability structure (MSI) in the PCI
2.3 compatible space.
7:0
RO
01h
CAPID: Capability ID
Provides the PM capability ID assigned by PCI-SIG.
3.8.9.2
PMCSR[7:2, 0] - Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express
port of the MCH.
®
132
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
54h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
54h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
54h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:24
RO
00h
Data: Data
Data read out based on data select (DSEL). Refer to section 3.2.6 of PCI PM
specification for details. This is not implemented in the Power Management
capability for Intel 5000P Chipset MCH and is hardwired to 0h.
23
22
RO
RO
0h
0h
BPCCEN: Bus Power/Clock Control Enable
This field is hardwired to 0h as it does not apply to PCI Express.
B2B3S: B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express.
21:16
15
RV
0h
0h
Reserved.
RWCST
PMESTS: PME Status
This PME Status is a sticky bit. When set, the PCI Express port generates a
PME internally independent of the PMEEN bit defined below. Software
clears this bit by writing a ‘1’ when it has been completed.
As a root port, the Intel 5000P Chipset MCH will never set this bit, because
it never generates a PME internally independent of the PMEEN bit.
14:13
12:9
8
RO
RO
0h
0h
0h
DSCL: Data Scale
This 2-bit field indicates the scaling factor to be used while interpreting the
“data_scale” field.
DSEL: Data Select
This 4-bit field is used to select which data is to reported through the “data”
and the “Data Scale” fields.
RWST
PMEEN: PME Enable
This field is a sticky bit and when set enables PMEs generated internally to
appear at the Intel 631xESB/632xESB I/O Controller Hub through the
“Assert(Deassert)_PMEGPE”message. This has no effect on the Intel 5000P
Chipset MCH since it does not generate PME events internally.
7:2
1:0
RV
0h
0h
Reserved.
RW
PS: Power State
This 2-bit field is used to determine the current power state of the function
and to set a new power state as well.
00: D0
01: D1 (reserved)
10: D2 (reserved)
11: D3_hot
If Software sets this to D1 or D2, then the power state will default to D0.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
133
Register Description
3.8.10
PCI Express Message Signaled Interrupts (MSI) Capability
Structure
Message Signaled Interrupts (MSI) is an optional feature that enables a device to
request service by writing a system-specified message to a system-specified address in
the form of an interrupt message. The transaction address (for example, FEEx_xxxxh)
specifies the message destination and the transaction data specifies the message. The
MSI mechanism is supported by the following registers: the MSICAPID, MSINXPTR,
MSICTRL, MSIAR and MSIDR register described below.
3.8.10.1
MSICAPID[7:2, 0] - MSI Capability ID
Device:
Function:
Offset:
0, 2-3
0
58h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
58h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
58h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
05h
CAPID: Capability ID
Assigned by PCI-SIG for message signaling capability.
3.8.10.2
MSINXPTR[7:2, 0]- MSI Next Pointer
Device:
Function:
Offset:
0, 2-3
0
59h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
59h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
59h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
RO
6Ch
NXTPTR: Next Pointer
This field is set to 6Ch for the next capability list (PCI Express capability
structure - PEXCAP) in the chain.
®
134
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.10.3
MSICTRL[7:2, 0] - Message Control Register
Device:
Function:
Offset:
0, 2-3
0
5Ah
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
5Ah
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
5Ah
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:8
7
RV
RO
00h
0
Reserved.
AD64CAP: 64-bit Address Capable
This field is hardwired to 0h since the message writes addresses are only 32-
bit addresses (for example, FEEx_xxxxh).
6:4
RW
000
MMEN: Multiple Message Enable
Software writes to this field to indicate the number of allocated messages
which is aligned to a power of two. When MSI is enabled, the software will
allocate at least one message to the device. See below for discussion on how
the interrupts are handled if N is the number of messages by software.
If software writes a value greater than the limit specified by the MMCAP field in
the MMEN field, it is considered as a programming error. The Intel 5000P
Chipset MCH GNB will only use the LSB of the MMEN (as a power of 2) to
decode up to 2 messages.
3:1
RO
001
MMCAP: Multiple Message Capable
Software reads this field to determine the number of requested messages.
which is aligned to a power of two. It is set to 2 messages (encoding of 001).
The Intel 5000P Chipset MCH is designed to handle MSIs for different events
•
•
HP/PM events
RAS Error events
0
RW
0
MSIEN: MSI Enable
The software sets this bit to select legacy interrupts or transmit MSI
messages.
0: Disables MSI from being generated.
1: Enables the Intel 5000P Chipset MCH to use MSI messages to request
context specific service through register bits defined in the Section 3.8.8.32
for events such as hot-plug, PM, RAS.
Refer to the Intel 5000P Chipset Programming Guide for details on the legacy,
ACPI and interrupt generation events.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
135
Register Description
3.8.10.4
MSIAR[7:2, 0] - MSI Address Register
The MSI Address Register (MSIAR) contains the system specific address information to
route MSI interrupts and is broken into its constituent fields.
Device:
Function:
Offset:
0, 2-3
0
5Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
5Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
5Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:20
RO
FEEh
AMSB: Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address.
19:12
RW
00h
ADSTID: Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
11:4
3
RW
RW
00h
0h
AEXDSTID: Address Extended Destination ID
This field is not used by IA32 processor.
ARDHINT: Address Redirection Hint
0: directed
1: redirectable
2
RW
RV
0h
0h
ADM: Address Destination Mode
0: physical
1: logical
1:0
Reserved.
Not used since the memory write is D-word aligned
3.8.10.5
MSIDR[7:2, 0] - MSI Data Register
The MSI Data Register (MSIDR) contains all the data (interrupt vector) related
information to route MSI interrupts.
®
136
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
60h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
60h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
60h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:16
15
RV
0000h
0h
Reserved.
RW
TM: Trigger Mode
This field Specifies the type of trigger operation
0: Edge
1: level
14
RW
0h
LVL: Level
If TM is 0h, then this field is a don’t care.
Edge triggered messages are consistently treated as assert messages. For
level triggered interrupts, this bit reflects the state of the interrupt input if TM
is 1h, then
0: Deassert Messages
1: Assert Messages
13:11
10:8
RW
RW
0h
0h
These bits are don’t care in IOxAPIC interrupt message data field specification.
DM: Delivery Mode
000: Fixed
001: Lowest Priority
010: SMI/HMI
011: Reserved
100: NMI
101: INIT
110: Reserved
111: ExtINT
7:0
RW
0h
IV: Interrupt Vector
The interrupt vector (LSB) will be modified by the Intel 5000P Chipset MCH to
provide context sensitive interrupt information for different events that require
attention from the processor. For example, hot-plug, Power Management and
RAS error events.
Depending on the number of Messages enabled by the processor in
Section 3.8.10.3, and Table 3-34 illustrates the breakdown.
Table 3-34. IV Handling and Processing by MCH
Number of Messages
enabled by Software
(MSICTRL.MMEN)
Events
IV[7:0]
xxxxxxxx1
xxxxxxx0
xxxxxxx1
1
2
All
HP, PM
RAS errors
Notes:
1. The term “xxxxxx” in the Interrupt vector denotes that software/BIOS initializes them
and the MCH will not modify any of the “x” bits except the LSB as indicated in the table
as a function of MMEN
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
137
Register Description
3.8.11
PCI Express Capability Structure
The PCI Express capability structure describes PCI Express related functionality,
identification and other information such as control/status associated with the port. It
is located in the PCI 2.3 compatible space and supports legacy operating system by
enabling PCI software transparent features.
3.8.11.1
PEXCAPL[7:2, 0]- PCI Express Capability List Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 2.3 configuration space.
Device:
Function:
Offset:
0, 2-3
0
6Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
6Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
6Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:8
RO
00h
NXTPTR: Next Ptr
This field is set to NULL pointer to terminate the PCI capability list.
7:0
RO
10h
CAPID: Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
3.8.11.2
PEXCAP[7:2, 0] - PCI Express Capabilities Register
The PCI Express Capabilities register identifies the PCI Express device type and
associated capabilities.
Device:
Function:
Offset:
0, 2-3
0
6Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
6Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
6Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:14
RV
0h
Reserved.
®
138
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
6Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
6Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
6Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
IMN: Interrupt Message Number
13:9
RO
00h
This field indicates the interrupt message number that is generated from the
PCI Express port. When there are more than one MSI interrupt Number, this
register field is required to contain the offset between the base Message Data
and the MSI Message that is generated when the status bits in the slot status
register or root port status registers are set. The chipset is required to update
the field if the number of MSI messages changes.
8
if
0
SLOT_Impl: Slot Implemented
(port
7-2)
{RW
O}
1: indicates that the PCI Express link associated with the port is connected to a
slot.
0: indicates no slot is connected to this port.
This register bit is of type “write once” and is controlled by BIOS/special
initialization firmware.
For the DMI port, this value should always be 0b since it is not hot-pluggable
and it is required for boot.
Rest of the PCI_Express ports which are slotted/hot-pluggable, BIOS or
Software can set this field to enable the slots.
elsif
(port
0)
{RO}
endif
7:4
3:0
RO
0100
0001
DPT: Device/Port Type
This field identifies the type of device. It is set to 0100 as defined in the spec
since the PCI Express port is a “root port” in the Intel 5000P Chipset MCH.
RO
VERS: Capability Version
This field identifies the version of the PCI Express capability structure. Set to
0001 by PCI SIG.
3.8.11.3
PEXDEVCAP[7:2, 0] - PCI Express Device Capabilities Register
The PCI Express Device Capabilities register identifies device specific information for
the port.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
139
Register Description
Device:
Function:
Offset:
0, 2-3
0
70h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
70h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
70h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:28
27:26
RV
RO
0h
0h
Reserved.
CSPLS: Captured Slot Power Limit Scale
Specifies the scale used for the Captured Slot Power Limit Value. It does not
apply to Intel 5000P Chipset MCH as it is a Root complex.
Hardwired to 0h.
25:18
RO
00h
CSPLV: Captured Slot Power Limit Value
This field specifies upper limit on power supplied by a slot in an upstream port.
It does not apply to Intel 5000P Chipset MCH as it is a Root complex.
Hardwired to 00h.
17:15
14
RV
RO
0h
0
Reserved
PIPD: Power Indicator Present on Device
This bit when set indicates that a Power Indicator is implemented.
0: PIPD is disabled in Intel 5000P Chipset MCH
1: Reserved
13
12
RO
RO
RO
0
0
AIPD: Attention Indicator Present
This bit when set indicates that an Attention Indicator is implemented.
0: AIPD is disabled in Intel 5000P Chipset MCH
1: Reserved
ABPD: Attention Button Present
This bit when set indicates that an Attention Button is implemented.
0: ABPD is disabled in Intel 5000P Chipset MCH
1: Reserved
11:9
111
EPL1AL: Endpoint L1 Acceptable Latency
This field indicates the acceptable latency that an Endpoint can withstand due
to the transition from L1 state to the L0 state.
000: Less than 1µs
001: 1 µs to less than 2 µs
010: 2 µs to less than 4 µs
011: 4 µs to less than 8 µs
100: 8 µs to less than 16 µs
101: 16 µs to less than 32 µs
110: 32 µs to 64 µs
111: More than 64 µs
The Intel 5000P Chipset MCH does not support EndpointL1 acceptable latency
and is set to the maximum value for safety.
®
140
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
70h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
70h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
70h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
8:6
RO
111
EPL0AL: Endpoints L0s Acceptable Latency
This field indicates the acceptable latency that an Endpoint can withstand due
to the transition from L0s state to the L0 state.
000: Less than 64 ns
001: 64 ns to less than 128 ns
010: 128 ns to less than 256 ns
011: 256 ns to less than 512 ns
100: 512 ns to less than 1 µs
101: 1 µs to less than 2 µs
110: 2 µs to 4 µs
111: More than 4 µs
Note that Intel 5000P Chipset MCH does not support L0s implementation and
for backup, this field is set to the maximum value.
5
RO
RO
0
ETFS: Extended Tag Field Supported
This field indicates the maximum supported size of the Tag field.
0: In the Intel 5000P Chipset MCH, only 5-bit Tag field is supported
4:3
0h
PFS: Phantom Functions Supported
This field indicates the number of most significant bits of the function number
portion of Requester ID in a TLP that are logically combined with the Tag
identifier.
0: For root ports, no function number bits for phantom functions are
supported
2:0
RO
001
MPLSS: Max Payload Size Supported
This field indicates the maximum payload size that the PCI Express port can
support for TLPs.
001: 256 B max payload size
Others - Reserved
Note that the Intel 5000P Chipset MCH only supports up to a maximum of 256
B payload (for example, writes, read completions) for each TLP and violations
will be flagged as PCI Express errors
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
141
Register Description
3.8.11.4
PEXDEVCTRL[7:2, 0] - PCI Express Device Control Register
The PCI Express Device Control register controls PCI Express specific capabilities
parameters associated with this port.
Device:
Function:
Offset:
0, 2-3
0
74h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
74h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
74h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15
RV
0h
Reserved.
RW
101
14:12
MRRS: Max_Read_Request_Size
This field sets maximum Read Request size generated by the Intel 5000P
Chipset MCH. The PCI Express port must not generate read requests with
size exceeding the set value.
000: 128B max read request size
001: 256B max read request size
010: 512B max read request size
011: 1024B max read request size
100: 2048B max read request size
101: 4096B max read request size
110: Reserved
111: Reserved
The MCH will not generate read requests larger than 64B in general on the
outbound side due to the internal Micro-architecture (CPU initiated, DMA or
Peer to Peer). Hence the field is set to 000b encoding.
11
RW
1
ENNOSNP: Enable No Snoop
When set, the PCI Express port is permitted to set the “No Snoop bit” in the
Requester Attributes of transactions it initiates that do not require hardware
enforced cache coherency. Typically the “No Snoop bit” is set by an
originating PCI Express device down in the hierarchy.
The Intel 5000P Chipset MCH never sets or modifies the “No snoop bit” in the
received TLP even if ENNOSNP is enabled. For outbound traffic, the Intel
5000P Chipset MCH does not need to snoop.
10
RWST
0
APPME: Auxiliary Power Management Enable
1: Enables the PCI Express port to draw AUX power independent of PME
AUX power.
0: Disables the PCI Express port to draw AUX power independent of PME
AUX power.
Devices that require AUX power on legacy operating systems should
continue to indicate PME AUX power requirements. AUX power is allocated
as requested in the AUX_Current field on the Power Management
Capabilities Register (PMC), independent of the PMEEN bit in the Power
Management.
Control & Status Register (PMCSR) defined in Section 3.8.9.2.
®
142
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
74h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
74h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
74h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
PFEN: Phantom Functions Enable
9
RO
0
This bit enables the PCI Express port to use unclaimed functions as Phantom
Functions for extending the number of outstanding transaction identifiers.
Intel 5000P Chipset MCH does not implement this bit (Root complex) and is
hardwired to 0.
8
RO
0h
ETFEN: Extended Tag Field Enable
This bit enables the PCI Express port to use an 8-bit Tag field as a requester.
The Intel 5000P Chipset MCH does not use this field (Root complex) and is
hardwired to 0.
7:5
RW
000
MPS: Max Payload Size
This field is set by configuration software for the maximum TLP payload size
for the PCI Express port. As a receiver, the Intel 5000P Chipset MCH must
handle TLPs as large as the set value. As a transmitter, it must not generate
TLPs exceeding the set value. Permissible values that can be programmed
are indicated by the Max_Payload_Size_Supported in the Device Capabilities
register:
000: 128B max payload size
001: 256B max payload size
010: 512B max payload size
011: 1024B max payload size
100: 2048B max payload size
101: 4096B max payload size
others: Reserved
Note: The MCH supports max payload sizes only up to 256B. If Software
programs a value that exceeds 256B for the MPS field, then it will be
considered as an error. For receive TLPs, it will be flagged as “unsupported
request” and for transmit TLPs, it will be recorded as a Malformed TLP.
Note: Due to erratum 501664, read completion coalescing cannot be used if
MPS=256 B is set by software. Read completion combining up to 128 B would
work only if the MPS is set by software. Read completion combining up to
128 B would work only if the MPS is set to 128 B. See
PEXCTRL.COALESCE_EN field.
4
3
RO
0
0
ENRORD: Enable Relaxed Ordering
Intel 5000P Chipset MCH enforces only strict ordering only and hence this bit
is initialized to ‘0’
RW
URREN: Unsupported Request Reporting Enable
This bit controls the reporting of unsupported requests to the MCH in the PCI
Express port.
0: Unsupported request reporting is disabled
1: Unsupported request reporting is enabled
Note that the reporting of error messages (such as ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by PCI Express port is controlled
exclusively by the PCI Express Root Control register (PEXRTCTRL) described
in Section 3.8.11.12.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
143
Register Description
Device:
Function:
Offset:
0, 2-3
0
74h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
74h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
74h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
FERE: Fatal Error Reporting Enable
2
RW
0
This bit controls the reporting of fatal errors internal to the MCH in the PCI
Express port.
0: Fatal error reporting is disabled
1: Fatal error reporting is enabled
1
0
RW
RW
0
0
NFERE: Non Fatal Error Reporting Enable
This bit controls the reporting of non fatal errors internal to the MCH in the PCI
Express port.
0: Non Fatal error reporting is disabled
1: Non Fatal error reporting is enabled
CERE: Correctable Error Reporting Enable
This bit controls the reporting of correctable errors internal to the MCH in the
PCI Express port.
0: Correctable error reporting is disabled
1: Correctable Fatal error reporting is enabled
3.8.11.5
PEXDEVSTS[7:2, 0] - PCI Express Device Status Register
The PCI Express Device Status register provides information about PCI Express device
specific parameters associated with this port.
Device:
Function:
Offset:
0, 2-3
0
76h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
76h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
76h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:6
5
RV
RO
000h
0h
Reserved.
TP: Transactions Pending
1: Indicates that the PCI Express port has issued Non-Posted Requests which
have not been completed.
0: A device reports this bit cleared only when all Completions for any
outstanding Non-Posted Requests have been received.
Since the MCH Root port that do not issue Non-Posted Requests on their own
behalf, it is hardwired to 0b.
®
144
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
76h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
76h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
76h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
4
RO
0
APD: AUX Power Detected
1- AUX power is detected by the PCI Express port.
0: No AUX power is detected
3
2
1
RWC
RWC
RWC
0
0
0
URD: Unsupported Request Detected
This bit indicates that the device received an Unsupported Request in the PCI
Express port. Errors are logged in this register regardless of whether error
reporting is enabled or not in the Device Control Register.
1: Unsupported Request detected at the port
This records the detection of receiving an unsupported request, error IO2.
FED: Fatal Error Detected
This bit indicates that status of a fatal (uncorrectable) error detected in the PCI
Express port. Errors are logged in this register regardless of whether error
reporting is enabled or not in the Device Control register.
1: Fatal errors detected
0: No Fatal errors detected
NFED: Non Fatal Error Detected
This bit indicates status of non-fatal errors detected. This bit gets set if a non-
fatal uncorrectable error is detected in the PCI Express port. Errors are logged
in this register regardless of whether error reporting is enabled or not in the
Device Control register.
1: Non Fatal errors detected
0: No non-Fatal Errors detected
0
RWC
0
CED: Correctable Error Detected
This bit indicates status of correctable errors detected. This bit gets set if a
correctable error is detected in the PCI Express port. Errors are logged in this
register regardless of whether error reporting is enabled or not in the PCI
Express Device Control register.
1: Correctable errors detected
0: No correctable errors detected
3.8.11.6
PEXLNKCAP[7:2,0] - PCI Express Link Capabilities Register
The Link Capabilities register identifies the PCI Express specific link capabilities.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
145
Register Description
Device:
Function:
Offset:
0, 2-3
0
78h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
78h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
78h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:24
RWO
if (port 0)
{0h} elsif
(port 2)
{02h} elsif
(port 3)
{03h} elsif
(port 4)
PN: Port Number
This field indicates the PCI Express port number for the link and is initialized
by software/BIOS. This will correspond to the device number for each port.
port 0- device number of 0 (ESI)
port 2 - device number of 2
{04h} elsif
(port 5)
{05h} elsif
(port 6)
{06h} elsif
(port 7)
{07h} endif
port 3 - device number of 3
port 4 - device number of 4
port 5- device number of 5
port 6- device number of 6
port 7- device number of 7
23:18
17:15
RV
RO
0h
7h
Reserved.
L1EL: L1 Exit Latency
This field indicates the L1 exit latency for the given PCI Express port. It
indicates the length of time this port requires to complete transition from L1
to L0.
000: Less than 1µs
001: 1 µs to less than 2 µs
010: 2 µs to less than 4 µs
011: 4 µs to less than 8 µs
100: 8 µs to less than 16 µs
101: 16 µs to less than 32 µs
110: 32 µs to 64 µs
111: More than 64us
The Intel 5000P Chipset MCH does not support L1 acceptable latency and is
set to the maximum value for safety
14:12
RO
7h
L0sEL: L0s Exit Latency
This field indicates the L0s exit latency (i.e L0s to L0) for the PCI Express
port.
000: Less than 64 ns
001: 64 ns to less than 128 ns
010: 128 ns to less than 256 ns
011: 256 ns to less than 512 ns
100: 512 ns to less than 1 µs
101: 1 µs to less than 2 µs
110: 2 µs to 4 µs
111: More than 4 µs
Note that Intel 5000P Chipset MCH does not support L0s exit latency
implementation and for safety, this field is set to the maximum value.
®
146
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
78h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
78h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
78h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
11:10
RO
01
ACTPMS: Active State Link PM Support
This field indicates the level of active state power management supported on
the given PCI Express port.
00: Disabled
01: L0s Entry Supported
10: Reserved
11: L0s and L1 Supported
The Intel 5000P Chipset MCH does not initiate L0s active state Power
Management but it does permit a downstream device from placing the link in
L0s
9:4
RO
if (port
0,1,3,5,7)
{x4} elseif
(port 2,6)
{x8} elseif
(port 4)
MLW: Maximum Link Width
This field indicates the maximum width of the given PCI Express Link
attached to the port.
000001: x1
000100: x4
001000: x8
010000: x16
{x16} endif
Others - Reserved
See Table 3-35.
3:0
RO
0001
MLS: Maximum Link Speed
This field indicates the maximum Link speed of the given PCI Express port.
0001: 2.5 Gb/s
Others - Reserved
Table 3-35. Maximum Link Width Default Value for Different PCI Express Ports
Device/Port
Maximum Link Width
Value
0,3,5,7
2,6
x4
x8
000100
001000
010000
001000
4
x16
x8
Table 3-35 shows various combining options for PCI Express ports. When ports
combine, the control registers for the combined port revert to the lower numbered
port. Thus when ports 2 and 3 are combined, the combined x8 port is accessed through
port 2 control registers.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
147
Register Description
3.8.11.7
PEXLNKCTRL[7:2, 0] - PCI Express Link Control Register
The PCI Express Link Control register controls the PCI Express Link specific parameters.
Device:
Function:
Offset:
0, 2-3
0
7Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
7Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
7Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:8
7
RV
00h
0
Reserved.
RW
Ext_Synch: Extended Synch
This bit when set forces the transmission of 4096 FTS ordered sets in the L0s
state followed by a single SKP ordered set prior to entering the L0 state, and
the transmission of 1024 TS1 ordered sets in the L1 state prior to entering the
Recovery state. This mode provides external devices (for example, logic
analyzers) monitoring the Link time to achieve bit and Symbol lock before the
Link enters the L0 or Recovery states and resumes communication.
6
RW
0
CCCON: Common Clock Configuration
0: indicates that this PCI Express port and its counterpart at the opposite end
of the Link are operating with an asynchronous reference clock.
1: indicates that this PCI Express port and its counterpart at the opposite end
of the Link are operating with a distributed common reference clock.
Components utilize this common clock configuration information to report the
correct L0s and L1 Exit Latencies.
5
4
WO
RW
0
0
RLNK: Retrain Link
This bit, when set, initiates link retraining in the given PCI Express port. It
consistently returns 0 when read.
LNKDIS: Link Disable
This field indicates whether the link associated with the PCI Express port is
enabled or disabled.
0: Enables the link associated with the PCI Express port
1: Disables the link associated with the PCI Express port
Software should wait a minimum of 2 ms to make sure the link has entered
the electrical idle state before clearing this bit.
3
RO
0
RCB: Read Completion Boundary
This field defines the read completion boundary for the PCI Express port.
Defined encodings for RCB capabilities are:
0: 64 byte
1: 128 byte
The Intel 5000P Chipset MCH supports only 64 B read completion boundary
and is hardwired to 0.
2
RV
0
Reserved.
®
148
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
7Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
7Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
7Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
1:0
RW
00
ASTPMCTRL: Active State Link PM Control
This field controls the level of active state power management supported on
the given PCI Express port.
00: Disabled
01: L0s Entry Supported
10: Reserved
11: L0s and L1 Supported
Note: This has no effect on the Intel 5000P Chipset MCH.
3.8.11.8
PEXLNKSTS[7:2, 0] - PCI Express Link Status Register
The PCI Express Link Status register provides information on the status of the PCI
Express Link such as negotiated width, training, and so forth.
Device:
Function:
Offset:
0, 2-3
0
7Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
7Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
7Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:13
12
RV
0h
1
Reserved.
RWO
SCCON: Slot Clock Configuration
This bit indicates that the component uses the same physical reference clock
that the platform provides on the connector. If the device uses an independent
clock irrespective of the presence of a reference on the connector, this bit
must be clear.
1: indicates same physical clock in the PCI Express connector as in the
platform.
0: indicates independent clock on the PCI Express connector from that of the
platform.
The Intel 5000P Chipset MCH initializes this bit to '1' because the expected
state of the platform is to have one clock source shared between the Intel
5000P Chipset MCH component and any down-devices or slot connectors. It is
the responsibility of BIOS to be aware of the real platform configuration, and
clear this bit if the reference clocks differ.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
149
Register Description
Device:
Function:
Offset:
0, 2-3
0
7Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
7Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
7Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
11
RO
0
LNKTRG: Link Training
This field indicates the status of an ongoing link training session in the current
PCI Express port and is controlled by the Hardware.
0: indicates that the LTSSM is neither in “Configuration” nor “Recovery” states.
1: indicates Link training in progress (Physical Layer LTSSM is in
Configuration or Recovery state or the RLNK (retrain link) was set in
Section 3.8.11.7 but training has not yet begun.
Also refer to the BCTRL.SBUSRESET for details on how the Link training bit can
be used for sensing Hot-reset states.
10
RO
RO
0
TERR: Training Error
This field indicates the occurrence of a Link training error.
0: indicates no Link training error occurred.
1: indicates Link training error occurred.
9:4
000100
NLNKWD: Negotiated Link Width1
This field indicates the negotiated width of the given PCI Express link after
training is completed.
Only x1, x4, x8, and x16 link width negotiations are possible in the Intel
5000P Chipset MCH. Refer to Table 3-36 for the port and link width
assignment after training is completed.
3:0
RO
1h
LNKSPD: Link Speed
This field indicates the negotiated Link speed of the given PCI Express Link:
0001- 2.5 Gb/s PCI Express link
Others - Reserved
Notes:
1. The NLNKWD field is set to a default value corresponding to x4 internally within the Intel 5000P Chipset MCH.
Note that this field is a don’t care until training is completed for the link. Software should not use this field to
determine whether a link is up (enabled) or not.
Table 3-36. Negotiated Link Width For Different PCI Express Ports After Training
Device/Port
Negotiated Link Width
Value
2,3,4,5,6,7
0,2,3,4,5,6,7
2,4,6
x1
x4
000001
000100
1
x8
001000
010000
2
4
x16
Notes:
1. Ports 3, 5, and 7 report 000000 as appropriate.
2. Ports 5, 6, and 7 report 000000 as appropriate.
3.8.11.9
PEXSLOTCAP[7:2, 0] - PCI Express Slot Capabilities Register
The Slot Capabilities register identifies the PCI Express specific slot capabilities.
®
150
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
80h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
80h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
80h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:19
RWO
0h
PSN: Physical Slot Number
This field indicates the physical slot number connected to the PCI Express
port. It should be initialized to 0 for ports connected to devices that are either
integrated on the system board or integrated within the same silicon such as
the Root port in Intel 5000P Chipset MCH.
18:17
16:15
RV
0h
0h
Reserved.
RWO
SPLS: Slot Power Limit Scale
This field specifies the scale used for the Slot Power Limit Value.
Range of Values:
00: 1.0x
01: 0.1x
10: 0.01x
11: 0.001x
14:7
6
RWO
RWO
00h
0h
SPLV: Slot Power Limit Value
This field specifies the upper limit on power supplied by slot in conjunction
with the Slot Power Limit Scale value defined previously.
Power limit (in Watts) = SPLS x SPLV
HPC: Hot-Plug Capable
This field defines hot-plug support capabilities for the PCI Express port.
0: indicates that this slot is not capable of supporting hot-plug operations.
1: indicates that this slot is capable of supporting hot-plug operations
5
RO
0h
HPS: Hot-Plug Surprise
This field indicates that a device in this slot may be removed from the system
without prior notification.
0: Indicates that hot-plug surprise is not supported
1: Indicates that hot-plug surprise is supported
The Intel 5000P Chipset MCH does not support hot-plug surprise feature.
4
3
RWO
RWO
0h
0h
PIP: Power Indicator Present
This bit indicates that a Power Indicator is implemented on the chassis for this
slot.
0: Indicates that Power Indicator is not present
1: Indicates that Power Indicator is present
AIP: Attention Indicator Present
This bit indicates that an Attention Indicator is implemented on the chassis for
this slot.
0: Indicates that an Attention Indicator is not present
1: Indicates that an Attention Indicator is present
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
151
Register Description
Device:
Function:
Offset:
0, 2-3
0
80h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
80h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
80h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
2
RWO
0h
MRLSP: MRL Sensor Present
This bit indicates that an MRL Sensor is implemented on the chassis for this
slot.
0: Indicates that an MRL Sensor is not present
1: Indicates that an MRL Sensor is present
1
0
RWO
RWO
0h
0h
PCP: Power Controller Present
This bit indicates that a Power Controller is implemented on the chassis for
this slot.
0: Indicates that a Power Controller is not present
1: Indicates that a Power Controller is present
ABP: Attention Button Present
This bit indicates that an Attention Button is implemented on the chassis for
this slot.
0: Indicates that an Attention Button is not present
1: Indicates that an Attention Button is present
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.11.10 PEXSLOTCTRL[7:2, 0] - PCI Express Slot Control Register
The Slot Control register identifies the PCI Express specific slot control specific
parameters for operations such as hot-plug and Power Management. Software issues a
command to a hot-plug capable Port by issuing a write transaction that targets Slot
Control Register fields viz, PWRCTRL, PWRLED, ATNLED described below. A single write
to the Slot Control register is considered to be a single command, even if the write
affects more than one field in the Slot Control register. In response to this transaction,
the port must carry out the requested actions and then set the associated status field
(PEXSLOTS.CMDCMP) for the command completed event. The PEXSLOTSTS.CMDCMP
bit will be set only when there is a unique change to the state of the PWRCTRL,
PWRLED, ATNLED in this register.
Device:
Function:
Offset:
0, 2-3
0
84h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
84h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
84h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:11
10
RV
0h
0h
Reserved.
RW
PWRCTRL: Power Controller Control
This bit indicates the current state of the Power applied to the slot of the PCI
Express port.
0: Power On
1: Power Off
9:8
RW
0h
PWRLED: Power Indicator Control
This bit indicates the current state of the Power Indicator of the PCI Express
port
00: Reserved.
01: On
10: Blink (The Intel 5000P Chipset MCH drives 1.5 Hz square wave for Chassis
mounted LEDs in the case of legacy card form factor for PCI Express devices)
11: Off
Default is set to 11b (OFF)
When this field is written, the Intel 5000P Chipset MCH sends appropriate
POWER_INDICATOR messages through the PCI Express port. For legacy card
based PCI Express devices, the event is signaled via the virtual pins1 of the
Intel 5000P Chipset MCH, in addition. For PCI Express modules with advanced
form factor that incorporate LEDs and onboard decoding logic, the PCI Express
messages are interpreted directly (No virtual pins).
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
153
Register Description
Device:
Function:
Offset:
0, 2-3
0
84h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
84h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
84h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
ATNLED: Attention Indicator Control
7:6
RW
0h
This bit indicates the current state of the Attention Indicator of the PCI
Express
port
00: Reserved.
01: On
10: Blink (The Intel 5000P Chipset MCH drives 1.5 Hz square wave)
11: Off
Default is set to 11b (OFF)
When this field is written, the Intel 5000P Chipset MCH sends appropriate
ATTENTION_INDICATOR messages through the PCI Express port. For legacy
card based PCI Express devices, the event is signaled via the virtual pins of
the Intel 5000P Chipset MCH, in addition. For PCI Express modules with
advanced form factor that incorporate LEDs and onboard decoding logic, the
PCI Express messages are interpreted directly (No virtual pins).
5
4
RW
RW
0h
0h
HPINTEN: Hot-Plug Interrupt Enable
This field enables the generation of hot-plug interrupts and events in the PCI
Express port.
0: disables hot-plug events and interrupts
1: enables hot-plug events and interrupts
CCIEN: Command Completed Interrupt Enable
This field enables the generation of hot-plug interrupts when a command is
completed by the hot-plug controller connected to the PCI Express port
0: Disables hot-plug interrupts on a command completion by a hot-plug
controller.
1: Enables hot-plug interrupts on a command completion by a hot-plug
controller.
3
RW
0h
PRSINTEN: Presence Detect Changed Enable
This bit enables the generation of hot-plug interrupts or wake messages via a
presence detect changed event.
0: Disables generation of hot-plug interrupts or wake messages when a
presence detect changed event happens.
1- Enables generation of hot-plug interrupts or wake messages when a
presence detect changed event happens.
2
RW
0h
MRLINTEN: MRL Sensor Changed Enable
This bit enables the generation of hot-plug interrupts or wake messages via a
MRL Sensor changed event.
0: Disables generation of hot-plug interrupts or wake messages when an MRL
Sensor changed event happens.
1: Enables generation of hot-plug interrupts or wake messages when an MRL
Sensor changed event happens.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
84h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
84h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
84h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
1
RW
0h
PWRINTEN: Power Fault Detected Enable
This bit enables the generation of hot-plug interrupts or wake messages via a
power fault event.
0: Disables generation of hot-plug interrupts or wake messages when a power
fault event happens.
1: Enables generation of hot-plug interrupts or wake messages when a power
fault event happens.
0
RW
0h
ATNINTEN: Attention Button Pressed Enable
This bit enables the generation of hot-plug interrupts or wake messages via an
attention button pressed event.
0: Disables generation of hot-plug interrupts or wake messages when the
attention button is pressed.
1: Enables generation of hot-plug interrupts or wake messages when the
attention button is pressed.
3.8.11.11 PEXSLOTSTS[7:2, 0] - PCI Express Slot Status Register
The PCI Express Slot Status register defines important status information for
operations such as hot-plug and Power Management.
Device:
Function:
Offset:
0, 2-3
0
86h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
86h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
86h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:7
6
RV
RO
0h
1h
Reserved.
PDS: Presence Detect State
This field conveys the Presence Detect status determined via an in-band
mechanism or through the Present Detect pins and shows the presence of a
card in the slot.
0: Slot Empty
1: Card Present in slot
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
155
Register Description
Device:
Function:
Offset:
0, 2-3
0
86h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
86h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
86h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
5
RO
0h
MRLSS: MRL Sensor State
This bit reports the status of an MRL sensor if it is implemented.
0: MRL Closed
1: MRL Open
4
RWC
0h
CMDCOMP: Command Completed
This bit is set by the Intel 5000P Chipset MCH when the hot-plug controller
completes an issued command and is ready to accept a new command. It is
subsequently cleared by software after the field has been read and processed.
3
2
1
0
RWC
RWC
RWC
RWC
0h
0h
0h
0h
PRSINT: Presence Detect Changed
This bit is set by the Intel 5000P Chipset MCH when a Presence Detect
Changed event is detected. It is subsequently cleared by software after the
field has been read and processed.
MRLSC: MRL Sensor Changed
This bit is set by the Intel 5000P Chipset MCH when an MRL Sensor Changed
event is detected. It is subsequently cleared by software after the field has
been read and processed.
PWRINT: Power Fault Detected
This bit is set by the Intel 5000P Chipset MCH when a power fault event is
detected by the power controller. It is subsequently cleared by software after
the field has been read and processed.
ABP: Attention Button Pressed
This bit is set by the Intel 5000P Chipset MCH when the attention button is
pressed. It is subsequently cleared by software after the field has been read
and processed.
Note that the Assert_intx/Assert_HPGPE message is sent to ESI port when any of the
events defined in bits[4:0] (CMDCOMP,PRSINT, MRLSC, PWRINT, ABP) of the
PEXSLOTSTS register are set provided the corresponding events in bits [4:0] of the
Section 3.8.11.10 and HPINTEN are enabled. Software writes to clear these bits and
MCH will send a Deassert_HPGPE message to ESI port (wired-OR).
For the case when MSI is enabled, any new event that sets these bits (e.g ABP, PRSINT
and so forth) will cause an MSI message to be sent to the FSB for each occurrence.
That is, each bit is considered unique.
Whereas in the case of Legacy interrupts, a wired-OR approach is used to mimic the
level sensitive behavior and only one assert_intx/assert_GPE (deassert_intx/
deassert_GPE) is sent even when multiple interrupt generating bits of the register get
set. Refer to Figure 3-5.
®
156
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Figure 3-5. PCI Express Hot-Plug Interrupt Flow
PEXHPINT
Intel® 5000P Chipset
Sends desassert_HPGP
E message via
DMI when the
Y
Intel® 5000P Chipset
Sends assert_HPGPE
message via DMI
(HPGPEEN == 1)
when the respective bits
PEXSLOTSTS str
cleared (wired-OR)
OR)
N
N
PEXSLOTCTRL[x].
HPINTEN = 1?
SW polls
status
Y
Intel® 5000P Chipset
Y
(MSICTRL[x].
MSIEN == 1) ?
Sends MSI per MSIAR
And MSIDR
N
Intel® 5000P Chipset
Sends desassert_INTx
message via DMI
when the
respective bits of
PEXSLOTSTS str
cleared (wired-
Intel® 5000P Chipset
Sends assert_INTx
message via DMI
per INTP
N
PEXCMD[x].INTx
Disable == 1?
Y
HPGPEEN
HPINTEN
MSIEN
INTx Disable
Output
1
0
0
0
0
x
1
1
1
0
x
1
0
0
x
x
x
0
1
x
assert_hpgpe
MSI
assert_intx
--
--
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
157
Register Description
3.8.11.12 PEXRTCTRL[7:2, 0] - PCI Express Root Control Register
The PCI Express Root Control register specifies parameters specific to the root
complex port.
Device:
Function:
Offset:
0, 2-3
0
88h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
88h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
88h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:4
3
RV
0h
0h
Reserved.
RW
PMEINTEN: PME Interrupt Enable
This field controls the generation of interrupts for PME messages.
1: Enables interrupt generation upon receipt of a PME message as reflected in
the PME Status bit defined in the PEXRTSTS register. A PME interrupt is
generated if the PMESTATUS register bit defined in Section 3.8.11.13, is set
when this bit is set from a cleared state.
0: Disables interrupt generation for PME messages.
2
1
0
RW
RW
RW
0h
0h
0h
SEFEEN: System Error on Fatal Error Enable
This field controls generation of system errors in the PCI Express port
hierarchy for fatal errors.
1: Indicates that a System Error should be generated if a fatal error
(ERR_FATAL) is reported by any of the devices in the hierarchy associated
with and including this PCI Express port.
0: No System Error should be generated on a fatal error (ERR_FATAL)
reported by any of the devices in the hierarchy.
SENFEEN: System Error on Non-Fatal Error Enable
This field controls generation of system errors in the PCI Express port
hierarchy for non-fatal errors.
1: Indicates that a System Error should be generated if a non-fatal error
(ERR_NONFATAL) is reported by any of the devices in the hierarchy
associated with and including this PCI Express port.
0: No System Error should be generated on a non-fatal error
(ERR_NONFATAL) reported by any of the devices in the hierarchy.
SECEEN: System Error on Correctable Error Enable
This field controls generation of system errors in the PCI Express port
hierarchy for correctable errors.
1: Indicates that a System Error should be generated if a correctable error
(ERR_COR) is reported by any of the devices in the hierarchy associated with
and including this PCI Express port
0: No System Error should be generated on a correctable error (ERR_COR)
reported by any of the devices in the hierarchy associated with and including
this PCI Express port.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.11.13 PEXRTSTS[7:2, 0] - PCI Express Root Status Register
The PCI Express Root Status register specifies parameters specific to the root
complex port.
Device:
Function:
Offset:
0, 2-3
0
8Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
8Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
8Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:18
17
RV
RO
0h
0h
Reserved.
PMEPEND: PME Pending
This field indicates that another PME is pending when the PME Status bit is
set. When the PME Status bit is cleared by software; the pending PME is
delivered by hardware by setting the PME Status bit again and updating the
Requestor ID appropriately. The PME pending bit is cleared by hardware if no
more PMEs are pending.
Note: The Intel 5000P Chipset MCH can handle two outstanding PM_PME
messages in its internal queues of the Power Management controller
per port. If the downstream device issues more than 2 PM_PME
messages successively, it will be dropped.
1
16
RWC
RO
0h
PMESTATUS: PME Status
This field indicates status of a PME that is underway in the PCI Express port.
1: PME was asserted by a requester as indicated by the PMEREQID field
This bit is cleared by software by writing a ‘1’. Subsequent PMEs are kept
pending until the PME Status is cleared.
15:0
0000h
PMEREQID: PME Requester ID
This field indicates the PCI requester ID of the last PME requestor.
Notes:
1.
PMEINTEN defined in PEXRTCTRL has to be set for PM interrupts to be generated. For non-MSI PM
interrupts, the PMESTATUS bit in each of the PEXRTSTS[2:7] registers are wired OR together and when set,
the MCH will send the “Assert_PMEGPE” message to the Intel 631xESB/632xESB I/O Controller Hub for
power management. When all the bits are clear, it will send the “Deassert_PMEGPE” message. PMEINTEN
defined in PEXRTCTRL has to be set for PM interrupts to be generated. PM_PME events that generate MSI
will depend on the MSIEN field in Section 3.8.10.3. Refer to the PM interrupt flow in Power Management
Chapter.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
159
Register Description
3.8.11.14 ESICTRL[0] - ESI Control Register
The ESICTRL register holds control information and defeature bits pertaining to the ESI
interface for power management.
Device:
Function:
Offset:
0
0
D4h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:15
14
RV
0h
1
Reserved.
RW
DL23R: Override L23 Ready - Recommend setting this bit to 1.
0: Wait for PME_Enter_L23 on all PCIe* ports
1: Do not wait for PME_Enter_L23 on all PCIe ports
13:12
11
RV
0
0
Reserved
RWC
PTE: PME_TO_Ack Time Expired
0: Default mode, “PME_TO_Ack” message received on all PCI Express ports
before timeout.
1: Signal that time expiration has occurred when the PTOV field described
below crosses the threshold in the Intel 5000P Chipset MCH.
10:9
RW
0h
PTOV: PME_TO_Ack Time Out Value
00: 1 ms (default)
01: 10 ms
10: 50 ms
11: Reserved
This register field provides the timer limit for the Intel 5000P Chipset MCH to
keep track of the elapsed time from sending “PME_Turn_off” to receiving a
“PME_TO_Ack”.
8:4
3:0
RV
0h
0h
Reserved.
RW
SAC: STOPGRANT ACK COUNT
This field tracks the number of Stop Grant acks received from the FSBs. The
MCH will forward the last StopGrantAck received from the FSB to the Intel
631xESB/632xESB I/O Controller Hub using the “Req_C2” command. Software
is expected to set this field to “THREADs-1” where the variable “THREAD” is
the total number of logical threads present in the system (currently can handle
up to 16). Typically each CPU thread will issue a StopGrantAck in response to a
STPCLK# assertion from the Intel 631xESB/632xESB I/O Controller Hub.
When the final StopGrantAck is received from the FSB and the internal counter
hits the value of SAC+1 (which is equal to THREAD), the MCH will initiate the
“Req_C2” command on the DMI.
It is illegal for the CPU to send more Stop Grant Acks than that specified in the
“THREAD” variable.
Note: For Sx Power management in H/W or S/W mode
3.8.12
PCI Express Advanced Error Reporting Capability
3.8.12.1
PEXENHCAP[7:2, 0] - PCI Express Enhanced Capability Header
This register identifies the capability structure and points to the next structure.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
100h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
100h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
100h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
NCAPOFF: Next Capability Offset
31:20
RO
140h
This field points to the next Capability in extended configuration space.
19:16
15:0
RO
RO
1h
CV: Capability Version
Set to 1h for this version of the PCI Express logic
0001h
PEXCAPID: PCI Express Extended CAP_ID
Assigned for advanced error reporting
3.8.12.2
UNCERRSTS[7:2] - Uncorrectable Error Status
This register identifies uncorrectable errors detected for the PCI Express Port. If an
error occurs and is unmasked in the detect register (EMSAK_UNCOR_PEX), the
appropriate error bit will be recorded in this register. If an error is recorded in the
UNCERRSTS register and the appropriate bit (along with the severity bit of the
UNCERRSEV register) determines which bit in the PEX_FAT_FERR, PEX_NF_COR_FERR,
PEX_FAT_NERR, PEX_NF_COR_NERR register gets recorded.These error log registers
are described starting from Section 3.8.12.24.
Device:
Function:
Offset:
2-3
0
104h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
104h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
104h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:21
20
RV
0h
0
Reserved
RWCST
RV
IO2Err: Received an Unsupported Request
Reserved
19
0
18
RWCST
RWCST
RWCST
RWCST
RWCST
0
IO9Err: Malformed TLP Status
IO10Err: Receiver Buffer Overflow Status
IO8Err: Unexpected Completion Status
IO7Err: Completer Abort Status
IO6Err: Completion Time-out Status
17
0
16
0
15
0
14
0
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
161
Register Description
Device:
Function:
Offset:
2-3
0
104h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
104h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
104h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
13
12
11:6
5
RWCST
RWCST
RV
0
0
IO5Err: Flow Control Protocol Error Status
IO4Err: Poisoned TLP Status
Reserved
0h
0
RWST
RWCST
RV
IO19Err: Surprise Link Down Error Status
IO0Err: Data Link Protocol Error Status
Reserved
4
0
3:1
0
0h
0
RWCST
IO3Err:Training Error Status
This field should not be used for obtaining Training error status due to a
recent PCI Express Base Specification, Revision 1.0a Errata Dec 2003 to
remove training error.
3.8.12.3
UNCERRSTS[0] - Uncorrectable Error Status For ESI Port
This register identifies uncorrectable errors detected on ESI Port. If an error occurs and
is unmasked in the detect register (EMASK_UNCOR_PEX), the appropriate error bit will
be recorded in this register. If an error is recorded in the UNCERRSTS register and the
appropriate bit (along with the severity bit of the UNCERRSEV register) determines
which bit in the PEX_FAT_FERR, PEX_NF_COR_FERR, PEX_FAT_NERR,
PEX_NF_COR_NERR registers get recorded. These error log registers are described
starting from Section 3.8.12.24.
Device:
Function:
Offset:
0
0
104h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:22
21
RV
0h
0
0
0
0
0
0
0
0
0
0
Reserved
RWCST
RWCST
RV
IO18Err: ESI Reset time-out
20
IO2Err: Received an Unsupported Request
Reserved
19
18
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
IO9Err: Malformed TLP Status
IO10Err: Receiver Buffer Overflow Status
IO8Err: Unexpected Completion Status
IO7Err: Completer Abort Status
IO6Err: Completion Time-out Status
IO5Err: Flow Control Protocol Error Status
IO4Err: Poisoned TLP Status
17
16
15
14
13
12
®
162
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0
Function:
Offset:
0
104h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
11:6
5
RV
0h
0
Reserved
RWST
RWCST
RV
IOErr: Surprise Link Down Error Status
IO0Err: Data Link Protocol Error Status
Reserved
4
0
3:1
0
0h
0
RWCST
IO3Err:Training Error Status
Note: This field should not be used for obtaining Training error status
due to a recent PCI Express Base Specification, Revision 1.0a
Errata Dec 2003 to remove training error. Hardware behavior is
undefined.
3.8.12.4
UNCERRMSK[7:2] - Uncorrectable Error Mask
This register masks uncorrectable errors from the UNCERRSTS[2:7] register from being
signaled.
Device:
Function:
Offset:
2-3
0
108h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
108h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
108h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:21
20
19
18
17
16
15
14
13
12
11:6
5
RV
0h
0
Reserved
RWST
RV
IO2Msk: Received an Unsupported Request
Reserved
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RV
0
IO9Msk: Malformed TLP Status
IO10Msk: Receiver Buffer Overflow Mask
IO8Msk: Unexpected Completion Mask
IO7Msk: Completer Abort Status
IO6Msk: Completion Time-out Mask
IO5Msk: Flow Control Protocol Error Mask
IO4Msk: Poisoned TLP Mask
0
0
0
0
0
0
0h
0
Reserved
RWST
RWST
RV
IO19Msk: Surprise Link Down Error Mask
IO0Msk: Data Link Layer Protocol Error Mask
Reserved
4
0
3:1
0
000
0
RWST
IO3Msk:Training Error Mask
Note: This field should not be used for setting Training error Mask due to
a recent PCI Express Base Specification, Revision 1.0a Errata Dec
2003 to remove training error. Hardware behavior is undefined.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
163
Register Description
3.8.12.5
UNCERRMSK[0] - Uncorrectable Error Mask For ESI Port
This register masks uncorrectable errors from the UNCERRSTS[0] register (ESI port)
from being signaled.
Device:
Function:
Offset:
0
0
108h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:22
21
20
19
18
17
16
15
14
13
12
11:5
5
RV
0h
0
Reserved
RWST
RWST
RV
IO18Msk: ESI Reset time-out
IO2Msk: Received an Unsupported Request
Reserved
0
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RV
0
IO9Msk: Malformed TLP Status
IO10Msk: Receiver Buffer Overflow Mask
IO8Msk: Unexpected Completion Mask
IO7Msk: Completer Abort Status
IO6Msk: Completion Time-out Mask
IO5Msk: Flow Control Protocol Error Mask
IO4Msk: Poisoned TLP Mask
Reserved
0
0
0
0
0
0
0h
0
RWST
RWST
RV
IO19Msk: Surprise Link Down Error Mask
IO0Msk: Data Link Layer Protocol Error Mask
Reserved
4
0
3:1
0
000
0
RWST
IO3Msk:Training Error Mask
This field should not be used for setting Training error Mask due to a recent
PCI Express Base Specification, Revision 1.0a Errata Dec 2003 to remove
training error. Hardware behavior is undefined.
3.8.12.6
UNCERRSEV[0] - Uncorrectable Error Severity For ESI
Port
This register indicates the severity of the uncorrectable errors for the ESI port. An error
is reported as fatal when the corresponding error bit in the severity register is set. If
the bit is cleared, the corresponding error is considered non-fatal. If an error is
recorded in the UNCERRSTS register, the corresponding bit of UNCERRSEV determines
if the error gets reflected as a device fatal or nonfatal error in the PEX_FAT_FERR,
PEX_NF_COR_FERR, PEX_FAT_NERR, PEX_NF_COR_NERR registers.
Device:
Function:
Offset:
0
0
10Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:22
21
RV
0h
1
Reserved
RWST
RWST
RV
IO18Severity: ESI Reset time-out
IO2Severity: Received an Unsupported Request
Reserved
20
0
19
0
18
RWST
1
IO9Severity: Malformed TLP Severity
®
164
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0
Function:
Offset:
0
10Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
17
16
15
14
13
12
11:6
5
RWST
RWST
RWST
RWST
RWST
RWST
RV
1
0
IO10Severity: Receiver Buffer Overflow Severity
IO8Severity: Unexpected Completion Severity
IO7Severity: Completer Abort Status
IO6Severity: Completion Time-out Severity
IO5Severity: Flow Control Protocol Error Severity
IO4Severity: Poisoned TLP Severity
Reserved
0
0
1
0
0h
0
RWST
RWST
IO19 Severity: Surprise Link Down Severity
4
1
IO0Severity: Data Link Protocol Error Severity
(See Figure 3-17 in PCI Express Base Specification, Revision 1.0a)
3:1
0
RV
000
1
Reserved
RWST
IO3Severity:Training Error Severity
This field should not be used for setting Training error severity due to a
recent PCI Express Base Specification, Revision 1.0a Errata Dec 2003 to
remove training error. Hardware behavior is undefined.
3.8.12.7
UNCERRSEV[7:2] - Uncorrectable Error Severity
This register indicates the severity of the uncorrectable errors. An error is reported as
fatal when the corresponding error bit in the severity register is set. If the bit is
cleared, the corresponding error is considered non-fatal. If an error is recorded in the
UNCERRSTS register, the appropriate bit of UNCERRSEV determines if the error gets
reflected as a device fatal or nonfatal error in the PEX_FAT_FERR, PEX_NF_COR_FERR,
PEX_FAT_NERR, PEX_NF_COR_NERR registers.
Device:
Function:
Offset:
2-3
0
10Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
10Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
10Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:21
20
RV
0h
0
Reserved
RWST
RV
IO2Severity: Received an Unsupported Request
Reserved
19
0
18
RWST
RWST
RWST
RWST
1
IO9Severity: Malformed TLP Severity
IO10Severity: Receiver Buffer Overflow Severity
IO8Severity: Unexpected Completion Severity
IO7Severity: Completer Abort Status
17
1
16
0
15
0
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
165
Register Description
Device:
Function:
Offset:
2-3
0
10Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
10Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
10Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
14
13
12
11:6
5
RWST
RWST
RWST
RV
0
1
IO6Severity: Completion Time-out Severity
IO5Severity: Flow Control Protocol Error Severity
IO4Severity: Poisoned TLP Severity
Reserved
0
0h
0
RWST
RWST
IO19Severity: Surprise Link Down Severity
4
1
IO0Severity: Data Link Protocol Error Severity
(See Figure 3-17 in PCI Express Base Specification, Revision 1.0a)
3:1
0
RV
000
1
Reserved
RWST
IO3Severity:Training Error Severity
This field should not be used for setting Training error severity due to a
recent PCI Express Base Specification, Revision 1.0a Errata Dec 2003 to
remove training error. Hardware behavior is undefined.
3.8.12.8
CORERRSTS[7:2, 0] - Correctable Error Status
This register identifies which unmasked correctable error has been detected. The error
is directed to the respective device correctable error bit in the PEX_NF_COR_FERR,
PEX_NF_COR_NERR registers (If the error is unmasked in the CORERRMSK register
defined in Section 3.8.12.9). These registers are discussed starting from
Section 3.8.12.25.
Device:
Function:
Offset:
0, 2-3
0
110h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
110h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
110h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:13
12
RV
0h
0
Reserved
RWCST
RV
IO16Err: Replay Timer Time-out Status
Reserved
11:9
8
0h
0
RWCST
IO15Err: Replay_Num Rollover Status
®
166
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
110h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
110h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
110h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7
6
RWCST
RWCST
RV
0
0
IO14Err: Bad DLLP Status
IO13Err: Bad TLP Status
Reserved
5:1
0
0h
0
RWCST
IO12Err: Receiver Error Status
3.8.12.9
CORERRMSK[7:2, 0] - Correctable Error Mask
This register masks correctable errors from being signalled. They are still logged in the
CORERRSTS register.
Device:
Function:
Offset:
0, 2-3
0
114h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
114h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
114h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:13
12
11:9
8
RV
0h
0
Reserved
RWST
RV
IO16Msk: Replay Timer Time-out Mask
Reserved
0h
0
RWST
RWST
RWST
RV
IO15Msk: Replay_Num Rollover Mask
IO14Msk: Bad DLLP Mask
IO13Msk: Bad TLP Mask
Reserved
7
0
6
0
5:1
0
0h
0
RWST
IO12Msk: Receiver Error Mask
3.8.12.10 AERRCAPCTRL[7:2, 0] - Advanced Error Capabilities and Control
Register
This register identifies the capability structure and points to the next structure.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
167
Register Description
Device:
Function:
Offset:
0, 2-3
0
118h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
118h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
118h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:9
8
RV
RO
0h
0
Reserved
ECRCCHKEN: ECRC Check Enable
This bit when set enables ECRC checking.
7
6
RO
RO
0
0
ECRCCHKCAP: ECRC Check Capable
Intel 5000P Chipset MCH does not support ECRC.
ECRCGENEN: ECRC Generation Enable
Intel 5000P Chipset MCH does not generate ECRC.
5
RO
0
ECRCGENCAP: ECRC Generation Capable
Intel 5000P Chipset MCH does not generate ECRC.
4:0
ROST
0h
FERRPTR: First error pointer
The First Error Pointer is a read-only register that identifies the bit position
of the first error reported in the Uncorrectable Error status register. Left
most error bit if multiple bits occurred simultaneously.
3.8.12.11 HDRLOG0[7:2, 0] - Header Log 0
This register contains the first 32 bits of the header log locked down when the first
uncorrectable error occurs. Headers of the subsequent errors are not logged.
Device:
Function:
Offset:
0, 2-3
0
11Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
11Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
11Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:0
ROST
0h
HDRLOGDW0: Header of TLP (DWORD 0) associated with first
uncorrectable error
3.8.12.12 HDRLOG1[7:2, 0] - Header Log 1
This register contains the second 32 bits of the header log.
®
168
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
120h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
120h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
120h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:0
ROST
0h
HDRLOGDW1: Header of TLP (DWORD 1) associated with error
3.8.12.13 HDRLOG2[7:2, 0] - Header Log 2
This register contains the third 32 bits of the header log.
Device:
Function:
0, 2-3
0
Offset:
124h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
124h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
124h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:0
ROST
0h
HDRLOGDW2: Header of TLP (DWORD 2) associated with error
3.8.12.14 HDRLOG3[7:2, 0] - Header Log 3
This register contains the fourth 32 bits of the header log.
Device:
Function:
0, 2-3
0
Offset:
128h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
128h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
128h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:0
ROST
0h
HDRLOGDW3: Header of TLP (DWORD 3) associated with error
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
169
Register Description
3.8.12.15 RPERRCMD[7:2, 0] - Root Port Error Command
This register controls behavior upon detection of errors.
Device:
Function:
Offset:
0, 2-3
0
12Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
12Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
12Ch
Version:
Intel 5000P Chipset
Bit
Attr
RV
Default
0h
Description
31:8
7:3
Reserved
Reserved
RV
0h
2
1
0
EN_FAT_ERR: FATAL Error Reporting Enable
Enable interrupt on fatal errors when set.
RW
RW
RW
0
0
0
EN_NONFAT_ERR: Non-FATAL Error Reporting Enable
Enable interrupt on a non-fatal (uncorrectable) error when set
EN_CORR_ERR: Correctable Error Reporting Enable
Enable interrupt on correctable errors when set
3.8.12.16 RPERRSTS[7:2, 0] - Root Error Status Register
The Root Error Status register reports status of error messages (ERR_COR,
ERR_NONFATAL, and ERR_FATAL) received by the Root Complex in the MCH, and errors
detected by the Root Port itself (which are treated conceptually as if the Root Port had
sent an error message to itself). The ERR_NONFATAL and ERR_FATAL messages are
grouped together as uncorrectable. Each correctable and uncorrectable (Non-fatal and
Fatal) error source has a first error bit and a next error bit associated with it
respectively. When an error is received by a Root Complex, the respective first error bit
is set and the Requestor ID is logged in the Error Source Identification register. A set
individual error status bit indicates that a particular error category occurred; software
may clear an error status by writing a 1 to the respective bit. If software does not clear
the first reported error before another error message is received of the same category
(correctable or uncorrectable), the corresponding next error status bit will be set but
the Requestor ID of the subsequent error message is discarded. The next error status
bit may be cleared by software by writing a 1 to the respective bit as well. This register
is updated regardless of the settings of the Root Control register in Section 3.8.11.12
and the Root Error Command register defined in Section 3.8.12.15.
®
170
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
130h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
130h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
130h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:27
RO
0h
ADVERR_INT_MSG_NUM: Advanced Error Interrupt Message Number
Advanced Error Interrupt Message Number offset between base message
data an the MSI message if assigned more than one message number to
be used of any status in this capability.
26:7
6
RV
0h
0
Reserved
RWCST
FAT_ERR_Rcvd: Fatal Error Messages Received
Set when one or more Fatal Uncorrectable error Messages
1
have been received.
5
RWCST
0
NFAT_ERR_Rcvd: Non-Fatal Error Messages Received
Set when one or more Non-Fatal Uncorrectable error
Messages have been received.
4
3
RWCST
RWCST
0
0
FRST_UNCOR_FATAL: First Uncorrectable Fatal
Set when the first Uncorrectable error message (which is FATAL) is
received.
MULT_ERR_NOFAT_ERR: Multiple ERR_FATAL NO FATAL_Received
Set when either a fatal or a non-fatal error message is received and
ERR_FAT_NONFAT_RCVD is already set, i.e log from the 2nd Fatal or No
fatal error message onwards
2
1
RWCST
RWCST
0
0
ERR_FAT_NOFAT_RCVD: ERROR FATAL NOFATAL Received
Set when either a fatal or a non-fatal error message is received and this bit
is already not set. That is, log the first error message
MULT_ERR_COR_RCVD: Multiple Correctable Error Received
Set when either a correctable error message is received and
ERR_CORR_RCVD is already set, i.e log from the 2nd Correctable error
message onwards
0
RWCST
0
ERR_CORR_RCVD: First Correctable Error Received
Set when a correctable error message is received and this bit is already not
set. That is, log the first error message
Notes:
1. This applies to both internal generated Root port errors and those messages received from an external source.
3.8.12.17 RPERRSID[7:2, 0] - Error Source Identification Register
The Error Source Identification register identifies the source (Requestor ID) of first
correctable and uncorrectable (Non-fatal/Fatal) errors reported in the Root Error Status
register defined in Section 3.8.12.16. This register is updated regardless of the settings
of the Root Control register defined in Section 3.8.11.12 and the Root Error Command
register defined in.Section 3.8.12.15.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
171
Register Description
Device:
Function:
Offset:
0, 2-3
0
134h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
134h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
134h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:16
ROST
0h
ERR_FAT_NOFAT_SID: Fatal No Fatal Error Source ID Requestor ID of
the source when an Fatal or No Fatal error is received and the
ERR_FAT_NOFAT_RCVD bit is not already set. i.e log ID of the first Fatal or
Non Fatal error
15:0
ROST
0h
ERR_CORR_SID: Correctable Error Source ID
Requestor ID of the source when a correctable error is received and the
ERR_CORR_RCVD is not already set. i.e log ID of the first correctable error.
3.8.12.18 Intel 5000P Chipset MCH SPCAPID[7:2, 0] - MCH Specific Capability ID
This register identifies the capability structure and points to the next structure.
Device:
Function:
Offset:
0, 2-3
0
140h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
140h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
140h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
NXTCAPOFF: Next Capability Offset
31:20
RO
0h
This field points to the next Capability in extended configuration space. It is
set 000h since this is the final structure in the chain.
19:16
15:0
RO
RO
0h
0h
VN: Version Number
Version number for this capability structure.
EXTCAPID: Extended CAP_ID
3.8.12.19 PEX_ERR_DOCMD[7:2, 0] - PCI Express Error Do Command Register
Link Error Commands for doing the various signaling: ERR[2:0] and MCERR.
®
172
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
144h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
144h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
144h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:8
RV
0h
Reserved.
PEX_RP_FAT_MAP: Root Port steering for fatal errors
00: ERR[0]
01: ERR[1]
7:6
RW
00
10: ERR[2]
11: MCERR
The Root Port Fatal errors are routed to one of the ERR[2:0] pins or MCERR.
PEX_RP_NF_MAP: Root Port steering for non-fatal errors
00: ERR[0],
01: ERR[1]
5:4
RW
00
10: ERR[2]
11: MCERR
The Root Port Non Fatal (uncorrectable) errors are routed to one of the
ERR[2:0] pins or MCERR.
PEX_RP_CORR_MAP: Root Port steering for correctable errors
00: ERR[0],
01: ERR[1]
3:2
RW
00
10: ERR[2]
11: MCERR
The Root Port correctable errors are routed to one of the ERR[2:0] pins or
MCERR.
PEX_DEV_UNSUP_MAP:
Report steering for unsupported request errors (master aborts) for legacy
devices.
00: ERR[0]
01: ERR[1]
10: ERR[2]
11: MCERR
1:0
RW
00
Unsupported request error report enable is in the Device control register. This
is Error IO2.
3.8.12.20 EMASK_UNCOR_PEX[0] - Uncorrectable Error Detect Mask For ESI
This register masks (blocks) the detection of the selected error bits for the ESI port.
When a specific error is blocked, it does NOT get reported or logged.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
173
Register Description
Device:
Function:
Offset:
0
0
148h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:22
21
RV
RW
RW
RV
0h
0
Reserved
IO18DMIRstDetMsk: ESI Reset time-out
IO2DetMsk: Received an Unsupported Request
Reserved
20
0
19
0
18
RW
RW
RW
RW
RW
RW
RW
RV
0
IO9DetMsk: Malformed TLP Status
IO10DetMsk: Receiver Buffer Overflow Status
IO8DetMsk: Unexpected Completion Status
IO7DetMsk: Completer Abort Status
IO6DetMsk: Completion Time-out Status
IO5DetMsk: Flow Control Protocol Error Status
IO4DetMsk: Poisoned TLP Status
Reserved
17
0
16
0
15
0
14
0
13
0
12
0
11:5
4
0h
0
RW
RV
IO0DetMsk: Data Link Protocol Error Status
Reserved
3:1
0
0h
0
RW
IO3DetMsk:Training Error Status
This field should not be used for setting Training error severity due to a recent
PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware behavior is
undefined.
3.8.12.21 EMASK_UNCOR_PEX[7:2] - Uncorrectable Error Detect Mask
This register masks (blocks) the detection of the selected error bits. When a specific
error is blocked, it does NOT get reported or logged.
Device:
Function:
Offset:
2-3
0
148h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
148h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
148h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:21
20
RV
RW
RV
0h
0
Reserved
IO2DetMsk: Received an Unsupported Request
Reserved
19
0
18
RW
RW
RW
0
IO9DetMsk: Malformed TLP Status
IO10DetMsk: Receiver Buffer Overflow Status
IO8DetMsk: Unexpected Completion Status
17
0
16
0
®
174
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
2-3
Function:
Offset:
0
148h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
148h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
148h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
IO7DetMsk: Completer Abort Status
15
14
13
12
11:6
5
RW
RW
RW
RW
RV
0
0
IO6DetMsk: Completion Time-out Status
IO5DetMsk: Flow Control Protocol Error Status
IO4DetMsk: Poisoned TLP Status
Reserved
0
0
0h
0
RW
RW
RV
IO19DetMsk: Surprise Link Down Mask
IO0DetMsk: Data Link Protocol Error Status
Reserved
4
0
3:1
0
0h
0
RW
IO3DetMsk:Training Error Status
This field should not be used for setting Training error severity due to a recent
PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware behavior is
undefined.
3.8.12.22 EMASK_COR_PEX[7:2, 0] - Correctable Error Detect Mask
This register masks (blocks) the detection of the selected bits. Normally all are
detected. But software can choose to disable detecting any of the error bits.
Device:
Function:
Offset:
0, 2-3
0
14Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
14Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
14Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:13
12
RV
RW
RV
0h
0
Reserved
IO16DetMsk: Replay Timer Time-out Mask
Reserved
11:9
8
0h
0
RW
RW
RW
RV
IO15DetMsk: Replay_Num Rollover Mask
IO14DetMsk: Bad DLLP Mask
IO13DetMsk: Bad TLP Mask
Reserved
7
0
6
0
5:1
0h
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
175
Register Description
Device:
Function:
Offset:
0, 2-3
0
14Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
14Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
14Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
IO12DetMsk: Receiver Error Mask
0
RW
0
3.8.12.23 EMASK_RP_PEX[7:2, 0] - Root Port Error Detect Mask
This register masks (blocks) the detection of the selected bits associated with the root
port errors. Normally, all are detected.
Device:
Function:
Offset:
0, 2-3
0
150h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
150h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
150h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:3
RV
RW
RW
RW
0h
0
Reserved
2
1
0
IO1DetMsk: Fatal Message Detect Mask
0
IO11DetMsk: Uncorrectable Message Detect Mask
IO17DetMsk: Correctable Message Detect Mask
0
3.8.12.24 PEX_FAT_FERR[7:2, 0] - PCI Express First Fatal Error Register
This register records the occurrence of the first unmasked PCI Express FATAL errors
and written by the MCH if the respective bits are not set prior. The classification of
uncorrectable errors into FATAL is based on the severity level of the UNCERRSEV
register described in Section 3.8.12.7.
®
176
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
154h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
154h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
154h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:13
RV
0h
0
0
0
0
0
0
0
0
0
0
Reserved
12
11
10
9
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
FIRST_FAT_Err_IO19: Surprise Link Down Status
First_FAT_Err_IO18: ESI Reset time-out
First_FAT_Err_IO9: PEX - Malformed TLP
First_FAT_Err_IO10: PEX - Receive Buffer Overflow Error
First_FAT_Err_IO8: PEX - Unexpected Completion Error
First_FAT_Err_IO7: PEX - Completer Abort
First_FAT_Err_IO6: PEX - Completion Timeout
First_FAT_Err_IO5: PEX - Flow Control Protocol Error
First_FAT_Err_IO4: PEX - Poisoned TLP
8
7
6
5
4
3
First_FAT_Err_IO3: PEX - Training Error
This field should not be used for setting Training error severity due to a
recent PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware
behavior is undefined.
2
1
0
RWCST
RWCST
RWCST
0
0
0
First_FAT_Err_IO2: PEX - Received Unsupported Request
First_FAT_Err_IO1: PEX - Received Fatal Error Message
First_FAT_Err_IO0: PEX - Data Link Layer Protocol Error
3.8.12.25 PEX_NF_COR_FERR[7:2, 0] - PCI Express First Non-Fatal or
Correctable Error Register
This register records the occurrence of the first unmasked PCI Express NON-FATAL
(Uncorrectable) and CORRECTABLE errors. These errors are written by the MCH if the
respective bits are not set prior. The classification of uncorrectable errors into FATAL or
Non-Fatal is based on the UNCERRSEV register described in Section 3.8.12.7.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
177
Register Description
.
Device:
Function:
Offset:
0, 2-3
0
158h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
158h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
158h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:18
17
RV
0h
0
Reserved
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
First_NFAT_Corr_Err_IO19: Surprise Link Down (uncorrectable)
First_NFAT_COR_Err_IO17: PEX - Received Correctable Error Message
First_NFAT_COR_Err_IO16: PEX - Replay Timer Timeout (correctable)
First_NFAT_COR_Err_IO15: PEX - Replay_Num Rollover (correctable)
First_NFAT_COR_Err_IO14: PEX - BAD DLLP Error (correctable)
First_NFAT_COR_Err_IO13: PEX - Bad TLP Error (correctable)
First_NFAT_COR_Err_IO12: PEX - Receiver Error (correctable)
16
0
15
0
14
0
13
0
12
0
11
0
10
0
First_NFAT_COR_Err_IO11: PEX - Received Non Fatal (uncorrectable)
Error Message
9
RWCST
0
First_NFAT_COR_Err_IO10: PEX - Receive Buffer Overflow Error
(uncorrectable)
8
7
RWCST
RWCST
0
0
First_NFAT_COR_Err_IO9: PEX -Malformed TLP (uncorrectable)
First_NFAT_COR_Err_IO8: PEX - Unexpected Completion Error
(uncorrectable)
6
5
4
RWCST
RWCST
RWCST
0
0
0
First_NFAT_COR_Err_IO7: PEX - Completer Abort (uncorrectable)
First_NFAT_COR_Err_IO6: PEX - Completion Timeout (uncorrectable)
First_NFAT_COR_Err_IO5: PEX - Flow Control Protocol Error
(uncorrectable)
3
2
RWCST
RWCST
0
0
First_NFAT_COR_Err_IO4: PEX - Poisoned TLP (uncorrectable)
First_NFAT_COR_Err_IO3: PEX - Training Error (uncorrectable)
This field should not be used for setting Training error severity due to a
recent PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware
behavior is undefined.
1
0
RWCST
RWCST
0
0
First_NFAT_COR_Err_IO2: PEX - Received Unsupported Request
(uncorrectable)
First_NFAT_COR_Err_IO0: PEX - Data Link Layer Protocol Error
(uncorrectable)
3.8.12.26 PEX_FAT_NERR[7:2, 0] - PCI Express Next Fatal Error Register
This register records the subsequent occurrences after the first unmasked PCI Express
FATAL errors and written by the MCH if the respective bits are set in the PEX_FERR_FAT
register.
®
178
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
0, 2-3
Function:
Offset:
0
15Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
15Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
15Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:13
RV
0h
0
0
0
0
0
0
0
0
0
0
Reserved
12
11
10
9
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
Next_FAT_Err_IO19: Surprise Link Down
Next_FAT_Err_IO18: ESI Reset time-out
Next_FAT_Err_IO9: PEX - Malformed TLP
Next_FAT_Err_IO10: PEX - Receive Buffer Overflow Error
Next_FAT_Err_IO8: PEX - Unexpected Completion Error
Next_FAT_Err_IO7: PEX - Completer Abort
Next_FAT_Err_IO6: PEX - Completion Timeout
Next_FAT_Err_IO5: PEX - Flow Control Protocol Error
Next_FAT_Err_IO4: PEX - Poisoned TLP
8
7
6
5
4
3
Next_FAT_Err_IO3: PEX - Training Error
This field should not be used for setting Training error severity due to a
recent PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware
behavior is undefined.
2
1
0
RWCST
RWCST
RWCST
0
0
0
Next_FAT_Err_IO2: PEX - Received Unsupported Request
Next_FAT_Err_IO1: PEX - Received Fatal Error Message
Next_FAT_Err_IO0: PEX - Data Link Layer Protocol Error
3.8.12.27 PEX_NF_COR_NERR[7:2, 0] - PCI Express Non Fatal or Correctable
Next Error Register
These errors are written by the MCH if the respective bits are set in PEX_NF_COR_FERR
register. This register records the subsequent occurrences of unmasked PCI Express
NON-FATAL (Uncorrectable) and CORRECTABLE errors.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
179
Register Description
Device:
Function:
Offset:
0, 2-3
0
160h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
160h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
160h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:18
17
RV
0h
0
Reserved
Next_NFAT_Corr_Err_IO19: Surprise Link Down
RWST
16
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
0
Next_NFAT_COR_Err_IO17: PEX - Received Correctable Error Message
Next_NFAT_COR_Err_IO16: PEX - Replay Timer Timeout (correctable)
Next_NFAT_COR_Err_IO15: PEX - Replay_Num Rollover (correctable)
Next_NFAT_COR_Err_IO14: PEX - BAD DLLP Error (correctable)
Next_NFAT_COR_Err_IO13: PEX - Bad TLP Error (correctable)
Next_NFAT_COR_Err_IO12: PEX - Receiver Error (correctable)
15
0
14
0
13
0
12
0
11
0
10
0
Next_NFAT_COR_Err_IO11: PEX - Received Non Fatal (uncorrectable)
Error Message
9
RWCST
0
Next_NFAT_COR_Err_IO10: PEX - Receive Buffer Overflow Error
(uncorrectable)
8
7
RWCST
RWCST
0
0
Next_NFAT_COR_Err_IO9: PEX -Malformed TLP (uncorrectable)
Next_NFAT_COR_Err_IO8: PEX - Unexpected Completion Error
(uncorrectable)
6
5
4
RWCST
RWCST
RWCST
0
0
0
Next_NFAT_COR_Err_IO7: PEX - Completer Abort (uncorrectable)
Next_NFAT_COR_Err_IO6: PEX - Completion Timeout (uncorrectable)
Next_NFAT_COR_Err_IO5: PEX - Flow Control Protocol Error
(uncorrectable)
3
2
RWCST
RWCST
0
0
Next_NFAT_COR_Err_IO4: PEX - Poisoned TLP (uncorrectable)
Next_NFAT_COR_Err_IO3: PEX - Training Error (uncorrectable)
This field should not be used for setting Training error severity due to a
recent PCI-SIG ECN (Jan 22, 04) to remove training error. Hardware
behavior is undefined.
1
0
RWCST
RWCST
0
0
Next_NFAT_COR_Err_IO2: PEX - Received Unsupported Request
(uncorrectable)
Next_NFAT_COR_Err_IO0: PEX - Data Link Layer Protocol Error
(uncorrectable)
3.8.12.28 PEX_UNIT_FERR[7:2, 0] - PCI Express First Unit Error Register
This register records the occurrence of the first unit errors that are specific to this PCI
Express port caused by external activities. For example, VPP error due to a
malfunctioning port on the SMBUS that did not receive acknowledge due to a PCI
Express hot-plug event. The unit errors are sent to the Coherency Engine to classify as
to which port cluster it came from ports 2-3 or ports 4-7 and the errors are recorded in
Coherency Engine and appropriate interrupts generated through ERR pins.
®
180
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
.
Device:
2-3
Function:
Offset:
0
168h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
168h
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
168h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:1
0
RV
0h
0
Reserved
RWCST
First_FAT_VPP_Err: VPP Error for PCI Express port
Records the occurrence of the first VPP error if this bit is not set prior.
Software clears this when the error has been serviced.
3.8.12.29 PEX_UNIT_NERR[7:2] - PCI Express Next Unit Error Register
This register records the occurrence of subsequent unit errors that are specific to this
PCI Express port caused by external activities. For example, VPP error due to a
malfunctioning port on the SMBUS that did not receive acknowledge due to a PCI
Express hot-plug event. The next unit errors are sent to the Coherency Engine
where the errors are further recorded and appropriate interrupts are generated through
ERR pins.
.
Device:
Function:
Offset:
2-3
0
16Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
16Ch
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
4-7
0
16Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:1
0
RV
0h
0
Reserved
RWCST
Next_FAT_VPP_Err: VPP Error for PCI Express port
Records the occurrence of subsequent VPP errors after the
PEX_UNIT_FERR.First_FAT_VP_ERR is set.
Software clears this when the error has been serviced.
3.8.12.30 PEX_SSERR[7:2,0]: PCI Express Stop and Scream Error Register
This register records the occurrence of stop and scream error due to data poisoning.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
181
Register Description
Device:
7-2, 0
Function: 0
Offset:
170h
Bit
Attr
Default
Description
RV
0h
7:1
Reserved
SSErr: Stop and Scream Error for PCI Express port
0
RWCST
0
Records the occurrence of the first stop and scream error on the PCI
Express port if this bit is clear.
3.8.13
Error Registers
This section describes the registers that record the first and next errors, logging,
detection masks, signalling masks, and error injection control. The FERR_GLOBAL (first
error register) is used to record the first error condition. The NERR_GLOBAL register is
used to record subsequent errors.
The contents of FERR_GLOBAL and NERR_GLOBAL are “sticky” across a reset (while
PWRGOOD remains asserted). This provides the ability for firmware to perform
diagnostics across reboots. Note that only the contents of FERR_GLOBAL affects the
update of the any error log registers.
3.8.13.1
FERR_GLOBAL - Global First Error Register
The first fatal and/or first non-fatal errors are flagged in the FERR_GLOBAL register,
subsequent errors are indicated in the NERR_GLOBAL register.
3.8.13.2
NERR_GLOBAL - Global Next Error Register
Once an error has been logged in the FERR_GLOBAL, subsequent errors are logged in
the NERR_GLOBAL register.
.
Device:
Function:
Offset:
16
2
44h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31
RWCST
0
Global_NERR_31:
Internal Fatal Error
30
29
28
RWCST
RWCST
RWCST
0
0
0
Global_NERR_30:
DMA Engine Device Fatal Error
Global_NERR_29:
FSB1 Fatal Error
Global_NERR_28:
FSB 0 Fatal Error
27:25
24
RV
0
0
Reserved
RWCST
Global_NERR_24:
FB-DIMM Channel 0,1,2 or 3 Fatal Error
23
22
RWCST
RWCST
0
0
Global_NERR_23:
PCI Express Device 7 Fatal Error
Global_NERR_22:
PCI Express Device 6 Fatal Error
®
182
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
16
Function:
Offset:
2
44h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
21
RWCST
0
Global_NERR_21:
PCI Express Device 5 Fatal Error
20
19
18
RWCST
RWCST
RWCST
0
0
0
Global_NERR_20:
PCI Express Device 4 Fatal Error
Global_NERR_19:
PCI Express Device 3 Fatal Error
Global_NERR_18:
PCI Express Device 2 Fatal Error
17
16
RV
0
0
Reserved
RWCST
Global_NERR_16:
ESI Fatal Error
15
14
13
12
RWCST
RWCST
RWCST
RWCST
0
0
0
0
Global_NERR_15:
Internal Intel 5000P Chipset MCH Non-Fatal Error
Global_NERR_14:
DMA Engine Device Non Fatal Error
Global_NERR_13:
FSB1 Non-Fatal Error
Global_NERR_12:
FSB 0 Non-Fatal Error
11:9
8
RV
0h
0
Reserved
RWCST
Global_NERR_08:
FB-DIMM Channel 0,1, 2 or 3 Non-Fatal Error
7
6
5
4
3
2
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
0
0
0
0
0
0
Global_NERR_07:
PCI Express Device 7 Non-Fatal Error
Global_NERR_06:
PCI Express Device 6 Non-Fatal Error
Global_NERR_05:
PCI Express Device 5 Non-Fatal Error
Global_NERR_04:
PCI Express Device 4 Non-Fatal Error
Global_NERR_03:
PCI Express Device 3 Non-Fatal Error
Global_NERR_02:
PCI Express Device 2 Non-Fatal Error
1
0
RV
0
0
Reserved
RWCST
Global_NERR_00:
ESI Non-Fatal Error
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
183
Register Description
3.8.13.3
FERR_FAT_FSB[1:0]: FSB First Fatal Error Register
Device:
Function:
Offset:
16
0
480h, 180h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
5
RV
RWCST
RV
00
0
Reserved
F9Err: FSB protocol Error
Reserved
4
0h
0
3
RWCST
RV
F2Err: Unsupported Processor Bus Transaction
Reserved
2:1
0
0h
0
RWCST
F1Err: Request/Address Parity Error
3.8.13.4
FERR_NF_FSB[1:0]: FSB First Non-Fatal Error Register
Device:
Function:
Offset:
16
0
481h, 181h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:3
2
RV
00000
Reserved
RWCST
RWCST
RWCST
0
0
0
F7Err: Detected MCERR from a processor
F8Err: Detected BINIT from a processor
F6Err: Parity Error in Data from FSB Interface
1
0
3.8.13.5
NERR_FAT_FSB[1:0]: FSB Next Fatal Error Register
This register logs all FSB subsequent errors after the FERR_FAT_FSB has logged the 1st
fatal error.
.
Device:
Function:
Offset:
16
0
482h, 182h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
5
RV
RWCST
RV
00
0
Reserved
F9Err: FSB protocol Error
Reserved
4
0h
0
3
RWCST
RV
F2Err: Unsupported Processor Bus Transaction
Reserved
2:1
0
0h
0
RWCST
F1Err: Request/Address Parity Error
3.8.13.6
NERR_NF_FSB[1:0]: FSB Next Non-Fatal Error Register
This register logs all FSB subsequent errors after the FERR_NF_FSB has logged the 1st
fatal error.
®
184
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
.
Device:
16
Function:
Offset:
0
483h, 183h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:3
2
RV
00000
Reserved
RWCST
RWCST
RWCST
0
0
0
F7Err: Detected MCERR from a processor
F8Err: Detected BINIT from a processor
F6Err: Parity Error in Data from FSB Interface
1
0
3.8.13.7
NRECFSB[1:0]: Non Recoverable FSB Error Log Register
FSB Log registers for non recoverable errors when a fatal error is logged in its
corresponding FERR_FAT_FSB Register.
Device:
Function:
Offset:
16
0
484h, 184h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:29
28:24
23:21
20:16
15:8
RV
000
00000
000
Reserved
ROST
ROST
ROST
ROST
ROST
REQA: REQa[4:0] fields of the FSB
REQB: REQb[2:0] fields of the FSB
EXF: EXF[4:0] fields of the FSB
ATTR: ATTR[7:0] fields of the FSB
DID: DID[7:0] fields of the FSB
00000
00h
7:0
00h
3.8.13.8
RECFSB[1:0]: Recoverable FSB Error Log Register
The following error log registers captures the FSB fields on the logging of an error in
the corresponding FERR_NF_FSB Register.
Device:
Function:
Offset:
16
0
488h, 188h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:29
28:24
23:21
20:16
15:8
RV
000
00000
000
Reserved
ROST
ROST
ROST
ROST
ROST
REQA: REQa[4:0] fields of the FSB
REQB: REQb[2:0] fields of the FSB
EXF: EXF[4:0] fields of the FSB
ATTR: ATTR[7:0] fields of the FSB
DID: DID[7:0] fields of the FSB
00000
00h
7:0
00h
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
185
Register Description
3.8.13.9
NRECADDRL[1:0]: Non Recoverable FSB Address Low Error Log
Register
This register captures the lower 32 bits of the FSB address for non recoverable errors
when a fatal error is logged in its corresponding FERR_FAT_FSB Register. This register
is only valid for Request FSB Errors.
.
Device:
Function:
Offset:
16
0
48Ch, 18Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:4
3
ROST
ROST
RV
0h
0
A31DT4: FSB Address [31:4]
A3: FSB Address [3]
Reserved
2:0
000
3.8.13.10 NRECADDRH[1:0]: Non Recoverable FSB Address High Error Log
Register
This register captures the upper 8 bits of the FSB address for non recoverable errors
when a fatal error is logged in its corresponding FERR_FAT_FSB Register. This register
is only valid for Request FSB Errors.
.
Device:
Function:
Offset:
16
0
490h, 190h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
A39DT32: FSB Address [39:32]
7:0
ROST
00h
3.8.13.11 EMASK_FSB[1:0]: FSB Error Mask Register
A ‘0’ in any field enables that error.
Device:
Function:
Offset:
16
0
492h, 192h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:9
8
RV
0h
1
Reserved
RWST
RWST
RWST
RWST
RV
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
7
1
6
1
5
1
4
0h
0h
0h
1
3
RV
Reserved
2
RV
Reserved
1
RWST
RWST
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
0
1
®
186
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.13.12 ERR2_FSB[1:0]: FSB Error 2 Mask Register
This register enables the signaling of Err[2] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
.
Device:
Function:
Offset:
16
0
498h, 198h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:9
8
RV
0h
1
Reserved
RWST
RWST
RWST
RWST
RV
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
7
1
6
1
5
1
4
0
3
RV
0h
0h
1
Reserved
2
RV
Reserved
1
RWST
RWST
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
0
1
3.8.13.13 ERR1_FSB[1:0]: FSB Error 1 Mask Register
This register enables the signaling of Err[1] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
Device:
Function:
Offset:
16
0
496h, 196h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:9
8
RV
0h
1
Reserved
RWST
RWST
RWST
RWST
RV
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
7
1
6
1
5
1
4
0h
0h
0h
1
3
RV
Reserved
2
RV
Reserved
1
RWST
RWST
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
0
1
3.8.13.14 ERR0_FSB[1:0]: FSB Error 0 Mask Register
This register enables the signaling of Err[0] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
187
Register Description
Device:
Function:
Offset:
16
0
494h, 194h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:9
8
RV
0h
1
Reserved
RWST
RWST
RWST
RWST
RV
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
7
1
6
1
5
1
4
0h
0h
0h
1
3
RV
Reserved
2
RV
Reserved
1
RWST
RWST
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
0
1
3.8.13.15 MCERR_FSB[1:0]: FSB MCERR Mask Register
This register enables the signaling of MCERR when an error flag is set. Note that one
and only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
Device:
Function:
Offset:
16
0
49Ah, 19Ah
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:9
8
RV
0h
1
Reserved
RWST
RWST
RWST
RWST
RV
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
7
1
6
1
5
1
4
0h
0h
0h
1
3
RV
Reserved
2
RV
Reserved
1
RWST
RWST
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
0
1
®
188
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.8.13.16 NRECSF - Non-Recoverable Error Control Information of Snoop Filter
3.8.13.17 RECSF - Recoverable Error Control Information of Snoop Filter
Device:
Function:
Offset:
16
2
B0h
Version:
Intel 5000X Chipset
Bit
Attr
Default
Description
63:38
37
RV
0h
0
Reserved
ROST
ROST
ROST
ROST
ROST
ROST
Hit(1), Miss(0)
Tag(A[39:19])
Set(A[18:7])
Interleave(A[6])
State
36:16
15:4
3
0h
000h
0
2
0
1:0
00
Presence Vector
Device:
Function:
Offset:
16
2
B8h
Intel 5000X Chipset
Version:
Bit
Attr
Default
Description
63:38
37
RV
0h
0
Reserved
ROST
ROST
ROST
ROST
ROST
ROST
Hit(1), Miss(0)
Tag(A[39:19])
Set(A[18:7])
Interleave(A[6])
State
36:16
15:4
3
0h
000h
0
2
0
1:0
00
Presence Vector
3.8.13.18 FERR_FAT_INT - Internal First Fatal Error Register
FERR_FAT _INT latches the first MCH internal fatal error. All subsequent errors get
logged in the NERR_FAT_INT.
Device:
Function:
Offset:
16
2
C0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:5
4
RV
000
0
Reserved
RWCST
RV
B7Err: Multiple ECC error in any of the ways during SF lookup
Reserved
3
0
2
RWCST
RWCST
RWCST
0
B3Err: Coherency Violation Error for WEWB
B2Err: Multi-Tag Hit SF
1
0
0
0
B1Err: DM Parity Error
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
189
Register Description
3.8.13.19 FERR_NF_INT - Internal First Non-Fatal Error Register
Device:
Function:
Offset:
16
2
C1h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:3
2
RV
0h
0
Reserved
RWCST
RWCST
RWCST
B8Err: SF Coherency Error for BIL (SF)
B6Err: Single ECC error on SF lookup (SF)
B5Err: Single Address Map Error (COH)
1
0
0
0
3.8.13.20 NERR_FAT_INT - Internal Next Fatal Error Register
Device:
Function:
Offset:
16
2
C2h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:5
4
RV
000
0
Reserved
RWCST
RV
B7Err: Multiple ECC error in any of the ways during SF lookup (SF)
Reserved
3
0
2
RWCST
RWCST
RWCST
0
B3Err: Coherency Violation Error (COH) for EWB
B2Err: Multi-Tag Hit SF (SF)
1
0
0
0
B1Err: DM Parity Error (DM)
3.8.13.21 NERR_NF_INT - Internal Next Non-Fatal Error Register
Device:
Function:
Offset:
16
2
C3h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:3
2
RV
0h
0
Reserved
RWCST
RWCST
RWCST
B8Err: SF Coherency Error for BIL (SF)
B6Err: Single ECC error on SF lookup (SF)
B5Err: Address Map Error (COH)
1
0
0
0
3.8.13.22 NRECINT - Non Recoverable Internal MCH Error Log Register
This register will log non-recoverable errors (Fatal and Non Fatal) based on the internal
MCH errors that originate from the FERR_FAT_INT, FERR_NF_INT described starting
from Section 3.8.13.18. For debugging VPP errors in this register, for example, if
VPP_PEX_PORT2-3 is set, then software can scan the PCI Express configuration space
for unit errors logged in the device 2,3 for PEX_UNIT_FERR/NERR register as defined in
Section 3.8.12.28 to determine the failing port. The same can be repeated for the
FB-DIMM Channels when VPP_FBD is set.
®
190
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
16
Function:
Offset:
2
C4h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:21
20:13
12:11
10:8
RV
ROST
RV
0h
0h
Reserved
DM entry
Reserved
00
ROST
00000
Internal Block that detected the Failure
001: VPP_PEX_PORT2-3
010: VPP_PEX_PORT4-7
011: VPP_FBD
100: COH
101: DM
Others: Reserved
7
RV
0
Reserved
6:0
ROST
0h
COH Entry of Failed Location
3.8.13.23 RECINT - Recoverable Internal MCH Data Log Register
This register is not currently used as there are no correctable errors with in the internal
data path of the MCH.
Device:
Function:
Offset:
16
2
C8h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:21
20:13
12:11
10:8
RV
ROST
RV
0h
0h
Reserved
DM entry
Reserved
00
ROST
000
Internal Block that detected the Failure
001: VPP_PEX_PORT2-3
010: VPP_PEX_PORT4-7
011: VPP_FBD
101: COH
101: DM
Others: Reserved
7
RV
0
Reserved
6:0
ROST
00h
COH Entry of Failed Location
3.8.13.24 EMASK_INT - Internal Error Mask Register
A ‘0’ in any bit position enables the corresponding error.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
191
Register Description
Device:
Function:
Offset:
16
2
CCh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
B8Msk: SF Coherency Error for BIL
7
6
5
4
3
2
1
0
RV
1
1
1
1
1
1
1
1
RWST
RWST
RWST
RWST
RWST
RWST
RWST
B7Msk: Multiple ECC error in any of the ways during SF lookup
B6Msk: Single ECC error on SF lookup
B5Msk: Address Map Error
B4Msk: Virtual Pin Port Error
B3Msk: Coherency Violation Error for EWB
B2Msk: Multi-Tag Hit SF
B1Msk: DM Parity Error
3.8.13.25 ERR2_INT - Internal Error 2 Mask Register
This register enables the signaling of Err[2] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits.
Device:
Function:
Offset:
16
2
D2h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
B8Err2Msk: SF Coherency Error for BIL
7
6
5
4
3
2
1
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
1
1
1
1
1
1
1
1
B7Err2Msk: Multiple ECC error in any of the ways during SF lookup
B6Err2Msk: Single ECC error on SF lookup
B5Err2Msk: Address Map Error
B4Err2Msk: SMBus Virtual Pin Error
B3Err2Msk: Coherency Violation Error for EWB
B2Err2Msk: Multi-Tag Hit SF
B1Err2Msk: DM Parity Error
3.8.13.26 ERR1_INT - Internal Error 1 Mask Register
This register enables the signaling of Err[1] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits.
Device:
Function:
Offset:
16
2
D1h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
B8Err1Msk: SF Coherency Error for BIL
7
6
5
RWST
RWST
RWST
1
1
1
B7Err1Msk: Multiple ECC error in any of the ways during SF lookup
B6Err1Msk: Single ECC error on SF lookup
®
192
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
16
Function:
Offset:
2
D1h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
B5Err1Msk: Address Map Error
4
3
2
1
0
RWST
RWST
RWST
RWST
RWST
1
1
1
1
1
B4Err1Msk: SMBus Virtual Pin Error
B3Err1Msk: Coherency Violation Error
B2Err1Msk: Multi-Tag Hit SF
B1Err1Msk: DM Parity Error
3.8.13.27 ERR0_INT - Internal Error 0 Mask Register
This register enables the signaling of Err[0] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits.
Device:
Function:
Offset:
16
2
D0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
B8Err0Msk: SF Coherency Error for BIL
7
6
5
4
3
2
1
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
1
1
1
1
1
1
1
1
B7Err0Msk: Multiple ECC error in any of the ways during SF lookup
B6Err0Msk: Single ECC error on SF lookup
B5Err0Msk: Address Map Error
B4Err0Msk: SMBus Virtual Pin Error
B3Err0Msk: Coherency Violation Error for EWB
B2Err0Msk: Multi-Tag Hit SF
B1Err0Msk: DM Parity Error
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
193
Register Description
3.8.13.28 MCERR_INT - Internal MCERR Mask Register
This register enables the signaling of MCERR when an error flag is set. Note that one
and only one error signal should be enabled. Note that one and only one error signal
should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and MCERR_INT for each of
the corresponding bits.
Device:
Function:
Offset:
16
2
D3h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7
6
5
4
3
2
1
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
1
1
1
1
1
1
1
1
B8McErrMsk: SF Coherency Error for BIL
B7McErrMsk: Multiple ECC error in any of the ways during SF lookup
B6McErrMsk: Single ECC error on SF lookup
B5McErrMsk: Address Map Error
B4McErrMsk: SMBus Virtual Pin Error
B3McErrMsk: Coherency Violation Error for EWB
B2McErrMsk: Multi-Tag Hit SF
B1McErrMsk: DM Parity Error
3.9
Memory Control Registers
3.9.1
MC - Memory Control Settings
Miscellaneous controls not implemented in other registers.
Device:
Function:
Offset:
16
1
40h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31
30
RV
0
0
Reserved
RW
RETRY: Retry Enable
‘1’ = enables retry.
‘0’ = disables retry.
29
RV
0
Reserved
28:25
RW
0h
BADRAMTH: BADRAM Threshold
Number of consecutive instances of adjacent symbol errors required to mark a bad
device in a rank. Number of patrol scrub cycles required to decrement a non-
saturated BADCNT.
If Software desires to enable the “enhanced mode” and use the BADRAMTH, it
needs to set a non-zero value to this register field prior. Otherwise, a value of 0 is
considered illegal and memory RAS operations may lead to indeterministic
behavior.
24:22
21
RV
0
0
Reserved
RW
INITDONE: Initialization Complete. This scratch bit communicates software
state from Intel 5000P Chipset MCH to BIOS. BIOS sets this bit to 1 after
initialization of the DRAM memory array is complete. This bit has no effect on Intel
5000P Chipset MCH operation.
®
194
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
16
Function:
Offset:
1
40h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
RW
Default
Description
20
0
FSMEN: FSM enable.
‘1’ = Enables operation of DDR protocol. This can be used as a synchronous reset to
the FSM. (normal)
‘0’ = Inhibits processing of enqueued transactions. Disables all DRAM accesses
which means that the FB-DIMM link comes up, trains, goes to L0, sends NOPs, does
alerts, syncs, fast resets, AMB configurations, and so forth, but does not perform:
a) Memory reads
b) Memory writes
c) Refreshes
Not preserved by SAVCFG bit in the SYRE register.
19:18
RW
0h
ETHROT: DIMM Electrical Throttling Limit
Electrical throttling is required to prevent data corruption by limiting the number of
activates within a specific time interval and is enabled by MTR.ETHROTTLE register
bit.
For each rank in the DIMM, Maximum number of activates is four per sliding
electrical throttle window as defined below:
00: 10 clocks(DDR533)
01: 13 clocks(DDR667)
10: 15 clocks(DDR800)
11: 20 clocks(safe/conservative setting)
The Memory controller should stop sending more than 4 activates for each sliding
electrical throttle window. When the sliding window boundary crosses, the counter
is reset and the process repeats.
17
RW
0
GTW_MODE: Global Throttling window mode
This register field is used to reduce the Global throttling window size for the
purposes of debug/validation.
0: Global/open-loop throttling window of 16384*1344 (default, normal working
mode). If global throttling is enabled in this normal window, it will be held active for
16 global throttling windows without any DIMM exceeding GBLACT.
1: Global/open-loop throttling window of 4*1344 (debug, validation). If global
throttling is enabled in this debug window, it will be held active for 2 global
throttling windows without any DIMM exceeding GBLACT.
16
RW
0
MIRROR: Mirror mode enable
‘1’ = mirroring enabled
‘0’ = mirroring disabled.
FBDHPC.NEXTSTATE defines other characteristics of mirrored mode. The Intel
5000P Chipset MCH does not support mirroring while sparing is enabled: this bit
should not be set if SPCPC.SPAREN is set. The Intel 5000P Chipset MCH does not
support mirroring with demand scrub: this bit should not be set if DEMSEN is set.
Note: When MIRROR mode is enabled, both WAY0 and WAY1 of MIR register should
be set to 1. Otherwise, it is a programming error.
15:9
8
RV
0h
0
Reserved
RW
SCRBALGO: Scrub Algorithm for x8 uncorrectable error detection
0: Normal mode
1: Enhanced mode
7
RW
RW
0
SCRBEN: Patrol Scrub Enable
1: Enables patrol scrubbing.
0: Disables patrol scrubbing
The scrub engine will start the scrub operations from the beginning to the end of
the memory each time the SCRBEN register bit is set.
Note that SCRBEN should be disabled during MIR updates.
6
0
DEMSEN: Demand Scrub Enable
Enables demand scrubbing. This bit must not be set when MIRROR is set.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
195
Register Description
Device:
Function:
Offset:
16
1
40h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
ERRDETEN: Error Detection Enable
5
RW
0
‘1’ = Northbound CRC/ECC checking enabled.
‘0’ = Northbound CRC/ECC checking disabled
FB-DIMM “Alert” detection is disabled, status packets are ignored, northbound error
logging and data poisoning are disabled when Northbound CRC/ECC checking is
disabled.
4
RWC
RV
0
SCRBDONE: Scrub Complete
The scrub unit will set this bit to ‘1’ when it has completed scrubbing the entire
memory. Software should poll this bit after setting the Scrub Enable (SCRBEN) bit
to determine when the operation has completed. If the Scrub enable bit is cleared
midway during the scrub cycle, then the SCRBDONE bit will not be set and the Intel
5000P Chipset MCH will stop the scrub cycle immediately.
3:0
0h
Reserved
3.9.2
GBLACT - Global Activation Throttle Register
This register contains the hostel limit for Global Activation throttle control.
Device:
Function:
Offset:
16
1
60h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
RW
Default
Description
7:0
0
GBLACTLM: Global Activation Throttle Limit
This field controls the activation of Global throttling based on the number of
activates sampled per DIMM pair on each branch.
1
If the number of activates in the global throttling window exceeds the number
indicated by the GBLACTLM filed in this register, then global throttling is started by
setting the THRSTS[1:0].GBLTHRT bit for the respective branch and the Global
activation throttling logic to use the THRTMID register for throttling.
The granularity of this field is 65536 activations. Refer to Table 3-37
If Software sets this value greater than 168, the chipset will cap the GBLACTLM
field to 168.
Notes:
1. If (MC.GTW_MODE==1), then the global throttling window is 4*1344 cycles (debug, validation). Else if
(MC.GTW_MODE==0), then the window is set to 16384*1344 cycles (normal).
Table 3-37. Global Activation Throttling as a Function of Global Activation Throttling Limit
(GBLACTM) and Global Throttling Window Mode (GTW_MODE) Register Fields
Number of Activations
GBLACT.GBLACTM
Range (0.168)
MC.GTW_MODE=0
(16384*1344 window)
MC.GTW_MODE=1
(4*1344 window)
0
No Throttling
(unlimited activations)
No Throttling
(unlimited activations)
1
65536
131072
16
32
2
16
32
64
1048576
2097152
4194304
256
512
1024
®
196
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-37. Global Activation Throttling as a Function of Global Activation Throttling Limit
(GBLACTM) and Global Throttling Window Mode (GTW_MODE) Register Fields
Number of Activations
GBLACT.GBLACTM
Range (0.168)
MC.GTW_MODE=0
(16384*1344 window)
MC.GTW_MODE=1
(4*1344 window)
96
6291456
6553600
1536
1600
100
128
150
168
8388608
2048
9830400
2400
11010048 (100% BW)
2688 (100% BW)
3.9.3
THRTSTS[1:0] - Thermal Throttling Status Register
Device:
Function:
Offset:
16
1
6Ah, 68h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:9
8
RV
RO
0h
0h
Reserved
1
GBLTHRT: Global Activation Throttle
This field is set by the Intel 5000P Chipset MCH to indicate the start of the Global
Activation throttling based on the number of activates sampled in the global
window.
If the number of activates in the global window (16384*1344 cycles) exceeds the
number indicated by the GBLACTLM field in this register, then THRTSTS.GBLTHRT
bit is set to enable the Global activation throttling logic.
2
Global activation throttling logic will remain active until 16 (or 2) global throttling
windows in a row have gone by without any DIMM exceeding the
GBLACT.GBLACTLM register at which point this register field will be reset.
7:0
RO
0h
THRMTHRT: Thermal Throttle Value
This field holds the current activation throttling value based on the Intel 5000P
Chipset MCH/FB-DIMM throttling algorithm.
0: No throttling (unlimited activation)
1: 4 activations per activation window
2: 8 activations per activation window
168: 672 activations per activation window
This field will be set by the Intel 5000P Chipset MCH and the value of this field will
vary between THRTLOW and THRTHI registers based on the throttling.
Notes:
1. The Intel 5000P Chipset MCH will use an internal signal called GBLTHRT* from its combinatorial cluster for
controlling open loop throttling.
2. If MC.GTW_MODE=1, then the debug mode is enabled and the Intel 5000P Chipset MCH will use 2 windows
for global activation logic to be valid.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
197
Register Description
3.9.4
THRTLOW - Thermal Throttling Low Register
Device:
Function:
Offset:
16
1
64h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
RW
Default
Description
7:0
0h
THRTLOWLM: Thermal Throttle Low Limit
A base throttling level that is applied when the temperature is in the low range
(below Tlow) and THRTCTRL.THRMHUNT is set and the THRTSTS.GBLTHRT* bit is
not set by the Global Throttling Window logic.
Note: The GBLTHRT* is an internal signal from the Intel 5000P Chipset MCH open
loop combinatorial cluster before it is latched in the THRSTS.GLTHRT
register. This will prevent any stale/delayed information from being used
for the open loop throttling logic.
This base throttling is also enabled If THRTCTRL.THRMHUNT = 0 and
THRTSTS.GBLTHRT* bit =0.
The maximum value this field can be initialized by software is 168 (decimal). This
corresponds to 672 activations per activation (throttling) window and gives 100%
BW.
The granularity of this field is 4 activations.
0: No throttling (unlimited activation)
1: 4 activations per activation window
2: 8 activations per activation window
168: 672 activations per activation window
If Software sets this value greater than 168, the chipset will cap the THRTLOWLM
field to 168.
3.9.5
THRTMID - Thermal Throttle Mid Register
Device:
Function:
Offset:
16
1
65h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
RW
Default
Description
7:0
0h
THRTMIDLM: Thermal Throttle Middle Limit
A mid level throttling level that is applied when the temperature is in the middle
range (above Tlow but below Tmid) and THRTCTRL.THRMHUNT is set or the
THRTSTS.GBLTHRT* bit is set by the Global Throttling Window logic in the Intel
5000P Chipset MCH.
The maximum value this field can be initialized by software is 168 (decimal). This
corresponds to 672 activations per activation window and gives 100% BW.
The granularity of this field is 4 activations.
0: No throttling (unlimited activation)
1: 4 activations per activation window
2: 8 activations per activation window
168: 672 activations per activation window
If Software sets this value greater than 168, the chipset will cap the THRTMIDLM
field to 168. This field should be less than or equal to the THRTLOW.THRTLOWLM.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.6
THRTHI - Thermal Throttle High Register
Device:
Function:
Offset:
16
1
66h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
RW
Default
Description
THRTHILM: Thermal Throttle High Limit
7:0
0h
The highest level of throttling (that is, minimum number of activations). When
THRTCTRL.THRMODE=1, this level is applied whenever the temperature is above
Tmid. When THRTCTRL.THRMODE=0, this level is the ceiling of the hunting
algorithm of the closed loop throttling. The temperature being above Tmid has
priority over the Global Throttling Window enabling throttling (the higher throttling
level takes precedence).
This throttling will be enabled if THRTCTRL.THRMHUNT is set.
The maximum value this field can be initialized by software is 168 (decimal). This
corresponds to 672 activations per activation window and gives 100% BW.
The granularity of this field is 4 activations.
0: No throttling (unlimited activation)
1: 4 activations per activation window
2: 8 activations per activation window
168: 672 activations per activation window
If Software sets this value greater than 168, the chipset will cap the THRTHILM field
to 168. This field should be less than or equal to the THRTMID.THRTMIDLM.
3.9.7
THRTCTRL - Thermal Throttling Control Register
Device:
Function:
Offset:
16
1
67h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:2
1
RV
0h
0
Reserved
RW
THRMODE: Thermal Throttle Mode
0: THRTSTS.THRMTHRT register is initialized by the Intel 5000P Chipset MCH such
that they vary in range between THRTMID and THRTHI above Tmid (staircase)
1: THRTSTS.THRMTHRT register field is “slammed” to THRTHI above Tmid.
0
RW
0
THRMHUNT: Intelligent Thermal Throttle Enable
0: THRTSTS.THRMTHRT register is not enabled
1: THRTSTS.THRMTHRT register is enabled for the temperature to have any
influence on the throttle parameters. If THRMHUNT=0 only the GBLTHRT bit from
the Global Throttle Window can change the THRMTHRT register field.
3.9.8
MCA - Memory Control Settings A
Additional miscellaneous control not reflected in other registers.
Device:
Function:
Offset:
16
1
58h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:28
RW
0h
TO: Starvation Timeout
A value of zero represents eight cycles. Each increment adds eight cycles.
Maximum is 128 cycles.
27:15
RV
0h
Reserved
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
199
Register Description
Device:
Function:
Offset:
16
1
58h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
SCHDIMM: Single Channel DIMM Operation
14
RW
0
0: The MC assumes that the Intel 5000P Chipset MCH is operating normally, that is,
MC is not operating with only one FB-DIMM channel as in single channel mode.
1: In this mode, the Intel 5000P Chipset MCH MC will operate such that only 1
channel (that is, branch 0, channel 0) is active and there can be one or more
DIMMS present in Channel 0.
13:0
RV
0h
Reserved.
3.9.9
DDRFRQ - DDR Frequency Ratio
This register specifies the CORE:DDR frequency ratio.
Device:
Function:
Offset:
16
1
56h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
5:4
RV
RO
0000h Reserved1
00h
NOW: Present CORE:DDR Frequency Ratio
‘00’ = 1:1. for example, if BUSCLK=333 MHz, then DDR=667 MHz.
‘01’ = Reserved
‘10’ = 4:5. for example, if BUSCLK=266 MHz, then DDR=667 MHz.
‘11’ = 5:4. for example, if BUSCLK=333 MHz, then DDR=533 MHz.
This field will only specify the relationship between the CORE-domain and FB-
DIMM-domain clocks. This field does not indicate the frequency of the FB-DIMM
SCiD link... that is entirely determined by the frequency of the FBDCLK reference
clocks. To achieve successful FB-DIMM channel initialization, the frequency of the
FBDCLK reference clock must match the frequency of the FB-DIMM-domain clock.
E.g. if the BUSCLK=333 MHz and the NOW field specifies a ratio of 1:1, then
FB-DIMM channel initialization will succeed with an FBDCLK frequency of 333 MHz.
3:2
1:0
RV
00h
00
Reserved
RWST
NEXT: Future CORE:DDR Frequency Ratio
This frequency ratio will take effect and transfer to the “NOW” field after the next
Intel 5000P Chipset MCH hard reset.
‘00’ = 1:1. for example, if BUSCLK=333 MHz, then DDR=667 MHz.
‘01’ = Reserved
‘10’ = 4:5. for example, if BUSCLK=266 MHz, then DDR=667 MHz.
‘11’ = 5:4. for example, if BUSCLK=333 MHz, then DDR=533 MHz.
This field will only set the relationship between the CORE-domain and FB-DIMM-
domain clocks. This field will not set the frequency of the FB-DIMM SCiD link... that
is entirely determined by the frequency of the FBDCLK reference clocks. To achieve
successful FB-DIMM channel initialization, the frequency of the FBDCLK reference
clock must match the frequency of the FB-DIMM-domain clock. For example, if the
BUSCLK=333 MHz and the NEXT field specifies a ratio of 1:1, then after the next
Intel 5000P Chipset MCH hard reset, FB-DIMM channel initialization will succeed
with an FBDCLK frequency of 333 MHz.
3.9.10
FBDTOHOSTGRCFG0: FB-DIMM to Host Gear Ratio
Configuration 0
This register consists of 8 nibbles of mux select data for the proper selection of gearing
behavior on the FB-DIMM. This is the first of two registers to control the behavior for
the FB-DIMM to host (north bound) data flow.
®
200
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
16
Function:
Offset:
1
160h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:0
RWST
11111111h FBDHSTGRMUX: FB-DIMM to Host Clock Gearing mux selector.
Eight nibbles of mux select for memory/DDR2 to FSB/core geared clock
boundary crossing phase enables.
Refer to Table 3-38 for the programming details.
Table 3-38. FB-DIMM to Host Gear Ratio Mux
1
FSB:Memory Frequency
Gear Ratio
Value
333:333
267:267
400:400
1:1
11111111h
333:267
267:333
267:333
5:4
00023230h
00004323h
00002323h
4:5 (conservative)
4:5 (aggressive)
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
3.9.11
FBDTOHOSTGRCFG1: FB-DIMM to Host Gear Ratio
Configuration 1
This register consists of eight nibbles of mux select data for the proper selection of
gearing behavior on the FB-DIMM for the 1:1 and 4:5 modes.This is the second register
for FB-DIMM to Host gearing control.
Device:
Function:
Offset:
16
1
164h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:0
RWST
00000000h FBDHSTGRMUX: FB-DIMM to Host Clock Gearing mux selector.
Eight nibbles of mux select for memory/DDR2 to FSB/core geared clock
boundary crossing phase enables.
Refer to Table 3-39 for the programming details.
Table 3-39. FB-DIMM to Host Gear Ratio Mux
1
FSB:Memory Frequency
Gear Ratio
Value
333:333
267:267
400:400
1:1
00000000h
2
333:267
267:333
267:333
5:4
00000000h
00002000h
00000400h
4:5 (conservative)
4:5 (aggressive)
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
201
Register Description
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
2. Ignored by MGr registers in the 5:4 mode.
3.9.12
HOSTTOFBDGRCFG: Host to FB-DIMM Gear Ratio
Configuration
This register consists of eight nibbles of mux select data for the proper selection of
gearing behavior on the Host to FB-DIMM path (south bound).
Device:
Function:
Offset:
16
1
168h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:0
RWST
11111111h HSTFBDGRMUX: Host to FB-DIMM Clock Gearing mux selector.
Eight nibbles of mux select for FSB/core to memory/DDR2 geared clock
boundary crossing phase enables.
Refer to Table 3-40 for the programming details.
Table 3-40. Host to FB-DIMM Gear Ratio Mux Select
1
FSB:Memory Frequency
Gear Ratio
Value
333:333
267:267
400:400
1:1
11111111h
333:267
267:333
267:333
5:4
00004323h
00023230h
00023023h
4:5 (conservative)
4:5 (aggressive)
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
3.9.13
GRFBDVLDCFG: FB-DIMM Valid Configuration
This register provides valid signals to assert data in the FB-DIMM side for various
gearing ratios. It primarily affects the southbound data path for 4:5 gearing and
determines when a NOP packet is to be inserted into the FB-DIMM.
Device:
Function:
Offset:
16
1
16Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:0
RWST
0h
FBDVLDMUX: FB-DIMM Data Valid Mux selector.
Determines which valid host cycle to insert NOP. Refer toTable 3-41 for the
programming details. This primarily affects the 4:5 gearing ratio.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-41. FB-DIMM Host Data Cycle Valid Mux Select
1
FSB:Memory Frequency
Gear Ratio
Value
333:333
267:267
400:400
1:1
00h
2
333:267
267:333
267:333
5:4
00h
4:5 (conservative)
4:5 (aggressive)
01h
04h
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
2. Ignored by Mgr registers in the 5:4 mode.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
203
Register Description
3.9.14
GRHOSTFULLCFG: Host Full Flow Control Configuration
This register configures flow control when the host is full. It primarily effects the
Southbound data path and determines when the flow control signal to the core is
asserted.
Device:
Function:
Offset:
16
1
16Dh
Bit
Attr
RWST
Default
Description
FCMUX: Flow Control Mux Selector
7:0
0h
Configures Flow control on the host according to Table 3-42. This primarily
affect the 5:4 gearing ratio.
Table 3-42. FB-DIMM to Host Flow Control Mux Select
1
FSB:Memory Frequency
Gear Ratio
Value
333:333
267:267
400:400
1:1
00h
333:267
267:333
267:333
5:4
02h
02h
08h
4:5 (conservative)
4:5 (aggressive)
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
3.9.15
GRBUBBLECFG: FB-DIMM Host Bubble Configuration
This register provides valid signals to assert data in the FB-DIMM side for various
gearing ratios. This primarily affects the Northbound data path for the 5:4 configuration
and determines when a bubble is inserted when gearing up.
.
Device:
Function:
Offset:
16
1
16Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:0
RWST
0h
FBDBBLMUX: FB-DIMM Data Bubble Mux selector.
Configures bubbles in the host according to Table 3-43. This primarily affect
the 5:4 gearing ratio.
Table 3-43. FB-DIMM Bubble Mux Select
FSB:Memory Frequency
Gear Ratio
Value
333:333
267:267
400:400
1:1
00h
333:267
267:333
5:4
4:5
04h
1
00h
Notes:
1. Ignored by Mgr registers in 4:5 mode.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.16
GRFBDTOHOSTDBLCFG: FB-DIMM To Host Double
Configuration
This register provides valid signals to assert data in the FB-DIMM side for various
gearing ratios. This primarily affects the Northbound data path of the 4:5 config and
determines when both the lanes in core contain valid FB-DIMM data.
Device:
Function:
Offset:
16
1
16Fh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:0
RWST
0h
FBDHSTDBLMUX: FB-DIMM to Host Double Mux Selector
Configures when both data lines are valid according to Table 3-44. This
primarily affect the 4:5 gearing ratio.
Table 3-44. FB-DIMM to Host Double Config Mux Select
1
FSB:Memory Frequency
Gear Ratio
Value
333:333
267:267
400:400
1:1
00h
2
333:267
267:333
267:333
5:4
00h
4:5 (conservative)
4:5 (aggressive)
08h
04h
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
2. Ignored by MGr registers in the 5:4 mode.
3.9.17
3.9.18
Summary of Memory Gearing Register operating modes
• FBDTOHOSTGRCFG1, GRFBDVLDCFG, and GRFBDTOHOSTDBLCFG are used only in
4:5 mode.
• GRBUBBLECFG is only used in 5:4 mode.
• GRHOSTFULLCFG is used in both 4:5 and 5:4 modes.
• FBDTOHOSTGRCFG0 and HOSTTOFBDGRCFG are used in 4:5, 5:4, AND 1:1 modes.
DRTA - DRAM Timing Register A
This register defines timing parameters for all DDR2 SDRAMs in the memory
subsystem. The parameters for these devices are obtained by serial presence detect.
This register must be set to provide timings that satisfy the specifications of all DRAMs
detected. For example, if DRAMs present have different TRCs, the maximum should be
used to program this register. Consult the JEDEC DDR2 DRAM specifications for the
technology of the devices in use.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
205
Register Description
Device:
Function:
Offset:
16
1
48h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31
RV
0
Reserved
TAL: Additive Latency for Posted CAS
30:28
RW
0h
This parameter is the posted-CAS “t ” DDR2 timing parameter. It must match the
AL
value written to the EMRS register in the DRAM.
27:22
RW
0h
TWRC: Activate command to activate command delay following a DDR
write
This parameter is the minimum delay from an activate command followed by a
write with page-close to another activate command on the same bank. This
parameter prevents bank activation protocol violations in the DRAM’s. This
parameter is defined as follows: tRCD + (tCL – 1) + BL/2 + tWR + tRP where t
RCD
is the DDR ras-to-cas delay, t is the cas-to-first-read-data latency, BL is the burst
CL
length, t
is the write recovery time, and tRP is the precharge time.This
WR
parameter is defined in core cycles. This parameter is set to greater than or equal
to the largest TWRC of any DIMM on the branch.
21:16
RW
0h
TRC: Activate command to activate command delay (same bank)
This parameter is the minimum delay from an activate command to another
activate or refresh command to the same bank. This parameter ensures that the
page of the bank that was opened by the first activate command is closed before
the next activate command is issued. This parameter is defined in core cycles. This
parameter is set to greater than or equal to the largest TRC of any DIMM on the
branch.
15:8
7:4
RW
RW
00h
0h
TRFC: Refresh command to activate command delay
This parameter is the minimum delay from a refresh command to another activate
or refresh command. This parameter ensures that the banks that were opened by
the refresh command are closed before the next activate command is issued. This
parameter is defined in core cycles. This parameter is set to greater than or equal
to the largest TRFC of any DIMM on the branch.
TRRD: Activate command to activate command delay (different banks)
This parameter is the minimum delay from an activate command to another
activate or refresh command to a different bank on the same rank. This parameter
ensures that the electrical disturbance to the SDRAM die caused by the first activate
has attenuated sufficiently before the next activate is applied. This parameter is
defined in core cycles. This parameter is set to greater than or equal to the largest
TRRD of any DIMM on the branch.
3:0
RW
0h
TREF: Refresh command to Refresh command delay
This parameter is the maximum delay from a refresh command to another refresh
command to the same rank. This parameter ensures that a sufficient number of
refreshes per time interval are issued to each rank. This parameter is defined as an
integral multiple of FBD super frames. An FBD super frame is 42 FBD packets (1:1,
5:4) or 40 FBD packets for 4:5 gear ratios in the Intel 5000P Chipset.
This parameter is set to less than or equal to the smallest TREF of any DIMM on the
memory sub-system. The refresh interval is typically 7.80 us for a DDRII DIMM
rank.
Refer to Table 3-45, “Optimum TREF values as a function of core: FBD gear ratios
(in FBD Super frames)”.
The refresh period is calculated as follows:
DIMM refresh period = TREF * Super_Frame_size * 8 * FBD clock period where the
number “8” is a constant denoting the maximum number of ranks supported by the
Intel 5000P Chipset.
As an example, the refresh period is given as 7 * 42 * 8 * 3 ns = 7056 ns for a
DDRII667 system with an FSB to FBD ratio of 1:1
A value of zero disables refresh and clears the refresh counter, allowing a test
program to align refresh events with the test and thus improve failure repeatability.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Table 3-45. Optimum TREF values as a function of core: FBD gear ratios (in FBD Super
frames)
Optimum TREF values as a function of core: FBD gear ratios
DIMM
(in FBD Super frames)
1:1
6
5:4
6
4:5
N/A
8
DDRII533
DDRII667
7
N/A
3.9.19
DRTB - DDR Timing Register B
This register defines timing parameters that work with all DDR ports in the memory
subsystem. This register must be set to provide timings that satisfy the specifications
of all detected DDR ports. For example, if DDR ports have different TR2Ws, the
maximum should be used to program this register.
Device:
Function:
Offset:
16
1
4Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:19
18:16
RV
000h
0h
Reserved
RW
TW2RDR: Write command to read command delay, different rank
This parameter is the minimum delay from a write command to a read command on
different ranks of the same DIMM. This parameter prevents data strobe protocol
violations on the DIMMs DDR data bus. This parameter is defined in core cycles.
This parameter is dependent on cache line size. The formula for this value is BL/2 +
t
- 1. t
is the turnaround time required to read from different ranks on the
FRR
FRR
DIMM.
15:12
RW
0h
TR2W: Read command to write command delay
This parameter is the minimum delay from a read command to a write command on
the same DIMM. This parameter prevents data strobe protocol violations on the
DIMMs DDR data bus. This parameter is defined in core cycles. This parameter is
dependent on cache line size. The formula for this value is BL/2 + t
+ 1. t
is
FRR
FRR
the turnaround time from read to write on the DIMM. This value applies to a DIMM-
hit in the conflict checking unit.
11:8
7:4
RW
RW
0h
0h
TW2R: Write command to read command delay, same rank
This parameter is the minimum delay from a write command to a read command on
the same rank. This parameter prevents data strobe protocol violations on the
DIMMs DDR data bus. This parameter is defined in core cycles. This parameter is
dependent on cache line size. The formula for this value is t - 1 + BL/2 + t
.
CL
WTR
TR2R: Read command to read command delay
This parameter is the minimum delay from a read command to another read
command on a different rank of the same DIMM. This parameter prevents data
strobe protocol violations on the DIMMs DDR data bus. This parameter is defined in
core cycles. The formula for this value is BL/2 + t . t is the turnaround time
FRR FRR
required to read from different ranks on the DIMM.
3:0
RW
0h
TW2W: Write command to write command delay
This parameter is the minimum delay from a write command to another write
command on the same DIMM. This parameter prevents data strobe protocol
violations on the DIMMs DDR data bus. This parameter is defined in core cycles.
This parameter is dependent on cache line size.The formula for this value is BL/2.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
207
Register Description
3.9.20
ERRPER - Error Period
Non-zero UERRCNT and CERRCNT counts are decremented when the error period
counter reaches this threshold. The error period counter is cleared on reset or when it
reaches this threshold. The error period counter increments every 32,768 cycles.
Table 3-46 indicates the timing characteristics of this register:
Table 3-46. Timing Characteristics of ERRPER
Core Frequency
Per Increment
Maximum Period
333 MHz
266 MHz
98.304us
4 days, 21 hours, 16 minutes, 52.465056596 seconds
6 days, 2 hours, 36 minutes, 5.581331712 seconds
122.880us
Device:
Function:
Offset:
16
1
50h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
RW
Default
Description
31:0
0h
THRESH: UERRCNT / CERRCNT decrement threshold.
3.9.21
Memory Map Registers
3.9.21.1
TOLM - Top Of Low Memory
This register defines the low MMIO gap below 4GB. See Section 3.9.21.2.
Whereas the MIR.LIMITs are adjustable, TOLM establishes the maximum address below
4 GB that should be treated as a memory access. TOLM is defined in a 256 MB
boundary.
This register must not be modified while servicing memory requests.
Device:
Function:
Offset:
16
1
6Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:12
RW
1h
TOLM: Top Of Low Memory
This register defines the maximum DRAM memory address that lies below
4GB.
Addresses equal to or greater than the TOLM, and less than 4G, are decoded
as low MMIO, MMCFG (if map within this range by HECBASE), chipset,
interrupt/SMM and firmware as described in the address mapping chapter. All
accesses less than the TOLM are treated as DRAM accesses (except for the
VGA region when enabled and PAM gaps).
Configuration software should set this field either to maximize the amount of
memory in the system (same as the top MIR.LIMIT), or to minimize the
allocated space for the lower PCI memory (low MMIO) plus 32 MB (chipset/
interrupt/SMM and firmware) at a 256 MB boundary.
This field must be set to at least 1h, for a minimum of 256 MB of DRAM. There
is also a minimum of 256MB between TOLM and 4 GB (for low MMIO, MMCFG,
chipset, interrupt/SMM and firmware) since TOLM is on a 256MB boundary.
This field corresponds to A[31:28]. Setting of “1111” corresponds to 3.75 GB
DRAM, and so on down to “0001” corresponds to 0.25GB DRAM. “0000”
setting is illegal and a programming error.
11:0
RV
000h
Reserved
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.21.2
MIR[2:0] - Memory Interleave Range
These registers define each memory branch’s interleave participation in processor-
physical (A) space.
Each register defines a range. If the processor-physical address falls in the range
defined by an MIR, the “way” fields in that MIR defines branch participation in the
interleave. The way-sensitive address bit is A[6]. For a MIR to be effective, WAY0 and
WAY1 fields can not be set to 00b. In mirror mode, the WAY0 and WAY1 fields should
be set to 11b. Matching addresses participate in the corresponding ways.
Compensation for a non-4GB MMIO gap size is performed by adjusting the limit of each
range upward if it is above TOLM as shown in Table 3-47.
MIR updates can only occur in the RESET, READY, FAULT, DISABLED, RECOVERYRESET,
RECOVERYFAULT, and RECOVERYREADY states.
Table 3-47. Interleaving of an address is governed by MIR[i]
Limit with respect to TOLM
Match MIR[i]
if MIR[i].LIMIT[7:0] <= TOLM
then MIR[i].LIMIT[7:0] > A[35:28] >= MIR[i-
1].LIMIT[7:0]
if MIR[i].LIMIT[7:0] > TOLM > MIR[i-1].LIMIT[7:0] then MIR[i].LIMIT[7:0] + (10H - TOLM) > A[35:28] >=
1
MIR[i-1] .LIMIT[7:0]
if MIR[i].LIMIT[7:0] > MIR[i-1].LIMIT[7:0] >=
TOLM
then MIR[i].LIMIT[7:0] + (10H - TOLM) > A[35:28] >=
MIR[i-1].LIMIT[7:0] + (10H - TOLM)
Notes:
1. For MIR[0], MIR[i-1] is defined to be 0.
Device:
Function:
Offset:
16
1
88h, 84h, 80h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:4
RW
000h
LIMIT
This field defines the highest address in the range A[39:28] prior to
modification by the TOLM register. Since MIRs only comprehend 64GB -
(TOLM.TOLM * 256 MB) of address space, LIMIT[11:8] (bits [15:12] of this
register) are ignored, and the largest legal value is (64 GB - (TOLM.TOLM *
28
256 MB)) / 2
Reserved
WAY1
.
3:2
1
RV
00
0
RW
Branch 1 participate in this MIR range if this bit is set AND (the way-sensitive
bit is 1b OR WAY0 of this MIR is 0b).
0
RW
0
WAY0
Branch 0 participate in this MIR range if this bit is set AND (the way-sensitive
bit is 1b OR WAY1 of this MIR is 0b).
3.9.21.3
AMIR[2:0] - Adjusted Memory Interleave Range
For the convenience of software which is trying to determine the physical location to
which a processor bus address is sent, 16 scratch bits are associated with each MIR.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
209
Register Description
Device:
Function:
Offset:
16
1
94h, 90h, 8Ch
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:0
RW
0000h
ADJLIMIT: Adjusted MIR Limit
3.9.22
FB-DIMM Error Registers
3.9.22.1
FERR_FAT_FBD - FB-DIMM First Fatal Errors
The first fatal error for an FB-DIMM branch is flagged in these registers. Only one flag is
ever set. Lower-numbered branches have higher priority than higher-numbered
branches. Lower-numbered channels have higher priority than higher-numbered
channels. Higher-order error bits within a register have higher priority than lower-order
bits. The FBDChan_Indx field is not an error. This register will display invalid index
channel data until an error has occurred.
Device:
Function:
Offset:
16
1
98h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:30
29:28
27:3
2
RV
RV
00
Reserved
00
FBDChan_Indx: Logs channel in which the error occurred
Reserved
RV
0000000h
RWCST
RWCST
RWCST
0
0
0
M3Err: >Tmid Thermal event with intelligent throttling disabled
M2Err: Northbound CRC error on non-redundant retry
M1Err: Alert on non-redundant retry or fast reset timeout
1
0
3.9.22.2
NERR_FAT_FBD - FB-DIMM Next Fatal Errors
If an error is already flagged in FERR_FAT_FBD, subsequent and lower-priority fatal
errors are logged in NERR_FAT_FBD.
Device:
Function:
Offset:
16
1
9Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Version:
Bit
Attr
Default
Description
31:3
RV
0h
0
Reserved
2
1
0
RWCST
RWCST
RWCST
M3Err: >Tmid Thermal event with intelligent throttling disabled
M2Err: Northbound CRC error on non-redundant retry
M1Err: Alert on non-redundant retry or fast reset timeout
0
0
3.9.22.3
FERR_NF_FBD - FB-DIMM First Non-Fatal Errors
The first non-fatal error for a FB-DIMM branch is flagged in these registers. Only one
flag is ever set. Lower-numbered branches have higher priority than higher-numbered
branches. Lower-numbered channels have higher priority than higher-numbered
®
210
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
channels. Higher-order error bits within a register have higher priority than lower-order
bits. The FBDChan_Indx field is not an error. This register will display invalid index
channel data until an error has occurred.
Device:
Function:
Offset:
16
1
A0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Defaul
Bit
Attr
Description
t
31:30
29:28
RV
00
00
Reserved
RWCST
FBDChan_Indx: Logs channel in which the error occurred
The least-significant-bit of this field has no significance for M4Err through
M12Err and M17Err through M20Err. The least-significant-bit of this field only
bears significance for M13Err through M15Err and M21Err and higher.
27:25
24
RV
0h
0
Reserved
RWCST
RWCST
RWCST
M28Err: DIMM-Spare Copy Completed
M27Err: DIMM-Spare Copy Started
Unused:
23
0
22
0
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use.
21
20
19
RWCST
RWCST
RWCST
0
0
0
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use.
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use.
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use.
18
17
16
15
14
13
12
11
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RV
0
0
0
0
0
0
0
0
M22Err: SPD protocol Error
M21Err: FBD Northbound CRC error on FBD Sync Status
M20Err: Correctable Patrol Data ECC
M19Err: Correctable Spare-Copy Data ECC
M18Err: Correctable Mirrored Demand Data ECC
M17Err: Correctable Non-Mirrored Demand Data ECC
Reserved
RWCST
M15Err: Non-Retry or Redundant Retry FBD Northbound CRC error on read
data
10
9
RWCST
RWCST
0
0
M14Err: Non-Retry or Redundant Retry FBD Configuration Alert
M13Err: Non-Retry or Redundant Retry FBD Memory Alert or Redundant Fast
Reset Timeout
8
7
6
5
4
3
2
1
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
0
0
0
0
0
0
0
0
M12Err: Non-Aliased Uncorrectable Patrol Data ECC
M11Err: Non-Aliased Uncorrectable Spare-Copy Data ECC
M10Err: Non-Aliased Uncorrectable Mirrored Demand Data ECC
M9Err: Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC
M8Err: Aliased Uncorrectable Patrol Data ECC
M7Err: Aliased Uncorrectable Spare-Copy Data ECC
M6Err: Aliased Uncorrectable Mirrored Demand Data ECC
M5Err: Aliased Uncorrectable Non-Mirrored Demand Data ECC
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
211
Register Description
Device:
Function:
Offset:
16
1
A0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Defaul
Bit
Attr
RWCST
Description
M4Err: Uncorrectable Data ECC on Replay
t
0
0
3.9.22.4
NERR_NF_FBD - FB-DIMM Next Fatal Errors
If an error is already flagged in FERR_NF_FBD, subsequent and lower-priority non-fatal
errors are logged in NERR_NF_FBD.
Device:
Function:
Offset:
16
1
A4h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Defaul
Bit
Attr
Description
t
31:25
24
RV
00h
0
Reserved
RWCST
RWCST
RWCST
M28Err: DIMM-Spare Copy Completed
M27Err: DIMM-Spare Copy Started
Unused:
23
0
22
0
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use.
21
20
19
RWCST
RWCST
RWCST
0
0
0
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use.
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use.
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use.
18
17
16
15
14
13
12
11
10
9
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RV
0
0
0
0
0
0
0
0
0
0
M22Err: SPD protocol Error
M21Err: FBD Northbound CRC error on FBD Sync Status
M20Err: Correctable Patrol Data ECC
M19Err: Correctable Spare-Copy Data ECC
M18Err: Correctable Mirrored Demand Data ECC
M17Err: Correctable Non-Mirrored Demand Data ECC
Reserved
RWCST
RWCST
RWCST
M15Err: Non-Retry or Redundant Retry FBD Northbound CRC error on read data
M14Err: Non-Retry or Redundant Retry FBD Configuration Alert
M13Err: Non-Retry or Redundant Retry FBD Memory Alert or Redundant Fast
Reset Timeout
8
7
6
5
4
RWCST
RWCST
RWCST
RWCST
RWCST
0
0
0
0
0
M12Err: Non-Aliased Uncorrectable Patrol Data ECC
M11Err: Non-Aliased Uncorrectable Spare-Copy Data ECC
M10Err: Non-Aliased Uncorrectable Mirrored Demand Data ECC
M9Err: Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC
M8Err: Aliased Uncorrectable Patrol Data ECC
®
212
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
16
Function:
Offset:
1
A4h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Defaul
Bit
Attr
Description
t
3
2
1
0
RWCST
RWCST
RWCST
RWCST
0
0
0
0
M7Err: Aliased Uncorrectable Spare-Copy Data ECC
M6Err: Aliased Uncorrectable Mirrored Demand Data ECC
M5Err: Aliased Uncorrectable Non-Mirrored Demand Data ECC
M4Err: Uncorrectable Data ECC on Replay
3.9.22.5
EMASK_FBD - FB-DIMM Error Mask Register
A ‘0’ in any field enables that error.
Device:
Function:
Offset:
16
1
A8h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:28
27
RV
00h
1
Reserved
RWST
RWST
RWST
M28Err: DIMM-Spare Copy Completed
M27Err: DIMM-Spare Copy Started
Unused:
26
1
25
1
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
24
23
22
RWST
RWST
RWST
1
1
1
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
21
20
19
18
17
16
15
14
13
12
RWST
RWST
RWST
RWST
RWST
RWST
RV
1
1
1
1
1
1
0
1
1
1
M22Err: SPD protocol Error
M21Err: FBD Northbound CRC error on FBD Sync Status
M20Err: Correctable Patrol Data ECC
M19Err: Correctable Spare-Copy Data ECC
M18Err: Correctable Mirrored Demand Data ECC
M17Err: Correctable Non-Mirrored Demand Data ECC
Reserved
RWST
RWST
RWST
M15Err: Non-Retry or Redundant Retry FBD Northbound CRC error on read data
M14Err: Non-Retry or Redundant Retry FBD Configuration Alert
M13Err: Non-Retry or Redundant Retry FBD Memory Alert or Redundant Fast
Reset Timeout
11
10
9
RWST
RWST
RWST
RWST
1
1
1
1
M12Err: Non-Aliased Uncorrectable Patrol Data ECC
M11Err: Non-Aliased Uncorrectable Spare-Copy Data ECC
M10Err: Non-Aliased Uncorrectable Mirrored Demand Data ECC
M9Err: Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC
8
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
213
Register Description
Device:
Function:
Offset:
16
1
A8h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7
6
5
4
3
2
1
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
1
1
1
1
1
1
1
1
M8Err: Aliased Uncorrectable Patrol Data ECC
M7Err: Aliased Uncorrectable Spare-Copy Data ECC
M6Err: Aliased Uncorrectable Mirrored Demand Data ECC
M5Err: Aliased Uncorrectable Non-Mirrored Demand Data ECC
M4Err: Uncorrectable Data ECC on Replay
M3Err: >Tmid Thermal event with intelligent throttling disabled
M2Err: Northbound CRC error on retry
M1Err: Alert on non-redundant retry or fast reset timeout
®
214
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.22.6
ERR0_FBD: FB-DIMM Error 0 Mask Register
A ‘0’ in any field enables that error. This register enables the signaling of Err[0] when
an error flag is set.
Device:
Function:
Offset:
16
1
ACh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:28
27
RV
0h
1
Reserved
RWCST
RWCST
RWCST
M28Err: DIMM-Spare Copy Completed
M27Err: DIMM-Spare Copy Started
Unused:
26
1
25
1
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
24
23
22
RWCST
RWCST
RWCST
1
1
1
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
21
20
19
18
17
16
15
14
13
12
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RV
1
1
1
1
1
1
0
1
1
1
M22Err: SPD protocol Error
M21Err: FBD Northbound CRC error on FBD Sync Status
M20Err: Correctable Patrol Data ECC
M19Err: Correctable Spare-Copy Data ECC
M18Err: Correctable Mirrored Demand Data ECC
M17Err: Correctable Non-Mirrored Demand Data ECC
Reserved
RWCST
RWCST
RWCST
M15Err: Non-Retry or Redundant Retry FBD Northbound CRC error on read data
M14Err: Non-Retry or Redundant Retry FBD Configuration Alert
M13Err: Non-Retry or Redundant Retry FBD Memory Alert or Redundant Fast
Reset Timeout
11
10
9
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
1
1
1
1
1
1
1
1
1
1
1
1
M12Err: Non-Aliased Uncorrectable Patrol Data ECC
M11Err: Non-Aliased Uncorrectable Spare-Copy Data ECC
M10Err: Non-Aliased Uncorrectable Mirrored Demand Data ECC
M9Err: Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC
M8Err: Aliased Uncorrectable Patrol Data ECC
8
7
6
M7Err: Aliased Uncorrectable Spare-Copy Data ECC
M6Err: Aliased Uncorrectable Mirrored Demand Data ECC
M5Err: Aliased Uncorrectable Non-Mirrored Demand Data ECC
M4Err: Uncorrectable Data ECC on Replay
5
4
3
2
M3Err: >Tmid Thermal event with intelligent throttling disabled
M2Err: Northbound CRC error on retry
1
0
M1Err: Alert on non-redundant retry or fast reset timeout
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
215
Register Description
3.9.22.7
ERR1_FBD: FB-DIMM Error 1 Mask Register
A ‘0’ in any field enables that error. This register enables the signaling of Err[1] when
an error flag is set.
Device:
Function:
Offset:
16
1
B0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Def
ault
Bit
Attr
Description
31:28
27
RV
0h
1
Reserved
RWCST
RWCST
RWCST
M28Err: DIMM-Spare Copy Completed
M27Err: DIMM-Spare Copy Started
Unused:
26
1
25
1
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
24
23
22
RWCST
RWCST
RWCST
1
1
1
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
21
20
19
18
17
16
15
14
13
12
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RV
1
1
1
1
1
1
0
1
1
1
M22Err: SPD protocol Error
M21Err: FBD Northbound CRC error on FBD Sync Status
M20Err: Correctable Patrol Data ECC
M19Err: Correctable Spare-Copy Data ECC
M18Err: Correctable Mirrored Demand Data ECC
M17Err: Correctable Non-Mirrored Demand Data ECC
Reserved
RWCST
RWCST
RWCST
M15Err: Non-Retry or Redundant Retry FBD Northbound CRC error on read data
M14Err: Non-Retry or Redundant Retry FBD Configuration Alert
M13Err: Non-Retry or Redundant Retry FBD Memory Alert or Redundant Fast
Reset Timeout
11
10
9
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
1
1
1
1
1
1
1
1
1
1
1
1
M12Err: Non-Aliased Uncorrectable Patrol Data ECC
M11Err: Non-Aliased Uncorrectable Spare-Copy Data ECC
M10Err: Non-Aliased Uncorrectable Mirrored Demand Data ECC
M9Err: Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC
M8Err: Aliased Uncorrectable Patrol Data ECC
8
7
6
M7Err: Aliased Uncorrectable Spare-Copy Data ECC
M6Err: Aliased Uncorrectable Mirrored Demand Data ECC
M5Err: Aliased Uncorrectable Non-Mirrored Demand Data ECC
M4Err: Uncorrectable Data ECC on Replay
5
4
3
2
M3Err: >Tmid Thermal event with intelligent throttling disabled
M2Err: Northbound CRC error on retry
1
0
M1Err: Alert on non-redundant retry or fast reset timeout
®
216
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.22.8
ERR2_FBD: FB-DIMM Error 2 Mask Register
A ‘0’ in any field enables that error. This register enables the signaling of Err[2] when
an error flag is set.
Device:
Function:
Offset:
16
1
B4h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Defaul
Bit
Attr
Description
t
31:28
27
RV
0h
1
Reserved
RWCST
RWCST
RWCST
M28Err: DIMM-Spare Copy Completed
M27Err: DIMM-Spare Copy Started
Unused:
26
1
25
1
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future used
24
23
22
RWCST
RWCST
RWCST
1
1
1
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
21
20
19
18
17
16
15
14
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RV
1
1
1
1
1
1
0
1
M22Err: SPD protocol Error
M21Err: FBD Northbound CRC error on FBD Sync Status
M20Err: Correctable Patrol Data ECC
M19Err: Correctable Spare-Copy Data ECC
M18Err: Correctable Mirrored Demand Data ECC
M17Err: Correctable Non-Mirrored Demand Data ECC
Reserved
RWCST
M15Err: Non-Retry or Redundant Retry FBD Northbound CRC error on read
data
13
12
RWCST
RWCST
1
1
M14Err: Non-Retry or Redundant Retry FBD Configuration Alert
M13Err: Non-Retry or Redundant Retry FBD Memory Alert or Redundant Fast
Reset Timeout
11
10
9
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
1
1
1
1
1
1
1
1
1
1
1
1
M12Err: Non-Aliased Uncorrectable Patrol Data ECC
M11Err: Non-Aliased Uncorrectable Spare-Copy Data ECC
M10Err: Non-Aliased Uncorrectable Mirrored Demand Data ECC
M9Err: Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC
M8Err: Aliased Uncorrectable Patrol Data ECC
8
7
6
M7Err: Aliased Uncorrectable Spare-Copy Data ECC
M6Err: Aliased Uncorrectable Mirrored Demand Data ECC
M5Err: Aliased Uncorrectable Non-Mirrored Demand Data ECC
M4Err: Uncorrectable Data ECC on Replay
5
4
3
2
M3Err: >Tmid Thermal event with intelligent throttling disabled
M2Err: Northbound CRC error on retry
1
0
M1Err: Alert on non-redundant retry or fast reset timeout
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
217
Register Description
3.9.22.9
MCERR_FBD - FB-DIMM MCERR Mask Register
A ‘0’ in any field enables that error. This register enables the signaling of MCERR when
an error flag is set.
Device:
Function:
Offset:
16
1
B8h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Def
ault
Bit
Attr
Description
31:28
27
RV
0h
1
Reserved
RWCST
RWCST
RWCST
M28Err: DIMM-Spare Copy Completed
M27Err: DIMM-Spare Copy Started
Unused:
26
1
25
1
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future used
24
23
22
RWCST
RWCST
RWCST
1
1
1
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future use
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future used
Unused:
This register field is of type “RWCST” and have no associated functionality
currently. They are allocated for future used
21
20
19
18
17
16
15
14
13
12
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RV
1
1
1
1
1
1
0
1
1
1
M22Err: SPD protocol Error
M21Err: FBD Northbound CRC error on FBD Sync Status
M20Err: Correctable Patrol Data ECC
M19Err: Correctable Spare-Copy Data ECC
M18Err: Correctable Mirrored Demand Data ECC
M17Err: Correctable Non-Mirrored Demand Data ECC
Reserved
RWCST
RWCST
RWCST
M15Err: Non-Retry or Redundant Retry FBD Northbound CRC error on read data
M14Err: Non-Retry or Redundant Retry FBD Configuration Alert
M13Err: Non-Retry or Redundant Retry FBD Memory Alert or Redundant Fast
Reset Timeout
11
10
9
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
1
1
1
1
1
1
1
1
1
1
1
1
M12Err: Non-Aliased Uncorrectable Patrol Data ECC
M11Err: Non-Aliased Uncorrectable Spare-Copy Data ECC
M10Err: Non-Aliased Uncorrectable Mirrored Demand Data ECC
M9Err: Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC
M8Err: Aliased Uncorrectable Patrol Data ECC
8
7
6
M7Err: Aliased Uncorrectable Spare-Copy Data ECC
M6Err: Aliased Uncorrectable Mirrored Demand Data ECC
M5Err: Aliased Uncorrectable Non-Mirrored Demand Data ECC
M4Err: Uncorrectable Data ECC on Replay
5
4
3
2
M3Err: >Tmid Thermal event with intelligent throttling disabled
M2Err: Northbound CRC error on retry
1
0
M1Err: Alert on non-redundant retry or fast reset timeout
®
218
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.22.10 NRECMEMA - Non-Recoverable Memory Error Log Register A
This register latches information on the first detected fatal memory error.
Device:
Function:
Offset:
16
1
BEh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15
14:12
11
RV
0
0h
0
Reserved
ROST
ROST
BANK: Bank of the failed request
RDWR
‘0’ = Read
‘1’ = Write
10:8
7:0
ROST
ROST
0h
RANK: Rank of the failed request
00h
REC_FBD_DM_BUF_ID: DM Buffer ID of the failed request
3.9.22.11 NRECMEMB - Non-Recoverable Memory Error Log Register B
This register latches information on the first detected fatal memory error.
Device:
Function:
Offset:
16
1
C0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:28
27:16
15
RV
ROST
RV
0h
000h
0
Reserved
CAS: CAS address of the failed request
Reserved
14:0
ROST
0h
RAS: RAS address of the failed request
3.9.22.12 NRECFGLOG - Non-Recoverable DIMM Configuration Access Error Log
Register
This register latches information on the first detected non-fatal DIMM configuration
register access.
Device:
Function:
Offset:
16
1
C4h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:28
27:24
23:16
15:12
11
RV
0h
0h
00h
0h
0
Reserved
ROST
ROST
RV
BE: Byte Enables of the failed request
REG: Register Address of the failed request
Reserved
ROST
RDWR
‘0’ = Read
‘1’ = Write
10:8
7:0
ROST
ROST
0h
FUNCTION: Function Number of the failed request
00h
CFG_FBD_DM_BUF_ID: DM Buffer ID of the failed request
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
219
Register Description
3.9.22.13 NRECFBDA: Non-Recoverable FB-DIMM Error Log Register A
The NRECFBD registers defined below (A through E) have the following mapping:
Table 3-48. NRECFBD Mapping Information
Bits
Description
155:144
143:128
127:0
CRC
ECC
DATA
This register latches information on the first detected fatal northbound CRC error.
Device:
Function:
Offset:
16
1
C8h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:0
ROST
0h
BITS: Bits [31:0] of the packet
3.9.22.14 NRECFBDB - Non-Recoverable FB-DIMM Error Log Register B
This register latches information on the first detected fatal northbound CRC error.
Device:
Function:
Offset:
16
1
CCh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
BITS: Bits [63:32] of the packet
31:0
ROST
0h
®
220
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.22.15 NRECFBDC - Non-Recoverable FB-DIMM Error Log Register C
This register latches information on the first detected fatal northbound CRC error.
Device:
Function:
Offset:
16
1
D0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
BITS: Bits [95:64] of the packet
31:0
ROST
0h
3.9.22.16 NRECFBDD - Non-Recoverable FB-DIMM Error Log Register D
This register latches information on the first detected fatal northbound CRC error.
Device:
Function:
Offset:
16
1
D4h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
BITS: Bits [127:96] of the packet
31:0
ROST
0h
3.9.22.17 NRECFBDE - Non-Recoverable FB-DIMM Error Log Register E
This register latches information on the first detected fatal northbound CRC error.
Device:
Function:
Offset:
16
1
D8h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:28
27:0
RV
0h
0h
Reserved
BITS: Bits [155:128] of the packet
ROST
3.9.22.18 REDMEMB: Recoverable Memory Data Error Log Register B
This register latches information on the first detected correctable ECC error.
Device:
Function:
Offset:
16
1
7Ch
Bit
Attr
Default
Description
31:18
17:0
RV
0
Reserved
ROST
0h
ECC _Locator: identifies the adjacent symbol pair in error for correctable
errors according to Table 3-49, Figure 5-2 and Figure 5-4.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
221
Register Description
:
Table 3-49. ECC Locator Mapping Information
Symbols
Locator Bit
DS[1:0]
DS[3:2]
0
1
DS[5:4]
2
DS[7:6]
3
DS[9:8]
4
DS[11:10]
DS[13:12]
DS[15:14]
CS[1:0]
5
6
7
8
DS[17:16]
DS[19:18]
DS[21:20]
DS[23:22]
DS[25:24]
DS[27:26]
DS[29:28]
DS[31:30]
CS[3:2]
9
10
11
12
13
14
15
16
17
®
222
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.22.19 RECMEMA - Recoverable Memory Error Log Register A
This register latches information on the first detected non-fatal memory error.
Device:
Function:
Offset:
16
1
E2h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Version:
Bit
Attr
Default
Description
15
14:12
11
RV
0
0h
0
Reserved
ROST
ROST
BANK: Bank of the failed request
RDWR
‘0’ = Read
‘1’ = Write
10:8
7:0
ROST
ROST
0h
RANK: Rank of the failed request
00h
REC_FBD_DM_BUF_ID: DM Buffer ID of the failed request
3.9.22.20 RECMEMB - Recoverable Memory Error Log Register B
This register latches information on the first detected non-fatal memory error.
Device:
Function:
Offset:
16
1
E4h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:29
28:16
15
RV
ROST
RV
0h
000h
0
Reserved
CAS: CAS address of the failed request
Reserved
14:0
ROST
0h
RAS: RAS address of the failed request
3.9.22.21 RECFGLOG - Recoverable DIMM Configuration Access Error Log
Register
This register latches information on the first detected fatal DIMM configuration register
access.
Device:
Function:
Offset:
16
1
E8h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:28
27:24
23:16
15:12
11
RV
0h
0h
00h
0h
0
Reserved
ROST
ROST
RV
BE: Byte Enables of the failed request
REG: Register Address of the failed request
Reserved
ROST
RDWR
‘0’ = Read
‘1’ = Write
10:8
7:0
ROST
ROST
0h
FUNCTION: Function Number of the failed request
00h
CFG_FBD_CE_BUF_ID: DM Buffer ID of the failed request
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
223
Register Description
3.9.22.22 RECFBDA - Recoverable FB-DIMM Error Log Register A
This register latches information on the first northbound CRC error.
Device:
Function:
Offset:
16
1
ECh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
31:0
ROST
0h
BITS: Bits [31:0] of the packet
3.9.22.23 RECFBDB - Recoverable FB-DIMM Error Log Register B
This register latches information on the first detected non-fatal northbound CRC error.
Device:
Function:
Offset:
16
1
F0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Version:
Bit
Attr
Default
Description
BITS: Bits [63:32] of the packet
31:0
ROST
0h
3.9.22.24 RECFBDC - Recoverable FB-DIMM Error Log Register C
This register latches information on the first detected non-fatal northbound CRC error.
Device:
Function:
Offset:
16
1
F4h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Version:
Bit
Attr
Default
Description
BITS: Bits [95:64] of the packet
31:0
ROST
0h
3.9.22.25 RECFBDD - Recoverable FB-DIMM Error Log Register D
This register latches information on the first detected non-fatal northbound CRC error.
Device:
Function:
Offset:
16
1
F8h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Version:
Bit
Attr
Default
Description
BITS: Bits [127:96] of the packet
31:0
ROST
0h
®
224
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.22.26 RECFBDE - Recoverable FB-DIMM Error Log Register E
This register latches information on the first detected non-fatal northbound CRC error.
Device: 16
Function: 1
Offset: FCh
Bit
Attr
Default
Description
31:28
27:0
RV
0h
0h
Reserved
BITS: Bits [155:128] of the packet
ROST
3.9.23
FB-DIMM Branch Registers
There are two sets of the following registers, one set for each FB-DIMM branch. They
each appear in function 0 of different devices as shown in Table 3-3.
3.9.23.1
FBDLVL[1:0][1:0] - FB-DIMM Packet Levelization
This register controls the FB-DIMM channel delays.
Device:
Function:
Offset:
21
0
45h, 44h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
45h, 44h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:6
5:0
RV
RO
00
0h
Reserved
TRRL: Read Round-Trip Latency
Measured from issue of the FB-DIMM channel’s southbound TS2 packet header to
the arrival of its northbound response header.
3.9.23.2
FBDHPC[1:0]: FBD State Control
This register controls the FBD channel for Initialization and Mirroring Recovery. It
consists of a next State field.
The index in FBDHPC[index] associates the FBDHPC with branch[index]. FBDHPC[0] is
associated with FBD branch 0, FBDHPC[1] is associated with FBD branch 1.
When software writes to FBDHPC[x].NEXTSTATE, the transition will take effect on one
or both channels within the branch depending on whether the branch is operating is
single- or dual-channel mode.
When BNB hardware transitions FBDST.STATE with the following encodings: 1)
disabled, 2) redundant, 3) recovery failed, 4) redundancy loss, and 5) reset, it will
transition states of one or both channels within the same branch depending on whether
the branch is operating in single- or dual-channel mode.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
225
Register Description
1
Device :22, 21
Function:0
Offset:4Fh
Bit
Attr
Default
Description
7:0
RW
00h
NEXTSTATE: FBD Branch State Control field
This field is written by software to change the branch state. It returns the last
value written when read. Some states can only be entered under hardware
control and should not be written by software.
00h: Reset
10h: Init
2
2
20h: Ready
30h: Active
2
40h: Redundant
50h: Disabled
2
60h: Redundancy Loss - may not be written
70h: Recovery Reset - (should only be selected when MC.MIRROR is set)
80h: Recovery Init - (should only be selected when MC.MIRROR is set)
2
90h: Recovery Ready - (should only be selected when MC.MIRROR is set)
2
A0h: Resilver - (should only be selected when MC.MIRROR is set)
(should not be written while FBDST.STATE=Resilver)
B0h: Recovery Fault
C0h: Recovery Failed
D0h: Fault
Notes:
1. The nomenclature is Device 22 (branch 1), 21 (branch 0)
2. Both sync and refresh packets are sent during this mode.
®
226
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.23.3
FBDST[1:0] - FB-DIMM Status
These registers are inspected by software to determine the current FB-DIMM branch
state. This register contains Mirroring recovery state, and Initialization state.
The indexing scheme is the same as in FBDHPC registers. The current FB-DIMM branch
state field indicates state for one or both channels within the same branch depending
on whether the branch is operating in single- or dual-channel mode.
Device:
Function:
Offset:
21
0
4Bh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
4Bh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0
ROST
00h
STATE: FBD Branch State
This field describes the current state of the FB-DIMM branch. It can be read
by software to determine which FB-DIMM branch is being sequenced through
recovery, and how far the FB-DIMM branch has progressed.
00h: Reset
10h: Init
20h: Ready
30h: Active
40h: Redundant
50h: Disabled
60h: Redundancy Loss - may not be written
70h: Recovery Reset - (should only be selected when MC.MIRROR is set)
80h: Recovery Init - (should only be selected when MC.MIRROR is set)
90h: Recovery Ready - (should only be selected when MC.MIRROR is set)
A0h: Reserved
B0h: Recovery Fault
C0h: Recovery Failed
D0h: Fault
This field is only sticky through hard reset when SYRE.S3 is set. This field is
not sticky through hard reset when SYRE.S3 is cleared.
3.9.23.4
FBDRST[1:0] - FB-DIMM Reset
The FB-DIMM I/O blocks are reset separately from the rest of the Intel 5000P Chipset
MCH. These blocks, composed of FAST-clocked (GHz unit-interval clocked) logic, are
supplied by a PLL whose FBDCLK is not available when PWRGOOD is asserted. After
FBDCLK is enabled and the FB-DIMM PLL has acquired lock, CORERESET# is deasserted
for a minimum of 21ns, then asserted for a minimum of 2us. After the 2us assertion,
CORERESET# is deasserted followed by a minimum delay of 3ns at which time
SOFTCORERESET# is deasserted. If the platform removes FBDCLK on a hot-remove of
the branch, CORERESET# and SOFTCORERESET# must be asserted prior to loss of
FBDCLK.
A “disabled” (not enabled) FBDCLK is floated at the source, and pulled to ground
through the termination near the receiver in the Intel 5000P Chipset MCH.
All timing specifications in Figure 3-6 are minimums. After the sequence in Figure 3-6
has been executed, the FB-DIMM branch is ready for initialization.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
227
Register Description
Figure 3-6. FB-DIMM Reset Timing
ENABLED
FBDCLK
T1
UNLOCKED
LOCKED
FBD PLL
CORERESET#
0
21ns
2us
3ns
SOFTCORERESET#
Device:
Function:
Offset:
21
0
53h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
53h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:
3
RV
00h
Reserved
2
RWST
0
BRSELCMPRESET: Branch Select for Compensation Reset
0: COMPreset is tied to CORERESET# from branch 0
1: COMPreset is tied to CORERESET# from branch 1
For Branch 1 to be selected for reset, this field has to be a ‘1’ for both branch
instances.
1
0
RWST
RWST
0
0
SOFTCORERESET#: Soft Core Reset
See Timing diagram Figure 3-6.
0: Soft Core Reset Asserted
1: Soft Core Reset De-Asserted
CORERESET#: Core Reset
See Timing diagram Figure 3-6.
0: Core Reset Asserted
1: Core Reset De-Asserted
3.9.23.5
SPCPC[1:0] - Spare Copy Control
These controls set up sparing for each branch. Branch zero (device 21) takes
precedence over branch one (device 22): if both spare-control-enabled branches’ spare
error thresholds trigger in the same cycle, sparing will only commence on branch zero.
Sparing will not commence on a competing branch until its in-progress competitor’s
spare control enable is cleared and it’s UERRCNT/CERRCNT criteria is still met.
®
228
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
21
Function:
Offset:
0
40h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
40h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:4
RW
0h
SETH: Spare Error Threshold
A spare fail-over operation will commence when the SPAREN bit is set and a
UERRCNT.RANK[i] and/or CERRCNT.RANK[i] count for one and only one rank hits
this threshold.
3:1
0
RWL
0h
0
SPRANK: Spare Rank
Target of the spare copy operation. This rank should not initially appear in a
DMIR.RANK field. After the spare copy, Intel 5000P Chipset MCH will update the
failed DMIR.RANK fields with this value. Enabled by SPAREN. Changes to this
register will not be acknowledged by the hardware while SPCPS.DSCIP is set.
RW
SPAREN: Spare Control Enable
‘1’ enables sparing, ‘0’ disables sparing. The SPRANK field defines other
characteristics of the sparing operation. The Intel 5000P Chipset MCH does not
support sparing in mirrored mode: this bit should not be set if MC.MIRROR is set.
If this bit is cleared before SPCPS.SFO is set, then if this bit is subsequently set
while the spare trigger is still valid, then the spare copy operation will not resume
from where it left off, but will instead restart from the beginning.
3.9.23.6
SPCPS[1:0] - Spare Copy Status
Device:
Function:
Offset:
21
0
41h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
41h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:6
5
RV
RO
00
0
Reserved
LBTHR: Leaky Bucket Threshold Reached
‘0’ = Leaky-bucket threshold not reached
‘1’ = Leaky-bucket count matches SPCPC.SETH. Generates error M27. Cleared by
reducing the offending count(s) in the UERRCNT/CERRCNT registers.
4
RO
0
DSCIP: DIMM Sparing Copy In Progress
‘0’ = DIMM sparing copy not in progress.
‘1’ = DIMM sparing copy in progress. Set when SPCPC.SPAREN is set, and only one
rank in UERRCNT/CERRCNT is at threshold. This bit remains set until SFO is set.
This bit is cleared when SFO is set. Error M27 is set when this bit transitions from
‘0’ to ‘1’.
3:1
0
RO
RO
000
0
FR: Failed Rank
Rank that was spared. Updated with the UERRCNT/CERRCNT rank that has reached
threshold when DSCIP is set.
SFO: Spare Fail-Over
‘0’ = Spare has not been substituted for failing DIMM rank.
‘1’ = Spare has been substituted for failing DIMM rank. Generates error M28.
Cleared when SPCPC.SPAREN is cleared.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
229
Register Description
3.9.23.7
MTR[1:0][3:0] - Memory Technology Registers
These registers define the organization of the DIMM’s. There is one MTR for each pair of
slots comprising either one or two ranks. The parameters for these devices can be
obtained by serial presence detect.
MTR[3:0] defines slot-pairs [3:0] on branch[0]. MTR[7:4] defines slot-pairs [3:0] on
branch[1].
MTR[3:0] in Table 3-24 is MTR[3:0] for Device 21 which is MTR[3:0] for this
Section 3.9.23.7.
MTR[3:0] in Table 3-24 is MTR[3:0] for Device 22 which is MTR[7:4] for this
Section 3.9.23.7.
This register must not be modified while servicing memory requests.
Device:
Function:
Offset:
21
0
8Ch, 88h, 84h, 80h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
8Ch, 88h, 84h, 80h
Intel 5000P Chipset
Version:
Bit
Attr
Default
Description
15:9
8
RV
00h
0
Reserved
RW
PRESENT: DIMMs are present
This bit is set if both DIMMs are present and their technologies are compatible.
7
RW
0
ETHROTTLE: Technology - Electrical Throttle
Defines the electrical throttling level for these DIMMs:
‘0’ = Electrical Throttling is disabled
‘1’ = Electrical Throttling is enabled using the throttling level defined by the
MC.ETHROT configuration field.
6
5
RW
RW
RW
RW
0
0
WIDTH: Technology - Width
Defines the data width of the SDRAMs used on these DIMMs
‘0’ = x4 (4 bits wide)
‘1’ = x8 (8 bits wide)
NUMBANK: Technology - Number of Banks
Defines the number of (real, not shadow) banks on these DIMMs
‘0’ = four-banked
‘1’ = eight-banked
4
0
NUMRANK: Technology - Number of Ranks
Defines the number of ranks on these DIMMs.
‘0’ = single ranked
‘1’ = double ranked
3:2
00
NUMROW: Technology - Number of Rows
Defines the number of rows within these DIMMs.
“00”= 8,192, 13 rows
“01”= 16,384, 14 rows
“10”= 32,768, 15 rows
“11”= Reserved
1:0
RW
00
NUMCOL: Technology - Number of Columns
Defines the number of columns within these DIMMs
“00”= 1,024, 10 columns
“01”= 2,048, 11 columns
“10”= 4,096, 12 columns
“11”= Reserved
3.9.23.8
DMIR[1:0][4:0] - DIMM Interleave Range
These registers define rank participation in various DIMM interleaves.
®
230
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Each register defines a range. If the Memory (M) address falls in the range defined by
an adjacent pair of DMIR.LIMIT’s, the rank fields in the upper DMIR define the number
and interleave position of ranks’ way participation. Matching addresses participate in
the corresponding ways. The combination of two equal ranks with three unequal ranks
is illegal.
When a DMIR is programmed for a 2-way interleave, RANK0/RANK2 should be with the
same rank number and RANK1/RANK3 should be another rank number.
This register must not be modified while servicing memory requests.
Device:
Function:
Offset:
21
0
A0h, 9Ch, 98h, 94h, 90h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
A0h, 9Ch, 98h, 94h, 90h
Intel 5000P Chipset
Version:
Bit
Attr
Default
Description
31:24
23:16
RV
000h
00h
Reserved
RW
LIMIT
This field defines the highest address in the range. Memory requests
participate in this DMIR range if LIMIT[i] > M[34:28] >= LIMIT[i-1]. For i = 0,
LIMIT[i-1]=0 (M[35] is considered as zero for the purpose of this comparison).
15:12
11:9
RV
0h
Reserved
RW
000
RANK3
Defines which rank participates in WAY3.
8:6
5:3
2:0
RW
RW
RW
000
000
000
RANK2
Defines which rank participates in WAY2.
RANK1
Defines which rank participates in WAY1.
RANK0
Defines which rank participates in WAY0.
3.9.23.9
FBDICMD[1:0][1:0] - FB-DIMM Initialization Command
These registers define channel behavior during the “Init”, “Recovery Init”, “Reset”, and
“Recovery Reset” hot-plug states. The “AMBID” field for the even-numbered channel
also defines branch behavior during fast reset.
Device:
Function:
Offset:
21
0
47h, 46h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
47h, 46h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7
RW
0
EN: Enable
‘0’ = Drive electrical idle on the channel.
‘1’ = Drive INITPAT on the channel.
This field is not used during fast reset.
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Register Description
Device:
Function:
Offset:
21
0
47h, 46h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
47h, 46h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
6:4
RW
00
INITPAT: Initialization pattern
“000”=TS0: Training Sequence 0 to last AMB (not valid in “Reset”)
“001”=TS1: Training Sequence 1 to last AMB (not valid in “Reset”)
“010”=TS2: Training Sequence 2 to last AMB (not valid in “Reset”)
“011”=TS3: Training Sequence 3 to last AMB (not valid in “Reset”)
“100”=reserved
“101”=TS2: Training Sequence 2 not to last AMB with NB Merge disabled
(not valid in “Reset”)
“110”=TS2: Training Sequence 2 not to last AMB with NB Merge enabled
(not valid in “Reset”)
“111”=All Ones (valid only in “Reset”)
This pattern is superseded by the “EN” bit.
This field is not used during fast reset.
The note ‘(not valid in “Reset”)’ indicates that is not valid when
FBDST.STATE=”Reset” or “Recovery Reset” and EN=’1’. The note ‘(valid only in
“Reset”)’ indicates that this is valid only when FBDST.STATE=”Reset” or
“Recovery Reset”.
3:0
RW
0h
AMBID: Advanced Memory Buffer IDentifier
Driven during the training sequences.
This field is also used during fast reset to identify the last (southernmost)
DIMM.
3.9.23.10 FBDISTS[1:0][1:0] - FB-DIMM Initialization Status
The contents of this register are valid only during “Initialization” states. The thirteen
bits [12:0] correspond to the northbound bit-lanes.
Device:
Function:
Offset:
21
0
5Ah, 58h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
5Ah, 58h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:13
12:0
RV
RO
000
Reserved
0000h
PATDET: Pattern Detection
“1”= Pattern recognized.
“0”= Pattern not recognized.
Bit-Lane Status is evaluated at the end of each instance of the pattern
specified by the FBDICMD.EN and FBDICMD.INITPAT fields. Bit-Lane status is
evaluated on each change to the FBDICMD.EN and FBDICMD.INITPAT.Only bits
[2:0] are valid during electrical idle, and only after the FBDRST reset sequence
has been executed.
A recognizable training sequence must contain the FBDICMD.AMBID.
TS1 detection is qualified by test patterns specified in section 4.3 of rev. 0.75
of FBD DFx specification, which defines the “SB/NB_Mapping” (1 bit), the “Test
Parameters” (24 bits), and the “Electrical Stress Pattern”.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.23.11 AMBPRESENT[1:0][1:0] - FB-DIMM AMB Slot Present Register
These registers control configuration transaction routing to AMB slots on a per FB-
DIMM channel basis. This includes both accesses through memory mapped region
(based on AMBASE register, see Section 3.8.3.1) and AMBSELECT (for SMBus/JTAG
access only, access via device 9, function 0. See Section 3.8.3.3). Software needs to
program this register after SPD discovery process. Intel 5000P Chipset MCH will check
this register before it sends actual FB-DIMM AMB configuration transaction.
Device:
Function:
Offset:
21
0
66h, 64h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
66h, 64h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:0
RWO
0h
AMBSP: Slot [bit_position] present in the FBD channel
1: Indicates AMB slot addressed by DS[3:0] in decimal = [bit_position] is
present; configuration transaction will be routed to FB-DIMM channel. Bit 15
controls DS[3:0] = 1111b, bit 14 controls DS[3:0] = 1110b,..., bit 0 controls
DS[3:0] = 0000b.
0: AMB slot addressed by DS[3:0] in decimal = [bit_position] is not
populated; no configuration transaction will be sent to FB-DIMM channel.
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233
Register Description
3.9.24
FB-DIMM RAS Registers
There are two sets of the following registers, one set for each FB-DIMM branch. They
each appear in function 0 of different devices as shown in Table 3-3.
3.9.24.1
UERRCNT[1:0] - Uncorrectable Error Count
This register implements the “leaky-bucket” counters for uncorrectable errors for each
rank. Each field “limits” at a value of “15” (“1111”). Non-zero counts are decremented
when the ERRPER threshold is reached by the error period counter. Counts are frozen at
the threshold defined by SPCPC.SETH and set the SPCPS.LBTHR bit. Writing a value of
“1111” clears and thaws the count. Changing SPCPC.SETH has no effect upon a frozen
count.
Note:
Aliased uncorrectable errors are NOT counted as uncorrectable errors in the
implementation of this register. They are treated as correctable errors and logged in
the CERRCNT register.
Device:
Function:
Offset:
21
0
A4h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
A4h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:28 RWCST
27:24 RWCST
23:20 RWCST
19:16 RWCST
15:12 RWCST
0h
0h
0h
0h
0h
0h
0h
0h
RANK7: Error Count for Rank 7
RANK6: Error Count for Rank 6
RANK5: Error Count for Rank 5
RANK4: Error Count for Rank 4
RANK3: Error Count for Rank 3
RANK2: Error Count for Rank 2
RANK1: Error Count for Rank 1
RANK0: Error Count for Rank 0
11:8
7:4
RWCST
RWCST
RWCST
3:0
3.9.24.2
CERRCNT[1:0] - Correctable Error Count
This register implements the “leaky-bucket” counters for correctable errors for each
rank. Each field “limits” at a value of “15” (“1111”). Non-zero counts are decremented
when the ERRPER threshold is reached by the error period counter. Counts are frozen at
the threshold defined by SPCPC.SETH and set the SPCPS.LBTHR bit. Writing a value of
“1111” clears and thaws the count. Changing SPCPC.SETH has no effect upon a frozen
count.
Note:
Aliased uncorrectable errors are counted as correctable errors in the implementation of
this register.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
21
Function:
Offset:
0
A8h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
A8h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:28 RWCST
27:24 RWCST
23:20 RWCST
19:16 RWCST
15:12 RWCST
0h
0h
0h
0h
0h
0h
0h
0h
RANK7: Error Count for Rank 7
RANK6: Error Count for Rank 6
RANK5: Error Count for Rank 5
RANK4: Error Count for Rank 4
RANK3: Error Count for Rank 3
RANK2: Error Count for Rank 2
RANK1: Error Count for Rank 1
RANK0: Error Count for Rank 0
11:8
7:4
RWCST
RWCST
RWCST
3:0
3.9.24.3
BADRAMA[1:0] - Bad DRAM Marker A
This register implements “failed-device” markers for the enhanced demand scrub
algorithm. Hardware “marks” bad devices. The “mark” is a number between 1 and 18
inclusive. A value of “0 0000h” indicates an “un-marked” rank: all RAM’s are presumed
“good”. Only ranks containing x8 DRAM are “marked”.
Device:
Function:
Offset:
21
0
ACh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
ACh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:30
RV
00
Reserved
29:25 RWCST
24:20 RWCST
19:15 RWCST
14:10 RWCST
00h
00h
00h
00h
00h
00h
RANK5: Bad device in Rank 5
RANK4: Bad device in Rank 4
RANK3: Bad device in Rank 3
RANK2: Bad device in Rank 2
RANK1: Bad device in Rank 1
RANK0: Bad device in Rank 0
9:5
4:0
RWCST
RWCST
3.9.24.4
BADRAMB[1:0] - Bad DRAM Marker B
This register implements “failed-device” markers for the enhanced demand scrub
algorithm. Hardware “marks” bad devices. The “mark” is a number between 1 and 18
inclusive. A value of “0_0000” indicates an “un-marked” rank: all DRAM’s are presumed
“good”. Only ranks containing x8 DRAM are “marked”.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
235
Register Description
Device:
Function:
Offset:
21
0
B0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
B0h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:10
RV
00h
00h
00h
Reserved
9:5
4:0
RWCST
RWCST
RANK7: Bad device in Rank 7
RANK6: Bad device in Rank 6
3.9.24.5
BADCNT[1:0] - Bad DRAM Counter
This register implements “failing-device” counters for the aliased uncorrectable error
identification algorithm. “Count” double-adjacent symbol errors within x8 devices.
“Drip” each counter after “MC.BADRAMTH” patrol scrub cycles through all of memory.
Values of “MC.BADRAMTH” and “0” cannot be “dripped”. A value of “MC.BADRAMTH”
cannot be incremented. “Mark” the BADRAM(A/B) register when a count reaches
“MC.BADRAMTH”.
Device:
Function:
Offset:
21
0
B4h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
B4h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:28 RWCST
27:24 RWCST
23:20 RWCST
19:16 RWCST
15:12 RWCST
0000
0000
0000
0000
0000
0000
0000
0000
RANK7: Adjacent x8 symbol error count in Rank 7
RANK6: Adjacent x8 symbol error count in Rank 6
RANK5: Adjacent x8 symbol error count in Rank 5
RANK4: Adjacent x8 symbol error count in Rank 4
RANK3: Adjacent x8 symbol error count in Rank 3
RANK2: Adjacent x8 symbol error count in Rank 2
RANK1: Adjacent x8 symbol error count in Rank 1
RANK0: Adjacent x8 symbol error count in Rank 0
11:8
7:4
RWCST
RWCST
RWCST
3:0
3.9.24.6
FBDSBTXCFG[1:0][1:0]: FB-DIMM Southbound Transmit Configuration
Register
This register controls the FB-DIMM Southbound I/O Transmit configuration during
normal operation. This value is programmed by BIOS on per channel basis.
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Register Description
Device:
21
Function:
Offset:
0
C1h, C0h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
C1h, C0h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
7:4
RV
0h
01
Reserved.
3:2
1:0
RWST
RWST
SBTXDRVCUR: South Bound Tx drive Current
00: 120% current
01: 100% current
10: 80% current
11: 60% current
00
SBTXDEEMP: South Bound Tx De-emphasis
With De-emphasis, the Tx differential p-p swing (eye height) is maintained at
nominal during data transitions, but drops down to the de-emphasized value
when there is no transition between the previous bit and current bit
00: No De-emphasis
01: -3.5dB
10: -6dB
11: -9.5 dB
3.9.25
FB-DIMM Intel IBIST Registers
3.9.25.1
FBD[3:2]IBPORTCTL: FB-DIMM IBIST Port Control Register
This register contains bits to control the operation of the Intel IBIST DFT feature.
Device:
22
Function: 0
Offset:
Bit
280h, 180h
Attr
Default
Description
31:26
RV
0h
Reserved
RXINVSWPMD: Rx Inversion Sweep Mode
0: Match Sweep according to the SB-to-NB_Mapping field in the TS1 training
sequence.
The default setting forces the RX inversion pointers to follow the unique
northbound inversion across the port width. It is based on a Modulo 5 of Intel
5000P Chipset MCHMAP bit setting. If e lanes Example;
If Intel 5000P Chipset MCHMAP = 0 then Lanes [4:0] are used as the reference
for checking Lanes[13:10], [9:5], and [4:0].
If Intel 5000P Chipset MCHMAP = 1 then Lanes [9:5] are used as the reference
for checking Lanes[13:10], [9:5], and [4:0].
25
RWST
0
For Intel 5000P Chipset MCH lane [13] does not exist but it does participate in
rotate-left-shift operations.
1: Enable full inversion sweep across the entire port.
When enabled the RX inversion pointers become a single entity.
Lanes [13:10] rotate left-shift completely across the width of the port. Even
though Lane[13] is a DFT lane it will be “shifted through” to make the logic
design easier.
0->1->2->3->4->5->6->7->8->9->10->11->12->13->0.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
237
Register Description
Device:
22
Function: 0
Offset:
Bit
280h, 180h
Attr
Default
Description
RXAUTOINVSWPEN: Auto-inversion sweep enable
This bit enable the inversion shift register to continuously rotate the pattern in
the FIBRXSHFT register. This register enables the inversion pattern to the lane at
the bit position indicated by a logic 1.
0: Disable Auto-inversion
1: Enable Auto-inversion
24
23
RW
1
Intel 5000P Chipset MCHMAP: Southbound to northbound mapping for
loopback testing
This bit indicates which set of lanes are replicated onto the northbound lanes.
0: Lower SB lanes
1: Upper SB lanes
RW
RW
0
0
CMMSTR: Compliance Measurement Mode
This bit forces the component into link reset then transmits the default
Intel IBIST pattern set of a fixed binary “1100” pattern continuously (depending
on implementation) on all Tx lanes until this bit is cleared. If the Intel IBIST
engine is used for CMM, then the standard initialization sequence is follow with
TS0, TS1 training set prior to entry into Intel IBIST.
22
0: Disable CMM
1: Enable CMM. This feature requires the Intel IBIST start bit to be set before the
mode is enabled.
ERRCNT: Error Counter [9:0]
Total number of errors encountered in this port. Errors are accumulated per lane.
If several errors occurred in one phit time then a binary encoded value of the
number of errors is added to the error count.
21:12
11:8
RWST
ROST
000h
00h
ERRLNNUM: Error Lane Number [3:0]
This points to the first lane that encountered an error. If more than one lane
reports an error in a cycle, the most significant lane number that reported the
error will be logged.
ERRSTAT: Port Error Status [1:0]
When Intel IBIST is started, status goes to 01 until first start delimiter is received
and then goes to 00 until the end or to10/11 as appropriate.
00: No error.
7:6
RWCST
0
1
01: Did not receive first start delimiter.
10: Transmission error (first error).
11: Reserved.
AUTOINVSWPEN: Auto-inversion sweep enable
This bit enable the inversion shift register to continuously rotate the pattern in
the FIBTXSHFT and FIBRXSHFT registers. These registers enable the inversion
pattern to the lane at the bit position indicated by a logic 1.
5
RW
0: Disable Auto-inversion
1: Enable Auto-inversion
STOPONERR: Stop Intel IBIST on Error
0: Do not stop on error, only update error counter
1: Stop on error
4
3
2
RW
RW
1
0
0
LOOPCON: Loop forever
0: No looping
1: Loop forever
IBDONE: Intel IBIST done flag
0: Not done
RWCST
1: Done
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
22
Function: 0
Offset:
Bit
280h, 180h
Attr
Default
Description
MSTRMD: Master Mode Enable
When this bit is set the next TS1 training set that has the loopback bit set will
cause the transmitter to operate as a master. Even though the Intel IBIST is in
the loopback state it is not in loopback.
1
RWST
1
0: Disable Master mode. This component will not enter into master when a TS1
training set with loopback bit set.
1: Enable Master Mode on the next TS1 training with loopback bit set
IBSTR: IBIST Start
When set, it enables receiver logic to look for start delimiters during TS1 training
set. If the MSTRMD bit is set, the start bit enables the transmit state machine to
start transmitting patterns during the TS1 training set. The receiver is enable in
both cases.
For master-slave mode, the pattern will be looped back as defined in the FB-
DIMM spec. In master-master mode, the IBIST controller will originate patterns
and also check the incoming pattern for errors.
0
RWST
0
0: Stop IBIST transmitter
1: Start IBIST transmitter
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
239
Register Description
3.9.25.2
FBD[1:0]IBPORTCTL: FB-DIMM Intel IBIST Port Control Register
This register contains bits to control the operation of the Intel IBIST DFT feature.
Device:
21
Function: 0
Offset:
280h, 180h
Bit
Attr
Default
Description
31:26
RV
0h
Reserved
RXINVSWPMD: Rx Inversion Sweep Mode
0: Match Sweep according to the SB-to-NB_Mapping field in the TS1 training
sequence.
The default setting forces the RX inversion pointers to follow the unique
northbound inversion across the port width. It is based on a Modulo 5 of Intel
5000P Chipset MCHMAP bit setting. If e lanes Example;
If Intel 5000P Chipset MCHMAP = 0 then Lanes [4:0] are used as the reference
for checking Lanes[13:10], [9:5], and [4:0].
If Intel 5000P Chipset MCHMAP = 1 then Lanes [9:5] are used as the reference
for checking Lanes[13:10], [9:5], and [4:0].
25
RWST
0
For Intel 5000P Chipset MCH lane [13] does not exist but it does participate in
rotate-left-shift operations.
1: Enable full inversion sweep across the entire port.
When enabled the RX inversion pointers become a single entity.
Lanes [13:10] rotate left-shift completely across the width of the port. Even
though Lane[13] is a DFT lane it will be “shifted through” to make the logic
design easier.
0->1->2->3->4->5->6->7->8->9->10->11->12->13->0.
RXAUTOINVSWPEN: Auto-inversion sweep enable
This bit enable the inversion shift register to continuously rotate the pattern in
the FIBRXSHFT register.
0: Disable Auto-inversion
1: Enable Auto-inversion
24
23
RW
RW
1
0
Intel 5000P Chipset MCHMAP: Southbound to northbound mapping for
loopback testing
This bit indicates which set of lanes are replicated onto the northbound lanes.
0: Lower SB lanes
1: Upper SB lanes
CMMSTR: Compliance Measurement Mode
This bit forces the component into link reset then transmits the contents of the
default Intel IBIST pattern set continuously (depending on implementation) on
all Tx lanes until this bit is cleared and the IBSTR bit is cleared. If the Intel IBIST
engine is used for CMM then the standard initialization sequence is follow with
TS0, TS1 training set prior to entry into Intel IBIST.
22
RW
0
0: Disable CMM
1: Enable CMM. This feature requires the Intel IBIST start bit to be set before the
mode is enabled.
ERRCNT: Error Counter [9:0]
Total number of errors encountered in this port. Errors are accumulated per lane.
If several errors occurred in one phit time then a binary encoded value of the
number of errors is added to the error count.
21:12
11:8
RWST
ROST
000h
00h
ERRLNNUM: Error Lane Number [3:0]
This points to the first lane that encountered an error. If more than one lane
reports an error in a cycle, the most significant lane number that reported the
error will be logged.
ERRSTAT: Port Error Status [1:0]
When Intel IBIST is started, status goes to 01 until first start delimiter is received
and then goes to 00 until the end or to10/11 as appropriate.
00: No error.
7:6
RWCST
0
01: Did not receive first start delimiter.
10: Transmission error (first error).
11: Reserved.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
21
Function: 0
Offset:
Bit
280h, 180h
Attr
Default
Description
TXAUTOINVSWPEN: Auto-inversion sweep enable
This bit enable the inversion shift register to continuously rotate the pattern in
the FIBTXSHFT register.
0: Disable Auto-inversion
1: Enable Auto-inversion
5
4
RW
1
STOPONERR: Stop Intel IBIST on Error
0: Do not stop on error, only update error counter
1: Stop on error
RW
RW
1
0
0
1
LOOPCON: Loop continuously
Enable IBIST operations to loop continuously. The Intel IBIST pattern generator
executes the each pattern loop for the counts specified in the bit fields but the
overall loop runs continuously. This bit should be protected (gated) by the
component’s security mechanisms.
0: No continuous operation
1: Loop continuously
3
2
1
IBDONE: Intel IBIST done flag
0: Not done
1: Done
RWCST
RWST
MSTRMD: Master Mode Enable
When this bit is set the next TS1 training set that has the loopback bit set will
cause the transmitter to operate as a master. Even though the Intel IBIST is in
the loopback state it is not in loopback.
0: Disable Master mode. This component will not enter into master when a TS1
training set with loopback bit set.
1: Enable Master Mode on the next TS1 training with loopback bit set
IBSTR: Intel IBIST Start
When set, it enables receiver logic to look for start delimiters during TS1 training
set. If the MSTRMD bit is set, the start bit enables the transmit state machine to
start transmitting patterns during the TS1 training set. The receiver is enable in
both cases.
For master-slave mode, the pattern will be looped back as defined in the FB-
DIMM spec. In master-master mode, the Intel IBIST controller will originate
patterns and also check the incoming pattern for errors.
0
RWST
0
0: Stop Intel IBIST transmitter
1: Start Intel IBIST transmitter
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
241
Register Description
3.9.25.3
FBD[3:2]IBTXPGCTL: FB-DIMM Intel IBIST Pattern Generator Control
Register
This register contains bits to control the operation of the Intel IBIST pattern generator.
Device:
22
Function: 0
Offset:
Bit
284h, 184h
Attr
Default
Description
OVRLOPCNT: Overall Loop Count[5:0]
31:26 RWST
25:21 RWST
04h
0h: Send no Intel IBIST data in payload
1h-3Fh: The number of times to loop through all the patterns
CNSTGENCNT: Constant Generator Loop Counter[4:0]
00h: Disable constant generator output
01h: 1Fh The number of times the Modulo-N counter should be repeated before
going to the next pattern type. Each buffer transfer is composed of two frames
(loop counts of 24-bits each).
0h
0
CNSTGENSET: Constant Generator Setting
0: Generate 0
20
RWST
1: Generate 1
MODLOPCNT: Modulo-N Loop Counter [7:0]
Each count represents 24-bits of the pattern specified by the MODPERIOD bit field.
00h: Disable Pattern Output
01h: 7Fh The number of times the Pattern Buffer should loop before going to the
next
19:13 RWST
12:10 RWST
19h
MODPERIOD: Period of the Modulo-N counter
001: L/2 0101_0101_0101_0101_0101_0101
010: L/4 0011_0011_0011_0011_0011_0011
011: L/6 0001_1100_0111_0001_1100_0111
100: L/8 0000_1111_0000_1111_0000_1111
110: L/12 0000_0000_0000_1111_1111_1111
1h
PATTLOPCNT: Pattern Buffer Loop Counter[6:0]
00h: Disable Pattern Output
9:3
2:0
RWST
RWST
19h
01h-3Fh: The number of times the Pattern Buffer should be repeated before going
to the next pattern type. Each buffer transfer is composed of two frames (loop
counts of 24-bits each).
PTGENORD: Pattern Generation Order
000: Pattern Store + Modulo N Cntr + Constant Generator
001: Pattern Store + Constant Generator + Modulo N Cntr
010: Modulo N Cntr + Pattern Store + Constant Generator
011: Modulo N Cntr + Constant Generator + Pattern Store
100: Constant Generator + Pattern Store + Modulo N Cntr
101: Constant Generator + Modulo N Cntr + Pattern Store
110: Reserved
000
111: Reserved
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.25.4
FBD[1:0]IBTXPGCTL: FB-DIMM Intel IBIST Pattern Generator Control
Register
This register contains bits to control the operation of the Intel IBIST pattern generator.
Device:
21
Function: 0
Offset:
Bit
284h, 184h
Attr
Default
Description
OVRLOPCNT: Overall Loop Count[5:0]
31:26 RWST
25:21 RWST
04h
0h: Send no IBIST data in payload
1h-3Fh: The number of times to loop through all the patterns
CNSTGENCNT: Constant Generator Loop Counter[4:0]
00h: Disable constant generator output
01h: 1Fh The number of times the Modulo-N counter should be repeated before
going to the next pattern type. Each buffer transfer is composed of two frames
(loop counts of 24-bits each).
0h
0
CNSTGENSET: Constant Generator Setting
0: Generate 0
20
RWST
1: Generate 1
MODLOPCNT: Modulo-N Loop Counter
Each count represents 24-bits of the pattern specified by the MODPERIOD bit field.
00h: Disable Pattern Output
01h: 7Fh The number of times the Pattern Buffer should loop before going to the
next
19:13 RWST
12:10 RWST
19h
MODPERIOD: Period of the Modulo-N counter
001: L/2 0101_0101_0101_0101_0101_0101
010: L/4 0011_0011_0011_0011_0011_0011
011: L/6 0001_1100_0111_0001_1100_0111
100: L/8 0000_1111_0000_1111_0000_1111
110: L/12 0000_0000_0000_1111_1111_1111
1h
PATTLOPCNT: Pattern Buffer Loop Counter[6:0]
00h: Disable Pattern Output
9:3
2:0
RWST
RWST
19h
01h-3Fh: The number of times the Pattern Buffer should be repeated before going
to the next pattern type. Each buffer transfer is composed of two frames (loop
counts of 24-bits each).
PTGENORD: Pattern Generation Order
000: Pattern Store + Modulo N Cntr + Constant Generator
001: Pattern Store + Constant Generator + Modulo N Cntr
010: Modulo N Cntr + Pattern Store + Constant Generator
011: Modulo N Cntr + Constant Generator + Pattern Store
100: Constant Generator + Pattern Store + Modulo N Cntr
101: Constant Generator + Modulo N Cntr + Pattern Store
110: Reserved
000
111: Reserved
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
243
Register Description
3.9.25.5
3.9.25.6
3.9.25.7
FBD[3:2]IBPATBUF: FB-DIMM Intel BIST Pattern Buffer Register
This register contains the pattern bits used in Intel IBIST operations.
Device:
22
Function: 0
Offset:
Bit
288h, 188h
Attr Default
Description
31:24 RV
0
Reserved
23:0 RWST 02CCFDh
IBPATBUF: IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
FBD[1:0]IBPATBUF: FB-DIMM Intel IBIST Pattern Buffer Register
This register contains the pattern bits used in Intel IBIST operations.
Device:
21
Function: 0
Offset:
Bit
288h, 188h
Attr Default
Description
31:24 RV
0
Reserved
23:0 RWST 02CCFDh
IBPATBUF: IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
FBD[3:2]IBTXMSK: Intel IBIST Transmitter Mask
This register determines which lanes are enabled for Intel IBIST operations. These bits
also control the power saving features of each lane. If a particular lane is masked off,
the power to that lane is reduced as much as possible.
Device:
22
Function: 0
Offset:
28Ch, 18Ch
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
txmaskhvm: Transmit Mask extra DFT pins for HVM symmetry
13:10 RWST
0h
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
txmask: Transmit Mask
9:0
RWST
3FFh
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
3.9.25.8
FBD[1:0]IBTXMSK: Intel IBIST Transmitter Mask
This register determines which lanes are enabled for Intel IBIST operations. These bits
also control the power saving features of each lane. If a particular lane is masked off,
the power to that lane is reduced as much as possible.
Device:
21
Function: 0
Offset:
28Ch, 18Ch
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
®
244
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
21
Function: 0
Offset:
Bit
28Ch, 18Ch
Attr
Default
Description
txmaskhvm: Transmit Mask extra DFT pins for HVM symmetry
13:10 RWST
0h
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
txmask: Transmit Mask
9:0
RWST
3FFh
Selects which lanes to enable for testing. A lane that is not selected remains
in electrical idle.
3.9.25.9
FBD[3:2]IBRXMSK: Intel IBIST Receiver Mask
This register determines which lanes are enabled for Intel IBIST operations. These bits
also control the power saving features of each lane. If a particular lane is masked off,
the power to that lane is reduced as much as possible.
Device:
22
Function: 0
Offset:
290h, 190h
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
rxmask: Receive Mask
Selects which lanes to enable for testing. An Rx lane that is not selected is not
included in Rx channel training does not contribute to the accumulation of
error counts.
13:0
RWST
1FFFh
3.9.25.10 FBD[1:0]IBRXMSK: Intel IBIST Receiver Mask
This register determines which lanes are enabled for Intel IBIST operations. These bits
also control the power saving features of each lane. If a particular lane is masked off,
the power to that lane is reduced as much as possible.
Device:
21
Function: 0
Offset:
290h, 190h
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
rxmask: Receive Mask
Selects which lanes to enable for testing. An Rx lane that is not selected is not
included in Rx channel training does not contribute to the accumulation of
error counts.
13:0
RWST
1FFFh
3.9.25.11 FBD[3:2]IBTXSHFT: Intel IBIST Transmit Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
Device:
22
Function: 0
Offset:
294h, 194h
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
245
Register Description
Device:
22
Function: 0
Offset:
Bit
294h, 194h
Attr
Default
Description
txinvshfthvm: Transmit Inversion shift register extra DFT pins for HVM
symmetry
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during Intel IBIST
operations.
13:10 RWST
0h
txinvshft: Transmitter Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during Intel IBIST
operations.
9:0
RWST
001h
3.9.25.12 FBD[1:0]IBTXSHFT: Intel IBIST Transmit Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
Device:
21
Function: 0
Offset:
294h, 194h
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
txinvshfthvm: Transmit Inversion shift register extra DFT pins for HVM
symmetry
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during Intel IBIST
operations.
13:10 RWST
0h
txinvshft: Transmitter Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. Because this is a shift register the
initial value will be left-shifted at the end of the loop count during Intel IBIST
operations.
9:0
RWST
001h
3.9.25.13 FBD[3:2]IBRXSHFT: Intel IBIST Receive Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
Device:
22
Function: 0
Offset:
298h, 198h
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
rxinvshfthi: Receiver Inversion Shift Register for DFT
The pattern loaded in this bit field indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This bit location will experience
rotate-left-shift operation with bits[12:0].
13
RWST
0
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
22
Function: 0
Offset:
Bit
298h, 198h
Attr
Default
Description
rxinvshft: Receiver Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This register acts as a rotate-left
shift register regardless of the setting of RXINVSWPMD bit. The Modulo-5
value is used to compare each sub-section of the northbound lanes for error
checking.
12:0
RWST
0001h
3.9.25.14 FBD[1:0]IBRXSHFT: Intel IBIST Receive Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
Device:
21
Function: 0
Offset:
298h, 198h
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
rxinvshfthi: Receiver Inversion Shift Register for DFT
The pattern loaded in this bit field indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This bit location will experience
rotate-left-shift operation with bits[12:0].
13
RWST
RWST
0
rxinvshft: Receiver Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This register acts as a rotate-left
shift register regardless of the setting of RXINVSWPMD bit. The Modulo-5
value is used to compare each sub-section of the northbound lanes for error
checking.
12:0
0001h
3.9.25.15 FBD[3:2]LNERR: IBIST Receive Lane Error Register
This register enables IBIST operations for individual lanes.
Device:
22
Function: 0
Offset:
29Ch, 19Ch
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
rxerrstat: Receive error lane status for DFT.
This register records the error from lane 13 of this port.
13
ROST
ROST
0
0
rxerrstat: Receive error lane status.
This register records the errors from all lanes of this port.
12:0
3.9.25.16 FBD[1:0]LNERR: Intel IBIST Receive Lane Error Register
This register enables Intel IBIST operations for individual lanes.
Device:
21
Function: 0
Offset:
29Ch, 19Ch
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
247
Register Description
Device:
21
Function: 0
Offset:
Bit
29Ch, 19Ch
Attr
Default
Description
rxerrstat: Receive error lane status for DFT.
This register records the error from lane 13 of this port.
13
ROST
0
rxerrstat: Receive error lane status.
This register records the errors from all lanes of this port.
12:0
ROST
0
3.9.25.17 FBD[3:2]IBRXPGCTL: FB-DIMM Intel IBIST Rx Pattern Generator
Control Register
This register contains bits to control the operation of the Rx pattern generator.
Device:
22
Function: 0
Offset:
Bit
2A0h, 1A0h
Attr
Default
Description
OVRLOPCNT: Overall Loop Count[5:0]
31:26 RWST
25:21 RWST
04h
0h: Send no Intel IBIST data in payload
1h-3Fh: The number of times to loop through all the patterns
CNSTGENCNT: Constant Generator Loop Counter[4:0]
00h: Disable constant generator output
01h: 1Fh The number of times the Modulo-N counter should be repeated before
going to the next pattern type. Each buffer transfer is composed of two frames
(loop counts of 24-bits each).
0h
0
CNSTGENSET: Constant Generator Setting
0: Generate 0
20
RWST
1: Generate 1
MODLOPCNT: Modulo-N Loop Counter [7:0]
Each count represents 24-bits of the pattern specified by the MODPERIOD bit field.
00h: Disable Pattern Output
01h: 7Fh The number of times the Pattern Buffer should loop before going to the
next
19:13 RWST
12:10 RWST
19h
MODPERIOD: Period of the Modulo-N counter
001: L/2 0101_0101_0101_0101_0101_0101
010: L/4 0011_0011_0011_0011_0011_0011
011: L/6 0001_1100_0111_0001_1100_0111
100: L/8 0000_1111_0000_1111_0000_1111
110: L/12 0000_0000_0000_1111_1111_1111
1h
PATTLOPCNT: Pattern Buffer Loop Counter[6:0]
00h: Disable Pattern Output
9:3
2:0
RWST
RWST
19h
01h-3Fh: The number of times the Pattern Buffer should be repeated before going
to the next pattern type. Each buffer transfer is composed of two frames (loop
counts of 24-bits each).
PTGENORD: Pattern Generation Order
000: Pattern Store + Modulo N Cntr + Constant Generator
001: Pattern Store + Constant Generator + Modulo N Cntr
010: Modulo N Cntr + Pattern Store + Constant Generator
011: Modulo N Cntr + Constant Generator + Pattern Store
100: Constant Generator + Pattern Store + Modulo N Cntr
101: Constant Generator + Modulo N Cntr + Pattern Store
110: Reserved
000
111: Reserved
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.9.25.18 FBD[1:0]IBRXPGCTL: FB-DIMM Intel IBIST Rx Pattern Generator
Control Register
This register contains bits to control the operation of the RX pattern generator.
Device:
21
Function: 0
Offset:
Bit
2A0h, 1A0h
Attr
Default
Description
OVRLOPCNT: Overall Loop Count[5:0]
31:26 RWST
25:21 RWST
04h
0h: Send no Intel IBIST data in payload
1h-3Fh: The number of times to loop through all the patterns
CNSTGENCNT: Constant Generator Loop Counter[4:0]
00h: Disable constant generator output
01h: 1Fh The number of times the Modulo-N counter should be repeated before
going to the next pattern type. Each buffer transfer is composed of two frames
(loop counts of 24-bits each).
0h
0
CNSTGENSET: Constant Generator Setting
0: Generate 0
20
RWST
1: Generate 1
MODLOPCNT: Modulo-N Loop Counter
Each count represents 24-bits of the pattern specified by the MODPERIOD bit field.
00h: Disable Pattern Output
01h: 7Fh The number of times the Pattern Buffer should loop before going to the
next
19:13 RWST
12:10 RWST
19h
MODPERIOD: Period of the Modulo-N counter
001: L/2 0101_0101_0101_0101_0101_0101
010: L/4 0011_0011_0011_0011_0011_0011
011: L/6 0001_1100_0111_0001_1100_0111
100: L/8 0000_1111_0000_1111_0000_1111
110: L/12 0000_0000_0000_1111_1111_1111
1h
PATTLOPCNT: Pattern Buffer Loop Counter[6:0]
00h: Disable Pattern Output
9:3
2:0
RWST
RWST
19h
01h-3Fh: The number of times the Pattern Buffer should be repeated before going
to the next pattern type. Each buffer transfer is composed of two frames (loop
counts of 24-bits each).
PTGENORD: Pattern Generation Order
000: Pattern Store + Modulo N Cntr + Constant Generator
001: Pattern Store + Constant Generator + Modulo N Cntr
010: Modulo N Cntr + Pattern Store + Constant Generator
011: Modulo N Cntr + Constant Generator + Pattern Store
100: Constant Generator + Pattern Store + Modulo N Cntr
101: Constant Generator + Modulo N Cntr + Pattern Store
110: Reserved
000
111: Reserved
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
249
Register Description
3.9.25.19 FBD[3:2]IBPATBUF2: FB-DIMM Intel IBIST Pattern Buffer 2 Register
This register contains the pattern bits used in Intel IBIST operations.
Device:
22
Function: 0
Offset:
Bit
2A4h, 1A4h
Attr Default
Description
31:24 RV
0
Reserved
23:0 RWST 02CCFDh
IBPATBUF: Intel IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
3.9.25.20 FBD[1:0]IBPATBUF2: FB-DIMM Intel IBIST Pattern Buffer 2 Register
This register contains the pattern bits used in Intel IBIST operations.
Device:
21
Function: 0
Offset:
Bit
2A4h, 1A4h
Attr Default
Description
31:24 RV
0
Reserved
23:0 RWST 02CCFDh
IBPATBUF: Intel IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
3.9.25.21 FBD[3:2]IBTXPAT2EN: Intel IBIST TX Pattern Buffer 2 Enable
This register enables which channels are inverted when Intel IBIST operations are
activated.
Device:
22
Function: 0
Offset:
2A8h, 1A8h
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
txpatt2hvmen: receiver Pattern Buffer 2 Enable for the HVM lanes
Selects which channels to enable the second pattern buffer.
13:10 RWST
Fh
txpatt2en: receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
9:0
RWST
3FFh
3.9.25.22 FBD[1:0]IBTXPAT2EN: Intel IBIST TX Pattern Buffer 2 Enable
This register enables which channels are inverted when Intel IBIST operations are
activated.
®
250
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
21
Function: 0
Offset:
2A8h, 1A8h
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
txpatt2hvmen: receiver Pattern Buffer 2 Enable for the HVM lanes
Selects which channels to enable the second pattern buffer.
13:10 RWST
Fh
txpatt2en: receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
9:0
RWST
3FFh
3.9.25.23 FBD[3:2]IBRXPAT2EN: Intel IBIST RX Pattern Buffer 2 Enable
This register enables inversion pattern testing on individual lanes.
Device:
22
Function: 0
Offset:
2ACh, 1ACh
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
rxpatt2en: Receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
13:0
RWST
3FFFh
3.9.25.24 FBD[1:0]IBRXPAT2EN: Intel IBIST RX Pattern Buffer 2 Enable
This register enables inversion pattern testing on individual lanes.
Device:
21
Function: 0
Offset:
2ACh, 1ACh
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
rxpatt2en: Receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
13:0
RWST
3FFFh
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
251
Register Description
3.9.26
Serial Presence Detect Registers
There are two sets of the following registers, one set for each FB-DIMM branch. They
each appear in function 0 of different devices as shown in Table 3-3.
3.9.26.1
SPD[1:0][1:0] - Serial Presence Detect Status Register
This register provides the interface to the SPD bus (SCL and SDA signals) that is used
to access the Serial Presence Detect EEPROM that defines the technology,
configuration, and speed of the DIMM’s controlled by the MCH.
Device:
Function:
Offset:
21
0
76h, 74h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
76h, 74h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15
RO
0
RDO: Read Data Valid.
This bit is set by the AMB when the Data field of this register receives read data
from the SPD EEPROM after successful completion of an SPDR command. It is
cleared by the Intel 5000P Chipset MCH when a subsequent SPDR command is
issued.
14
13
12
RO
RO
RO
0
0
0
WOD: Write Operation Done.
This bit is set by the Intel 5000P Chipset MCH when a SPDW command has been
completed on the SPD bus. It is cleared by the Intel 5000P Chipset MCH when a
subsequent SPDW command is issued.
SBE: SPD Bus Error.
This bit is set by the Intel 5000P Chipset MCH if it initiates an SPD bus transaction
that does not complete successfully. It is cleared by the AMB when an SPDR or
SPDW command is issued.
BUSY: Busy state.
This bit is set by the Intel 5000P Chipset MCH while an SPD command is executing.
11:8
7:0
RV
RO
0h
Reserved.
00h
DATA: Data.
Holds data read from SPDR commands.
3.9.26.2
SPDCMD[1:0][1:0] - Serial Presence Detect Command Register
A write to this register initiates a DIMM EEPROM access through the SPD bus.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
21
Function:
Offset:
0
7Ch, 78h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
22
0
7Ch, 78h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:28 RWST
1010
DTI: Device Type Identifier.
This field specifies the device type identifier. Only devices with this device-type will
respond to commands. “1010” specifies EEPROM’s. “0110” specifies a write-protect
operation for an EEPROM. Other identifiers can be specified to target non-EEPROM
devices on the SPD bus.
27
RWST
1
CKOVRD: Clock Override.
‘0’ = Clock signal is driven low, overriding writing a ‘1’ to CMD.
‘1’ = Clock signal is released high, allowing normal operation of CMD.
Toggling this bit can be used to “move” the port out of a “stuck” state.
26:24 RWST
23:16 RWST
000
00h
00h
SA: Slave Address.
This field identifies the DIMM EEPROM to be accessed through the SPD register.
BA: Byte Address.
This field identifies the byte address to be accessed through the SPD register.
15:8
RWST
DATA: Data.
Holds data to be written by SPDW commands.
7:1
0
RV
0h
0
Reserved
RWST
CMD: Command.
Writing a ‘0’ to this bit initiates an SPDR command. Writing a ‘1’ to this bit initiates
an SPDW command.
3.10
DMA Engine Configuration Registers
3.10.1
PCICMD: PCI Command Register
Device:
Function:
Offset:
8
0
04h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
15:11 RV
0h
0
Reserved
10
RW
INTxDisable: Interrupt Disable
This bit controls the ability of the DMA engine device to assert a legacy PCI
interrupt during DMA completions or DMA errors.
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
9
RO
0
FB2B: Fast Back-to-Back Enable
This bit does not apply to the DMA engine Device and hardwired to 0.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
253
Register Description
Device:
Function:
Offset:
8
0
04h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
8
RW
0
SERRE: SERR Message Enable
This bit indicates whether the DMA Engine device is allowed to signal a SERR
condition.
This field handles the reporting of fatal and non-fatal errors by enabling the error
pins ERR[2:0].
1: The DMA engine device is enabled to send fatal/non-fatal errors.
0: The DMA engine device is disabled from generating fatal/non-fatal errors.
7
6
RV
0
0
Reserved
RW
PERRRSP: Parity Error Response
Controls the response when a parity error is detected in the DMA engine
1: The device can report Parity errors
0: Parity errors can be ignored by the device.
5:4
3
RV
RO
00
0
Reserved
SPCEN: Special Cycle Enable
This bit does not apply to the DMA Engine Device.
2
RW
0
BME: Bus Master Enable
Controls the ability for the DMA engine device to initiate transactions to memory
including MMIO
1: Enables the DMA engine device to successfully complete memory read/write
requests.
0: Disables upstream memory writes/reads
If this bit is not set and the DMA engine is programmed by software to process
descriptors, the Chipset will flag read(write) errors (*DMA8/*DMA9) and also
record the errors in the CHANERR registers when it attempts to issue cacheline
requests to memory.
1
0
RW
RO
0
0
MAEN: Memory Access Enable
Controls the ability for the DMA Engine Device to respond to memory mapped I/O
transactions initiated in the Intel 5000P Chipset MCH in its range.
1: Allow MMIO accesses in the DMA Engine
0: Disable MMIO accesses in DMA Engine
This only applies to access CB_BAR space in Device 8, fn 1 where the MMIO space
resides (Requests from both fast/slow paths will be master-aborted)
IOAEN: I/O Access Enable
Controls the ability for the DMA Engine Device to respond to legacy I/O
transactions. The DMA Engine Device does not support/allow legacy I/O cycles.
The PCI Command register follows a subset of the PCI Local Bus Specification, Revision
2.3 specification. This register provides the basic control of the ability of the DMA
engine device to initiate and respond to transactions sent to it and maintains
compatibility with PCI configuration space.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.10.2
PCISTS: PCI Status Register
Device:
Function:
Offset:
8
0
06h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
15
Attr
Default
Description
RWC
RWC
0
DPE: Detected Parity Error
This bit is set when the DMA engine device receives an uncorrectable data error or
Address/Control parity errors regardless of the Parity Error Enable bit (PERRE). This
applies only to parity errors that target the DMA engine device (inbound/outbound
direction). The detected parity error maps to B1, F6, M2 and M4 (uncorrectable data
error from FSB, Memory or internal sources). The DMA engine also records the data
parity error in bit[6] (Cdata_par_err)of the CHANERR register.
14
0
SSE: Signalled System Error
1: The DMA engine device reported internal FATAL/NON FATAL errors (DMA0-15)
through the ERR[2:0] pins with SERRE bit enabled. Software clears this bit by
writing a ‘1’ to it.
0: No internal DMA engine device port errors are signaled.
13
12
11
10:9
8
RO
0
RMA: Received Master Abort Status
This field is hardwired to 0 as there is no Master Abort for the DMA operations
RWC
RWC
RO
0
RTA: Received Target Abort Status
This field is hardwired to 0 as there is no Target Abort for the DMA operations
0
STA: Signalled Target Abort Status:
This field is hardwired to 0
00
0
DEVSELT: DEVSEL# Timing:
This bit does not apply to the DMA Engine Device.
RWC
MDIERR: Master Data Integrity Error
This bit is set by the DMA engine device if the Parity Error Enable bit (PERRE) is
set and it receives error B1, F2, F6, M2 and M4 (uncorrectable data error or
Address/Control parity errors or an internal failure). If the PERRRSP bit in the
Section 3.10.1 is cleared, this bit is never set.
7
RO
0
FB2B: Fast Back-to-Back Capable
Not applicable to DMA Engine. Hardwired to 0.
6
5
RV
RO
0
0
Reserved
66MHZCAP: 66MHz capable.
Not applicable to DMA Engine. Hardwired to 0.
4
3
RO
RO
1
0
CAPL: Capability List Implemented:
This bit indicated that the DMA Engine device implements a PCI Capability list. See
CAPPTR at offset 34h
INTxST: INTx State
This bit is set by the hardware when the DMA engine device issues a legacy INTx
(pending) and is reset when the Intx is deasserted.
The intx status bit should be deasserted when all the relevant
status bits/events viz DMA errors/completions that require
legacy interrupts are cleared by software.
2:0
RV
000
Reserved
The PCI Status register follows a subset of the PCI Local Bus Specification, Revision 2.3
specification. This register maintains compatibility with PCI configuration space. Since
this register is part of the standard PCI header, there is a PCISTS register per PCI
function.
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255
Register Description
3.10.3
CCR: Class Code Register
Device:
Function:
Offset:
8
0
09h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
08h
Description
23:16 RWO
Base Class Code: A 08H code indicates that the DMA engine device is a
peripheral device . A 06H code is used to indicate a Host bridge device.
1
Default: 08h
15:8
RWO
RWO
80h
0h
Sub-Class Code: An 80H code indicates that the DMA engine device is a non-
specific peripheral device. A 00H code is used to indicate a Host bridge device.
Default: 80h
7:0
Register-Level Programming Interface: This field identifies a default value
for non-specific programming requirements.
Notes:
1. A peripheral device in this case denotes an integrated device in the root complex.
The bits in this register are writable once by BIOS in order to allow the device to be
programmable either as an OS-visible device [088000h](implementing a driver) or a
chipset host bridge device [060000h] (relying on BIOS code and/or pure hardware
control for programming the DMA engine registers). The default value of the CCR is set
to 088000h (corresponding to an integrated device in the root port).
3.10.4
CB_BAR: DMA Engine Base Address Register
Device:
Function:
Offset:
8
0
10h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
63:40 RO
0h
CB_BASE_Win_Upper: Upper DMABase Window:
The upper bits of the 64-bit addressable space are initialized to 0 as default
and is unusable in Intel 5000 Series Chipset.
39:10 RW
003F9C00h
CB_BASE_WIN: DMABase Window
This marks the 1KB memory-mapped registers used for the chipset DMA and
can be placed in any MMIO region (low/high) within the physical limits of the
system. For instance the Intel 5000P Chipset MCH uses only 40-bit
addressable space. Hence bits 39:10 are assumed to be valid and also contains
the default value of the CB_BAR in the FE70_0000h to FE70_03FFh range.
9:4
3
RV
RO
0h
0
Reserved
Pref: Prefetchable
The DMA registers are not prefetchable.
2:1
0
RO
RO
10
0
Type: Type
The DMA registers is 64-bit address space and can be placed anywhere within
the addressable region of the Intel 5000 Series Chipset (up to 40-bits).
Mem_space: Memory Space
This Base Address Register indicates memory space.
This DMA Engine base address register marks the memory-mapped registers used for
the DMA functionality.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.10.5
CAPPTR: Capability Pointer Register
Device:
Function:
Offset:
8
0
34h
Version:
Intel 5000P Chipset
Bit
7:0
Attr
RO
Default
Description
50h
CAPPTR: Capability Pointer
This register field points to the first capability. PM structure in the DMA Engine
device.
3.10.6
INTL: Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between initialization code and the device driver. The Intel 5000 Series MCH does not
have a dedicated interrupt line and is not used.
Device:
Function:
Offset:
8
0
3Ch
Version:
Intel 5000P Chipset
Bit
7:0
Attr
RWO
Default
Description
00h
INTL: Interrupt Line
BIOS writes the interrupt routing information to this register to indicate which input
of the interrupt controller this PCI-Express Port is connected to. Not used in the
Intel 5000 Series MCH since the PCI-Express port does not have an interrupt lines.
3.10.7
INTP: Interrupt Pin Register
The INTP register identifies legacy interrupts for INTA, INTB, INTC and INTD as
determined by BIOS/firmware. These are emulated over the ESI port using the
Assert_Intx commands as appropriate.
Device:
Function:
Offset:
8
0
3Dh
Version:
Intel 5000P Chipset
Bit
Attr
RWO
Default
Description
7:0
01h
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI Express port.
001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
3.10.8
Power Management Capability Structure
The DMA engine integrated device within the MCH incorporates power management
capability with D0 (working) and a pseudo D3 hot/cold states (sleep) that can be
controlled independently through software. From a software perspective, the D3 states
convey information to the power controller that the device is in the sleep mode though
the physical entity inside the chipset may be fully powered. During transition1 from D0
to D3, it will ensure that all pending DMA Channels are completed in full.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
257
Register Description
3.10.8.1
PMCAP - Power Management Capabilities Register
The PM Capabilities Register defines the capability ID, next pointer and other power
management related support. The following PM registers /capabilities are added for
software compliance.
Device:
Function:
Offset:
8
0
50h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:27
RO
11001
PMES: PME Support
Identifies power states which assert PMEOUT. Bits 31, 30 and 27 must be set
to '1' for PCI-PCI bridge structures representing ports on root complexes. The
definition of these bits is taken from the PCI Bus Power Management Interface
Specification Revision 1.1.
XXXX1b - PMEOUT can be asserted from D0
XXX1Xb - PMEOUT can be asserted from D1 (Not supported by Intel 5000P
Chipset MCH)
XX1XXb - PMEOUT can be asserted from D2 (Not supported by Intel 5000P
Chipset MCH)
X1XXXb - PMEOUT can be asserted from D3 hot
1XXXXb - PMEOUT can be asserted from D3 cold
26
25
RO
RO
0
0
D2S: D2 Support
The Intel 5000P Chipset MCH does not support power management state D2.
D1S: D1 Support
The Intel 5000P Chipset MCH does not support power management state D1.
24:22
21
RO
RO
RV
RO
0h
0
AUXCUR: AUX Current
DSI: Device Specific Initialization
Reserved.
20
0
19
0
PMECLK: PME Clock
This field is hardwired to 0h.
18:16
15:8
7:0
RO
RO
RO
010
58h
01h
VER: Version
This field is set to 2h as version number from the PCI Express 1.0
specification.
NXTCAPPTR: Next Capability Pointer
This field is set to offset 58h for the next capability structure (MSI) in the PCI
2.3 compatible space.
CAPID: Capability ID
Provides the PM capability ID assigned by PCI-SIG.
1. When software initiates an S0 => S3 transition, it should make the DMA engine device to enter
D3 before completing the power management handshake with the MCH.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.10.8.2
PMCSR - Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express port of the DMA
Engine Device.
Device:
Function:
Offset:
8
0
54h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:24
RO
0h
Data: Data
Data read out based on data select (DSEL). Refer to section 3.2.6 of PCI PM
specification for details. This is not implemented in the e Power
Management capability for Intel 5000P Chipset MCH and is hardwired to
0h.
23
22
RO
RO
0h
0h
BPCCEN: Bus Power/Clock Control Enable
This field is hardwired to 0h.
B2B3S: B2/B3 Support
This field is hardwired to 0h.
21:16
15
RV
0h
0h
Reserved.
RWCST
PMESTS: PME Status
This PME Status is a sticky bit. When set, the device generates a PME
internally independent of the PMEEN bit defined below. Software clears
this bit by writing a ‘1’.
As an integrated device within the root complex, the Intel 5000P Chipset
MCH will never set this bit, because it never generates a PME internally
independent of the PMEEN bit.
14:13
12:9
8
RO
RO
0h
0h
0h
DSCL: Data Scale
This 2-bit field indicates the scaling factor to be used while interpreting the
“data_scale” field.
DSEL: Data Select
This 4-bit field is used to select which data is to reported through the “data”
and the “Data Scale” fields.
RWST
PMEEN: PME Enable
This field is a sticky bit and when set enables PMEs generated internally to
appear at the Intel 631xESB/632xESB I/O Controller Hub through the
“Assert(Deassert)_PMEGPE”message. This has no effect on the Intel
5000P Chipset MCH since it does not generate PME events internally.
7:2
1:0
RV
0h
0h
Reserved.
RW
PS: Power State
This 2-bit field is used to determine the current power state of the function
and to set a new power state as well.
00: D0
01: D1 (reserved)
10: D2 (reserved)
11: D3_hot
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
259
Register Description
3.10.9
MSICAPID - Message Signalled Interrupt Capability ID
Register
Device:
Function:
Offset:
8
0
58h
Version:
Intel 5000P Chipset
Bit
7:0
Attr
RO
Default
Description
05h
CAPID: MSI Capability ID
This code denotes the standard MSI capability assigned by PCI-SIG
3.10.10 MSINXPTR - Message Signalled Interrupt Next Pointer
Register
Device:
Function:
Offset:
8
0
59h
Version:
Intel 5000P Chipset
Bit
7:0
Attr
RO
Default
Description
6Ch
NXTPTR: MSI Next Pointer: The DMA Engine device is implemented as a PCI
Express device and this points to the PCI Express capability structure.
3.10.11 MSICTRL - Message Signalled Interrupt Control Register
Device:
Function:
Offset:
8
0
5Ah
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:8
7
RO
RO
0h
0
Reserved
AD64CAP: 64-bit Address Capable
All processors used with the GNC MCH do not support 64-bit addressing, hence this
is hardwired to 0
6:4
3:1
RW
RO
000
0h
MMEN: Multiple Message Enable
Software initializes this to indicate the number of allocate messages which is
aligned to a power of two. When MSI is enabled, the software will allocate at least
one message to the device. See Section 3.10.13 below for discussion on how the
interrupts are handled.
MMCAP: Multiple Message Capable
The Intel 5000P Chipset MCH DMA Engine supports only one interrupt message
(power of two) for handling
• DMA errors
• DMA completions
0
RW
0
MSIEN: MSI Enable
This bit enables MSI as the interrupt mode of operation instead of the legacy
interrupt mechanism.
0: Disables MSI from being generated.
1: Enables MSI messages to be generated for DMA related interrupts.
An extract of the flowchart of the DMA Engine error handling is given in Figure 3-7
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260
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Figure 3-7. Intel 5000P Chipset DMA Error/Channel Completion Interrupt Handling Flow
DMA errors/completion
interrupts
Y
Y
(PEXCTRL[x]
MSICBEN == 1)?
(MSICTRL[x].
MSIEN == 1)
MSIDR
N
N
Intel® 5000P Chipset
N
PEXCMD[x].INTx
Disable == 1?
Sends assert_INTx
message via DMI
per INTP
Will send only 1
MSI For both DMA
interrupts and
Channel completions
Y
Intel® 5000P Chipset
Sends deassert_INTx
message via DMI
per INTP when
INTRCTRL.intp is
reset (wired-OR)
MSIEN
MSICBEN
INTx Disable
Output
1
1
0
0
1
0
x
x
x
x
0
1
MSI
--
assert_intx
--
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
261
Register Description
3.10.12 MSIAR: Message Signalled Interrupt Address Register
Device:
Function:
Offset:
8
0
5Ch
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:20
RO
FEEh
AMSB: Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address.
19:12
RW
0h
ADSTID: Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
11:4
3
RW
RW
0h
0
AEXDSTID: Address Extended Destination ID
This field is not used by IA32 processor.
ARDHINT: Address Redirection Hint
0: directed
1: redirectable
2
RW
RV
0
ADM: Address Destination Mode
0: physical
1: logical
1:0
00
Reserved.
Not used since the memory write is D-word aligned
3.10.13 MSIDR: Message Signalled Interrupt Data Register
Device:
Function:
Offset:
8
0
60h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:16
15
RV
0000h Reserved.
RW
0h
0h
TM: Trigger Mode
This field Specifies the type of trigger operation
0: Edge
1: level
14
RW
LVL: Level
if TM is 0h, then this field is a don’t care.
Edge triggered messages are consistently treated as assert messages.
For level triggered interrupts, this bit reflects the state of the interrupt input
if TM is 1h, then:
0: Deassert Messages
1: Assert Messages
13:11
RW
0h
These bits are don’t care in IOxAPIC interrupt message data field specification.
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262
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
8
Function:
Offset:
0
60h
Version:
Intel 5000P Chipset
Bit
Attr
RW
Default
Description
10:8
0h
DM: Delivery Mode
000: Fixed
001: Lowest Priority
010: SMI/HMI
011: Reserved
100: NMI
101: INIT
110: Reserved
111: ExtINT
7:0
RW
0h
IV: Interrupt Vector
The interrupt vector as programmed by BIOS/Software will be used by the Intel
5000P Chipset MCH to provide context sensitive interrupt information for different
events such as DMA Errors, DMA completions that require attention from the
processor. See Table 3-50 for IV handling for DMA.
Table 3-50. IV Vector Table for DMA Errors and Interrupts
Number of Messages
enabled by Software
(MMEN)
Events
IV[7:0]
xxxxxxxx1
1
All
(DMA completions/errors)
Notes:
1. The term “xxxxxx” in the Interrupt vector denotes that software/BIOS initializes them
and the MCH will not modify any of the “x” bits since it handles only 1 message vector
that is common to all events
3.10.14 PEXCAPID: PCI Express Capability ID Register
Device:
Function:
Offset:
8
0
6Ch
Version:
Intel 5000P Chipset
Bit
7:0
Attr
RO
Default
Description
10h
CAPID: PCI Express Capability ID
This code denotes the standard PCI Express capability.
3.10.15 PEXNPTR: PCI Express Next Pointer Register
Device:
Function:
Offset:
8
0
6Dh
Version:
Intel 5000P Chipset
Bit
7:0
Attr
RO
Default
Description
00h
NXTPTR: PCI Express Next Pointer
The PCI Express capability structure is the last capability in the linked list and set to
NULL.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
263
Register Description
3.10.16 PEXCAPS - PCI Express Capabilities Register
Device:
Function:
Offset:
8
0
6Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:14 RV
0h
0h
Reserved
13:9
RO
RO
IMN: Interrupt Message Number:
This field indicates the interrupt message number that is generated from the DMA
Engine device. When there are more than one MSI interrupt Number, this register
field is required to contain the offset between the base Message Data and the MSI
Message that is generated when the status bits in the slot status register or root port
status registers are set.
8
0
Slot_Impl: Slot Implemented: DMA Engine is an integrated device and therefore a
slot is never implemented.
7:4
3:0
RO
RO
0000
0001
DPT: Device/Port Type: DMA Engine device represents a PCI Express Endpoint.
VERS: Capability Version: DMA Engine supports Revision 1 of the PCI Express
specification.
3.10.17 PEXDEVCAP - Device Capabilities Register
Device:
Function:
Offset:
8
0
70h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
31:28 RV
27:26 RO
0h
00
Reserved
CSPLS: Captured Slot Power Limit Scale
This field applies only to upstream ports. Hardwired to 0h
25:18 RO
17:15 RV
00h
CSPLV: Captured Slot Power Limit Value
This field applies only to upstream ports. Hardwired to 0h
0h
0
Reserved
14
RO
RO
RO
RO
RO
PIPD: Power Indicator Present
The DMA Engine is an integrated device and therefore, an Power Indicator does not
exist. Hardwired to 0h
13
0
AIPD: Attention Indicator Present
The DMA Engine is an integrated device and therefore, an Attention Indicator does
not exist. Hardwired to 0h
12
0
ABPD: Attention Button Present
The DMA Engine is an integrated device and therefore, an Attention Button does not
exist. Hardwired to 0h
11:9
8:6
000
000
EPL1AL: Endpoint L1 Acceptable Latency
The DMA Engine device is not implemented on a physical PCI Express link and
therefore, this value is irrelevant. Hardwired to 0h
EPL0AL: Endpoint L0s Acceptable Latency
The DMA Engine device is not implemented on a physical PCI Express link and
therefore, this value is irrelevant. Hardwired to 0h
5
RO
RO
0
ETFS: Extended Tag Field Supported
The DMA Engine device does not support extended tags. Hardwired to 0h
4:3
00
PFS: Phantom Functions Supported
The DMA Engine device does not support Phantom Functions. Hardwired to 0h
®
264
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
8
Function:
Offset:
0
70h
Version:
Intel 5000P Chipset
Bit
2:0
Attr
RO
Default
Description
000
MPLSS: Max_Payload_Size Supported
This field indicates the maximum payload size that the CB integrated device can
support.
000: 128B max payload size
others- Reserved
3.10.18 PEXDEVCTRL - Device Control Register
Device:
Function:
Offset:
8
0
74h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15
RV
0
Reserved
14:12 RO
000
MRRS: Max_Read_Request_Size
Since the DMA Engine device does not issue read requests on a PCI Express
interface, this field is irrelevant. Hardwired to 0h
11
RW
1
ENNOSNP: Enable No Snoop
1: Setting this bit enables the DMA Engine device to issue requests with the No
Snoop attribute.
0: Clearing this bit behaves as a global disable when the corresponding capability is
enabled for source/destination snoop control in the DMA’s descriptor’s Desc_Control
field.
10
9
RO
RO
RO
RW
0
APPME: Auxiliary Power PM Enable
The DMA Engine device does not implement auxiliary power so setting this bit has
no effect. Hardwired to 0h
0
PFEN: Phantom Functions Enable
The DMA Engine device does not implement phantom functions so setting this bit
has no effect. Hardwired to 0h
8
0
ETFEN: Extended Tag Field Enable:
The DMA Engine device does not implement extended tags so setting this bit has no
effect.
7:5
000
MPS: Max_Payload_Size:
The DMA Engine device must not generate packets on any PCI Express interface
which exceeds the length allowed with this field.
000: 128B max payload size
001: 256B max payload size
010: 512B max payload size
011: 1024B max payload size
100: 2048B max payload size
101: 4096B max payload size
Note: This field has no impact internally to Intel 5000P Chipset MCH and the
maximum payload size of the TLPs that appear on the PCI Express port is
governed by the PEXDEVCTRL.MPS for that port defined in Table 3.8.11.4
4
RO
0
ENRORD: Enable Relaxed Ordering
No relaxed ordering is supported by Intel 5000P Chipset MCH. Hardwired to 0h.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
265
Register Description
Device:
Function:
Offset:
8
0
74h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
URREN: Unsupported Request Reporting Enable
3
2
RO
0
For an integrated DMA Engine device, this bit is irrelevant. Hardwired to 0h
RW
0
FERE: Fatal Error Reporting Enable:
This bit controls the reporting of fatal errors internal to the DMA Engine device
0: Fatal error reporting is disabled
1: Fatal error reporting is enabled
1
0
RW
RW
0
0
NFERE: Non-Fatal Error Reporting Enable
This bit controls the reporting of non fatal errors internal to the DMA Engine device
in the PCI Express port.
0: Non Fatal error reporting is disabled
1: Non Fatal error reporting is enabled
This has no effect on the Intel 5000P Chipset MCH DMA Engine device as it does not
report any non-fatal errors.
CERE: Correctable Error Reporting Enable
This bit controls the reporting of correctable errors internal to the DMA Engine
device in the PCI Express port.
0: Correctable error reporting is disabled
1: Correctable Fatal error reporting is enabled
This has no effect on the Intel 5000P Chipset MCH DMA Engine device as it does not
report any correctable errors.
3.10.19 PEXDEVSTS - PCI Express Device Status Register
Device:
Function:
Offset:
8
0
76h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:6
5
RV
RO
0h
0
Reserved
TP: Transactions Pending
This bit indicates that the DMA Engine device has issued non-posted PCI Express
transactions which have not yet completed.
Note the Intel 5000P Chipset MCH DMA Engine device does not issue any NP
transactions and hence this is hardwired to zero.
4
3
RO
RO
0
0
APD: AUX Power Detected
The DMA Engine device does not support AUX power. Hardwired to 0h.
URD: Unsupported Request Detected
This does not apply to DMA Engine in Intel 5000 Series Chipset as there are no
messages for the DMA engine. Hardwired to 0h
2
RWC
0
FED: Fatal Error Detected
This bit gets set if a fatal uncorrectable error is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the Device Control
register (See FERE in Section 3.10.18)
1: Fatal errors detected
0: No Fatal errors detected
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
8
Function:
Offset:
0
76h
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
1
0
RWC
0
NFED: Non-Fatal Error Detected
This bit gets set if a non-fatal uncorrectable error is detected.
Errors are logged in this register regardless of whether error reporting is enabled or
not in the Device Control register. (See NFERE in Section 3.10.18)
1: Non Fatal errors detected
0: No non-Fatal Errors detected
RWC
0
CED: Correctable Error Detected
This bit gets set if a correctable error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register. (See CERE in Section 3.10.18)
1: correctable errors detected
0: No correctable errors detected
3.11
PCI Express Intel IBIST Registers
3.11.1
DIOIBSTR: PCI Express Intel IBIST Global Start/Status
Register
This register contains the global start for all the ports in the Intel 5000P Chipset MCH
component simultaneously. One start bit is placed in the register for each port. Intel
IBIST will start at approximately the same time on all ports written to with a 1 in the
same write access.
Device:
Function:
Offset:
0
0
398h
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7
6
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
RV
0
0
0
0
0
0
0
0
START7: Writing a 1 starts Intel IBIST on port 7.
START6: Writing a 1 starts Intel IBIST on port 6.
START5: Writing a 1 starts Intel IBIST on port 5.
START4: Writing a 1 starts Intel IBIST on port 4.
START3: Writing a 1 starts Intel IBIST on port 3.
START2: Writing a 1 starts Intel IBIST on port 2.
Reserved
RW
START0: Writing a 1 starts Intel IBIST on port 0.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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Register Description
3.11.2
DIO0IBSTAT: PCI Express Intel IBIST Completion Status
Register
Device:
0
Function: 0
Offset:
394h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
IBSTAT7: Intel IBIST Status port 7
0: Intel IBIST either has not started the first time or it is still running.
1: Intel IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
7
RO
0
IBSTAT6: Intel IBIST Status port 6
0: Intel IBIST either has not started the first time or it is still running.
1: Intel IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
6
5
4
3
RO
RO
RO
RO
0
0
0
0
IBSTAT5: Intel IBIST Status port 5
0: Intel IBIST either has not started the first time or it is still running.
1: Intel IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
IBSTAT4: Intel IBIST Status port 4
0: Intel IBIST either has not started the first time or it is still running.
1: Intel IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
IBSTAT3: Intel IBIST Status port 3
0: Intel IBIST either has not started the first time or it is still running.
1: Intel IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
IBSTAT2: Intel IBIST Status port 2
0: Intel IBIST either has not started the first time or it is still running.
1: Intel IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
2
1
0
RO
RV
RO
0
0
0
Reserved.
IBSTAT0: Intel IBIST Status port 0
0: Intel IBIST either has not started the first time or it is still running.
1: Intel IBIST is done. This bit will be cleared by hardware when the start bit is
asserted.
3.11.3
DIO0IBERR: PCI Express Intel IBIST Error Register
Device:
0
Function: 0
Offset:
Bit
395h
Attr
Default
Description
P7ERRDET: Error Detected on port 7
7
6
5
4
3
2
1
0
RWC
RWC
RWC
RWC
RWC
RWC
RV
0
0
0
0
0
0
0
0
P6ERRDET: Error Detected on port 6
P5ERRDET: Error detected on port 5
P4ERRDET: Error detected on port 4
P3ERRDET: Error Detected on port 3
P2ERRDET: Error Detected on port 2
Reserved
RWC
P0ERRDET: Error detected on port 0
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.11.4
PEX[7:2,0]IBCTL: PEX Intel IBIST Control Register
This register contains the control bits and status information necessary to operate the
Fixed and Open modes of the Intel IBIST logic. The default settings allow the CMM logic
to operate with link width of a PEX port. Only valid PCI Express control characters/
symbols are allowed for Intel IBIST testing.
Device:
3-2, 0
Function: 0
Offset:
380h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
380h
Version:
Intel 5000Z Chipset
Device:
7-4
Function: 0
Offset:
380h
Version: Intel 5000P Chipset
Bit
Attr
Default
Description
SYMTYPSEL3: Symbol[3] Type Select
31
RW
0
1: selects Symbol [3] as a control character
0: selects Symbol [3] to a data character
SYMTYPSEL2: Symbol[2] Type Select
1: selects Symbol [2] as a control character
0: selects Symbol [2] to a data character
30
29
RW
RW
1
0
SYMTYPSEL1: Symbol[1] Type Select
1: selects Symbol [1] as a control character
0: selects Symbol [1] to a data character
SYMTYPSEL0: Symbol[0] Type Select
1: selects Symbol [0] as a control character
0: selects Symbol [0] to a data character
28
RW
RV
1
0
27:23
Reserved
ERRVAL: Error Value
This is the raw 9-bit error value captured on the lane that asserted the Error
Detected bit (ERRDET) or the Global Error status bit if this register is
implemented. The value must be extracted in the datapath before the 10b/8b
decoder in order to examine its contents for debugging potential link errors.
22:14
13:9
RO
0h
ERRLNNUM: Error Lane Number
This field indicates which lane reported the error that was detected when
ERRDET was asserted.
Note: When the number of lanes reporting exceeds 32, this field will show an
aliased error lane number and cannot be used to indicate the errant lane.
Larger lane indications will require an extended register to display accurate
information.
RO
0h
ERRDET: Error Detected
A mis-compare between the transmitted symbol and the symbol received on
link indicates an error condition occurred. Refer to Error Value, Error Symbol
Pointer and Error Symbol Type bit fields for further information about fault
locations. This bit is cleared by writing a logic ‘1’ and it remains asserted
through reset (sticky).
0: No error detected
1: Error Detected
8
RWCST
0
Note: The error signal that causes this bit to be set should be made available
externally to the Intel IBIST logic. It is implementation specific as to how this
is accomplished. The purpose is for symbol (bit) error rate testing. It is
assumed that this signal is either sent to a performance counter or an
external pin for signal assertion accumulation. There is not any error counting
resources available in this spec.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
269
Register Description
Device:
3-2, 0
Function: 0
Offset:
380h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
380h
Version:
Intel 5000Z Chipset
Device:
7-4
Function: 0
Offset:
380h
Version: Intel 5000P Chipset
Bit
Attr
Default
Description
SUPSKP: Suppress Skips
0: Skips are still inserted in the Intel IBIST data stream during Intel IBIST test
operations.
7
RW
0
1: Skip insertion is suppressed
DSYMINJLNUM: Delay Symbol Injection Lane Number
This selects the Lane number to inject the delay symbol pattern. All 8 values
could be valid depending on the setting of the IBEXTCTL.LNMODUEN bit field.
This is true regardless of whether this Intel IBIST engine is instantiated for a
x4 or a x8 port.
6:4
RW
000
AUTOSEQEN: Automatic Sequencing Enable of Delay Symbol
0: Disable delay symbol auto-sequence. Intel IBIST does not automatically
sequence the delay symbol across the width of the link.
1: Enable delay symbol auto-sequencing.
3
2
RW
RV
1
0
Reserved
INITDISP: Initial Disparity
This bit sets the disparity of the first Intel IBIST data pattern symbol. The
default is negative meaning that the first symbol transmitted by Tx will have a
negative disparity regardless of what the running disparity is. This allows a
deterministic pattern set to be transmitted on the link for every Intel IBIST
run. If Intel IBIST causes a discontinuous disparity error in the receiver this
error can be ignored in the reporting register. It will not affect the operation of
the Intel IBIST since it is outside of its domain. Higher levels of software
management must be aware that side effects from running Intel IBIST could
cause other errors and should they be ignored.
1
0
RW
0
0
0: Disparity starts as negative
1: Disparity starts as positive
IBSTR: Intel IBIST Start
This bit is OR’ed with the global start bit.
0: Stop Intel IBIST
RW
1: Start Intel IBIST
3.11.5
PEX[7:2,0]IBSYMBUF: PEX Intel IBIST Symbol Buffer
This register contains the character symbols that are transmitted on the link. Only valid
PCI Express control characters/symbols are allowed for Intel IBIST testing.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
Device:
3-2, 0
Function: 0
Offset:
384h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
384h
Version:
Intel 5000Z Chipset
Device:
7-4
Function: 0
Offset:
384h
Version: Intel 5000P Chipset
Bit
Attr
Default
Description
CHARSYM3: Character Symbol [3]
31:24
RW
4Ah
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for D10.2.
CHARSYM2: Character Symbol [2]
23:16
15:8
7:0
RW
RW
RW
BCh
B5h
BCh
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for K28.5.
CHARSYM1: Character Symbol [1]
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for D21.5.
CHARSYM0: Character Symbol [0]
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for K28.5.
3.11.6
PEX[7:2,0]IBEXTCTL: PEX Intel IBIST Extended Control
Register
This register extends the functionality of the Intel IBIST with pattern loop counting,
skip character injection, and symbol management. A bit is provided to ignore the count
value and loop continuously for port testing. Only valid PCI Express control characters/
symbols are allowed for Intel IBIST testing.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
271
Register Description
Device:
3-2, 0
Function: 0
Offset:
388h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
388h
Version:
Intel 5000Z Chipset
Device:
7-4
Function: 0
Offset:
388h
Version: Intel 5000P Chipset
Bit
Attr
Default
Description
31:29
RV
0h
Reserved
FRCENT: Forced Entry:
Setting this bit forces entry into master Intel IBIST loopback state when the Start
bit is asserted. No TS1s are sent when enabled. The Intel IBIST is granted direct
control of the transmitted path regardless of which state the LTSSM is in. The Intel
IBIST state machine sends the contents of the pattern buffer until the stop
condition is reached. The receiver isn’t expected to perform any error checking
and must ignore input symbols.
28
RW
0
NOTE: For Intel 5000P Chipset MCH the user must reset the component to stop
this function. The
receiver sets the done condition and the receiver is disabled with this function.
0: Execute normally
1: Force to Loopback state as a ‘master’ condition.
LNMODUEN: Lane Modulo Enable for Delay Symbol Injection
00: No symbols sent on lanes
27:26
RW
01
01: Delay symbols sent on modulo 4 group of lanes across the width of the port.
10: Delay symbols sent on modulo 8 group of lanes across the width of the port.
11: Reserved
DISSTOP: Disable Stop on Error
0: Enable Stop on Error
25
24
RW
RW
0
0
1: Disable Stop on Error. The Intel IBIST engine continues to run in its current
mode in the presence of an error. If an error occurs overwrite the error status
collected from a previous error event.
LPCON: Loop Continuously
0: Use loop counter. Test terminates at the end of the global count.
1: Loop symbols continuously.
SKPCNTINT: Skip Count Interval
This register indicates when a skip order sequence is sent on the transmitter. Upon
reaching this count the transmitter sends an SOS then clears the skip counter and
counting resumes until the next match on the skip count interval.
000: No Skip Ordered Sets are sent on TX.
nnn: The number of 8 symbol sets transmitted before a Skip Ordered Set is sent.
23:12
RW
RW
000h
07Fh
LOOPCNTLIM: Loop Count Limit
This register indicates the number of times the data symbol buffer is looped as a
set of 8 symbol times. If LOOPCON is set then this count limit is ignored.
00: No symbols are sent from symbol buffer unless LOOPCON is set. If LOOPCON
is cleared and this value is 000h then the transmitter immediately exits out of
loopback state by sending EIOS without sending a pattern buffer payload.
11:0
01-FFF: 1 to 4095 sets of symbols from the symbol buffer. One set of symbols is
defined as either two copies of the contents of the buffer or the modified delayed
symbol set.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.11.7
PEX[7:2,0]IBDLYSYM: PEX Intel IBIST Delay Symbol
This register stores the value of the delay symbol used in lane inversion cross-talk
testing. Only valid PCI Express control characters/symbols are allowed for Intel IBIST
testing.
Device:
3-2, 0
Function: 0
Offset:
38Ch
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
38Ch
Version:
Intel 5000Z Chipset
Device:
7-4
Function: 0
Offset:
38Ch
Version: Intel 5000P Chipset
Bit
Attr
Default
Description
15:9
RV
0h
Reserved
DLYSYM: Delay Symbol
This is the 9-bit delay symbol value used (default is K28.5).
8:0
RW
1BCh
3.11.8
PEX[7:2,0]IBLOOPCNT: PEX Intel IBIST Loop Counter
This register stores the current value of the loop counter.
Device:
Function:
Offset:
3-2, 0
0
38Eh
Version:
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
38Eh
Version:
Intel 5000Z Chipset
Device:
Function:
Offset:
7-4
0
38Eh
Version:
Intel 5000P Chipset
Bit
Attr
Default
Description
15:12
RV
0h
Reserved
LOOPCNTVAL: Loop Count Value
Once the Intel IBIST is engaged, loop counts are incremented when a set of 8
symbols has been received. If an error occurs, this register reflects the loop count
value of the errant Rx lane. If there is no error then this register reads 00h.
Note: Since each receiver is not deskewed with respect to the Intel IBIST pattern
generator we cannot have a coherent loop count value with N number of receivers
and only one loop counter. It would require additional logic to select which
receiver indicates the count.
11:0
RO
000h
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
273
Register Description
3.11.9
PEX[7:2,0]IBLNS[3:0]: PEX Intel IBIST Lane Status
This register contains the control bits and status information necessary to perate the
Fixed and Open modes of the Intel IBIST logic. The default settings allow the CMM logic
to operate with link width of a PEX port. Only valid PCI Express control characters/
symbols are allowed for Intel IBIST testing.
Device:
3-2, 0
Function: 0
Offset:
393h, 392h, 391h, 390h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
4-5
0
393h, 392h, 391h, 390h
Intel 5000Z Chipset
Version:
Device:
4-7
Function: 0
Offset:
393h, 392h, 391h, 390h
Version: Intel 5000P Chipset
Bit
Attr
Default
Description
ERRPTRTYP: Error Symbol Pointer Type
This bit indicates whether or not the errant symbol pointer was a delay symbol
set. If an Intel IBIST engine is implemented with the MISR compare method
then this field is reserved.
7
RO
0
0: Errant symbol pointer was a DATA symbol set
1: Errant symbol pointer was a DELAY symbol set
ERRPTR: Error Symbol Pointer
This value indicates which symbol of the 8 possible symbols sent on the lane, as
a set of characters, failed. The value corresponds to position of the set of 8
symbols. If an Intel IBIST engine is implemented with the MISR compare
method then this field is reserved.
6:4
RO
0h
0
IBLOOPSTAT: Intel IBIST Loopback State Status:
This bit is set when the Rx received a TS1 with the loopback bit set. Write a logic
‘1’ to clear.
3
RWC
0: Intel IBIST did not receive a TS1 with loopback bit set.
1: Intel IBIST received a TS1 with loopback bit set.
2
1
RV
0
0
Reserved.
ERRLNSTAT: Error Lane Status
Error assertion for this lane. Writing a logic ‘1’ will clear this bit. This bit is sticky.
0: No error on this lane
RWCST
1: Error has occurred on this lane
LNSTREN: Lane Start Enable
When the lane is disabled, no electrical transmissions may occur on the Tx
driver and the receiver’s (Rx) Intel IBIST error reporting is suppressed. This
allows the pattern generator and receiver checking logic to function normally if
required for design simplicity. But it forces a quite Tx lane for adjacent lane
testing.
0
RW
1
0: This lane is disabled from Intel IBIST testing, no Tx transmissions and Rx
error reporting is suppressed.
1: Lane enabled. Allows the port start bit to begin Intel IBIST symbol operations
on this lane.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Register Description
3.11.10 DIO[1:0]SQUELCH_CNT: PCIe Cluster Squelch Count
Device:
4, 0
Function: 0
Offset:
Bit
396h
Attr
Default
Description
15:12
11
RV
1h
1h
Reserved
RWST
Dis_Rx_L1L0s_idle: Disable automatic shutoff of receivers during L1.Idle/
L0s.Idle power states
1: Disable automatic shut off of receivers during L1 or L0s idle power state entry.
(default).
0: Enables Rx shut off. This bit when clear forces the hardware to shut off the
Receiver side in BNB during the L0s/L1 power states.
Note: This bit is functional in MCH steppings B3 and newer. Refer to erratum 19
(501621).
DIS_LANE_LANE_DESKEW: Disable Lane to Lane Deskew
1: Lane to lane deskew is disabled. Should be set before Intel IBIST is started and
cleared after Intel IBIST is stopped
0: Normal link operation. i.e Lane to lane deskew is enabled (default)
10
RWST
RV
0h
9:0
164h
Reserved
§
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
275
Register Description
®
276
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
System Address Map
4 System Address Map
The Intel 5000X chipset MCH supports 36 bits of memory address space. Internally
Intel 5000P Chipset carries 40 bits of address into various memory controller
components. The processors designed for Intel 5000P Chipset, support only 36 bits of
memory addressing and 16 bits of addressable I/O space. However internally the MCH
supports 40 bits and several of the MCH memory configuration registers require 40 bit
address programming.
There is a legacy (compatibility) memory address space under the 1-MB region that is
divided into regions that can be individually controlled with programmable attributes
(for example, disable, read/write, write only, or read only). Attribute programming is
described in Chapter 3. The Intel 5000X chipset MCH supports several fixed address
ranges in addition to the compatibility range. These are:
• Compatibility area below 1MB
• Interrupt delivery region
• System region in 32MB just below 4GB
There are several relocatable regions such as the memory mapped I/O region.These
regions are controlled by various programmable registers covered in Chapter 3.
This chapter focuses on how the memory space is partitioned and the uses of the
separate memory regions.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the ESI/PCI Express/PCI interfaces. VGA address ranges are mapped to PCI
Express address space as well. In the absence of more specific references, cycle
descriptions referencing PCI should be interpreted as the ESI/PCI interface.
The Intel 5000X chipset MCH memory map includes a number of programmable
ranges. All of these ranges must be unique and non-overlapping as shown in
Figure 4-1. There are no hardware interlocks to prevent problems in the case of
overlapping ranges. Accesses to overlapped ranges may produce indeterminate results.
For example, setting HECBASE to all zeros will overlap the MMCFG region and the
compatibility region resulting in unpredictable results.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
277
System Address Map
Figure 4-1. System Memory Address Map
64 GB
PCI-E/PCI-X/PCI
Memory Address
Range
Graphics AGP Address
Graphics (AGP)
Aperture
Memory
Range
Top of the Physical
DRAM Memory
Independently Programmable Non-
Overlapping Memory Windows
Main Memory
Address Range
0
4.1
System Memory Address Ranges
The Intel 5000X chipset MCH platform supports 36 bits (64 GB) of physical memory Or
maximum of 40-bit system address with up to 64 GB or physical memory support.
Other address spaces supported by the Intel 5000P Chipset are:
• 36-bit local address supported over the FB-DIMM channels for physical memory
space.
• 32 and 64 bit address bit formats supported for PCI Express interfaces.
The chipset treats accesses to various address ranges in different ways. There are fixed
ranges like the compatibility region below 1 MB, and variable ranges like the memory
mapped I/O range. The locations of these ranges in the memory map are illustrated in
Figure 4-2.
4.1.1
32/64-bit addressing
For inbound and outbound writes and reads, the Intel 5000P chipset MCH supports
64-bit address format. If an outbound transaction’s address is a 32-bit address, the
Intel 5000P Chipset MCH will issue the transaction with a 32-bit addressing format on
PCI Express. Only when the address requires more than 32 bits will the Intel 5000P
Chipset MCH initiate transactions with 64-bit address format. It is the responsibility of
the software to ensure that the relevant bits are programmed for 64-bits based on the
OS limits. (for example, 40-bits for Intel 5000P Chipset MCH).
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
System Address Map
Figure 4-2. Detailed Memory System Address Map
F FFFF FFFFh
High
MMIO
64 GB
System
Memory
Physical maximum
High Extended
1 0000 0000 h
memory is ~64 GB
Memory
FFFF FFFFh
FFFF FFFFh
FFC 0 0000 h
Firmware
16 MB
4 MB
FF 00 0000 h
FEC 0 0000 h
4 GB
Interrupt / SMM
Chipset
CB_ BAR
1 MB
System
Memory
12 MB
FE 70 0000 h
AMB _ MMIO
Low/Medium
Extended
Memory
AMBASE
FE 00 7 FFFh
FE 00 0000 h
Low MMIO
Relocation
MMCFG
Relocation
256 MB
HECBASE
TOLM
0010 0000 h
1 MB
ESMMTOP
Extended
SMRAM Space
DOS Compatibility
ESMMTOP
TSEG _SZ
-
1 MB
000 F FFFFh
Area
Upper BIOS
0
Area (64 KB)
000 F 0000 Fh
000 E FFFFh
960 KB
896 KB
Lower BIOS
Area (64 KB;
16 KB x 4)
000 E 0000 h
000 D FFFFh
Expansion
Card BIOS C
and D
Segments
( 128 KB)
000 C 0000 h
000 B FFFFh
768 KB
640 KB
VGA Memory
Std. PCI/ISA
Video Memory
(128 KB)
000 A 0000 h
.
0009 FFFFh
1. Physical maximum memory is the
maximum address validated by
Intel® 5000 P: 64 GB - 256 MB
DOS Region
( 640 KB)
0000 0000 h
0
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
279
System Address Map
4.2
Compatibility Area
This is the range from 0 - 1 MB (0 0000h to F FFFFh). Requests to the compatibility
area are directed to main memory, the Compatibility Bus (ESI), or the VGA device. Any
physical DRAM addresses that would be addressed by requests in this region that are
mapped to the Compatibility Bus (ESI) and are not recovered.
DRAM that has a physical address between 0-1 MB must not be recovered or relocated
or reflected. This range must always be available to the OS as DRAM, even if at times
addresses in this range are sent to the compatibility bus or VGA or other non-DRAM
areas.
Addresses below 1 M that are mapped to memory are accessible by the processors and
by any I/O bus. The address range below 1 M is divided into five address regions. These
regions are:
• 0 - 640 KB MS-DOS Area.
• 640 – 768 KB Video Buffer Area.
• 768 – 896 KB in 16-KB sections (total of eight sections) - Expansion Card BIOS,
Segments C and D.
• 896 - 960 KB in 16-KB sections (total of four sections) - Lower Extended System
BIOS, Segment E.
• 960 KB–1 MB memory (BIOS Area) - Upper System BIOS, Segment F.
There are fifteen memory segments in the compatibility area. Thirteen of the memory
ranges can be enabled or disabled independently for both read and write cycles.
Table 4-1.
Memory Segments and Their Attributes
Memory Segments
000000h–09FFFFh
Attributes
Comments
Fixed: mapped to main DRAM
0 to 640 KB – DOS Region
0A0000h–0BFFFFh
Mapped to ESI, x16 graphics port
Video Buffer (physical DRAM
configurable as SMM space)
0C0000h–0C3FFFh
0C4000h–0C7FFFh
0C8000h–0CBFFFh
0CC000h–0CFFFFh
0D0000h–0D3FFFh
0D4000h–0D7FFFh
0D8000h–0DBFFFh
0DC000h–0DFFFFh
0E0000h–0E3FFFh
0E4000h–0E7FFFh
0E8000h–0EBFFFh
0EC000h–0EFFFFh
0F0000h–0FFFFFh
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
WE RE
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
BIOS Extension
BIOS Extension
BIOS Extension
BIOS Extension
BIOS Area
4.2.1
MS-DOS Area (0 0000h–9 FFFFh)
The MS-DOS area is 640 KB in size and is mapped to main memory controlled by the
MCH.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
System Address Map
4.2.2
Legacy VGA Ranges (A 0000h–B FFFFh)
The 128 KB Video Graphics Adapter Memory range (A 0000h to B FFFFh) can be
mapped to the VGA device which may be on any PCI Express or ESI port, or optionally
it can be mapped to main memory (it must be mapped to SMM space). Mapping of this
region is controlled by the VGA steering bits. At power on this space is mapped to the
ESI port.
Priority for VGA mapping is constant in that the MCH consistently decodes internally
mapped devices first. The MCH positively decodes internally mapped devices. This
region can be redirected by BIOS to point to any bus which has a VGA card. If the
VGAEN bit is set in one of the Intel 5000P Chipset MCH.BCTRL configuration registers
associated with the PCI Express port, then transactions in this space are sent to that
PCI Express port.
The VGAEN bit can only be set in one and only one of the Intel 5000P Chipset
MCH.BCTRL registers. If any VGAEN bits are set, all the ISAEN bits must be set. If the
VGAEN bit of a PCI Express port x in the Intel 5000P Chipset MCH is set and
BCTRL[x].VGA16bdecode is set to zero, then ISAEN bits of all peer PCI Express ports
with valid I/O range (PCICMD.IOAE = 1, IOLIMIT >= IOBASE) in the MCH must be set
by software. Otherwise, it is a programming error due to the resulting routing conflict.
If the VGAEN bit of a PCI Express port x in the MCH is set, and
BCTRL[x].VGA16bdecode is set to one, and if there is another PCI Express port y (x !=
y) with valid I/O range including the lowest 4K I/O addresses (PCICMD[y].IOAE = 1,
IOLIMIT[y] >= IOBASE[y] = 0000h), BCTRL[y].ISAEN bit must be set to one by
software. Otherwise, it is a programming error.
This region is non-cacheable.
Compatible SMRAM Address Range (A 0000h–B FFFFh)
The legacy VGA range may also be used for mapping SMM space. The SMM range (128
KB) can overlay the VGA range in the A and B segments. If the SMM range overlaps an
enabled VGA range then the state of the SMMEM# signal determines where accesses to
the SMM Range are directed. SMMEM# is a special FSB message bit that uses
multiplexed address bit FSBxA[7]#. SMMEM# is valid during the second half of the FSB
request phase clock. (the clock in which FSBxADS# is driven asserted).
SMMEM# asserted directs the accesses to the memory and SMMEM# deasserted
directs the access to the PCI Express bus where VGA has been mapped.
When compatible SMM space is enabled, SMM-mode processor accesses to this range
are routed to physical system DRAM at this address. Non-SMM-mode processor
accesses to this range are considered to be to the video buffer area as described above.
Graphics port and ESI originated cycles to enabled SMM space are not allowed and are
considered to be to the Video Buffer Area.
Monochrome Adapter (MDA) Range (B 0000h–B 7FFFh)
The Intel 5000X chipset does not support this range.
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4.2.3
Expansion Card BIOS Area (C 0000h–D FFFFh)
This 128-KB ISA Expansion Card BIOS covers segments C and D. This region is further
divided into eight, 16-KB segments. Each segment can be assigned one of four read/
write states: read only, write only, read/write, or disabled. Typically, these blocks are
mapped through the MCH and are subtractively decoded to ISA space. Memory that is
disabled is not remapped.
Read and write transactions may be directed to different destinations with in the range
C 0000h to D FFFFh. Historically, these blocks were used to shadow ISA device BIOS
code. For the Intel 5000P Chipset, these regions are used to provide address space to
PCI devices requiring memory space below 1 MB. The range is divided into 8 sub-
ranges. These ranges are defined by Intel 5000P Chipset MCH.PAM registers. There is a
PAM register for each sub-range that defines the routing of reads and writes.
Table 4-2.
PAM Settings
PAM [5:4]/1:0] Write Destination
Read Destination
Result
00
01
10
11
ESI
ESI
Mapped to ESI Port
Memory Write Protect
In-Line Shadowed
ESI
Main Memory
ESI
Main Memory
Main Memory
Main Memory
Mapped to main memory
The power-on default for these segments is mapped read/write to the ESI port (Intel®
631xESB/632xESB I/O Controller Hub). Software should not set cacheable memory
attributes for any of these ranges, unless both reads and writes are mapped to main
memory. Chipset functionality is not guaranteed if this region is cached in any mode
other than both reads and writes being mapped to main memory.
For locks to this region, the Intel 5000P Chipset will complete, but does not guarantee
the atomicity of locked access to this range when writes and reads are mapped to
separate destinations. If inbound accesses are expected, the C and D segments MUST
be programmed to send accesses to DRAM.
4.2.4
Lower System BIOS Area (E 0000h–E FFFFh)
This 64-KB area, from E 0000h to E FFFFh, is divided into four, 16-KB segments. Each
segment can be assigned independent read and write attributes through the Intel
5000P Chipset MCH.PAM registers. This area can be mapped either the ESI port (Intel
631xESB/632xESB I/O Controller Hub) or to main memory. Historically this area was
used for BIOS ROM. Memory segments that are disabled are not remapped elsewhere.
The power-on default for these segments is to map them to the ESI port (Intel
631xESB/632xESB I/O Controller Hub). Software should not set cacheable memory
attributes for any of these ranges unless both read and write transactions are mapped
to main memory. Chipset functionality is not guaranteed if this region is cached.
For locks to this region, the Intel 5000P Chipset will complete them, but does not
guarantee the atomicity of locked access to this range when writes and reads are
mapped to separate destinations. If inbound transactions are expected, the E segment
MUST be programmed to send these transactions to DRAM.
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4.2.5
Upper System BIOS Area (F 0000h–F FFFFh)
This area is a single, 64-KB segment, from E 0000h - F FFFFh. This segment can be
assigned read and write attributes through the Intel 5000P Chipset MCH.PAM registers.
The power-on default is set to read/write disabled with transactions forwarded to the
ESI port (Intel 631xESB/632xESB I/O Controller Hub). By manipulating the read/write
attributes, the MCH can “shadow” BIOS into the main system memory. When disabled,
this segment is not remapped.
For locks to this region, the Intel 5000P Chipset will complete them, but does not
guarantee the atomicity of locked access to this range when writes and reads are
mapped to separate destinations. If inbound transactions are expected, the F segment
MUST be programmed to send these transactions to DRAM.
4.3
System Memory Area
The low/medium memory regions range from 1MB to 4 GB. It consists of sub-regions
for Firmware, Processor memory mapped functions, and Intel 5000P Chipset specific
registers.
The Extended Memory Area covers from 10 0000h (1 MB) to FFFF FFFFh (4 GB-1)
address range and it is divided into the following regions:
• Main System Memory from 1 MB to the Top of Memory; 4-GB system memory.
• PCI Memory space from the Top of Memory to 4 GB with two specific ranges:
• APIC Configuration Space from FEC0 0000h (4 GB–20 MB) to FECF FFFFh and FEE0
0000h to FEEF FFFFh
• High BIOS area is from 16MB to 4 GB - 1
Main System DRAM Address Range (0010 0000h to Top of System Memory)
The address range from 1 MB to the top of system memory is mapped to system
memory address range controlled by the MCH. The Top of Main Memory (TOLM) is
limited to 4-GB DRAM. All accesses to addresses within this range will be forwarded by
the MCH to the system memory.
The MCH provides a maximum system memory address decode space of 4 GB. The
MCH does not remap APIC memory space. The MCH does not limit system memory
address space in hardware.
4.3.1
4.3.2
System Memory
See Section 4.3.9.
15 MB - 16 MB Window (ISA Hole)
The Intel 5000P Chipset does not support the legacy ISA hole between addresses F0
0000h - FF FFFFh. All transactions to this address range are treated as system memory.
4.3.3
Extended SMRAM Space (TSEG)
SMM space allows system management software to partition a region in main memory
to be used by system management software. This region is protected for access by
software other than system management software. When the SMM range is enabled,
memory in this range is not exposed to the Operating System. The Intel 5000P Chipset
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allows accesses to this range only when the SMMEM# signal on the processor bus is
asserted with the request. If SMMEM# is deasserted, accesses to the SMM Range are
master aborted. If SMMEM# is asserted the access is routed to main memory. Intel
5000P Chipset uses the SMM enable and range registers to determine where to route
the access.
Extended SMRAM Space is different than the SMM space defined with in the VGA
address space, A 0000h - B FFFFh. This region is controlled by the Intel 5000P Chipset
registers Intel 5000P Chipset MCH.EXSMRC.TSEG_SZ and Intel 5000P Chipset
MCH.EXSMRTOP.ESMMTOP. The TSEG SMM space starts at ESMMTOP - TSEG_SZ and
ends at ESMMTOP. This region may be 512 KB, 1 MB, 2 MB, or 4 MB in size, depending
on the TSEG_SZ field. ESMMTOP is relocatable to accommodate software that wishes to
configure the TSEG SMM space before MMIO space is known. The ESMMTOP will default
to the same default value as Top Of Low Memory (TOLM), defined by the TOLM register.
Intel 5000P Chipset will not support a locked access that crosses an SMM boundary.
Firmware should not create data structures that span this boundary. SMM main
memory is protected from Inbound accesses.
In order to make cacheable SMM possible, the chipset must accept EWB’s and must
absorb IWB data regardless of the condition of the SMMEM# pin. The Intel 5000X
chipset MCH will not set the error bit EXSMRAMC.E_SMERR in this case. Because of
this, care must be used when attempting to cache SMM space. The chipset/platform
cannot protect against processors who attempt to illegally access SMM space that is
modified in another processor’s cache. Any software that creates such a condition (for
example, by corrupting the page table) will jeopardize the protective properties of
SMM.
4.3.4
Memory Mapped Configuration (MMCFG) Region
There is one relocatable memory mapped configuration region in the Intel 5000X
chipset MCH. The processor bus address defines the particular configuration register to
be accessed. This configuration mechanism is atomic.
The memory mapped configuration region is compatible with the PCI Express enhanced
configuration mechanism. The MMCFG region is a 256 MB window that maps to PCI
Express registers on both the Intel 5000P Chipset and the south bridge.
The location of this MMCFG window is defined by the Intel 5000P Chipset
MCH.HECBASE register. The HECBASE register could also be accessed through a fixed
location. The default value of Intel 5000P Chipset MCH.HECBASE maps this region such
that there will be no wasted memory that is lost behind it. The default value for the PCI
Express registers is the same as the default value of TOLM. If this range is moved, the
following recommendations will enable reclaiming the memory that is lost to MMCFG
accesses.
1. MMCFG range is mapped to a legal location within the range between TOLM and
4GB. Since ranges must not overlap other legal ranges, it is safest to put this range
between TOLM and the lowest real MMIO range. (The current default is in these
ranges) OR
2. Put the region above 4GB Low/Medium Memory limit and not overlapping above
4 GB MMIO space.
BIOS/software must ensure there are no outstanding configuration accesses or
memory accesses to the old and new MMCFG range addresses when relocating this
range.
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Note:
An SMM program can address up to 4 GB of memory. SMM is similar to read-address
mode in that there are no privileges or address mapping. The Intel 5000P Chipset MCH
allows the relocation of HECBASE above 4 GB. However, SMM code cannot access
extended configuration space if HECBASE is relocated above 4 GB. This is a CPU
limitation. Page Size Extension (PSE) is supported in SMM but Page Address Extension
(PAE) support in SMM is currently not in Intel® Xeon® processors. Refer to the IA-32
Intel® Architecture Software Developer’s Manual, Vol. 3, Sect. 13.1.
For more information on the memory mapped configuration mechanism described here,
please see the Configuration Map and Access Chapter.
4.3.5
Low Memory Mapped I/O (MMIO)
This is the first of two Intel 5000X chipset memory mapped I/O ranges. The low
memory mapped I/O range is defined to be between Top Of Low Memory, (TOLM) and
FE00 0000h. This low MMIO region is further subdivided between the PCI Express and
ESI ports. The following table shows the registers used to define the MMIO ranges for
each PCI Express/ESI device. These registers are compatible with PCI Express and the
PCI to PCI bridge specifications. Note that all subranges must be contained in the low
memory mapped I/O range (between TOLM and FE00 0000). In other words, the lowest
base address must be above TOLM and the highest LIMIT register must be below
FE00_0000. Subranges must also not overlap each other.
Table 4-3.
Low Memory Mapped I/O1
I/O Port
MCH Base
MCH Limit
2
2
ESI
N/A
N/A
PEX2 Memory
MBASE2
PMBASE2
MBASE3
PMBASE3
MBASE4
PMBASE4
MBASE5
PMBASE5
MBASE6
PMBASE6
MBASE7
PMBASE7
MLIMIT2
PMLIMIT2
MLIMIT3
PMLIMIT3
MLIMIT4
PMLIMIT4
MLIMIT5
PMLIMIT5
MLIMIT6
PMLIMIT6
MLIMIT7
PMLIMIT7
PEX2 Prefetchable Memory
PEX3 Memory
PEX3 Prefetchable Memory
PEX4 Memory
PEX4 Prefetchable Memory
PEX5 Memory
PEX5 Prefetchable Memory
PEX6 Memory
PEX6 Prefetchable Memory
PEX7 Memory
PEX7 Prefetchable Memory
Notes:
1.
This table assumes Intel 5000P Chipset MCH.PMLU and Intel 5000P Chipset MCH.PMBU are 0’s. Otherwise,
the prefetchable memory space will be located in high MMIO space.
2.
MCH does not need base/limit for Intel 631xESB/632xESB I/O Controller Hub because subtractive decoding
will send the accesses to the Intel 631xESB/632xESB I/O Controller Hub. This is OK for software also, since
the Intel 631xESB/632xESB I/O Controller Hub is considered part of the same bus as the MCH.
The Intel 5000X chipset MCH will decode addresses in this range and route them to the
appropriate ESI or PCI Express port. If the address is in the low MMIO range, but is not
contained in any of the PCI Express base and limit ranges, it will be routed to the ESI.
If the Intel 5000P Chipset MCH.PMLU and Intel 5000P Chipset MCH.PMBU registers are
greater than 0, then the corresponding prefetchable region will be located in the high
MMIO range instead.
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4.3.6
Chipset Specific Range
The address range FE00 0000h - FEBF FFFFh region is reserved for chipset specific
functions.
FE00 0000h - FE00 8000h: This range (with size of 128 KB for four FB-DIMM
channels; 16 Advanced Memory Buffer (AMB) per channel, 2 KB per AMB), is used for
accessing AMB registers. These registers can only be accessed through memory
mapped register access mechanism as MMIO. Notice that they are not accessible
through CF8/CFC or MMCFG which are used for PCI/PCI Express configuration space
registers. This range could be relocated by programming AMBASE register. The
AMBASE register could also be accessed through a fixed location.
FE60 0000h - FE6F FFFFh: This range is used for fixed memory mapped Intel 5000P
Chipset registers. They are accessible only from the processor bus. These registers are
fixed since they are needed early during the boot process. The registers include:
• Four Scratch Pad Registers
• Four Sticky Scratch Pad Registers
• Four Boot flag registers
• HECBASE register for MMCFG
• AMBASE register for AMB memory mapped registers
These registers are described in the Intel 5000X chipset MCH Configuration Register,
Chapter 3, “Register Description.” The Intel 5000X chipset MCH will master abort
requests to the remainder of this region unless they map into one of the relocatable
regions such as MMCFG. The mechanism for this range can be the same as it is for the
memory mapped configuration accesses.
4.3.7
Interrupt/SMM Region
This 4 MB range is used for processor specific applications. This region lies between
FEC0 0000h and FEFF FFFFh and is split into four 1 MB segments.
Figure 4-3. Interrupt /SMM Region
F E F F F F F F h
R oute to Intel® 631 xE S B /
632 xE S B I / O C ontroller H ub
F E E F F F F F h
F E E 0 0000 h
F D E B F F F F h
F D E A 0000 h
F E D 3 F F F F h
F E D 2 0000 h
Interrupt
R oute to Intel® 631 xE S B /
632 xE S B I / O C ontroller H ub
H igh S M M
R oute to Intel® 631 xE S B /
632 xE S B I / O C ontroller H ub
R eserved
R oute to Intel® 631 xE S B /
632 xE S B I / O C ontroller H ub
( M M T = F E D 0 000 h - F E D 0
3 F F F h )
F E C 9 0000 h
F E C 8 F F F F h
I/ O A P IC
F E 00 0000
h
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This region is used to support various processor and system functions. These functions
include I/O APIC control range which is used to communicate with I/O APIC controllers
located on Intel 6700PXH 64 bit PCI Hub and Intel 631xESB/632xESB I/O Controller
Hub devices. The high SMM range is enabled under register control. Transactions
directed to this range are redirected to physical memory located in the compatible
(legacy) SMM space; 0A 0000h - 0B FFFFh. The interrupt range is used to deliver
interrupts. Memory read or write transactions from the processor are illegal.
4.3.7.1
I/O APIC Controller Range
This address range FEC0 0000h to FEC8 FFFF is used to communicate with the IOAPIC
controllers in the Intel® 6700PXH 64 bit PCI Hub or Intel 631xESB/632xESB I/O
Controller Hub devices.
The APIC ranges are hard coded. Reads and writes to each IOAPIC region should be
sent to the appropriate ESI or PCI Express port as indicated below.
Table 4-4.
I/O APIC Address Mapping
IOAPIC0 (ESI)
IOAPIC1 (PEX2)
IOAPIC2 (PEX3)
IOAPIC3 (PEX4)
IOAPIC4 (PEX5)
IOAPIC5 (PEX6)
IOAPIC6 (PEX7)
FEC0 0000h to FEC7 FFFFh
FEC8 0000h to FEC8 0FFFh
FEC8 1000h to FEC8 1FFFh
FEC8 2000h to FEC8 2FFFh
FEC8 3000h to FEC8 3FFFh
FEC8 4000h to FEC8 4FFFh
FEC8 5000h to FEC8 5FFFh
FEC0 6000h to FEC8 FFFFh
Reserved (Intel®
631xESB/632xESB
I/O Controller Hub
for master abort)
For Hot-Plug I/O APIC support, it is recommended that software use the standard MMIO
range to communicate with the Intel 6700PXH 64 bit PCI Hub. To accomplish this, the
Intel 6700PXH 64 bit PCI Hub.MBAR and/or Intel 6700PXH 64 bit PCI
Hub.XAPIC_BASE_ADDRESS_REG must be programmed within the PCI Express device
MMIO region.
Inbound accesses to this memory range should also be routed to the I/O APIC
controllers. This could happen if software configures MSI devices to send MSIs to an I/
O APIC controller.
4.3.7.2
High SMM Range
If high SMM space is enabled by EXSMRC.H_SMRAME, then requests to the address
range from FEDA 0000h to FEDB FFFFh will be aliased down to the physical address of
A 0000h to B FFFFh. The HIGHSMM space allows cacheable accesses to the compatible
(legacy) SMM space. In this range, the chipset will accept EWBs (BWLs) regardless of
the SMMEM# pin. Also, if there is an implicit write back (HITM with data), the chipset
will update memory with the new data (regardless of the SMMEM# pin). Note that if the
HIGHSMM space is enabled, the aliased SMM space of 0A 0000h - 0B FFFFh will be
disabled.
Note: In order to make cacheable SMM possible, the chipset must accept EWBs (BWLs)
and must absorb IWB (HITM) data regardless of the condition of the SMMEM# pin.
Because of this, care must be used when attempting to cache SMM space. The chipset/
platform cannot protect against processors who attempt to illegally access SMM space
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that is modified in another processor’s cache. Any software that creates such a
condition (for example, by corrupting the page table) will jeopardize the protective
properties of SMM.
4.3.7.3
Interrupt Range
Requests to the address range FEE0 0000h to FEEF FFFFh are used to deliver
interrupts. Memory reads or write transactions to this range are illegal from the
processor. The processor issues interrupt transactions to this range. Inbound interrupt
requests from the PCI Express devices in the form of memory writes are converted by
the MCH to processor bus interrupt requests.
4.3.7.4
4.3.7.5
Reserved Ranges
The Intel 5000X chipset MCH will master abort requests to the addresses in the
interrupt/reserved range (FEC0 0000h - FEFF FFFFh) which are not specified. This can
be done by sending the request to the compatibility bus (ESI) to be master aborted.
Firmware Range
The Intel 5000X chipset platform allocates 16 MB of firmware space from FF00 0000h
to FFFF FFFFh. Requests in this range are directed to the Compatibility Bus. The Intel
631xESB/632xESB I/O Controller Hub will route these to its FWH interface. This range
is accessible from any processor bus.
4.3.8
High Extended Memory
This is the range above 4 GB. The range from 4 GB to Intel 5000P Chipset
MCH.MIR[2].LIMIT is mapped to system memory. There can also be a memory mapped
I/O region that is located at the top of the address space. (Just below 1 TB).
4.3.8.1
4.3.8.2
System Memory
See Section 4.3.9
High MMIO
The high memory mapped I/O region is located above the top of memory as defined by
Intel 5000P Chipset MCH.MIR[2].LIMIT. These Intel 5000P Chipset MCH.PMBU and Intel
5000P Chipset MCH.PMLU registers in each PCI Express configuration device determine
whether there is memory mapped I/O space above the top of memory. If an access is
above MIR[2].LIMIT and it falls within the Intel 5000P Chipset MCH.PMBU+PMBASE and
Intel 5000P Chipset MCH.PMLU+PMLIMIT range, it should be routed to the appropriate
PCI Express port. For accesses above MIR[2].LIMIT (and above 4 GB) that are not in a
high MMIO region, they should be master aborted.
4.3.8.3
Extended Memory
The range of memory just below 4 GB from TOLM to 4 GB (Low MMIO, Chipset,
Interrupt/SMM/LT) does not map to memory. If the DRAM memory, behind the TOLM to
4 GB range, is not relocated, it will be unused.
The Intel 5000X chipset MCH uses MIR[2].LIMIT to indicate the top of usable memory.
Note that ESMMTOP cannot be greater than TOLM.
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4.3.9
Main Memory Region
4.3.9.1
Application of Coherency Protocol
The Intel 5000X chipset MCH applies the coherency protocol to all accesses to main
memory. Application of the coherency protocol includes snooping the other processor
bus.
Two exceptions to this rule are the Expansion Card BIOS area, 0C 0000h - 0F FFFFh
and the legacy SMM, 0A 0000h - 0B FFFFh, range. The Expansion Card BIOS area 0C
0000h - 0F FFFFh may not necessarily route both reads and writes to memory, the
legacy SMM range, 0A 0000h - 0B FFFFh, may target non-memory when not in SMM
mode. The coherency protocol is not applied to these two exceptions.
4.3.9.2
Routing Memory Requests
When a request appears on the processor bus, ESI port, or PCI Express link, and it
does not fall in any of the previously mentioned regions, it is compared against the
MIR.LIMIT registers in the MCH.
The Intel 5000P Chipset MCH.MIR.LIMIT registers will decode an access into a specific
interleaving range. Within the interleaving range, the Intel 5000P Chipset
MCH.MIR.LIMIT register indicates which FB-DIMM memory branch the address is
associated with. In the event that a mirroring event is occurring, memory writes are
associated with both FB-DIMM branches.
4.4
Memory Address Disposition
The following section presents a summary of address dispositions for the Intel 5000X
chipset MCH.
4.4.1
Registers Used for Address Routing
Table 4-5 is a summary of the registers used to control memory address disposition.
These registers are described in detail in Section 3.
Table 4-5.
Intel 5000X chipset MCH Memory Mapping Registers (Sheet 1 of 2)
Name
Function
MIR[2:0]
Memory Interleaving Registers (FB-DIMM Branch Interleaving)
AMIR[2:0]
Scratch pad register for software to use related to memory interleaving. For
example, software can write MMIO gap adjusted limits here to aid in subsequent
memory RAS operations.
PAM[6:0]
Defines attributes for ranges in the C and D segments. Supports shadowing by
routing reads and writes to memory of I/O.
SMRAMC
EXSMRC, EXSMRAMC
EXSMRTOP
BCTRL
SMM Control
Extended SMM Control
Top of extended SMM memory
Contains VGAEN and ISAEN for each PCI Express.
TOLM
Top of low memory. Everything between TOLM and 4 GB will not be sent to
memory.
HECBASE
Base of the memory mapped configuration region that maps to all PCI Express
registers.
MBASE (dev 2-7)
Base address for memory mapped I/O to PCI Express ports 2 - 7.
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Table 4-5.
Intel 5000X chipset MCH Memory Mapping Registers (Sheet 2 of 2)
Name
Function
MLIMIT (dev 2-7)
PMBASE (dev 2-7)
Limit address for memory mapped I/O to PCI Express ports 2 - 7.
Base address for memory mapped I/O to prefetchable memory of PCI Express
1
ports 2-7
PMLIMIT (dev 2-7)
PMBU (dev 2-7)
Limit address for memory mapped I/O to prefetchable memory of PCI Express
ports 2-7.
Prefetchable Memory Base (Upper 32 bits) - Upper address bits to the base
address of prefetchable memory space. If the prefetchable memory is below 4 GB,
this register will be set to all 0’s.
PMLU (dev 2-7)
Prefetchable Memory Limit (Upper 32 bits) - Upper address bits to the limit address
of prefetchable memory space. If the prefetchable memory is below 4 GB, this
register will be set to all 0’s.
PCICMD (dev 2-7)
MSE (Memory Space Enable) bit enables the memory and prefetchable ranges.
Notes:
1. The chipset treats memory and prefetchable memory the same. These are just considered 2 apertures to the
PCI Express port.
4.4.2
Address Disposition for Processor
The following tables define the address disposition for the Intel 5000X chipset MCH.
Table 4-6 defines the disposition of outbound requests entering the Intel 5000X chipset
MCH on the processor bus. Table 4-10 defines the disposition of inbound requests
entering the Intel 5000X chipset MCH on an I/O bus. For address dispositions of PCI
Express/ESI devices, please refer to the respective product specifications for the
Intel 6700PXH 64 bit PCI Hub or Intel 631xESB/632xESB I/O Controller Hub.
Table 4-6.
Address Disposition for Processor (Sheet 1 of 2)
Address
Conditions
0 to 09FFFFh
Intel 5000P Chipset Behavior
Range
DOS
Coherent Request to Main Memory.
Route to main memory according to Intel 5000P
Chipset MCH.MIR registers. Apply Coherence Protocol.
SMM/VGA
0A0000h to 0BFFFFh
see Table 4-8 and Table 4-9.
C and D BIOS
segments
0C0000h to 0DFFFFh and PAM=11
Non-coherent request to main memory. Rout to
appropriate FB-DIMM device according to Intel 5000P
Chipset MCH.MIR registers.
Write to
0C0000h to 0DFFFFh and PAM=10
Read to
0C0000h to 0DFFFFh and PAM=01
Read to
Issue request to ESI.
0C0000h to 0DFFFFh and PAM=10
Write to
0C0000h to 0DFFFFh and PAM=01
0C0000h to 0DFFFFh and PAM=00
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Table 4-6.
Address Disposition for Processor (Sheet 2 of 2)
Address
Range
Conditions
Intel 5000P Chipset Behavior
E and F BIOS
segments
0E0000h to 0FFFFFh and PAM=11
Non-coherent request to main memory. Rout to
appropriate FB-DIMM device according to Intel 5000P
Chipset MCH.MIR registers.
Write to
0E0000h to 0FFFFFh and PAM=10
Read to
0E0000h to 0FFFFFh and PAM=01
Read to
Issue request to ESI.
0E0000h to 0FFFFFh and PAM=10
Write to
0E0000h to 0FFFFFh and PAM=01
0E0000h to 0FFFFFh and PAM=00
10_0000 <= Addr < TOLM
Low/Medium
Memory
Coherent request to main memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Coherence protocol is applied.
Note: The extended SMRAM space is within this range.
Extended
SMRAM Space
ESMMTOP-TSEG_SZ <= Addr <
ESMMTOP
see Table 4-8 and Table 4-9.
Low MMIO
TOLM <= Addr < FE00_0000 and
falls into a legal BASE/LIMIT range PMBASE/PMLIMIT> registers.
Request to PCI Express based on <MBASE/MLIMIT and
TOLM <= Addr < FE00_0000 and
not in a legal BASE/LIMIT range
Send to ESI to be master aborted.
PCI Express
MMCFG
HECBASE <= Addr <
HECBASE+256MB
Convert to a configuration access and route according
to the Configuration Access Disposition.
Intel 5000X
FE00_0000h to FEBF_FFFFh AND
Issue configuration access to memory mapped register
inside Intel 5000P Chipset or to the FB-DIMM based on
chipset specific valid Intel 5000P Chipset memory
mapped register address plus AMB the context.
targeted addresses
FE00_0000h to FEBF_FFFFh AND
(NOT a valid Intel 5000P Chipset
memory mapped register address
or NOT a valid AMB targeted
address)
Send to ESI to be master aborted.
I/O APIC
registers
FEC0_0000 to FEC8_FFFFh
Non-coherent request to PCI Express or ESI based on
Table 4-4.
Intel®
FEC9_0000h to FED1_FFFF
Issue request to ESI.
631xESB/
632xESB I/O
Controller Hub
/ Intel®
631xESB/
632xESB I/O
Controller Hub
timers
High SMM
Interrupt
FEDA_0000h to FEDB_FFFF
see Table 4-8 and Table 4-9.
Route to appropriate FSB(s).
interrupt transaction to
FEE0_0000h to FEEF_FFFFh
(not really memory space)
memory transaction to
Send to ESI to be master aborted.
Issue request to ESI.
FEE0_0000h to FEEF_FFFFh
Firmware
FF00_0000h to FFFF_FFFFh
High Memory
1_0000_0000 to MIR[2].LIMIT
(max FF_FFFF_FFFF)
Coherent request to main memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Coherence protocol is applied.
High MMIO
All others
PMBU+PMBASE <= Addr <=
PMLU+PMLIMIT
Route request to appropriate PCI Express port.
All Others (subtractive decoding)
Issue request to ESI.
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4.4.2.1
Access to SMM Space (Processor Only)
Accesses to SMM space are restricted to processors, inbound transactions are
prohibited. Inbound transactions to enabled SMM space are not allowed and
Intel 5000X chipset MCH will set Intel 5000P Chipset MCH.EXSMRAMC.E_SMERR bit.
The following table defines when a SMM range is enabled. All the enable bits:
G_SMRAME, H_SMRAM_EN, and TSEG_EN are located in the Intel 5000P Chipset
MCH.EXSMRC register.
Table 4-7.
Enabled SMM Ranges
Extended
SMRAM Space
(TSEG)
Global Enable
G_SMRAME
High SMM Enable TSEG Enable
Legacy SMM
Enabled?
HIGH SMM
Enabled?
H_SMRAM_EN
TSEG_EN
Enabled?
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
No
Yes
Yes
No
No
No
No
No
No
Yes
No
Yes
Yes
No
Yes
The processor bus has a SMMEM# signal that qualifies the request asserted as having
access to a system management memory. The SMM register defines SMM space that
may fall in one of three ranges: legacy SMRAM, Extended SMRAM Space (TSEG), or
High SMRAM Space (H_SMM). Table 4-8 defines the access control of SMM memory
regions from processors.
Table 4-8.
SMM Memory Region Access Control from Processor
Code Access to
Data Access to
G_SMRAME
D_LCK
D_CLS
D_OPEN
SMMEM#
1
2
SMM Memory
SMM Memory
3
0
x
0
0
0
0
x
x
0
0
1
x
0
0
1
0
x
0
1
x
1
no
no
no
no
1
1
1
1
yes
yes
yes
yes
yes
no (legacy SMM)
yes (H_SMM,
TSEG)
4
1
x
1
1
1
1
1
0
1
0
1
1
x
0
x
0
x
0
0
1
1
illegal settings
illegal settings
1
1
1
1
no
no
no
no
yes
yes
yes
no (legacy SMM)
yes (H_SMM,
TSEG)
Notes:
1. BRLC
2. Data access transaction other than BRLC
3. For access to TSEG region (address range between ESMMTOP - TSEG_SZ and ESMMTOP), Intel 5000P Chipset
MCH will route to identical system memory by definition (as TSEG is not enabled).
4. It is a programming error if D_CLS and D_OPEN are both set to 1, Intel 5000P Chipset MCH’s
behavior is undefined. Intel 5000P Chipset MCH could master abort SMM access.
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The Intel 5000P Chipset prevents illegal processor access to SMM memory. This is
accomplished by routing memory requests from processors as a function of transaction
request address, code or data access, the SMMEM# signal accompanying request and
the settings of the Intel 5000P Chipset MCH.SMRAMC, Intel 5000P Chipset
MCH.EXSMRC, and Intel 5000P Chipset MCH.BCTRL registers. Table 4-9 defines Intel
5000P Chipset MCH’s routing for each case. Illegal accesses are either routed to the ESI
bus where they are Master Aborted or are blocked with error flagging. SMMEM# only
affects Intel 5000P Chipset behavior if it falls in an enabled SMM space. Note that the
D_CLS only applies to the legacy (A_0000-B_FFFF) SMM region. The bold values
indicate the reason SMM access was granted or denied.
Note:
If a spurious inbound access targets the enabled SMM range (viz., legacy, High SMM
Memory and Extended SMRAM (T-segment)), then it will be Master-aborted. The
EXSMRAMC.E_SMERR register field (Invalid SMRAM) is set for accesses to the High
SMM Memory and Extended SMRAM (T-segment)). Refer to Table 4-10.
Table 4-9.
Decoding Processor Requests to SMM and VGA Spaces
SMM
Transaction
Address
Range
SMM Memory
Address
Access
SMM region
Routing
Control
Range
1
Legacy
VGA/SMM
A_0000h
to
B_FFFFh
A_0000h
to
B_FFFFh
x
0
1
1
1
0
1
1
1
1
x
1
x
0
x
x
x
x
x
x
x
x
x
x
0
1
1
1
x
x
x
x
x
x
x
1
0
to the VGA-enabled port (in
BCTRL);
otherwise, ESI
2
yes
no
yes
x
3
to SMM memory
Extended
SMRAM
(TSEG)
ESMMTOP -TSEG_SZ
to
ESMMTOP
ESMMTOP -TSEG_SZ
to
ESMMTOP
to identical system memory
by definition
x
yes
no
no
to SMM memory
block access: master abort
set EXSMRAMC.E_SMERR
High SMM
FEDA_0000h
to
FEDB_FFFFh
A_0000h
to
B_FFFFh
x
0
1
1
1
1
x
0
1
1
1
x
x
x
x
x
x
x
x
1
0
to ESI (where access will be
master aborted)
x
4
yes
no
no
to SMM memory
block access: master abort
set EXSMRAMC.E_SMERR
Notes:
1. SMM memory access control, see Table 4-8.
2. Software must not cache this region.
3. One and only one BCTRL can set the VGAEN; otherwise, send to ESI.
4. Notice this range is mapped into legacy SMM range (A_0000h to B_FFFFh).
4.4.3
Inbound Transactions
In general, inbound I/O transactions are decoded and dispositioned similarly to
processor transactions. The key differences are in SMM space, memory mapped
configuration space, and interrupts. Inbound transaction targeting at itself will be
master aborted.
Note that inbound accesses to the SMM region must be handled in such a way that FSB
snooping and associated potential implicit writebacks are avoided. This is necessary to
prevent compromising SMM data by returning real content to the I/O subsystem. Note
also that DMA engine is treated as an I/O device, thus accesses initiated by the DMA
engine are considered as inbound accesses.
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For all table entries where an access is forwarded to ESI to be master aborted, if an
access comes from ESI, the Intel 5000X chipset MCHESI may master abort a
transaction without forwarding it back to the ESI.
Table 4-10. Address Disposition for Inbound Transactions (Sheet 1 of 2)
Address
Conditions
0 to 09FFFFh
Intel 5000P Chipset Behavior
Range
DOS
Coherent Request to Main Memory.
Route to main memory according to Intel 5000P
Chipset MCH.MIR registers. Apply Coherence Protocol.
SMM/VGA
0A0000h to 0BFFFFh,
and VGAEN=0
Send to ESI to be master aborted. Set
EXSMRAMC.E_SMERR
0A0000h to 0BFFFFh
and VGAEN=1
Non-coherent read/write request to the decoded PCI
1
Express or to ESI based on BCTRL
2
C, D, E, and F
BIOS segments
0C0000h to 0FFFFFh and PAM=11
Non-coherent request to main memory. (Coherency
does not need to be guaranteed. Coherency protocol
can be followed if it simplifies implementation.) Route
to appropriate FB-DIMM according to Intel 5000P
Chipset MCH.MIR registers.
Low/Medium
Memory
10_0000 <= Addr < ESMMTOP -
TSEG_SZ
Coherent Request to Main Memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Apply Coherence Protocol.
Extended
SMRAM Space
ESMMTOP -TSEG_SZ <= Addr <
ESMMTOP
Send to system memory if G_SMRAME = 0 or
(G_SMRAME = 1 and T_EN = 0); otherwise Send to
ESI to be master aborted. Set EXSMRAMC.E_SMERR
bit
Low MMIO
TOLM <= Addr < FE00_0000 and
Request to PCI Express based on <MBASE/MLIMIT and
falls into a legal BASE/LIMIT range PMBASE/PMLIMIT> registers.
TOLM <= Addr < FE00_0000 and
not in a legal BASE/LIMIT range
Send to ESI to be master aborted.
PCI Express
MMCFG
HECBASE <= Addr <
HECBASE+256MB
Inbound MMCFG access is not allowed and will be
aborted.
Intel 5000X
FE00_0000h to FEBF_FFFFh AND
Inbound MMCFG access is not allowed and will be
aborted.
chipset specific valid Intel 5000P Chipset memory
mapped register address
FE00_0000h to FEBF_FFFFh AND
NOT a valid Intel 5000P Chipset
memory mapped register address
Send to ESI to be master aborted.
I/O APIC
registers
FEC0_0000 to FEC8_FFFFh
Non-coherent request to PCI Express or ESI based on
Table 4-4
Intel 631xESB/ FEC9_0000h to FED1_FFFF
Issue request to ESI.
632xESB I/O
Controller Hub
/ Intel
631xESB/
632xESB I/O
Controller Hub
timers
High SMM
FEDA_0000h to FEDB_FFFF
Send to ESI to be master aborted. Set
EXSMRAMC.E_SMERR bit
Interrupt
Inbound write to FEE0_0000h -
FEEF_FFFFh
Route to appropriate FSB(s). See Interrupt Chapter for
details on interrupt routing.
memory transaction (other than
write) to FEE0_0000h -
FEEF_FFFFh
Send to ESI to be master aborted.
Firmware
FF00_0000h to FFFF_FFFFh
Master abort
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Table 4-10. Address Disposition for Inbound Transactions (Sheet 2 of 2)
Address
Range
Conditions
Intel 5000P Chipset Behavior
High Memory
1_0000_0000 to MIR[2].LIMIT
(max FF_FFFF_FFFF)
Coherent Request to Main Memory. Route to main
memory according to Intel 5000P Chipset MCH.MIR
registers. Apply Coherence Protocol.
High MMIO
PMBU+PMBASE <= Addr <=
PMLU+PMLIMIT
Route request to appropriate PCI Express port
All others
All Others (subtractive decoding)
Issue request to ESI.
Notes:
1. One and only one BCTRL can set the VGAEN; otherwise, send to ESI for master abort.
2. Other combinations of PAM’s are not allowed if inbound accesses to this region can occur. Just like Cayuse,
chipset functionality is not guaranteed.
4.5
I/O Address Map
The I/O address map is separate from the memory map and is primarily used to
support legacy code/drivers that use I/O mapped accesses rather than memory
mapped I/O accesses. Except for the special addresses listed in Section 4.5.1, I/O
accesses are decoded by range and sent to the appropriate ESI/PCI Express port, which
will route the I/O access to the appropriate device.
4.5.1
Special I/O Addresses
There are two classes of I/O addresses that are specifically decoded by the Intel 5000X
chipset MCH:
• I/O addresses used for VGA controllers.
• I/O addresses used for the PCI Configuration Space Enable (CSE) protocol. The I/O
addresses 0CF8h and 0CFCh are specifically decoded as part of the CSE protocol.
Historically, the 64 K I/O space actually was 64 K+3 bytes. For the extra three bytes,
A#[16] is asserted on FSB. The Product Name decodes only A#[15:3] when the
request encoding indicates an I/O cycle. Therefore first three byte I/O accesses with
A#[16] asserted are decoded as if they were accesses to the first three bytes starting
from I/O addresses 0 (wrap-around the 64 KB line). A[16] is not forwarded by Intel
5000X chipset MCH.
At power-on, all I/O accesses are mapped to the ESI.
4.5.2
Outbound I/O Access
The Intel 5000P Chipset MCH chipset allows I/O addresses to be mapped to resources
supported on the I/O buses underneath the Intel 5000P Chipset. This I/O space is
partitioned into 16 4 KB segments. Each of PCI Express port can have from 1 to 16
consecutive segments mapped to it by programming its IOBASE and IOLIM registers.
Each PCI Express port must be assigned contiguous segments. The lowest segment,
from 0 to 0FFFh, should be programmed to send to the ESI for compatibility.
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Figure 4-4. System I/O Address Space
1_0003
FFFF
+3 bytes
(Decoded
as 0_000X)
Segment F
F000
2000
1000
Segment 1
Segment 0
0000
4.5.2.1
Outbound I/O Accesses Routing
The Intel 5000P Chipset applies these routing rules in the following order:
(A[2:0] for the following is not physically present on the processor bus, but are
calculated from BE[7:0]).
1. I/O addresses used for VGA controllers on PCI Express:
If PCICMD[y].IOAE and BCTRL[y].VGAEN of PCI Express port y are set to 1 and
BCTRL[y].VGA16bdecode = 0, then I/O accesses with the following VGA addresses
will be forwarded to PCI Express port y: A[9:0] (A[15:10] are ignored for this
decode since BCTRL[y].VGA16bdecode is set to 0) = 3B0h - 3BBh, 3C0h - 3DFh if
every addressed byte is within these two ranges. For example, a two byte read
starting at X3BBh includes X3BB -X3BCh. (X can be any hex number since
A[15:10] are ignored) Since the second byte with A[9:0] = 3BCh is not within
these ranges, the access is not routed to port y.
If PCICMD[y].IOAE and BCTRL[y].VGAEN of port y are set to 1 and
BCTRL[y].VGA16bdecode = 1, then I/O accesses with the following VGA addresses
will be forwarded to PCI Express port y: A[15:0] = 03B0h - 03BBh, 03C0h - 03DFh
if every addressed byte is within these two ranges. For example, a four byte I/O
read starting at F3B0h includes F3B0 - F3B3h are not within these ranges, the
access is not routed to port y.
Note that software should program PEXCMDs and BCTRLs to ensure that at most
only one port is allowed to forward these accesses with VGA addresses. It is a
programming error if more than one port are programmed to forward accesses with
VGA addresses.
2. Configuration accesses: If a request is a DW accesses to 0CF8h (See CFGADR
register) or
1-4 B accesses to 0CFCh (See CFGDAT register) with configuration space enabled
(See CFGE bit, bit 31, of CFGADR register), the request is considered a
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configuration access. Configuration accesses are routed based on the bus and
device numbers as programmed by software.
3. ISA Aliases: If the PCICMD[y].IOAE and BCTRL[y].ISAEN are set to 1 for a PCI
Express port y and the I/O address falls within (IOBASE[y], IOLIMIT[y]) and if the
addresses are X100-X3FFh, X500-X7FFh, X900-XBFF, and XD00-XFFFh (X can be
any hex number) will result in the access being sent out to the ESI (Intel 631xESB/
632xESB I/O Controller Hub). This is the top 768 B in each 1 KB block.
4. I/O defined by IOBASE/IOLIMIT: If PCICMD[y].IOAE is set for a given PCI Express
port and the I/O address falls in this range: (IOBASE[y] <= address <=
IOLIMIT[y]) for that port, then the access will be routed to the PCI Express port y.
5. Otherwise, the I/O Read/Write is sent to ESI (Intel 631xESB/632xESB I/O
Controller Hub).
4.6
Configuration Space
All chipset registers are represented in the memory address map. In addition, some
registers are also mapped as PCI registers in PCI configuration space.These adhere to
the PCI Local Bus Specification, Revision 2.2 .
The memory mapped configuration space is described in Section 4.3.4. Individual
register maps are in the registers chapters of the Intel 5000X chipset MCH Component
Specifications.
If a CPU issues a zero length configuration cycle accessing the Intel 5000P Chipset
MCH’s internal configuration space registers or the CB_BAR/AMB Memory mapped area,
then it will be completed on the FSB “in order” with no data.
4.7
I/O Address Map
The I/O address map is separate from the memory map and is primarily used to
support legacy code/drivers that use I/O mapped accesses rather than memory
mapped I/O accesses. Except for the special addresses listed in “Special I/O addresses”
on page 246, I/O accesses are decoded by range and sent to the appropriate ESI/PCI
Express port, which will route the I/O access to the appropriate device.
4.7.1
Special I/O Addresses
There are two classes of I/O addresses that are specifically decoded by the Intel 5000X
chipset MCH:
• I/O addresses used for VGA controllers.
• I/O addresses used for the PCI Configuration Space Enable (CSE) protocol. The I/O
addresses 0CF8h and 0CFCh are specifically decoded as part of the CSE protocol.
Historically, the 64 K I/O space actually was 64 K+3 bytes. For the extra 3 bytes,
A#[16] is asserted. The Intel 5000P Chipset decodes only A#[15:3] when the request
encoding indicates an I/O cycle. Therefore accesses with A#[16] asserted are decoded
as if they were accesses to address 0 and are forwarded to the Compatibility Bus.
At power-on, all I/O accesses are mapped to the Compatibility Bus.
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4.7.2
Outbound I/O Access
The Intel 5000X chipset allows I/O addresses to be mapped to resources supported on
the I/O buses underneath the MCH. This I/O space is partitioned into 16 4 KB
segments. Each of the I/O buses can have from 1 to 15 segments mapped to it by
programming its IOBASE and IOLIM registers. Each PCI bus must be assigned
contiguous segments. The lowest segment, from 0 to 0-+FFFh, is sent to the ESI.
Figure 4-5. System I/O Address Space
1 0003h
+3 bytes
(Decoded as
0 000Xh)
FFFFh
F000h
Segment F
Segment 2
through
Segment E
2000h
1000h
Segment 1
Segment 0
Compatability
Bus Only
0000h
4.8
Configuration Space
All chipset registers are represented in the memory address map. In addition, some
registers are also mapped as PCI registers in PCI configuration space.These adhere to
the PCI Local Bus Specification, Revision 2.2.
§
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Functional Description
5 Functional Description
This chapter describes each of the MCH interfaces and functional units including the
Dual Independent Bus (DIB), processor Frontside Bus (FSB) interface, the PCI Express
ports, system memory controller, power management, and clocking.
5.1
Processor Front Side Buses
The MCH supports two Dual-Core Intel® Xeon® 5000 Sequence processors on a 65
nanometer process in a 771-land, FC-LGA4 package. Dual-Core Intel Xeon 5000
Sequence is a fourth generation 32-bit Intel® Xeon processor supporting Intel®
Extended Memory 64 Technology (Intel® EM64T) based on Intel NetBurst®
microarchitecture.
The MCH supports 1066/1333 MHz FSB which is a quad-pumped bus running off a
266/333 MHz system clock, and a point to point DIB processor system bus interface.
Each processor FSB supports peak address generation rates of 533 Million Addresses/
second. Both FSB data buses are quad pumped 64-bits which allows peak bandwidths
of 8.5 GB/s (1066 MT/s) and 10.5 GB/s (1333 MT/s). The MCH supports 36-bit host
addressing, decoding up to 64 GB of the processor’s memory address space. Host-
initiated I/O cycles are decoded to AGP/PCI, PCI Express, ESI interface or MCH
configuration space. Host-initiated memory cycles are decoded to AGP/PCI, PCI
Express, ESI or system memory.
5.1.1
FSB Overview
The MCH is the only priority agent for two point to point, independent, processor front
side buses (FSB). These two buses are referred to as Dual Independent Buses (DIB).
The MCH maintains coherency across these two buses. The MCH may complete
deferrable transactions with either defer-replies or in-order responses. Intel 5000X
chipset contains an internal Snoop-Filter to remove unnecessary snoops on the remote
FSB, and to be able to complete transactions in-order without deferring for transactions
that do not need to have a remote snoop. Data transactions on the FSBs are optimized
to support 64 byte cache lines.
Each processor FSB contains a 36 bit address bus, a 64 bit data bus, and associated
control signals. The FSB utilizes a split-transaction, deferred reply protocol. The FSB
uses source-synchronous transfer of address and data to improve performance. The
FSB address bus is double pumped (2X) with ADS being sourced every other clock. The
address bus generates a maximum bandwidth of 133 Million Addresses/second (MA/s).
The FSB data bus is quad pumped (4X) and supports peak bandwidths of 8.5 GB/s
(1066 MT/s) and 10.5 GB/s (1333 MT/s). Parity protection is applied to the data bus.
This yields a combined bandwidth of 17 GB/s (1066 MT/s) and 21 GB/s (1333 MT/s) for
both FSBs.
Interrupts are also delivered via the FSB.
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5.1.2
FSB Dynamic Bus Inversion
The MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data
from the processor. DBI limits the number of data signals that are driven to a low
voltage on each quad pumped data phase. This decreases the worst-case power
consumption of the MCH. The DBI[3:0]# signals indicate if the corresponding 16 bits of
data are inverted on the bus for each quad pumped data phase.
Table 5-1.
DBI[3:0]# / Data Bit Correspondence
DBI[3:0]#
Data Bits
DBI0#
DBI1#
DBI2#
DBI3#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
When the processor or the MCH drives data, each 16-bit segment is analyzed. If more
than 8 of the 16 signals would normally be driven low on the bus, the corresponding
DBI# signal will be asserted and the data will be inverted prior to being driven on the
bus. When the processor or the MCH receives data, it monitors DBI[3:0]# to determine
if the corresponding data segment should be inverted.
5.1.3
FSB Interrupt Overview
The Dual-Core Intel Xeon 5000 Sequence processor supports FSB interrupt delivery.
The legacy APIC serial bus interrupt delivery mechanism is not supported. Interrupt-
related messages are encoded on the FSB as “Interrupt Message Transactions.” In the
Intel 5000X chipset platform, FSB interrupts may originate from the processor on the
system bus, or from a downstream device on the Enterprise South Bridge Interface
(ESI) or AGP. In the later case, the MCH drives the Interrupt Message Transaction onto
the system bus.
In the Intel 5000X chipset the Intel 631xESB/632xESB I/O Controller Hub contains
IOxAPICs, and its interrupts are generated as upstream ESI memory writes.
Furthermore, PCI 2.3 defines Message Signaled Interrupts (MSI) that are also in the
form of memory writes. A PCI 2.3 device may generate an interrupt as an MSI cycle on
its PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be
directed to the IOxAPIC which in turn generates an interrupt as an upstream ESI
memory write. Alternatively, the MSI may be directed directly to the FSB. The target of
an MSI is dependent on the address of the interrupt memory write. The MCH forwards
inbound ESI and AGP/PCI (PCI semantic only) memory writes to address 0FEEx_xxxxh
to the FSB as Interrupt Message Transactions.
5.1.3.1
Upstream Interrupt Messages
The MCH accepts message-based interrupts from PCI (PCI semantics only) or ESI and
forwards them to the FSB as Interrupt Message Transactions. The interrupt messages
presented to the MCH are in the form of memory writes to address 0FEEx xxxxh. At the
ESI or PCI interface, the memory write interrupt message is treated like any other
memory write; it is either posted into the inbound data buffer (if space is available) or
retried (if data buffer space is not immediately available). Once posted, the memory
write from PCI or ESI to address 0FEEx xxxxh is decoded as a cycle that needs to be
propagated by the MCH to the FSB as an Interrupt Message Transaction.
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5.2
Snoop Filter
The Snoop Filter (SF) offers significant performance enhancements on several
workstation benchmarks by eliminating traffic on the snooped frontside bus of the
processor being snooped. By removing snoops from the snooped bus, the full
bandwidth is available for other transactions. Supporting concurrent snoops effectively
reduces performance degradation attributable to multiple snoop stalls. See Figure 5-1,
“Snoop Filter” on page 302.
The SF is composed of two affinity groups each containing 8K sets of x16-way
associative entries. The overall SF size is 16MB in size. Each affinity group supports a
pseudo-LRU replacement algorithm. Lookups are done on a full 32-way per set for hit/
miss checks.
As shown in Figure 5-1 the snoop filter is organized in two halves referred to as the
Affinity Group 1 and Affinity Group 0 or the odd and even snoop filters respectively. As
shown in Figure 5-1 Affinity Group 1 is associated with processor 1 and Affinity Group 0
is associated with processor 0. Under normal conditions a snoop is competed with a 1
snoop stall penalty. When the processors request simultaneous snoops the first snoop
is completed with a one snoop stall penalty, the second snoop requires a 2 snoop stall
penalty.
For the purposes of simultaneous SF access arbitration, processor 0 is given priority
over processor 1. Thus simultaneous snoops are resolved with a 1 snoop stall penalty
for processor 0 and a 2 snoop stall penalty for processor 2.
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Functional Description
Figure 5-1. Snoop Filter
PROC 1
PROC 0
FSB0
FSB1
Coherency
Engine
8K
Sets
16 - Way
16 - Way
Affinity
Affinity
Group 0
Group 1
CDM
MEM IO
The SF stores the tags and coherency state information for all cache lines in the
system. The SF is used to determine if a cache line associated with an address is
cached in the system and where. The coherency protocol engine (CE) accesses the SF
to look-up an entry, update/add an entry, or invalidate an entry in the snoop filter.
The SF has the following features:
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• Snoop Filter tracks total of 16 MB of cachelines (218 L2 lines).
• 8K sets organized as one interleave via a 2 x 16 Affinity Set-Associativity array.
There are a total of 8K x 2 x 16 = 256K Lines (218).
• 2 x 16 Affinity Set-Associativity will allocate/evict entries within the 16-way
corresponding to the assigned affinity group if the SF look up is a miss. Each SF
look up will be based on 32-way (2x16 ways) look up.
• The array size of the snoop filter RAM is equivalent to 1MB plus 0.03MB of Pseudo-
Least-Recently-Used (pLRU) RAM.
Tag array size = 8192 sets * 4 bytes/set/group * (2 groups* 16 ways) = 1048576B
=1MB
pLRU array size = 8192 sets * 15 bits/set/group * (2 groups) = 30720B =
~0.03MB
• The Snoop Filter is operated at 2x of Intel 5000X chipset MCH core frequency, i.e.
533MHz to provide 267 MLUU/s (where a Look-Up-Update operation is a read
followed by a write operation to the tag and pLRU arrays).
— The maximum lookup and update bandwidth of the Snoop Filter is equal to the
max request bandwidth from both FSB’s. The lookup and update bandwidth
from I/O coherent transactions have to share the bandwidth with both FSBs per
request weighted-round-robin arbitration.
— The SF lookup latency is four SF-clocks or two Intel 5000X chipset MCH core
clocks to support single snoop stall in idle condition (single request issued from
either bus). If both bus are making requests simultaneously, the snoop-filter
will always select bus 0 first. In such scenario, bus 0 request will have one
snoop-stall and bus 1 request will have two snoop-stalls.
• Pseudo-Least-Recently-Used (pLRU) replacement algorithm, with updates on
lookups, and invalidates.
• Tag entries supporting a 40-bit internal physical address space. The MCH external
address space is 36 bits.
• Stores coherency state (EM) and Bus[1:0] for each valid cache line in the system.
The tracking algorithm utilizes conservative tracking (super-set tracking). The
processor can silently down grade a line state from E to S/I or S to I without any
action appearing on the FSB. Therefore, a line appearing in the SF as E states may
actually missed in the corresponding processor caches. Conversely a SF S-line will
never be found in E/M state in a processors L2 cache, or a SF miss will never be
found in M/E/S state in a processors L2 cache. The following is the summery of the
snoop-filter state definitions:
— Coherency state: the cache line is in E/M state if the bit is set; else, the line is
in share state
— If Bus[1:0]=00, the entry is invalid.
— If Bus[1:0]=01, the FSB0 processor(s) has ownership of the line.
— If Bus[1:0]=10, the FSB1 processor(s) has ownership of the line.
— If Bus[1:0]=11, both buses have ownership and the line must be shared by
both FSB processors (EM must be 0).
— EM||Bus[1:0] =111 is a reserved definition.
• ECC coverage, with correction of single bit errors, detection of double bit errors
(SEC-DED).
— pLRU array does not need ECC protection. Bit failure will result in selecting
different entry than the pLRU selection and may affect the performance. There
are no correctness issue.
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Functional Description
• Snoop-Filter Fast array initialization and/or self test through configuration register
access.
5.2.1
Snoop Filter Address Bit Mapping
The SF supports a 40-bit physical address. Table 5-1 shows the partitioning of the
address for indexing into the SF array.
Table 5-1.
Snoop Filter Physical Address Partitioning
Tag (21b)
Set (13b)
Byte Offset (6b)
A[39:19]
A[18:6]
A[5:0]
5.2.2
Operations and Interfaces
The following table shows the snoop-filter look up qualifier for coherent transaction
issued from processors, i.e. ADS# assertion driven from processors.
Table 5-2.
FSB transaction encoding qualification for SF look up
SF look up transactions from FSB:
The following REQa[2:0] encoding with ADS#
assertion from processor qualification.
REQa[2:0]
Request Names
BRIL/BIL
BRLC
0
1
1
1
1
1
0
1
0
1
0
0
0
1
1
BRLD/BLR
BWL
BWIL/BLW
Table 5-1, “Snoop Filter” on page 302 shows the organization of each snoop filter entry,
and interpretation of the contents.
Table 5-3.
Snoop Filter Entry
Bits
[31]
Value
Redundant bit.
ECC check bits
[30:24
]
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Table 5-3.
Snoop Filter Entry
Bits
Value
State of the cache line
1 The cache line is in E/M state, i.e. the line is either exclusive (but clean) or modified (dirty) state.
0 The cache line is in non-E/M state, i.e. S state if Bus presence vector is non-zero or I state if Bus
presence vector is zero.
[23]
Bus presence vector
[00] The entry is invalid
[22:21
]
[xx] The entry is present in any of the processor L2 in the corresponding FSB. Bus0 is the least
significant bit. Bus0 corresponds to FSB0 on the Intel 5000 series chipset MCH. Bus1 corresponding
to FSB1
[20:0]
Tag portion of the address
The snoop filter supports the following key operations during normal operation. Due to
timing constraints, these lookup and update commands have been removed for the SF
configuration access.
• SF_Lookup with pLRU status update by MRU operation
On a lookup, the SF uses the tag and set portion of the input address to determine
if the entry is in the SF. The SF asserts a hit if there is a match and provides the
contents, and way information for the matched entry. If the lookup is a miss, the
SF provides the contents of the victim entry, set and way information of the victim.
The pLRU vector is updated according to a Most-Recently-Used (MRU) algorithm.
The SF indicates if a single or double bit error was detected. Single-bit errors are
corrected (but the array is not updated). Hit/miss calculation is performed after the
ECC logic. All FSB request to memory will use this command for SF lookup.
• SF_Lookup with no pLRU status update operation
The SF uses the tag and set portion of the input address to determine if the entry is
in the SF. The SF asserts a hit if there is a match and provides the contents, and
way information for the matched entry. If the lookup is a miss, the SF provides the
contents of the victim entry, set and way information of the victim. The pLRU vector
is not updated. The SF indicates if a single or double bit error was detected. Single-
bit errors are corrected (but the array is not updated). Hit/miss calculation is
performed after the ECC logic. Inbound memory accesses will use this command
for SF lookup.
• SF_Update with pLRU status update by LRU operation
Set and way are provided for write operations. Writes can either be updates or
invalidates. On SF-invalidations, the pLRU array is updated using a Least-Recently-
Used (LRU) entry tracking algorithm. The SF update during inbound write will also
use the “SF_Update with pLRU status update by LRU op” if there is a hit during SF
lookup.
• SF_Update with no pLRU status update operation
Set and way are provided for write operations. The pLRU array is not updated. This
command is used during non-SF-entry-invalidation operations.
5.3
System Memory Controller
The MCH masters four Fully-Buffered DIMM (FB-DIMM) memory channels. Up to four
DIMMs can be connected to each FB-DIMM channel (up to sixteen DIMMs for the entire
array). FB-DIMM memory utilizes a narrow high speed frame oriented interface referred
to as a channel.
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Functional Description
The four FB-DIMM channels are organized into two branches of two channels per
branch. Each branch is supported by a separate Memory Controller (MC). The two
channels on each branch operate in lock step to increase FB-DIMM bandwidth. A branch
transfers 16 bytes of payload/frame on Southbound lanes and 32 bytes of payload/
frame on Northbound lanes.
The two branches may be operated in mirrored (RAID 1) or non-mirrored mode. When
operating in mirrored mode, 64 GB of memory will produce an effective 32 GB memory
space.
The key features of the FB-DIMM memory interface are summarized in the following
list.
• Four Fully Buffered DDR (FB-DIMM) memory channels.
• Branch channels are paired together in lock step to match FSB bandwidth
requirement.
• Each FB-DIMM Channel can link up to four Fully Buffered - DDR DIMMs (FB-DIMM).
• Supports up to 16 dual-ranked FB-DDR2 4GB DIMMs, that is, 64GB1of physical
memory in non-mirrored configuration or 32GB of physical memory in mirrored
configuration.
• The FB-DIMM link speed is at 6x the DDR data transfer speed. A 3.2 GHz FB-DIMM
link supports DDR2-533 (FSB@1067 MT/s).
• The MCH will comply with the FB-DIMM specification definition of a host and will be
compatible with any FB-DIMM-compliant DIMM.
• Special single channel, single DIMM operation mode (Branch 0, Channel 0, Slot 0
position only).
• All memory devices must be DDR2.
Table 5-2 and Figure 5-4 present system memory capacity as a function of DRAM
device capacity and MCH operating mode.
Table 5-2.
Minimum System Memory Configurations & Upgrade Increments
Smallest System
Configuration - One
DIMM
Smallest Upgrade
Increment - Two
DIMM
DRAM Technology
256 Mb
512 Mb
256 MB
512 MB
512 MB
1024 MB
2048 MB
4096 MB
1024 Mb
2048 Mb
1024 MB
2048 MB
The Smallest System Configuration - One DIMM column represents the smallest
possible single DIMM capacity for a given technology (MCH operating in single channel,
single DIMM mode with x8 single rank (x8SR) DIMM populated). The Smallest Upgrade
Increment - Two DIMMs column represents the smallest possible memory upgrade
capacity for a given technology using two x8 single rank DIMMs.
1. User can only access up to 63.5 GB of memory due to minimum 256 MB MMIO/TOLM and limited
address decoding above 64 GB.
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Table 5-3.
Maximum 16 DIMM System Memory Configurations
DRAM Technology x8
Single Rank
Maximum Capacity
Mirrored Mode
Maximum Capacity
Non-Mirrored Mode
256 Mb
512 Mb
2 GB
4 GB
8 GB
16 GB
4 GB
8 GB
1024 Mb
2048 Mb
16 GB
32 GB
Note: The Maximum Capacity Mirrored Mode and Maximum Capacity Non-Mirrored Mode columns represent
the system memory available when all DIMM slots are populated with identical x8 Single Rank (x8DR)
DIMMs using the DRAM Technology indicated.
Table 5-4.
Maximum 16 DIMM System Memory Configurations
DRAM Technology x4
Dual Rank
Maximum Capacity
Mirrored Mode
Maximum Capacity
Non-Mirrored Mode
256 Mb
512 Mb
8 GB
16 GB
32 GB
32 GB
16 GB
32 GB
64 GB
64 GB
1024 Mb
2048 Mb
Note: The Maximum Capacity Mirrored Mode and Maximum Capacity Non-Mirrored Mode columns represent
the system memory available when all DIMM slots are populated with identical x4 Double Rank (x4DR)
DIMMs using the DRAM Technology indicated.
5.3.1
Memory Population Rules
DIMM population rules depend on the operating mode of the MC. When operating in
non-mirrored mode the minimum memory upgrade increment is two identical DIMMs
per branch (DIMMs must be identical with respect to size, speed, and organization).
Non-mirrored mode has an exceptional mode that operates with a single DIMM which is
discussed in the following section. When operating in mirrored mode the minimum
upgrade increment is four identical DIMMs
5.3.1.1
Non-Mirrored Mode Memory Upgrades
The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must
cover the same slot position on both channels. DIMMs that cover a slot position must
be identical with respect to size, speed, and organization. DIMMs that cover adjacent
slot positions need not be identical.
Within a branch memory DIMMs must be populated in slot order; slot 0 is populated
first, slot 1 second, slot 2 third, and slot 3 last. Slot 0 is closest to the MCH.
Section 5-2 depicts the minimum two DIMM configuration. The populated DIMMs are
depicted in gray (Slot 0 of Branch 0 populated).
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Functional Description
Figure 5-2. Minimum Two DIMM Configuration
SLOT 3
SLOT 2
SLOT 1
SLOT 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
BRANCH 0
BRANCH 1
Memory Controller
Figure 5-3 depicts the next two positions where DIMMs may be added. These positions
are depicted in dark gray. The two upgrade positions are Branch 0, Slot 1 and Branch 1,
Slot 0. Of these Branch 1, Slot 0 is the preferred upgrade because it allows both
branches to operate independently and simultaneously. FB-DIMM memory bandwidth is
doubled when both branches operate in parallel.
While it is possible to completely populate one branch before populating the second
branch, it is not desirable to do so from a performance standpoint. In general memory
upgrades should be balanced with respect to both branches to optimize FB-DIMM
performance.
Figure 5-3. Next Two DIMM Upgrade Positions
SLOT 3
SLOT 3
SLOT 2
SLOT 1
SLOT 0
SLOT 2
SLOT 1
SLOT 0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
BRANCH 0
BRANCH 1
Memory Controller
Figure 5-4 depicts a special single DIMM non-mirrored operation mode. This mode
requires that the DIMM be placed in Branch 0, Channel 0, Slot 0. When upgrading from
this mode the normal two DIMM memory upgrade rules are followed.
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Figure 5-4. Single DIMM Operation Mode
SLOT 3
SLOT 2
SLOT 1
SLOT 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
BRANCH 0
BRANCH 1
Memory Controller
5.3.1.2
Mirrored Mode Memory Upgrades
When operating in mirrored mode both branches operate in lock step. In mirrored
mode Branch 1 contains a replicate copy of the data in Branch 0. For this reason the
minimum memory upgrade increment, for mirrored mode, is four DIMMs across all
branches. The DIMMs must cover the same slot position on both branches. DIMMs that
cover a slot position must be identical with respect to size, speed, and organization.
DIMMs within a slot position must match each other, but aren’t required to match
adjacent slot positions.
Figure 5-5 shows the minimum memory configuration required to operate in mirrored
mode.
Figure 5-5. Minimum Mirrored Mode Memory Configuration
SLOT 3
SLOT 2
SLOT 1
SLOT 0
SLOT 3
SLOT 2
SLOT 1
SLOT 0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
BRANCH 0
BRANCH 1
Memory Controller
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Figure 5-6 shows the positions of the next four DIMM upgrade. Like non-mirrored mode
upgrade DIMMs must be added in slot order, starting from the slot closest to the MCH.
DIMMs in a slot position must be identical with respect to size, and organization. Speed
should be matched but is not required. The MCH will adjust to the lowest speed DIMM.
DIMMs in adjacent slots need not be identical.
Figure 5-6. Mirrored Mode Next Upgrade
SLOT 3
SLOT 3
SLOT 2
SLOT 1
SLOT 0
SLOT 2
SLOT 1
SLOT 0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
BRANCH 0
BRANCH 1
Memory Controller
5.3.2
Fully Buffered DIMM Technology and Organization
Fully Buffered DIMM technology was developed to address the higher performance
needs of server and workstation platforms. FB-DIMM addresses the dual needs for
higher bandwidth and larger memory sizes.
FB-DIMM memory DIMMs contain an Advanced Memory Buffer (AMB) device that
serves as an interface between the point to point FB-DIMM Channel links and the DDR2
DRAM devices. Each AMB is capable of buffering up to two ranks of DRAM devices. Each
AMB supports two complete FB-DIMM channel interfaces. The first FB-DIMM interface is
the incoming interface between the AMB and its proceeding device. The second
interface is the outgoing interface and is between the AMB and its succeeding device.
The point to point FB-DIMM links are terminated by the last AMB in a chain. The
outgoing interface of the last AMB requires no external termination.
There are three major components of the FB-DIMM channel interface:
• 14 Differential Northbound Signal pairs
• 10 Differential Southbound Signal pairs
• 1 Differential Clock Signal pair
Figure 5-7 depicts a single FB-DIMM channel with these three signal groups.
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Figure 5-7. FB-DIMM Channel Schematic
NORTHBOUND
NORTHBOUND
14
SOUTHBOUND
10
14
SOUTHBOUND
10
CLOCK
GENERATOR
A FB-DIMM channel consists of 14 unidirectional differential signal pairs referred to as
the Northbound path, 10 unidirectional differential signal pairs referred to as the
Southbound path, and a differential reference clock.
NOTE: The northbound signal pairs are enumerated from 0 to 13. Signal pair 13 is not
active but must be connected to properly terminate the FB-DIMM channel. See
sections, Figure 2.2.1, “FB-DIMM Branch 0” on page 29 and Figure 2.2.2, “FB-DIMM
Branch 1” on page 30.
The southbound path is used to convey DIMM commands and write data to the
addressed DIMMs. The northbound path returns read data and status from the
addressed DIMM.
The northbound and southbound paths are used to convey FB-DIMM frames that are
synchronized to the reference clock. Each frame consists of 12 data transfers.
Southbound frames contain a payload of 8 bytes per frame per channel. Northbound
frames contain a payload of 16 bytes per frame per channel.
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Functional Description
5.3.3
FB-DIMM Memory Operating Modes
The MCH supports two major modes of operation, mirrored and non-mirrored.
5.3.3.1
Non-Mirrored Mode Operation
When operating in non-mirrored mode the MCH operates the two branches
independently. In non-mirrored mode the full MCH address space of 64GB is available.
Normally when operating in non-mirrored mode both channels on a branch are
operated in lock step, referred to as dual-channel mode. There is a single DIMM, single
channel mode of operation referred to as single-channel mode.
5.3.3.1.1
Non-Mirrored Mode ECC
ECC is supported differently for each of these single- and dual-channel modes:
Dual-Channel Mode:
When branches operate in dual-channel mode, the MCH supports the 18 device DRAM
failure correction code option for FB-DIMM. As applied by Intel 5000X chipset MCH, this
code has the following properties:
• Correction of any x4 or x8 DRAM device failure
• Detection of 99.986% of all single bit failures that occur in addition to a x8 DRAM
failure. The MCH will detect a series of failures on a specific DRAM and use this
information in addition to the information provided by the code to achieve 100%
detection of these cases.
• Detection of all two wire faults on the DIMMs. This includes any pair of single bit
errors.
• Detection of all permutations of two x4 DRAM failures.
Single-Channel Mode:
When the branch operates in single-channel/single-DIMM mode, the MCH employs x8
SDDC as in the dual channel case. However, in this case, the ECC RAS feature set is
limited for the single DIMM memory subsystem. In the single DIMM mode (for
example, nine x8 devices), the SDDC cannot correct single wire fault (stuck-at) errors
or permanent full device errors. This is because the error correction capability in the
SDDC is limited to adjacent symbol errors on a 16-bit boundary and in the single DIMM
mode with a Burst Length of 8, there are 4 transfers of 8B to form a 32B codeword.
Hence a single wire failure in the same device is replicated across all 4 symbols
hampering the error correction. The SDDC can detect most x4/x8 DRAM failures but it
can only correct adjacent symbol errors that occur within a 16-bit boundary of each
codeword
5.3.3.2
Mirrored Mode Operation
Memory Mirroring MCH is a user-selectable feature. Mirrored mode provides for
complete recovery from a DIMM device failure. The mirroring feature is fundamentally
a way for hardware to maintain two copies of all data in the memory subsystem, such
that a hardware failure or uncorrectable error is no longer fatal to the system. When an
uncorrectable error is encountered during normal operation, hardware simply retrieves
the “mirror” copy of the corrupted data, and no system failure will occur unless both
primary and mirror copies of the same data are corrupt simultaneously (statistically
very unlikely).
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When operating in mirrored mode FB-DIMM Branch 0 (Channels 0/1) and Branch 1
(Channels 2/3) contain replicate copies of data (are mirrored images). Since Branch 1
contains a replicate copy of Branch 0’s data, the maximum addressable memory is
reduced to 32 GB.
Mirrored mode must be selected at configuration time by enabling mirrored operation.
The general flows for mirroring are as follows:
• The same Write (in the non-failed case) is issued to both branches in the same
cycle (which is complete when both branches acknowledge).
• Different Reads (in the non-failed case) are issued to each branch in the same
cycle. Read returns from Branch 1 are delayed two cycles from read returns from
Branch 0.
• Corrected data will be forwarded to the requester.
• Uncorrectable errors will be retried from the other image. If the other image is off-
line, uncorrectable errors will be retried from the same image.
• Software can temporarily degrade operation to one memory branch and then
resume operation with both memory branches.
• To recover from a failed DIMM:
— DIMM failure is detected
— The defective branch is shut down
— The system is gracefully shut down by operator and the defective DIMM is
replaced
— The system is repowered up
— Normal processing is restored
5.3.3.3
5.3.3.4
Mirrored Mode ECC
When operating in non-mirrored mode the MCH operates the two branches in lock step
(one branch mirroring the contents of the other). In mirrored mode the maximum
address space is reduced to 32GB because the two channels are mirroring each other.
When operating in mirrored mode both channels on a branch are operated in lock step,
referred to as dual-channel mode.
ECC is calculated using the dual-channel method defined in Section 5.3.3.1.1.
Memory Sparing
At configuration time, a DIMM rank is set aside to replace a defective DIMM rank. When
the error rate for a failing DIMM rank reaches a pre-determined threshold, the
SPCPS.LBTHRconfiguration bit will issue an interrupt and initiate a spare copy. While
the copy engine is automatically reading locations from the failing DIMM rank and
writing them to the spare (see Section 3.9.23.4 and Section 3.9.23.5, “Spare Copy
Status & Spare Copy Control”, system reads will be serviced from the failing DIMM
rank, and system writes will be written to both the failing DIMM rank and the spare
DIMM rank. At the completion of the copy, the failing DIMM rank is disabled and the
“spared” DIMM rank will be used in its place. The MCH will change the rank numbers in
the DMIRs from the failing rank to the spare rank. DMIR.LIMIT’s are not updated.
This mechanism requires no software support once it has been enabled by designating
the spare rank through the SPCPC.SPRANK configuration register field and enabling
sparing by setting the SPCPC.SPAREN configuration bit. Hardware will detect the
threshold-initiated fail, accomplish the copy, and off-line the “failed” DIMM rank once
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Functional Description
the copy has completed. This is accomplished autonomously by the memory control
subsystem. The SPCPS.SFO configuration bit is set and an interrupt is issued indicating
that a sparing event has completed.
Sparing cannot be invoked while operating a mirrored memory configuration. Sparing
to a smaller DIMM is not supported.
Note: DIMM sparing is not validated in the Single Channel Mode when Intel 5000P
Chipset.MCA.SCHDIMM is set.
5.3.4
Data Poisoning in Memory
Data Poisoning in memory is defined as all zeroes in the code word (32B0 except for
the least significant bytes being 0xFF00FF. The Intel 5000P Chipset MCH poisons a
memory location based on the events described in Table 5.5, “Memory Poisoned Table”
Table 5-5.
Memory Poisoning Table
Event
Correctable Error
UnCorrectable Error
Normal Memory
Read
Correct Data to be given register
Detects an Uncorrectable and logs a M9
error (Non-aliased uncorrectable non-
mirrored demand data ECC error)
Intel 5000P Chipset MCH logs M17 error.
(Correctable Non-Mirrored demand data
ECC Error)
Re-Issue Read to Memory
Correct Data to be written back to
memory
If error persistent
1. Poison the response to requester and log.
2. Leave data untouched in memory location
Patrol Scrub
Correct Data to be written back to
memory and log M20 error. (Correctable uncorrectable patrol data ECC error).
patrolled data ECC error)
1. Log and Signal M12 Error (Non-Aliased
2: Leave data untouched in memory
location.
DIMM Spare Copy Correct Data to be written back to
memory and log M19 error. (Correctable
If error persistent
1. Log and Signal M11 Error (Non Aliased
uncorrectable re-silver or spare copy data
ECC error).
re-silver or spare copy data ECC error)
2: Poison Location in DIMM Spare
Mirror Copy
Correct Data to be written to new
memory and log M19 error. (Correctable error. (Non-aliased uncorrectable re-silver or
re-silver or spare copy data ECC error)
Re-use Read to memory and signal a M11
spare copy data ECC error).
If error persistent
1. Poison the new memory image.
5.3.5
Patrol Scrubbing
To enable this function, the MC.SCRBEN configuration bit must be set. The scrub unit starts at DIMM Rank
0 / Address 0 upon reset. Every 16k core cycles the unit will scrub one cache line and then increment the
address one cache line provided that back pressure or other internal dependencies (queueing, conflicts etc) do
not prolong the issuing of these transactions to FB-DIMM. Using this method, roughly 64GBytes of memory
behind the Intel 5000P Chipset MCH can be completely scrubbed every day (estimate). Error logs include
RAS/CAS/BANK/RANK. Patrol scrub writes hit both branches in mirrored mode (when MC.MIRROR is
set). Normally, one branch is scrubbed in entirety before proceeding to the other branch. In the instance of a
fail-down to non-redundant operation that off-lines the branch that was being scrubbed, the scrub pointer
merely migrates to the other branch without being cleared. In this unique instance, the scrub cycles for that
branch is incomplete.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
5.3.6
Demand Scrubbing
To enable this function, the MC.DEMSEN configuration bit must be set. Correctable read
data will be corrected to the requestor and scrubbed in memory. This adds an extra
cycle of latency to accomplish the correction. Error logs include RAS/CAS/BANK/RANK.
Demand scrubbing is not available in mirrored mode (when MC.MIRROR is set) to
simplify the design. If a correctable error is encountered, the data is corrected and sent
to the requestor at the cost of one extra cycle of latency. The probability of soft errors
due to alpha rays affecting multiple x4/x8 devices is low. However, patrol scrubbing
when enabled in the Intel 5000P Chipset MCH for the Mirrored mode will clean up all
correctable errors in the memory running in the background and runs twice as fast.
There is no incurred RAS benefit by enforcing demand scrubbing in mirrored mode with
the exception of the error logging. Demand scrubbing does not help in failed ECC case
(uncorrectable errors). That is, If the data read is uncorrectable from the bad branch,
then the golden data needs to be retrieved from the other mirrored branch (copy) at
the cost of additional FB-DIMM reset, link training and DDR protocol rules. The failed
branch is offlined and needs to be replaced for mirroring to continue.
5.3.7
x8 Correction
5.3.7.1
Normal
This correction mode is in effect when the MC.SCRBALGO configuration bit is cleared.
An erroneous read will be logged. If the ECC was correctable, it is corrected (scrubbed)
in memory. A conflicting read or write request pending issue will be held until the scrub
is either completed or aborted because it was uncorrectable.
5.3.7.2
Enhanced
This correction mode is in effect when the MC.SCRBALGO configuration bit is set and
software has initialized the MC.BADRAMTH to a non-zero value.
• Maintain 4-bit saturating counters per rank in the BADCNT configuration registers.
Floor at zero. Saturate at the value of the MC.BADRAMTH configuration register field.
Increment on correctable errors on both symbols of a x8 device and Northbound CRC
OK. Decrement upon completion of the number of patrol scrub cycles through the
entire memory specified by the MC.BADRAMTH configuration register field. A sufficient
resolution of this period is three patrol scrub cycles through all memory.
• Maintain five-bit bad-device marks per rank in the BADRAM(A/B) configuration
registers.
Upon incrementing BADCNT to saturation, then mark the bad devices in the
BADRAM(A/B) configuration registers.
• A correctable ECC in a symbol other than that marked in the BADRAM(A/B)
configuration registers is an aliased uncorrectable read.
An erroneous read will be logged. If the read was correctable, it is corrected (scrubbed)
in memory. A conflicting read or write request remains pending until the scrub
succeeds or is dropped. A failed scrub is replayed once, resulting in success or a drop.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
315
Functional Description
5.3.8
Single Device Data Correction (SDDC) Support
The Intel 5000X chipset MCH employs a single device data correction (SDDC)
algorithm for the memory subsystem that will recover from a x4/x8 component failure.
The chip disable is a 32-byte two-phase code. SDDC is also supported for x4 devices.
In addition the MCH supports demand and patrol scrubbing.
A scrub corrects a correctable error in memory. A four-byte ECC is attached to each 32-
byte “payload”. An error is detected when the ECC calculated from the payload
mismatches the ECC read from memory. The error is corrected by modifying either the
ECC or the payload or both and writing both the ECC and payload back to memory.
Only one demand or patrol scrub can be in process at a time.
The attributes of the SDDC code are as follows:
• Two Phase Code over 32 bytes of data.
• 100% Correction for all single x4 or x8 component failures.
• 100% Detection of all double x4 component failures.
• Detection Characteristics for x8 double device errors are provided in the Table 5-6
Table 5-6.
x8 Double Device Detection Characteristics
Overall coverage - 99.986%
Double bit errors - 100%
Double wire faults - 100%
Wire plus single bit - 100%
Device plus single - 99.99999%
Device plus wire - 99.99998%
Device plus equal/phase - 99.9998%
Equal/phase plus equal/phase - 100%
To increase the detection coverage of a (x8 device failure + SBE), that is, to avoid silent
data corruption in the event of a particle induced error while correcting for a failed
device, the Intel 5000X chipset MCH MCH provides the following features:
• Each rank will have an encoded value of the “failed” x8 component or pair of x4
components.
• If for any given rank, the Intel 5000X chipset MCH MCH detects a correctable error
with a weight >1 and the “corrected” symbol does not match the “failed”
component then the Intel 5000X chipset MCH MCH will assume that the error is
multi-bit uncorrectable error and signal a “fatal error”.
5.3.9
FB-DIMM Memory Configuration Mechanism
Before any cycles to the memory interface can be supported, the MCH DRAM registers
must be initialized. The MCH must be configured for operation with the installed
memory types. Detection of memory type and size is accomplished via the 4 Serial
Presents Detect (System Management Bus) interfaces on the MCH (SMBus 1, 2, 3 and
4). The SMBus interfaces are two-wire buses are used to extract the DRAM type and
size information from the Serial Presence Detect port on the DIMMs.
FB-DIMMs contain a 6-pin Serial Presence Detect interface, which includes SCL (serial
clock), SDA (serial data), and SA[3:0] (serial address). Devices on the SMBus bus have
a 7-bit address. For the DIMMs, the upper three bits are fixed at 101. The lower four
bits are strapped via the SA[3:0] pins. SCL and SDA are connected to the respective
SPDxSMBDATA, SPDxSMBCLK pins on the MCH, see Figure 5-8.
®
316
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
The Intel 5000X chipset MCH MCH integrates a 100KHz SPD controller to access the
DIMM SPD EEPROM’s. There are four SPD ports. SPD0SMBDATA, and SPD0SMBCLK are
defined for channel 0; SPD1SMBDATA, and SPD1SMBCLK are defined for channel 1;
SPD2SMBDATA, and SPD2SMBCLK are defined for channel 2; and SPD3SMBDATA, and
SPD3SMBCLK are defined for channel 3. There can be a maximum of eight SPD
EEPROM’s associated with each SPD bus. Therefore, the SPD interface is wired as
indicated in Figure 5-8.
Figure 5-8. Connection of DIMM Serial I/O Signals
C H A N N E L
0
C H A N N E L
1
C H A N N E L
2
C H A N N E L
3
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0 S A 0
S A 1 S A 1
S A 2 S A 2
S L O T
S L O T
S L O T
S L O T
3
2
1
0
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
D IM M
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0 S A 0
S A 1 S A 1
S A 2 S A 2
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0 S A 0
S A 1 S A 1
S A 2 S A 2
S A 0
S A 1
S A 2
S A 0
S A 1
S A 2
S A 0 S A 0
S A 1 S A 1
S A 2 S A 2
S C L 1 / S C L 2 /
S D A 1
S D A 2
S C L 3 /
S D A 3
S C L 0 /
S D A 0
In te l® 5 0 0 0 P
C h ip s e t
Board layout must map chip selects to SPD Slave Addresses as shown in Table 5-7. The
slave address is written to the SPDCMD configuration register (see Section 3.9.26.2).
Table 5-7.
SPD Addressing
FB-DIMM
Channel
SPD Bus
SLOT Slave Address
0
0
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
1
2
3
1
2
3
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
317
Functional Description
5.3.10
FB-DIMM Memory Failure Isolation Mechanisms
Since the Intel 5000X chipset MCH does not operate FB-DIMM in fail-over mode, CRC
accompanies Northbound data. Successful transaction completion is signalled by the
absence of alerts within a read round-trip. Bad CRC accompanies alerts. Alerts preempt
read data. Detection of corrupted CRC or corrupted write acknowledge (idle) will
initiate an FB-DIMM fast reset followed by a retry of all commands since completion of
the last successful transaction. A consecutive CRC/ack failure on the same transaction
is fatal.
5.3.10.1
5.3.10.2
FB-DIMM Configuration Read Error
An erroneous configuration read return will be master aborted and return all 1’s. It will
not be retried.
DIMM Failure Isolation
The failing DIMM may be isolated using information contained in several registers. ECC
error flag bits are recorded in register FERR_NF_FBD, Section 3.9.22.3. This register
records various error sources related to FB-DIMM memory transactions. When an error
occurs the channel/branch information is recorded in the FBDChan_indx field.
The FBDChan_indx is a two bit field that records branch ECC errors. ECC errors are
reported on a per branch basis (the LSB of this field has no relevance for ECC errors).
For ECC errors the possible values for this field are:
FBDChan_indx = 0 Branch 0 ECC error
FBDChan_indx = 2 Branch 1 ECC error
Once the branch is determined the failing DIMM is determined, the rank and DIMM is
determined from the RECMEMA.RANK and REDMEMB.ECC_Locator fields. The
ECC_Locator indicates which x8 SDRAM device (or pair of adjacent x4 devices) caused
the error. If any of the bits [8:0] is set, a DIMM on the even channel caused the error.
If any of the bits [17:9] is set, a DIMM on the odd channel caused the error. See
Table 3-49.
For uncorrectable errors the NRECMEMA.RANK register is used to identify the failing
DIMM pair (lockstep channels).
After a mirrored branch is taken off line, BIOS can execute MemBIST routines on the
suspect DIMM-Pair to reproduce failures. This can be performed out-of-band using the
SPD (SM bus) interface.
5.3.10.3
ECC Code
When branches operate in dual-channel mode, the MCH supports the 18 device DRAM
failure correction code (SDDC aka SECC) option for FB-DIMM. As applied by Intel
5000P Chipset, this code has the following properties:
• Correction of any x4 or x8 DRAM device failure
• Detection of 99.986% of all single bit failures that occur in addition to a x8 DRAM
failure. The Intel 5000X chipset MCH will detect a series of failures on a specific
DRAM and use this information in addition to the information provided by the code
to achieve 100% detection of these cases.
• Detection of all 2 wire faults on the DIMMs. This includes any pair of single bit
errors.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
• Detection of all permutations of 2 x4 DRAM failures.
When the branch operates in single-channel/single-DIMM mode, the Intel 5000P
Chipset MCH employs x8 SDDC as in the dual channel case. However, in this case, the
ECC RAS feature set is limited for the single DIMM memory subsystem. In the single
DIMM mode (for example, nine x8 devices), the SDDC cannot correct single wire fault
(stuck-at) errors or permanent full device errors. This is because the error correction
capability in the SDDC is limited to adjacent symbol errors on a 16-bit boundary and in
the single DIMM mode with a Burst Length of 8, there are 4 transfers of 8B to form a
32Bcode word. Hence a single wire failure in the same device is replicated across all 4
symbols hampering the error correction. The SDDC can detect most x4/x8 DRAM
failures but it can only correct adjacent symbol errors that occur within a 16-bit
boundary of each code word.
5.3.10.4
Inbound ECC Code Layout for Dual-Channel Branches
The code is systematic: that is, the data is separated from the check-bits rather than all
being encoded together. It consists of 32 eight-bit data symbols (DS31-DS0) and four
eight-bit Check-bit Symbols (CS3-CS0). The code corrects any two adjacent symbols in
error. The symbols are arranged so that the data from every x8 DRAM is mapped to two
adjacent symbols, so any failure of the DRAM can be corrected.
Figure 5-9 illustrates the ECC code layout for branch 0. The figure shows how the
symbols are mapped on the FB-DIMM branch and to DRAM bits by the DIMM for a
transfer in which the critical 16 B is in the lower half of the code-word (A[4]=0). If the
upper portion of the code-word were transferred first, bits[7:4] of each symbol would
be transferred first on the DRAM interface and in the first six transfers on the FB-DIMM
channel. The layout for branch 1 is the same.
The bits of Data Symbol 0 (DS0) are traced from DRAM to FB-DIMM Northbound. The
same mapping of symbols to data and code bits applies to Southbound data. The lower
nibble (DS0A) consists of DS0[3:0] the upper nibble (DS0B) consists of DS0[7:4]. On
the DRAM interface, DS0 is expanded to show that it occupies 4 DRAM lines for two
transfers. DS0[3:0] appears in the first transfer. DS0[7:4] appear in the second
transfer. DS0 and DS1 are the adjacent symbols that protect the eight lines from the
first DRAM on DIMM0. The same DS0 is shown expanded on the Northbound FB-DIMM
interface where it occupies the FD0NB[P:N][0] signal. DS0 and DS1 cover all transfers
on FD0NB[P:N][0] (even though FD0NB[P:N][0] does not cover all of DS1).
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
319
Functional Description
Figure 5-9. Code Layout for Single-Channel Branches
x8 x8 x8 x8 x8 x8 x8 x8 x8
CB
[7:0]
DQ[71:0]
DRAMs
DIMMChannel 0
D D D D D D
C C
S S
1 0
A A
D D D D D D D D D D
S S S S S S S S S S
9 8 7 6 5 4 3 2 1 0
A A A A A A A A A A
S S S S S S
1 1 1 1 1 1
5 4 3 2 1 0
A A A A A A
D D D D D D
S S S S S S
1 1 1 1 1 1
5 4 3 2 1 0
B B B B B B
Transfer 0
Transfer 1
Transfer 0
C C
S S
1 0
B B
D D D D D D D D D D
S S S S S S S S S S
9 8 7 6 5 4 3 2 1 0
B B B B B B B B B B
DS0 DS0 DS0
DS0
[0]
[3]
[2]
[1]
D D
S S
3 3
1 0
A A
D D
S S
3 3
1 0
B B
D D D D D D D D
D D D D D D
C C
S S
3 2
A A
S S
1 1
S S S S S S S S S S S S
2 2 2 2 2 2 2 2 2 2 1 1
3 2 1 0 9 8 7 6
A A A A A A A A
D D D D D D D D
S S S S S S S S
2 2 2 2 1 1 1 1
3 2 1 0 9 8 7 6
B B B B B B B B
9 8 7 6 5 4
A A A A A A
D D D D D D
S S S S S S
2 2 2 2 2 2
9 8 7 6 5 4
B B B B B B
DS0 DS0
[6] [5]
DS0
[7]
DS0
[4]
C C
S S
3 2
B B
Transfer 1
D[131] D[130] D[129] D[128]
DQ[3] DQ[2] DQ[1] DQ[0]
DRAMpins
Data
Bits
TRANSFER
D[0]
FD0NBy[0]
C D D D
D
S
D
S
D
S
D
S
DS0
[0]
0
1
2
3
4
5
6
7
8
D
S
9
D
S
6
D
S
3
D
S
0
D[1]
D[2]
D[3]
S
1
5
A
S
1
2
A
S
S
DS0
[1]
D
S
8
D
S
5
D
S
2
C
S
1
D
S
1
4
A
D
S
1
1
A
A
A
A
A
1
3
A
1
0
A
DS0
[2]
0
A
7
A
4
A
1
A
A
A
A
A
Packet 0
C D D D
D
S
D
S
D
S
D
S
DS0
[3]
D[128]
D[129]
D
S
9
D
S
6
D
S
3
D
S
0
S
1
5
B
S
1
2
B
S
S
DS1
[0]
D
S
8
D
S
5
D
S
2
C
S
1
D
S
1
4
B
D
S
1
1
B
B
B
B
B
9
1
D[130]
D[131]
1
3
B
1
0
B
DS1
[1]
0
B
7
B
4
B
1
B
0
1
B
B
B
B
1
0
DS0
[4]
C D D D D D D D D D D D
S
3
1
A
S
2
8
A
S
2
5
A
S
2
2
A
S
1
9
A
S
1
6
A
1
2
3
4
5
6
7
8
S
S
S
S
S
S
DS0
[5]
D[n+2]
C
S
3
D
S
3
0
A
D
S
2
7
A
D
S
2
4
A
D
S
2
1
A
D
S
1
8
A
2
9
A
2
6
A
2
3
A
2
0
A
1
7
A
DS0
[6]
2
A
D[n+3]
A
Packet 1
DS0
[7]
C D D D D D D D D D D D
S
3
1
B
S
2
8
B
S
2
5
B
S
2
2
B
S
1
9
B
S
1
6
B
S
S
S
S
S
S
DS1
[4]
C
S
3
D
S
3
0
B
D
S
2
7
B
D
S
2
4
B
D
S
2
1
B
D
S
1
8
B
9
1
FBDChannel 0
2
9
B
2
6
B
2
3
B
2
0
B
1
7
B
DS1
[5]
2
B
0
D[n]
1
B
1
F
D
0
N
B
y
F F
D D
0 0
N N
B B
y y
1 1
1 0
F F F F F F F F F F
D D D D D D D D D D
0 0 0 0 0 0 0 0 0 0
N N N N N N N N N N
B B B B B B B B B B
y y y y y y y y y y
9 8 7 6 5 4 3 2 1 0
D[n+1]
FBD
Signals
FBD
Signal
y=[P:N]
0
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
Figure 5-10. Code Layout for Dual-Channel Branches
x8 x8 x8 x8 x8 x8 x8 x8 x8
x8 x8 x8 x8 x8 x8 x8 x8 x8
CB
CB
[7:0]
DQ[71:0]
[7:0]
DQ[71:0]
DRAMs
DIMMChannel 1
DIMMChannel 0
D D D D D D D D D D D D D D D D
S S S S S S S S S S S S S S S S
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
D D D D D D
C C
S S
3 2
A A
C C
S S
1 0
A A
D D D D D D D D D D
S S S S S S S S S S
9 8 7 6 5 4 3 2 1 0
A A A A A A A A A A
S S S S S S
1 1 1 1 1 1
5 4 3 2 1 0
A A A A A A
Transfer 0
Transfer 1
A A A A A A A A A A A A A A A A
D D D D D D D D D D D D D D D D
S S S S S S S S S S S S S S S S
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1
D D D D D D
S S S S S S
1 1 1 1 1 1
5 4 3 2 1 0
B B B B B B
C C
S S
3 2
C C
S S
1 0
B B
D D D D D D D D D D
S S S S S S S S S S
9 8 7 6 5 4 3 2 1 0
B B B B B B B B B B
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
B B
B B B B B B B B B B B B B B B B
DS0 DS0 DS0 DS0
[3]
[2]
[1]
[0]
D[3]
D[2]
D[1]
D[0]
T
R
A
N
S
F
Data
Bits
E
R
D[0]
D[1]
FD0NBy[0]
DS0 DS0 DS0 DS0
[7] [6] [5] [4]
DS0
[0]
C DS D DS D DS D DS D DS D DS C DS D DS
D
S
D
S
D
S
D
S
0
1
2
3
4
5
6
7
8
D
S
9
D
S
6
D
S
3
D
S
0
A
D[131] D[130] D[129] D[128]
3
1
C A
S
2
2
8
A
2
5
A
2
2
A
1
9
A
1
6
A
1
5
C A
S
0
1
2
A
S
S
S
S
S
S
S
S
DS0
[1]
D
S
8
D
S
5
D
S
2
D[2]
D
S
3
0
A
D
S
2
7
A
D
S
2
4
A
D
S
2
1
A
D
S
1
8
A
D
S
1
4
A
D
S
1
1
A
A
A
A
DS0
[2]
2
9
A
2
6
A
2
3
A
2
0
A
1
7
A
1
3
A
1
0
A
DQ[3] DQ[2] DQ[1] DQ[0]
DRAMpins
7
A
4
A
1
A
3
A
1
A
D[3]
A
A
A
A
A
Packet
DS0
[3]
C DS D DS D DS D DS D DS D DS C DS D DS
D
S
D
S
D
S
D
S
D
S
9
D
S
6
D
S
3
D
S
0
D[128]
D[129]
D[130]
D[131]
3
1
C B
S
2
2
8
B
2
5
B
2
2
B
1
9
B
1
6
B
1
5
C B
S
0
1
2
B
S
S
S
S
S
S
S
S
DS1
[0]
D
S
8
D
S
5
D
S
2
D
S
3
0
B
D
S
2
7
B
D
S
2
4
B
D
S
2
1
B
D
S
1
8
B
D
S
1
4
B
D
S
1
1
B
B
B
B
B
9
1
DS1
[1]
2
9
B
2
6
B
2
3
B
2
0
B
1
7
B
1
3
B
1
0
B
7
B
4
B
1
B
3
B
1
B
0
1
B
B
B
B
B
1
DS0
[4]
F F
D D
1 1
N N
B B
y y
1 1
1 0
F F
D D
0 0
N N
B B
y y
1 1
1 0
F F F F F F F F F F
D D D D D D D D D D
1 1 1 1 1 1 1 1 1 1
N N N N N N N N N N
B B B B B B B B B B
y y y y y y y y y y
9 8 7 6 5 4 3 2 1 0
F F F F F F F F F F
D D D D D D D D D D
0 0 0 0 0 0 0 0 0 0
N N N N N N N N N N
B B B B B B B B B B
y y y y y y y y y y
9 8 7 6 5 4 3 2 1 0
DS0
[5]
FBD
Signals
D[n+2]
DS0
[6]
y=[P:N]
D[n+3]
DS0
[7]
FBDBranch 0
DS1
[4]
DS1
[5]
D[n]
F
D
0
D[n+1]
FBD
Signal
N
B
y
0
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
321
Functional Description
5.3.10.5
ECC Code Layout for a Single-Channel Branch
The ninth byte of each burst on each DIMM contains the ECC bits for 8 bytes of data.
These nine bytes comprise a code word. There are eight code words in a cache line.
5.3.11
DDR2 Protocol
5.3.11.1
Posted CAS
Posted CAS timing is used.
5.3.11.2
Refresh
Regardless of the number of DIMMs installed, each rank will get a minimum of one
refresh every eight periods defined by the DRT.TREF configuration register field. The
refreshes cycle through all eight DIMM ranks.
The DIMM enters self-refresh mode during an FB-DIMM fast reset.
5.3.11.3
5.3.11.4
Access Size
All memory accesses are 64B.
Transfer Mode
Each DIMM is programmed to use a burst-length of 32 bytes (4 transfers) across the
channel. The Mode Register of each DIMM must be programmed for a burst length of 4,
and interleave mode.
5.3.11.5
Invalid and Unsupported DDR Transactions
The memory controller prevents cycle combinations leading to data interruption or
early termination. The memory controller prevents combinations of DDR commands
that create bus contention (that is, where multiple ranks would be required to drive
data simultaneously on a DIMM). The memory controller does not interrupt writes for
reads. A precharge command is provided, but early read or write termination due to
precharge is not supported.
5.3.12
Memory Thermal Management
The Intel 5000X chipset MCH supports FB-DIMM throttling and power management
through several mechanisms. The first mechanism forces power down of unused or
failed channels by setting the FB-DIMMHPC.State to Reset. This corresponds to the
Disable state in the FB-DIMM specification which holds the FB-DIMM channel in reset.
When in reset, the channel receivers and drivers are disabled.
The second method of power management utilizes an adaptive methodology to control
the number of activations (memory requests) sent to a FB-DIMM. This methodology is
composed of two components:
1. Activation throttling: This is composed of closed and open loop throttling
mechanisms to control the number of activations sent to FB-DIMM devices.
a. Closed loop thermal activation control is based on the temperature of the FB-
DIMM device. This mechanism becomes active when the FB-DIMM device
temperature exceeds programmed thresholds.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
b. Open loop global activate control becomes active when the number of activates
exceeds a programmed number with in a long window period.
2. Electrical throttling is used to prevent silent data corruption by limiting the number
of activates per rank with in a short sliding window period.
5.3.12.1
Closed Loop Thermal Activate Throttle Control
Closed loop thermal activate throttling control uses the temperature of the FB-DIMM
temperature sensor located in the AMB to determine when to throttle. FB-DIMM (AMB
temperature) is returned each sync packet. A thermal throttle period is defined as
window consisting of 1,344 cycles (42*32). The throttling logic in the memory
controller uses this information to limit the number of activates to any DIMM within a
throttling window based on temperature threshold crossing algorithm described later.
Every 42 frames the host controller is required to send a sync1 packet, which returns a
status packet from the AMBs along with temperature information. The AMB component
has two temperature threshold points, Tlow (programmed into the GB.TEMPLO register,
a.k.a. T1) and Tmid (programmed into the GB.TEMPMID register, a.k.a. T2), and the
current temperature of the GB with respect to these thresholds are returned in the
status packet. In addition, the sync and status packets guarantees that enough
transitions occur on each lane to maintain proper bit lock.
1. The sync packet may be dispatched by the MCH at an interval less than 42 frames
depending on the gear ratios, timing, circuit and other parameters. For example, in the
case of the core running at 266 MHz and the DDR2 clock at 333 MHz (4:5), the MCH
can send a SYNC every 32@266 MHz=40 DDR2 333 MHz clocks. This meets the
minimum 42 clock requirement of the FB-DIMM protocol for sync packet generation
frequency.
In each 42 frame period:
Frames 1-40 are used for normal DRAM traffic: The A slot for DRAM commands and
B/C for write data, as necessary.
Frame 41 is used for configuration commands: If a configuration read, it will appear
in the A slot. If a configuration write it will appear in B/C (which is the only choice).
Frame 42 is used by the Sync packet and occupies the A, B, and C slots.
FB-DIMM thermal information is returned in the Sync packet as an encoded 2 bit field.
The encoding of this field described in the following table.
Table 5-8.
AMB Thermal Status Bit Definitions
Thermal Trip: This field indicates various
S[2:1]
thermal conditions of the AMB as follows:
Below TEMPLO
00
01
10
11
Above TEMPLO
Above TEMPMID and falling
Above TEMPMID and rising
This data is a duplication of the contents of the AMB.FBDS0 register discussed in the
Gold Bridge Component External Design Specification. These 2 bits are returned for
each AMB during in the Status packet.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
323
Functional Description
The TEMPLO threshold is generally used to inform the host to accelerate refresh events.
The TEMPMID threshold is generally used to inform the host that a thermal limit has
been exceeded and that thermal throttling is needed.
There are separate counters associated with each of the 2 lockstep FB-DIMM pairs in a
given branch (one counter per FB-DIMM pair per branch). When any of the counters
reaches its limit (as specified by the THRTSTS.THRMTHRT register field for a given
branch), the entire branch is throttled until the end of the throttle window. No new
DRAM commands are issued to any of the DIMMs on the branch until the end of the
throttle window. If an activate has been issued to a bank, the follow on read or write
may be issued, including an additional page hit access if applicable, to allow the page
to close.
5.3.12.2
Sequence of Actions During Throttling
When throttling begins during a given throttling window, the following actions take
place:
1. Stop new DRAM commands
2. Wait “X” clocks for DRAM commands to complete. Where “X” is the worst case
delay as defined below
3. Assert CKE low
4. Wait for throttling window to expire
5. Just before end of activation throttle window (about 3 clocks before for the CKE
setup), Assert CKE high
Once the branch has been throttled, the memory controller sends a broadcast CKE for
each DIMM command to take the CKE low on all DIMMs of the branch. This command is
sent after the proper time has elapsed so that the outstanding transfers complete
properly on the DRAMs. When activation throttling starts, CKE must not go low on the
DRAMs until the last command has completed in the DRAMs. The worst case is an
activate immediately followed by a posted CAS. A fixed time from the last command is
used by the Intel 5000X chipset MCH corresponding to the worst case delay (X)
defined by
X = Max(worst_case_round_trip_delay, M ¥ TRFC)
⎧
⎨
⎩
1.25 if Core to FBD clock ratio is 5:4
Otherwise
M =
1
with a suitable guard band1 to protect any data loss. The TRFC parameter (Refresh to
Activate Command delay) is factored into the equation since a refresh could be just
underway when the last activate was about to be issued. The “1.25” scaling factor is to
account for the 5:4 gearing ratio required for a FSB frequency of (333 MHz) and FBD/
DDR clock frequency of (266MHz). The default scale factor used on platforms is 1 (FSB
(266 MHz) and FBD/DDR clocks (266 MHz)).
During the time that CKE is low, no DRAM commands should be sent on the channel.
However, Non-DRAM commands such as Configuration register and SYNC are required
to be sent during this period.
When the throttle window is about to expire, a CKE command is sent to take all CKEs
high. This must be done at least 3 clocks before the first command.
1. The worst case round trip delay is expected to be in the 10-20 clock range for a posted CAS
command and the Intel 5000X chipset MCH RTL can be microarchitected appropriately.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
5.3.12.3
CKE State Near End of Activation Throttling Window
If the throttling begins very close to the end of the window, then the assertion of CKE
low command would be delayed beyond the end of the throttle window. To prevent this
occurrence, the memory controller logic does not observe a throttle event in the last
few clocks of the window, or assert a CKE low command.
If the activation throttle is set to begin within Y clocks before the end of the window,
the memory controller skips the asserting CKE low step, where Y is X + 61 (and the
number “6” is derived from 3 clocks for the CKE low to high minimum, plus another 3
clocks for the CKE high until first command after the throttling window.
5.3.12.4
5.3.12.5
Refresh Handling During Throttling
The Intel 5000X chipset memory controller ensures that refreshes, which are lost
during the activation throttle period (possibly up to 2), are made up at the end of the
period. Double refresh rates to the DIMMs should be carried out when needed
regardless of the setting of the MC.THRMHUNT bit. This is particularly important for
open loop throttling when the temperature could rise beyond 85’C.
Throttling Parameters for Activation Throttling.
The current throttling parameters for each branch are stored in the THRMTHRT register
field defined in Section 3.9.3. All activation throttling parameters in the THRMTHRT
registers are 8-bits wide, and provide increments of 4 activations per throttle window
(1344 clocks). Three levels of throttling limits are defined.
• THRTLOW: A base throttling level that is applied when the temperature is in the low
range (below Tlow) and the THRTSTS.GBLTHRT*2 bit is not set by the Global
Throttling Window logic. See Section 3.9.4
• THRTMID: A mid level throttling level that is applied when the temperature is in the
middle range (above Tlow but below Tmid) or the THRSTS.GBLTHRT* bit is set by the
Global Throttling Window logic. See Section 3.9.5
• THRTHI: The highest level of throttling. When MC.THRMODE=1, this level is applied
whenever the temperature is above Tmid. When MC.THRMODE=0, this level is the
ceiling of the hunting algorithm of the closed loop throttling. The temperature being
above Tmid has priority over the Global Throttling Window throttling (the higher
throttling level takes precedence). See Section 3.9.6
The MC.THRMHUNT bit must be enabled for the temperature to have any influence on
the throttle parameters. If MC.THRMHUNT=0, only the GBLTHRT bit from the Global
Throttle Window, when enabled can change the THRMTHRT register field. Refer to
Figure 5-11 and Figure 5-12 for the thermal envelopes.
1. Intel 5000X chipset MC design needs to adjust the value based on the latest JEDEC
recommendation for CKE low to high transition.
2. GBLTHRT* is an internal combinatorial signal before it is latched in the THRSTS.GBLTHRT register
field to enable the open loop throttling logic to use the latest value of the signal.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
325
Functional Description
Figure 5-11. Thermal Throttling with THRMHUNT=1
THRMTHRT
GBLTHRT=0
THRTLOW
THRTMID
GBLTHRT=1
THRMODE=0
Temp. increasing
THRTHI
Temp. decreasing
THRMODE=1
Tlow
Tmid
Temperature
THRMHUNT = 1
Figure 5-12. Thermal Throttling with THRMHUNT=0
THRMTHRT
GBLTHRT=0
THRTLOW
THRTMID
GBLTHRT=1
THRTHI
Tlow
Tmid
Temperature
THRMHUNT = 0
5.3.12.6
Closed Loop Activation Throttling Policy
Individual DIMMs flag their thermal state in the FB-DIMM status return. When the
MC.THRMHUNT configuration bit is set, memory reads and writes (summed together)
will be regulated on a per-DIMM-pair basis according to the following algorithm
described in Figure 5-13. Note that the Intel 5000X chipset MCH provides a greater
degree of thermal throttling if there is a sudden temperature spike between from Tlow
to Tmid by setting the THRMTHRT register to THRTMID as a starting point when
MC.THRMODE=0. Once this point is reached, if temperature increased further during
the next global window, then THRMTHRT register will be adjusted by the equation
THRMTHRT= MAX(THRMTHRT -2, THRTHI). See staircase effect in Figure 5-11. If
temperature decreased but is still greater than Tmid, then the THRMTHRT will retain its
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
last value. This provides some degree of hysteresis control to allow the DIMMs to cool
further before THRMTHRT jumps back to a larger number (i.e less throttling) at the
junction when the temperature reached Tmid. Refer to the dotted line in Figure 5-11.
This scheme helps in reducing the thermal power by limiting the number of activates.
See Figure 5-13 for further details.
1. Staircase Conditioning [THRTCTRL.THRMODE=0]: This method is employed when
THRTCTRL.THRMODE=0 and temperature crosses above Tmid . The THRMTHRT
registries capped to THRTMID (starting point) and it uses a linearly increasing (less
aggressive) throttling algorithm to reduce activations and balance performance and
power envelope when temperature rises and falls around Tmid point. Once
THRTMID is reached, if temperature increases further during the next global
window, then THRMTHRT register will be adjusted by the equation THRMTHRT=
MAX(THRMTHRT -2, THRTHI). This produces the staircase effect as shown in Figure
5-10, “Thermal Throttling with THRMHUNT=1” on page 387. If temperature
decreases subsequently but is still greater than Tmid, then the THRMTHRT will
retain its last value. This provides some degree of hysteresis control to allow the
DIMMs to cool further before THRMTHRT jumps back to a larger number (i.e less
throttling) at the junction when the temperature reached Tmid. Refer to the dotted
line in Figure 5-10, “Thermal Throttling with THRMHUNT=1” on page 387. This
scheme helps in reducing the thermal power by limiting the number of activates.
See Figure 5-12, “Thermal throttling Activation Algorithm” on page 389 for further
details.
2. Step Conditioning (brute force) [THRTCTRL.THRMODE=1]: This method is
employed when THRTCTRL.THRMODE=1 and temperature crosses Tmid . The
THRMTHRT register is capped to THRTHI and it provides a greater degree of
throttling by allowing fewer activates to the memory allowing the DIMM to cool
down quicker but at the expense of performance. This can be used to control
sudden temperature surges that moves the envelope from below Tlow to above
Tmid. and stays there for a long period.
During the global window, the Intel 5000P Chipset MCH will broadcast one
configuration write to the DIMMs AMB.UPDATED registers. This write will not be re-
played or re-sent.
Note:
A channel fault could drop an AMB.UPDATED write. If the temperature increased during
the previous global window, but had not actually increased during the current global
window, then THRMTHRT will un-necessarily decrease. If the temperature had not
increased during the previous global window, but had actually increased during the
current global window, then THRMTRHT will remain unresponsive to the temperature
increase for one global throttling window. The situation will rectify itself in the next
global throttling window.
1. If there is a sudden temperature spike between from below Tlow to above Tmid by
setting the THRMTHRT register to THRTMID as a starting point when
THRTCTRL.THRMODE=0. If temperature rose from above Tlow to above Tmid, then
the THRMTHRT will use THRTMID value if THRTCTRL.THRMODE=0; otherwise it will
use THRTHI if THRTCTRL.THRMODE=1. See the right side of Table 5-8 on page 390
for the various modes.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
327
Functional Description
Figure 5-13. Thermal Throttling Activation Algorithm
T H R M T H R T
= T H R T L O W ( I n it ia liz e t o b a s e - le v e l A c t iv a t io n s )
if ( G lo b a l_ T i m e r e x p ir e s )
{
if (M C .G T W _ M O D E = = 1 )
// C h o o s e w in d o w s iz e b a s e d o n m o d e s e t t in g
// V a lid a t io n D e b u g M o d e
{
{
G lo b a l_ T im e r = 4 * 1 3 4 4
&
}
e ls e
G lo b a l_ T i m e r = 0 .6 5 6 2 5 * 2 ^ 2 5 = 1 6 3 8 4 * 1 3 4 4
// m a k e g lo b a l t h r o t t lin g w in d o w a n in t e g r a l m u lt i p le o f t h e c lo s e d lo o p w in d o w
}
if ( T H R T C T R L .T H R M H U N T = = 1 )
{
f o r ( e a c h D I M M - p a ir [ m ] o n e a c h b r a n c h [ n ] ) /* m = 0 ..3 , n = 0 ..1 * /
{
if ( t e m p e r a t u r e o f a n y D I M M [ i] > = T m id ) /* 0 < = i < = 3 * /
if ( T H R T C T R L .T H R M O D E = = 0 )
if ( T H R M T H R T T H R T M I D )
/* T h is w ill c a p t h e s t a r t p o in t t o T H R T M I D if t h e r e is a * /
{
>
{
/* s p ik e in t h e G B T e m p e r a t u r e f r o m T lo w t o T m id
/* P r o v id e s b e t t e r t h r o t t lin g a n d c o n t r o l * /
& b e y o n d * /
T H R M T H R T
= T H R T M I D
}
e ls e
{
/* S ta ir c a s e r o ll d o w n m a y h a p p e n f o r s u b s e q u e n t s a m p lin g s
if (t h e t e m p e r a t u r e o f a n y D I M M w h ic h is a b o v e T m id , in c r e a s e d )
{
T H R M T H R T
} /* O t h e r w is e r e t a in la s t T H R M T H R T v a lu e * /
} /* e n d o f T H R M T H R T T H R T M I D c h e c k * /
= m a x ( T H R M T H R T - 2 , T H R T H I )
>
}
e ls e
{
T H R M T H R T
= T H R T H I
}
/* e n d o f T H R M O D E = = 0 c h e c k * /
}
e ls e if ( (t e m p e r a t u r e o f a n y D I M M [ i] > = T lo w [ i] )
& & ( t e m p e r a t u r e o f a ll D I M M ’ s [ i]
<
T m i d [ i] ) )
{
}
T H R M T H R T = T H R T M I D
e ls e if ( t e m p e r a t u r e o f a ll D I M M ’ s [ i] < T lo w [ i] ))
{
if ( G B L T H R T = = 1 )
{
}
T H R M T H R T
=
T H R T M I D
T H R T L O W
e ls e
{
}
T H R M T H R T
=
}
}
}
e ls e
{
if ( G B L T H R T = = 1 )
{
T H R M T H R T
=
T H R T M I D
}
e ls e
{
T H R M T H R T
= T H R T L O W
}
}
}
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
Table 5-9.
FB_DIMM Bandwidth as a Function of Closed Loop Thermal Throttling
THRMTHRT
% BW
BW per
sys BW, 1 sys BW 2 sys BW 4
Reg Value Activates
0 unlimited
allowed
DIMM GB/s DIMM/ch DIMM/ch DIMM/ch
1
2
3
4
5
6
7
8
4
8
12
16
20
24
28
32
48
0.60%
1.19%
1.79%
2.38%
2.98%
3.57%
4.17%
4.76%
7.14%
0.03
0.06
0.10
0.13
0.16
0.19
0.22
0.25
0.38
0.51
0.63
0.76
0.89
1.02
1.14
1.27
1.40
1.52
2.03
2.29
2.54
3.05
4.06
4.57
5.08
5.33
0.13
0.25
0.38
0.51
0.63
0.76
0.89
1.02
1.52
2.03
2.54
3.05
3.56
4.06
4.57
5.08
5.59
6.10
8.13
9.14
10.16
12.19
16.25
18.29
20.32
21.33
0.25
0.51
0.76
1.02
1.27
1.52
1.78
2.03
3.05
4.06
5.08
6.10
7.11
8.13
9.14
10.16
11.17
12.19
16.25
18.29
20.32
0.51
1.02
1.52
2.03
2.54
3.05
3.56
4.06
6.10
12
16
20
24
28
32
36
40
44
48
64
72
80
96
128
144
160
168
64
80
96
9.52%
8.13
11.90%
14.29%
16.67%
19.05%
21.43%
23.81%
26.19%
28.57%
38.10%
42.86%
47.62%
57.14%
76.19%
85.71%
95.24%
100.00%
10.16
12.19
14.22
16.25
18.29
20.32
112
128
144
160
176
192
256
288
320
384
512
576
640
672
5.3.12.7
Open Loop Global Throttling
In the open loop global window throttling scheme, the number of activates per DIMM
pair per branch is counted for a larger time period called the “Global Throttling
window”. The Global throttling window is chosen as an integral multiple of the thermal
throttling window of 1344 clocks for maintaining a simpler implementation. Under
normal operating conditions, the Global Throttling Window is 0.65625*225clocks in
duration and this translates to 16384*1344 clocks (~66.06 ms) for DDR2667. However,
for purposes of validation and debug, the global throttling window can be reduced to a
smaller duration, 4*1344 cycles1 (16.128 μs) for DDR2667 and this is controlled
through the GTW_MODE register bit defined in Section 3.9.1. The global throttling
window prevents shorts peaks in bandwidth from causing closed loop activation
throttling when there has not been sufficient DRAM activity over a long period of time
to warrant throttling. It is in effect a low pass filter on the closed loop activation
throttling.
1. If MC.GTW_MODE=1, the Intel 5000X chipset MCH will use the 4*1344 cycle duration for the
global throttling window.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
329
Functional Description
During this Global throttling window, the number of activates is counted for each DIMM
pair per branch (24-bit counters are required). If the number exceeds the number
indicated by the GBLACT.GBLACTLM register defined in Section 3.9.2, then the
THRTSTS[1:0].GBLTHRT bit is set for the respective branch, causing the activation
throttling logic to use the THRTMID register. The THRTSTS[1:0].GBLTHRT will remain
active until 16 (or 2) global throttling windows in a row have gone by without any DIMM
exceeding the GBLACT.
At the end of the 16 (or 2) global throttling windows, if no DIMM pair activates exceed
the GBLACT.GBLACTLM value, then the MC indicates the end of the period by clearing
the THRTSTS[1:0].GBLTHRT register field.
If part way through the count of 16 (or 2) global throttling windows, the
GBLACT.GBLACTLM is again exceeded within one Global Throttle Window, the counter
gets reset and it will once again count 16 (or 2) global throttle windows throttling at the
THRTMID level.
5.3.12.8
Global Activation Throttling Software Usage
In practice, the throttle settings for THRTMID are likely to be set by software such that
the memory controller throttle logic will actually prevent the GBLACT limit from being
exceeded and the result will often be that such that THRTLOW is used for a Global
Throttle Window, at which time, the GBLACT.GBLACTLM is exceeded, causing the MC s
to use a larger throttling period THRTMID for 16 (or 2) global1 windows. During each of
those global windows, GBLACT limit is not exceeded, because the throttling will prevent
it from being exceeded. After 16 (or 2) global2 throttling windows, it switches back to
THRTLOW, and on the next global window GBLACT is again exceeded, causing another
16 (or 2) windows2. Hence, we can get a cumulative pattern of 16,1,16,1 (or 2,1,2,1)
global2 throttling windows and this prevents excessive heat dissipation in the FB-
DIMMs by prolonging the throttle period.
Note:
It should be mentioned that the open and closed loop throttling control policies
implemented on the Intel 5000X chipset MCH uses the internal core clocks for the
calculating the windows and not the DDR clocks. Thus any software/BIOS should take
this into account for manipulating the THRMTHRT registers when dealing with different
FB-DIMM technologies and speeds.
5.3.12.9
Dynamic Update of Thermal Throttling Registers
In general, the Intel 5000P Chipset registers should not updated dynamically during
runtime as it may interfere with the internal state machines not designed exclusively
for such changes and could result in a system hang/lock up. This requirement is
relaxed (subject to validation) for the Intel 5000P Chipset thermal throttling registers
where it is desirable for BIOS or special OEM software in BMC to exercise dynamic
control on throttling for open/closed loop algorithm implementation. The following
examples are some of the potential areas of this usage model where dynamic change is
needed to balance performance and acoustic levels in the system
Fan control for CPU temperature related system acoustics or other BMC related
operations. Limit hacker activity by increasing memory throttling via throttle register
updates to condition the system based on some event (excessive bandwidth or CPU
activity)
• Fan failure/breakdown. When this occurs, temperature conditioning can be
provided by reducing the activity level in the DIMMs to a certain threshold until the
failed fan can be repaired by the technician and service restored to normalcy.
1. The 2 window Global Throttling count will be chosen if MC.GTW_MODE=1.
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5.3.12.10 General Software Usage Assumptions
Under normal circumstances, it is expected that there is no change of throttling values
once it is configured by BIOS during boot. The external Fan control and the BIOS
settings of the OEM via BMC would ensure adequate cooling and maintain the DIMMs
within the prescribed tolerance limits of the TDP. However, situations such as thermal
virus or fan fail down condition might warrant the BIOS/SW to take preemptive action
in adjusting the throttling to say 40-70% of the normal mode before it is cleared. This
means that changes to throttling registers can happen at random intervals (infrequent)
and the platform should be able to tolerate any transients changes that may result
when the Intel 5000P Chipset is updated with the new throttle values. These
requirements are captured below.
5.3.12.11 Dynamic Change Operation Requirements for Open Loop Thermal
Thottling (OLTT)
The Intel 5000P Chipset Memory throttle control register affected by OLTT include
THRTMID (T2), THRTLOW (T1), GBLACT, and the THRTCTRL.THRMHUNT field.
(THRMHUNT=0 selects the open loop mode).
Each update to the above mentioned throttle register takes approximately 40 core
clocks in the configuration ring to complete.
Configuration register updates for throttling should be spaced out at approximately 80
core cycles apart. (2x guard band)
Only one CFC/CF8 or MMCFG configuration transaction is allowed at a time in the
system.
When the number of activates exceed the GBLACT.GBLACTLM in a global throttling
window, OLTT is entered and GBLTHRT is set by the Intel 5000P Chipset for 16
consecutive global throttling windows (irrespective of the new parameters) as
described in Section 5.3.12.7. Note that OLTT is NOT history-based algorithm. Hence if
software assigns new values to THRTLOW or THRMID values at some point in time, the
MC cluster will update the registers and use the new values for limiting the activates
immediately via THRMTHRT register for 16 consecutive global throttling windows. See
also Figure 5-13.
Software can update the throttling registers as frequently as it desires provided it
maintains the minimum spacing for the configuration writes and follows the other
guidelines as described above. It is also software’s responsibility for the fallout/
transient effect of the thermal control algorithm during such updates.
5.3.12.12 Dynamic Change Operation Requirements for Closed Loop Thermal
Thottling (CLTT)
In addition to all the conditions/requirements as stipulated in Section 5.3.12.11, the
closed loop throttling which uses GB temperature feedback to adjust the throttling
levels requires the following:
• Intel 5000P Chipset Registers that are affected by dynamic updated include
THRTMID (T2), THRTLOW (T1), THRTHI and THRTCTRL.THRMHUNT. (THRMHUNT=1
selects the closed loop mode)
• •When Temperature crosses Tmid, the CLTT switched to either the staircase function
(if THRMCTRL.THRTMODE=0) or the single step function (THRMCTRL.THRMODE=1)
as depicted in the right side of Figure 5-11. See also Figure 5-13. Note that CLTT is
NOT history-based algorithm except in the staircase mode which uses the old
value. In this case, the staircase function that always decrements the old value of
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THRMTHRT by 2. By design THRMTHRT can never be below THRTHI. If the new
THRTHI is greater than THRMTHRT, then the algorithm will reset THRMTHRT to
THRTHI & the staircase function can no longer be used since the bottom (aka
ceiling) of THRTHI has already been reached as defined by the following equation
extracted from Figure 5-13.
THRMTHRT = max(THRMTHRT - 2, THRTHI)
5.3.12.13 Disabling Closed/Open Loop Throttling
The following registers in the Intel 5000P Chipset can be initialized to disable throttling
(open/closed) if software desires to turn off throttling.
• THRTCTRL.THRMHIUNT = 0 /* This forces the Intel 5000P Chipset to ignore
temperature for closed loop */
• THRTHI.THRHILM = 0 (or 168d)
• THRTHI.THRMIDLM = 0 (or 168d)
• THRTLOW.THRLOWLM = 0 (or 168d)
• GBLACT.BLACTLM = 0 (or 168d) /*Above changes force Open loop throttling to be
off */
Table 5-10. Global Activation Throttling BW allocation as a function of GBLACTLM for a
16384**1344 window with MC.GTW_Mode=0 (normal)
GBLACT.
GBLACTLM Activates
0 unlimited
# of
% BW
allowed
BW per
DIMM GB/s DIMM/ch
sys BW, 1 sys BW 2 sys BW 4
DIMM/ch DIMM/ch
1
2
3
4
5
6
7
8
65536
131072
196608
262144
327680
393216
458752
524288
786432
1048576
1310720
1572864
1835008
2097152
2359296
2621440
2883584
3145728
4194304
4718592
5242880
6291456
8388608
9437184
0.60%
1.19%
1.79%
2.38%
2.98%
3.57%
4.17%
4.76%
7.14%
0.03
0.06
0.10
0.13
0.16
0.19
0.22
0.25
0.38
0.51
0.63
0.76
0.89
1.02
1.14
1.27
1.40
1.52
2.03
2.29
2.54
3.05
4.06
4.57
5.08
5.33
0.13
0.25
0.51
1.02
1.52
2.03
2.54
3.05
3.56
4.06
6.10
0.25
0.38
0.51
0.63
0.76
0.89
1.02
1.52
2.03
2.54
3.05
3.56
4.06
4.57
5.08
5.59
6.10
8.13
9.14
10.16
12.19
16.25
18.29
20.32
21.33
0.51
0.76
1.02
1.27
1.52
1.78
2.03
3.05
4.06
5.08
6.10
7.11
8.13
9.14
10.16
11.17
12.19
16.25
18.29
20.32
12
16
20
24
28
32
36
40
44
48
64
72
80
96
128
144
9.52%
8.13
11.90%
14.29%
16.67%
19.05%
21.43%
23.81%
26.19%
28.57%
38.10%
42.86%
47.62%
57.14%
76.19%
85.71%
95.24%
100.00%
10.16
12.19
14.22
16.25
18.29
20.32
160 10485760
168 11010048
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5.3.13
Electrical Throttling
Electrical throttling is a mechanism that limits the number of activates (burstiness)
within a very short time interval that would otherwise cause silent data corruption on
the DIMMs. Electrical throttling is enabled by setting the MTR.ETHROTTLE bit defined in
Section 3.9.23.7. These bits occur on a per DIMM pair basis per branch as to whether
electrical throttling should be used. It is assumed that both ranks within a DIMM would
be the same technology, and therefore does need not separate enable bits.
The per rank electrical throttling for FB-DIMM is 4 activates per 37.5ns window (JEDEC
consensus) and is summarized in Table 5-11 for various DIMM technologies.
Table 5-11. Electrical Throttle Window as a Function of DIMM Technology
Intel 5000P
1
Chipset MCH
Core: FB-DIMM
clock Ratio
Electrical Throttle Window (in core clocks per rank
per DIMM pair per branch)
DIMM Modes
DDR533
1:1
5:4
1:1
4:5
All
10
13
DDR667
13
13 (conservative)
b
DDR800
15
20
Conservative
(safe mode)
All
Notes:
1. Maximum 4 activates per rank is allowed within the window.
b. This is not a supported technology/nor a POR for Intel 5000P Chipset MCH and is tabulated for
information/illustrative purposes only.
The MC.ETHROT configuration register field limits the number of activations per sliding
electrical throttle window. The memory controller logic can implement the sliding
electrical throttle window with a 20-bit shift register per rank in each DIMM pair per
branch. This register records for the last 20 clocks, whether an activate was issued or
not to that rank. The number of activates can then be summed up from the state of the
shift register and compared with the respective limit as shown in Figure 5-11. If the
limit is reached, then further activates to the rank are blocked until the count falls
below the limit. The Electrical throttling logic in the MC masks off the end bits for the
DIMM technologies that require fewer clocks. As an example, if the DIMM technology
used is DDR667, then it can allow 4 activates within the last 13 clocks, the remaining 7
bits are masked (forced to 0) so they do not prevent activates.
5.4
Behavior on Overtemp State in AMB
Overtemperature occurring in an AMB may lead to data corruption in the .
• If EI is received by due to Overtemp detection in one of the AMBs, will capture
random data that most likely will be interpreted as having a CRC or uncorrectable
ECC error causing the link to go into a fast reset loop without data corruption.
• If the EI is interpreted as having both good CRC and good ECC, this could cause
data corruption until a bad CRC/ECC frame is detected and the link enters the fast
reset loop.
Note:
An all 0 frame fits this case of good CRC and ECC. This is just as unlikely as any other
random frame contents when interpreting EI.
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5.5
Interrupts
The Intel 5000X chipset supports both the XAPIC and traditional 8259 methods of
interrupt delivery. I/O interrupts and inter processor interrupts (IPIs) appear as write
or interrupt transactions in the system and are delivered to the target processor via the
processor bus. This chipset does not support the three-wire sideband bus (the APIC
bus) that is used by Pentium® and Pentium® Pro processors.
XAPIC interrupts that are generated from I/O will need to go through an I/O(x)APIC
device unless they support Message Signalled Interrupts (MSI). In this document, I/
O(x)APIC is an interrupt controller that is found in the Intel 631xESB/632xESB I/O
Controller Hub component of the chipset.
The legacy 8259 functionality is embedded in the Intel 631xESB/632xESB I/O
Controller Hub component. The Intel 5000X chipset will support inband 8259 interrupt
messages from PCI Express devices for boot. The chipset also supports the processor
generated “interrupt acknowledge” (for legacy 8259 interrupts), and “end-of-interrupt”
transactions (XAPIC).
Routing and delivery of interrupt messages and special transactions are described in
this section.
5.6
XAPIC Interrupt Message Delivery
The XAPIC interrupt architectures deliver interrupts to the target processor core via
interrupt messages presented on the front side bus. This section describes how
messages are routed and delivered in a Intel 5000X chipset system, this description
includes interrupt redirection.
Interrupts can originate from I/O(x)APIC devices or processors in the system.
Interrupts generated by I/O(x)APIC devices occur in the form of writes with a specific
address encoding. Interrupts generated by the processor appear on the processor bus
as transactions with a similar address encoding, and a specific encoding on the REQa/
REQb signals (REQa=01001, REQb=11100).
The XAPIC architecture provides for lowest priority delivery, through interrupt
redirection by the chipset. If the redirectable hint bit is set in the XAPIC message, the
chipset may redirect the interrupt to another processor. Note that redirection of
interrupts can be to any processor on either Processor Bus ID and can be applied to
both I/O interrupts and IPIs. The redirection can be performed in logical and physical
destination modes. For more details on the interrupt redirection algorithm, see
Section 5.6.3.
5.6.1
XAPIC Interrupt Message Format
Interrupt messages have an address of 0x000_FEEz_zzzY. The 16-bit “zzzz” field
(destination field) determines the target to which the interrupt is being sent. The Y field
is mapped to A3 (redirectable interrupt) and A2 (destination mode). Figure 5-18 shows
the address definition in IA32 systems (XAPIC). For each interrupt there is only one data
transfer. The data associated with the interrupt message specifies the interrupt vector,
destination mode, delivery status, and trigger mode. The transaction type on the
processor bus is a request type of, interrupt transaction. The transaction type on the
PCI Express and ESI buses is a write. The address definition of Figure 5-18 applies to
both the PCI Express bus and processor bus. Note that the current assumption is that
we can’t make any conclusions about which FSB an interrupt ID is associated with. At
power-up, there is an association for certain types of interrupts, but the current
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assumption is that the OS can reprogram the interrupt ID’s. Therefore, for directed
interrupts, the Intel 5000X chipset MCH will ensure that each interrupt is seen on both
FSBs.
Figure 5-14. XAPIC Address Encoding
31 20 19
12 11
4 3 2*
0
rsvd
EDID (not used) rh dm
0xFEE
DID
DID: 8-bit destination ID. Software may assign each ID to any value.
EDID: Not used, is a reserved field in the Processor EHS.
rh: redirection bit (0=directed, 1=redirectable)
dm: destination mode (0=physical, 1=logical)
*: PCI/PCI Express transaction encoding. Copied to Ab5 on processor bus
The data fields of an interrupt transaction are defined by the processor and XAPIC
specifications. It is included here for reference.
Table 5-12. XAPIC Data Encoding
D[63:16]
D[15]
Trigger Mode
D[14]
D[13:11]
D[10:8]
D[7:0]
x
Delivery Status
x
Delivery Mode
Vector
5.6.2
XAPIC Destination Modes
The destination mode refers to how the processor interprets the destination field of the
interrupt message. There are two types of destination modes; physical destination
mode, and logical destination mode. The destination mode is selected by A[2] in PCI
Express and Ab[5] on the processor bus.
5.6.2.1
Physical Destination Mode (XAPIC)
In physical mode, the APIC ID is 8 bits, supporting up to 255 agents. Each processor
has a Local APIC ID Register where the lower 5 bits are initialized by hardware (Cluster
ID=ID[4:3], Bus Agent ID=ID[2:1], thread ID=ID[0]). The upper 3 bits default to 0’s
at system reset. These values can be modified by software. The Cluster ID is set by
address bits A[12:11] during reset. By default, the Intel 5000P Chipset will drive
A[12:11] to ‘00 for FSB0, and ‘01 for FSB1. The value driven on bit A[12] during reset
can be modified through the POC register on the Intel 5000X chipset MCH.
The Intel 5000P Chipset will not rely on the cluster ID or any other fields in the APIC ID
to route interrupts. The Intel 5000P Chipset will ensure the interrupt is seen on both
busses and the processor with the matching APIC ID will claim the interrupt.
Physical destination mode interrupts can be directed, broadcast, or redirected. An
XAPIC message with a destination field of all 1’s denotes a broadcast to all.
In a directed physical mode message the agent claims the interrupt if the upper 8 bits
of the destination field (DID field) matches the Local APIC ID of the processor or the
interrupt is a broadcast interrupt.
Redirected interrupts are redirected and converted to a directed interrupt by the
chipset as described in Section 5.6.3.2.
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5.6.2.2
Logical Destination Mode (XAPIC)
In logical destination mode, destinations are specified using an 8 bit logical ID field.
Each processor contains a register called the Logical Destination Register (LDR) that
holds this 8-bit logical ID. Interpretation of the LDR is determined by the contents of
the processor’s Destination Format Register (DFR). Processors used with the Intel
5000X chipset MCH operate in flat mode. Logical destination mode interrupts can be
directed (fixed delivery), redirectable (lowest priority delivery), or broadcast. The LDR
is initialized to flat mode (0) at reset and is programmed by firmware. The Intel 5000P
Chipset also has an equivalent bit in the External Task Priority Register (XTPR0) to
indicate flat or cluster mode. This is set to flat mode by reset and must not be changed,
since the processors used with Intel 5000X chipset operate in flat mode only.
The 8-bit logical ID is compared to the 8-bit destination field of the incoming interrupt
message. If there is a bit-wise match, then the local XAPIC is selected as a destination
of the interrupt. Each bit position in the destination field corresponds to an individual
Local XAPIC Unit. The flat model supports up to 8 agents in the system. An XAPIC
message where the DID (destination field) is all 1’s is a broadcast interrupt.
5.6.2.3
XAPIC Interrupt Routing
Interrupt messages that originate from I/O(x)APIC devices or from processing nodes
must be routed and delivered to the target agents in the system. In general XAPIC
messages are delivered to both processor busses because there is no reliable way to
determine the destination processor of the message from the destination field.
Interrupts originating from I/O can be generated from a PCI agent using MSI
interrupts, or by an interrupt controller on a bridge chip such as the Intel 631xESB/
632xESB I/O Controller Hub. Table 5-13 shows the routing rules used for routing
XAPIC messages in an Intel 5000X chipset-based platform. This table is valid for both
broadcast and non-broadcast interrupts.
Table 5-13. Intel 5000X Chipset XAPIC Interrupt Message Routing and Delivery
Source
Type
Routing
I/O
physical or logical directed
Deliver to all processor busses as an interrupt
transaction.
Processor
physical or logical directed
Deliver to other processor bus as an interrupt
transaction.
Any Source
logical, redirectable
physical, redirectable
Redirection (see “Interrupt Redirection” on
page 352) is performed by the Intel 5000X
chipset MCH and is delivered to both FSBs.
5.6.3
Interrupt Redirection
The XAPIC architecture provides for lowest priority delivery through interrupt
redirection by the Intel 5000P Chipset. If the redirectable “hint bit” is set in the XAPIC
message, the chipset may redirect the interrupt to another agent. Redirection of
interrupts can be applied to both I/O interrupts and IPIs.
5.6.3.1
XTPR Registers
To accomplish redirection, the Intel 5000X chipset MCH implements a set of External
Task Priority registers (XTPRs), one for each logical processor (a thread is considered a
logical processor). Each register contains the following fields:
1. Agent priority (Task Priority)
2. APIC enable bit (TPR Enable)
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3. Logical APIC ID (LOGID)
4. Processor physical APIC ID (PHYSID)
The XTPR registers are modified by a front side bus xTPR_Update transaction. In
addition, the XTPR registers can be modified by software.
In addition, XTPR0 also contains a bit for Global Cluster Mode bit used in redirection of
logical destination mode messages. This bit indicates to the Intel 5000X chipset MCH
that destination field of the message is “flat” or physical (note that the XAPIC message
indicates whether the destination mode is physical or logical). The default logical mode
at reset is “flat” and must not be changed to “cluster” mode. Cluster mode is not
supported by the Intel® 5000X Chipset.
More details on the Intel 5000P Chipset XTPR registers are described in the XTPR
register definition in Section 3.8.6.3.
The XTPR special cycle must guarantee that the XTPR register is updated for interrupt
redirection in a consistent manner. For reproducibility, there needs to be an internal
serialization point after which subsequent interrupts will be redirected based on the
updated XTPR value.
5.6.3.2
Redirection Algorithm
Redirection is performed if an interrupt redirection hint bit (A[3]) is set. This is the
algorithm used in determining the processor that the interrupt will be redirected to.
1. If A[3] =1, then this is a redirection (also known as “lowest priority”) interrupt
request. Proceed to the next step.
2. FLAT: If Destination Mode = 1 (A2 for I/O, Ab5 for IPIs) is disabled (0) in the XTPR,
then this is Flat-Logical Destination Mode. (Otherwise, proceed to the next step). To
select the arbitration pool, for each XTPR register: Note: Cluster Mode is not
supported and should always be disabled.
If (A[19:12] (DID) AND XTPR[n].LOGID[7:0]) > 0h
AND XTPR[n].TPREN =1
then XTPR[n] is included in the arbitration pool.
3. PHYSICAL: If Destination Mode = 0 (A2 for I/O, Ab5 for IPIs), then this is Physical
Destination Mode. All enabled xTPR’s are included in the arbitration pool.
4. If there are no xTPR’s in the arbitration pool, then forward to FSB with A[3]=0, but
otherwise “without modification”. Otherwise, continue to the next step.
5. XTPRs in the pool are categorized into 4 priority buckets depending on the priority.
The priority bucket levels are defined by register bits BUCKET(0-2)_LIM in the
REDIRCTL register.
If (0 <= XTPR.PRIORITY < BUCKET0_LIM) then priority bucket = 0
If (BUCKET0_LIM <= XTPR.PRIORITY < BUCKET1_LIM) then priority bucket =
1
If (BUCKET1_LIM <= XTPR.PRIORITY < BUCKET2_LIM) then priority bucket =
2
If (BUCKET2_LIM <= XTPR.PRIORITY < 16) then priority bucket = 3
6. All xTPR’s in the arbitration pool are compared. The xTPR register with the lowest
priority bucket value (0=lowest, 3=highest) is the “winner”.
7. If more than one xTPR register in the arbitration pool has the same lowest priority
bucket value, then LRU arbitration logic will pick an xTPR that was not recently
picked.
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8. The “winning” xTPR register provides the values to be substituted in the
Aa[19:12]# field of the FSB Interrupt Message Transaction driven by the Intel
5000P Chipset. A[19:12]# is replaced by the logical or physical ID, depending on
the type of interrupt. The interrupt is driven onto both processor buses with the
redirection hint bit disabled (A3).
5.6.4
EOI
For XPF platforms using XAPIC, the EOI is a specially encoded processor bus
transaction with the interrupt vector attached. Since the EOI is not directed, the Intel
5000P Chipset will broadcast the EOI transaction to all I/O(x)APIC’s. The Intel 5000X
chipset MCH.PEXCTRL.DIS_APIC_EOI bit per PCI Express port can be used to
determine whether an EOI needs to be sent to a specific PCI Express port. EOI usage is
further described in Section 5.6.4.
Note:
The Intel 5000X chipset MCH will translate the EOI on the FSB into an EOI TLP
message type on the PCI Express/ESI ports.
5.7
I/O Interrupts
For I/O interrupts from the Intel 631xESB/632xESB I/O Controller Hub components
receive interrupts with either dedicated interrupt pins or with writes to the integrated
redirection table. The I/OxAPIC controller integrated within these components turns
these interrupts into writes destined for the processor bus with a specific address.
Interrupts triggered from an I/O device can be triggered with either a dedicated
interrupt pin or through an inbound write message from the PCI Express bus (MSI).
Note that if the interrupt is triggered by a dedicated pin, the I/OxAPIC controller in the
I/O bridge (Intel® 6700PXH 64 bit PCI Hub or ICH6 or ESB) turns this into an inbound
write. On the processor bus, the interrupt is converted to an interrupt request. Other
than a special interrupt encoding, the processor bus interrupt follows the same format
as discussed in Section 5.6.1. Therefore, to all components other than the Intel®
6700PXH 64 bit PCI Hub, ICH6 or ESB, and the processor, an interrupt is an inbound
write following the format mentioned in Section 5.6.1. Intel 5000X chipset will not
write combine or cache the APIC address space.
I/O(x)APIC’s can be configured through two mechanisms. The traditional mechanism is
the hard coded FEC0_0000 to FECF_FFFF range is used to communicate with the
IOAPIC controllers in the Intel® 6700PXH 64 bit PCI Hub, ICH6 or ESB.
The second method is to use the standard MMIO range to communicate to the Intel
6700PXH 64 bit PCI Hub. To accomplish this, the Intel® 6700PXH 64 bit PCI Hub.MBAR
and/or Intel 6700PXH 64 bit PCI Hub.XAPIC_BASE_ADDRESS_REG must be
programmed within the PCI Express device MMIO region.
5.7.1
Ordering
Handling interrupts as inbound writes has inherent advantages. First, there is no need
for the additional APIC bus resulting in extra pins and board routing concerns. Second,
with an out-of-band APIC bus, there are ordering concerns. Any interrupt needs to be
ordered correctly and all prior inbound writes must get flushed ahead of the interrupt.
The PCI Local Bus Specification, Revision 2.2attempts to address this by requiring all
interrupt routines to first read the PCI interrupt register. Since PCI read completions
are required to push all writes ahead of it, then all writes prior to the interrupt are
guaranteed to be flushed. However, this assumes that all drivers perform this read.
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5.7.2
Hardware IRQ IOxAPIC Interrupts
Dedicated pin interrupts may be edge or level triggered. They are routed to IRQ pins on
IOxAPIC device such as the Intel 6700PXH 64 bit PCI Hub, or Intel 631xESB/632xESB
I/O Controller Hub. The IOxAPIC device will convert the interrupt into either an XAPIC
or 8259 interrupt.
For level-triggered interrupts, the I/OxAPIC will generate an interrupt message when
any of the interrupt lines coming into it become asserted. The processor will handle the
interrupt and eventually write to the initiating device that the interrupt is complete. The
device will deassert the interrupt line to the I/OxAPIC. After the interrupt has been
serviced, the processor sends an EOI command to inform the I/OxAPIC that the
interrupt has been serviced. Since the EOI is not directed, the Intel 5000P Chipset will
broadcast the EOI transaction to all I/O(x)APIC’s. If the original I/O(x)APIC sees the
interrupt is still asserted, it knows there’s another interrupt (shared interrupts) and will
send another interrupt message.
For edge-triggered interrupts, the flow is the same except that there is no EOI message
indicating that the interrupt is complete. Since the interrupt is issued whenever an
edge is detected, EOIs are not necessary.
While not recommended, agents can share interrupts to better utilize each interrupt
(implying level-triggered interrupts). Due to ordering constraints, agents can not use
an interrupt controller that resides on a different PCI bus. Therefore either only agents
on the same PCI bus can share interrupts, or the driver MUST follow the PCI
requirement that interrupt routines must first read the PCI interrupt register
The Intel 5000X chipset MCH supports the INTA (interrupt acknowledge) special bus
cycle for legacy 8259 support. These are routed to the compatibility ICH6 or ESB in the
system. The INTA will return data that provides the interrupt vector.
5.7.3
Message Signalled Interrupts
A second mechanism for devices to send interrupts is to issue the Message Signalled
Interrupt (MSI) introduced in the PCI Local Bus Specification, Revision 2.2. This
appears as a 1 DWORD write on the PCI/PCI-X/PCI Express bus.
With PCI devices, there are two types of MSIs. One type is where a PCI device issues
the inbound write to the interrupt range. The other type of MSI is where a PCI device
issues an inbound write to the upstream APIC controller (for example, in the Intel
6700PXH 64 bit PCI Hub) where the APIC controller converts it into an inbound write to
the interrupt range. The second type of MSI can be used in the event the OS doesn’t
support MSIs, but the BIOS does. In either way, the interrupt will appear as an inbound
write to the Intel 5000P Chipset over the PCI Express ports.
MSI is expected to be supported by the operating systems when the Intel 5000X
chipset MCH is available. An Intel 5000X chipset platform will also feature a backup
interrupt mechanism in the event that there is a short period of time when MSI is not
available. This is described in the next section.
5.7.4
Non-MSI Interrupts - “Fake MSI”
For interrupts coming through the Intel 6700PXH 64 bit PCI Hub, and Intel 631xESB/
632xESB I/O Controller Hub components, their APIC controller will convert interrupts
into inbound writes, so inbound interrupts will appear in the same format as an MSI.
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For interrupts that are not coming through an APIC controller, it is still required that the
interrupt appear as an MSI-like interrupt. If the OS does not yet support MSI, the PCI
Express device can be programmed by the BIOS to issue inbound MSI interrupts to an
IOxAPIC in the system. The safest IOxAPIC to choose would be the Intel 631xESB/
632xESB I/O Controller Hub since it is always present in a system. Although the Intel
5000X chipset supports the PCI Express “Assert_Int” and “Deassert_Int” packets for
boot, the performance is not optimal and is not recommended for run time interrupts.
In this method, PCI Express devices are programmed to enable MSI functionality, and
given a write path directly to the pin assertion register in a selected IOxAPIC already
present in the platform. The IOxAPIC will generate an interrupt message in response,
thus providing equivalent functionality to a virtual (edge-triggered) wire between the
PCI Express endpoint and the I/OxAPIC. This mechanism is the same as is used in
Longhorn* (XYZZY).
All PCI Express devices are strictly required to support MSI. When MSI is enabled, PCI
Express devices generate a memory transaction with an address equal to the I/
OxAPIC_MEM_BAR + 20 and a 32-bit data equal to the interrupt vector number
corresponding to the device. This information is stored in the device's MSI address and
data registers, and would be initialized by the system firmware (BIOS) prior to booting
a non-MSI aware operating system. (With the theory that an MSI aware O/S would
then over-write the registers to provide interrupt message delivery directly from the
endpoint to the CPU complex.)
The PCI Express memory write transaction propagates to the Intel 5000P Chipset and
is redirected down the appropriate PCI Express port following the Intel 5000P Chipset
IOAPIC address mapping definition. The IOAPIC memory space ranges are fixed and
cannot be relocated by the OS. The assert message is indistinguishable from a memory
write transaction, and is forwarded to the destination I/OxAPIC, which will then create
an upstream APIC interrupt message in the form of an inbound memory write. The
write nature of the message “pushes” all applicable pre-interrupt traffic through to the
Intel 5000P Chipset core, and the Intel 5000P Chipset core architecture guarantees
that the subsequent APIC message cannot pass any posted data already within the
Intel 5000P Chipset.
5.8
Interprocessor Interrupts (IPIs)
• Previous IA-32 processors use IPIs after reset to select the boot strap processor
(BSP). Recent XPF processors do not use IPIs to select the BSP. A hardware
arbitration mechanism is used instead.
• IA32 processors use Startup IPIs (SIPIs) to wake up sleeping application
processors (non boot strap processors) that are in “Wait for SIPI state”. These are
broadcast interrupts.
• Interrupts transactions are claimed with TRDY# and No-Data Response.
• For directed XAPIC (A[3] = 0) interrupts, the Intel 5000P Chipset completes the
interrupt normally and forwards the interrupt to the other bus.
• For redirectable XAPIC interrupts, the Intel 5000P Chipset will generate an
interrupt message to both processor buses Intel 5000P Chipset with A[3]
(redirectable hint bit) set to 0. This message will contain a processor ID based on
the redirection algorithm.
• For directed XAPIC broadcast interrupts (Destination ID = 0xFF), the Intel 5000P
Chipset will forward the broadcast interrupt to the other processor bus.
• Interrupts are not deferred.
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• Since XAPIC directed interrupts (A[3] = 0) cannot be retried, they must be
accepted. If the Intel 5000P Chipset cannot accept the interrupt, then it must
assert BPRI# until resources are available.
5.8.0.1
IPI Ordering
In a system, there are ordering requirements between IPIs and other previous
coherent and non-coherent accesses. The way the ordering is maintained is that it is
expected that the chipset will defer the previous ordered access. The chipset will not
complete the transaction until the write is “posted” or the read data is delivered. Since
the processor will not issue an ordered IPI until the previous transaction has been
completed, ordering is automatically maintained.
An example where the ordering must be maintained is if a processor writes data to
memory and issues an IPI to indicate the data has been written, subsequent reads to
the data (after the IPI) must be the updated values. (Producer consumer). For this
example, assuming cacheable memory, the chipset defers the BIL/BRIL (read for
ownership). Only after all other processor caches have been invalidated, and the
deferred reply is returned (where the cache will be written) will the subsequent IPI be
issued.
There are no ordering requirements between IPIs. There are no ordering requirements
between IPIs and subsequent request. The IPIs are claimed on the FSB (front side bus)
and are not deferred. Therefore, software must not rely on the ordered delivery
between the IPI and subsequent transactions. If ordering is needed, it must protect any
subsequent coherent and non-coherent accesses from the effects of a previous IPI
using synchronization primitives. Also, software must not rely on ordered delivery of an
IPI with respect to other IPI from the same processor to any target processor.
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5.9
Chipset Generated Interrupts
The Intel 5000X chipset MCH can trigger interrupts for chipset errors and for PCI
Express. For these events, the chipset can be programmed to assert pins that the
system can route to an APIC controller. The interrupts generated by the chipset are still
being defined. The following is a preliminary list of interrupts that can be generated.
1. Chipset error - Intel 5000X chipset MCH asserts appropriate ERR pin, depending
on severity. This can be routed by the system to generate an interrupt at an
interrupt controller. (Intel 5000X chipset MCH pins ERR[2:0], MCERR, Intel
631xESB/632xESB I/O Controller Hub Reset). The ERR[0] pin denotes a correctable
and recoverable error. The ERR[1] pin denotes an uncorrectable error from Intel
5000X chipset MCH. The ERR[2] pin denotes a fatal error output from Intel 5000X
chipset MCH.
2. PCI Express error - Intel 5000X chipset MCH asserts appropriate ERR pin,
depending on severity. This can be routed by the system to generate an interrupt.
a. The Intel 5000X chipset MCH can receive error indications from the PCI Express
ports. These are in the form of inbound ERR_COR/UNC/FATAL messages. Intel
5000X chipset MCH will assert the appropriate ERR signal just like any internal
Intel 5000X chipset MCH error as described in the RAS chapter.
3. PCI Express hot-plug - Intel 5000X chipset MCH send Assert_HPGPE
(Deassert_HPGPE) or generates an MSI or a legacy interrupt on behalf of a PCI
Express Hot-Plug event.
a. Intel 5000X chipset MCH generated Hot-Plug event such as PresDet change,
Attn button, MRL sensor changed, power fault, and so forth. Each of these
events have a corresponding bit in the PCI Express Hot-Plug registers (Attention
Button, Power Indicator, Power Controller, Presence Detect, MRL Sensor, Port
Capabilities/Slot registers). This will generate an interrupt via the
assert_HPGPE, intx, or an MSI. Refer to Figure 5-15 for the Hotplug interrupt
flow priority.
b. PCI Express Hot-Plug event from downstream.
— GPE message: Upon receipt of a Assert_GPE message from PCI Express, Intel
5000X chipset MCH will send assert_GPE signal to the ESI port. To generate an
SCI (ACPI), this signal will be routed to the Intel® 631xESB/632xESB I/O
Controller Hub appropriate GPIO pin to match the GPE0_EN register settings.
When the Hot-Plug event has been serviced, Intel 5000X chipset MCH will
receive a Deassert_GPE message. At this point the Intel 5000X chipset MCH
can deassert_GPE message to ESI. There needs to be a tracking bit per PCI
Express port to keep track of Assert/Deassert_GPE pairs. These tracking bits
should be OR’d together to determine whether to send the assert_GPE/
Deassert_GPE message. When Intel 5000X chipset MCH receives a matching
deassert_GPE message for that port, it will clear the corresponding tracking bit.
When all the tracking bits are cleared, the Intel 5000X chipset MCH will send a
Deassert_GPE message to the ESI port.
— Sideband signals: Some systems may choose to connect the interrupt via
sideband signals directly to the Intel 631xESB/632xESB I/O Controller Hub. No
action is required from the Intel 5000X chipset MCH.
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Figure 5-15. PCI Express Hot-Plug Interrupt Flow
PEXHPINT
Intel® 5000P Chipset
sends desassert_HPGP
E message via
Intel® 5000P Chipset
Sends assert_HPGPE
message via DMI
Y
(PEXCTRL.HPGPE
EN == 1)
DMI when the
respective bits of
PEXSLOTSTS str
cleared (wired-
OR)
N
N
PEXSLOTCTRL[x].
HPINTEN = 1?
SW polls
status
Y
Intel® 5000P Chipset
sends MSI
Y
(MSICTRL[x].
MSIEN == 1) ?
per MSIAR and
MSIDR
N
Intel® 5000P Chipset
Sends desassert_INTx
message via DMI
when the
respective bits of
PEXSLOTSTS str
cleared (wired-
OR)
Intel® 5000P Chipset
Sends assert_INTx
message via DMI
per INTP
N
PEXCMD[x].INTx
Disable == 1?
Y
HPGPEEN
HPINTEN
MSIEN
INTx Disable
Output
1
0
0
0
0
x
1
1
1
0
x
1
0
0
x
x
x
0
1
x
assert_hpgpe
MSI
assert_intx
--
--
4. PCI Hot-Plug - Chipset will receive an Assert/Deassert GPE message from the PCI
Express port when a PCI Hot-Plug event is happening. Assert/Deassert GPE
messages should be treated the same as Assert/Deassert GPE messages for PCI
Express Hot-Plug. (Keep track of Assert/Deassert GPE messages from each port
and send Assert_GPE, Deassert_GPE message to ESI appropriately)
5. PCI Express Power management - PCI Express sends a PME message. Chipset
sends Assert_PMEGPE to ESI port when a power management event is detected.
a. Upon receipt of the PME message, Intel 5000X chipset MCH will set the
PEXRTSTS.PMESTATUS bit corresponding to that port and send Assert_PMEGPE
to ESI port to generate the interrupt. (Assert_PMEGPE should be sent if one or
more of the PMESTATUS bits are set and enabled.) To generate an SCI (ACPI),
this message will be used by the Intel 631xESB/632xESB I/O Controller Hub to
drive appropriate pin. When software has completed servicing the power
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Functional Description
management event, it will clear the PEXRTSTS.PMESTATUS bit (by writing 1), at
which point the Intel 5000X chipset MCH can send Deassert_PMEGPE to ESI
port.
The following table summarizes the different types of chipset generated interrupts that
were discussed. Although the interrupt and SW mechanism is flexible and can be
changed depending on how the system is hooked up, for reference this table also
describes what SW mechanism is expected to be used.
Table 5-14. Chipset Generated Interrupts
Intel 5000X Chipset MCH
signal method
Expected SW
mechanism
Source
Chipset Error
Signalling mechanism
Intel 5000X chipset MCH
registers
ERR[2:0], MCERR, Intel
631xESB/632xESB I/O
Controller Hub Reset
Any
PCI Express Error
PCI Express ERR_COR/UNC/FATAL ERR[2:0], MCERR, Intel
Any
message
631xESB/632xESB I/O
Controller Hub Reset
PCI Express HP (PresDet Intel 5000X chipset MCH
chg, Attn button, and so registers
MSI or Assert_intx,
Deassert_intx, or
Assert_HPGPE,
SCI->ACPI or
MSI
forth.)
For card-these registers are set
via the VPP/SM bus interface.
Deassert_HPGPE
For module- these registers are
set by inband Hot-Plug messages.
PCI Express HP from
downstream device
MSI
MSI interrupt (processor
bus)
MSI
PCI Express HP from
downstream device
(non-native, Intel part)
PCI Express Assert/Deassert GPE Assert_GPE, Deassert_GPE
to ESI
SCI->ACPI
PCI Express HP from
downstream device
(non-native, non-Intel
part)
Sideband signals directly to Intel N/A
631xESB/632xESB I/O Controller
Hub
SCI->ACPI
Downstream PCI Hot-
Plug
PCI Express Assert/Deassert GPE Assert_GPE, Deassert_GPE
to ESI
SCI->ACPI
SCI->ACPI
Power Management
Event (PME)
PCI Express PM_PME message
Assert_PMEGPE,
Deassert_PMEGPE to ESI
5.9.1
Intel 5000X Chipset Generation of MSIs
The Intel 5000X chipset MCH generates MSIs on behalf of PCI Express Hot-Plug events
if Intel 5000P Chipset MCH.MSICTRL.MSIEN is set. Refer to Figure 5-15. The Intel
5000X chipset MCH will interpret PCI Express Hot-Plug events and generate an MSI
interrupt based on Intel 5000P Chipset MCH.MSIAR and Intel 5000P Chipset
MCH.MSIDR registers. When the Intel 5000X chipset MCH detects any PCI Express
Hot-Plug event, it will generate an interrupt transaction to both processor buses. The
address will be the value in Intel 5000P Chipset MCH.MSIAR. The data value will be the
value in MSIDR.
Internal to the Intel 5000X chipset MCH, the MSI can be considered an inbound write
to address MSIAR with data value of MSIDR, and can be handled the same as other
inbound writes that are MSIs or APIC interrupts.
5.9.1.1
MSI Ordering in Intel 5000X Chipset MCH
Ordering issues on internally generated MSIs could manifest in the Intel 5000X chipset
MCH if software/device drivers rely on certain usage models, for example, interrupt
rebalancing, Hot-Plug to flush them. The producer-consumer violation may happen, if a
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Functional Description
root port has posted an MSI write internally in the MCH and the software wants to
“flush” all MSI writes from the root port that is, guarantee that all the MSI writes
pending in the MCH from the root port have been delivered to the local APIC in the
processor. To accomplish this flush operation, OS can perform a configuration read to,
say, the VendorID/DeviceID register of the root port and the expectation is that the
completion for this read will flush all the previously issued memory writes. The reason
the OS wants to flush is for cases where an interrupt source (like a root port) is being
retargeted to a different processor and OS needs to flush any MSI that is already
pending in the fabric that is still targeting the old processor.
As a case in point, reads to Intel 5000X chipset MCH PCI Express (internal)
configuration spaces will not generally guarantee ordering of internal MSIs from a root
port/DMA Engine device as required since the Intel 5000X chipset MCH uses a
configuration ring methodology which houses the registers for the various PCI Express
ports, MC, DMA Engine, Dfx and so forth) and it operates independently of the MSI/
interrupt generation logic. Thus any configuration ring access targeting a PCI Express
port registers will not necessarily order and align with the internal MSIs.
Solution: To mitigate this problem and enforce ordering of the MSIs, the Intel 5000X
chipset MCH will implement a “pending MSI signal” that is broadcast from the MSI/
Hotplug blocks to the coherency engine and thereby block the configuration request
(non-posted) till all the MSI gets committed. Software will ensure that it will block
future MSI generation for that device when it issues the configuration read for that
device.
The CE will block sending any completion with the new bit-slice bit set when any of the
pending MSI wires is asserted. CE will not block other transactions or completions
during the block. When the pending MSI wires are deasserted, CE will be able to send
the configuration completions.
The Intel 5000X chipset MCH Coherency Engine (CE) will block processor initiated MCH
configuration access completions (MMCFG or CFC/CF8) if there is a pending internally
generated MSI within the Intel 5000X chipset MCH. (MSIs could be generated from the
DMA engine or the HotPlug-Pwr-Mgr-PEX Error block.
The pending MSI signal will be deasserted after fetch-completion is asserted for the
MSI from CE, that is, global visibility is guaranteed on the FSB. Then release the
configuration block and allow the configuration completion to flow through. This
approach will order the MSI and then send the non-posted configuration for that
device.
CE will add a bit-slice (one bit per table entry) to track processor initiated MCH
configuration access in CE transaction table. Note: Inbound configuration access will
not set this bit.
A defeature mode to control the MSI/NP_CFG ordering is defined in the
COHDEF.DIS_MSI_NPCFG register field.
Note:
Internal MSIs cannot be continuously generated since the corresponding status register
field needs to be cleared by software through configuration access before a new MSI
can be asserted.
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Functional Description
5.10
Legacy/8259 Interrupts
8259 interrupt controller is supported in Intel 5000X chipset platforms. 8259 interrupt
request is delivered using the interrupt group sideband signals LINT[1:0] (a.k.a. NMI/
INTR) or through an I/O xAPIC using the message based interrupt delivery mechanism
with the delivery mode set to ExtINT (111b). There can be only one active 8259
controller in the system.
The mechanism in which a PCI Express device requests an 8259 interrupt is a PCI
Express inband message. (ASSERT_INTA/B/C/D, DEASSERT_INTA/B/C/D).
The target processor for the interrupt uses the interrupt acknowledge transaction to
obtain the interrupt vector from the 8259 controller. The Intel 5000P Chipset forwards
the interrupt acknowledge to the Intel 631xESB/632xESB I/O Controller Hub where
the active 8259 controller resides.
The Intel 5000P Chipset will support PCI Express devices that generate 8259 interrupts
(for example, during boot). 8259 interrupts from PCI Express devices will be sent in-
band to the Intel 5000P Chipset which will forward these interrupts to the Intel
631xESB/632xESB I/O Controller Hub.
The Intel 5000X chipset will have a mechanism to track inband 8259 interrupts from
each PCI Express and assert virtual interrupt signals to the 8259 through the inband
“Assert_(Deassert)_Intx” messages. This is done by a tracking bit per interrupt (A, B,
C, D) in each PCI Express which are combined (OR’d) into virtual signals that are sent
to the Intel 631xESB/632xESB I/O Controller Hub. Each interrupt signal (A, B, C, D)
from each PCI Express is OR’ed together to form virtual INT A, B, C, and D signals to
the Intel 631xESB/632xESB I/O Controller Hub (Assert_(Deassert)_IntA/B/C/D
(assertion encoding)). When all of the tracking bits for a given interrupt (A, B, C, or D)
are cleared from all PCI Express ports, the virtual signal A, B, C, or D is deasserted via
the inband Deassert_Intx message.
For PCI Express hierarchies, interrupts will be consolidated at each level. For example,
a PCI Express switch connected to a Intel 5000P Chipset PCI Express port will only send
a maximum of 4 interrupts at a time, regardless of how many interrupts are issued
downstream.
SMI (System Management Interrupt) interrupts are initiated by the SMI# signal in the
platform. On accepting a System Management Interrupt, the processor saves the
current state and enters SMM mode.
Note that the Intel 5000X chipset core components do not interact with the LINT[1:0]
and SMI signals. They are present on the Intel 631xESB/632xESB I/O Controller Hub
and the processor. Intel 5000X chipset interrupt signals described in Section 5.9 can
be routed to the Intel 631xESB/632xESB I/O Controller Hub to generate an SMI
interrupt. Similarly SCI interrupts can be generated by routing Intel 5000X chipset
interrupt signals to the appropriate Intel 631xESB/632xESB I/O Controller Hub pin.
5.11
Interrupt Error Handling
Software must configure the system so that each interrupt has a valid recipient. In the
event that an interrupt doesn’t have a valid recipient, since the Intel 5000X chipset will
not necessarily know that the interrupt is targeted for a non-existing processor, will
deliver the interrupt to the processor buses following the interrupt routing rules
described in this chapter. If the interrupt targets a non-existing processor, it may be
ignored but the transaction should still complete.
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Any error in the data part of an interrupt message, interrupt acknowledge, or EOI will
be treated the same way as data error with any other transaction – single bit errors will
be corrected by ECC, double bit error will be treated and logged as uncorrectable. For
more details on error handling, please refer to the RAS chapter.
5.12
Enterprise South Bridge Interface (ESI)
The Enterprise South Bridge Interface (ESI) in the Intel 5000X chipset north bridge is
the chip-to-chip connection to the Intel 631xESB/632xESB I/O Controller Hub see
Figure 5-16. The ESI is an extension of the standard PCI Express specification with
special commands/features added to enhance the PCI Express interface for enterprise
applications. This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic. Base functionality is completely transparent permitting
current and legacy software to operate normally. For the purposes of this document,
the Intel 631xESB/632xESB I/O Controller Hub will be used as a reference point for
the ESI discussion in the Intel 5000X chipset north bridge.
Figure 5-16. MCH to Intel 631xESB/632xESB I/O Controller Hub Enterprise South Bridge
Interface
M CH
Transaction
Link
Physical
Port 0
DMI
Physical
Link
Transaction
Intel® 631xESB/632xESB I/O
Controller Hub
The ESI port in the Intel 5000X chipset north bridge may be combined with two
additional PCI Express ports to augment the available bandwidth to the Intel 631xESB/
632xESB I/O Controller Hub. When operating alone the available bi-directional
bandwidth to the Intel 631xESB/632xESB I/O Controller Hub is 2 GB/s (1 GB/s each
direction). When the ESI is pared with 2 additional x4 PCI Express links the available
bi-directional bandwidth to the Intel 631xESB/632xESB I/O Controller Hub is increased
to 6 GB/s. The details of how the ESI port is combined with additional x4 PCI Express
ports are covered in Section 5.13.3.
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5.12.1
Power Management Support
The Intel 631xESB/632xESB I/O Controller Hub provides a rich set of power
management capabilities for the operating system. The MCH receives PM_PME
messages on its standard PCI Express port and propagates it to the Intel 631xESB/
632xESB I/O Controller Hub over the ESI as an Assert_PMEGPE message. When
software clears the PEXRTSTS.PME Status register bit, in the PEXRSTSTS[7:2, 0] PCI
Express Root Status Register, after it has completed the PME protocol, the MCH will
generate a Deassert_PMEGPE message to the Intel 631xESB/632xESB I/O Controller
Hub. The MCH must also be able to generate the Assert_PMEGPE message when exiting
S3 (after the reset). The PMGPE messages are also sent using a wired-OR approach.
5.12.1.1
Rst_Warn and Rst_Warn_Ack
The Rst_Warn message is generated by the Intel 631xESB/632xESB I/O Controller Hub
as a warning to the MCH that it wants to assert PLTRST# before sending the reset. In
the past, problems have been encountered due to the effects of an asynchronous reset
on the system memory states. Since memory has no reset mechanism itself other than
cycling the power, it can cause problems with the memory’s internal states when clocks
and control signals are asynchronously tri-stated or toggled, if operations resume
following this reset without power cycling. To protect against this, the Intel 631xESB/
632xESB I/O Controller Hub will send a reset warning to the MCH. The Gold Bridge
(Advanced Memory Buffer) is supposed to handle putting the DIMMs into a non-lockup
state in the event the link “goes down” in the middle of DDR2 protocol. The Intel 5000P
Chipset MCH is NOT required to place quiesce the DRAM’s prior to reset.
The MCH completes the handshake by generating the Rst_Warn_Ack message to the
ICH6 at the earliest.
5.12.1.2
STPCLK Propagation
The Intel 631xESB/632xESB I/O Controller Hub has a sideband signal called STPCLK.
This signal is used to place IA32 CPUs into a low power mode. Traditionally, this signal
has been routed directly from the I/O Controller Hub to the CPUs.
In future ESBx components, the plan is to rearchitect the mechanism for alerting the
CPUs of a power management event. However, this chipset (using Intel 631xESB/
632xESB I/O Controller Hub) will require the same method used for past server
chipsets (route STPCLK on the board as appropriate). The MCH will not provide any
in-band mechanisms for STPCLK.
5.12.2
5.12.3
Special Interrupt Support
The Intel 631xESB/632xESB I/O Controller Hub integrates an I/O APIC controller. This
controller is capable of sending interrupts to the processors with an inbound write to a
specific address range that the processors recognize as an interrupt. In general, the
compatibility interface cluster treats these no differently from inbound writes to DRAM.
However, there are a few notable differences listed below.
Inbound Interrupts
To the MCH, interrupts from the Intel 631xESB/632xESB I/O Controller Hub are simply
inbound non-coherent write commands routed to the processor buses. The MCH does
not support the serial APIC bus.
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5.12.4
Legacy Interrupt Messages
The ESI and PCI Express interfaces support two methods for handling interrupts: MSI
and legacy interrupt messages. The interrupt messages are a mechanism for taking
traditionally out-of -band interrupt signals and using in-band messages to
communicate. Each PCI Express interface accepts up to four interrupts (A through D)
and each interrupt has an assert/deassert message to emulate level-triggered
behavior. The MCH effectively wire-ORs all the INTA messages together (INTBs are
wire-ORed together, and so forth).
When the MCH accepts these PCI Express interrupt messages, it aggregates and passes
the corresponding “assert_intx” messages to the Intel 631xESB/632xESB I/O
Controller Hub’s I/OAPIC with from the PCI Express ports (wired-OR output transitions
from 0−>1) mechanism. When the corresponding deassert_intx message is received at
all the PCI Express ports (wired-OR output transitions from 1−>0), the “deassert_intx”
message is sent to ESI port.
5.12.5
End-of-Interrupt (EOI) Support
The EOI is a specially encoded processor bus transaction with the interrupt vector
attached. Since the EOI is not directed, the MCH will broadcast the EOI transaction to
all I/O(x)APICs. The MCH.PEXCTRL.DIS_APIC_EOI bit per PCI Express port can be used
to determine whether an EOI needs to be sent to a specific port.
5.12.6
Error Handling
Table 5-31 describes the errors detected on ESI through the standard PCI Express and
Advanced error reporting mechanism.
5.12.6.1
Inbound Errors
In general, if an inbound read transaction results in a Master Abort (unsupported
request), the compatibility interface cluster returns a Master Abort completion with
data as all ones. Likewise, for a Target Abort condition, the ESI cluster returns a Target
Abort completion with data as all ones. If a read request results in a Master or Target
Abort, the MCH returns the requested number of data phases with all ones data.
Master aborted inbound writes are dropped by the MCH, the error is logged, and the
data is dropped.
If the MCH receives an inbound unsupported Special Cycle message it is ignored and
the error condition is logged. If the completion required bit is set, an Unsupported
Special Cycle completion is returned.
5.12.6.2
Outbound Errors
It is possible that the compatibility interface cluster will receive an error response for
an outbound request. This can include a Master or Target Abort for requests that
required completions. The MCH might also receive an “Unsupported Special Cycle”
completion.
5.13
PCI Express Ports
The Intel 5000X chipset MCH contains two classes of PCI Express derived ports. These
are:
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• Enterprise South Bridge Interface (ESI), Port 0
• General purpose ports, Port 2, Port 3,
Note:
There is no PCI Express port designated as Port 1.
The ESI port is the primary interface to the Intel 631xESB/632xESB I/O Controller Hub.
This interface can be paired with up to two of the PCI Express ports (Port 2 and Port 3)
to increase available bandwidth to the Intel 631xESB/632xESB I/O Controller Hub. The
Intel 5000X chipset MCH supports a high performance x16 graphics PCI Express port.
This port contains several architectural enhancements to increase graphics
performance.
The following sections describe the characteristics of each of these port classes in
detail.
5.13.1
Intel 5000X Chipset MCH PCI Express Port Overview
The Intel 5000X chipset MCH utilizes general purpose PCI Express high speed ports to
achieve superior I/O performance. The MCH PCI Express ports are compliant with the
PCI Express Interface Specification, Rev 1.0a.
A PCI Express port is defined as a collection of bit lanes. Each bit lane consists of two
differential pairs in each direction (transmit and receive) as depicted in Table 5-17.
Figure 5-17. x4 PCI Express Bit Lane
Rx
Tx
Tx
Rx
AC coupling capacitors
LANE 0
Rx
Tx
AC coupling capacitors
P
O
R
T
P
O
R
Tx
Rx
LANE 1
Rx
Tx
T
AC coupling capacitors
Tx
Rx
LANE 2
Rx
Tx
Tx
Rx
AC coupling capacitors
LANE 3
LINK (x4)
The raw bit-rate per PCI Express bit lane is 2.5 Gbit/s. This results in a real bandwidth
per bit lane pair of 250 MB/s given the 8/10 encoding used to transmit data across this
interface. The result is a maximum theoretical realized bandwidth on a x4 PCI Express
port of 1 GB/s in each direction.
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Each of the Intel 5000X chipset MCH PCI Express port are organized as four bi-
directional bit lanes, and are referred to as a x4 port.
5.13.2
5.13.3
Enterprise South Bridge Interface (ESI)
The ESI is the Intel 631xESB/632xESB I/O Controller Hub to Intel 5000X chipset MCH
interface. The available bandwidth to the Intel 631xESB/632xESB I/O Controller Hub
can be increased by using the one or more of the PCI Express ports 2 and 3.
Figure 5-18 depicts the ESI port and PCI Express ports 2 and 3.
PCI Express Ports 2 and 3
The PCI Express ports 2 and 3 are general purpose x4 PCI Express ports that may be
used to connect to PCI Express devices. The possible configurations of the PCI Express
ports are depicted in Figure 5-18. By configuring ports 2 and 3 with the ESI port to the
Intel 631xESB/632xESB I/O Controller Hub, bandwidth is definable from 1GB/s in each
direction up to a maximum of 6 GB/s bi-directional. Figure 5-19 depicts the various
combinations of ESI and ports 2 and 3 connecting to the Intel 631xESB/632xESB I/O
Controller Hub. Ports 2 and 3 are also general purpose PCI Express ports that may be
used as high performance interfaces to other PCI Express devices.
Figure 5-18. ESI and PCI Express Ports 2 and 3
M C H
T r a n s a c t i o n
L i n k
P h y s i c a l
P o r t
0
D
M I
P h y s i c a l
L i n k
T r a n s a c t i o n
I n t e l ®
6 3 1 x E S
u b
B
/ 6 3 2 x E S
B
I / O
C
o n t r o l l e r
H
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Figure 5-19. MCH to Intel 631xESB/632xESB I/O Controller Hub Port Configurations
M C H
P o rt3
P o rt2
E S I
P C I-E x4
2 G B/s e c 2 G B/s e c
P C I-E x4
E S I
2 G B/s e c
In te l® 6 3 1 x E S B /6 3 2 x E S B I/O C o n tro lle r
H u b
5.13.4
PCI Express General Purpose Ports
Port 4, Port 5, Port 6, and Port 7 are configurable for general purpose I/O applications.
The Intel 5000X chipset MCH combines these four general purpose x4 ports into a
single optimized x16 high performance graphics interface. This interface is depicted in
Figure 5-20. These ports contain several architectural enhancements to improve
graphics performance.
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Figure 5-20. Intel 5000X Chipset PCI Express* High Performance x16 Port
PCI-Express cluster (IOU1)
Transaction
Link
Physical
Port 4
Port 5
Port 6
Port 7
High Performance
Graphics Port
5.13.5
Supported Length Width Port Partitioning
To establish a connection between PCI Express endpoints, they both participate in a
sequence of steps known as training. This sequence will establish the operational width
of the link as well as adjust skews of the various lanes within a link so that the data
sample points can correctly take a data sample off of the link. In the case of a x8 port,
the x4 link pairs will first attempt to train independently, and will collapse to a single
link at the x8 width upon detection of a single device returning link ID information
upstream. Once the number of links has been established, they will negotiate to train
at the highest common width, and will step down in its supported link widths in order to
succeed in training. The ultimate result may be that the link has trained as a x1 link.
Although the bandwidth of this link size is substantially lower than a x8 link or x4 link,
it will allow communication between the two devices. Software will then be able to
interrogate the device at the other end of the link to determine why it failed to train at
a higher width.
This autonomous capability can be overridden by the values sampled on the
PEWIDTH[3:0] pins. Table 5-4 illustrates the PEWIDTH strapping options for various
link widths in the PCI Express ports in the MCH.
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Table 5-4.
PCI Express Link Width Strapping Options for Port CPCI Configuration in MCH
Port0
(ESI)
PEWIDTH[3:0]
Port2
Port3
Port4
Port5
Port6
Port7
0000
0001
0010
0011
0100
others
1000
1001
1010
1011
1100
others
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x8
x8
x8
x8
x4
x4
x16
Reserved
x4
x4
x4
x4
x4
x8
x8
x8
x8
x8
x4
x4
x4
x4
x4
x4
x4
x4
x8
x8
x8
x8
x16
Reserved
All port widths determined by link negotiation.
1111
x4.
Note:
Note:
Intel 5000V Chipset does not have PCI Express ports 4, 5, 6, and 7. So the only option
is to configure ports 2 and 3 as a single x8 or two x4 ports.
The PCI Express Base Specification, Revision 1.0a requires that a port be capable of
negotiating and operating at the native width and 1x. The Intel 5000X chipset MCH will
support the following link widths for its PCI-Express ports viz., x16, x8, x4, x2 and x1.
During link training, the MCH will attempt link negotiation starting from its native link
width from the highest and ramp down to the nearest supported link width that passes
negotiation. For example, a port strapped at 8x, will first attempt negotiation at 8x. If
that attempt fails, an attempt is made at x4, then a x1 link.Note that the x8 and x4 link
widths will only use the LSB positions from lane 0 while a x1 can be connect to any of
the 4 positions (lane0,lane1, lane2, lane3) providing a higher tolerance to single point
lane failures.
5.13.6
PCI Express Port Support Summary
The following table describes the options and limitations supported by the MCH PCI
Express ports.
Table 5-15. Options and Limitations (Sheet 1 of 2)
Parameter
Support
The MCH will support six x4 standard PCI Express ports and an additional
x4 ESI port for Intel 631xESB/632xESB I/O Controller Hub. (Total: 6 + 1
= 7 ports)
Number of supported ports
Max payload
Hot-Plug
256B
Serial port to support pins
MCH only supports VC0
MCH does not support isochrony
MCH does not support ECRC
MCH only supports strict PCI ordering
Virtual Channels
Isochrony
ECRC
Ordering
MCH will not snoop processor caches for transactions with the No Snoop
attribute
No Snoop
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Table 5-15. Options and Limitations (Sheet 2 of 2)
Parameter
Support
The MCH cannot be powered down, but will forward messages, generate
PME_Turn_Off and collect PME_TO_Acks. It will provide the PM Capabilities
structure. The MCH does not support Active State Power Management nor
the L0s state.
Power Management
Retry buffers are sized to meet the Intel 5000X chipset platform
requirements for an integrated DP chassis and which do not require cable
or repeater support. Only an 8 inches of FR4 internal trace connector
latency is assumed.
No Cable Support & no repeaters
Poisoning
MCH will poison data that it cannot correct
5.13.7
PCI Express Port Physical Layer Characteristics
The PCI Express physical layer implements high-speed differential serial signalling
using the following techniques:
• Differential signalling (1.6 V peak-to-peak)
• 2.5 GHz data rate (up to 2 GB/s/direction peak bandwidth for a x8 port)
• 8b/10b encoding for embedded clocking and packet framing
• Unidirectional data path in each direction supporting full duplex operation
• Random idle packets and spread-spectrum clocking for reduced EMI
• Loop-back mode for testability
• Lane reversal
• Polarity Inversion
Figure 5-21 illustrates the scope of the physical layer on a PCI Express packet. There
are two types of packets: Link layer packets and Transaction Layer Packets. The
physical layer is responsible for framing these packets with STP/END symbols
(Transaction Layer Packets) and SDP/END symbols (Data Link Layer packets). The
grayed out segment is not decoded by the Physical layer.
Figure 5-21. PCI Express Packet Visibility By Physical Layer
STP Link/Txn Layer Visible Info END
SDP
Link Layer Visible Info
END
5.13.7.1
PCI Express Training
To establish a connection between PCI Express endpoints, they both participate in a
sequence of steps known as training. This sequence will establish the operational width
of the link as well as adjust skews of the various lanes within a link so that the data
sample points can correctly take a data sample off of the link. In the case of a x8 port,
the x4 link pairs will first attempt to train independently, and will collapse to a single
link at the x8 width upon detection of a single device returning link ID information
upstream. Once the number of links has been established, they will negotiate to train
at the highest common width, and will step down in its supported link widths in order to
succeed in training. The ultimate result may be that the link has trained as a x1 link.
Although the bandwidth of this link size is substantially lower than a x8 link or x4 link,
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it will allow communication between the two devices. Software will then be able to
interrogate the device at the other end of the link to determine why it failed to train at
a higher width.
5.13.7.2
5.13.7.3
8b/10b Encoder/Decoder and Framing
As a transmitter, the physical layer is responsible for encoding each byte into a 10 bit
data symbol before transmission across the link. Packet framing is accomplished by the
physical layer by adding special framing symbols (STP, SDP, END). PCI Express
implements the standard Ethernet and InfiniBand* 8b/10b encoding mechanism.
Elastic Buffers
Every PCI Express port implements an independent elastic buffer for each PCI Express
lane. The elastic buffers are required since the Intel 5000X chipset MCH and PCI
Express endpoints could be clocked from different sources. Clocks from different
sources will never be exactly the same. The outputs of the elastic buffers feed into the
deskew buffer.
Figure 5-22. PCI Express Elastic Buffer (x4 Example)
Local Clock = 2.501 GHz
Remote Clock = 2.499 GHz
The elastic buffer is eight symbols deep. This accounts for three clocks of
synchronization delay, the longest possible TLP allowed by the Intel 5000X chipset
MCH (256 B), a 600ppm difference between transmitter and receiver clocks, and worst
case skip ordered sequence interval of 1538, framing overheads, and a few symbols of
margin.
5.13.7.4
Deskew Buffer
Every PCI Express port implements a deskew buffer. The deskew buffer compensates
for the different arrival times for each of the symbols that make up a character. The
outputs of the deskew buffer is the data path fed into the Link layer.
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Figure 5-23. PCI Express Deskew Buffer (4X Example)
Elastic Buffer
At reset, the delay of each lane in the deskew buffer is adjusted so that the symbols on
each lane are aligned. The receiver must compensate for the allowable skew between
lanes within a multi-lane link before delivering the data and control to the data link
layer. The deskew buffer is eight symbols deep to compensate for up to 20 ns of skew
between lanes.
5.13.7.5
Polarity Inversion
The PCI Express Base Specification, Revision 1.0a defines a concept called polarity
inversion. Polarity inversion allows the board designer to connect the D+ and D- lines
incorrectly between devices. The Intel 5000X chipset MCH supports polarity inversion.
5.13.8
Link Layer
The Data Link Layer of the PCI Express protocol is primarily responsible for data
integrity. This is accomplished with the following elements:
• Sequence number assignment for each packet
• ACK/NAK protocol to ensure successful transmission of every packet
• CRC protection of packets
• Time-out mechanism to detect “lost” packets
• Credit exchange
Figure 5-24 illustrates the scope of the link layer on a PCI Express packet. There are
two types of packets: data link layer packets (DLLP) and Transaction Layer Packets
(TLP). Data Link layer packets are sent between the Link layers of each PCI Express
device and do not proceed to the Transaction Layer.
For Transaction layer packets (TLP), the link layer is responsible for prepending
sequence numbers and appending 32-bit CRC. The grayed out segment is not decoded
by the Data Link layer.
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Figure 5-24. PCI Express Packet Visibility By Link Layer
Seq #
TLP
CRC
DLLP
5.13.8.1
Data Link Layer Packets (DLLP)
Refer to PCI Express Base Specification, Revision 1.0a for an explicit definition of all the
fields in a Data Link Layer packet.
DLLPs are used to ACK or NAK packets as they are sent from the transmitter to the
receiver. They are sent by the receivers of the packet to indicate to the transmitter that
a packet was successfully received (ACK) or not (NAK). DLLPs are also used to
exchange credit information between the transmitter and receiver.
DLLPs are protected with 16b CRC. If the CRC of a received DLLP indicates an error, the
DLLP is dropped. This is safe because the PCI Express protocol supports dropping these
packets and the next DLLP allows the transmitter to process successfully.
5.13.8.2
ACK/NAK
The Data Link layer is responsible for ensuring that packets are successfully
transmitted between PCI Express agents. PCI Express implements an ACK/NAK
protocol to accomplish this. Every packet is decoded by the physical layer and
forwarded to the link layer. The CRC code appended to the packet is then checked. If
this comparison fails, the packet is “retried”.
If the comparison is successful, an ACK is issued back to the transmitter and the packet
is forwarded for decoding by the receiver’s Transaction layer. Typically, as each packet
is successfully received by the Data Link layer, the receiver issues an ACK. However,
the PCI Express protocol allows that ACKs can be combined.
5.13.8.3
Link Level Retry
The PCI Express Base Specification, Revision 1.0a lists all the conditions where a
packet gets negative acknowledged. One example is on a CRC error. The link layer in
the receiver is responsible for calculating 32 b CRC (using the polynomial defined in the
PCI Express Base Specification, Revision 1.0a) for incoming packets and comparing the
calculated CRC with the received CRC. If they do not match, then the packet is retried
by negative acknowledging the packet with a NAK DLLP and specifying the sequence
number of the last good packet. Subsequent packets are dropped until the reattempted
packet is observed again.
When the transmitter receives the NAK, it is responsible for retransmitting the packet.
Furthermore, any packets sent after the last good packet will also be resent since the
receiver has dropped any packets after the corrupt packet.
The transmitter keeps track of packets that have been sent but not acknowledged
through the use of a retry buffer. Transactions are added to the buffer as they are on
the PCI Express port. Transactions are removed from the buffer after they have been
acknowledged by the receiver.
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5.13.8.4
ACK Time-out
Packets can get “lost” if the packet is corrupted such that the receiver’s physical layer
does not detect the framing symbols properly. Normally, lost packets are detectable
with non-linearly incrementing sequence numbers. A time-out mechanism exists to
detect (and bound) cases where the last packet sent (over a long period of time) was
corrupted. A replay timer bounds the time a retry buffer entry waits for an ACK or NAK.
Refer to the PCI Express Base Specification, Revision 1.0a for details on this
mechanism for the discussion on Retry Management and the recommended timer
values.
5.13.9
Flow Control
The PCI Express mechanism for flow control is credit based and only applies to TLPs.
DLLP packets do not consume any credits. Through initial hardware negotiation and
subsequent updates, a PCI Express transmitter is aware of the credit capabilities of the
interfacing device. A PCI Express requester will never issue a transaction when there
are not enough advertised credits in the other component to support that transaction.
If there are not enough credits, the requester will hold off that transaction until enough
credits free up to support the transaction. If the ordering rules and available credits
allow other subsequent transactions to proceed, the MCH will allow those transactions.
For example, assume that there are no Non-Posted Request Header Credits (NPRH)
credits remaining and a memory write is the next transaction in the queue. PCI Express
ordering rules allow posted writes to pass reads. Therefore, the Intel 5000X chipset
MCH will issue the memory write. Subsequent memory reads from the source device
must wait until enough NPRH credits free up.
Note:
Flow control is orthogonal with packet ACKs.
The PCI Express flow control credit types are described in Table 5-16. The PCI Express
Base Specification, Revision 1.0a defines which TLPs are covered by each flow control
type.
Table 5-16. PCI Express Credit Mapping for Inbound Transactions (Sheet 1 of 2)
Flow Control
Type
Initial MCH
Advertisement
Definition
Inbound Posted
Request Header
Credits (IPRH)
Tracks the number of inbound posted requests the agent is
capable of supporting. Each credit accounts for one posted
request.
14 (4x)
28(8x)
56(x16)
Inbound Posted
Request Data
Credits (IPRD)
Tracks the number of inbound posted data the agent is capable
of supporting. Each credit accounts for up to 16 bytes of data.
54 (4x)
108(8X)
216(16X)
Inbound Non-
Posted Request
Header Credits
(INPRH)
Tracks the number of non-posted requests the agent is capable
of supporting. Each credit accounts for one non-posted request.
14 (4X)
28(8X)
56(16X)
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Table 5-16. PCI Express Credit Mapping for Inbound Transactions (Sheet 2 of 2)
Flow Control
Type
Initial MCH
Advertisement
Definition
Inbound Non-
Posted Request
Data Credits
(INPRD)
Tracks the number of non-posted data the agent is capable of
supporting. Each credit accounts for up to 16 bytes of data.
2 (4X)
4 (8X)
8 (16X)
Completion
Header Credits
(CPH) (outbound
request
completions
received at the
MCH)
Tracks the number of completion headers the agent is capable
0 (Infinite)
(4) [x4]
(8) [x8]
1
of supporting.
(16) (x16)
Completion Data
Credits (CPD)
(outbound
Tracks the number of completion data the agent is capable of
supporting. Each credit accounts for up to 16 bytes of data.
0 (Infinite)
(8) [x4]
(16) [x8]
(32) [x16]
request
completions
(data) received at
the MCH)
Notes:
1. Root complexes and end points are permitted to advertise an infinite number of credits for completions.
Though the MCH implements finite queue structures as indicated in bracket for the completions on the inbound
side, by construction, it will never overflow since for each outbound request, the MCH allocates sufficient space
on the inbound side. i.e guarantee by construction
Table 5-17. PCI Express Credit Mapping for Outbound Transactions
Flow Control
Type
Initial MCH
Advertisement
Definition
Outbound Posted
Request Header
Credits (OPRH)
Tracks the number of outbound posted requests the agent is
capable of supporting. Each credit accounts for one posted
request.
4(4x)
8(8x)
16(16)
Outbound Posted
Request Data
Credits (OPRD)
Tracks the number of outbound posted data the agent is
capable of supporting. Each credit accounts for up to 16 bytes
of data.
8(4x)
16(8X)
32(16X)
Outbound Non-
Posted Request
Header Credits
(ONPRH)
Tracks the number of non-posted requests the agent is capable
of supporting. Each credit accounts for one non-posted request.
16(4X)
32(8X)
64(16X)
Outbound Non-
Posted Request
Data Credits
(ONPRD)
Tracks the number of non-posted data the agent is capable of
supporting. Each credit accounts for up to 16 bytes of data.
16(4X)
32(8X)
64(16X)
Completion
Header Credits
(CPLH) (inbound
request
Tracks the number of completion headers the agent is capable
of supporting.
2(x4)
4(x8)
8(x16)
completions from
MCH)
Completion Data
Credits (CPLD)
(inbound request
completions
Tracks the number of completion data the agent is capable of
supporting. Each credit accounts for up to 16 bytes of data.
8(x4)
16(x8)
32(x16)
(data) from the
MCH)
The credit advertisements for the MCH are shown in Table 5-16 and Table 5-17. Every
PCI Express device tracks the above six credit types (inbound) for both itself and the
interfacing device. The rules governing flow control are described in the PCI Express
Base Specification, Revision 1.0a.
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5.13.9.1
Credit Update Mechanism, Flow Control Protocol (FCP)
After reset, credit information is initialized with the values indicated in Table 5-16 by
following the flow control initialization protocol defined in the PCI Express Base
Specification, Revision 1.0a. Since the MCH supports only VC0, only this channel is
initialized.
5.13.10 Transaction Layer
The PCI Express Transaction Layer is responsible for sending read and write operations
between components. This is the PCI Express layer which actually moves software
visible data between components. The transaction layer provides the mechanisms for:
• Software configuration of components
• Communication between the processor bus and different I/O technologies
• Communication between the memory and different I/O technologies
Figure 5-17 illustrates the scope of the transaction layer on a PCI Express packet.
Some transaction layer packets have only a header (for example, read request). Some
transaction layer packets have a header followed by data (for example, write requests
and read completions).
Figure 5-25. PCI Express Packet Visibility By Transaction Layer
Hdr
Hdr
Payload
5.14
Power Management
The Intel 5000X chipset MCH power management support includes:
• ACPI supported
• System States: S0, S1 (desktop), S3, S4, S5, C0, C1, C2 (desktop)
5.14.1
Supported ACPI States
The MCH supports the following ACPI States:
• Processor
— C0: Full On.
— C1: Auto Halt.
— C2 Desktop: Stop Grant. Clock to processor still running. Clock stopped to
processor core.
• System
— G0/S0: Full On.
— G1/S1: Stop Grant, Desktop S1, same as C2.
— G1/S2: Not supported.
— G1/S3: Suspend to RAM (STR). Power and context lost to chipset.
— G1/S4: Suspend to Disk (STD). All power lost (except wake-up logic on Intel
631xESB/632xESB I/O Controller Hub).
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— G2/S5: Soft off. Requires total system reboot.
— G3: Mechanical Off. All power lost (except real time clock).
5.14.2
FB-DIMM Thermal Management
The Intel 5000X chipset MCH implements the following thermal management
mechanisms. These mechanisms manage the read and write cycles of the system
memory interface to implement thermal throttling.
Hardware-Based Thermal Management
The number of hex-words transferred over the DRAM interface are tracked per row. The
tracking mechanism takes into account that the DRAM devices consume different levels
of power based on cycle type (page hit/miss/empty). If the programmed threshold is
exceeded during a monitoring window, the activity on the DRAM interface is reduced.
This helps in lowering the power and temperature.
Software-Based Thermal Management
This is used when the external thermal sensor in the system interrupts the processor to
engage a software routine for thermal management.
5.14.3
FB-DIMM Thermal Diode Overview
The FB-DIMM Advanced Memory Buffer (AMB) contains an internal thermal diode to
measure AMB / DIMM temperature. Upon detecting a thermal over temperature
condition the AMB initiates a thermal throttling event. For more information see the
Gold Bridge Component External Design Specification.
5.15
System Reset
The Intel 5000X chipset MCH is the root of the I/O subsystem tree, and is therefore
responsible for general propagation of system reset throughout the platform. The MCH
must also facilitate any specialized synchronization of reset mechanisms required by
the various system components.
5.15.1
MCH Power Sequencing
General power sequencing requirements for the Intel 5000X chipset MCH are simple.
In general higher voltages must come up before lower voltages. Figure 5-26 depicts the
sequencing of the three main voltages powering the Intel 5000X chipset MCH.
Figure 5-26. Intel 5000P Chipset Power Sequencing
Note: Power-up -> 3.3V must ramp ahead and stay above 1.5V, which must ramp ahead and stay above 1.2V.
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3.3V must always be at least 0.7V greater than 1.5V. Duration of the power ramp must be between
0.1 ms and 100 ms.
5.15.2
MCH Reset Types
The Intel 5000X chipset MCH differentiates among five types of reset as defined in
table Table 5-18.
Table 5-18. MCH Reset Classes
Type
Mechanism
Effect / Description
Power-Good
PwrGd Input Pin
Propagated throughout the system hierarchy. Resets all logic and state
machines, and initializes all registers to their default states (sticky and
non-sticky). Tri-states all MCH outputs, or drives them to “safe” levels.
Hard
RSTIN# Input Pin,
Configuration Write
Propagated throughout the system hierarchy. Resets all logic and state
machines, and initializes all non-sticky registers to their default states.
Tri-states all MCH outputs, or drives them to “safe” levels.
Processor-
only
Configuration Write
Configuration Write
Propagated to all processors via the FSBxRERSET# pins on the FSB.
The MCH does not undergo an internal reset.
Targeted
Propagated down the targeted PCI Express port hierarchy. Treated as
a “Hard” reset by all affected components, clearing all machine state
and non-sticky configuration registers.
BINIT#
Internal Error
Handling Propagated
via FSB BINIT# pin
Propagated to all FSB attached components (the MCH and up to two
processors). Clears the IOQ, and resets all FSB arbiters and state
machines to their default states. Not recoverable.
5.15.2.1
Power-Good Mechanism
The initial boot of a Intel 5000X chipset MCH platform is facilitated by the Power-Good
mechanism. The voltage sources from all platform power supplies are routed to a
system component which tracks them as they ramp-up, asserting the platform “PwrGd”
signal a fixed interval (nominally 2mS) after the last voltage reference has stabilized.
There are no requirements within the MCH regarding the precise sequencing of power-
supply ramps, thus the platform should initialize properly regardless of the order in
which supplies stabilize.
Both the Intel 5000X chipset MCH and the Intel 631xESB/632xESB I/O Controller Hub
receive the system PwrGd signal via dedicated pins as an asynchronous input, meaning
that there is no assumed relationship between the assertion or deassertion of PwrGd
and any system reference clock. When PwrGd is deasserted all platform subsystems
are held in their reset state. This is accomplished by various mechanisms on each of
the different interfaces. The MCH will hold itself in a power-on reset state when PwrGd
is deasserted. The Intel 631xESB/632xESB I/O Controller Hub is expected to assert its
PCIRST# output and maintain its assertion for 1mS after power is good. The PCIRST#
output from Intel 631xESB/632xESB I/O Controller Hub is expected to drive the
RSTIN# input pin on the Intel 5000X chipset MCH, which will in turn hold the processor
complex in reset via assertion of the FSBxRESET# FSB signals.
The PCI Express attached devices and any hierarchy of components underneath them
are held in reset via implicit messaging across the PCI Express interface. The MCH is
the root of the hierarchy, and will not engage in link training until power is good and the
internal “hard” reset has deasserted.
A PwrGd reset will clear all internal state machines and logic, and initialize all registers
to their default states, including “sticky” error status bits that are persistent through all
other reset classes. To eliminate potential system reliability problems, all devices are
also required to either tri-state their outputs or to drive them to “safe” levels during a
power-on reset.
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Functional Description
The only system information that will “survive” a PwrGd reset is either contained in
battery-backed or non-volatile storage.
5.15.2.2
Hard Reset Mechanism
Once the Intel 5000X chipset MCH platform has been booted and configured, a full
system reset may still be required to recover from system error conditions related to
various device or subsystem failures. The “hard” reset mechanism is provided to
accomplish this recovery without clearing the “sticky” error status bits useful to track
down the cause of system reboot.
A hard reset is typically initiated by the Intel 631xESB/632xESB I/O Controller Hub
component via the PCIRST# output pin, which is commonly connected directly to the
Intel 5000X chipset MCH RSTIN# input pin. The Intel 631xESB/632xESB I/O
Controller Hub may be caused to assert PCIRST# via both software and hardware
mechanisms. The Intel 5000X chipset MCH will recognize a hard reset any time
RSTIN# is asserted while PwrGd remains asserted.
The Intel 5000X chipset MCH will propagate a hard reset to the FSB and to all
subordinate PCI Express subsystems. The FSB components are reset via the
FSBxRESET# signals, while the PCI Express subsystems are reset implicitly when the
root port links are taken down.
A hard reset will clear all internal state machines and logic, and initialize all “non-
sticky” registers to their default states. Note that although the error registers will
remain intact to facilitate root-cause of the hard reset, the Intel 5000X chipset MCH
platform in general will require a full configuration and initialization sequence to be
brought back on-line.
5.15.2.3
Processor-Only Reset Mechanism
For power management and other reasons, the Intel 5000X chipset MCH supports a
targeted processor only reset semantic. This mechanism was added to the platform
architecture to eliminate double-reset to the system when reset-signaled processor
information (such as clock gearing selection) must be updated during initialization
bringing the system back to the S0 state after power had been removed from the
processor complex.
5.15.3
Targeted Reset Mechanism
The targeted reset is provided for Hot-Plug events, as well as for port-specific error
handling under Machine Check Architecture (MCA) or SMI software control. The former
usage model is new with PCI Express technology, and the reader is referred to the PCI
Express Interface Specification, Rev 1.0a for a description of the Hot-Plug mechanism.
A targeted reset may be requested by setting bit 6 (Secondary Bus Reset) of the Bridge
Control Register (offset 3Eh) in the target root port device. This reset will be identical
to a general hard reset from the perspective of the destination PCI Express device; it
will not be differentiated at the next level down the hierarchy. Sticky error status will
survive in the destination device, but software will be required to fully configure the
port and all attached devices once reset and error interrogation have completed. After
clearing bit 6, software may determine when the downstream targeted reset has
effectively completed by monitoring the state of bit 1 (Link Active) of the VS_STS1
register (offset 47h) in the target root port device. This bit will remain deasserted until
the link has regained “link up” status, which implies that the downstream device has
completed any internal and downstream resets, and successfully completed a full
training sequence.
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Functional Description
Under normal operating conditions it should not be necessary to initiate targeted resets
to downstream devices, but the mechanism is provided to recover from combinations
of fatal and uncorrectable errors which compromise continued link operation.
5.15.4
BINIT# Mechanism
The BINIT# mechanism is provided to facilitate processor handling of system errors
which result in a hang on the FSB. The Machine Check Architecture (MCA) code
responding to an error indication, typically IERR# or MCERR#, will cause an attempt to
interrogate the MCH for error status, and if that FSB transaction fails to complete the
processor will automatically time out and respond by issuing a BINIT# sequence on the
FSB.
When BINIT# is asserted on the FSB, all bus agents (CPUs and MCH) are required to
reset their internal FSB arbiters and all FSB tracking state machines and logic to their
default states. This will effectively “un-hang” the bus to provide a path into chipset
configuration space. Note that the MCH device implements “sticky” error status bits,
providing the platform software architect with free choice between BINIT# and a
general hard reset to recover from a hung system.
Although BINIT# will not clear any configuration status from the system, it is not a
recoverable event from which the platform may continue normal execution without first
running a hard reset cycle. To guarantee that the FSB is cleared of any hang condition,
the MCH will clear all pending transaction states within its internal buffers. This applies
to outstanding FSB cycles as required, but also to in-flight memory transactions and
inbound transactions. The resulting state of the platform will be highly variable
depending upon what precisely got wiped-out due to the BINIT# event, and it is not
possible for hardware to guarantee that the resulting state of the machine will support
continued operation. What the MCH will guarantee is that no subordinate device has
been reset due to this event (PCI Express links will remain “up”), and that no internal
configuration state (sticky or otherwise) has been lost. The MCH will also continue to
maintain main memory via the refresh mechanism through a BINIT# event, thus
machine-check software will have access not only to machine state, but also to
memory state in tracking-down the source of the error.
5.15.5
Reset Sequencing
Figure 5-27, “Power-On Reset Sequence” on page 366 contains a timing diagram
illustrating the progression through the power-on reset sequence. This is intended as a
quick reference for system designers to clarify the requirements of the MCH.
Note the breaks in the clock waveform at the top of Figure 5-27, which are intended to
illustrate further elapsed time in the interest of displaying a lengthy sequence in a
single picture. Each of the delays in the reset sequence is of fixed duration, enforced by
either the MCH or the Intel 631xESB/632xESB I/O Controller Hub. In the case of a
power-on sequence, the MCH internal “hard” and “core” resets deassert
simultaneously. The two lines marked with names beginning “HLA” illustrate the ESI
special cycle handshake between the MCH and the Intel 631xESB/632xESB I/O
Controller Hub to coordinate across the deasserting edge of the FSBxRESET# output
from the MCH.
Table 5-19 summarizes the durations of the various reset stages illustrated above, and
attributes the delays to the component that enforces them.
The fixed delays provide time for subordinate PLL circuitry to lock on interfaces where
the clock is withheld or resynchronized during the reset sequence.
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Functional Description
Figure 5-27. Power-On Reset Sequence
HCLK
PwrGd
1 mS
Cold_Reset
RSTIN#
1 mS
4-6 HCLK
Hard_Reset
Core_Reset
HLA_cpurstdone
HLA_rstdonecomp
CPURST#
Table 5-19. Reset Sequences and Durations
From
To
PwrGd
Duration
Source
Comment
Power on
>2 mS
Platform
Control logic on the platform must ensure that there
are at least 2 mS of stable power before PwrGd is
asserted.
PwrGd
RSTIN#
deassertion
1 mS
Intel
Intel 631xESB/632xESB I/O Controller Hub enforces
631xESB/ delay between detecting PwrGd asserted and
632xESB
I/O
releasing PCIRST# (note that Intel 631xESB/
632xESB I/O Controller Hub PCIRST# is directly
Controller connected to MCH RSTIN#).
Hub
RSTIN#
deassertion deassertion
Hard/Core
4-6 HCLK
1 mS
MCH
MCH waits for a common rising edge on all internal
clocks, then releases core reset(s).
RSTIN# FSBxRESET#
deassertion deassertion
MCH
MCH enforces delay between RSTIN# and
FSBxRESET# deassertion. ESI handshake is
incremental to the timer.
5.16
SMBus Interfaces Description
The Intel 5000X chipset MCH provides six fully functional System Management Bus
(SMBus) Revision 2.0 compliant target interfaces. These interfaces are used to support
platform level operations such as FB-DIMM memory Serial Presence Detect, PCI Hot-
Plug, and configuration of platform devices. Each of these interfaces have dedicated
uses as shown in Figure 5-28.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
Figure 5-28. MCH SM Bus Interfaces
JTAG
aster: PCI-E
ot-plug VPI
SM Bus 6
Intel® 5000P
Chipset
SM Bus 4
SM Bus 3
SM Bus 2
SM Bus 1
aster: SPD
(MCH)
ave: SM Bus
SM Bus 0
SM Buses 1, 2, 3 and 4 are dedicated to memory serial presence detect and FB-DIMM
configuration. Each bus is dedicated to a single FB-DIMM channel. SM Bus 1 is assigned
to FB-DIMM channel 0, SM Bus 2 is assigned to FB-DIMM channel 1, SM Bus 3 is
assigned to FB-DIMM channel 2, and SM Bus 4 is assigned to FB-DIMM channel 3. SM
Bus 6 is used to support PCI Express Hot-Plug.
The each SMBus interface consists of two interface pins; one a clock, and the other
serial data. Multiple initiator and target devices may be electrically present on the same
pair of signals. Each target recognizes a start signaling semantic, and recognizes its
own 7-bit address to identify pertinent bus traffic. The MCH address is hard-coded to
01100000b (60h).
The SMBus protocol allows for traffic to stop in “mid sentence,” requiring all targets to
tolerate and properly “clean up” in the event of an access sequence that is abandoned
by the initiator prior to normal completion. The MCH is compliant with this requirement.
The protocol comprehends “wait states” on read and write operations, which the MCH
takes advantage of to keep the bus busy during internal configuration space accesses.
5.16.1
Internal Access Mechanism
All SMBus accesses to internal register space are initiated via a write to the CMD byte.
Any register writes received by the MCH while a command is already in progress will
receive a NAK to prevent spurious operation. The master is no longer expected to poll
the CMD byte to prevent the obliteration a command in progress prior to issuing further
writes. The SMBus access will be delayed by stretching the clock until such time that
the data is delivered. Note that per the System Management Bus (SMBus)
Specification, Rev 2.0, this can not be longer than 25 ms. To set up an internal access,
the four ADDR bytes are programmed followed by a command indicator to execute a
read or write. Depending on the type of access, these four bytes indicate either the Bus
number, Device, Function, Extended Register Offset, and Register Offset, or the
memory-mapped region selected and the address within the region. The configuration
type access utilizes the traditional bus number, device, function, and register offset;
but in addition, also uses an extended register offset which expands the addressable
register space from 256 bytes to 4 Kilobytes. The memory-mapped type access
redefines these bytes to be a memory-mapped region selection byte, a filler byte which
is all zeroes, and then the memory address within the region. Refer to the earlier
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Functional Description
tables, which display this information. Note that the filler byte is not utilized, but
enforces that both types of accesses have the same number of address bytes, and does
allow for future expansion.
It is perfectly legal for an SMBus access to be requested while an FSB-initiated access
is already in progress. The MCH supports “wait your turn” arbitration to resolve all
collisions and overlaps, such that the access that reaches the configuration ring arbiter
first will be serviced first while the conflicting access is held off. An absolute tie at the
arbiter will be resolved in favor of the FSB. Note that SMBus accesses must be allowed
to proceed even if the internal MCH transaction handling hardware and one or more of
the other external MCH interfaces are hung or otherwise unresponsive.
5.16.2
SMBus Transaction Field Definitions
The SMBus target port has it’s own set of fields which the MCH sets when receiving an
SMBus transaction. They are not directly accessible by any means for any device.
Table 5-20. SMBus Transaction Field Summary
Position
Mnemonic
Field Name
1
2
3
4
CMD
Command
Byte Count
BYTCNT
ADDR3
ADDR2
Bus Number (Register Mode) or Destination Memory (Memory Mapped Mode)
Device / Function Number (Register Mode) or Address Offset [23:16] (Memory
Mapped Mode)
5
ADDR1
Extended Register Number (Register Mode) or Address Offset [15:8] (Memory
Mapped Mode)
6
7
ADDR0
DATA3
DATA2
DATA1
DATA0
STS
Register Number (Register Mode) or Address Offset [7:0] (Memory Mapped Mode)
Fourth Data Byte [31:24]
Third Data Byte [23:16]
Second Data Byte [15:8]
First Data Byte [7:0]
8
9
10
11
Status, only for reads
Table 5-20 indicates the sequence of data as it is presented on the SMBus following the
byte address of the MCH itself. Note that the fields can take on different meanings
depending on whether it is a configuration or memory-mapped access type. The
command indicates how to interpret the bytes.
5.16.2.1
Command Field
The command field indicates the type and size of transfer. All configuration accesses
from the SMBus port are initiated by this field. While a command is in progress, all
future writes or reads will be negative acknowledged (NAK) by the MCH to avoid having
registers overwritten while in use. The two command size fields allows more flexibility
on how the data payload is transferred, both internally and externally. The begin and
end bits support the breaking of the transaction up into smaller transfers, by defining
the start and finish of an overall transfer.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
Position
Description
7
Begin Transaction Indicator.
0 = Current transaction is NOT the first of a read or write sequence.
1 = Current transaction is the first of a read or write sequence. On a single transaction sequence
this bit is set along with the End Transaction Indicator.
6
End Transaction Indicator.
0 = Current transaction is NOT the last of a read or write sequence.
1 = Current transaction is the last of a read or write sequence. On a single transaction sequence
this bit is set along with the Begin Transaction Indicator.
5
4
Address Mode. Indicates whether memory or configuration space is being accessed in this SMBus
sequence.
0 = Memory Mapped Mode
1 = Configuration Register Mode
Packet Error Code (PEC) Enable. When set, each transaction in the sequence ends with an extra
CRC byte. The MCH would check for CRC on writes and generate CRC on reads. PEC is not
supported by the MCH.
0 = Disable
1 = Not Supported
3:2
1:0
Internal Command Size. All accesses are naturally aligned to the access width. This field specifies
the internal command to be issued by the SMBus slave logic to the MCH core.
00 = Read Dword
01 = Write Byte
10 = Write Word
11 = Write Dword
SMBus Command Size. This field specifies the SMBus command to be issued on the SMBus. This
field is used as an indication of the length of the transfer so that the slave knows when to expect
the PEC packet (if enabled).
00 = Byte
01 = Word
10 = DWord
11 = Reserved
5.16.2.2
Byte Count Field
The byte count field indicates the number of bytes following the byte count field when
performing a write or when setting up for a read. The byte count is also used, when
returning data, to indicate the number of bytes (including the status byte) which are
returned prior to the data. Note that the byte count is only transmitted for block type
accesses on SMBus. SMBus word or byte accesses do not use the byte count.
Position
Description
7:0
Byte Count. Number of bytes following the byte count for a transaction.
5.16.2.3
Address Byte 3 Field
This field should be programmed with the bus number of the desired configuration
register in the lower 5 bits for a configuration access. For a memory-mapped access,
this field selects which memory-map region is being accessed. There is no status bit to
poll to see if a transfer is in progress, because by definition if the transfer completed
when the task is done. Clock stretch is used to guarantee the transfer is truly complete.
The MCH does not support access to other logical bus numbers via the SMBus port. All
registers “attached” to the SMBus have access to all other registers that are on logical
bus#0. The MCH makes use of this knowledge to implement a modified usage of the
Bus Number register providing access to internal registers outside of the PCI
compatible configuration window.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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Functional Description
Position
Configuration Register Mode Description
Memory Mapped Mode Description
7:5
4:0
Ignored.
Memory map region to access.
01h = DMA
08h = DDR
09h = CHAP
Bus Number. Must be zero: the SMBus port
can only access devices on the MCH and all
devices are bus zero.
Others = Reserved
5.16.2.4
Address Byte 2 Field
This field indicates the Device Number and Function Number of the desired
configuration register if for a configuration type access, otherwise it should be set
to zero.
Position
Configuration Register Mode Description
Memory Mapped Mode Description
7:3
2:0
Device Number. Can only be devices on the MCH. Zeros used for padding.
Function Number.
5.16.2.5
Address Byte 1 Field
This field indicates the upper address bits for the 4K region specified by the
register offset. Only the lower bit positions of this field are used, the upper four bits
are ignored.
Position
Description
7:4
3:0
Ignored.
Extended Register Number. Upper address bits for the 4K region of register offset.
5.16.2.6
5.16.2.7
Address Byte 0 Field
This field indicates the lower eight address bits for the register with the 4K region,
regardless whether it is a configuration or memory-map type of access.
Position
Description
7:0
Register Offset.
Data Field
This field is used to receive read data or to provide write data associated with the
addressed register.
At the completion of a read command, this field will contain the data retrieved from the
addressed register. All reads will return an entire aligned DWord (32 bits) of data.
For write operations, the number of byte(s) of this 32 bit field is loaded with the desired
write data. For a byte write only bits 7:0 will be used, for a Word write only bits 15:0
will be used, and for a DWord write all 32 bits will be used.
Position
Description
Byte 3 (DATA3). Data bits [31:24] for DWord.
31:24
23:16
15:8
7:0
Byte 2 (DATA2). Data bits [23:16] for DWord.
Byte 1 (DATA1). Data bits [15:8] for DWord and Word.
Byte 0 (DATA0). Data bits [7:0] for DWord, Word and Byte.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
5.16.2.8
Status Field
For a read cycle, the returned data is preceded by one byte of status. The following
table shows how the status byte bits are defined.
Position
Description
7
Internal Time-out.
0 = SMBus request is completed within 2 ms internally
1 = SMBus request is not completed in 2 ms internally.
6
5
Ignored.
Internal Master Abort.
0 = No Internal Master Abort Detected.
1 = Detected an Internal Master Abort.
4
Internal Target Abort.
0 = No Internal Target Abort Detected.
1 = Detected an Internal Target Abort.
3:1
0
Ignored.
Successful.
0 = The last SMBus transaction was not completed successfully.
1 = The last SMBus transaction was completed successfully.
5.16.2.9
Unsupported Access Addresses
It is possible for an SMBus master to program an unsupported bit combination into the
ADDR registers. The MCH does not support such usage, and may not gracefully
terminate such accesses.
5.16.3
SMB Transaction Pictographs
The Intel 5000X chipset MCH SMBus target interface is targeted to enterprise domains.
The enterprise domain is an extension of the original SMBus desktop domain. The
following drawings are included to describe the SMBus enterprise transactions.
i
Figure 5-29. DWORD Configuration Read Protocol (SMBus Block Write / Block Read,
PEC Disabled)
S
0110_000
W A
Cmd = 11000010
A
Byte Count = 4
A
Bus Number
A
Device/Function
A
Reg Number[15:0] A
CLOCK STRETCH
A
P
Reg Number [7:0]
S
Sr
0110_000
0110_000
W A
Cmd = 11000010
Byte Count = 5
A
A
R
A
Status
A
Data[31:24]
A
Data[23:16]
A
Data[15:8]
N
P
A
Data[7:0]
Figure 5-30. DWORD Configuration Write Protocol (SMBus Block Write, PEC Disabled)
A
Bus Number
A
Device/Function
A
Reg Number[15:8]
A
Reg Number [7:0]
A
Data[31:24]
S
0110_000
W A
Cmd = 11001110
Data[16:8]
A
Byte Count = 8
Data[7:0]
A
Data[23:16]
A
A
CLOCK STRETCH A P
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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Functional Description
Figure 5-31. DWORD Memory Read Protocol (SMBus Block Write / Bock Read, PEC
Disabled)
S
0110_000
W A
Cmd = 11100010
A
Byte Count = 4
A
Destination Mem
A
Add Offset[23:16]
A
Add Offset[15:8]
A
Add Offset[7:0]
CLOCK STRETCH A P
S
Sr
0110_000
0110_000
W A
Cmd = 11100010
Byte Count = 5
A
A
Data[7:0]
R
A
Status
A
Data[31:24]
A
Data[23:16]
A
Data[15:8]
A
N P
Figure 5-32. DWORD Memory Write Protocol
Byte Count = 8
Data[7:0]
S
A
0110_000
W A
A
Cmd = 11101110
Data[16:8]
A
A
A
Destination Mem
A
Add Offset[23:16]
A
Add Offset[15:8]
A
Add Ofset[7:0]
A
Data[31:24]
CLOCK STRETCH
A P
Data[23:16]
Figure 5-33. DWORD Configuration Read Protocol (SMBus Word Write / Word Read,
PEC Disabled)
S
S
0110_000
0110_000
W
W
A
A
Cmd = 10000001
Cmd = 01000001
A
A
Bus Number
A
A
Device/Function
A P
Register Num[7:0]
CLOCK STRETCH
A P
Register Num[15:8]
S
0110_000
0110_000
W
R
A
A
Cmd = 10000001
Status
A
A
Sr
Data[31:24]
Data[15:8]
P
P
N
N
S
0110_000
0110_000
W
R
A
A
Cmd = 00000001
Data[23:16]
A
A
Sr
S
0110_000
0110_000
W
A
Cmd = 01000000
Data[7:0]
A
Sr
R
A
P
N
Figure 5-34. DWORD Configuration Write Protocol (SMBus Word Write, PEC Disabled)
S
S
0110_000
0110_000
W
W
A
A
Cmd = 10001101
Cmd = 00001101
A
A
Bus Number
A
A
Device/Function
A
P
A
P
Register Num[7:0]
Register Num[15:8]
A
P
S
S
0110_000
0110_000
W
W
A
A
Cmd = 00001101
Cmd = 01001101
A
A
A
A
Data[23:16]
Data[7:0]
Data[31:24]
Data[15:8]
CLOCK STRETCH
A P
S
S
0110_000
0110_000
W
W
A
A
Cmd = 10101101
Cmd = 00101101
A
A
Dest Mem
A
A
Add Offset[23:16]
Add Offset[7:0]
A P
A
P
Add Offset[15:8]
A
P
S
0110_000
0110_000
W
A
Cmd = 00101101
Cmd = 01101101
A
A
Data[23:16]
Data[7:0]
Data[31:24]
Data[15:8]
S
W
A
A
A
CLOCK STRETCH
A
P
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
Figure 5-35. DWORD Memory Read Protocol (SMBus Word Write / Word Read, PEC
Disabled)
S
S
0110_000
0110_000
W
W
A
A
Cmd = 10100001
Cmd = 01100001
A
A
Dest Mem
A
A
Add Offset[23:16]
Add Offset[7:0]
P
A
CLOCK STRETCH
A P
Add Offset[15:8]
S
0110_000
0110_000
W
R
A
A
Cmd = 10100001
Status
A
A
Sr
Data[31:24]
Data[15:8]
N
P
P
S
0110_000
0110_000
W
R
A
A
Cmd = 00100001
Data[23:16]
A
A
Sr
N
S
0110_000
0110_000
W
A
Cmd = 01100000
Data[7:0]
A
Sr
R
A
P
N
Figure 5-36. WORD Configuration Wrote Protocol (SMBus Byte Write, PEC Disabled)
S
0110_000
W
A
Cmd = 10001000
A
Bus Number
A
P
S
0110_000
W
A
Cmd = 00001000
Device/Function
A
P
A
A
A
P
P
S
S
0110_000
0110_000
W
W
A
A
Cmd = 00001000
Cmd = 00001000
A
A
Register Num[15:8]
Register Num[7:0]
S
S
0110_000
0110_000
W
W
A
A
Cmd = 00001000
Cmd = 01001000
A
A
A P
Data[W:X]
Data[Y:Z]
CLOCK STRETCH
A
P
5.16.4
Slave SM Bus, SM Bus 0
System Management software in a Intel 5000X chipset platform can initiate system
management accesses to the configuration registers via the Slave SM bus, SM Bus 0.
The mechanism for the Server Management (SM) software to access configuration
registers is through a SMBus Specification, Revision 2.0 compliant slave port. Some
Intel 5000X chipset components contain this slave port and allow accesses to their
configuration registers. The product specific details are compatible with the Intel
631xESB/632xESB I/O Controller Hub SMBus configuration access mechanism. Most of
the Intel 5000X chipset MCH registers can be accessed through the SMBus
configuration mechanism.
SMBus operations are made up of two major steps:
1. Writing information to registers within each component
2. Reading configuration registers from each component.
The following sections will describe the protocol for an SMBus master to access a Intel
5000X chipset platform component’s internal configuration registers. Refer to the
SMBus Specification, Revision 2.0 for the bus protocol, timings, and waveforms.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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Functional Description
Each component on the Intel 5000X chipset platform must have a unique address.
Intel 5000X chipset platform component addresses are defined in the following table.
Table 5-21. SMBus Address for Product Name Platform
SMBus Address
Component
(7:1)
Intel 5000X chipset MCH
1100_000
5.16.4.1
Supported SMBus Commands
Product Name components SMBus Rev. 2.0 slave ports support the following six SMBus
commands:
• Block Write
• Block Read
• Word Write
• Word Read
• Byte Write
• Byte Read
Sequencing these commands will initiate internal accesses to the component’s
configuration registers.
Each configuration read or write first consists of an SMBus write sequence which
initializes the Bus Number, Device Number, and so forth. The term sequence is used
since these variables may be written with a single block write or multiple word or byte
writes. Once these parameters are initialized, the SMBus master can initiate a read
sequence (which perform a configuration read) or a write sequence (which performs a
configuration write).
Each SMBus transaction has an 8-bit command driven by the master. The format for
this command is illustrated in Table 5-22 below.
Table 5-22. SMBus Command Encoding
7
6
5
4
3:2
1:0
Begin
End
Rsvd
PEC_en
Internal Command:
SMBus Command:
00 - Read DWord
01 - Write Byte
10 - Write Word
11 - Write DWord
00 - Byte
01 - Word
10 - Block
11 - Rsvd
The Begin bit indicates the first transaction of a read or write sequence.
The End bit indicates the last transaction of a read or write sequence.
The Pecan bit enables the 8-bit Packet Error Code (PEC) generation and checking logic.
The Internal Command field specifies the internal command to be issued by the SMBus
slave logic. Note that the Internal Command must remain consistent during a sequence
that accesses a configuration register. Operation cannot be guaranteed if it is not
consistent when the command setup sequence is done.
The SMBus Command field specifies the SMBus command to be issued on the bus. This
field is used as an indication of the length of transfer so the slave knows when to
expect the Packet Error Code packet.
Reserved bits should be written to zero to preserve future compatibility.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
5.16.4.2
Configuration Register Read Protocol
Configuration reads are accomplished through an SMBus write(s) and later followed by
an SMBus read. The write sequence is used to initialize the Bus Number, Device,
Function, and Register Number for the configuration access. The writing of this
information can be accomplished through any combination of the supported SMBus
write commands (Block, Word or Byte). The Internal Command field for each write
should specify Read DWord.
After all the information is set up, the last write (End bit is set) initiates an internal
configuration read. If the data is not available before the slave interface acknowledges
this last write command (ACK), the slave will “clock stretch” until the data returns to
the SMBus interface unit. If an error occurs during the internal access, the last write
command will receive a NAK. A status field indicates abnormal termination and contains
status information such as target abort, master abort, and time-outs. The status field
encoding is defined in the following table.
Table 5-23. Status Field Encoding for SMBus Reads
Bit
Description
7
Internal Time-out. This bit is set if an SMBus request is not
completed in TBD internally (2ms?)
6
Reserved
5
Internal Master Abort
Internal Target Abort
Reserved
4
3:1
0
Successful
Examples of configuration reads are illustrated below. All of these examples have
Packet Error Code (PEC) enabled. If the master does not support PEC, then bit 4 of the
command would be cleared and there would not be a PEC phase. For the definition of
the diagram conventions below, refer to the SMBus Specification, Revision 2.0. For
SMBus read transactions, the last byte of data (or the PEC byte if enabled) is NAKed by
the master to indicate the end of the transaction. For diagram compactness, “Register
Number[]” is also sometimes referred to as “Reg Number” or “Reg Num”.
Figure 5-37. SMBus Configuration Read (Block Write / Block Read, PEC Enabled)
S
11X0_XXX
W A
Cmd = 11010010
A
Byte Count = 4
A
Bus Number
A
Device/Function
A
Reg Number[7:0]
A
CLOCK
STRETCH
Reg Number [15:8]
A P
A
PEC
SMBUS write
S
11X0_XXX
11X0_XXX
W A
Cmd = 11010010
Byte Count = 5
A
A
Sr
R
A
Status
A
A
Data[31:24]
Data[7:0]
A
A
Data[23:16]
A
N P
PEC
Data[15:8]
SMBUS read
This is an example using word reads. The final data is a byte read.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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Functional Description
Figure 5-38. SMBus Configuration Read (Word Writes / Word Reads, PEC Enabled)
S
S
11X0_XXX
11X0_XXX
W
W
A
A
Cmd = 10010001
Cmd = 01010001
A
A
Bus Number
A
A
Device/Function
A
A
PEC
PEC
A P
CLOCK
STRETCH
Register Number[15:8]
Register Number[7:0]
A
P
S
11X0_XXX
11X0_XXX
W
R
A
A
Cmd = 10010001
Status
A
A
Sr
Data[31:24]
Data[15:8]
PEC
A
A
N
PEC
PEC
N
N
P
P
S
11X0_XXX
11X0_XXX
W
R
A
A
Cmd = 00010001
Data[23:16]
A
A
Sr
S
11X0_XXX
11X0_XXX
W
R
A
A
Cmd = 01010000
Data[7:0]
A
A
Sr
P
The following example uses byte reads.
Figure 5-39. SMBus Configuration Read (Write Bytes / Read Bytes, PEC Enabled)
S
S
S
S
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
W
W
W
W
A
A
A
A
Cmd = 10010000
Cmd = 00010000
Cmd = 00010000
Cmd = 01010000
A
A
A
A
Bus Number
Device/Function
Register[15:8]
Register[7:0]
A
A
A
A
PEC
PEC
PEC
PEC
A
A
A
P
P
P
CLOCK STRETCH
A
P
S
11X0_XXX
11X0_XXX
W
R
A
A
Cmd = 10010000
Status
A
A
Sr
PEC
PEC
PEC
PEC
PEC
N
N
N
N
N
P
P
P
P
P
S
11X0_XXX
11X0_XXX
W
R
A
A
Cmd = 00010000
Data[31:24]
A
A
Sr
S
11X0_XXX
11X0_XXX
W
R
A
A
Cmd = 00010000
Data[23:16]
A
A
Sr
S
11X0_XXX
11X0_XXX
W
R
A
A
Cmd = 00010000
Data[15:8]
A
A
Sr
S
11X0_XXX
11X0_XXX
W
R
A
A
Cmd = 01010000
Data[7:0]
A
A
Sr
5.16.4.3
Configuration Register Write Protocol
Configuration writes are accomplished through a series of SMBus writes. As with
configuration reads, a write sequence is first used to initialize the Bus Number, Device,
Function, and Register Number for the configuration access. The writing of this
information can be accomplished through any combination of the supported SMBus
write commands (block, word or byte).
Examples of configuration writes are illustrated below. For the definition of the diagram
conventions below, refer to the SMBus Specification, Revision 2.0.
Figure 5-40. SMBus Configuration Write (Block Write, PEC Enabled)
A
Data[31:24]
Byte Count = 8
A
Bus Number
Data[23:16]
A
Device/Function
Data[16:8]
A
Reg Number[15:8]
Data[7:0]
A
Reg Number [7:0]
PEC
S
11X0_XXX
WA Cmd = 11011110
A
CLOCK
STRETCH
A
A
A
A
A P
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
Figure 5-41. SMBus Configuration Write (Word Writes, PEC Enabled)
S
S
S
S
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
W A
W A
W A
W A
Cmd = 10011101
Cmd = 00011101
Cmd = 00011101
Cmd = 01011101
A
A
A
A
Bus Number
Register[15:8]
Data[31:24]
Data[15:8]
A
A
A
A
Device/Function
Register[7:0]
Data[23:16]
Data[7:0]
A
A
A
A
PEC
PEC
PEC
PEC
A P
A P
A P
A P
Figure 5-42. SMBus Configuration Write (Write Bytes, PEC Enabled)
S
S
S
S
S
S
S
S
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
11X0_XXX
W
W
W
W
W
W
W
W
A
A
A
A
A
A
A
A
Cmd = 10011100
Cmd = 00011100
Cmd = 00011100
Cmd = 00011100
Cmd = 00011100
Cmd = 00011100
Cmd = 00011100
Cmd = 01011100
A
A
A
A
A
A
A
A
Bus Number
Device/Function
Register[15:8]
Register[7:0]
Data[31:24]
Data[23:16]
Data[15:8]
A
A
A
A
A
A
A
A
PEC
A
A
A
A
A
A
A
A
P
PEC
PEC
PEC
PEC
PEC
PEC
PEC
P
P
P
P
P
P
P
Data[7:0]
5.16.4.4
SMBus Error Handling
The SMBus slave interface handles two types of errors: Internal and PEC. For example,
internal errors can occur when the Intel 5000P Chipset issues a configuration read on
the PCI Express port that read’s terminates in error. These errors manifest as a not-
acknowledge (NAK) for the read command (End bit is set). If an internal error occurs
during a configuration write, the final write command receives a NAK just before the
stop bit. If the master receives a NAK, the entire configuration transaction should be
reattempted.
If the master supports Packet Error Checking (PEC) and the PEC_en bit in the command
is set, then the PEC byte is checked in the slave interface. If the check indicates a
failure, then the slave will NAK the PEC packet.
5.16.4.5
SMBus Interface Reset
• The slave interface state machine can be reset by the master in two ways:
• The master holds SCL low for 25 ms cumulative. Cumulative in this case means
that all the “low time” for SCL is counted between the Start and Stop bit. If this
totals 25 ms before reaching the Stop bit, the interface is reset.
• The master holds SCL continuously high for 50 ms.
Note:
Since the configuration registers are affected by the reset pin, SMBus masters will not
be able to access the internal registers while the system is reset.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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Functional Description
5.16.5
FB-DIMM SPD Interface, SM Buses 1, 2, 3 and 4
The MCH integrates a 100 KHz SPD controller to access the FB-DIMM configuration
information. SMBus 1 is dedicated to FB-DIMM branch 0, channel 0 DIMMs. SMBus 2 is
dedicated to FB-DIMM branch 0, channel 1 DIMMs. SMBus 3 is dedicated to FB-DIMM
branch 1, channel 0 DIMMs and SMBus 4 is dedicated to FB-DIMM branch 1, channel 1
DIMMs. There can be a maximum of four SPD EEPROM’s associated with each SPD bus.
The FB-DIMM SPD interfaces are wired as depicted in Figure 5-8.
Board layout must map chip selects to SPD Slave Addresses as shown in Table 5-7. The
slave address is written to the SPDCMD configuration register.
5.16.5.1
SPD Asynchronous Handshake
The SPD bus is an asynchronous serial interface. Once software issues an SPD
command (SPDCMD.CMD = SPDW or SPDR), software is responsible for verifying
command completion before another SPD command can be issued. Software can
determine the status of an SPD command by observing the SPD configuration register.
An SPD command has completed when any one command completion field (RDO, WOD,
SBE) of the SPD configuration register is observed set to 1. An SPDR command has
successfully completed when the RDO field is observed set to 1. An SPDW command
has successfully completed when the WOD field is observed set to 1. An unsuccessful
command termination is observed when the SBE field is set to 1. The MCH will clear the
SPD configuration register command completion fields automatically whenever an
SPDR or SPDW command is initiated. Polling may begin immediately after initiating an
SPD command.
Software can determine when an SPD command is being performed by observing the
BUSY field of the SPD configuration register. When this configuration bit is observed set
to 1, the interface is executing a command.
Valid SPD data is stored in the DATA field of the SPD configuration register upon
successful completion of the SPDR command (indicated by 1 in the RDO field). Data to
be written by an SPDW command is placed in the DATA field of the SPDCMD
configuration register.
Unsuccessful command termination will occur when an EEPROM does not acknowledge
a packet at any of the required ACK points, resulting in the SBE field being set to 1.
5.16.5.2
Request Packet for SPD Random Read
Upon receiving the SPDR command, the MCH generates the Random Read Register
command sequence as shown in Figure 5-43. The returned data is then stored in the
MCH SPD configuration register in bits [7:0], and the RDO field is set to 1 by the MCH
to indicate that the data is present and that the command has completed without error.
Figure 5-43. Random Byte Read Timing
Slave Address
Byte Address
Slave Address
DATA
S
T
A
R
T
S
T
A
R
T
D
T
I
D
T
I
D
T
I
D
T
I
D
T
I
D
T
I
D
T
I
D
T
I
N
A
C
K
S
T
O
P
S
A
1
S
A
1
S
A
2
S
A
0
R
/
W
A
C
K
B
A
7
B
A
6
B
A
5
B
A
4
B
A
3
B
A
2
B
A
1
B
A
0
A
C
K
S
A
2
S
A
0
R
/
W
A
C
K
3
2
1
0
3
2
1
0
0
1
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
5.16.5.3
Request Packet for SPD Byte Write
Upon receiving the SPDW command, the MCH generates the Byte Write Register
command sequence as shown in Figure 5-44. The MCH indicates that the SIO command
has completed by setting the WOD bit of the SPD configuration register to 1.
Figure 5-44. Byte Write Register Timing
Slave Address
S
Byte Address
DATA
D
T
I
D
T
I
D
T
I
D
T
I
S
T
O
P
S
A
2
S
A
1
S
A
0
R
/
W
A
C
K
B
A
7
B
A
6
B
A
5
B
A
4
B
A
3
B
A
2
B
A
1
B
A
0
A
C
K
A
C
K
T
A
R
T
3
2
1
0
0
5.16.5.4
SPD Protocols
The MCH supports the SPD protocols shown in Table 5-24.
Table 5-24. MCH Supported SPD Protocols
MCH Supported SPD
Protocols
Random Byte Read
Byte Write
5.16.5.5
SPD Bus Time-out
If there is an error in the transaction, such that the SPD EEPROM does not signal an
acknowledge, the transaction will time out. The MCH will discard the cycle and set the
SBE bit of the SPD configuration register to 1 to indicate this error. The time-out
counter within the MCH begins counting after the last bit of data is transferred to the
DIMM, while the MCH waits for a response.
5.16.6
PCI Express Hot-Plug Support, SM Bus 6
SM Bus 6 is the PCI Express Hot-Plug port. SM Bus 6 is a Hot-Plug Virtual Pin Port (VPP)
that operates using the SM Bus Masters protocol as defined in System Management Bus
Specification 2.0.
SM Bus 6 is dedicated to support PCI Express Hot-Plug devices. Support for PCI
Express is an option described in PCI Express Base Specification, Revision 1.0a. The
PCI Express Hot-Plug model implies a hot-plug controller per port which is identified to
software as a capability of the P2P Bridge configuration space.
PCI Express hot-plug support requires that the Intel 5000X chipset MCH supports a set
of hot-plug messages (listed in Figure 5-15 and Figure 5-21) to manage the states
between the hot-plug controller and the device.
The PCI Express form factor has an impact to the level of support required of the MCH.
For example, some of the hot-plug messages are required only if the LED indicators
reside on the actual card and are accessed through the endpoint device. The Intel
5000X chipset MCH supports all of the hot-plug messages so that the platform is not
constrained to any particular form factor.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
379
Functional Description
A standard hot-plug usage model is beneficial to customers who buy systems with hot-
plug slots because many customers utilize hardware and software from different
vendors. A standard usage model allows customers to use the PCI hot-plug slots on all
of their systems without having to retrain operators.
In order to define a programming model for the PCI Standard Hot-Plug Controller
(SHPC), it is necessary to make some assumptions about the interface between a
human operator and a hot-plug slot. The SHPC programming model includes two
indicators, one optional push button, and a sensor on the manually-operated retention
latch for each supported slot.
5.16.6.1
Hot-Plug Indicators
The Standard Usage Model assumes that the platform provides two indicators per slot
(the Power Indicator and the Attention Indicator). Each indicator is in one of three
states: on, off, or blinking. Hot-plug system software has exclusive control of the
indicator states by issuing commands to the SHPC.
The SHPC controls blink frequency, duty cycle, and phase. Blinking indicators operate
at a frequency of 1.5 Hz and 50% (+/- 5%) duty cycle. Both indicators are completely
under the control of system software.
5.16.6.2
Attention Button
An Attention Button is a momentary-contact push-button, located adjacent to each
hotplug slot, that is pressed by the user to initiate a hot-insertion or a hot-removal at
that slot. The Power Indicator provides visual feedback to the human operator (if the
system software accepts the request initiated by the Attention Button) by blinking.
Once the Power Indicator begins blinking, a 5-second abort interval exists during which
a second depression of the Attention Button cancels the operation. Software has the
responsibility to implement this 5-second abort interval.
5.16.7
5.16.8
Hot-Plug Controller
PCI Express Hot-Plug requires that the Intel 5000X chipset MCH implement a Hot-Plug
controller for every Hot-Pluggable interface. The Hot-Plug controller is a capability of
the bridge configuration space and the register set is accessible through the standard
PCI capability mechanism defined in the PCI Express Base Specification, Revision 1.0a.
Details on Hot-Plug operation and flow will be described in the Intel 5000P Chipset
Software Programmer’s Guide.
PCI Express Hot-Plug Usage Model
Not all concepts from the PCI standard hot-plug definition apply directly to PCI Express
interfaces. The PCI Express specification still calls for an identical software interface in
order to facilitate adoption with minimal development overhead on this aspect of the
implementation. The largest variance from the old PCI hot-plug model is in control of
the interface itself. PCI required arbitration support for idling already connected
components, and “quick switches” to isolate the bus interface pins of a hot-plug slot.
PCI Express is a point-to-point interface, making hot-plug a degenerate case of the old
model that doesn’t require such arbiter support. Furthermore, the PCI Express
interface is inherently tolerant of hot connect or disconnect, and does not have explicit
clock or reset pins defined as a part of the bus (although they are standard pieces of
some defined PCI Express connector form factors). As a result of these differences,
some of the inherited hot-plug command and status codes are misleading when applied
to PCI Express.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
The compatible set of hot-plug registers may be accessed via memory-mapped
transactions, or via the Intel 5000X chipset MCH configuration mechanism as defined
in the configuration mechanism chapter of this document. For specific information on
the hot-plug register set, refer to the chapter on configuration register details.
The messages used for the hot-plug model are listed in Table 5-15, “PCI Express Hot-
Plug Interrupt Flow” on page 343 and Table 5-19, “MCH to Intel 631xESB/632xESB I/O
Controller Hub Port Configurations” on page 352 describe the behavior of the button
and LEDs.
5.16.9
Virtual Pin Ports
Shown in the Figure 5-1 is a high level block diagram of virtual pin ports and theoretical
maximum number of PCI Express card slots that could be supported for hot-plug
operations. In this VPP usage model, 16 slots (max) are shown in Figure 5-1 but for the
Intel 5000P Chipset Platform only 6 PCI Express slots1 will be used for the I/O hot-plug
operations.
Note: Port 0, the ESI slot, is not hot-pluggable.
Since Intel 5000X chipset MCH has only six PCI Express ports, only six hot-plug slots
should be present in a Intel 5000X chipset MCH platform. Intel 5000X chipset MCH
PCI Express virtual pin port will only process six hot-plug slots accordingly.
1. This does not include the ESI (port 0) which is not hot-pluggable.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
381
Functional Description
Figure 5-1. PCI Express Hot-Plug/VPP Block Diagram
FSB 0
FSB 1
Intel ® 5000P chipset
MSI
PEX Root Port
(P2P bridge, HPC)
ICH6/ESB
INTx
VPP
100K Hz SM Bus
A2 A1 A0
A2 A1 A0
I/O extender 0
I/O extender 1
I/O extender 7
Board Power
Manager
Button
LED
Button
LED
Button
LED
Button
LED
Button
LED
Button
LED
Slot 0
Slot 1
Slot 2
Slot 3
Slot 14
Slot 15
The Intel 5000X chipset MCH masters a 100KHz hot-plug SMBus interface thru pins
GPIOSMBCLK,and GPIOSMBDATA, for PCI Express ports that connect to a variable
number of serial to parallel I/O ports such as the Phillips PCA95551 I/O Extender. The
Intel 5000X chipset MCH only supports SMBus devices with registers mapped as per
Table 5-25. These I/O Extender components have 16 I/Os, divided into two 8-bit ports
that can be configured as inputs or outputs. The Intel 5000X chipset MCH has a
crossbar which associates each PCI Express Hot-Plug Unit (HPU) slots with one of these
8-bit ports. The mapping is defined by a Virtual Pin Port register field, PEXCTRL.VPP, for
each of the PCI Express HPU slots. The VPP register holds the SMBus address and port
number of the IO Port associated with the PCI Express HPU. A[2:0] pins on each I/O
Extender (that is, PCA9555 or compatible components) connected to the Intel 5000X
chipset MCH must strapped uniquely. Table 5-26 defines how the eight hot-plug signals
are mapped to pins on the VPP.
1. Intel 5000X chipset MCH VPP supports PCA9555 or compatible I/O Extender only.
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
.
Table 5-25. I/O Port Registers in I/O Extender supported by Intel 5000X Chipset MCH
Register
Name
Intel 5000X Chipset MCH Usage
0
1
2
3
4
5
6
7
Input Port 0
Input Port 1
Continuously Reads Input Values
Output Port 0
Continuously Writes Output Values
Not written by Intel 5000X chipset MCH
Direction set as per Table 5-26
Output Port 1
Polarity Inversion Port 0
Polarity Inversion Port 1
Configuration Port 0
Configuration Port 1
5.16.9.0.1Operation
When the Intel 5000X chipset MCH comes out of reset, the I/O ports are inactive. After
a reset, the Intel 5000X chipset MCH is not aware of how many IO Ports are connected
to it, what their addresses are, nor what PCI Express ports are hot-pluggable. The Intel
5000X chipset MCH does not master any commands on the SMBus until a hot-plug
Capable bit is set.
For a PCI Express slot, an additional DIS_VPP bit is used to differentiate card or module
hot-plug support, DIS_VPP bit needs to be set to 0 to enable hot-plug support for PCI
Express card slot.
When BIOS sets a Hot-plug Capable bit (PEXSLOTCAP.HPC and PEXCTRL.DIS_VPP for
PCI Express; HPCTL.HPC for FB-DIMM HPU), the Intel 5000X chipset MCH initializes
the associated VPP with Direction and Voltage Logic Level configuration as per
Table 5-26. VPP registers for PCI Express which do not have the hot-plug capable bit
set are invalid. Additionally, if the DIS_VPP bit is set to 1, then the corresponding VPP
register is invalid for the PCI Express slot. This is intended for PCI Express module hot-
plug which no VPP support is required. The I/O Extender’s Polarity is left at its default
value and never written, but the direction and voltage logic levels are written using the
addresses defined in Table 5-26.
When the Intel 5000X chipset MCH is not doing a direction write, it performs input
register reads and output register writes to all valid VPPs. This sequence repeats
indefinitely until a new hot-plug capability bit is set. To minimize the completion time of
this sequence and minimize complexity, both ports are always read or written. For the
maximum number of 6 IO Ports, and assuming no clock stretching, this sequence can
take up to 51ms. If new hot-plug capability bits are not being set, this is the maximum
timing uncertainty in sampling or driving these signals.
Table 5-26 describes the Hot-Plug Signals used for hot-plug.
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Functional Description
Table 5-26. Hot-Plug Signals on a Virtual Pin Port
Voltage Logic
Logic True
Meaning
Bit
Direction
Signal
Logic False Meaning
Level
ATTN LED is to
be turned ON
ATTN LED is to be
turned OFF
0
1
Output
Output
High_true
ATNLED
PWRLED
PWR LED is to
be turned ON
PWR LED is to be
turned OFF
High_true
ATTN Button is
Pressed
ATTN Button is NOT
Pressed
2
3
4
Input
Input
Input
Low_true
Low_true
low_true
BUTTON#
PWRFLT#
PRSNT#
PWR Fault in the No PWR Fault in the VRM
VRM
Card Present in
Slot
Card NOT Present in Slot
Power is to be
enabled on the
Slot
Power is NOT to be
enabled on the Slot
5
Output
high_true
PWREN
MRL is open
MRL is closed
6
7
Input
Input
low_true
low_true
MRL#
GPI#
Power good on
Slot
No Power good on Slot
The Intel 5000X chipset MCH will send Assert_intx/Deassert_intx or Assert_HPGPE/
Deassert_HPGPE messages to the ESI port as virtual pin messages to enable the Intel
631xESB/632xESB I/O Controller Hub take the appropriate action for handling the hot-
plug (legacy/ACPI interrupt mode) in non-MSI mode.
5.17
Clocking
The following section describes the Intel 5000X chipset MCH Clocks.
5.17.1
Reference Clocks
The BUSCLK, and CORECLK (herein referred to “in aggregate” as “BUSCLK”) reference
clocks, operating at 133/166/266 MHz, are supplied to the Intel 5000X chipset MCH.
These are the processor bus, core, and snoop filter PLL reference clocks. This frequency
is common between all processor bus agents. Phase matching between agents is
required. The two processor FSBs operate in phase with the core clock.
The FB-DIMM(0/1)CLK reference clocks, (herein referred to as FBDCLK) operating at
half the DDR2 frequency (operating at the SDRAM command-clock frequency, which is
the FB-DIMM packet frequency), are supplied to the Intel 5000X chipset MCH. This is
the FB-DIMM PLL reference clock. This frequency is common between the Intel 5000X
chipset MCH and DIMMs. Phase matching between agents is not required
(plesiochronous). The Intel 5000X chipset MCH and DIMMs treat this frequency
domain synchronously. The FB-DIMM unit-interval (UI) PLL outputs 12x the FBDCLK
frequency. For example, for DDR2 667 MHz DIMMs, the FBDCLK frequency is 333 MHz
and the UI (link) frequency is 4.0 GHz.
The PECLK reference clock, operating at 100 MHz, is supplied to the Intel 5000X
chipset MCH. This is the PCI Express PLL reference clock. The PCI Express flit PLL
outputs 250 MHz. The PCI Express phit PLL outputs 2.5 GHz. The phit clock frequency
must be tightly matched (mesochronous mode) between both PCI Express agents when
spectrum-spreading is not employed. The phit clock frequency is common to both PCI
Express agents when spectrum-spreading is employed. When the phit clock frequency
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
is common to both PCI Express agents, no phase matching between them is required
(plesiochronous mode). The Intel 5000X chipset MCH core treats this frequency
domain asynchronously.
The BUSCLK and FBDCLK reference clocks are derived from the same oscillator. The
PECLK reference clock may be derived from a different oscillator.
The PCI Express interfaces operate asynchronously with respect to the core clock.
Table 5-27. Intel 5000X Chipset MCH Frequencies for Processors and Core
Reference
Clock
Core
Domain
Frequency
133 MHz
BUSCLK
FSB 1X
FSB 2X
FSB 4X
BUSCLK
FSB 1X
FSB 2X
FSB 4X
BUSCLK
FSB 1X
FSB 2X
FSB 4X
BUSCLK
FSB 1X
FSB 2X
FSB 4X
133 MHz
BUSCLK
266 MHz
533 MHz
266 MHz
266 MHz
333 MHz
333 MHz
533 MHz
1,067 MHz
167 MHz
333 MHz
667 MHz
333 MHz
667 MHz
1333 MHz
Table 5-28. Intel 5000X Chipset MCH Frequencies for Memory
Reference
Clock
DDR
Domain
Frequency
533 MHz
FBD U
FBD packet
FBDCLK
3.2 GHz
266 MHz
133 MHz
4.0 GHz
333 MHz
167 MHz
4.8 GHz
400 MHz
200 MHz
FBDCLK
667 MHz
800 MHz
FBD U
FBD packet
FBDCLK
FBD U
FBD packet
FBDCLK
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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Functional Description
Table 5-29. Intel 5000X Chipset MCH Frequencies for PCI Express
Reference
Clock
Domain
Frequency
PCI Express phit
PCI Express flit
2.5 GHz
250 MHz
PECLK
PECLK
5.17.2
5.17.3
JTAG
TCK is asynchronous to core clock. For private TAP register accesses, one TCK cycle is a
minimum of 10 core cycles. The TCK high time is a minimum of 5 core cycles in
duration. The TCK low time is a minimum of 5 core cycles in duration. The possibility of
metastability during private register access is mitigated by circuit design. A
metastability hardened synchronizer will guarantee an MTBF greater than 107 years.
For public TAP register accesses, TCK operates independently of the core clock.
SMBus Clock
The SMBus clock is synchronized to the core clock. Data is driven into the Intel 5000P
Chipset with respect to the serial clock signal. Data received on the data signal with
respect to the clock signal will be synchronized to the core using a metastability
hardened synchronizer guaranteeing an MTBF greater than 107 years. The serial clock
can not be active until 10 mS after RESETI# deassertion. When inactive, the serial
clock should be deasserted (High). The serial clock frequency is 100 KHz.
5.17.4
5.17.5
GPIO Serial Bus Clock
The transmitted 100 Khz Virtual Pin Interface (VPI) clock (one of the SCL[4:0]’s) is
derived from the core clock. The PCI Express Hot-Plug signals reside on the Virtual Pin
Interface.
Clock Pins
Table 5-30. Clock Pins (Sheet 1 of 2)
Pin Name
Pin Description
BUSCLKP
Processor bus clock
BUSCLKN
Processor bus clock (Complement)
PCI Express clock
PECLKP
PECLKN
PCI Express clock (Complement)
FB-DIMM clocks
FBD{0/1}CLKP
FBD{0/1}CLKN
PLLBYPASS
PRCSPEED
VCC{0/1/2/3}AMP
VSS{0/1/2/3}AMP
VCCAPB
FB-DIMM clocks (Complement)
PLL Bypass mode
BUSCLK:CORECLK Bus Ratio Selector
Analog power supply for FB-DIMM PLLs
Analog ground for FB-DIMM PLLs
Analog power supply for processor bus PLL
Analog ground for processor bus PLL
Analog power supply for PCI Express PLLs
VSSAPB
VCCAPE
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
Table 5-30. Clock Pins (Sheet 2 of 2)
Pin Name
Pin Description
VSSAPE
Analog ground for PCI Express PLLs
Analog power supply for Core PLL
Analog ground for Core PLL
TAP clock
VCCACORE
VSSACORE
TCK
GPIOSCL
GPIO (Virtual Pin Port) clock
SMBus clock
SCL
OCPSTBP#
Debug bus data strobe
OCPSTBN#
PB{0/1}STBP[3:0]#
PB{0/1}STBN[3:0]#
PB{0/1}ADSTB[1:0]#
Debug bus data strobe (Complement)
Processor bus data strobes
Processor bus data strobes (Complements)
Processor bus address strobes
5.17.6
High Frequency Clocking Support
5.17.6.1
Spread Spectrum Support
The Intel 5000X chipset MCH PLLs will support Spread Spectrum Clocking (SSC). SSC
is a frequency modulation technique for EMI reduction. Instead of maintaining a
constant frequency, SSC modulates the clock frequency/period along a predetermined
path, that is, the modulation profile.The Intel 5000X chipset MCH is designed to
support a nominal modulation frequency of 30 KHz with a down spread of 0.5%.
5.17.6.2
5.17.6.3
Stop Clock
PLLs in the Intel 5000X chipset MCH cannot be stopped.
Jitter
The FB-DIMM UI clocks are produced by PLLs that multiply the FBDCLK frequency by
12. The PCI Express phit clocks are produced by PLLs that multiply the PECLK
frequency by 25. These multi-GHz phit clocks require ultra-clean sources, ruling out all
but specifically-crafted low-jitter clock synthesizers.
5.17.6.4
5.17.6.5
External Reference
An external crystal oscillator is the preferred source for the PLL reference clock. A
spread spectrum frequency synthesizer that meets the jitter input requirements of the
PLL is acceptable.
PLL Lock Time
All PLLs should be locked by PWRGOOD signal assertion. The reference clocks must be
stable 1ms before the assertion of the PWRGOOD signal. The assertion of the
PWRGOOD signal initiates the PLL lock process. External clocks dependent on PLLs are
GPIO clock and SMBus clock. Many JTAG private registers are dependent on core PLL-
generated clocks.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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Functional Description
5.17.6.6
Other PLL Characteristics
The PLL VCOs oscillate continually from power-up. The PLL output dividers consistently
track the VCO, providing pulses to the clock trees. Logic that does not receive an
asynchronous reset can thus be reset “synchronously”.
A “locked” PLL will only serve to prove that the feedback loop is continuous. It will not
prove that the entire clock tree is continuous.
5.17.6.7
5.17.6.8
Analog Power Supply Pins
The Intel 5000X chipset MCH incorporates seven PLLs. Each PLL requires an Analog
Vcc and Analog Vss pad and external LC filter. Therefore, there will be external LC
filters for the Intel 5000X chipset MCH. IMPORTANT: The filter is NOT to be connected
to board Vss. The ground connection of the filter will be routed through the package
and grounded to on-die Vss.
I/O Interface Metastability
PCI Express can be operated frequency-locked to the core. Flits are fifteen-sixteenths
of the core frequency in 266 MHz mode, three-quarters of the core frequency in
333 MHz mode.
However, the phase between the frequency-locked domains is not controlled. This
scheme results in the possibility of a metastability resonance where, for example, the
commands generated by the core miss setup and hold to I/O every time. This condition
can be tolerated by carefully hardened metastability design.
5.18
Error List
This section provides a summary of errors detected by the Intel 5000X chipset . In the
following table, errors are listed by the unit / interfaces. Some units / interfaces may
provide additional error logging registers.
The following table provides the list of detected errors of a the MCH.
Table 5-31. Intel 5000X chipset Error List (Sheet 1 of 7)
ERR #
in MCH
Error
Type
Error Name
Definition
Log Register
Cause / Actions
F1
Request/
Address Parity
Error
MCH monitors the address
and request parity signals
on the FSB. A parity
discrepancy over these
fields during a valid
Fatal
FERR_FAT_FSB/
Complete transaction on FSB
with response (non-hard fail
response)
NERR_FAT_FSB. NRECFSB,
NRECFSB_ADDRH,
NRECFSB_ADDRL for FERR
only.
request. MCH only detects
this error caused by CPUs.
F2
F5
Unsupported
Request or
data size on
FSB.
MCH detected an FSB
Unsupported transaction.
MCH only detects this error
caused by CPUs.
Fatal
Fatal
FERR_FAT_FSB/
NERR_FAT_FSB. NRECFSB
for FERR only.
Treat as NOP. No Data
Response or Retry by MCH
Outstanding
Deferred FSB
transaction
MCH detected that a
FERR_FAT_FSB/
NERR_FAT_FSB. NRECFSB
for FERR only
An access issued on the FSB
has timed out.
previously deferred FSB txn
has not completed with
Defer Reply within a
has timed out
specified time frame.
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
Table 5-31. Intel 5000X chipset Error List (Sheet 2 of 7)
ERR #
in MCH
Error
Type
Error Name
Definition
Log Register
Cause / Actions
F6
Data Parity
Error
MCH monitors the data/
parity signals on the FSB.
Set when the MCH detects
an parity error during the
data transfer. MCH only
detects this error caused by
CPUs.
UnCorr
FERR_NF_FSB/
NERR_NF_FSB. RECFSB for
FERR only
Received a parity error.
Poison Data and forward to
the appropriate interface.
F7
F8
F9
Detected
MCERR
MCH detected that a
UnCorr
UnCorr
Fatal
FERR_NF_FSB/
NERR_NF_FSB. based on
POC[5] setting
If (receive an MCERR)
forward the MCERR to the
other FSB bus, adhering to
the MCERR protocol
processor issued an MCERR.
B-INIT
MCH detected that a
processor issued an B-INIT.
FERR_NF_FSB/
NERR_NF_FSB. based on
POC[5] setting
Do not propagate to other
FSB bus, reset arb. unit, and
programatically reset
platform
FSB protocol
Error
BND detected FSB protocol
error, for example, HitM on
BIL and HitM on EWB.
FERR_FAT_FSB/
Complete transaction on FSB
with response (IWB as in the
example)
NERR_FAT_FSB. NRECFSB,
NRECFSB_ADDRH,
NRECFSB_ADDRL for FERR
only.
IO0
PCI Express -
Data Link
Layer Protocol
Error
MCH detects a DL layer
protocol error from the
DLLP.
Default= Log PEX_FAT_FERR/NERR
Log Header of DLLP Packet.
Fatal
or PEX_NF_COR_FERR/
NERR based on their
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
(Check
UNCERR
SEV)
respective Error types and
Severity (UNCERRSEV)
Log RPERRSTS for IO1,
IO11 and IO17.
Log UNCERRSTS for their
respective Error Types.
IO1
IO2
PCI Express -
Received Fatal
Error Message
MCH received a Fatal error
message from the south
bridge.
Fatal
Log header of packets with
errors
PCI Express -
Received
Unsupported
Request
Received an unsupported
request, similar to master
abort.
Default= Log the first error pointer
Log header of packet
UnCorr
(Check
for UNCERRSTS in
AERRCAPCTRL.
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
UNCERR Log CORRERSTS for their
SEV)
respective Error Types.
Log PEXDEVSTS for IO12
and other I/O errors based
on UNCERSEV(
IO4
IO5
PCI Express -
Poisoned TLP
Received a poisoned
transaction layer packet
from the South Bridge.
Default=
UnCorr
(Check
UNCERR
SEV)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
PCI Express -
Flow Control
Protocol Error
MCH has detected a PCI
Express Flow Control
Protocol Error
Default=
Fatal
(Check
UNCERR
SEV)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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Functional Description
Table 5-31. Intel 5000X chipset Error List (Sheet 3 of 7)
ERR #
in MCH
Error
Type
Error Name
Definition
Log Register
Cause / Actions
IO6
PCI Express -
Completion
Time-out
Pending transaction was
ACKed in the data link layer
but not within the time
limit.
Default= Log PEX_FAT_FERR/NERR
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
UnCorr
or PEX_NF_COR_FERR/
NERR based on their
respective Error types and
Severity (UNCERRSEV)
(Check
UNCERR
SEV)
Log RPERRSTS for IO1,
IO11 and IO17.
Log UNCERRSTS for their
respective Error Types.
Log the first error pointer
for UNCERRSTS in
AERRCAPCTRL.
IO7
PCI Express -
Completer
Abort
Received return CA status
for horrible error on the
component. This is
equivalent to a target abort
on PCI.
Default=
UnCorr
(Check
UNCERR
SEV)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log CORRERSTS for their
Default= respective Error Types.
IO8
PCI Express -
Unexpected
Completion
Error
Received a Completion
RequestorID that matches
the requestor but the Tag
does not match any
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
UnCorr
(Check
Log PEXDEVSTS for IO12
and other I/O errors based
UNCERR on UNCERSEV
SEV)
pending entries.
IO9
PCI Express -
Malformed TLP packet that does not follow
the TLP formation rules.
Received a transaction layer
Default=
UnCorr
(Check
UNCERR
SEV)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
IO10
IO11
PCI Express -
Receive Buffer
Overflow Error allow.
Receiver gets more data or
transactions than credits
Default=
Fatal
(Check
UNCERR
SEV)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
PCI Express -
Received
NonFatal Error
Message
MCH received a NonFatal
error message from the
south bridge.
UnCorr
Log header of packets with
errors
IO12
IO13
PCI Express -
Receiver Error
Log header of packets with
errors
Corr
Corr
Log header of packets with
errors
PCI Express -
Bad TLP Error
Received bad CRC or a bad
sequence number in a
transport layer packet.
Log header of packets with
errors
IO14
IO15
PCI Express -
BAD DLLP
Received bad CRC in a data
link layer packet.
Corr
Corr
Log header of packets with
errors
PCI Express -
Replay_Num
Rollover
Replay maximum count for
the Retry Buffer has been
exceeded.
Log header of packets with
errors
IO16
IO17
PCI Express -
Replay Timer
Time-out
Replay timer timed out
waiting for an Ack or Nak
DLLP.
Corr
Corr
Log header of packets with
errors
PCI Express -
Received
Correctable
Error Message
MCH received a correctable
error message from the
south bridge.
Log header of packets with
errors
IO18
ESI reset time- Did not receive ESI
Fatal
Log PEX_FAT_FERR/NERR
Deassert processor RESET#.
Necessary to prevent
processor thermal runaway.
out
CPU_Reset_Done_Ack or
CPU_Reset_Done_Ack_Secr
ets messages within T
10max
after assertion of processor
RESET# while PWRGOOD
was asserted
®
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
Table 5-31. Intel 5000X chipset Error List (Sheet 4 of 7)
ERR #
in MCH
Error
Type
Error Name
Definition
Log Register
Cause / Actions
B1
MCH -Parity
Error from DM
(Do not
Include
Poisoned Data) interface)
MCH detected internal DM
parity error. (This error was
not generated by receiving
bad data from an external
Fatal
FERR_FAT_INT/
NERR_FAT_INT and
NRECINT
log DM Entry on FERR.
B2
B3
MCH-Multi-Tag MCH detected multiple hits
Hit from snoop in the SF lookup on any SF
filter on any SF lookup port
Fatal
Fatal
FERR_FAT_INT/
NERR_FAT_INT and NRECSF and Presence vector on
FERR.
Log, Hit/Miss, Set, Tag, State
lookup port
MCH-
MCH detected a cache
coherency protocol error for
EWB.
FERR_FAT_INT/
NERR_FAT_INT NRECINT
and NRECSF
Log CE entry on FERR
Coherency
Violation Error
Any requestor not in “E/M”
state in the SF
B4
B5
Virtual Pin
MCH detected an error on
Fatal
FERR_FAT_INT/
NERR_FAT_INT and
NRECINT
Interface Error the virtual pin interface
MCH-Address
Map Error
MCH detected address
mapping error due to
software programming
error. The errors are
described in system
address map chapter.
UnCorr
FERR_NF_INT/
NERR_NF_INT and
NRECINT
MCH might malfunction.
B6
Single bit ECC
MCH detected a hit in SF
Corr
FERR_NF_INT/
NERR_NF_INT and RECSF
Log, Hit/Miss, Set, Tag, State
and Presence vector on
FERR.
error on snoop lookup and the entry has a
filter lookup
single bit ECC error, or
MCH detected a miss in SF
lookup and the victim entry
has a single bit error.
B7
B8
Multiple bit
ECC error on
snoop filter
lookup
MCH detected a multiple
ECC error in any of the
ways during snoop filter
lookup
Fatal
FERR_FAT_INT/
NERR_FAT_INT and NRECSF and Presence vector on
FERR.
Log, Hit/Miss, Set, Tag, State
Write Post
Queue Parity
Error
Intel 5000X chipset MCH
detected a cache coherency Fatal
protocol error for a BIL.
Non
FERR_FAT_INT/
NERR_FAT_INT NRECINT
and NRECSF
Log CE entry on FERR This
applies to SF enable mode
only
Any requestor from the bus
that issued BIL not present
in the SF.
M1
M2
Alert on FB-
DIMM Replay
or Fast Reset
Time-out
The MCH detected an
Fatal
FERR_FAT_FBD
NERR_FAT_FBD
NRECMEM
Memory read: poison to
requestor, update NRECMEM
Configuration read: master-
abort to requestor, update
CFGLOG
“Alert” on a non-redundant
replay or hit a time-out on
non-redundant fast reset
before normal completion
NRECFGLOG
All others: drop.
Northbound
CRC error on
FB-DIMM
The MCH detected a
northbound CRC error on a
replay
Fatal
FERR_FAT_FBD
NERR_FAT_FBD
NRECMEM
NRECFGLOG
NRECFBD
Memory read: poison to
requestor, update NRECMEM
Configuration read: master-
abort to requestor, update
CFGLOG
Replay
All others: drop.
M3
M4
Tmid thermal
event with
intelligent
throttling
Intelligent throttling is
disabled and the thermal
sensor transitions from
“below Tmid” to “above
Tmid”.
Fatal
FERR_FAT_FBD
NERR_FAT_FBD
disabled
Uncorrectable
Data ECC Error uncorrectable data ECC
on FB-DIMM
Replay
The MCH detected an
Uncorr
FERR_NF_FBD
NERR_NF_FBD
Poison to requestor.
Don’t log error again... it was
logged when the replay was
launched.
error during replay of the
head of the FB-DIMM replay
queue
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Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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Functional Description
Table 5-31. Intel 5000X chipset Error List (Sheet 5 of 7)
ERR #
Error
Type
Error Name
Definition
Log Register
Cause / Actions
Re-read once.
If ECC is uncorrectable with
good CRC after re-read, then
poison the data in memory
and to the requestor.
If correctable after re-read,
then correct the data in
memory and to the
requestor.
in MCH
M5
Aliased
The MCH determined that a
normally “correctable” error
could be an aliased (x8
only) full device failure plus
an additional single bit
error.
Rec
FERR_NF_FBD
NERR_NF_FBD
RECMEM
REDMEM
UERRCNT
Uncorrectable
Non-Mirrored
Demand Data
ECC Error
M6
Aliased
Uncorrectable
Mirrored
Demand Data
ECC Error
In mirrored mode, the MCH
determined that a normally
“correctable” error could be
an aliased (x8 only) full
device failure plus an
Rec
FERR_NF_FBD
NERR_NF_FBD
RECMEM
First redundant read to
branch X fails.
MCH performs a fast reset on
both branches X and Y.
If both branches pass, then
replay on branch Y.
REDMEM
UERRCNT
additional single bit error.
If branch X fails the disable
branch X and replay on
branch Y.
If both branches fail or
branch Y fails disable branch
X and poison data. Under
these conditions we get an
M1 error.
Second redundant read to
branch X fails with an
uncorrectable error.
Perform fast reset and
disable branch X and replay
on branch Y.
M7
Aliased
Uncorrectable
Spare-Copy
Data ECC Error normally “correctable” error
could be an aliased (x8
only) full device failure plus
an additional single bit
error.
During a Sparing copy read
from the failing DIMM the
MCH determined that a
Rec
FERR_NF_FBD
NERR_NF_FBD
RECMEM
Re-read once.
If ECC is uncorrectable with
good CRC after re-read, then
poison the data in the spare
DIMM or the off-line branch.
If correctable after re-read,
then correct the data in the
spare DIMM or the off-line
branch.
REDMEM
UERRCNT
M8
M9
Aliased
During a Patrol Scrub, the
MCH determined that a
normally “correctable” error
could be an aliased (x8
only) full device failure plus
an additional single bit
error.
Rec
Rec
FERR_NF_FBD
NERR_NF_FBD
RECMEM
The patrol read is dropped.
Uncorrectable
Patrol Data
ECC Error
REDMEM
UERRCNT
Non-Aliased
Uncorrectable
Non-Mirrored
Demand Data
ECC Error
The MCH detected
uncorrectable data with
good CRC.
FERR_NF_FBD
NERR_NF_FBD
RECMEM
Re-read once.
If ECC is uncorrectable with
good CRC after re-read, then
poison the data in memory
and to the requestor.
UERRCNT
If correctable after re-read,
then correct the data in
memory and to the
requestor.
Does not include poisoned
northbound data.
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Table 5-31. Intel 5000X chipset Error List (Sheet 6 of 7)
ERR #
in MCH
Error
Type
Error Name
Definition
Log Register
Cause / Actions
M10
Non-Aliased
Uncorrectable
Mirrored
Demand Data
ECC Error
In mirrored mode, the MCH
detected uncorrectable or
poisoned data with good
CRC.
Rec
FERR_NF_FBD
NERR_NF_FBD
RECMEM
First redundant read to
branch X fails.
MCH performs a fast reset on
both branches X and Y.
If both branches pass, then
replay on branch Y.
UERRCNT
If branch X fails the disable
branch X and replay on
branch Y.
If both branches fail or
branch Y fails disable branch
X and poison data. Under
these conditions we get an
M1 error.
Second redundant read to
branch X fails with an
uncorrectable error.
Perform fast reset and
disable branch X and replay
on branch Y
M11
Non-Aliased
Uncorrectable
Spare-Copy
Data ECC Error DIMM rank during a sparing
copy.
The MCH detected
uncorrectable data with
good CRC from the failing
Rec
FERR_NF_FBD
NERR_NF_FBD
RECMEM
Re-read once.
If ECC is uncorrectable with
good CRC after re-read, then
poison the data in the spare
DIMM or the off-line branch.
UERRCNT
If correctable after re-read,
then correct the data in the
spare DIMM or the off-line
branch.
Does not include poisoned
northbound data.
M12
M13
Non-Aliased
Uncorrectable
Patrol Data
ECC Error
During a patrol scrub, the
MCH detected uncorrectable
data with good CRC.
Rec
Rec
FERR_NF_FBD
NERR_NF_FBD
RECMEM
The patrol read is dropped.
UERRCNT
Non-Retry or
redundant FB-
DIMM Memory
Alert, or
redundant fast memory access packet or
reset time-out
The MCH detected an
FERR_NF_FBD
NERR_NF_FBD
RECMEM
Non-redundant or 1st
attempt: Fast reset and
Initiate replay.
Redundant replay or fast
reset time-out: auto-
degrade.
“Alert” or corrupted write
acknowledgement on the
first attempt at an FB-DIMM
on the replay of a
redundant FB-DIMM
memory access packet.
M14
Non-Retry FB-
DIMM
Configuration
Alert
The MCH detected an
“Alert” or corrupted write
acknowledgement on the
first attempt at an FB-DIMM
configuration write
Rec
FERR_NF_FBD
NERR_NF_FBD
CFGLOG
1st attempt: Fast reset and
Initiate replay.
Redundant replay: auto-
degrade.
command or on the replay
of a redundant FB-DIMM
configuration write
command
M15
Non-Retry FB-
DIMM
Northbound
CRC error on
read data
The MCH detected a
Rec
FERR_NF_FBD
NERR_NF_FBD
RECFBD
1st redundant memory read:
re-read once from other
image.
Replay redundant memory
read: auto-degrade
All others: fast reset and
initiate replay from the same
image, branch, or channel.
northbound CRC error on
the first attempt at a
configuration or memory
read or on the replay of a
redundant configuration or
memory read.
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Table 5-31. Intel 5000X chipset Error List (Sheet 7 of 7)
ERR #
in MCH
Error
Type
Error Name
Definition
Log Register
Cause / Actions
M17
M18
M19
M20
M21
Correctable
Non-Mirrored
Demand Data
ECC Error.
The MCH detected
correctable data.
Corr
Corr
Corr
Corr
Corr
FERR_NF_FBD
NERR_NF_FBD
RECMEM
REDMEM
CERRCNT
BADCNT
Correct the data in memory
and to the requestor.
BADRANK
Correctable
Mirrored
Demand Data
ECC Error
The MCH detected
correctable data.
FERR_NF_FBD
NERR_NF_FBD
RECMEM
REDMEM
CERRCNT
BADCNT
BADRANK
Correct the data in memory
and to the requestor.
Correctable
Spare-Copy
Data ECC Error failing DIMM rank during a
sparing copy.
The MCH detected
correctable data from the
FERR_NF_FBD
NERR_NF_FBD
RECMEM
Correct the data in the spare
DIMM or the off-line branch.
REDMEM
CERRCNT
BADCNT
BADRANK
Correctable
Patrol Data
ECC Error
During a patrol scrub, the
MCH detected correctable
data.
FERR_NF_FBD
NERR_NF_FBD
RECMEM
Correct the data in memory.
REDMEM
CERRCNT
BADCNT
BADRANK
FB-DIMM
The MCH detected a
northbound CRC error on a
Sync Status
FERR_NF_FBD
NERR_NF_FBD
RECFBD
Drop. If sync was issued to
prepare a fast reset for alert
recovery then replay any
queued configuration
command destined for an
alerting DIMM or a DIMM with
a corrupted status CRC.
Northbound
CRC error on
FB-DIMM Sync
Status
WARNING: Possible double
DIMM configuration
command execution may
incur undesirable side-
effects.
M22
SPD protocol
Error
The MCH detected an SPD
interface error.
Corr
FERR_NF_FBD
NERR_NF_FBD
Successive correction
attempts performed by
software.
M27
M28
DIMM-Spare
Copy start
Triggered DIMM-Spare copy
DIMM-Spare copy
Corr
Corr
FERR_NF_FBD
NERR_NF_FBD
Start DIMM-spare copy
DIMM-Spare
Copy complete completed normally
FERR_NF_FBD
NERR_NF_FBD
No Action
§
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6 Testability
6.1
JTAG Port
Each component in the Intel 5000P Chipset includes a Test Access Port (TAP) slave
which complies with the IEEE 1149.1 (JTAG) test architecture standard. Basic
functionality of the 1149.1- compatible test logic is described here, but this document
does not describe the IEEE 1149.1 standard in detail. For this, the reader is referred to
the published standard1, and to the many books currently available on the subject.
6.1.1
JTAG Access to Configuration Space
JTAG has become a name that is synonymous with the IEEE 1149.1 test access port
(TAP). Besides the boundary scan capabilities for low speed buses and pins, it provides
an inexpensive serial interface port to up/download data to and from the chip.
Throughout this document any reference to JTAG will imply the test access port (TAP)
and the private chains that it is connected too, unless specifically mentioning the
boundary scan attributes.
The feature described here is a JTAG private data chain that initiate a configuration
request to the components configuration arbitration logic. During platform debug it is
helpful to have a back door access to register space to determine correct configuration
states. The In-Target Probe (ITP) provides an effective observation capability that links
the hardware and the user together to examine and control a number of DFT and
debug features.
Access to a component’s configuration space must be non-blocking to a JTAG initiated
configuration request to the Intel 5000P Chipset MCH’s register space. Since the Intel
5000P Chipset MCH can source configuration transactions to other components and an
errant configuration transaction that could potentially hang the system and prevent a
JTAG access to the Intel 5000P Chipset MCH’s configuration space. An additional chain
is provided to ensure the ITP tool has unconditional access privilege to the Intel 5000P
Chipset MCH in case there are configuration transaction hangs from another source.
6.1.2
TAP Signals
The TAP logic is accessed serially through five dedicated pins on each component as
shown in Table 6-1.
Table 6-1.
TAP Signal Definitions
TCK
TAP Clock input
TMS
TDI
Test Mode Select. Controls the TAP finite state machine.
Test Data Input. The serial input for test instructions and data.
Test Data Output. The serial output for the test data.
Test Reset input.
TDO
TRST#
TMS, TDI and TDO operate synchronously with TCK (which is independent of all other
clocks). TRST# is an asynchronous reset input signal. This 5-pin interface operates as
defined in the 1149.1 specification. A simplified block diagram of the TAP used in the
Intel 5000P Chipset components is shown in Figure 6-1.
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Figure 6-1. Simplified TAP Controller Block Diagram
The TAP logic consists of a finite state machine controller, a serially-accessible
instruction register, instruction decode logic and data registers. The set of data
registers includes those described in the 1149.1 standard (the bypass register, device
ID register, and so forth.), plus Intel 5000X chipset-specific additions.
6.1.3
Accessing the TAP Logic
The TAP is accessed through an 1149.1-compliant TAP controller finite state machine,
which is illustrated in Figure 6-1. The two major branches represent access to either
the TAP Instruction Register or to one of the component-specific data registers. The
TMS pin controls the progress through the state machine. TAP instructions and test
data are loaded serially (in the Shift-IR and Shift-DR states, respectively) using the TDI
pin. A brief description of the controller’s states follows; refer to the IEEE 1149.1
standard for more detailed descriptions.
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Figure 6-2. TAP Controller State Machine
The following list describes the behavior of each state in the TAP.
Test-Logic-Reset: In this state, the test logic is disabled so that normal operation of
the device can continue unhindered. The instruction in the Instruction Register is forced
to IDCODE. The controller is guaranteed to enter Test- Logic-Reset when the TMS input
is held active for at least five clocks. The controller also enters this state immediately
when TRST# is pulled active. The TAP controller cannot leave this state as long as
TRST# is held active.
Run-Test/Idle: The TAP idle state. All test registers retain their previous values.
Capture-IR: In this state, the shift register contained in the Instruction Register loads
a fixed value (of which the two least significant bits are “01”) on the rising edge of TCK.
The parallel, latched output of the Instruction Register (“current instruction”) does not
change.
Shift-IR: The shift register contained in the Instruction Register is connected between
TDI and TDO and is shifted one stage toward its serial output on each rising edge of
TCK. The output arrives at TDO on the falling edge of TCK. The current instruction does
not change.
Pause-IR: Allows shifting of the Instruction Register to be temporarily halted. The
current instruction does not change.
Update-IR: The instruction which has been shifted into the Instruction Register is
latched onto the parallel output of the Instruction Register on the falling edge of TCK.
Once the new instruction has been latched, it remains the current instruction until the
next Update-IR (or until the TAP controller state machine is reset).
Capture-DR: In this state, the Data Register selected by the current instruction may
capture data at its parallel inputs.
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Shift-DR: The Data Register connected between TDI and TDO as a result of selection by
the current instruction is shifted one stage toward its serial output on each rising edge
of TCK. The output arrives at TDO on the falling edge of TCK. The parallel, latched
output of the selected Data Register does not change while new data is being shifted in.
Pause-DR: Allows shifting of the selected Data Register to be temporarily halted
without stopping TCK. All registers retain their previous values.
Update-DR: Data from the shift register path is loaded into the latched parallel
outputs of the selected Data Register (if applicable) on the falling edge of TCK. This and
Test-Logic-Reset are the only controller states in which the latched paralleled outputs of
a data register can change.
All other states are temporary controller states, used to advance the controller between
active states. During such temporary states, all test registers retain their prior values.
6.1.4
Reset Behavior of the TAP
The TAP and its related hardware are reset by transitioning the TAP controller finite
state machine into the Test-Logic-Reset state. Once in this state, all of the reset actions
listed in Figure 6-2 are performed. The TAP is completely disabled upon reset (i.e. by
resetting the TAP, the device will function as though the TAP did not exist).
Table 6-2.
TAP Reset Actions
Related TAP Instructions
(instr equivalent to reset is highlighted)
TAP Logic Affected
TAP Reset State Action
TAP instruction register
Boundary scan logic
TDO pin
IDCODE
Disabled
Tri-stated
—
EXTEST
—
The TAP can be transitioned to the Test-Logic-Reset state in one of two ways:
• Assert the TRST# pin at any time. This asynchronously resets the TAP controller.
Cycling power on a device does not ensure that the TAP is reset. System designers
must utilize one of the two methods stated above to reset the TAP. The method used
depends on the manufacturing and debug requirements of the system.
6.1.5
6.1.6
Clocking the TAP
There is no minimum frequency at which the Intel 5000P Chipset TAP will operate.
Because the private chains are synchronized to the local core clock of that chain there
is a maximum rate relative to the core that the interface can operate. The ratio is 12:1
providing a maximum rate of 27 MHz for a core frequency of 333 MHz.
Accessing the Instruction Register
Figure 6-3 shows the (simplified) physical implementation of the TAP instruction
register. This register consists of a 7-bit shift register (connected between TDI and
TDO), and the actual instruction register (which is loaded in parallel from the shift
register). The parallel output of the TAP instruction register goes to the TAP instruction
decoder.
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Figure 6-3. TAP Instruction Register
Figure 6-4 shows the operation of the instruction register during the Capture-IR, Shift-
IR and Update-IR states. Shaded areas indicate the bits that are updated. In
Capture-IR, the shift register portion of the instruction register is loaded in parallel with
the fixed value “0000001”. In Shift-IR, the shift register portion of the instruction
register forms a serial data path between TDI and TDO. In Update-IR, the shift register
contents are latched in parallel into the actual instruction register. Note that the only
time the outputs of the actual instruction register change is during Update-IR.
Therefore, a new instruction shifted into the TAP does not take effect until the Update-
IR state is visited.
Figure 6-4. TAP Instruction Register Operation
Figure 6-5 illustrates the timing when loading the BYPASS instruction (opcode
1111111b) into the TAP instruction register. Vertical arrows on the figure show the
specific clock edges on which the Capture-IR, Shift-IR and Update-IR actions actually
take place. Capture-IR (which preloads the instruction register with 0000001b) and
Shift-IR operate on rising edges of TCK, and Update- IR (which updates the actual
instruction register) takes place on the falling edge of TCK.
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Figure 6-5. TAP Instruction Register Access
6.1.7
Accessing the Data Registers
The test data registers in the Intel 5000P chipset components are architected in the
same way as the instruction register, with components (that is, either the “capture” or
“update” functionality) removed from the basic structure as needed. Data registers are
accessed just as the instruction register is, only using the “select-DR-scan” branch of
the TAP finite state machine in Table 6-2. A specific data register is selected for access
by each TAP instruction. Note that the only controller states in which data register
contents actually change are Capture-DR, Shift-DR, Update-DR and Run-Test/ Idle. For
each of the TAP instructions described below, therefore, it is noted what operation (if
any) occurs in the selected data register in each of these four states.
6.1.8
Public TAP Instructions
Table 6-3 contains descriptions of the encoding and operation of the public TAP
instructions. There are four 1149.1-defined instructions implemented in the Intel
5000P Chipset devices. These instructions select from among three different TAP data
registers – the boundary scan, device ID, and bypass registers. The public instructions
can be executed with only the standard connection of the JTAG port pins. This means
the only clock required will be TCK. Full details of the operation of these instructions
can be found in the 1149.1 standard. The opcodes are 1149.1-compliant, and are
consistent with the Intel-standard encodings. A brief description of each instruction
follows. For more thorough descriptions refer to the IEEE 1149.1 specification.
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Table 6-3.
Public TAP Instructions
Instructio
n
Data Register
Encoding
Description
Selected
BYPASS
EXTEST
11111111
Boundary Scan
The BYPASS command selects the Bypass register, a single bit
register connected between the TDI and TDO pins. This allows
more rapid movement of test data to and from other
components in the system.
00000000
00000001
Boundary Scan
Boundary Scan
The EXTEST instruction allows circuitry or wiring external to
the devices to be tested. Boundary Scan register cells at
outputs are used to apply stimulus, while Boundary Scan
register cells at inputs are used to capture data.
SAMPLE/
PRELOAD
The SAMPLE/PRELOAD instruction is used to allow scanning of
the Boundary Scan register without causing interference to the
normal operation of the device. Two functions can be
performed by use of the SAMPLE/PRELOAD instruction:
1.
SAMPLE allows a snapshot of the data flowing into and
out of the device to be taken without affecting the normal
operation of the device.
2.
PRELOAD allows an initial pattern to be placed into the
Boundary Scan register cells. This allows initial known
data to be present prior to the selection of another
Boundary Scan test operation.
IDCODE
0000010
IDCODE
The IDCODE instruction is forced into the parallel output
latches of the instruction register during the Test-Logic-Tap
state. This allows the Device Identification register to be
selected by manipulation of the broadcast TMS and TCK signals
for testing purposes, as well as by a conventional instruction
register scan operation.
CLAMP
HIGHZ
0000100
0001000
Bypass
Bypass
This allows static “guarding” values to be set into components
that are not specifically being tested while maintaining the
Bypass register as the serial path through the device.
The HIGHZ instruction is used to force all outputs of the device
(except TDO) into a high impedance state. This instruction
shall select the Bypass register to be connected between TDI
and TDO in the Shift-DR controller state.
6.1.9
Public Data Instructions
This section describes the data registers that are accessed by the public and private
instructions. Data shifts into all chains through the MSB of the data register as shown in
Figure 6-6 which is the same as the instruction register.
Figure 6-6. TAP Data Register
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6.1.10
Public Data Register Control
Table 6-4 define the actions that occur in the selected data register in controller states
that can alter data register contents. If a TAP state does not affect the selected data
register, then the corresponding table entry will be blank. Not all data registers have a
parallel output latch. All data registers have a parallel input latch. Several table entries
are still under investigation.
Table 6-4.
Actions of Public TAP Instructions During Various TAP States
Instruction
Bypass
Capture-DR
Shift-DR
Update-DR
Reset Bypass Register
Reset Bypass Register
Shift Bypass register
Shift Bypass register
Shift ID register
HighZ
IDcode
Load device ID into
register
Extest
Load input pin values into Shift Boundary Scan shift Load Boundary Scan shift
Boundary Scan shift
register
register
register into Boundary
Scan register; drive pins
accordingly
Sample/Preload
Load pin values into
Boundary Scan shift
register
Shift Boundary Scan shift Load Boundary Scan shift
register
register into Boundary
Scan register
6.1.11
Bypass Register
This register provides the minimal length path between TDI and TDO. It is loaded with a
logical 0 during the Capture-DR state. The Bypass Register is a single bit register and is
used to provide a minimum-length serial path through the device. This allows more
rapid movement of test data to and from other components in the system. When in
Bypass Mode, the operation of the test logic shall have no effect on the operation of the
devices normal logic. Refer to Figure 6-7 for an implementation example.
6.1.11.1
Bypass Register Definition
Figure 6-7. Bypass Register Implementation
6.1.12
Device ID Register
This register contains the device identification code in the format shown in Table 6-5
Three fields are predefined as the version number (stepping number), the
manufacturer’s identification code, and a logical 1 field. The component identification
field is sub-divided into 3 fields. The Product Segment field identifies if the component
is intended for CPU, laptop, desktop, server, etc. Product Type further defines the
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component within a segment by stating it to be a CPU, memory, chipset, etc. The last
field is a sequential component number assignment. This value will be maintained as
sequential as possible depending on when each component’s request was satisfied in
the corporate database.
Table 6-5.
Intel® 5000P chipset Device ID Codes
Component Identification Fields
Versio
n
Manufacturing
ID
EntireCode
(hex)
Device
“1”
Product
Segment
Product
Type
Component
Number
4
6
5
5
11
1
1
32
Intel
5000P
Chipset
MCH – A0
0000
000100
01000
01000
00000001001
0x0118013
6.1.12.1
Device ID Register
JTAG encode: 0000010
Bit
Attr
Default
0000
Description
31:28
R
Version: This number changes for each stepping including metal
“dash” steppings.
The most significant 2 bits are the stepping number: 00 A-step;
01 B-step, 10 C-step, and 11 D-step.
The least significant 2 bits is the revision within a stepping.
27:22
21:17
16:12
R
R
R
000100
Product Segment: Number assigned that determines the market
segment into which this component belongs. Since this format is
new, the value for chipset is shown with others as an example.
R&D:000 000
CPU:100 000
Desktop:010 000
Laptop:001 000
Server:000 100
etc.
01000
Product Type: Number assigned to further define the component
within the market segment. Since this format is new, the value
for chipset is shown with others as an example.
Test:00 000
CPU:10 010
Memory:00 100
Modem:00 101
Chipset:01 000
etc.
Listed in next
column
Component Number: Sequential listing based on request to
database.
Intel® 5000P chipset MCH:01000b
11:1
0
R
R
00000001001
1
Manufacturing ID: This number is assigned to Intel.
‘1’
6.1.13
Boundary Scan Register
The following requirements apply to those interfaces that continue to support boundary
scan (bscan) or the miscellaneous I/O signals.
• Each signal or clock pin (with the exception of the TAP specific pins TCK, TDI, TDO,
TMS, & TRST#) will have an associated Boundary-Scan Register Cell. Differential
Driver or Receiver Pin Pairs that cannot be used independently shall be considered
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a single pin (that is, one Boundary-Scan Register Cell after the
differential receiver).
• Internal Signals which control the direction of I/O pins shall also have associated
Boundary- Scan Register Cells.
• Each Output pin (with the exception of TDO) shall be able to be driven to a tristate
condition for HIGHZ test.
6.2
Extended Debug Port (XDP)
The Extended Debug Port is covered in the XDP Design Guide.
§
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Electrical Characteristics
7 Electrical Characteristics
This chapter provides the absolute maximum ratings and DC Characteristics for the
Intel 5000P Chipset MCH.
7.1
Absolute Maximum Ratings
Table 7-1 lists the maximum environmental stress ratings for the Intel 5000P Chipset
MCH. Functional operation at or exceeding the absolute maximum and minimum
ratings is neither implied nor guaranteed. Functional operating parameters are listed in
the AC tables.
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only. Operating beyond the “operating conditions” is
not recommended and extended exposure beyond “operating conditions” may affect
reliability.
Table 7-1.
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
T
Storage Temperature
-40.0
-0.50
-0.30
85.0
1.85
1.85
°C
V
storage
Vcc
MCH Supply Voltage with respect to Vss
V
FSB Termination Supply Voltage input with respect to Vss
V
TT
7.1.1
Thermal Characteristics
For information on thermal characteristics, consult the Intel® 5000P/5000V Chipset
Memory Controller Hub (MCH) Thermal/Mechanical Design Guidelines.
7.1.2
Power Characteristics
Table 7-2.
Operating Condition Power Supply Rails
DC
Min
DC
Max
AC
Max
Symbol
Parameter
AC Min
Nom
Unit Notes
V
Host AGTL+ Termination
Voltage
1.140
1.164
1.20
1.236 1.260
4.8
V
A
1,2
TT
I
Host AGTL+ Termination
Current
2.6
TT
VCC
ICC
ICC
ICC
1.5V MCH Supply Voltage
1.5V MCH Supply Current
1.5V MCH Supply Current
1.5V MCH Supply Current
1.425
1.455
1.53
17.6
19.3
15.3
1.575 1.605
22.0
V
A
A
A
1, 2
3
24.1
4
19.1
5
AMB VCC
Other
1.5V FBD Supply Voltage
3.3V Supply Voltage
1.425
1.5
3.3
1.575
V
V
6
1.455
1.605
3.1185
3,3825
3.2175
3,481
5
Notes:
1.
Under no circumstances may the supply voltage go past the AC min/max window. The supply voltage may
go outside the DC min/max window for transient events,
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2.
The supply voltage must stay within the DC min/max window in a static system (no active switching). The
DC window only assumes voltage regulator ripple and motherboard induced noise
3.
4.
5.
6.
Intel 5000P Chipset MCH with 4 active FB-DIMM channels. Total Core + I/O current drawn off the 1.5 Vrail
Intel 5000X Chipset MCH with 4 active FB-DIMM channels. Total Core + I/O current drawn off the 1.5 V rail
Intel 5000V Chipset MCH with 2 active FB-DIMM channels. Total Core + I/O current drawn off the 1.5 V rail
Tolerances are specified at the AMB DRAM package(s) and FB-DIMM voltage regulator designs should be
scaled accordingly to support these tolerances for the 1.5. DC min/max per the JEDEC specification. AC
tolerances from VR loop BW ~30 kHz to 1 MHz.
Table 7-3.
Analog and Bandgap Voltage and Current Specifications
Uni
t
Symbol
Parameter
Min
Nom
Max
Notes
VCCA
Analog MCH Supply Voltage
Analog MCH Supply Current
Analog PLL Voltage
1.4055
1.5
1.545
28.9
1.545
28.9
1.545
52
V
1
ICCA
mA
V
FSBVCCA
FSBICCA
FBDVCCA
FBDICCA
PEVCCA
PEICCA
1.4055
1.4055
1.4055
2.425
1.5
1.5
1.5
2.5
1
Analog PLL Current
mA
Analog FBD Voltage
Analog FBD Current
mA
V
Analog PCI Express Voltage
Analog PCI Express Current
1.545
48
1
1
1
mA
V
PEVCCBG
Analog PCI Express Bandgap
Voltage
2.575
PEICCBG
Analog PCI Express Bandgap
Current
600
μA
1
1.
The analog voltage is intended to be a filtered copy of its associated supply voltage. Refer to the New Dual-
Core Intel® Xeon® Processor-Based Servers Platform Design Guide (PDG) for the recommended
implementation and frequency response requirements of each filter.
7.2
DC Characteristics
This section documents the DC characteristics of the MCH. The specifications are split
into five sections:
• Clocks
• FSB Interface
• FB-DIMM (Fully Buffered DIMM) Memory Interface1
• PCI Express/ ESI Interface
• Miscellaneous Interface
— SMBus Interface
— JTAG Interface
®
1. Refer to the Intel 6400/6402 Advanced Memory Buffered External Design Specification (EDS)
Addendum for additional details on the FB-DIMM interface.
®
406
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Electrical Characteristics
7.2.1
Clock DC Characteristics
Table 7-4.
Clock DC Characteristics
Signal
Note
s
Symbol
Parameter
Group
Min
Nom
Max
Unit
333 MHz FSB Clock (CORECLKN / CORECLKP)
V
V
V
V
(h)
(h)
(h)
(h)
Input Low Voltage
-0.150
0.660
0
0.150
0.850
V
1
IL
Input High Voltage
0.700
V
V
V
IH
Absolute Crossing Point
Relative Crossing Point
0.250
0.550
2, 7
7, 8
CROSS(abs)
CROSS(rel)
0.250 + 0.5
0.550 - 0.5
x (0.700 - V
x (V
– 0.700)
)
Havg
Havg
ΔV
(h)
(h)
(h)
(h)
(h)
Range of Crossing Points
Overshoot
0.140
V
V
V
V
V
CROSS
V
V
V
V
V
+ 0.300
3
4
5
6
OS
IH
Undershoot
-0.300
0.200
– 0.100
US
Ringback Margin
Threshold Region
RBM
TR
V
V
+ 0.100
CROSS
CROSS
266 MHz FSB Clock (CORECLKN / CORECLKP)
V
V
V
V
(h)
(h)
(h)
(h)
Input Low Voltage
-0.150
0.660
0
0.150
V
V
V
V
1
IL
Input High Voltage
0.700
0.850
0.550
IH
Absolute Crossing Point
Relative Crossing Point
0.250
2, 7
7, 8
CROSS(abs)
CROSS(rel)
0.250 + 0.5
0.550 - 0.5
x (0.700 - V
x (V
– 0.700)
)
Havg
Havg
ΔV
(h)
(h)
(h)
(h)
(h)
Range of Crossing Points
Overshoot
0.140
V
V
CROSS
V
V
V
V
V
+ 0.300
3
4
5
6
OS
IH
Undershoot
-0.300
0.200
– 0.100
V
V
V
US
Ringback Margin
Threshold Region
RBM
TR
V
V
+ 0.100
CROSS
CROSS
100 MHz PCI Express Clock (PECLKN / PECLKP)
V
V
V
V
(q)
(q)
(q)
(q)
Input Low Voltage
-0.150
0.660
0
V
V
V
V
IL
Input High Voltage
0.700
0.850
IH
Absolute Crossing Point
Relative Crossing Point
0.250
0.550
2, 7
CROSS(abs)
CROSS(rel)
0.250 + 0.5
0.550 + 0.5
7, 8
x (V
– 0.700)
x (V
– 0.700)
Havg
Havg
ΔV
(q)
(q)
(q)
(q)
(q)
Range of Crossing Points
Overshoot
0.140
+ 0.300
V
V
V
V
V
1, 2
3
CROSS
V
V
V
V
V
OS
IH
Undershoot
-0.300
0.200
– 0.100
4
US
Ringback Margin
Threshold Region
5
RBM
TR
V
V
+ 0.100
6
CROSS
CROSS
133/167 MHz FB-DIMM Clock (FBDxxCLKN/ FBDxxCLKP)
V
V
V
V
(k)
(k)
(k)
(k)
Input Low Voltage
-0.150
0.660
0
V
V
V
V
IL
Input High Voltage
0.700
0.850
IH
Absolute Crossing Point
Relative Crossing Point
0.250
0.550
2, 7
7, 8
CROSS(abs)
CROSS(rel)
0.250 + 0.5
0.550 + 0.5
x (V
– 0.700)
x (V
– 0.700)
Havg
Havg
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
407
Electrical Characteristics
Notes:
®
®
®
1.
Refer to chapter 5 of Intel 5000P chipset/Intel 5000V chipset and Intel 5000X chipset External Design Specification
(EDS) Addendum.
2.
Crossing voltage is defined as the instantaneous voltage when the rising edge of CORECLKP is equal to the falling edge of
CORECLKN.
3.
4.
5.
Overshoot is defined as the absolute value of the maximum voltage.
Undershoot is defined as the absolute value of the minimum voltage.
Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum
Falling Edge Ringback. Both maximum Rising and Falling Ringbacks should not cross the threshold region.
Threshold Region is defined as a region centered around the crossing point voltage in which the differential receiver switches.
It includes input threshold hysteresis.
6.
7.
8.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
VHavg (the average of V ) can be measured directly using “Vtop” on Agilent scopes and “High” on Tektronix scopes.
IH
7.2.2
FSB Interface DC Characteristics
Table 7-5.
FSB Interface DC Characteristics
Signal
Group
Note
s
Symbol
Parameter
Min
Nom
Max
Unit
V
V
V
V
Host AGTL+ Input Low
Voltage
0
GTLREF –
V
1, 2
1, 3
IL
IH
OL
OH
OL
LI
•
•
•
•
•
•
•
•
•
(a) (b)
(0.1 × V
)
TT
Host AGTL+ Input High
Voltage
GTLREF +
(0.1 × V
V
V
V
TT
(a) (b)
(a) (c)
(a) (c)
(a) (c)
(a) (b)
(a) (b)
)
TT
Host AGTL+ Output Low
Voltage
0.4
Host AGTL+ Output High
Voltage
0.90 x V
V
V
4
TT
TT
I
I
I
Host AGTL+ Output Low
Current
V
/ (0.50 x
mA
uA
uA
Ω
8
TT
R
+ R
)
tt_min
on_min
Host AGTL+ Input Leakage
Current
n/a
n/a
7
+/- 200
+/- 200
11
5, 6
5, 6
Host AGTL+ Output
Leakage Current
LO
R
Buffer on Resistance
on
GTLREF
Host Bus Reference
Voltage
(0.98 x 0.67) x V
45
0.67 x
(1.02 x 0.67) x V
55
V
1
7
TT
TT
(e)
V
TT
R
Host Termination
Resistance Common Clock,
Async on Stripline
50
Ω
TT
•
Notes:
1.
GTLREF is equivalent to FSBxFSBVREF. GTLREF is generated from V on the baseboard by a voltage divider or 1%
resistors.
TT
2.
3.
4.
V
V
V
is defined as the voltage range at a receiving agent that will be interpreted as an electrical low value.
is defined as the voltage range at a receiving agent that will be interpreted as an electrical high value.
IL
IH
IH
and V
may experience excursions above V
However, input signal drivers must comply with the signal quality
OH
CC.
specifications chapter in the document.
5.
6.
7.
8.
Leakage to VSS with land held at V
TT.
Leakage to V with land held at 300 mV.
TT
Use 50 ohm ±15% for all Microstrip.
I
is defined as current when Output Low. The formula computes the total current drawn by the driver from VR (Voltage
OL
Regulator). Half of the total current goes through RTT on the chipset, and another half goes through the RTT on the CPU (the
End-Bus-Agency).
®
408
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Electrical Characteristics
7.2.3
FB-DIMM DC Characteristics
Table 7-6.
FB-DIMM Transmitter (Tx) Output DC Characteristics
Signal
Group
Note
s
Symbol
Parameter
Min
Nom
Max
Unit
V
V
V
(i) (j)
DC Common Mode Output
Voltage for Small Voltage
Swing
135
280
mV
1
TX-CM_S
TX-CM_L
TX-SE
(i) (j)
DC Common Mode Output
Voltage for Large Voltage
Swing
375
700
mV
1
(i) (j)
(i) (j)
(i) (j)
Single-ended Voltage
0
mV
dB
dB
RLTX-Diff
RLTX-CM
Differential Return Loss
-10
-6
Common Mode Return
Loss
Z
(i) (j)
(i) (j)
D+/D- TX Impedance
Difference
4%
20
Ω
2
TX-MATCH-DC
Z
D+/D- TX Common Mode
High Impedance State
5
kΩ
TX-COM-ESI-
IMP-DC
Notes:
1.
2.
Defined as: V
= DC
of | V
+ V
| / 2.
TX-CM
(avg)
TX-D+
TX-D-
TX DC impedance matching between D+ and D- on a given lane.
Table 7-7.
FB-DIMM Receiver (Rx) Output DC Characteristics
Signal
Group
Note
s
Symbol
Parameter
Min
Nom
Max
Unit
V
Z
(i) (j)
DC Common Mode Input
Voltage
190
400
mV
1
2
RX-CM
(i) (j)
D+/D- RX Impedance
Difference
4%
Ω
RX-MATCH-DC
RLRX-Diff
RLRX-CM
(i) (j)
(i) (j)
Differential Return Loss
-10
-6
dB
dB
Common Mode Return
Loss
Notes:
1.
2.
DC (avg) of | V
+ V
| / 2.
RX-D-
RX-D+
RX DC impedance matching between D+ and D- on a given lane.
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
409
Electrical Characteristics
7.2.4
PCI Express/ ESI Interface DC Characteristics
Table 7-8.
PCI Express/ ESI Differential Transmitter (Tx) Output DC Characteristics
Signal
Group
Note
s
Symbol
Parameter
Min
Nom
Max
Unit
VTX-DIF-DC
(o) (p)
Differential Peak to Peak
Output Voltage
0.8
1.2
V
2
2
VTX-CM-DC-
ACTIVE-
IDLE-DELTA
(o) (p)
(o) (p)
Absolute Delta of DC
Common Mode Voltage
During L0 and Electrical
Idle
0
100
mV
VTX-CM-DC-
LINE-DELTA
Absolute Delta of DC
Common Mode Voltage
between D+ and D-
0
25
mV
2
2
VTX-IDLE-
DIFFp
(o) (p)
(o) (p)
Electrical Idle Differential
Peak Output Voltage
20
mV
mV
VTX-RCV-
DETECT
The amount of voltage
change allowed during
Receiver Detection
600
VTX-DC-CM
ITX-SHORT
ZTX-DIFF-DC
(o) (p)
(o) (p)
(o) (p)
(o) (p)
The TX DC Common Mode
Voltage
0
3.6
90
V
mA
Ω
2
The Short Circuit Current
Limit
DC Differential TX
Impedance
80
40
100
120
ZTX-DC
Transmitter DC Impedance
Ω
Notes:
1.
2.
No test load is necessarily associated with this value.
Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive
TX UIs.
Table 7-9.
PCI Express/ ESI Differential Receiver (Rx) Input DC Characteristics
Signal
Group
Note
s
Symbol
Parameter
Min
Nom
Max
Unit
ZRX-DIFF-DC
(o) (p)
DC Differential Input
Impedance
80
100
120
Ω
5
ZRX-DC
(o) (p)
(o) (p)
DC Input Impedance
40
50
60
Ω
Ω
2, 3
6
ZRX-High-
Imp-DC
Power Down DC Input
Common Mode Impedance
200k
VRX-IDLE-
DET-DIFFp
(o) (p)
Electrical Idle Detect
Threshold
65
175
mV
Notes:
1.
2.
No test load is necessarily associated with this value.
Specified at the measurement point and measured over any 250 consecutive UIs. If the clock to the RX and TX are not
derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the
eye diagram.
3.
A TRX-EYE=0.40UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total.6 UI jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
4.
The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to
300mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The
reference impedance for return loss measurements for is 50 ohms to ground for both the D+ and D- line (that is, as measured
by a Vector Network Analyzer with 50 ohm probes). Note: that the series capacitors CTX is optional for the return loss
measurement.
®
410
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Electrical Characteristics
5.
6.
Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM)
there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port.
The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps
ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be
measured at 300 mV above the RX ground.
7.2.5
Miscellaneous DC Characteristics
Table 7-10. SMBus DC Characteristics
Signal
Group
Note
s
Symbol
Parameter
Min
Nom
Max
Unit
V
V
V
(w)
(w)
(w)
(w)
(w)
(w)
Input High Voltage
Input Low Voltage
Output Low Voltage
Output Low Current
Leakage Current
Pad Capacitance
2.1
V
V
IH
0.8
0.4
4
IL
V
1
OL
I
I
mA
μA
pF
OL
10
10
Leak
C
Pad
Notes:
1. At Vol max, Iol = max.
Table 7-11. JTAG DC Characteristics
Signal
Group
Note
s
Symbol
Parameter
Min
Nom
Max
Unit
V
V
V
I
(y)
(y)
Input High Voltage
Input Low Voltage
Output Low Voltage
Leakage Current
0.9
V
V
IH
0.5
0.4
2.9
IL
(z)
V
OL
(y) (z)
μA
Leak
Table 7-12. 1.5 V CMOS DC Characteristics
Signal
Group
Note
s
Symbol
Parameter
Min
Nom
Max
Unit
V
V
V
V
I
(d) (cc)
(d) (cc)
(cc)
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Leakage Current
1.0
-0.2
1.1
1.6
0.5
V
V
IH
IL
V
OH
OL
(cc)
0.4
70
V
(cc)
μA
V
Leak
V
(d) (cc)
Input Damage Thresholds
-0.2
1.6
ABS
Table 7-13. 3.3 V CMOS DC Characteristics (Sheet 1 of 2)
Signal
Group
Note
s
Symbol
Parameter
Min
Nom
Max
Unit
V
V
V
(dd)
(dd)
(ee)
Input High Voltage
Input Low Voltage
Output High Voltage
2.1
V
V
V
IH
0.8
IL
OH
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
411
Electrical Characteristics
Table 7-13. 3.3 V CMOS DC Characteristics (Sheet 2 of 2)
Signal
Group
Note
s
Symbol
Parameter
Min
Nom
Max
Unit
V
I
(ee)
(ee)
(dd)
Output Low Voltage
Leakage Current
0.4
10
V
μA
V
OL
Leak
V
Input Damage Thresholds
-0.3
3.5
ABS
§
®
412
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
8 Ballout and Package
Information
8.1
Intel 5000X Chipset MCH Ballout
The following section presents preliminary ballout information for the Intel 5000X
Chipset MCH. This ballout is subject to change and is to be used for informational
purposes only.
Figure 8-1. Intel 5000X Chipset Quadrant Map
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1716 15 14 1312 11 10 9 8
7
6
4
2 1
3
5
AV
AU
AT
AR
AP
AN
AV
AU
AT
AR
AP
AN
AM
AL
AK
AM
AL
AK
FSB0
FSB1
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
PE0
PE3
Vcc Core
LWS
W
V
U
W
V
U
T
R
P
N
T
R
P
N
PE2
PE7
RSVD
M
L
K
M
L
K
FBD
J
H
J
H
G
F
E
G
F
E
PE5
Misc
PE4
D
C
D
C
B
A
B
A
PE6
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1312 11 10 9 8
7
6
4
2 1
3
5
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
413
Ballout and Package Information
Figure 8-2. Intel 5000X Chipset MCH Ballout Left Side (Top View)
38
37
36
35
34
33
32
31
30
29
28
27
26
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
VSS
VSS
FSB0DEFER#
FSB0BPRI#
VSS
FSB0HITM#
VSS
VSS
FSB0RS[0]#
FSB0RS[2]#
VSS
FSB0BNR#
VSS
VSS
FSB0A[17]#
FSB0A[21]#
VSS
RSVD
VSS
VSS
VSS
FSB0D[21]#
FSB0D[19]#
FSBSLWCRES
FSBCRES
VSS
FSB0HIT#
FSB0TRDY#
VSS
FSB0ADS#
FSB0DRDY#
VSS
FSB0A[25]#
FSB0A[24]#
VSS
VSS
FSB0D[22]#
FSB0DP[1]#
RSVD
FSB0LOCK#
FSB0DBSY#
VSS
FSB0A[23]#
FSB0A[19]#
VSS
FSB0DSTBP[1]# FSB0DSTBN[1]# VSS
FSBODTCRES
FSB0D[20]#
VSS
FSB0DP[0]#
FSB0DP[2]#
VSS
FSB0BPM[4]#
RSVD
FSB0D[27]#
VSS
FSB0DBI[1]#
VSS
FSB0D[23]#
FSB0D[26]#
VSS
FSB0D[18]#
FSB0D[24]#
VSS
VSS
RSVD
FSB0BPM[5]#
FSB0DP[3]#
VSS
FSB0A[7]#
FSB0A[6]#
VSS
FSB0D[16]#
FSB0D[12]#
VSS
FSB0D[5]#
VSS
FSB0RESET#
FSB0VREF
VSS
VSS
FSB0RSP#
FSB0VREF
VSS
FSB0D[28]#
FSB0D[50]#
VSS
FSB0D[31]#
FSB0D[52]#
VSS
FSB0D[29]#
FSB0D[17]#
VSS
RSVD
FSB0BREQ[0]#
FSB0RS[1]#
VSS
FSB0D[51]#
FSB0D[53]#
VSS
FSB0D[25]#
FSB0D[30]#
VSS
FSB0DBI[0]#
FSB0D[7]#
FSB0D[1]#
FSB0D[3]#
VSS
FSB0REQ[0]#
FSB0AP[1]#
VSS
FSB0DSTBP[0]# FSB0DSTBN[0]# VSS
FSB0D[6]#
FSB0D[10]#
VSS
FSB0BINIT#
FSB0MCERR#
VSS
FSB0D[56]#
FSB0D[57]#
VSS
FSB0D[55]#
FSB0DBI[3]#
VSS
FSB0D[49]#
FSB0D[15]#
VSS
FSB0D[8]#
FSB0D[11]#
VSS
FSB0D[0]#
FSB0D[2]#
VSS
FSB0D[61]#
FSB0D[60]#
VSS
FSB0DSTBP[3]# FSB0DSTBN[3]# VSS
FSB0D[9]#
FSB0D[36]#
VSS
FSB0D[4]#
FSB0D[13]#
VSS
FSB0AP[0]#
FSB0BREQ[1]#
VSS
FSB0D[54]#
VSS
VSS
FSB0D[32]#
FSB0D[37]#
VSS
FSB0D[33]#
FSB0DBI[2]#
VSS
FSB0D[14]#
VSS
FSB0D[59]#
FSB0D[58]#
VSS
FSB0D[48]#
FSB0D[63]#
VSS
FSB0VREF
FSB0D[34]#
VSS
FSB0D[35]#
FSB0D[40]#
FSB0D[45]#
FSB0D[47]#
VSS
FSB0D[62]#
VSS
VCCSF
FSB0D[39]#
FSB0D[43]#
FSB0D[46]#
VSS
VSS
VTT
FSB0D[38]#
VSS
FSB0DSTBP[2]# FSB0DSTBN[2]# VSS
FSB0D[41]#
FSB0D[42]#
VSS
VSS
VCCSF
VSS
FBD0SBON[6]
FBD0SBOP[6]
VSS
TESTHI
FBD0SBOP[8]
FBD0SBON[7]
VSS
FBD0SBON[8]
VSS
VSS
FSB0D[44]#
FBD0NBIP[2]
VSS
VSS
VSS
VCCSF
FBD0SBON[5]
FBD0SBOP[5]
VSS
VSS
FBD0SBOP[7]
FBD0SBON[9]
VSS
FBD0NBIN[2]
FBD0SBOP[2]
VSS
VSS
VSS
VSS
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VSS
FBD0SBOP[9]
FBD0SBOP[4]
VSS
FBD0SBON[2]
FBD0SBON[3]
VSS
VSS
VSS
VSS
VCCFBD
FBD0NBIP[0]
VSS
FBD0SBON[4]
VSS
FBD0SBOP[3]
FBD0NBIP[9]
VSS
FBD0NBIN[1]
FBD0SBON[0]
VSS
FBD0NBIP[1]
VSS
VSS
FBD0NBIN[0]
FBD0NBIP[5]
VSS
W
V
W
V
FBD0SBON[1]
FBD0SBOP[1]
VSS
FBD0NBIN[9]
FBD0NBIP[10]
VSS
FBD0SBOP[0]
FBD0NBIP[7]
VSS
FBD0NBIN[5]
FBD0NBIP[13]
VSS
VSS
FBD0NBIN[10]
FBD0NBIP[11]
VSS
FBD0NBIN[7]
FBD0NBIP[8]
VSS
FBD0NBIN[13]
FBD0NBIP[12]
VSS
FBD0NBIP[3]
FBD0NBIN[3]
VCCFBD
VSS
U
U
FBD0NBIN[11]
RSVD
FBD0NBIN[8]
FBD01VSSA
VSS
FBD0NBIN[12]
FBD0NBIP[6]
VSS
FBD0NBIP[4]
FBD0NBIN[4]
VSS
T
T
FBD01CLKN
FBD01CLKP
VSS
FBD01VCCA
FBD1SBON[6]
VSS
FBD0NBIN[6]
FBD1SBON[8]
VSS
VSS
R
R
VSS
FBD1SBOP[6]
FBD1SBON[5]
VSS
FBD1SBOP[8]
FBD1SBON[7]
VSS
VSS
VSS
P
P
FBD1SBOP[5]
FBD1SBON[9]
VSS
FBD1SBOP[7]
FBD1SBOP[4]
VSS
VSS
VSS
VSS
FBD1NBIN[0]
FBD1NBIP[3]
VSS
FBD1NBIP[0]
VSS
VCCFBD
VCCFBD
FBD1NBIP[1]
VSS
N
N
FBD1SBOP[9]
VSS
FBD1SBON[4]
FBD1SBOP[3]
VSS
FBD1NBIN[12]
FBD1NBIP[12]
VSS
VSS
VSS
FBD1NBIN[3]
FBD1NBIP[4]
VSS
M
M
FBD1SBON[3]
FBD1SBOP[1]
VSS
FBD1NBIN[6]
FBD1NBIP[6]
VSS
VSS
FBD1NBIN[4]
FBD1NBIP[5]
VSS
FBD1NBIN[1]
FBD1NBIP[2]
VSS
L
L
FBD1SBON[2]
FBD1SBOP[2]
VSS
FBD1SBON[1]
VSS
FBD1NBIN[7]
FBD1NBIP[7]
VSS
FBD1NBIN[5]
FBD1NBIP[13]
VSS
FBD1NBIN[2]
VSS
K
K
FBD1NBIN[8]
FBD1NBIP[8]
VSS
FBD1NBIN[13]
FBD2SBOP[8]
VSS
VSS
VSS
J
J
FBD1SBON[0]
FBD1NBIN[10]
VSS
FBD1SBOP[0]
FBD1NBIP[10]
VSS
FBD2SBON[8]
FBD2SBOP[7]
VSS
VSS
VSS
VSS
VSS
VSS
H
H
FBD1NBIN[11]
FBD1NBIP[11]
VSS
FBD2SBON[7]
FBD2SBOP[6]
VSS
VSS
VSS
VSS
VSS
VSS
G
G
FBD2SBON[6]
VSS
VSS
VSS
FBD2SBON[0]
FBD2SBOP[1]
VSS
FBD2SBOP[0]
VSS
VSS
FBD3SBOP[1]
VSS
F
F
FBD1NBIN[9]
FBD1NBIP[9]
FBDICOMPBIAS VSS
FBD2SBON[4]
FBD2SBOP[9]
VSS
FBD2SBOP[4]
VSS
VSS
FBD2SBON[1]
FBD2SBOP[2]
VSS
FBD23VSSA
FBD23VCCA
VSS
E
E
FBD2NBIN[11]
FBD2NBIP[11]
VSS
FBDBGBIASEXT FBDRESIN
VSS
FBD2SBON[9]
FBD2SBON[2]
FBD2SBOP[3]
FBD2NBIP[13]
FBD2NBIN[13]
VSS
FBD23CLKN
FBD23CLKP
FBD2NBIP[3]
FBD2NBIN[3]
VSS
VSS
D
D
FBD2NBIN[10]
FBD2NBIP[10]
VSS
VSS
FBD2SBON[5]
VSS
FBD2SBOP[5]
FBD2NBIP[7]
FBD2NBIN[7]
VSS
FBD2SBON[3]
VSS
RSVD
FBD3NBIN[11]
VSS
C
C
FBD2NBIP[9]
FBD2NBIN[9]
VSS
VSS
VSS
VSS
VSS
B
B
FBD2NBIP[8]
FBD2NBIN[8]
35
FBD2NBIP[6]
FBD2NBIN[6]
33
FBD2NBIP[12]
FBD2NBIN[12]
32
FBD2NBIP[5]
FBD2NBIN[5]
30
FBD2NBIP[4]
FBD2NBIN[4]
29
FBD2NBIP[2]
FBD2NBIN[2]
27
FBD2NBIP[1]
FBD2NBIN[1]
26
A
A
38
37
36
34
31
28
®
414
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Figure 8-3. Intel 5000X Chipset MCH Ballout Center (Top View)
25
24
23
22
21
20
19
18
17
16
15
14
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
FSB0A[28]#
FSB0A[22]#
VSS
FSB0A[31]#
VSS
VSS
FSB0A[35]#
FSB0A[34]#
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
RSVD
VSS
VSS
VSS
FSB0A[29]#
FSB0A[30]#
VSS
FSBVCCA
COREVCCA
VSS
COREVSSA
VSS
FSB0A[27]#
FSB0A[20]#
VSS
FSB1VREF
VSS
FSB0A[26]#
FSB0A[18]#
VSS
FSB0A[33]#
FSB0A[32]#
VSS
RSVD
FSB0ADSTB[1]#
RSVD
CORECLKN
CORECLKP
VSS
FSB1D[55]#
VSS
FSB1D[47]#
FSB1D[50]#
VSS
FSB0A[4]#
RSVD
FSB1D[53]#
FSB1D[51]#
VSS
FSB0A[5]#
FSB0A[3]#
VSS
VSS
FSB0A[9]#
FSB0A[12]#
VSS
FSB1D[49]#
FSB1D[56]#
VSS
VSS
FSB0ADSTB[0]#
RSVD
VCC
FSB1D[52]#
FSB1DSTBN[3]#
VSS
FSB0REQ[2]#
FSB0REQ[3]#
VSS
RSVD
VSS
FSB1DSTBP[3]#
FSB1D[60]#
VSS
FSB0REQ[4]#
FSB0REQ[1]#
VSS
VSS
FSB0A[11]#
FSB0A[13]#
VSS
FSB1D[61]#
FSB1D[54]#
VSS
FSB0A[8]#
FSB0A[15]#
VSS
VSS
FSB1D[48]#
FSB1D[62]#
VSS
FSB0A[10]#
VSS
VSS
FSB1D[59]#
FSB1D[58]#
VTT
FSB0A[14]#
VTT
FSB0A[16]#
VTT
VSS
FSB1D[63]#
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCCSF
VSS
VCC
VSS
VCC
VSS
VCC
VTT
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VSSSEN
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCCSF
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCCPE
W
V
W
V
VSS
VCC
VSS
VCC
VSS
VCC
VCCPE
VCC
VSS
VCC
VSS
VCC
VSS
VCCPE
U
U
VSS
VCC
VSS
VCC
VSS
VCC
VCCPE
T
T
VCC
VSS
VCC
VSS
VCC
VSS
VCCPE
R
R
VSS
VCC
VSS
VCC
VSS
VCC
VCCPE
P
P
VCC
VSS
VCC
VSS
VCC
VSS
VCCPE
N
N
VCCFBD
VCCFBD
VCCSEN
VSS
VCCFBD
VCCFBD
VCCFBD
VCCFBD
FBD3SBON[3]
VCCFBD
FBD3SBOP[4]
FBD3NBIP[9]
VCCFBD
FBD3NBIP[7]
FBD3NBIN[7]
VSS
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VSS
VCCFBD
VCCFBD
VCCFBD
VCCFBD
FBD3SBOP[5]
FBD3SBON[9]
VSS
VCCFBD
VCCFBD
VCCFBD
VSS
VCC
VSS
VCCPE
VCCPE
M
M
VCC
VCC
VCCPE
VCCPE
L
L
VCC
VCC
VCCPE
VCCPE
K
K
FBD3SBOP[8]
VSS
FBD3SBON[8]
FBD3SBON[7]
FBD3SBOP[7]
VSS
VSS
VSS
SPD1SMBDATA
XDPSLWCRES
SPD3SMBCLK
VSS
CFGSMBCLK
CFGSMBDATA
VSS
J
J
VSS
FBD3SBOP[3]
FBD3SBON[2]
VSS
FBD3SBON[5]
VCCFBD
FBD3NBIP[0]
FBD3NBIN[0]
VCCFBD
FBD3NBIP[13]
FBD3NBIN[13]
VSS
VSS
SPD1SMBCLK
SPD3SMBDATA
TESTHI_V3REF
VSS
H
H
FBD3SBOP[2]
FBD3SBON[1]
VCCFBD
FBD3NBIN[10]
FBD3NBIP[11]
FBD2NBIP[0]
FBD2NBIN[0]
VSS
FBD3SBOP[9]
FBD3SBON[4]
VSS
FBD3SBON[6]
FBD3SBOP[6]
VSS
PWRGOOD
RESETI#
TESTHI_V3REF
VSS
G
G
XDPODTCRES
XDPCOMCRES
XDPD[5]#
VSS
F
F
FBD3NBIN[9]
FBD3NBIP[10]
VSS
VSS
FBD3NBIP[1]
FBD3NBIN[1]
VSS
SPD2SMBCLK
SPD2SMBDATA
XDPD[8]#
VSS
E
E
FBD3SBON[0]
FBD3SBOP[0]
VSS
VSS
FBD3NBIN[5]
FBD3NBIP[5]
VSS
XDPD[15]#
XDPD[14]#
XDPD[12]#
VSS
D
D
VSS
FBD3NBIN[2]
FBD3NBIP[2]
VSS
C
C
VSS
FBD3NBIP[12]
FBD3NBIN[12]
VSS
FBD3NBIN[3]
FBD3NBIP[3]
VSS
XDPDSTBP#
XDPD[7]#
XDPD[10]#
14
B
B
FBD3NBIN[8]
FBD3NBIP[8]
24
FBD3NBIP[6]
FBD3NBIN[6]
22
FBD3NBIN[4]
FBD3NBIP[4]
19
XDPD[9]#
XDPD[13]#
15
A
A
VSS
VCCFBD
20
XDPRDY#
17
XDPD[11]#
16
25
23
21
18
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
415
Ballout and Package Information
Figure 8-4. Intel 5000X Chipset MCH Ballout Right Side (Top View)
13
12
11
10
9
8
7
6
5
4
3
2
1
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
AV
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
FSBSLWCTRL
VSS
FSB1D[40]#
VSS
VSS
FSB1D[39]#
FSB1D[38]#
VSS
FSB1D[37]#
VSS
VSS
FSB1D[32]#
FSB1D[13]#
VSS
FSB1D[9]#
VSS
VSS
FSB1D[10]#
VSS
FSB1DBI[2]#
FSB1D[41]#
VSS
FSB1D[33]#
FSB1D[36]#
VSS
FSB1D[15]#
FSB1D[8]#
VSS
FSB1DSTBP[0]# FSB1DSTBN[0]#
VSS
VSS
FSB1D[42]#
FSB1D[46]#
VSS
FSB1D[34]#
FSB1D[11]#
FSB1D[12]#
VSS
VSS
FSB1D[7]#
FSB1D[4]#
VSS
FSB1D[6]#
VSS
VSS
FSB1D[45]#
FSB1D[43]#
VSS
FSB1DSTBP[2]# FSB1D[35]#
FSB1DSTBN[2]# VSS
FSB1D[14]#
FSB1DBI[0]#
VSS
FSB1D[5]#
FSB1D[2]#
VSS
FSB1D[3]#
FSB1D[0]#
VSS
FSB1D[44]#
FSB1D[27]#
VSS
FSB1D[22]#
FSB1D[23]#
VSS
FSB1D[1]#
FSB1VREF
VSS
FSB1ADS#
FSB1BPM[4]#
VSS
FSB1D[25]#
FSB1D[26]#
VSS
VSS
FSB1D[24]#
FSB1D[18]#
FSB1D[20]#
VSS
FSB1BPM[5]#
FSB1DRDY#
VSS
FSB1D[28]#
FSB1D[30]#
VSS
FSB1DSTBP[1]# FSB1D[21]#
FSB1DSTBN[1]# VSS
RSVD
FSB1DBSY#
FSB1LOCK#
VSS
FSB1BREQ[1]#
FSB1RS[1]#
VSS
FSB1D[29]#
FSB1DBI[1]#
VSS
FSB1D[17]#
FSB1HIT#
VSS
FSB1D[16]#
VSS
FSB1RS[2]#
FSB1RS[0]#
VSS
FSB1BREQ[0]#
FSB1RSP#
VSS
FSB1D[31]#
FSB1DP[1]#
VSS
VSS
FSB1D[19]#
FSB1DEFER#
VSS
FSB1TRDY#
FSB1REQ[2]#
VSS
FSB1BNR#
FSB1A[26]#
VSS
FSB1D[57]#
FSB1DBI[3]#
VSS
FSB1BPRI#
VCCSF
FSB1HITM#
RSVD
FSB1BINIT#
FSB1VREF
VSS
RSVD
FSB1MCERR#
FSB1DP[0]#
VSS
FSB1A[6]#
FSB1A[7]#
VSS
FSB1A[19]#
FSB1A[18]#
VSS
FSB1A[24]#
RSVD
FSB1A[25]#
VSS
FSB1AP[0]#
FSB1DP[2]#
VSS
FSB1AP[1]#
VSS
FSB1REQ[0]#
FSB1REQ[3]#
VSS
VSS
RSVD
FSB1ADSTB[1]#
FSB1A[28]#
VSS
FSB1DP[3]#
VTT
FSB1A[8]#
FSB1A[9]#
VSS
FSB1A[11]#
VSS
FSB1A[17]#
FSB1A[30]#
VSS
VSS
FSB1A[27]#
FSB1A[32]#
VSS
FSB1RESET#
FSB1REQ[1]#
VSS
FSB1REQ[4]#
VSS
RSVD
FSB1A[21]#
FSB1A[23]#
VSS
FSB1A[31]#
FSB1A[33]#
VSS
VTT
FSB1A[3]#
FSB1A[5]#
VSS
FSB1A[4]#
FSB1A[12]#
VSS
FSB1A[20]#
FSB1A[22]#
VSS
FSB1A[29]#
FSB1A[35]#
VSS
VTT
FSB1ADSTB[0]# FSB1A[13]#
FSB1A[15]#
PE0RN[2]
VSS
FSB1A[34]#
PE0TP[2]
VSS
PSEL[0]
PSEL[2]
VSS
VCCSF
FSB1A[10]#
PEWIDTH[0]
VSS
FSB1A[14]#
VSS
VSS
PE0RP[2]
PE0TP[3]
VSS
PE0TN[2]
PE0RP[3]
VSS
PSEL[1]
PE0TN[1]
VSS
VCCSF
FSB1A[16]#
PEWIDTH[1]
VCCPE
PE0TN[3]
PE0RN[0]
VSS
PE0RN[3]
PE0TN[0]
VCCPE
PE3RN[1]
PE3TP[2]
VSS
PE0TP[1]
PE0RN[1]
VSS
VCCPE
PE0RP[0]
PEWIDTH[3]
VSS
PE0TP[0]
PE3RP[2]
VSS
PE0RP[1]
PE3TN[1]
VSS
RSVD
W
V
W
V
VCCPE
PEWIDTH[2]
VSS
PE3RN[2]
PE3TP[3]
VCCPE
PE2TP[0]
RSVD
PE3TP[1]
PE3RP[1]
VSS
PE3RN[0]
PE3RP[0]
VCCPE
RSVD
VCCPE
VSS
PE3TN[3]
PE3RP[3]
VSS
PE3TN[0]
PE3TP[0]
VSS
VSS
U
U
VCCPE
VSS
VSS
PE3RN[3]
VSS
PE3TN[2]
PE2TN[0]
VSS
PE2TP[1]
PE2TN[1]
VCCPE
PE2RN[3]
PE2RP[3]
VSS
T
T
VCCPE
VSS
VSS
PE2RP[0]
PE2RN[0]
VSS
PE2TN[3]
PE2TP[3]
VSS
R
R
VCCPE
PEICOMPI
PERCOMPO
VCCPE
PEVCCBG
VSS
VCCPE
RSVD
RSVD
RSVD
PE2RN[2]
PE2RP[2]
VSS
P
P
VCCPE
RSVD
VSS
RSVD
RSVD
PE2RN[1]
PE2RP[1]
VSS
PE2TN[2]
PE2TP[2]
VSS
N
N
VCCPE
PEVSSBG
RSV1
RSVD
VSS
RSVD
RSVD
VCCPE
RSVD
RSVD
RSVD
M
M
VCCPE
RSVD
VSS
PE6TP[0]
VSSQUIET
VSS
PE6TN[0]
VCCPE
PE6RN[3]
PE6RP[3]
VSS
VSS
RSVD
RSVD
RSVD
L
L
VCCPE
GPIOSMBDATA
VSS
VSS
PE4RN[3]
PE4RP[3]
VCCPE
PE5RP[0]
PE5RN[0]
VSS
PE7TN[2]
PE7TP[2]
VSS
RSVD
VSS
PE7RN[3]
PE7RP[3]
VSS
RSVD
VCCPE
PEVSSA
PEVCCA
VSS
K
K
GPIOSMBCLK
VSS
PE4TN[3]
PE4TP[3]
VSS
VSS
PE7TN[3]
PE7TP[3]
VSS
VSS
PECLKN
PECLKP
VSS
J
J
PE4TN[0]
PE4TP[0]
VCCPE
PE5TP[0]
PE5TN[0]
VSS
PE6TN[3]
PE6TP[3]
VSS
RSVD
H
H
SPD0SMBCLK
SPD0SMBDATA
V3REF
PE5RN[3]
PE5RP[3]
VSS
PE7RN[2]
PE7TN[0]
VSS
PE7RP[2]
VSS
RSVD
G
G
PE4RP[1]
PE4RN[1]
VSS
PE5RN[2]
PE5RP[2]
VSS
PE7TP[0]
PE6RN[2]
VSS
PE7TP[1]
PE7RN[0]
VSS
PE7TN[1]
VSS
F
F
PE4RP[0]
PE4RN[0]
VSS
PE5TP[1]
PE5TN[1]
VSS
PE6RP[2]
ERR[0]#
VSS
PE7RP[0]
PE6RN[1]
VSS
E
E
VSS
PE4RN[2]
PE4RP[2]
VSS
PE5TN[3]
PE5TP[3]
VSS
PE6RP[1]
PE6TN[1]
VSS
PE7RN[1]
PE7RP[1]
VSS
D
D
XDPD[3]#
XDPDSTBN#
XDPD[6]#
VSS
PE4TN[2]
PE4TP[2]
VSS
PE5TP[2]
PE5TN[2]
VSS
PE6TP[1]
PE6RN[0]
VSS
ERR[2]#
PE6TN[2]
VSS
C
C
PE4TP[1]
PE4TN[1]
XDPD[4]#
12
PE5RP[1]
PE5RN[1]
VSS
PE6RP[0]
TDO
PE6TP[2]
VSS
B
B
XDPD[1]#
XDPD[2]#
10
TDI
TDIOCATHODE
TDIOANODE
4
A
A
XDPD[0]#
11
TRST#
TMS
TCK
ERR[1]#
5
VSS
13
9
8
7
6
3
2
1
®
416
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 1 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
A3
A4
VSS
TDIOANODE
ERR[1]#
TCK
Power/Other
Analog
B6
B7
TDO
TDI
JTAG
JTAG
Ouput
I
A5
CMOS
O
I
B8
VSS
Power/Other
PEX
A6
JTAG
B9
PE5RN[1]
XDPD[1]#
VSS
I
A7
TMS
JTAG
I
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
C1
XDP
I/O
A8
TRST#
JTAG
I
Power/Other
PEX
A9
VSS
Power/Other
XDP
PE4TN[1]
XDPD[6]#
XDPD[7]#
XDPD[9]#
VSS
O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
B2
XDPD[2]#
XDPD[0]#
XDPD[4]#
VSS
I/O
I/O
I/O
XDP
I/O
I/O
I/O
XDP
XDP
XDP
XDP
Power/Other
XDP
Power/Other
Power/Other
FBD
XDPD[10]#
XDPD[13]#
XDPD[11]#
XDPRDY#
VSS
I/O
I/O
I/O
I/O
VSS
XDP
FBD3NBIP[3]
FBD3NBIN[4]
VSS
I
I
XDP
FBD
XDP
Power/Other
FBD
Power/Other
FBD
FBD3NBIN[12]
FBD3NBIP[6]
VSS
I
I
FBD3NBIP[4]
VCCFBD
VSS
I
FBD
Power/Other
Power/Other
FBD
Power/Other
FBD
FBD3NBIN[8]
FBD2NBIN[0]
FBD2NBIP[1]
FBD2NBIP[2]
FBD2NBIN[3]
FBD2NBIP[4]
FBD2NBIP[5]
FBD2NBIN[13]
FBD2NBIP[12]
FBD2NBIP[6]
FBD2NBIN[7]
FBD2NBIP[8]
FBD2NBIN[9]
VSS
I
I
I
I
I
I
I
I
I
I
I
I
I
FBD3NBIN[6]
VSS
I
I
FBD
Power/Other
FBD
FBD
FBD3NBIP[8]
VSS
FBD
Power/Other
FBD
FBD
FBD2NBIN[1]
FBD2NBIN[2]
VSS
I
I
FBD
FBD
FBD
Power/Other
FBD
FBD
FBD2NBIN[4]
FBD2NBIN[5]
VSS
I
I
FBD
FBD
FBD
Power/Other
FBD
FBD
FBD2NBIN[12]
FBD2NBIN[6]
VSS
I
I
FBD
FBD
FBD
Power/Other
FBD
Power/Other
Power/Other
PEX
FBD2NBIN[8]
VSS
I
VSS
Power/Other
Power/Other
Power/Other
Analog
C2
PE6TN[2]
PE6TP[2]
VSS
O
O
VSS
C3
PEX
B3
VSS
C4
Power/Other
PEX
B4
TDIOCATHODE
VSS
C5
PE6RN[0]
PE6RP[0]
PE5TP[3]
I
I
B5
Power/Other
Power/Other
C6
PEX
C7
VSS
D7
PEX
O
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
417
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 2 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
C8
C9
PE5TN[2]
PE5RP[1]
VSS
PEX
PEX
O
I
D8
D9
PE5TP[2]
VSS
PEX
Power/Other
PEX
O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
D1
Power/Other
PEX
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
E1
PE4RP[2]
PE4TN[2]
VSS
I
PE4TP[2]
PE4TP[1]
XDPDSTBN#
XDPDSTBP#
VSS
O
O
PEX
O
PEX
Power/Other
XDP
XDP
I/O
I/O
XDPD[3]#
VSS
I/O
XDP
Power/Other
XDP
Power/Other
XDP
XDPD[8]#
XDPD[14]#
FBD3NBIN[2]
VSS
I/O
I/O
I
XDPD[12]#
FBD3NBIP[2]
FBD3NBIN[3]
VSS
I/O
XDP
FBD
I
I
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD3NBIP[5]
FBD3NBIP[13]
VSS
I
I
FBD3NBIN[13]
FBD3NBIP[12]
VSS
I
I
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD3SBOP[0]
FBD3NBIP[7]
VSS
O
I
FBD3NBIN[7]
VSS
I
I
FBD
Power/Other
FBD
Power/Other
FBD
FBD2NBIP[0]
VSS
FBD3NBIP[11]
FBD3NBIN[11]
VSS
I
I
Power/Other
Power/Other
FBD
FBD
VSS
Power/Other
Analog
No Connect
Power/Other
FBD
FBD2NBIP[3]
VSS
I
I
I
FBD23CLKP
RSVD
Power/Other
Power/Other
FBD
VSS
VSS
FBD2NBIP[13]
VSS
FBD2SBOP[3]
FBD2SBON[3]
VSS
O
O
Power/Other
Power/Other
FBD
FBD
VSS
Power/Other
FBD
FBD2NBIP[7]
VSS
FBD2SBOP[5]
FBD2SBON[5]
VSS
O
O
Power/Other
FBD
FBD
FBD2NBIP[9]
FBD2NBIP[10]
VSS
I
I
Power/Other
FBD
FBD
FBD2NBIN[10]
FBD2NBIP[11]
PE7RN[1]
VSS
I
I
I
Power/Other
PEX
FBD
PE7RP[1]
ERR[2]#
VSS
I
PEX
D2
CMOS
O
E2
Power/Other
PEX
D3
Power/Other
PEX
E3
PE6RN[1]
PE6RP[1]
VSS
I
I
D4
PE6TN[1]
PE6TP[1]
VSS
O
O
E4
PEX
D5
PEX
E5
Power/Other
CMOS
D6
Power/Other
PEX
E6
ERR[0]#
O
I
E7
PE5TN[3]
VSS
O
F7
VSS
Power/Other
PEX
E8
Power/Other
F8
PE5RP[2]
®
418
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 3 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
F1
PE5TN[1]
PE4RN[2]
VSS
PEX
PEX
O
I
F9
PE5TP[1]
VSS
PEX
Power/Other
PEX
O
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
G1
Power/Other
PEX
PE4RN[1]
PE4RP[0]
V3REF
I
I
PE4RN[0]
VSS
I
PEX
Power/Other
XDP
Analog
XDPD[5]#
SPD2SMBDATA
XDPD[15]#
VSS
I/O
I/O
I/O
XDPCOMCRES
SPD2SMBCLK
VSS
Analog
SMB
SMB
I/O
XDP
Power/Other
Power/Other
FBD
Power/Other
FBD
TESTHI_V3REF
FBD3NBIP[1]
VSS
FBD3NBIN[1]
FBD3NBIN[5]
VCCFBD
I
I
I
I
FBD
Power/Other
FBD
Power/Other
Power/Other
FBD
FBD3NBIN[0]
VSS
VSS
Power/Other
Power/Other
FBD
FBD3SBON[0]
VCCFBD
O
VSS
Power/Other
FBD
FBD3NBIP[9]
FBD3NBIN[9]
VCCFBD
VSS
I
I
FBD3NBIP[10]
FBD3NBIN[10]
VSS
I
I
FBD
FBD
Power/Other
Power/Other
Power/Other
Power/Other
FBD
Power/Other
Power/Other
Analog
FBD23VCCA
FBD23CLKN
VSS
FBD23VSSA
VSS
I
Power/Other
FBD
FBD2SBOP[1]
FBD2SBON[1]
VSS
O
O
FBD2SBOP[2]
FBD2SBON[2]
VSS
O
O
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD2SBOP[4]
FBD2SBON[4]
VSS
O
O
FBD2SBOP[9]
FBD2SBON[9]
VSS
O
O
FBD
FBD
Power/Other
Analog
Power/Other
Analog
FBDICOMPBIAS
FBD1NBIP[9]
FBD1NBIN[9]
VSS
FBDRESIN
FBDBGBIASEXT
FBD2NBIN[11]
VSS
FBD
I
I
Analog
FBD
FBD
I
Power/Other
PEX
Power/Other
PEX
PE7TN[1]
PE7TP[1]
VSS
O
O
F2
PE7RN[0]
PE7RP[0]
VSS
I
I
G2
PEX
F3
PEX
G3
Power/Other
PEX
F4
Power/Other
PEX
G4
PE7TN[0]
PE7TP[0]
VSS
O
O
F5
PE6RN[2]
PE6RP[2]
PE5RP[3]
PE5RN[2]
VSS
I
I
I
I
G5
PEX
F6
PEX
G6
Power/Other
PEX
G7
PEX
H7
PE5RN[3]
VSS
I
G8
PEX
H8
Power/Other
PEX
G9
Power/Other
H9
PE5TN[0]
O
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
419
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 4 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
H1
PE5RN[0]
PE4RP[1]
VCCPE
PEX
PEX
I
I
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
J1
PE5RP[0]
VSS
PEX
Power/Other
PEX
I
Power/Other
SMB
PE4TP[0]
SPD0SMBCLK
VSS
O
SPD0SMBDATA
XDPODTCRES
VSS
I/O
SMB
I/O
Analog
Power/Other
SMB
Power/Other
Power/Other
CMOS
SPD3SMBCLK
SPD3SMBDATA
PWRGOOD
FBD3SBOP[7]
FBD3SBON[6]
VCCFBD
FBD3SBON[9]
FBD3SBOP[9]
VCCFBD
FBD3SBON[2]
FBD3SBOP[2]
VSS
I/O
I/O
I
TESTHI_V3REF
RESETI#
VSS
SMB
I
CMOS
Power/Other
FBD
FBD
O
FBD3SBOP[6]
FBD3NBIP[0]
VSS
O
I
FBD
O
FBD
Power/Other
FBD
Power/Other
FBD
O
O
FBD3SBON[4]
FBD3SBOP[4]
VSS
O
O
FBD
FBD
Power/Other
FBD
Power/Other
FBD
O
O
FBD3SBON[1]
FBD3SBOP[1]
VSS
O
O
FBD
FBD
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
Power/Other
FBD
VSS
FBD2SBOP[0]
FBD2SBON[0]
VSS
O
O
VSS
FBD
VSS
Power/Other
Power/Other
Power/Other
Power/Other
FBD
VSS
VSS
VSS
VSS
VSS
VSS
FBD2SBOP[7]
FBD2SBON[7]
VSS
O
O
FBD2SBOP[6]
FBD2SBON[6]
VSS
O
O
FBD
FBD
Power/Other
FBD
Power/Other
Power/Other
FBD
FBD1NBIP[10]
FBD1NBIN[10]
FBD1NBIN[11]
VSS
I
I
I
VSS
FBD
FBD1NBIP[11]
RSVD
I
FBD
No Connect
Power/Other
PEX
Power/Other
Analog
H2
VSS
J2
PECLKP
H3
PE7RP[2]
PE7RN[2]
VSS
I
I
J3
RSVD
No Connect
Power/Other
PEX
H4
PEX
J4
VSS
H5
Power/Other
PEX
J5
PE7TP[3]
PE6TN[3]
PE7TP[2]
PE6RN[3]
VSS
O
O
O
I
H6
PE6TP[3]
VSS
O
J6
PEX
J7
Power/Other
PEX
K7
PEX
J8
PE6RP[3]
PE5TP[0]
VCCPE
I
K8
PEX
J9
PEX
O
K9
Power/Other
PEX
J10
Power/Other
K10
PE4RP[3]
I
®
420
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 5 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
K1
PE4TP[3]
PE4TN[0]
VSS
PEX
PEX
O
O
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
K35
K36
K37
K38
L1
PE4TN[3]
VSS
PEX
O
Power/Other
SMB
Power/Other
SMB
GPIOSMBCLK
CFGSMBCLK
SPD1SMBDATA
VSS
I/O
I/O
I/O
CFGSMBDATA
XDPSLWCRES
SPD1SMBCLK
VSS
I/O
I/O
O
SMB
Analog
SMB
SMB
Power/Other
Power/Other
FBD
Power/Other
FBD
VSS
FBD3SBON[7]
VSS
FBD3SBON[8]
FBD3SBOP[8]
VSS
O
O
Power/Other
FBD
FBD
FBD3SBON[5]
FBD3SBOP[5]
VSS
O
O
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
FBD
VCCFBD
VCCFBD
VCCFBD
VSS
Power/Other
FBD
FBD3SBON[3]
FBD3SBOP[3]
VSS
O
O
FBD
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FBD1NBIP[13]
FBD1NBIN[13]
VSS
I
I
FBD2SBOP[8]
FBD2SBON[8]
VSS
O
O
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD1NBIP[7]
FBD1NBIN[8]
VSS
I
I
FBD1NBIP[8]
FBD1SBOP[0]
FBD1SBON[0]
VSS
I
FBD
FBD
O
O
Power/Other
Power/Other
FBD
FBD
VSS
Power/Other
Analog
FBD1SBOP[2]
PEVSSA
VCCPE
RSVD
O
PEVCCA
PECLKN
VSS
Analog
K2
Analog
L2
Power/Other
No Connect
PEX
K3
Power/Other
PEX
L3
K4
PE7RP[3]
PE7TN[3]
VSS
I
L4
PE7RN[3]
VSS
I
K5
PEX
O
L5
Power/Other
No Connect
Power/Other
PEX
K6
Power/Other
PEX
L6
RSVD
L7
PE7TN[2]
VCCPE
O
I
M7
VSS
L8
Power/Other
Analog
M8
PE6TN[0]
PE6TP[0]
VSS
O
O
L9
VSSQUIET
PE4RN[3]
VSS
M9
PEX
L10
L11
PEX
M10
M11
Power/Other
No Connect
Power/Other
RSV1
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
421
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 6 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32
L33
L34
L35
L36
L37
L38
M1
GPIOSMBDATA
VCCPE
SMB
I/O
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
M31
M32
M33
M34
M35
M36
M37
M38
N1
RSVD
VCCPE
VCCPE
VCCPE
VCC
No Connect
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Temp
VCCPE
VCCPE
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCSEN
VSSSEN
VSS
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
FBD1NBIP[1]
FBD1NBIN[1]
VSS
Temp
Power/Other
FBD
I
I
FBD1NBIP[2]
FBD1NBIN[2]
VSS
I
I
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD1NBIP[4]
FBD1NBIN[4]
VSS
I
I
FBD1NBIP[5]
FBD1NBIN[5]
VSS
I
I
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD1NBIP[12]
FBD1NBIN[6]
VSS
I
I
FBD1NBIP[6]
FBD1NBIN[7]
VSS
I
I
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD1SBOP[3]
FBD1SBON[3]
VSS
O
O
FBD1SBOP[1]
FBD1SBON[1]
FBD1SBON[2]
VSS
O
O
O
FBD
FBD
Power/Other
Power/Other
PEX
FBD
VSS
Power/Other
No Connect
No Connect
Power/Other
No Connect
No Connect
No Connect
No Connect
Power/Other
No Connect
Analog
PE2TP[2]
RSVD
O
I
M2
RSVD
N2
No Connect
Power/Other
PEX
M3
RSVD
N3
VSS
M4
VSS
N4
PE2RP[1]
RSVD
M5
RSVD
N5
No Connect
Power/Other
No Connect
Power/Other
No Connect
No Connect
Power/Other
Analog
M6
RSVD
N6
VCCPE
RSVD
N7
RSVD
P7
N8
RSVD
P8
VSS
N9
VSS
P9
RSVD
N10
N11
N12
RSVD
P10
P11
P12
RSVD
PEVSSBG
VCCPE
VSS
Power/Other
PERCOMPO
®
422
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 7 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
N30
N31
N32
N33
N34
N35
N36
N37
N38
P1
VCCPE
VCCPE
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
R1
VCCPE
VCCPE
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
VCCPE
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VSS
VCC
VSS
VCC
VSS
VCC
VCCFBD
VCCFBD
FBD1NBIP[0]
FBD1NBIN[0]
VSS
I
I
FBD1NBIP[3]
FBD1NBIN[3]
VSS
I
I
FBD
FBD
Power/Other
Power/Other
Power/Other
Power/Other
FBD
Power/Other
Power/Other
FBD
VSS
VSS
VSS
FBD1NBIN[12]
VSS
I
VSS
Power/Other
FBD
FBD1SBON[7]
FBD1SBOP[7]
VSS
O
O
FBD1SBOP[4]
FBD1SBON[4]
VSS
O
O
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD1SBON[5]
FBD1SBOP[5]
VSS
O
O
FBD1SBON[9]
FBD1SBOP[9]
PE2TN[2]
VSS
O
O
O
FBD
FBD
Power/Other
Power/Other
PEX
PEX
VSS
P2
Power/Other
PEX
R2
PE2TP[3]
PE2RN[2]
VCCPE
PE2RN[0]
RSVD
O
I
P3
PE2RP[2]
PE2RN[1]
VSS
I
I
R3
PEX
P4
PEX
R4
Power/Other
PEX
P5
Power/Other
No Connect
Power/Other
No Connect
No Connect
Power/Other
Analog
R5
I
P6
RSVD
R6
No Connect
PEX
R7
VSS
T7
PE2TN[0]
PE2TP[0]
VSS
O
O
R8
RSVD
T8
PEX
R9
RSVD
T9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
R10
R11
R12
R13
VCCPE
T10
T11
T12
T13
VSS
PEVCCBG
PEICOMPI
VCCPE
VSS
Analog
VSS
Power/Other
VCCPE
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
423
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 8 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
T1
VCCPE
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
T38
U1
VCCPE
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCCFBD
VSS
VCCFBD
VCCFBD
VCCFBD
FBD0NBIN[4]
VSS
VSS
I
I
VSS
FBD
VSS
Power/Other
Power/Other
FBD
VSS
VSS
VSS
FBD0NBIP[6]
FBD0NBIN[6]
VSS
I
I
FBD1SBON[8]
FBD1SBOP[8]
VSS
O
O
FBD
FBD
Power/Other
Power/Other
Power/Other
Power/Other
No Connect
Analog
Power/Other
FBD
FBD01VSSA
FBD01VCCA
VSS
FBD1SBON[6]
FBD1SBOP[6]
VSS
O
O
FBD
Power/Other
Analog
RSVD
FBD01CLKP
PE2RP[3]
PE2TN[3]
VSS
I
I
FBD01CLKN
PE2RN[3]
VCCPE
PE3TP[0]
PE2TP[1]
VSS
I
I
PEX
PEX
T2
PEX
O
U2
Power/Other
PEX
T3
Power/Other
PEX
U3
O
O
T4
PE2TN[1]
PE2RP[0]
VSS
O
I
U4
PEX
T5
PEX
U5
Power/Other
PEX
T6
Power/Other
PEX
U6
PE3TP[2]
VSS
O
U7
PE3TN[2]
VCCPE
PE3RP[3]
PE3RN[3]
VSS
O
V7
Power/Other
PEX
U8
Power/Other
PEX
V8
PE3TP[3]
PE3TN[3]
VSS
O
O
U9
I
I
V9
PEX
U10
U11
U12
U13
U14
PEX
V10
V11
V12
V13
V14
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VCCPE
VCCPE
VCCPE
VCCPE
®
424
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 9 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
U34
U35
U36
U37
U38
V1
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
V35
V36
V37
V38
W1
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCCFBD
VCCFBD
FBD0NBIN[3]
FBD0NBIP[4]
VSS
VCCFBD
VCCFBD
FBD0NBIP[3]
VSS
I
I
I
FBD
Power/Other
FBD
Power/Other
FBD
FBD0NBIP[13]
FBD0NBIN[13]
VSS
I
I
FBD0NBIP[12]
FBD0NBIN[12]
VSS
I
I
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD0NBIP[7]
FBD0NBIN[7]
VSS
I
I
FBD0NBIP[8]
FBD0NBIN[8]
VSS
I
I
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD0NBIP[10]
FBD0NBIN[10]
VSS
I
I
FBD0NBIP[11]
FBD0NBIN[11]
VSS
I
I
FBD
FBD
Power/Other
FBD
Power/Other
Power/Other
PEX
FBD0SBOP[1]
RSVD
O
I
VSS
No Connect
PEX
V2
PE3RP[0]
PE3TN[0]
VSS
I
W2
PE3RN[0]
VSS
V3
PEX
O
W3
Power/Other
PEX
V4
Power/Other
PEX
W4
PE3TN[1]
PE3TP[1]
VCCPE
PE0TP[0]
VSS
O
O
V5
PE3RP[1]
PE3RN[1]
PE3RP[2]
PE3RN[2]
VSS
I
I
I
I
W5
PEX
V6
PEX
W6
Power/Other
PEX
W7
PEX
Y7
O
W8
PEX
Y8
Power/Other
PEX
W9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Y9
PE0RN[0]
PE0RP[0]
VSS
I
I
W10
W11
W12
W13
W14
W15
PEWIDTH[3]
PEWIDTH[2]
VCCPE
VCCPE
VCCPE
VCC
I
I
Y10
Y11
Y12
Y13
Y14
Y15
PEX
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
PEWIDTH[1]
VCCPE
VCCPE
VSS
I
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
425
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 10 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
W30
W31
W32
W33
W34
W35
W36
W37
W38
Y1
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
AA1
AA2
AA3
AA4
AA5
AA6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCCFBD
VCCFBD
VSS
VCCFBD
VCCFBD
FBD0NBIP[0]
FBD0NBIN[0]
VSS
I
I
FBD0NBIP[5]
FBD0NBIN[5]
VSS
I
I
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD0NBIP[1]
FBD0NBIN[1]
VSS
I
I
FBD0SBON[0]
FBD0SBOP[0]
VSS
O
O
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD0SBON[3]
FBD0SBOP[3]
VSS
O
O
FBD0NBIP[9]
FBD0NBIN[9]
VSS
I
I
FBD
FBD
Power/Other
FBD
Power/Other
Power/Other
FBD
FBD0SBOP[4]
FBD0SBON[4]
VSS
O
O
VSS
FBD
FBD0SBON[1]
RSVD
O
Power/Other
Power/Other
PEX
No Connect
Power/Other
PEX
VSS
Y2
VSS
PE0TN[1]
PE0TP[1]
VSS
O
O
Y3
PE0RN[1]
PE0RP[1]
VSS
I
I
PEX
Y4
PEX
Power/Other
PEX
Y5
Power/Other
PEX
PE0RP[3]
PE0RN[3]
PE0RN[2]
PE0RP[2]
VSS
I
I
I
I
Y6
PE0TN[0]
VSS
O
PEX
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
Power/Other
PEX
PEX
PE0TP[3]
PE0TN[3]
VSS
O
O
PEX
PEX
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
FSB1A[14]#
FSB1A[10]#
VSS
I/O
I/O
PEWIDTH[0]
FSB1A[16]#
VCCSF
VSS
I
I/O
VCCSF
VCCSF
VSS
VCC
VSS
VCC
®
426
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 11 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB1
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AB35
AB36
AB37
AB38
AC1
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCCFBD
VCCFBD
VCCFBD
VSS
VCCFBD
VCCFBD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FBD0NBIP[2]
FBD0NBIN[2]
VSS
I
I
FBD0SBOP[2]
FBD0SBON[2]
VSS
O
O
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD0SBON[7]
FBD0SBOP[7]
VSS
O
O
FBD0SBON[9]
FBD0SBOP[9]
VSS
O
O
FBD
FBD
Power/Other
FBD
Power/Other
FBD
FBD0SBOP[6]
FBD0SBON[5]
PSEL[0]
VSS
O
O
I
FBD0SBOP[5]
PSEL[2]
PSEL[1]
VSS
O
I
FBD
CMOS
CMOS
AB2
CMOS
I
AC2
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AB3
Power/Other
PEX
AC3
FSB1A[35]#
FSB1A[34]#
VSS
I/O
I/O
AB4
PE0TP[2]
PE0TN[2]
VSS
O
O
AC4
AB5
PEX
AC5
AB6
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AC6
FSB1A[22]#
VSS
I/O
AC7
FSB1A[15]#
VSS
I/O
AD7
AC8
AD8
FSB1A[12]#
FSB1A[4]#
VSS
I/O
I/O
AC9
FSB1A[13]#
FSB1ADSTB[0]#
VSS
I/O
I/O
AD9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
FSB1REQ[1]#
FSB1A[3]#
VTT
I/O
I/O
FSB1A[5]#
VTT
I/O
VTT
VTT
VCC
VTT
VSS
VTT
VCC
VTT
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
427
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 12 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AC37
AC38
AD1
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
FBD
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE1
VTT
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
VSS
VTT
VCC
VTT
VSS
VTT
VCC
VTT
VSS
VTT
VCCSF
VCCSF
VSS
VTT
VCCSF
VSS
VSS
VSS
VSS
FSB0D[46]#
FSB0D[41]#
VSS
I/O
I/O
FSB0D[42]#
FSB0D[44]#
VSS
I/O
I/O
FSB0DSTBN[2]#
FSB0DSTBP[2]#
VSS
I/O
I/O
FBD0SBON[8]
FBD0SBOP[8]
VSS
O
O
FBD
Power/Other
No Connect
FBD
FSB0D[38]#
VSS
I/O
TESTHI
FBD0SBON[6]
VSS
O
VSS
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Source Sync
No Connect
Power/Other
Source Sync
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
FSB1A[32]#
FSB1A[31]#
VSS
I/O
I/O
AD2
FSB1A[33]#
FSB1A[29]#
VSS
I/O
I/O
AE2
AD3
AE3
AD4
AE4
FSB1A[30]#
FSB1A[21]#
VSS
I/O
I/O
AD5
FSB1A[23]#
FSB1A[20]#
FSB1A[9]#
RSVD
I/O
I/O
I/O
AE5
AD6
AE6
AE7
AF7
FSB1A[8]#
VSS
I/O
I/O
AE8
AF8
AE9
VSS
AF9
FSB1REQ[3]#
VSS
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
FSB1REQ[4]#
FSB1RESET#
VSS
I/O
I
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
VSS
FSB1DP[2]#
FSB1DP[3]#
VSS
I/O
I/O
VTT
VTT
VTT
FSB1D[58]#
FSB1D[63]#
VSS
I/O
I/O
VTT
VTT
VTT
VTT
®
428
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 13 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AE36
AE37
AE38
AF1
VTT
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Common Clk
Common Clk
Common Clk
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AF36
AF37
AF38
AG1
VTT
VTT
Power/Other
Power/Other
Power/Other
Source Sync
Power/Other
Power/Other
Source Sync
Power/Other
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
No Connect
Source Sync
Power/Other
Source Sync
No Connect
No Connect
Source Sync
Power/Other
Power/Other
Common Clk
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
No Connect
Power/Other
Power/Other
VTT
VTT
VTT
FSB0A[16]#
VSS
I/O
I/O
I/O
VTT
VTT
VSS
VTT
FSB0A[14]#
VSS
VTT
VSS
VSS
FSB0D[47]#
FSB0D[43]#
VSS
I/O
I/O
FSB0D[45]#
VSS
FSB0DBI[2]#
FSB0D[35]#
VSS
I/O
I/O
FSB0D[40]#
FSB0D[39]#
VSS
I/O
I/O
FSB0D[37]#
FSB0VREF
VSS
I/O
FSB0D[34]#
VCCSF
I/O
FSB0D[62]#
FSB0D[63]#
FSB0D[58]#
FSB1A[27]#
VSS
I/O
I/O
I/O
I/O
VSS
FSB0D[48]#
FSB0D[59]#
VSS
I/O
I/O
AF2
AG2
RSVD
AF3
FSB1A[28]#
FSB1A[17]#
VSS
I/O
I/O
AG3
FSB1ADSTB[1]#
VSS
I/O
I/O
AF4
AG4
AF5
AG5
FSB1A[18]#
RSVD
AF6
FSB1A[11]#
VSS
I/O
AG6
AG7
AH7
RSVD
AG8
FSB1A[7]#
FSB1REQ[0]#
FSB1AP[1]#
FSB1DP[0]#
FSB1AP[0]#
VSS
I/O
I/O
I/O
I/O
I/O
AH8
FSB1A[6]#
VSS
I/O
I/O
AG9
AH9
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
VCCSF
FSB1MCERR#
VSS
FSB1DBI[3]#
FSB1D[48]#
VSS
I/O
I/O
FSB1D[62]#
FSB1D[59]#
VSS
I/O
I/O
FSB1D[54]#
VSS
I/O
VSS
VTT
VTT
VTT
VTT
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
429
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 14 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AG31
AG32
AG33
AG34
AG35
AG36
AG37
AG38
AH1
VTT
VTT
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Common Clk
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Power/Other
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AH33
AH34
AH35
AH36
AH37
AH38
AJ1
VTT
VTT
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Common Clk
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
No Connect
Power/Other
Source Sync
Common Clk
Power/Other
Source Sync
Power/Other
Common Clk
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
No Connect
Power/Other
Power/Other
Power/Other
VSS
FSB0A[13]#
FSB0A[8]#
VSS
I/O
I/O
FSB0A[15]#
FSB0A[10]#
VSS
I/O
I/O
FSB0REQ[1]#
FSB0AP[0]#
VSS
I/O
I/O
FSB0BREQ[1]#
FSB0D[14]#
VSS
I/O
I/O
FSB0D[2]#
FSB0D[4]#
VSS
I/O
I/O
FSB0D[13]#
FSB0D[33]#
VSS
I/O
I/O
FSB0D[11]#
FSB0D[9]#
VSS
I/O
I/O
FSB0D[36]#
FSB0D[32]#
VSS
I/O
I/O
FSB0DSTBN[3]#
FSB0DSTBP[3]#
FSB0D[61]#
FSB0DBI[3]#
FSB0D[57]#
RSVD
I/O
I/O
I/O
I/O
I/O
FSB0D[54]#
FSB0D[60]#
VSS
I/O
I/O
VSS
FSB1A[25]#
FSB1A[24]#
VSS
I/O
I/O
AH2
AJ2
VSS
AH3
AJ3
FSB1A[26]#
FSB1BINIT#
VSS
I/O
I/O
AH4
FSB1VREF
FSB1A[19]#
VSS
AJ4
AH5
I/O
I/O
AJ5
AH6
AJ6
FSB1REQ[2]#
VSS
I/O
AJ7
FSB1HITM#
VSS
AK7
AJ8
AK8
FSB1HIT#
FSB1D[19]#
VSS
I/O
I/O
AJ9
FSB1DEFER#
FSB1BPRI#
VSS
O
O
AK9
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
FSB1DBI[1]#
FSB1D[31]#
VSS
I/O
I/O
FSB1DP[1]#
FSB1D[57]#
VSS
I/O
I/O
FSB1DSTBN[3]#
FSB1DSTBP[3]#
VSS
I/O
I/O
FSB1D[60]#
FSB1D[61]#
VSS
I/O
I/O
RSVD
VTT
VTT
VTT
VTT
VTT
VTT
®
430
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 15 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AJ37
AJ38
AK1
VTT
FSB0A[11]#
VSS
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Common Clk
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Common Clk
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL1
VTT
VSS
Power/Other
Power/Other
No Connect
Source Sync
Power/Other
Source Sync
Common Clk
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
No Connect
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
I/O
RSVD
FSB0REQ[3]#
FSB0REQ[4]#
VSS
I/O
I/O
FSB0REQ[2]#
VSS
I/O
FSB0AP[1]#
FSB0BINIT#
VSS
I/O
I/O
FSB0MCERR#
FSB0D[0]#
VSS
I/O
I/O
FSB0D[3]#
FSB0D[6]#
VSS
I/O
I/O
FSB0D[10]#
FSB0D[8]#
VSS
I/O
I/O
FSB0DSTBN[0]#
FSB0DSTBP[0]#
VSS
I/O
I/O
FSB0D[15]#
FSB0D[49]#
VSS
I/O
I/O
FSB0D[30]#
FSB0D[53]#
VSS
I/O
I/O
VSS
FSB0D[55]#
FSB0D[56]#
VSS
I/O
I/O
VSS
FSB1RS[1]#
FSB1BREQ[0]#
VSS
I
AK2
FSB1RSP#
FSB1BNR#
VSS
I
AL2
I/O
AK3
I/O
AL3
AK4
AL4
FSB1LOCK#
FSB1RS[2]#
VSS
I/O
I
AK5
FSB1RS[0]#
FSB1TRDY#
FSB1D[16]#
FSB1D[17]#
VSS
I
AL5
AK6
O
AL6
AL7
I/O
I/O
AM7
RSVD
AL8
AM8
VSS
AL9
AM9
FSB1D[21]#
FSB1DSTBP[1]#
VSS
I/O
I/O
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
FSB1DSTBN[1]#
FSB1D[29]#
VSS
I/O
I/O
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
FSB1D[26]#
FSB1D[28]#
VSS
I/O
I/O
FSB1D[30]#
FSB1D[52]#
VSS
I/O
I/O
FSB1D[51]#
FSB1D[49]#
VSS
I/O
I/O
FSB1D[56]#
VCC
I/O
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
431
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 16 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AL36
AL37
AL38
AM1
FSB0A[12]#
FSB0ADSTB[0]#
VSS
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Common Clk
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Analog
I/O
I/O
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM37
AM38
AN1
FSB0A[9]#
VSS
Source Sync
Power/Other
No Connect
Source Sync
Power/Other
Power/Other
Common Clk
Power/Other
Power/Other
No Connect
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Common Clk
Common Clk
Power/Other
Power/Other
Source Sync
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Analog
I/O
RSVD
FSB0A[3]#
FSB0REQ[0]#
VSS
I/O
I/O
FSB0A[5]#
VSS
I/O
I/O
FSB0VREF
FSB0BREQ[0]#
VSS
FSB0RS[1]#
FSB0D[1]#
VSS
I
I/O
FSB0VREF
RSVD
FSB0D[7]#
FSB0DBI[0]#
VSS
I/O
I/O
VSS
FSB0D[12]#
FSB0D[29]#
VSS
I/O
I/O
FSB0D[17]#
FSB0D[25]#
FSB0D[51]#
FSB0D[52]#
FSB0D[50]#
FSB1BREQ[1]#
VSS
I/O
I/O
I/O
I/O
I/O
I/O
VSS
FSB0D[31]#
FSB0D[28]#
VSS
I/O
I/O
AM2
AN2
FSB1BPM[4]#
FSB1BPM[5]#
VSS
I/O
I/O
AM3
FSB1DRDY#
FSB1DBSY#
VSS
I/O
I/O
AN3
AM4
AN4
AM5
AN5
FSB1VREF
FSB1D[18]#
FSB1DBI[0]#
FSB1D[22]#
VSS
AM6
FSB1D[20]#
VSS
I/O
AN6
I/O
I/O
I/O
AN7
AP7
AN8
FSB1D[23]#
FSB1D[24]#
VSS
I/O
I/O
AP8
AN9
AP9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
FSB1DSTBN[2]#
FSB1D[44]#
VSS
I/O
I/O
FSB1D[27]#
FSB1D[25]#
VSS
I/O
I/O
FSB1D[43]#
FSB1D[47]#
VSS
I/O
I/O
FSB1D[50]#
FSB1D[53]#
VSS
I/O
I/O
FSB1D[55]#
CORECLKN
VTT
I/O
I
CORECLKP
VTT
I
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
VTT
VTT
VTT
VTT
VTT
VTT
VSS
FSB0A[32]#
I/O
®
432
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 17 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP1
RSVD
FSB0A[4]#
VSS
No Connect
Source Sync
Power/Other
Source Sync
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Common Clk
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
No Connect
No Connect
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Power/Other
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AR1
FSB0ADSTB[1]#
VSS
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
No Connect
Common Clk
Power/Other
Common Clk
No Connect
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
I/O
I/O
FSB0A[18]#
FSB0A[7]#
VSS
I/O
I/O
FSB0A[6]#
FSB0RSP#
VSS
I/O
I
RSVD
FSB0DP[3]#
FSB0RESET#
VSS
I/O
I
FSB0BPM[5]#
VSS
I/O
I/O
FSB0DP[2]#
RSVD
FSB0D[5]#
FSB0D[16]#
VSS
I/O
I/O
VSS
FSB0D[20]#
FSB0D[18]#
FSB0D[23]#
FSB0DBI[1]#
FSB0D[27]#
FSB1D[3]#
VSS
I/O
I/O
I/O
I/O
I/O
I/O
FSB0D[24]#
FSB0D[26]#
VSS
I/O
I/O
VSS
FSB1D[0]#
FSB1ADS#
VSS
I/O
I/O
AP2
AR2
AP3
AR3
FSB1D[4]#
FSB1D[5]#
VSS
I/O
I/O
AP4
FSB1D[2]#
FSB1D[1]#
VSS
I/O
I/O
AR4
AP5
AR5
AP6
AR6
FSB1D[12]#
VSS
I/O
AR7
FSB1D[14]#
VSS
I/O
AT7
AR8
AT8
FSB1D[36]#
FSB1D[34]#
VSS
I/O
I/O
AR9
FSB1D[35]#
FSB1DSTBP[2]#
VSS
I/O
I/O
AT9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AT10
AT11
AT12
AT13
AT14
AT15
AT16
AT17
AT18
AT19
AT20
AT21
AT22
AT23
FSB1D[41]#
FSB1D[42]#
VSS
I/O
I/O
FSB1D[46]#
FSB1D[45]#
VSS
I/O
I/O
FSB1VREF
VSS
RSVD
RSVD
VSS
VSS
COREVCCA
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
FSB0A[33]#
VSS
I/O
VSS
FSB0A[30]#
I/O
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
433
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 18 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AT1
FSB0A[20]#
FSB0A[26]#
VSS
Source Sync
Source Sync
Power/Other
Source Sync
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
No Connect
Analog
I/O
I/O
AT24
AT25
AT26
AT27
AT28
AT29
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU2
FSB0A[27]#
VSS
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Analog
I/O
FSB0A[24]#
FSB0A[23]#
VSS
I/O
I/O
FSB0A[19]#
FSB0BPM[4]#
VSS
I/O
I/O
FSB0DRDY#
FSB0LOCK#
VSS
I/O
I/O
FSB0DBSY#
FSB0DP[0]#
VSS
I/O
I/O
FSB0TRDY#
FSB0DP[1]#
VSS
O
RSVD
I/O
FSBODTCRES
VSS
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
FSBCRES
FSB0D[19]#
FSB0D[22]#
VSS
VSS
Source Sync
Source Sync
Power/Other
Power/Other
Source Sync
Source Sync
Source Sync
Power/Other
Source Sync
Power/Other
Source Sync
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
No Connect
Source Sync
I/O
I/O
FSB0DSTBN[1]#
FSB0DSTBP[1]#
VSS
I/O
I/O
VSS
AT2
FSB1D[6]#
FSB1D[7]#
VSS
I/O
I/O
AU3
FSB1DSTBN[0]#
FSB1DSTBP[0]#
FSB1D[15]#
VSS
I/O
I/O
I/O
AT3
AU4
AT4
AU5
AT5
FSB1D[8]#
FSB1D[11]#
FSB1D[33]#
VSS
I/O
I/O
I/O
AU6
AT6
AU7
FSB1D[13]#
VSS
I/O
I/O
AU8
AV11
AV12
AV13
AV14
AV15
AV16
AV17
AV18
AV19
AV20
AV21
AV22
AV23
AV24
AV25
AV26
AV27
AV28
AU9
FSB1D[40]#
FSBSLWCTRL
VSS
AU10
AU11
AU12
AU13
AU14
AU15
AU16
AU17
AU18
AU19
AU20
AU21
AU22
AU23
AU24
AU25
FSB1D[38]#
FSB1DBI[2]#
VSS
I/O
I/O
VSS
VSS
VSS
VSS
VSS
VSS
VTT
COREVSSA
FSBVCCA
VTT
VTT
VTT
VTT
VTT
FSB0A[35]#
VSS
I/O
VTT
VTT
FSB0A[31]#
FSB0A[28]#
VSS
I/O
I/O
FSB0A[34]#
FSB0A[29]#
VSS
I/O
I/O
RSVD
FSB0A[22]#
I/O
FSB0A[17]#
I/O
®
434
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-1.
Intel 5000X Chipset MCH Signals (by Ball Number) (Sheet 19 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AU26
AU27
AU28
AU29
AU30
AU31
AU32
AU33
AU34
AU35
AU36
AU37
AV3
FSB0A[25]#
VSS
Source Sync
Power/Other
Source Sync
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Analog
I/O
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
VSS
FSB0BNR#
FSB0RS[0]#
VSS
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Power/Other
I/O
I
FSB0A[21]#
FSB0ADS#
VSS
I/O
I/O
FSB0HITM#
FSB0DEFER#
VSS
I/O
O
FSB0RS[2]#
FSB0HIT#
VSS
I
I/M105O
VSS
FSB0BPRI#
FSBSLWCRES
FSB0D[21]#
VSS
O
Source Sync
Power/Other
Power/Other
Source Sync
Power/Other
Source Sync
Source Sync
Power/Other
Source Sync
Source Sync
I/O
VSS
AV4
FSB1D[10]#
VSS
I/O
AV5
AV6
FSB1D[9]#
FSB1D[32]#
VSS
I/O
I/O
AV7
AV8
AV9
FSB1D[37]#
FSB1D[39]#
I/O
I/O
AV10
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
435
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 1 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
K14
J14
CFGSMBCLK
CFGSMBDATA
CORECLKN
CORECLKP
COREVCCA
COREVSSA
ERR[0]#
SMB
SMB
I/O
V32
U33
FBD0NBIP[7]
FBD0NBIP[8]
FBD0NBIP[9]
FBD0SBON[0]
FBD0SBON[1]
FBD0SBON[2]
FBD0SBON[3]
FBD0SBON[4]
FBD0SBON[5]
FBD0SBON[6]
FBD0SBON[7]
FBD0SBON[8]
FBD0SBON[9]
FBD0SBOP[0]
FBD0SBOP[1]
FBD0SBOP[2]
FBD0SBOP[3]
FBD0SBOP[4]
FBD0SBOP[5]
FBD0SBOP[6]
FBD0SBOP[7]
FBD0SBOP[8]
FBD0SBOP[9]
FBD1NBIN[0]
FBD1NBIN[1]
FBD1NBIN[10]
FBD1NBIN[11]
FBD1NBIN[12]
FBD1NBIN[13]
FBD1NBIN[2]
FBD1NBIN[3]
FBD1NBIN[4]
FBD1NBIN[5]
FBD1NBIN[6]
FBD1NBIN[7]
FBD1NBIN[8]
FBD1NBIN[9]
FBD1NBIP[0]
FBD2NBIN[1]
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
I
I
I/O
AP17
AN17
AT17
AU16
E6
Analog
Analog
Power/Other
Power/Other
CMOS
CMOS
CMOS
Analog
Analog
Power/Other
Power/Other
FBD
I
I
W34
W31
W38
AA33
Y33
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
O
I
A5
ERR[1]#
Y37
D2
ERR[2]#
AB38
AC37
AB34
AC33
AA35
W32
V38
T38
R38
T35
T34
Y28
Y31
V36
U37
U31
V30
AB32
U27
T28
W29
T32
V33
U34
W35
Y27
Y30
V35
U36
U30
V29
AB31
V27
U28
W28
T31
M26
FBD01CLKN
FBD01CLKP
FBD01VCCA
FBD01VSSA
FBD0NBIN[0]
FBD0NBIN[1]
FBD0NBIN[10]
FBD0NBIN[11]
FBD0NBIN[12]
FBD0NBIN[13]
FBD0NBIN[2]
FBD0NBIN[3]
FBD0NBIN[4]
FBD0NBIN[5]
FBD0NBIN[6]
FBD0NBIN[7]
FBD0NBIN[8]
FBD0NBIN[9]
FBD0NBIP[0]
FBD0NBIP[1]
FBD0NBIP[10]
FBD0NBIP[11]
FBD0NBIP[12]
FBD0NBIP[13]
FBD0NBIP[2]
FBD0NBIP[3]
FBD0NBIP[4]
FBD0NBIP[5]
FBD0NBIP[6]
FBD1NBIP[1]
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
FBD
FBD
AA32
Y34
FBD
FBD
Y36
FBD
AA38
AB37
AB35
AC34
AA36
P28
FBD
FBD
FBD
FBD
FBD
FBD
M27
H37
I
FBD
I
FBD
H38
I
FBD
N32
I
FBD
K32
I
FBD
L28
I
FBD
N29
I
FBD
M30
L31
I
FBD
I
FBD
M33
L34
I
FBD
I
FBD
K35
I
FBD
F37
I
FBD
P27
I
FBD
A26
I
®
436
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 2 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
H36
G38
M32
K31
L27
N28
M29
L30
L33
K34
J35
FBD1NBIP[10]
FBD1NBIP[11]
FBD1NBIP[12]
FBD1NBIP[13]
FBD1NBIP[2]
FBD1NBIP[3]
FBD1NBIP[4]
FBD1NBIP[5]
FBD1NBIP[6]
FBD1NBIP[7]
FBD1NBIP[8]
FBD1NBIP[9]
FBD1SBON[0]
FBD1SBON[1]
FBD1SBON[2]
FBD1SBON[3]
FBD1SBON[4]
FBD1SBON[5]
FBD1SBON[6]
FBD1SBON[7]
FBD1SBON[8]
FBD1SBON[9]
FBD1SBOP[0]
FBD1SBOP[1]
FBD1SBOP[2]
FBD1SBOP[3]
FBD1SBOP[4]
FBD1SBOP[5]
FBD1SBOP[6]
FBD1SBOP[7]
FBD1SBOP[8]
FBD1SBOP[9]
FBD23CLKN
FBD23CLKP
FBD
FBD
I
D37
E38
A32
B31
A27
B28
A29
A30
A33
B34
A35
B36
C25
B26
C37
D38
B32
C31
B27
C28
B29
B30
B33
C34
B35
C36
G29
F30
E31
D32
F33
D35
G35
H34
J33
FBD2NBIN[10]
FBD2NBIN[11]
FBD2NBIN[12]
FBD2NBIN[13]
FBD2NBIN[2]
FBD2NBIN[3]
FBD2NBIN[4]
FBD2NBIN[5]
FBD2NBIN[6]
FBD2NBIN[7]
FBD2NBIN[8]
FBD2NBIN[9]
FBD2NBIP[0]
FBD2NBIP[1]
FBD2NBIP[10]
FBD2NBIP[11]
FBD2NBIP[12]
FBD2NBIP[13]
FBD2NBIP[2]
FBD2NBIP[3]
FBD2NBIP[4]
FBD2NBIP[5]
FBD2NBIP[6]
FBD2NBIP[7]
FBD2NBIP[8]
FBD2NBIP[9]
FBD2SBON[0]
FBD2SBON[1]
FBD2SBON[2]
FBD2SBON[3]
FBD2SBON[4]
FBD2SBON[5]
FBD2SBON[6]
FBD2SBON[7]
FBD2SBON[8]
FBD2SBON[9]
FBD2SBOP[0]
FBD3SBON[1]
FBD3SBON[2]
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
FBD
I
I
I
FBD
I
I
FBD
I
I
FBD
I
I
FBD
I
I
FBD
I
I
FBD
I
I
FBD
I
I
FBD
I
I
FBD
I
I
F36
J37
FBD
I
I
FBD
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
L37
L38
M36
N35
P36
R35
P33
R32
N37
J36
FBD
I
FBD
I
FBD
I
FBD
I
FBD
I
FBD
I
FBD
I
FBD
I
FBD
I
FBD
I
L36
K38
M35
N34
P37
R36
P34
R33
N38
E28
D28
E27
F27
B25
F29
E30
FBD
I
FBD
I
FBD
I
FBD
O
O
O
O
O
O
O
O
O
O
O
O
O
FBD
FBD
FBD
FBD
FBD
Analog
Analog
Power/Other
Power/Other
FBD
FBD23VCCA
FBD23VSSA
FBD2NBIN[0]
FBD2SBOP[1]
FBD2SBOP[2]
E34
G28
G25
H24
I
FBD
O
O
FBD
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
437
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 3 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
D31
F32
D34
G34
H33
J32
FBD2SBOP[3]
FBD2SBOP[4]
FBD2SBOP[5]
FBD2SBOP[6]
FBD2SBOP[7]
FBD2SBOP[8]
FBD2SBOP[9]
FBD3NBIN[0]
FBD3NBIN[1]
FBD3NBIN[10]
FBD3NBIN[11]
FBD3NBIN[12]
FBD3NBIN[13]
FBD3NBIN[2]
FBD3NBIN[3]
FBD3NBIN[4]
FBD3NBIN[5]
FBD3NBIN[6]
FBD3NBIN[7]
FBD3NBIN[8]
FBD3NBIN[9]
FBD3NBIP[0]
FBD3NBIP[1]
FBD3NBIP[10]
FBD3NBIP[11]
FBD3NBIP[12]
FBD3NBIP[13]
FBD3NBIP[2]
FBD3NBIP[3]
FBD3NBIP[4]
FBD3NBIP[5]
FBD3NBIP[6]
FBD3NBIP[7]
FBD3NBIP[8]
FBD3NBIP[9]
FBD3SBON[0]
FSB0A[26]#
FBD
FBD
O
J23
G22
FBD3SBON[3]
FBD3SBON[4]
FBD3SBON[5]
FBD3SBON[6]
FBD3SBON[7]
FBD3SBON[8]
FBD3SBON[9]
FBD3SBOP[0]
FBD3SBOP[1]
FBD3SBOP[2]
FBD3SBOP[3]
FBD3SBOP[4]
FBD3SBOP[5]
FBD3SBOP[6]
FBD3SBOP[7]
FBD3SBOP[8]
FBD3SBOP[9]
FBDBGBIASEXT
FBDICOMPBIAS
FBDRESIN
FBD
FBD
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
FBD
O
J20
FBD
FBD
O
H19
FBD
FBD
O
J18
FBD
FBD
O
K18
FBD
E33
F20
E18
E25
D26
B21
C20
D17
C18
B19
E19
A22
C23
B24
F24
G20
F18
E24
D25
C21
D20
C17
B18
A19
D19
B22
D23
A24
F23
E22
AR25
AT24
AV25
FBD
O
H21
FBD
FBD
I
D22
FBD
FBD
I
G26
FBD
FBD
I
H25
FBD
FBD
I
J24
FBD
FBD
I
G23
FBD
FBD
I
J21
FBD
FBD
I
G19
FBD
FBD
I
H18
FBD
FBD
I
K19
FBD
FBD
I
H22
FBD
FBD
I
E37
Analog
FBD
I
F35
Analog
FBD
I
E36
Analog
FBD
I
AG24
AJ22
AL22
AH22
AF25
AG23
AF22
AV28
AP25
AR27
AR24
AU28
AU25
AT27
AT26
AU26
AL34
AP35
AT36
FSB0A[10]#
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FBD
I
FSB0A[11]#
FBD
I
FSB0A[12]#
FBD
I
FSB0A[13]#
FBD
I
FSB0A[14]#
FBD
I
FSB0A[15]#
FBD
I
FSB0A[16]#
FBD
I
FSB0A[17]#
FBD
I
FSB0A[18]#
FBD
I
FSB0A[19]#
FBD
I
I
FSB0A[20]#
FBD
FSB0A[21]#
FBD
I
FSB0A[22]#
FBD
I
FSB0A[23]#
FBD
I
FSB0A[24]#
FBD
O
I/O
I/O
I/O
FSB0A[25]#
Source Sync
Source Sync
Source Sync
FSB0D[17]#
FSB0D[18]#
FSB0D[19]#
FSB0A[27]#
FSB0A[28]#
®
438
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 4 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AU23
AL25
AT23
AV24
AP22
AR22
AU22
AV22
AN24
AM25
AN26
AP26
AH23
AM22
AU29
AL23
AP23
AH26
AK26
AK27
AV30
AR28
AP29
AU34
AM28
AG26
AJ28
AL29
AJ30
AH31
AM33
AG29
AG27
AJ33
AN33
AL36
AL37
AK36
AG35
FSB0A[29]#
FSB0A[3]#
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Source Sync
Source Sync
Common Clk
Source Sync
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
AH28
AP34
AU36
AT37
AP36
AN35
AL35
AN36
AP38
AM38
AM34
AK29
AK35
AM37
AG33
AG30
AE34
AF31
AG32
AF33
AD35
AE32
AH29
AE31
AD30
AC30
AE29
AC31
AF28
AD29
AE28
AF37
AJ34
AN32
AL38
AT30
AJ27
AL26
AH25
FSB0D[2]#
FSB0D[20]#
FSB0D[21]#
FSB0D[22]#
FSB0D[23]#
FSB0D[24]#
FSB0D[25]#
FSB0D[26]#
FSB0D[27]#
FSB0D[28]#
FSB0D[29]#
FSB0D[3]#
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Source Sync
Source Sync
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FSB0A[30]#
FSB0A[31]#
FSB0A[32]#
FSB0A[33]#
FSB0A[34]#
FSB0A[35]#
FSB0A[4]#
FSB0A[5]#
FSB0A[6]#
FSB0A[7]#
FSB0A[8]#
FSB0D[30]#
FSB0D[31]#
FSB0D[32]#
FSB0D[33]#
FSB0D[34]#
FSB0D[35]#
FSB0D[36]#
FSB0D[37]#
FSB0D[38]#
FSB0D[39]#
FSB0D[4]#
FSB0A[9]#
FSB0ADS#
FSB0ADSTB[0]#
FSB0ADSTB[1]#
FSB0AP[0]#
FSB0AP[1]#
FSB0BINIT#
FSB0BNR#
FSB0BPM[4]#
FSB0BPM[5]#
FSB0BPRI#
FSB0BREQ[0]#
FSB0BREQ[1]#
FSB0D[0]#
FSB0D[40]#
FSB0D[41]#
FSB0D[42]#
FSB0D[43]#
FSB0D[44]#
FSB0D[45]#
FSB0D[46]#
FSB0D[47]#
FSB0D[48]#
FSB0D[49]#
FSB0D[5]#
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FSB0D[1]#
FSB0D[10]#
FSB0D[11]#
FSB0D[12]#
FSB0D[13]#
FSB0D[14]#
FSB0D[15]#
FSB0D[16]#
FSB0D[51]#
FSB0D[52]#
FSB0D[53]#
FSB0D[54]#
FSB0D[50]#
FSB0LOCK#
FSB0MCERR#
FSB0REQ[0]#
FSB0REQ[1]#
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
439
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 5 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AJ37
AJ38
AH38
AE38
AF38
AK30
AG36
AH36
AE36
AE37
AL31
AJ31
AH32
AL32
AP37
AF30
AH37
AR30
AV34
AR31
AT33
AP31
AN29
AT29
AK32
AR37
AD32
AH34
AK33
AR38
AD33
AH35
AU32
AV33
AE2
FSB0D[55]#
FSB0D[56]#
FSB0D[57]#
FSB0D[58]#
FSB0D[59]#
FSB0D[6]#
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
AK24
AJ24
AJ25
AN30
AV31
AL28
AU31
AN27
AT32
AF34
AM27
AM30
AB11
AF6
FSB0REQ[2]#
FSB0REQ[3]#
FSB0REQ[4]#
FSB0RESET#
FSB0RS[0]#
FSB0RS[1]#
FSB0RS[2]#
FSB0RSP#
FSB0TRDY#
FSB0VREF
FSB0VREF
FSB0VREF
FSB1A[10]#
FSB1A[11]#
FSB1A[12]#
FSB1A[13]#
FSB1A[14]#
FSB1A[15]#
FSB1A[16]#
FSB1A[17]#
FSB1A[18]#
FSB1A[19]#
FSB1A[20]#
FSB1A[21]#
FSB1A[22]#
FSB1A[23]#
FSB1A[24]#
FSB1A[25]#
FSB1A[26]#
FSB1A[27]#
FSB1A[28]#
FSB1A[29]#
FSB1A[3]#
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
I/O
I/O
I/O
I
I
I
FSB0D[60]#
FSB0D[61]#
FSB0D[62]#
FSB0D[63]#
FSB0D[7]#
I
I
O
FSB0D[8]#
FSB0D[9]#
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FSB0DBI[0]#
FSB0DBI[1]#
FSB0DBI[2]#
FSB0DBI[3]#
FSB0DBSY#
FSB0DEFER#
FSB0DP[0]#
FSB0DP[1]#
FSB0DP[2]#
FSB0DP[3]#
FSB0DRDY#
FSB0DSTBN[0]#
FSB0DSTBN[1]#
FSB0DSTBN[2]#
FSB0DSTBN[3]#
FSB0DSTBP[0]#
FSB0DSTBP[1]#
FSB0DSTBP[2]#
FSB0DSTBP[3]#
FSB0HIT#
AD8
AC9
AB10
AC7
AA12
AF4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/M105O
I/O
I/O
I/O
I/O
I/O
I/O
AG5
AH5
AD6
AE5
AC6
AD5
AH2
AH1
AJ3
AF1
AF3
AD3
AD12
AE4
FSB0HITM#
FSB1A[31]#
FSB1A[32]#
FSB1A[33]#
FSB1A[34]#
FSB1A[35]#
FSB1A[30]#
FSB1D[22]#
FSB1D[23]#
FSB1D[24]#
FSB1D[25]#
FSB1D[26]#
AP8
AE1
AN8
AD2
AN9
AC4
AN12
AM12
AC3
®
440
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 6 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AD9
AC12
AH8
AG8
AF7
FSB1A[4]#
FSB1A[5]#
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Source Sync
Source Sync
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
AN11
AM13
AL11
AR1
FSB1D[27]#
FSB1D[28]#
FSB1D[29]#
FSB1D[3]#
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
FSB1A[6]#
FSB1A[7]#
FSB1A[8]#
AL13
AK12
AV7
FSB1D[30]#
FSB1D[31]#
FSB1D[32]#
FSB1D[33]#
FSB1D[34]#
FSB1D[35]#
FSB1D[36]#
FSB1D[37]#
FSB1D[38]#
FSB1D[39]#
FSB1D[4]#
AE7
AP2
AC10
AG3
AG12
AG10
AJ4
FSB1A[9]#
FSB1ADS#
FSB1ADSTB[0]#
FSB1ADSTB[1]#
FSB1AP[0]#
FSB1AP[1]#
FSB1BINIT#
FSB1BNR#
FSB1BPM[4]#
FSB1BPM[5]#
FSB1BPRI#
FSB1BREQ[0]#
FSB1BREQ[1]#
FSB1D[0]#
AU8
AT9
AR9
AT8
AV9
AK3
AN2
AN3
AJ10
AL2
AU10
AV10
AR3
AV12
AT11
AT12
AP13
AP11
AR13
AR12
AP14
AH14
AM16
AR4
FSB1D[40]#
FSB1D[41]#
FSB1D[42]#
FSB1D[43]#
FSB1D[44]#
FSB1D[45]#
FSB1D[46]#
FSB1D[47]#
FSB1D[48]#
FSB1D[49]#
FSB1D[5]#
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AM1
AP1
AP5
AV4
FSB1D[1]#
FSB1D[10]#
FSB1D[11]#
FSB1D[12]#
FSB1D[13]#
FSB1D[14]#
FSB1D[15]#
FSB1D[16]#
FSB1D[17]#
FSB1D[18]#
FSB1D[19]#
FSB1D[2]#
AT6
AR6
AU7
AR7
AU5
AL7
AN14
AM15
AL14
AN15
AH16
AP16
AL16
AE10
AE11
AK5
FSB1D[50]#
FSB1D[51]#
FSB1D[52]#
FSB1D[53]#
FSB1D[54]#
FSB1D[55]#
FSB1D[56]#
FSB1REQ[4]#
FSB1RESET#
FSB1RS[0]#
FSB1RS[1]#
FSB1RS[2]#
FSB1RSP#
AL8
AN6
AK9
AP4
AM6
AM9
AJ13
AF15
AG15
AT2
FSB1D[20]#
FSB1D[21]#
FSB1D[57]#
FSB1D[58]#
FSB1D[59]#
FSB1D[6]#
I
AL1
I
AJ15
AJ16
FSB1D[60]#
FSB1D[61]#
AL5
I
AK2
I
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
441
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 7 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AG14
AF16
AT3
FSB1D[62]#
FSB1D[63]#
FSB1D[7]#
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
PEX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
AK6
AH4
AN5
AT14
AT35
AR34
AU35
AV13
AU17
K13
L12
Y9
FSB1TRDY#
FSB1VREF
FSB1VREF
FSB1VREF
FSBCRES
FSBODTCRES
FSBSLWCRES
FSBSLWCTRL
FSBVCCA
GPIOSMBCLK
GPIOSMBDATA
PE0RN[0]
PE0RN[1]
PE0RN[2]
PE0RN[3]
PE0RP[0]
PE0RP[1]
PE0RP[2]
PE0RP[3]
PE0TN[0]
Common Clk
Power/Other
Power/Other
Power/Other
Analog
Analog
Analog
Power/Other
Power/Other
SMB
O
AT5
FSB1D[8]#
AV6
AP7
AK11
AU11
AH13
AM4
AJ9
FSB1D[9]#
FSB1DBI[0]#
FSB1DBI[1]#
FSB1DBI[2]#
FSB1DBI[3]#
FSB1DBSY#
FSB1DEFER#
FSB1DP[0]#
FSB1DP[1]#
FSB1DP[2]#
FSB1DP[3]#
FSB1DRDY#
FSB1DSTBN[0]#
FSB1DSTBN[1]#
FSB1DSTBN[2]#
FSB1DSTBN[3]#
FSB1DSTBP[0]#
FSB1DSTBP[1]#
FSB1DSTBP[2]#
FSB1DSTBP[3]#
FSB1HIT#
I/O
I/O
I
SMB
AG11
AJ12
AF12
AF13
AM3
AU3
AL10
AP10
AK14
AU4
AM10
AR10
AK15
AK8
AJ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PEX
Y3
PEX
I
AB7
AA6
Y10
Y4
PEX
I
PEX
I
PEX
I
PEX
I
AB8
AA5
Y6
PEX
I
PEX
I
PEX
O
O
O
O
O
O
O
O
I
AA2
AB5
AA9
Y7
PE0TN[1]
PEX
PE0TN[2]
PEX
PE0TN[3]
PEX
PE0TP[0]
PEX
AA3
AB4
AA8
R5
PE0TP[1]
PEX
FSB1HITM#
FSB1LOCK#
FSB1MCERR#
FSB1REQ[0]#
FSB1REQ[1]#
FSB1REQ[2]#
FSB1REQ[3]#
PE2RP[1]
PE0TP[2]
PEX
AL4
PE0TP[3]
PEX
AH11
AG9
AD11
AJ6
PE2RN[0]
PE2RN[1]
PE2RN[2]
PE2RN[3]
PE2RP[0]
PE4TN[3]
PEX
P4
PEX
I
R3
PEX
I
U1
PEX
I
AF9
N4
T5
PEX
I
K11
H12
C12
C11
J11
PEX
O
O
O
O
O
I
P3
PE2RP[2]
PEX
I
PE4TP[0]
PEX
T1
PE2RP[3]
PEX
I
PE4TP[1]
PEX
T7
PE2TN[0]
PEX
O
PE4TP[2]
PEX
T4
PE2TN[1]
PEX
O
PE4TP[3]
PEX
P1
PE2TN[2]
PEX
O
G10
B9
PE5RN[0]
PE5RN[1]
PEX
T2
PE2TN[3]
PEX
O
PEX
I
®
442
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 8 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
T8
U4
PE2TP[0]
PE2TP[1]
PE2TP[2]
PE2TP[3]
PE3RN[0]
PE3RN[1]
PE3RN[2]
PE3RN[3]
PE3RP[0]
PE3RP[1]
PE3RP[2]
PE3RP[3]
PE3TN[0]
PE3TN[1]
PE3TN[2]
PE3TN[3]
PE3TP[0]
PE3TP[1]
PE3TP[2]
PE3TP[3]
PE4RN[0]
PE4RN[1]
PE4RN[2]
PE4RN[3]
PE4RP[0]
PE4RP[1]
PE4RP[2]
PE4RP[3]
PE4TN[0]
PE4TN[1]
PE4TN[2]
PE7RN[1]
PE7RN[2]
PE7RN[3]
PE7RP[0]
PE7RP[1]
PE7RP[2]
PE7RP[3]
PE7TN[0]
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
O
O
O
O
I
G8
H7
H10
C9
F8
PE5RN[2]
PE5RN[3]
PE5RP[0]
PE5RP[1]
PE5RP[2]
PE5RP[3]
PE5TN[0]
PE5TN[1]
PE5TN[2]
PE5TN[3]
PE5TP[0]
PE5TP[1]
PE5TP[2]
PE5TP[3]
PE6RN[0]
PE6RN[1]
PE6RN[2]
PE6RN[3]
PE6RP[0]
PE6RP[1]
PE6RP[2]
PE6RP[3]
PE6TN[0]
PE6TN[1]
PE6TN[2]
PE6TN[3]
PE6TP[0]
PE6TP[1]
PE6TP[2]
PE6TP[3]
PE7RN[0]
RSVD
PEX
PEX
I
I
N1
PEX
I
R2
PEX
I
W2
V6
PEX
I
I
G7
H9
E9
C8
E7
J9
PEX
I
W8
U10
V2
I
PEX
O
O
O
O
O
O
O
O
I
I
PEX
I
PEX
V5
I
PEX
W7
U9
I
PEX
I
F9
PEX
V3
O
O
O
O
O
O
O
O
I
D8
D7
C5
E3
F5
PEX
W4
U7
PEX
PEX
V9
PEX
I
U3
PEX
I
W5
U6
K8
C6
E4
F6
PEX
I
PEX
I
V8
PEX
I
E12
F11
E10
L10
F12
G11
D10
K10
J12
B12
D11
E1
PEX
I
I
J8
PEX
I
I
M8
D4
C2
J6
PEX
O
O
O
O
O
O
O
O
I
I
PEX
I
PEX
I
PEX
I
M9
D5
C3
H6
F2
PEX
I
PEX
O
O
O
I
PEX
PEX
PEX
M2
M3
M5
M6
M12
N2
N5
N7
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
H4
I
RSVD
L4
I
RSVD
F3
I
RSVD
D1
I
RSVD
H3
I
RSVD
K4
I
RSVD
G4
O
RSVD
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
443
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 9 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
G1
L7
PE7TN[1]
PE7TN[2]
PE7TN[3]
PE7TP[0]
PE7TP[1]
PE7TP[2]
PE7TP[3]
PECLKN
PEX
PEX
O
O
O
O
O
O
O
N8
N10
P6
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SPD0SMBCLK
VCC
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
SMB
K5
PEX
G5
PEX
P7
G2
PEX
P9
K7
PEX
P10
R6
J5
PEX
K2
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Power/Other
Power/Other
Power/Other
Power/Other
CMOS
R8
J2
PECLKP
R9
R12
P12
K1
PEICOMPI
PERCOMPO
PEVCCA
T37
W1
Y1
R11
L1
PEVCCBG
PEVSSA
AE8
AG2
AG6
AH7
AJ1
N11
AA11
Y12
W11
W10
AC1
AB2
AB1
H17
G17
M11
D29
H1
PEVSSBG
PEWIDTH[0]
PEWIDTH[1]
PEWIDTH[2]
PEWIDTH[3]
PSEL[0]
I
I
I
I
I
I
I
I
I
AK17
AK23
AM7
AM24
AM31
AN23
AP28
AP32
AR15
AR16
AR33
AV27
H13
T18
PSEL[1]
CMOS
PSEL[2]
CMOS
PWRGOOD
RESETI#
CMOS
CMOS
RSV1
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
SMB
RSVD
RSVD
J3
RSVD
L3
RSVD
L6
RSVD
I/O
G13
J16
K15
F15
E15
H15
H16
A6
SPD0SMBDATA
SPD1SMBCLK
SPD1SMBDATA
SPD2SMBCLK
SPD2SMBDATA
SPD3SMBCLK
SPD3SMBDATA
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
SMB
T20
VCC
SMB
T22
VCC
SMB
T24
VCC
SMB
U15
U17
U19
U21
U23
VCC
SMB
VCC
SMB
VCC
JTAG
VCC
B7
TDI
JTAG
I
VCC
®
444
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 10 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
A4
B4
TDIOANODE
TDIOCATHODE
TDO
Analog
V16
V18
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FBD
Analog
B6
JTAG
Ouput
V20
VCC
AC36
F17
TESTHI
TESTHI_V3REF
TESTHI_V3REF
TMS
No Connect
Power/Other
Power/Other
JTAG
V22
VCC
V24
VCC
G16
A7
W15
W17
W19
W21
W23
Y16
VCC
I
I
VCC
A8
TRST#
V3REF
VCC
JTAG
VCC
F13
Analog
VCC
L16
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
L17
VCC
VCC
L18
VCC
Y18
VCC
L19
VCC
Y20
VCC
M16
M17
M18
N17
N19
P16
P18
P20
P22
P24
R15
R17
R19
R21
R23
T16
VCC
Y22
VCC
VCC
Y24
VCC
VCC
AA13
AA15
AA17
AA19
AA21
AA23
AB13
AB14
AB16
AB18
AB20
AB22
AB24
AC15
R25
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AC17
AC19
AC21
AC23
AC25
AC26
AD26
AE35
AH10
AL17
VCC
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCC
T25
VCC
T26
VCC
T27
I
VCC
U25
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
U26
VCC
V25
VCC
V26
VCC
W25
W26
VCC
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
445
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 11 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
A20
E20
E23
F25
H20
H23
K21
K22
K23
L20
L21
L22
L23
M20
M21
M22
M23
M24
M25
N20
N21
N22
N23
N24
N25
N26
P25
P26
T13
T14
U2
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCPE
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Y25
Y26
AA25
AA26
AA27
AB25
AB26
G12
J10
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
L2
L8
L13
L14
L15
M13
M14
M15
N6
N12
N13
N14
N15
P13
P14
R4
R10
R13
R14
C7
VCCPE
C10
C15
C19
C22
C24
C26
C27
C29
C30
C32
VSS
VCCPE
VSS
U8
VCCPE
VSS
U13
U14
V13
V14
W6
VCCPE
VSS
VCCPE
VSS
VCCPE
VSS
VCCPE
VSS
VCCPE
VSS
W12
W13
VCCPE
VSS
VCCPE
VSS
®
446
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 12 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
W14
Y13
Y14
L24
A3
VCCPE
VCCPE
VCCPE
VCCSEN
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Temp
C33
C35
C38
D3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
D6
A9
D9
A13
A18
A21
A23
A25
A28
A31
A34
A36
B2
D12
D14
D18
D21
D24
D27
D30
D33
D36
E2
B3
E5
B5
E8
B8
E11
E13
E17
E21
E26
E29
E32
E35
F1
B11
B16
B17
B20
B23
B37
C1
C4
F4
H35
J1
F7
F10
F16
F19
F21
F22
F26
F28
F31
F34
F38
J4
J7
J13
J17
J19
J22
J25
J26
J27
J28
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
447
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 13 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
G3
G6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J29
J30
J31
J34
J38
K3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
G9
G15
G18
G21
G24
G27
G30
G31
G32
G33
G36
G37
H2
K6
K9
K12
K16
K17
K20
K24
K25
K26
K27
K28
K29
K30
K33
K36
K37
L5
H5
H8
H11
H14
H26
H27
H28
H29
H30
H31
H32
L32
L35
M1
L11
L26
L29
R16
R18
R20
R22
R24
R26
R27
R28
R29
R30
R31
R34
R37
M4
M7
M10
M19
M28
M31
M34
M37
M38
N3
®
448
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 14 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
N9
N16
N18
N27
N30
N31
N33
N36
P2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
T3
T6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
T9
T10
T11
T12
T15
T17
T19
T21
T23
T29
T30
T33
T36
U5
P5
P8
P11
P15
P17
P19
P21
P23
P29
P30
P31
P32
P35
P38
R1
U11
U12
U16
U18
U20
U22
U24
U29
U32
Y29
Y32
Y35
Y38
AA1
AA4
AA7
AA10
AA14
AA16
AA18
AA20
AA22
AA24
R7
U35
U38
V1
V4
V7
V10
V11
V12
V15
V17
V19
V21
V23
V28
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
449
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 15 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
V31
V34
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AA28
AA29
AA30
AA31
AA34
AA37
AB3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
V37
W3
W9
W16
W18
W20
W22
W24
W27
W30
W33
W36
W37
Y2
AB6
AB9
AB12
AB15
AB17
AB19
AB21
AB23
AB27
AB28
AB29
AB30
AB33
AB36
AC2
Y5
Y8
Y11
Y15
Y17
Y19
Y21
AC5
Y23
AC8
AC11
AC16
AC18
AC20
AC22
AC24
AC27
AC28
AC29
AC32
AC35
AC38
AD1
AD4
AD7
AF24
AF26
AF27
AF29
AF32
AF35
AF36
AG1
AG4
AG7
AG13
AG16
AG17
AG22
AG25
®
450
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 16 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AD10
AD27
AD28
AD31
AD34
AD36
AD37
AD38
AE3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AG28
AG31
AG34
AG37
AG38
AH3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
No Connect
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AH6
AH9
AH12
AH15
AH17
AH24
AH27
AH30
AH33
AJ2
AE6
AE9
AE12
AE27
AE30
AE33
AF2
AF5
AJ5
AF8
AJ8
AF10
AF11
AF14
AF17
AF23
AJ29
AJ32
AJ35
AJ36
AK1
AJ11
AJ14
AJ17
AJ23
AJ26
AN1
AN4
AN7
AN10
AN13
AN16
AN22
AN25
AN28
AN31
AN34
AN37
AN38
AP3
AK4
AK7
AK10
AK13
AK16
AK22
AK25
AK28
AK31
AK34
AK37
AP6
AP9
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
451
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 17 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AK38
AL3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AP12
AP15
AP24
AP27
AP30
AP33
AR2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AL6
AL9
AL12
AL15
AL24
AL27
AL30
AL33
AM2
AR5
AR8
AR11
AR14
AR17
AR23
AR26
AR29
AR32
AR35
AR36
AT1
AM5
AM8
AM11
AM14
AM17
AM23
AM26
AM29
AM32
AM35
AM36
AT13
AT15
AT16
AT22
AT25
AT28
AT31
AT34
AT38
AU2
AT4
AT7
AT10
AC14
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AE13
AE14
AE15
AU6
AU9
AU12
AU13
AU14
AU15
AU24
®
452
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 18 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AU27
AU30
AU33
AU37
AV3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQUIET
VSSSEN
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Analog
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF18
AF19
AF20
AF21
AG18
AG19
AG20
AG21
AH18
AH19
AV18
AV19
AV20
AV21
F14
VTT
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Analog
VTT
VTT
VTT
AV5
VTT
AV8
VTT
AV11
AV14
AV15
AV16
AV17
AV23
AV26
AV29
AV32
AV35
AV36
L9
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
L25
Temp
VTT
AC13
AH20
AH21
AJ18
AJ19
AJ20
AJ21
AK18
AK19
AK20
AK21
AL18
AL19
AL20
AL21
AM18
AM19
AM20
AM21
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
XDPCOMCRES
XDPD[0]#
XDPD[1]#
XDPD[10]#
XDPD[11]#
XDPD[12]#
XDPD[13]#
XDPD[14]#
XDPD[15]#
XDPD[2]#
XDPD[3]#
XDPD[4]#
XDPD[5]#
XDPD[6]#
VTT
A11
XDP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VTT
B10
XDP
VTT
A14
XDP
VTT
A16
XDP
VTT
C16
XDP
VTT
A15
XDP
VTT
D16
XDP
VTT
E16
XDP
VTT
A10
XDP
VTT
D13
XDP
VTT
A12
XDP
VTT
E14
XDP
VTT
B13
XDP
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
453
Ballout and Package Information
Table 8-2.
Intel 5000X Chipset MCH Signals (by Signal Name) (Sheet 19 of 19)
Ball No.
Signal Name
Buffer Type
Direction
Ball No.
Signal Name
Buffer Type
Direction
AN18
AN19
AN20
AN21
AP18
AP19
AP20
AP21
AR18
AR19
AR20
AR21
AT18
AT19
AT20
AT21
AU18
AU19
AU20
AU21
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
B14
D15
B15
C13
C14
G14
A17
J15
XDPD[7]#
XDPD[8]#
XDP
XDP
I/O
I/O
I/O
I/O
I/O
XDPD[9]#
XDP
XDPDSTBN#
XDPDSTBP#
XDPODTCRES
XDPRDY#
XDP
XDP
Analog
XDP
I/O
XDPSLWCRES
Analog
®
454
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
8.2
Package Information
Figure 8-5. Bottom View
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
455
Ballout and Package Information
Figure 8-6. Top View
®
456
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
Ballout and Package Information
Figure 8-7. Package Stackup
®
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
457
Ballout and Package Information
Figure 8-8. Notes
§
®
458
Intel 5000X Chipset Memory Controller Hub (MCH) Datasheet
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