RD28F1608VPPT110 [INTEL]

Memory IC;


型号：	RD28F1608VPPT110
厂家：	INTEL
描述：	Memory IC
文件：	总66页 (文件大小：958K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

3 Volt Advanced+ Stacked Chip Scale

Package Memory

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Preliminary Datasheet

Product Features

■ Flash Memory Plus SRAM

■ Advanced+ Boot Block Flash Memory

—90 ns 16-Mb Access Time at 2.7 V

—100 ns 32-Mb Access Time at 2.7 V

—Reduces Memory Board Space

Required, Simplifying PCB Design

Complexity

—110 ns 32-Mb Access Time at 2.7 V with

8-Mbit SRAM

—Instant, Individual Block Locking

—128-bit Protection Register

■ Stacked Chip Scale Package Technology

—Smallest Memory Subsystem Footprint

—16-Mbit Flash + 2-Mbit SRAM:

Area: 8 mm by 10 mm, Height: 1.4 mm

—12 V Production Programming

—Ultra Fast Program and Erase Suspend

—Extended Temperature –25 °C to +85 °C

■ Blocking Architecture

—Block Sizes for Code + Data Storage

—4-Kword Parameter Blocks (for data)

—64-Kbyte Main Blocks (for code)

—100,000 Erase Cycles per Block

■ Low Power Operation

—32-Mbit Flash + 4-Mbit SRAM:

Area: 8 mm by 14mm, Height: 1.4 mm

—32-Mbit Flash + 8-Mbit SRAM,

16-Mbit Flash + 4-Mbit SRAM:

Area: 8 mm by 12 mm, Height: 1.4 mm

■ Advanced SRAM Technology

—70 ns Access Time

—Low Power Operation

—Low Voltage Data Retention Mode

■ Flash Data Integrator (FDI) Software

—Async Read Current: 9 mA

—Real-Time Data Storage and Code

Execution in the Same Memory Device

—Full Flash File Manager Capability

—Standby Current: 10 µA

—Automatic Power Saving Mode

■ 0.25 µm ETOX™ VI Flash Technology

■ Industry Compatibility

—Sourcing Flexibility and Stability

The 3 Volt Advanced+ Stacked Chip Scale Package (Stacked-CSP) memory delivers a feature-

rich solution for low-power applications. Stacked-CSP memory devices incorporate flash

memory and static RAM in one package with low voltage capability to achieve the smallest

system memory solution form-factor together with high-speed, low-power operations. The flash

memory offers a protection register and flexible block locking to enable next generation security

capability. Combined with the Intel-developed Flash Data Integrator (FDI) software, the

Stacked-CSP memory provides you with a cost-effective, flexible, code plus data storage

solution.

Notice: This document contains preliminary information on new products in production. The

specifications are subject to change without notice. Verify with your local Intel sales office that

you have the latest datasheet before finalizing a design.

Order Number: 290666-006

August, 2000

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any

intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no

liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties

relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are

not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 28F1602C3, 28F1604C3, 28F3204C3 may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

*Other brands and names are the property of their respective owners.

PRELIMINARY

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Contents

1.0

Introduction..................................................................................................................1

1.1

1.2

1.3

1.4

Document Conventions.........................................................................................1

Product Overview..................................................................................................1

Package Ballout ....................................................................................................2

Signal Definitions...................................................................................................3

2.0

Principles of Operation............................................................................................5

2.1

Bus Operation .......................................................................................................5

2.1.1 Read.........................................................................................................5

2.1.2 Output Disable..........................................................................................6

2.1.3 Standby ....................................................................................................6

2.1.4 Flash Reset ..............................................................................................7

2.1.5 Write.........................................................................................................7

3.0

Flash Memory Modes of Operation.....................................................................7

3.1

3.2

3.3

Read Array (FFh) ..................................................................................................7

Read Identifier (90h)..............................................................................................7

Read Status Register (70h)...................................................................................8

3.3.1 Clear Status Register (50h)......................................................................8

Read Query (98h)..................................................................................................9

Word Program (40h/10h).......................................................................................9

3.5.1 Suspending and Resuming Program (B0h/D0h)......................................9

Block Erase (20h)................................................................................................10

3.6.1 Suspending and Resuming Erase (B0h/D0h) ........................................10

Instant, Individual Block Locking .........................................................................12

3.7.1 Block Locking Operation Summary........................................................12

3.7.2 Locked State ..........................................................................................13

3.7.3 Unlocked State.......................................................................................13

3.7.4 Lock-Down State....................................................................................13

3.7.5 Reading a Block’s Lock Status...............................................................13

3.7.6 Locking Operation during Erase Suspend..............................................14

3.7.7 Status Register Error Checking..............................................................14

128-Bit Protection Register .................................................................................15

3.8.1 Reading the Protection Register ............................................................15

3.8.2 Programming the Protection Register (C0h) ..........................................15

3.8.3 Locking the Protection Register .............................................................16

Additional Flash Features....................................................................................16

3.9.1 Improved 12 Volt Production Programming ...........................................16

3.9.2 F-VPP £ VPPLK for Complete Protection ..............................................17

3.4

3.5

3.6

3.7

3.8

3.9

4.0

Electrical Specifications........................................................................................17

4.1

4.2

4.3

4.4

4.5

4.6

Absolute Maximum Ratings.................................................................................17

Operating Conditions...........................................................................................18

Capacitance ........................................................................................................18

DC Characteristics ..............................................................................................19

Flash AC Characteristics—Read Operations......................................................23

Flash AC Characteristics—Write Operations ......................................................25

PRELIMINARY

iii

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

4.7

Flash Erase and Program Timings(1) .................................................................26

4.8

4.9

4.10

4.11

Flash Reset Operations ......................................................................................28

SRAM AC Characteristics—Read Operations(1)................................................29

SRAM AC Characteristics—Write Operations(1, 2)............................................31

SRAM Data Retention Characteristics(1) —Extended Temperature ..................32

5.0

6.0

Migration Guide Information ...............................................................................33

System Design Considerations..........................................................................34

6.1

Background.........................................................................................................34

6.1.1 Flash + SRAM Footprint Integration.......................................................34

6.1.2 Advanced+ Boot Block Flash Memory Features....................................34

Flash Control Considerations..............................................................................34

6.2.1 F-RP# Connected to System Reset.......................................................35

6.2.2 F-VCC, F-VPP and F-RP# Transition.....................................................35

Noise Reduction..................................................................................................36

Simultaneous Operation......................................................................................37

6.4.1 SRAM Operation during Flash “Busy”....................................................38

6.4.2 Simultaneous Bus Operations................................................................38

Printed Circuit Board Notes.................................................................................38

System Design Notes Summary .........................................................................38

6.2

6.3

6.4

6.5

6.6

7.0

8.0

Ordering Information..............................................................................................39

Additional Information...........................................................................................39

Appendix A Program/Erase Flowcharts.............................................................................40

Appendix B CFI Query Structure...........................................................................................46

Appendix C Word-Wide Memory Map Diagrams.............................................................53

Appendix D Device ID Table....................................................................................................55

Appendix E Protection Register Addressing...................................................................56

Appendix F Mechanical and Shipping Media Details...................................................57

PRELIMINARY

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Revision History

Date of

Version

Revision

Description

03/30/99

04/26/99

-001

-002

Original version

Corrected title headings in Appendix B

Removed reference to 8-Mbit devices, Appendix B, Table B7, Device Geometry

Definition

Corrected 4-Mb SRAM I

specification

CC2

06/15/99

08/11/99

-003

-004

Removed extra SRAM standby mode

Clarified Locking Operations Flowchart (Appendix A)

Added 16Mbit Flash + 4Mbit SRAM product references

Clarified Operating Mode Table (Section 4.1.2)

Clarified“Unlock” in CommandBusDefinitions Table(Section5.0)

Updated DC characteristics V ,V ,and I

(Section 9.4)

IL IH

CCD

Updated AC characteristics t

(Section 9.5)

EHQZ

Updated AC characteristics t (Section 9.9)

Removed 3.0-3.3V specifications (Section 9.5 and Section 9.6)

01/20/00

08/09/00

-005

-006

Increased Erase Cycles per Block to 1,000,000

Pinout Update (Figure 1)

Operating Modes clarifications (Table 3)

Clarified product proliferations

Structure/Text of document simplified for readability

Datasheet changed to “Preliminary” status

Change the Erase Cycles per Block to 100,000

Pinout update (Figure 1)

Figure 2 FvvQ line added

Operating Modes added S-UB# and S-LB#, and modify S-WE# output disable

and notes updates.

Spec minimum Temperature change from -40’C to -25’C

Change V

to V , Change S-CS#1 to S-CS1#

CC1

Added 8-Meg SRAM specifications

PRELIMINARY

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

1.0

Introduction

This document contains the specifications for the 3 Volt Advanced+ Stacked Chip Scale Package

(Intel^®Stacked-CSP) memory. These stacked memory solutions are offered in the following

combinations: 32-Mbit flash + 8-Mbit SRAM, 32-Mbit flash + 4-Mbit SRAM, 16-Mbit flash +

4-Mbit SRAM, or 16-Mbit flash memory + 2-Mbit SRAM.

1.1

Document Conventions

Throughout this document, the following conventions have been adopted.

• Voltages: “2.7 V” refers to the full voltage range, 2.7 V–3.3V; 12 V refers to 11.4 V to 12.6 V

• Main block(s): 32-Kword block

• Parameter block(s): 4-Kword block

1.2

Product Overview

The 3 Volt Advanced+ Stacked-CSP combines flash and SRAM into a single package.

The Intel Stacked-CSP memory provides secure low-voltage memory solutions for portable

applications. This memory family combines two memory technologies, flash memory and SRAM,

in one package. The flash memory delivers enhanced security features, a block locking capability

that allows instant locking/unlocking of any flash block with zero-latency, and a 128-bit protection

applications. Improved 12 V production programming can be used to improve factory throughput.

Table 1. Block Organization (x16)⁽¹⁾

Memory Device

Kwords

32-Mbit Flash

16-Mbit Flash

2-Mbit SRAM

4-Mbit SRAM

8-Mbit SRAM

2048

1024

128

256

512

NOTE: 1. All words are 16 bits each.

The flash device is asymmetrically-blocked to enable system integration of code and data storage

in a single device. Each flash block can be erased independently of the others up to 100,000 times.

The flash has eight 8-KB parameter blocks located at either the top (denoted by -T suffix) or the

bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols

for kernel code location. The remaining flash memory is grouped into 32-Kword main blocks. Any

individual flash block can be locked or unlocked instantly to provide complete protection for code

or data (see Section 4.7, “Flash Erase and Program Timings(1)” on page 26 for details).

The flash contains both a Command User interface (CUI) and a Write State Machine (WSM). The

CUI serves as the interface between the microcontroller and the internal operation of the flash

memory. The internal WSM automatically executes the algorithms and timings necessary for

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

program and erase operations, including verification, thereby unburdening the microprocessor or

microcontroller. The flash’s status register indicates the status of the WSM by signifying block

erase or word program completion and status.

Flash program and erase automation allows program and erase operations to be executed using an

industry-standard two-write command sequence to the CUI. Program operations are performed in

word increments. Erase operations erase all locations within a block simultaneously. Both program

and erase operations can be suspended by the system software in order to read from any other flash

block. In addition, data can be programmed to another flash block during an erase suspend.

3 Volt Advanced+ Stacked-CSP memories offer two low-power savings features: Automatic Power

Savings (APS) for flash memory and standby mode for flash and SRAM. The device automatically

enters APS mode following the completion of a read cycle from the flash memory. Standby mode

is initiated when the system deselects the device by driving F-CE# and S-CS₁# or

S-CS₂inactive. Power savings features significantly reduce power consumption.

The flash memory can be reset by lowering F-RP# to GND. This provides CPU-memory reset

synchronization and additional protection against bus noise that may occur during system reset and

power-up/-down sequences.

1.3

Package Ballout

72-

Figure 1. 68-Ball Stacked Chip Scale Package

F-V_SSF-V_CCQ

A₂₀

A₁₆

A₁₁

A₈

A₁₅

A₁₀

A₂₁

A₁₄

A₁₃

A₁₂

A₉DQ₁₅S-WE#

DQ₇

DQ₁₄

F-WE# NC

DQ₁₃DQ₆DQ₄DQ₅

S-V_SSF-RP# A₂₂

DQ₁₂S-CS₂S-V_CCF-V_CC

DQ₁₀DQ₂DQ₃

F-WP# V_PPA₁₉DQ₁₁

S-UB#

A₁₇

DQ₉DQ₈DQ₀DQ₁

S-LB#

A₁₈

S-OE#

A₇

A₆

A₃

A₂

A₁S-CS₁#

A₅

A₄

A₀F-CE# F-V_SSF-OE# NC

Top View, Balls Down

NOTE: Flash upgrade address lines are shown for A (64-Mbit flash) and A (128-Mbit flash). In all flash and

SRAM combinations, 66 balls are populated (A and A are not populated). Location A is “NC” on

16/2 devices only.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

1.4

Signal Definitions

Table 2. defines the signal definitions shown in the previous ballout.

Table 2. 3 Volt Advanced+ Stacked-CSP Ball Descriptions

Symbol

Type

Name and Function

ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or

erase cycle.

INPUT

0– 20

Flash: 16-Mbit x 16, A[0-19]; 32-Mbit x 16, A[0-20]

SRAM: 2-Mbit x 16, A[0-16]; 4-Mbit x 16, A[0-17];8-Mbit x 16, A[0-18]

DATA INPUTS/OUTPUTS: Inputs array data for SRAM write operations and on the second F-CE#

and F-WE# cycle during a flash Program command. Inputs commands to the flash’s Command

User Interface when F-CE# and F-WE# are active. Data is internally latched. Outputs array,

configuration and status register data. The data balls float to tri-state when the chip is de-selected

or the outputs are disabled.

INPUT /

OUTPUT

0–

FLASH CHIP ENABLE: Activates the flash internal control logic, input buffers, decoders and

sense amplifiers. F-CE# is active low. F-CE# high de-selects the flash memory device and reduces

power consumption to standby levels.

F-CE#

INPUT

SRAM CHIP SELECT1: Activates the SRAM internal control logic, input buffers, decoders and

S-CS #

sense amplifiers. S-CS # is active low. S-CS # high de-selects the SRAM memory device and

1 1

reduces power consumption to standby levels.

SRAM CHIP SELECT2: Activates the SRAM internal control logic, input buffers, decoders and

S-CS

sense amplifiers. S-CS is active high. S-CS low de-selects the SRAM memory device and

2 2

reduces power consumption to standby levels.

FLASH OUTPUT ENABLE: Enables flash’s outputs through the data buffers during a read

operation. F-OE# is active low.

F-OE#

S-OE#

INPUT

SRAM OUTPUT ENABLE: Enables SRAM’s outputs through the data buffers during a read

operation. S-OE# is active low.

FLASH WRITE ENABLE: Controls writes to flash’s command register and memory array. F-WE#

is active low. Addresses and data are latched on the rising edge of the second F-WE# pulse.

F-WE#

S-WE#

S-UB#

INPUT

SRAM WRITE ENABLE: Controls writes to the SRAM memory array. S-WE# is active low.

SRAM UPPER BYTE ENABLE: Enables the upper bytes for SRAM (DQ –DQ ).

S-UB# is active low.

SRAM LOWER BYTE ENABLE: Enables the lower bytes for SRAM (DQ –DQ ).

S-LB# is active low.

S-LB#

INPUT

FLASH RESET/DEEP POWER-DOWN: Uses two voltage levels (V , V ) to control reset/deep

power-down mode.

When F-RP# is at logic low, the device is in reset/deep power-down mode, which drives the

outputs to High-Z, resets the Write State Machine, and minimizes current levels (I ).

F-RP#

INPUT

CCD

When F-RP# is at logic high, the device is in standard operation. When F-RP# transitions from

logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode.

FLASH WRITE PROTECT: Controls the lock-down function of the flexible Locking feature.

When F-WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-

down cannot be unlocked through software.

F-WP#

INPUT

When F-WP# is logic high, the lock-down mechanism is disabled and blocks previously

locked-down are now locked and can be unlocked and locked through software. After F-WP# goes

low, any blocks previously marked lock-down revert to that state.

See Section 6.0, “System Design Considerations” on page 34 for details on block locking.

FLASH POWER SUPPLY: [2.7 V–3.3 V] Supplies power for device core operations.

FLASH I/O POWER SUPPLY: [2.7 V–3.3 V] Supplies power for device I/O operations.

F-V

SUPPLY

CCQ

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 2. 3 Volt Advanced+ Stacked-CSP Ball Descriptions

Symbol

Type

Name and Function

SRAM POWER SUPPLY: [2.7 V–3.3 V] Supplies power for device operations.

S-V

SUPPLY

See Section 6.2.2, “F-VCC, F-VPP and F-RP# Transition” on page 35 for details of power

connections.

FLASH PROGRAM/ERASE POWER SUPPLY: [1.65 V–3.3 V or 11.4 V–12.6 V] Operates as an

input at logic levels to control complete flash protection. Supplies power for accelerated flash

program and erase operations in 12 V ± 5% range. This ball cannot be left floating.

Lower F-V ≤ V

, to protect all contents against Program and Erase commands.

PPLK

Set F-V = F-V for in-system read, program and erase operations. In this configuration,

INPUT /

SUPPLY

F-V

F-V can drop as low as 1.65 V to allow for resistor or diode drop from the system supply. Note

that if F-V is driven by a logic signal, V

1.65 V. That is, F-V must remain above 1.65 V to

IH =

perform in-system flash modifications.

Raise F-V to 12 V ± 5% for faster program and erase in a production environment. Applying

12 V ± 5% to F-V can only be done for a maximum of 1000 cycles on the main blocks and 2500

cycles on the parameter blocks. F-V may be connected to 12 V for a total of 80 hours maximum.

F-GND

S-GND

SUPPLY

FLASH GROUND: For all internal circuitry. All ground inputs must be connected.

SRAM GROUND: For all internal circuitry. All ground inputs must be connected.

NOT CONNECTED: Internally disconnected within the device.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

2.0

Principles of Operation

The flash memory utilizes a CUI and automated algorithms to simplify program and erase

operations. The WSM automates program and erase operations by handling data and address

latches, WE#, and system status requests.

Figure 2. 3 Volt Advanced+ Stacked Chip Scale Package Block Diagram

F-V_PP

F-V_CC

F-GND

F-CE#

F-OE#

F-WE#

F-RP#

F-WP#

1,048,576 x16 bit (16 Mbit)

2,097,152 x16 bit (32 Mbit)

3 Volt Advanced+ Boot Block

Flash Memory

A_17-19/A_18-20

A_0-16/A_0-17

/ A_0-18

DQ_0-15

S-CS₁#

S-CS₂

131,072 x16 bit (2 Mbit)

262,144 x16 bit (4 Mbit)

S-OE#

S-WE#

SRAM

S-UB#

S-LB#

S-GND

S-V_CC

2.1

Bus Operation

All bus cycles to or from the Stacked-CSP conform to standard microcontroller bus cycles. Four

control signals dictate the data flow in and out of the flash component: F-CE#, F-OE#, F-WE# and

F-RP#. Four separate control signals handle the data flow in and out of the SRAM component:

S-CS₁#, S-CS₂, S-OE#, and S-WE#. These bus operations are summarized in Table 2 and Table 3.

2.1.1

Read

The flash memory has four read modes: read array, read identifier, read status and read query.

These flash memory read modes are not dependent on the F-V_PPvoltage. Upon initial device

power-up or after exit from reset, the flash device automatically defaults to read array mode. F-CE#

and F-OE# must be driven active to obtain data from the flash component.

The SRAM has one read mode available. S-CS₁#, S-CS₂, and S-OE# must be driven active to

obtain data from the SRAM device. See Table 3, “Recommended Memory System Operating

Mode Summary” on page 6 for a summary of operations.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 3. Recommended Memory System Operating Mode Summary

Flash Signals

SRAM Signals

Memory Output

Modes

Notes

D –

Read

Flash

Other

SRAM

2,3,4

2,4

5,6

2,4

OUT

SRAM must be in High Z

Write

Standby

Output Disable

Reset

High Z

Any SRAM mode is allowable

Read

FLASH must be in High Z

OUT

Write

Standby

Other

High Z

4,5,6

Any FLASH mode is allowable

Output Disable

Data Retention

Other

High Z

4,5,6

4,5,7

same as a standby

NOTES:

1. Signals S-UB# and S-LB# must be tied together.

2. Two devices may not drive the memory bus at the same time.

3. Allowable flash read modes include read array, read query, read configuration, and read status.

4. SRAM is enabled and/or disabled with the logical function: S-CS # OR S-CS

5. Outputs are dependent on a separate device controlling bus outputs.

6. Modes of the flash and SRAM can be interleaved so that while one is disabled, the other controls outputs.

7. The SRAM may be placed into data retention mode by lowering the S-V to the V range, as specified.

Simultaneous operations can exist, as long as the operations are interleaved such that only one

device attempts to control the bus outputs at a time.

2.1.2

2.1.3

Output Disable

With F-OE# and S-OE# inactive, the Stacked-CSP outputs signals are placed in a high-impedance

state.

Standby

With F-CE# and S-CS₁# or S-CS₂inactive, the Stacked-CSP enters a standby mode, which

substantially reduces device power consumption. In standby, outputs are placed in a high-

impedance state independent of F-OE# and S-OE#. If the flash is deselected during a program or

erase operation, the flash continues to consume active power until the program or erase operation is

complete.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

2.1.4

Flash Reset

The device enters a reset mode when RP# is driven low. In reset mode, internal circuitry is turned

off and outputs are placed in a high-impedance state.

After return from reset, a time t_PHQVis required until outputs are valid, and a delay (t_PHWLor

t_PHEL) is required before a write sequence can be initiated. After this wake-up interval, normal

operation is restored. The device defaults to read array mode, the status register is set to 80h, and

the read configuration register defaults to asynchronous reads.

If RP# is taken low during a block erase or program operation, the operation will be aborted and the

memory contents at the aborted location are no longer valid.

2.1.5

Write

Writes to flash take place when both F-CE# and F-WE# are low and F-OE# is high. Writes to

SRAM take place when both S-CS₁# and S-WE# are low and S-OE# and S-SC₂are high.

Commands are written to the flash memory’s Command User Interface (CUI) using standard

microprocessor write timings to control flash operations. The CUI does not occupy an addressable

memory location within the flash component. The address and data buses are latched on the rising

edge of the second F-WE# or F-CE# pulse, whichever occurs first. (See Figure 6 and Figure 7 for

read and write waveforms.)

3.0

Flash Memory Modes of Operation

The flash memory has four read modes: read array, read configuration, read status, and read query.

The write modes are program and erase. Three additional modes (erase suspend to program, erase

suspend to read and program suspend to read) are available only during suspended operations.

These modes are reached using the commands summarized in Table 5, “Flash Memory Command

Definitions” on page 11.

3.1

Read Array (FFh)

When F-RP# transitions from V_IL(reset) to V_IH, the device defaults to read array mode and will

respond to the read control inputs without any additional CUI commands.

In addition, the address of the desired location must be applied to the address balls. If the device is

not in read array mode, as would be the case after a program or erase operation, the Read Array

command (FFh) must be written to the CUI before array reads can take place.

3.2

Read Identifier (90h)

The read configuration mode outputs the manufacturer/device identifier. The device is switched to

this mode by writing the read configuration command (90h). Once in this mode, read cycles from

addresses shown in Table 4, “Read Configuration Table” on page 8 retrieve the specified

information. To return to read array mode, write the Read Array command (FFh).

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

The Read Configuration mode outputs three types of information: the manufacturer/device

identifier, the block locking status, and the protection register. The device is switched to this mode

by writing the Read Configuration command (90h). Once in this mode, read cycles from addresses

shown in Table 4 retrieve the specified information. To return to read array mode, write the Read

Array command (FFh).

Table 4. Read Configuration Table

Item

Address

Data

Manufacturer Code (x16)

Device ID (See Appendix D)

Block Lock Configuration⁽¹⁾

• Block Is Unlocked

00000

00001

0089

XX002⁽²⁾

LOCK

DQ = 0

• Block Is Locked

DQ = 1

• Block Is Locked-Down

Protection Register Lock³

Protection Register (x16)

DQ = 1

PR-LK

81-88

NOTES:

1. See Section 3.7 for valid lock status outputs.

2. “XX” specifies the block address of lock configuration being read.

3. See Section 3.8 for protection register information.

Other locations within the configuration address space are reserved by Intel for future use.

3.3

Read Status Register (70h)

The status register indicates the status of device operations, and the success/failure of that

operation. The Read Status Register (70h) command causes subsequent reads to output data from

the status register until another command is issued. To return to reading from the array, issue a

Read Array (FFh) command.

The status register bits are output on DQ₀–DQ₇. The upper byte, DQ₈–DQ₁₅, outputs 00h during a

Read Status Register command.

The contents of the status register are latched on the falling edge of F-OE# or F-CE#, whichever

occurs last. This prevents possible bus errors which might occur if status register contents change

while being read. F-CE# or F-OE# must be toggled with each subsequent status read, or the status

When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status

Table 6, “Flash Memory Status Register Definition” on page 12).

3.3.1

Clear Status Register (50h)

The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear

status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these

bits can only be cleared through the use of the Clear Status Register (50h) command. By allowing

the system software to control the resetting of these bits, several operations may be performed

(such as cumulatively programming several addresses or erasing multiple blocks in sequence)

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

before reading the status register to determine if an error occurred during that series. Clear the

status register before beginning another command or sequence. Note that the Read Array command

must be issued before data can be read from the memory array. Resetting the device also clears the

status register.

3.4

3.5

Read Query (98h)

The read query mode outputs Common Flash Interface (CFI) data when the device is read. This can

be accessed by writing the Read Query Command (98h). The CFI data structure contains

information such as block size, density, command set and electrical specifications. Once in this

mode, read cycles from addresses shown in Appendix B retrieve the specified information. To

return to read array mode, write the Read Array command (FFh).

Word Program (40h/10h)

Programming is executed using a two-write sequence. The Program Setup command (40h) is

written to the CUI followed by a second write which specifies the address and data to be

programmed. The WSM will execute a sequence of internally timed events to program desired bits

of the addressed location, then verify the bits are sufficiently programmed. Programming the

memory results in specific bits within an address location being changed to a “0.” If the user

attempts to program “1”s, the memory cell contents do not change and no error occurs.

The status register indicates programming status: while the program sequence executes, status bit 7

is “0.” The status register can be polled by toggling either F-CE# or F-OE#. While programming,

the only valid commands are Read Status Register, Program Suspend, and Program Resume.

When programming is complete, the program status bits should be checked. If the programming

operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If

SR.3 is set then F-V_PPwas not within acceptable limits, and the WSM did not execute the program

command. If SR.1 is set, a program operation was attempted on a locked block and the operation

was aborted.

The status register should be cleared before attempting the next operation. Any CUI instruction can

follow after programming is completed; however, to prevent inadvertent status register reads, be

sure to reset the CUI to read array mode.

3.5.1

Suspending and Resuming Program (B0h/D0h)

The Program Suspend command halts an in-progress program operation so that data can be read

from other locations of memory. Once the programming process starts, writing the Program

Suspend command to the CUI requests that the WSM suspend the program sequence (at

predetermined points in the program algorithm). The device continues to output status register data

after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will

determine when the program operation has been suspended (both will be set to “1”). t_WHRH1

t_EHRH1specify the program suspend latency.

A Read Array command can be written to the CUI to read data from any block other than the

suspended block. The only other valid commands, while program is suspended, are Read Status

command is written to the flash memory, the WSM will continue with the programming process

and status register bits SR.2 and SR.7 will automatically be cleared. The device automatically

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

outputs status register data when read (see Appendix A, Program Suspend/Resume Flowcharts)

after the Program Resume command is written. F-V_PPmust remain at the same F-V_PPlevel used

for program while in program suspend mode. F-RP# must also remain at V_IH.

3.6

Block Erase (20h)

To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an

address identifying the block to be erased. This address is latched internally when the Erase

Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only

one block can be erased at a time. The WSM will execute a sequence of internally timed events to

program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all

bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”

When the status register indicates that erasure is complete, check the erase status bit to verify that

the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status

after the Erase Confirm command was issued, the WSM will not execute the erase sequence;

instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to

identify that F-V_PPsupply voltage was not within acceptable limits.

After an erase operation, clear the status register (50h) before attempting the next operation. Any

CUI instruction can follow after erasure is completed; however, to prevent inadvertent status

3.6.1

Suspending and Resuming Erase (B0h/D0h)

Since an erase operation requires on the order of seconds to complete, an Erase Suspend command

is provided to allow erase-sequence interruption in order to read data from or program data to

another block in memory. Once the erase sequence is started, writing the Erase Suspend command

to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status

specified by t_WHRH2/t_EHRH2

A Read Array/Program command can now be written to the CUI to read/program data from/to

blocks other than that which is suspended. This nested Program command can subsequently be

suspended to read yet another location. The only valid commands while erase is suspended are

Read Status Register, Read Configuration, Read Query, Program Setup, Program Resume, Erase

Resume, Lock Block, Unlock Block and Lock-Down Block. During erase suspend mode, the chip

can be placed in a pseudo-standby mode by taking F-CE# to V_IH. This reduces active current

consumption.

Erase Resume continues the erase sequence when F-CE# = V_IL. As with the end of a standard erase

operation, the status register must be read and cleared before the next instruction is issued.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 5. Flash Memory Command Definitions

First Bus Cycle

Second Bus Cycle

Command

Note

Operation

Address

Data

Operation

Address

Data

Read Array

1, 2

Write

FFh

90h

Read Identifier

Read

Read Query

98h

Read Status Register

Clear Status Register

Word Program

70h

SRD

50h

1, 3

40h/10h

20h

Write

Block Erase/Confirm

Program/Erase Suspend

Program/Erase Resume

Lock Block

D0h

B0h

D0h

60h

Write

01h

D0h

2Fh

Unlock Block

1, 4

60h

Lock-Down Block

Protection Register Program

Lock Protection Register

60h

C0h

FFFD

X = Don’t Care

PA = Program Address BA = Block Address

IA = Identifier Address QA = Query Address

ID = Identifier Data QD = Query Data

SRD = Status Register Data PD = Program Data

NOTES:

1. When writing commands, the upper data bus [DQ –DQ ] should be either V or V , to minimize current

draw.

2. Following the Read Configuration or Read Query commands, read operations output device configuration or

CFI query information, respectively.

3. Either 40h or 10h command is valid, but the Intel standard is 40h.

4. When unlocking a block, WP# must be held for three clock cycles (1 clock cycle after the second command

bus cycle).

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 6. Flash Memory Status Register Definition

WSMS

ESS

VPPS

PSS

BLS

NOTES:

SR.7 WRITE STATE MACHINE STATUS

1 = Ready (WSMS)

Check Write State Machine bit first to determine Word Program or

Block Erase completion, before checking Program or Erase Status

bits.

0 = Busy

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

When Erase Suspend is issued, WSM halts execution and sets

both WSMS and ESS bits to “1.” ESS bit remains set to “1” until an

Erase Resume command is issued.

0 = Erase In Progress/Completed

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erase

When this bit is set to “1,” WSM has applied the max. number of

erase pulses and is still unable to verify successful block erasure.

0 = Successful Block Erase

SR.4 = PROGRAM STATUS (PS)

1 = Error in Programming

When this bit is set to “1,” WSM has attempted but failed to

program a word/byte.

0 = Successful Programming

SR.3 = F-V STATUS (VPPS)

The F-V status bit does not provide continuous indication of V

PP PP

1 = F-V Low Detect, Operation Abort

level. The WSM interrogates F-V level only after the Program or

0 = F-V OK

Erase command sequences have been entered, and informs the

system if F-V has not been switched on. The F-V is also

checked before the operation is verified by the WSM. The F-V

status bit is not guaranteed to report accurate feedback between

and V min.

PPLK

PP1

SR.2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended

When Program Suspend is issued, WSM halts execution and sets

both WSMS and PSS bits to “1.” PSS bit remains set to “1” until a

Program Resume command is issued.

0 = Program in Progress/Completed

SR.1 = BLOCK LOCK STATUS

If a program or erase operation is attempted to one of the locked

1 = Prog/Erase attempted on a locked block; Operation blocks, this bit is set by the WSM. The operation specified is

aborted.

aborted and the device is returned to read status mode.

0 = No operation to locked blocks

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserved for future use and should be masked out when

polling the status register.

NOTE: A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.

3.7

Instant, Individual Block Locking

The instant, individual block locking feature that allows any flash block to be locked or unlocked

with no latency, which enables instant code and data protection.

This locking offers two levels of protection. The first level allows software-only control of block

locking (useful for data blocks that change frequently), while the second level requires hardware

interaction before locking can be changed (useful for code blocks that change infrequently).

The following sections will discuss the operation of the locking system. The term “state [XYZ]”

will be used to specify locking states; e.g., “state [001],” where X = value of WP#, Y = bit DQ₁of

the Block Lock status register, and Z = bit DQ₀of the Block Lock status register. Table 8, “Block

Locking State Transitions” on page 15 defines all of these possible locking states.

3.7.1

Block Locking Operation Summary

The following concisely summarizes the locking functionality.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

All blocks are locked when powered-up, and can be unlocked or locked with the Unlock and Lock

commands.

• The Lock-Down command locks a block and prevents it from being unlocked when WP# = 0.

• When WP# = 1, Lock-Down is overridden and commands can unlock/lock locked-down

blocks.

• When WP# returns to 0, locked-down blocks return to Lock-Down.

• Lock-Down is cleared only when the device is reset or powered-down.

The locking status of each block can set to Locked, Unlocked, and Lock-Down, each of which will

be described in the following sections. A comprehensive state table for the locking functions is

shown in Table 8 on page 15, and a flowchart for locking operations is shown in Figure 19 on

page 44.

3.7.2

Locked State

The default status of all blocks upon power-up or reset is locked (states [001] or [101]). Locked

blocks are fully protected from alteration. Any program or erase operations attempted on a locked

block will return an error on bit SR.1 of the status register. The status of a locked block can be

changed to Unlocked or Lock-Down using the appropriate software commands. Unlocked blocks

can be locked issuing the “Lock” command sequence, 60h followed by 01h.

3.7.3

3.7.4

Unlocked State

Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks

return to the Locked state when the device is reset or powered down. The status of an unlocked

block can be changed to Locked or Locked-Down using the appropriate software commands. A

Locked block can be unlocked by writing the Unlock command sequence, 60h followed by D0h.

Lock-Down State

Blocks that are Locked-Down (state [011]) are protected from program and erase operations (just

like Locked blocks), but their protection status cannot be changed using software commands alone.

A Locked or Unlocked block can be Locked-down by writing the Lock-Down command sequence,

60h followed by 2Fh. Locked-Down blocks revert to the Locked state when the device is reset or

powered down.

The Lock-Down function is dependent on the WP# input ball. When WP# = 0, blocks in Lock-

Down [011] are protected from program, erase, and lock status changes. When WP# = 1, the Lock-

Down function is disabled ([111]) and locked-down blocks can be individually unlocked by

software command to the [110] state, where they can be erased and programmed. These blocks can

then be re-locked [111] and unlocked [110] as desired while WP# remains high. When WP# goes

low, blocks that were previously locked-down return to the Lock-Down state [011] regardless of

any changes made while WP# was high. Device reset or power-down resets all blocks, including

those in Lock-Down, to Locked state.

3.7.5

Reading a Block’s Lock Status

The lock status of every block can be read in the configuration read mode of the device. To enter

this mode, write 90h to the device. Subsequent reads at Block Address + 00002 will output the lock

status of that block. The lock status is represented by the least significant outputs, DQ₀and DQ₁.

DQ₀indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Unlock command. It is also automatically set when entering Lock-Down. DQ₁indicates Lock-

Down status and is set by the Lock-Down command. It cannot be cleared by software, only by

device reset or power-down.

Table 7. Block Lock Status

Item

Address

Data

Block Lock Configuration

• Block Is Unlocked

XX002

LOCK

DQ = 0

• Block Is Locked

DQ = 1

• Block Is Locked-Down

DQ = 1

3.7.6

Locking Operation during Erase Suspend

Changes to block lock status can be performed during an erase suspend by using the standard

locking command sequences to unlock, lock, or lock-down a block. This is useful in the case when

another block needs to be updated while an erase operation is in progress.

To change block locking during an erase operation, first write the erase suspend command (B0h),

then check the status register until it indicates that the erase operation has been suspended. Next

write the desired lock command sequence to a block and the lock status will be changed. After

completing any desired lock, read, or program operations, resume the erase operation with the

Erase Resume command (D0h).

If a block is locked or locked-down during a suspended erase of the same block, the locking status

bits will be changed immediately, but when the erase is resumed, the erase operation will complete.

Locking operations cannot be performed during a program suspend.

3.7.7

Status Register Error Checking

Using nested locking or program command sequences during erase suspend can introduce

ambiguity into status register results.

Since locking changes are performed using a two cycle command sequence, e.g., 60h followed by

01h to lock a block, following the Configuration Setup command (60h) with an invalid command

will produce a lock command error (SR.4 and SR.5 will be set to 1) in the status register. If a lock

command error occurs during an erase suspend, SR.4 and SR.5 will be set to 1, and will remain at 1

after the erase is resumed. When erase is complete, any possible error during the erase cannot be

detected via the status register because of the previous locking command error.

A similar situation happens if an error occurs during a program operation error nested within an

erase suspend.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 8. Block Locking State Transitions

Current State

Next State after Command Input

Erase/

Program

Allowed?

WP# DQ

Name

Lock

Unlock

Lock-Down

Unlocked

Yes

Go To [001]

–

Go To [011]

Go To [111]

Go To [011]

Go To [111]

–

Go To [101]

–

Locked (Default)

Locked

–

Go To [000]

Go To [100]

–

Locked-Down

–

Yes

Go To [111]

–

Go To [111]

–

Lock-Down

Disabled

Go To [110]

NOTES:

1. “–” indicates no change in the current state.

2. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ , and Z = DQ .

The current locking state of a block is defined by the state of WP# and the two bits of the block lock status

(DQ , DQ ). DQ indicates if a block is locked (1) or unlocked (0). DQ indicates if a block has been locked-

down (1) or not (0).

3. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). holding WP# = 0 is the

recommended default.

4. The “Erase/Program Allowed?” column shows whether erase and program operations are enabled (Yes) or

disabled (No) in that block’s current locking state.

5. The “Lock Command Input Result [Next State]” column shows the result of writing the three locking

commands (Lock, Unlock, Lock-Down) in the current locking state. For example, “Goes To [001]” would mean

that writing the command to a block in the current locking state would change it to [001].

6. The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is

programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is

left blank for customer designs to program as desired. Once the customer segment is programmed, it can be

locked to prevent reprogramming.

3.8

128-Bit Protection Register

The 3 Volt Advanced+ Stacked-CSP architecture includes a 128-bit protection register than can be

used to increase the security of a system design. For example, the number contained in the

protection register can be used to “mate” the flash component with other system components such

as the CPU or ASIC, preventing device substitution.

3.8.1

3.8.2

Reading the Protection Register

The protection register is read in the configuration read mode. The device is switched to this mode

by writing the Read Configuration command (90h). Once in this mode, read cycles from addresses

shown in Appendix E retrieve the specified information. To return to read array mode, write the

Read Array command (FFh).

Programming the Protection Register (C0h)

The protection register bits are programmed using the two-cycle Protection Program command.

The 64-bit number is programmed 16 bits at a time for word-wide parts. First write the Protection

Program Setup command, C0h. The next write to the device will latch in address and data and

program the specified location. The allowable addresses are shown in Appendix E. See Figure 20,

“Protection Register Programming Flowchart” on page 45.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Any attempt to address Protection Program commands outside the defined protection register

address space will result in a status register error (program error bit SR.4 will be set to 1).

Attempting to program or to a previously locked protection register segment will result in a status

3.8.3

Locking the Protection Register

The user-programmable segment of the protection register is lockable by programming Bit 1 of the

PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the

unique device number. This bit is set using the Protection Program command to program FFFDh to

the PR-LOCK location. After these bits have been programmed, no further changes can be made to

the values stored in the protection register. A Protection Program command to locked words will

result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1).

The protection register lockout state is not reversible.

Figure 3. Protection Register Memory Map

88H

4 Words

User Programmed

85H

84H

4 Words

Factory Programmed

81H

80H

PR-LOCK

0645_05

3.9

Additional Flash Features

Intel 3 Volt Advanced+ Stacked-CSP products provide in-system programming and erase in the

1.65 V–3.3 V range. For fast production programming, it also includes a low-cost, backward-

compatible 12 V programming feature.

3.9.1

Improved 12 Volt Production Programming

When F-V_PPis between 1.65 V and 3.3 V, all program and erase current is drawn through the

F-V_CCsignal. Note that if F-V_PPis driven by a logic signal, V_IHmin = 1.65 V. That is, F-V_PPmust

remain above 1.65 V to perform in-system flash modifications. When F-V_PPis connected to a 12 V

power supply, the device draws program and erase current directly from the F-V_PPsignal. This

eliminates the need for an external switching transistor to control the voltage F-V_PP. Figure 12,

“Example Power Supply Configurations” on page 35 shows examples of how the flash power

supplies can be configured for various usage models.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

The 12 V F-V_PPmode enhances programming performance during the short period of time

typically found in manufacturing processes; however, it is not intended for extended use. 12 V may

be applied to F-V_PPduring program and erase operations for a maximum of 1000 cycles on the

main blocks and 2500 cycles on the parameter blocks. F-V_PPmay be connected to 12 V for a total

of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage.

3.9.2

F-V ≤ V

for Complete Protection

PPLK

In addition to the flexible block locking, the F-V_PPprogramming voltage can be held low for

absolute hardware write protection of all blocks in the flash device. When F-V_PPis below V_PPLK

any program or erase operation will result in a error, prompting the corresponding status register bit

(SR.3) to be set.

4.0

Electrical Specifications

4.1

Absolute Maximum Ratings

Parameter

Extended Operating Temperature

Maximum Rating

During Read

During Flash Block Erase and Program

Temperature under Bias

–25°C to +85°C

Storage Temperature

–65°C to +125°C

/ S-V and F-V ) with Respect –0.5 V to +3.3 V⁽¹⁾

Voltage on Any Ball (except F-V /F-V

CCQ

to GND

F-V Voltage (for BLock Erase and Program) with Respect to GND

–0.5 V to +13.5 V^(1,2,4)

–0.2V to +3.3 V

100 mA⁽³⁾

F-V / F-V

/ S-V Supply Voltage with Respect to GND

CCQ

Output Short Circuit Current

NOTES:

1. Minimum DC voltage is –0.5 V on input/output balls. During transitions, this level may undershoot to –2.0 V

for periods < 20 ns. Maximum DC voltage on input/output balls is F-V / F-V

/ S-V + 0.5 V which,

CCQ

during transitions, may overshoot to

F-V / F-V

/ S-V + 2.0 V for periods < 20 ns.

CCQ

2. Maximum DC voltage on F-V may overshoot to +14.0 V for periods < 20 ns.

3. F-V voltage is normally 1.65 V–3.3 V. Connection to supply of 11.4 V–12.6 V can only be done for 1000

cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. F-V may be

connected to 12 V for a total of 80 hours maximum. See Section 3.9.1 for details

4. Output shorted for no more than one second. No more than one output shorted at a time.

NOTICE: This datasheet contains information on products in full production. The specifications are subject to

change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a

design.

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended

and extended exposure beyond the “Operating Conditions” may affect device reliability.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

4.2

Operating Conditions

Table 9. Temperature and Voltage Operating Conditions

Symbol

Parameter

Notes

Min

Max

Units

Operating Temperature

–25

+85

°C

F-V /F-V

Voltage

/S-V Supply

CCQ

/ V

2.7

3.3

Volts

CCQ

Supply Voltage

1, 2

1.65

11.4

3.3

Volts

PP1

12.6

PP2

Cycling

Block Erase Cycling

100,000

Cycles

NOTES:

1. F-V /F-V

must share the same supply. F-V /S-V must share the same supply when not in data

CC CC

CCQ

retention.

2. Applying F-V

11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on

PP =

the main blocks and 2500 cycles on the parameter blocks. F-V may be connected to 12 V for a total of 80

hours maximum. See Section 3.9.1 for details.

4.3

Capacitance

T_A= +25°C, f = 1 MHz

Sym

Parameter

Notes

Typ

Max

Units

Conditions

= 0 V

Input Capacitance

Output Capacitance

OUT

= 0 V

OUT

NOTE: 1. Sampled, not 100% tested.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

4.4

DC Characteristics

Table 10. DC Characteristics (Sheet 1 of 2)

2.7 V – 3.3 V

Symbol

Parameter

Device

Note

Unit

Test Conditions

Typ

Max

F-V /S-V = V Max

Flash/

SRAM

Input Load Current

± 2

µA

= V Max or GND

F-V /S-V = V Max

Flash/

SRAM

Output Leakage Current

0.2

± 10

= V Max or GND

F-V = V Max

F-CE# = F-RP# = V

Flash

µA

F-WP# = V or GND

= V Max or GND

V Standby Current

2-Mb

SRAM

CCS

µA

S-V = V Max

CC CC

S-CS # = V , S-CS = V

4-Mb/

8-Mb

SRAM

or S-CS = GND

= V Max or GND

F-V = V Max

Deep Power-Down Current

Flash

µA

= V Max or GND

IN CC

CCD

F-RP# = GND ± 0.2 V

= 0 mA, S-CS # = V

2-Mb

SRAM

Operating Power Supply Current

(cycle time = 1 µs)

S-CS = S-WE# = V

4-Mb

SRAM

= V or V

IL IH

8-Mb

SRAM

2-Mb

SRAM

Cycle time = Min, 100% duty,

I = 0 mA, S-CS # = V ,

S-CS = V

Operating Power Supply Current

(min cycle time)

CC2

4-Mb

SRAM

= V or V

IH, IN IL IH

8-Mb

SRAM

F-V = V Max

F-OE# = V , F-CE# = V

Read Current

Flash

1,2

1,3

CCR

f = 5 MHz, I

= 0 mA

OUT

= V or V

IL IH

F-V = V

PP1

Program in Progress

F-V = V (12 V)

Program Current

CCW

PP2

Program in Progress

F-V = V

PP1

Erase in Progress

F-V = V (12 V)

Erase Current

Flash

1,3

CCE

PP2

Erase in Progress

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 10. DC Characteristics (Sheet 2 of 2)

2.7 V – 3.3 V

Symbol

Parameter

Device

Note

Unit

Test Conditions

Typ

Max

F-CE# = V , Erase Suspend

in Progress

Erase Suspend Current

Flash

1,3,4

µA

CCES

F-CE# = V , Program

Program Suspend Current

CCWS

Suspend in Progress

F-RP# = GND ± 0.2 V

F-V Deep Power-Down Current

Flash

0.2

µA

PPD

PPS

F-V ≤ V

F-V Standby Current

0.2

µA

F-V ≤ V

±15

200

F-V ≤ V

PP CC

F-V Read Current

Flash

PPR

1,2

F-V ≥ V

PP CC

F-V =V

PP1

0.05

0.1

µA

Program in Progress

F-V = V (12 V)

F-V Program Current

Flash

1,2

PPW

PP2

Program in Progress

F-V = V

PP1

0.05

0.1

Program in Progress

F-V = V (12 V)

F-V Erase Current

Flash

PPE

PP2

Program in Progress

F-V = V

PP1

0.2

Erase Suspend in Progress

F-V = V (12 V)

F-V Erase Suspend Current

Flash

1,2

PPES

PP2

200

µA

Erase Suspend in Progress

F-V = V

PP1

0.2

µA

Program Suspend in Progress

F-V Program Suspend Current

PPWS

F-V = V (12 V)

PP2

200

Program Suspend in Progress

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal F-V /S-V , T = +25 °C.

2. Automatic Power Savings (APS) reduces I

inputs).

to approximately standby levels in static operation (CMOS

CCR

3. Sampled, not 100% tested.

4. I

and I

are specified with device de-selected. If device is read while in erase suspend, current draw

CCES

CCWS

is sum of I

and I

. If the device is read while in program suspend, current draw is the sum of I

CCR CCWS

CCES

and I

CCR

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 11. DC Characteristics, Continued

2.7 V – 3.3 V

Symbol

Parameter

Device

Note

Unit

Test Conditions

Min

Max

Flash/

SRAM

Input Low Voltage

–0.2

0.6

Flash/

SRAM

+0.2

Input High Voltage

Output Low Voltage

2.2

F-V /S-V = V Min

Flash/

SRAM

–0.10

0.10

= 100 µA

F-V /S-V = V Min

Flash/

SRAM

–

Output High Voltage

0.1

= –100 µA

F-V Lock-Out Voltage

Flash

1.0

3.3

Complete Write Protection

PPLK

PP1

PP2

LKO

F-V during Program / Erase

1.65

11.4

1.5

Operations

1,2

12.6

Prog/Erase Lock Voltage

Flash

1.5

Flash/

SRAM

Input Low Voltage

Input High Voltage

NOTES:

–0.2

2.2

0.6

Flash/

SRAM

+0.2

1. Erase and Program are inhibited when F-V < V

and not guaranteed outside the valid F-V ranges of

PPLK

and V

PP1

PP2

2. Applying F-V = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on

the main blocks and 2500 cycles on the parameter blocks. F-V may be connected to 12 V for a total of 80

hours maximum. See Section 3.9.1 for details.

Figure 4. Input/Output Reference Waveform

V_CC

0.0

V_CC

TEST POINTS

INPUT

OUTPUT

0645_07

NOTE: AC test inputs are driven at V

for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output

CCQ

timing ends, at V

/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are

CCQ

when V

= V

Min.

CCQ

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 5. Test Configuration

V_CCQ

R₁

R₂

Device

Under Test

Out

C_L

0666_05

NOTE: C includes jig capacitance.

Flash Test Configuration Component Values Table

Test Configuration

(pF)

R (Ω)

2.7 V–3.3 V Standard Test

25K

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

4.5

Flash AC Characteristics—Read Operations

Table 12. Flash AC Characteristics—Read Operations

Density

Product

16 Mbit

32 Mbit

-90

-110

-100

-110

Sym

Parameter

Unit

Voltage Range

Note

2.7 V – 3.3 V

Min Max

Min

Max

Min

Max

Min

Max

Read Cycle Time

150

110

100

110

AVAV

Address to Output Delay

F-CE# to Output Delay

F-OE# to Output Delay

F-RP# to Output Delay

F-CE# to Output in Low Z

F-OE# to Output in Low Z

F-CE# to Output in High Z

F-OE# to Output in High Z

110

100

110

AVQV

ELQV

GLQV

PHQV

ELQX

GLQX

EHQZ

GHQZ

150

Output Hold from Address, F-CE#,

or F-OE# Change, Whichever

Occurs First

R10

NOTES:

1. F-OE# may be delayed up to t

–t

after the falling edge of CE# without impact on t

ELQV GLQV ELQV

2. .Sampled, but not 100% tested.

See Figure 6, “AC Waveform: Flash Read Operations” on page 24.

See Figure 4, “Input/Output Reference Waveform” on page 21 for timing measurements and maximum

allowable input slew rate.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 6. AC Waveform: Flash Read Operations

Device and

Address Selection

Data

Valid

Standby

V_IH

ADDRESSES (A)

V_IL

Address Stable

V_IH

CE# (E)

V_IL

V_IH

OE# (G)

V_IL

V_IH

WE# (W)

Valid Output

R10

V_IL

V_OH

DATA (D/Q)

V_OL

High Z

V_IH

RP#(P)

V_IL

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

4.6

Flash AC Characteristics—Write Operations

Table 13. Flash AC Characteristics—Write Operations

Density

Product

16 Mbit

32 Mbit

-90

-110

-100

-110

Sym

Parameter

Unit

Voltage Range

Note

2.7 V – 3.3 V

Min

Max

Min

Max

PHWL

PHEL

F-RP# High Recovery to F-WE# (F-CE#) Going Low

F-CE# (F-WE#) Setup to F-WE# (F-CE#) Going Low

F-WE# (F-CE#) Pulse Width

150

ELWL

WLEL

ELEH

WLWH

DVWH

DVEH

Data Setup to F-WE# (F-CE#) Going High

Address Setup to F-WE# (F-CE#) Going High

F-CE# (F-WE#) Hold Time from F-WE# (F-CE#) High

Data Hold Time from F-WE# (F-CE#) High

Address Hold Time from F-WE# (F-CE#) High

F-WE# (F-CE#) Pulse Width High

AVWH

AVEH

WHEH

EHWH

WHDX

EHDX

WHAX

EHAX

WHWL

EHEL

VPWH

VPEH

W10

W11

F-V Setup to F-WE# (F-CE#) Going High

200

F-V Hold from Valid SRD

QVVL

NOTES:

1. Write pulse width (t ) is defined from F-CE# or F-WE# going low (whichever goes low last) to F-CE# or

F-WE# going high (whichever goes high first). Hence, t = t

= t

. Similarly, write

WLWH

ELEH

WLEH

ELWH

pulse width high (t

) is defined from F-CE# or F-WE# going high (whichever goes high first) to F-CE# or

WPH

F-WE# going low (whichever goes low first). Hence, t

= t

WPH

WHWL

EHEL

WHEL EHWL.

2. Refer to Table 5, “Flash Memory Command Definitions” on page 11 for valid A or D

3. Sampled, but not 100% tested.

See Figure 4, “Input/Output Reference Waveform” on page 21 for timing measurements and maximum

allowable input slew rate.

See Figure 7, “AC Waveform: Flash Program and Erase Operations” on page 27.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

4.7

Flash Erase and Program Timings⁽¹⁾

Table 14. Flash Erase and Program Timings

F-V

1.65 V– 3.3 V

11.4 V– 12.6 V

Symbol

Parameter

Unit

Note

Typ⁽¹⁾

Max

Typ⁽¹⁾

Max

4-KW Parameter Block Program Time (Word)

32-KW Main Block Program Time (Word)

Word Program Time

2, 3

0.10

0.8

0.5

0.30

2.4

200

0.03

0.24

0.12

BWPB

BWMB

/ t

185

µs

WHQV1 EHQV1

/ t

4-KW Parameter Block Erase Time (Word)

32-KW Main Block Erase Time (Word)

Program Suspend Latency

0.4

0.6

WHQV2 EHQV2

/ t

WHQV3 EHQV3

/ t

µs

WHRH1 EHRH1

/ t

Erase Suspend Latency

WHRH2 EHRH2

NOTES:

1. Typical values measured at T = +25 °C and nominal voltages.

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 7. AC Waveform: Flash Program and Erase Operations

V_IH

ADDRESSES [A]

CE#(WE#) [E(W)]

A_IN

V_IL

V_IH

(Note 1)

V_IL

V_IH

OE# [G]

V_IL

V_IH

(Note 1)

WE#(CE#) [W(E)]

V_IL

V_IH

V_IL

High Z

Valid

SRD

DATA [D/Q]

D_IN

V_IH

V_IL

V_IH

RP# [P]

WP#

V_IL

W10

W11

V_PPH

V_PPLK

V_IL

[V]

NOTES:

1. F-CE# must be toggled low when reading Status Register Data. F-WE# must be inactive (high) when reading

Status Register Data.

A. F-V Power-Up and Standby.

B. Write Program or Erase Setup Command.

C. Write Valid Address and Data (for Program) or Erase Confirm Command.

D. Automated Program or Erase Delay.

E. Read Status Register Data (SRD): reflects completed program/erase operation.

F. Write Read Array Command.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

4.8

Flash Reset Operations

Figure 8. AC Waveform: Reset Operation

RP# (P)

t_PHQV

t_PHWL

t_PHEL

V_IL

t_PLPH

(A) Reset during Read Mode

Abort

Complete

t _PLRH

t_PHQV

t_PHWL

t_PHEL

V_IH

V_IL

RP# (P)

t _PLPH

t_PLPH

t_PLRH

(B) Reset during Program or Block Erase,

Abort Deep

Complete Power-

t_PHQV

t_PHWL

t_PHEL

Down

t_PLRH

V_IH

V_IL

RP# (P)

t _PLPH

t_PLPHt_PLRH

Table 15. Reset Specifications⁽¹⁾

F-V 2.7 V – 3.3 V

Symbol

Parameter

Note

Unit

Min

Max

F-RP# Low to Reset during Read (If F-RP# is tied

2,4

100

PLPH

to V , this specification is not applicable)

F-RP# Low to Reset during Block Erase

3,4

µs

PLRH1

F-RP# Low to Reset during Program

3,4

PLRH2

NOTES:

1. See Section 2.1.4, “Flash Reset” on page 7 for a full description of these conditions.

2. If t is < 100 ns the device may still reset but this is not guaranteed.

PLPH

3. If F-RP# is asserted while a block erase or word program operation is not executing, the reset will complete

within 100 ns.

4. Sampled, but not 100% tested.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

4.9

SRAM AC Characteristics—Read Operations⁽¹⁾

Table 16. SRAM AC Characteristics—Read Operations⁽¹⁾

Density

Voltage Range

Note

2/4/8 Mbit

Sym

Parameter

2.7 V– 3.3 V

Unit

Min

Max

Read Cycle Time

–

Address to Output Delay

–

S-CS1#, S-CS2 to Output Delay

S-OE# to Output Delay

–

CO1, CO2

–

S-UB#, LB# to Output Delay

S-CS1#, S-CS2 to Output in Low Z

S-OE# to Output in Low Z

–

, t

2,3

LZ1 LZ2

–

OLZ

, t

S-CS1#, S-CS2 to Output in High Z

S-OE# to Output in High Z

2,3,4

3,4

HZ1 HZ2

OHZ

Output Hold from Address, S-CS1#,

R10

S-CS2, or S-OE# Change, Whichever Occurs

First

–

R11

R12

S-UB#, S-LB# to Output in Low Z

S-UB#, S-LB# to Output in High Z

–

BLZ

BHZ

NOTE:

1. See Figure 9, “AC Waveform: SRAM Read Operations” on page 30.

2. At any given temperature and voltage condition, t (Max) is less than and t (Max) both for a given device

and from device to device interconnection.

3. Sampled, but not 100% tested.

4. Timings of t and t

are defined as the time at which the outputs achieve the open circuit conditions and

OHZ

are not referenced to output voltage levels.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 9. AC Waveform: SRAM Read Operations

Device

Standby

Data Valid

Address Selection

V_IH

Address Stable

ADDRESSES (A)

V_IL

V_IH

CS₁# (E₁)

V_IL

V_IH

CS₂(E₂)

V_IL

V_IH

OE# (G)

V_IL

V_IH

WE# (W)

V_IL

V_OH

V_OL

R10

R11

High Z

DATA (D/Q)

UB#, LB#

Valid Output

R12

V_IH

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

4.10

SRAM AC Characteristics—Write Operations^{(1, 2)}

Table 17. SRAM AC Characteristics—Write Operations^(1,2)

Density

Volt

2/4/8 Mbit

Sym

Parameter

2.7 V – 3.3 V

Unit

Note

Min

Max

Write Cycle Time

–

Address Setup to S-WE# (S-CS #) and S-UB#,

S-LB# Going Low

S-WE# (S-CS #) Pulse Width

–

Data to Write Time Overlap

Address Setup to S-WE# (S-CS #) Going High

S-CE# (S-WE#) Setup to S-WE# (S-CS #) Going

High

Data Hold Time from S-WE# (S-CS #) High

–

Write Recovery

S-UB#, S-LB# Setup to S-WE# (S-CS #) Going High

NOTES:

1. See Figure 10, “AC Waveform: SRAM Write Operations” on page 32.

2. A write occurs during the overlap (t ) of low S-CS # and low S-WE#. A write begins when S-CS # goes low

and S-WE# goes low with asserting S-UB# or S-LB# for single byte operation or simultaneously asserting

S-UB# and S-LB# for double byte operation. A write ends at the earliest transition when S-CS # goes high

and S-WE# goes high. The t

is measured from the beginning of write to the end of write.

3. t is measured from the address valid to the beginning of write.

4. t

5. t

is measured from S-CS # going low to end of write.

is measured from the end of write to the address change. t

applied in case a write ends as S-CS # or

S-WE# going high.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 10. AC Waveform: SRAM Write Operations

Device

Standby

Address Selection

V_IH

Address Stable

ADDRESSES (A)

CS₁# (E₁)

V_IL

V_IH

V_IL

V_IH

CS₂(E₂)

V_IL

V_IH

V_IL

V_IH

V_IL

OE# (G)

WE# (W)

V_OH

V_OL

High Z

Data In

DATA (D/Q)

UB#, LB#

V_IH

SRAM Data Retention Characteristics⁽¹⁾Extended

Temperature

—

4.11

Table 18. SRAM Data Retention Characteristics⁽¹⁾—Extended Temperature

Sym

Parameter

Note

Min

Typ

Max

Unit

Test Conditions

CS # ≥V 0.2 V

S-V for Data Retention

1.5

–

3.3

CC –

S-V = 1.5 V

Deep Retention Current

–

µA

CS # ≥V

0.2 V

CC –

Data Retention Set-up Time

–

See Data Retention Waveform

SDR

Recovery Time

RDR

NOTES:

1. Typical values at nominal S-V , T = +25 °C.

2. S-CS # ≥V

0.2 V, S-CS ≥V

0.2 V (S-CS # controlled) or S-CS ≤ 0.2 V (S-CS controlled).

CC –

CC – 1 2 2

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 11. SRAM Data Retention Waveform

t_SDR

Data Retention Mode

t_RDR

CS1# Controlled

V_CC

3.0/2.7V

2.2V

CS₁# (E₁)

V_DR

GND

Data Retention Mode

t_SDR

CS2 Controlled

t_RDR

V_CC

3.0/2.7V

CS₂(E₂)

V_DR

0.4V

GND

5.0

Migration Guide Information

Typically, it is important to discuss footprint migration compatibility between a new product and

existing products. In this specific case, the Stacked CSP allows the system designer to remove two

separate memory footprints for individual flash and SRAM and replace them with a single

footprint, thus resulting in an overall reduction in board space required. This implies that a new

printed circuit board would be used to take advantage of this feature.

Since the flash in Stacked-CSP shares the same features as the Advanced+ Boot Block Features,

conversions from the Advanced Boot Block are described in AP-658 Designing for Upgrade to the

Advanced+ Boot Block Flash Memory, order number 292216.

Please contact your local Intel representation for detailed information about specific Flash +

SRAM system migrations.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

6.0

System Design Considerations

This section contains information that would have been contained in a product design guide in

earlier generations. In an effort to simplify the amount of documentation, relevant system design

considerations have been combined into this document.

6.1

Background

The Intel Advanced+ Boot Block Stacked chip scale package combines the features of the

Advanced+ Boot Block flash memory architecture with a low-power SRAM to achieve an overall

reduction in system board space. This enables applications to integrate security with simple

software and hardware configurations, while also combining the system SRAM and flash into one

common footprint. This section discusses how to take full advantage of the 3 Volt Advanced+ Boot

Block Stacked Chip Scale Package.

6.1.1

6.1.2

Flash + SRAM Footprint Integration

The Stacked Chip Scale Package memory solution can be used to replace a subset of the memory

subsystem within a design. Where a previous design may have used two separate footprints for

SRAM and Flash, you can now replace with the industry-standard I-ballout of the Stacked CSP

device. This allows for an overall reduction in board space, which allows the design to integrate

both the flash and the SRAM into one component.

Advanced+ Boot Block Flash Memory Features

Advanced+ Boot Block adds the following new features to Intel Advanced Boot Block

architecture:

• Instant, individual block locking provides software/hardware controlled, independent locking/

unlocking of any block with zero latency to protect code and data.

• A 128-bit Protection Register enables system security implementations.

• Improved 12 V production programming simplifies the system configuration required to

implement 12 V fast programming.

• Common Flash Interface (CFI) provides component information on the chip to allow software-

independent device upgrades.

For more information on specific advantages of the Advanced+ Boot Block Flash Memory, please

see AP-658 Designing with the Advanced+ Boot Block Flash Memory Architecture.

6.2

Flash Control Considerations

The flash device is protected against accidental block erasure or programming during power

transitions. Power supply sequencing is not required, since the device is indifferent as to which

power supply, F-V_PPor F-V_CC, powers-up first. Example flash power supply configurations are

shown in Figure 12, “Example Power Supply Configurations” on page 35.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

6.2.1

F-RP# Connected to System Reset

The use of F-RP# during system reset is important with automated program/erase devices since the

system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs

without a flash memory reset, proper CPU initialization will not occur because the flash memory

may be providing status information instead of array data. Intel recommends connecting F-RP# to

the system CPU RESET# signal to allow proper CPU/flash initialization following system reset.

System designers must guard against spurious writes when F-V_CCvoltages are above V_LKO. Since

both F-WE# and F-CE# must be low for a command write, driving either signal to V_IHwill inhibit

writes to the device. The CUI architecture provides additional protection since alteration of

memory contents can only occur after successful completion of the two-step command sequences.

The device is also disabled until F-RP# is brought to V_IH, regardless of the state of its control

inputs.

By holding the device in reset (F-RP# connected to system PowerGood) during power-up/down,

invalid bus conditions during power-up can be masked, providing yet another level of memory

protection.

6.2.2

F-V , F-V and F-RP# Transition

CC PP

The CUI latches commands as issued by system software and is not altered by F-V_PPor F-CE#

transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after

F-V_CCtransitions above V_LKO(Lockout voltage), is read array mode.

After any program or block erase operation is complete (even after F-V_PPtransitions down to

_PPLK), the CUI must be reset to read array mode via the Read Array command if access to the

flash memory array is desired.

Figure 12. Example Power Supply Configurations

System Supply

V_CC

V_PP

V_CC

12 V Supply

V_PP

Prot#

(Logic Signal)

≤ KΩ

12 V Fast Programming

Low-Voltage Programming

Absolute Write Protection With V _PP

≤

V_PPLK

Absolute Write Protection via Logic Signal

System Supply

(Note 1)

System Supply

V_CC

V_PP

12 V Supply

Low Voltage and 12 V Fast Programming

Low-Voltage Programming

NOTE: 1. A resistor can be used if the F-V supply can sink adequate current based on resistor value.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

6.3

Noise Reduction

Stacked-CSP memory’s power switching characteristics require careful device decoupling. System

designers should consider three supply current issues for both the flash and SRAM:

1. Standby current levels (I_CCS

2. Read current levels (I_CCR

)

3. Transient peaks produced by falling and rising edges of F-CE#, S-CS₁#, and S-CS₂.

Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-

line control and proper decoupling capacitor selection will suppress these transient voltage peaks.

Each device should have a capacitors between individual power (F-V_CC, F-V_CCQ,F-V_PP,S-

_CC)and ground (GND) signals. High-frequency, inherently low-inductance capacitors should be

placed as close as possible to the package leads.

Noise issues within a system can cause devices to operate erratically if it is not adequately filtered.

In order to avoid any noise interaction issues within a system, it is recommended that the design

contain the appropriate number of decoupling capacitors in the system. Noise issues can also be

reduced if leads to the device are kept very short, in order to reduce inductance.

Decoupling capacitors between V_CCand V_SSreduce voltage spikes by supplying the extra current

needed during switching. Placing these capacitors as close to the device as possible reduces line

inductance. The capacitors should be low inductance capacitors; surface mount capacitors typically

exhibit lower inductance.

It is highly recommended that systems use a 0.1 µf capacitor for each of the D9, D10, A10 and E4

grid ballout locations (see Figure 1, “68-Ball Stacked Chip Scale Package” on page 2 for ballout).

These capacitors are necessary to avoid undesired conditions created by excess noise. Smaller

capacitors can be used to decouple higher frequencies.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 13. Typical Flash + SRAM Substrate Power and Ground Connections

SUBSTRATE

FLASH DIE

SRAM DIE

S-V_SSQ

F-V_SSQ

S-V_CC

S-V_SS

S-V_CCQ

F-V_CC

D10

A10

F-V_CCQ

F-V_PP

F-V_SS

Substrate connection to package ball

S-X

F-X

SRAM die bond pad connection

Flash die bond pad connection

NOTES:

1. Substrate connections refer to ballout locations shown in Figure 1, “68-Ball Stacked Chip Scale Package” on

page 2.

2. 0.1µf capacitors should be used with D9, D10, A10and E4.

3. Some SRAM devices do not have a S-V

4. Some SRAM devices do not have a S-V

; in this case, this pad is a S-V

SSQ

; in this case, this pad is a V

6.4

Simultaneous Operation

The term simultaneous operation in used to describe the ability to read or write to the SRAM while

also programming or erasing flash. In addition, F-CE#, S-CS₁# and S-CS₂should not be enabled at

the same time. (See Table 2, “3 Volt Advanced+ Stacked-CSP Ball Descriptions” on page 3 for a

summary of recommended operating modes.) Simultaneous operation of the can be summarized by

the following:

• SRAM read/write are during a Flash Program or Erase Operation are allowed.

• Simultaneous Bus Operations between the Flash and SRAM are not allowed (because of bus

contention).

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

6.4.1

6.4.2

SRAM Operation during Flash “Busy”

This functionality provides the ability to use both the flash and the SRAM “at the same time”

within a system, similar to the operation of two devices with separate footprints. This operation can

be achieved by following the appropriate timing constraints within a system.

Simultaneous Bus Operations

Operations that require both the SRAM and Flash to be in active mode are disallowed. An example

of these cases would include simultaneous reads on both the flash and SRAM, which would result

in contention for the data bus. Finally, a read of one device while attempting to write to the other

(similar to the conditions of direct memory access (DMA) operation) are also not within the

recommended operating conditions. Basically, only one memory can drive the outputs out the

device at one given point in time.

6.5

Printed Circuit Board Notes

The Intel Stacked CSP will save significant space on your PCB by combining two chips into one

BGA style package. Intel Stacked CSP has a 0.8 mm pitch that can be routed on your Printed

Circuit Board with conventional design rules. Trace widths of 0.127 mm (0.005 inches) are typical.

Unused balls in the center of the package are not populated to further increase the routing options.

Standard surface mount process and equipment can be used for the Intel Stacked CSP.

Figure 14. Standard PCB Design Rules Can be Used with Stacked CSP Device

Land Pad Diameter: 0.35 mm (0.0138 in)

Solder Mask Opening: 0.50 mm (0.0198 in)

Trace Width: 0.127 mm (0.005 in)

Trace Spaces: 0.160 mm (0.00625 in)

Via Capture Pad: 0.51 mm (0.020 in)

Via Drill Size: 0.25 mm (0.010 in)

NOTE: Top View

6.6

System Design Notes Summary

The Advanced+ Boot Block Stacked CSP allows higher levels of memory component integration.

Different power supply configurations can be used within the system to achieve different

objectives. At least three different 0.1 µf capacitors should be used to decouple the devices within a

system. SRAM reads or writes during a flash program or erase are supported operations. Standard

printed circuit board technology can be used.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

7.0

Ordering Information

R D 2 8 F 1 6 0 2 C 3 T 9 0

Access Speed (ns)

16 Mbit = 90, 110

32 Mbit = 110

Package

RD = 8x12 Ball Matrix CSP

T = Top Blocking

B = Bottom Blocking

Product line designator

for all Intel^®Flash products

Product Family

C3 = 3 V Advanced+ Boot Block

V_CC= 2.7 V - 3.6 V

V_PP= 1.65 V - 3.6 V or

11.4 V - 12.6 V

Flash Device Density

320 = x16 (32 Mbit)

160 = x16 (16 Mbit)

SRAM Device Density

8 = x16 (8 Mbit)

4 = x16 (4 Mbit)

2 = x16 (2 Mbit)

8.0

Additional Information

Order Number

Document/Tool

292216

292215

AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory

AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture

Contact Your Intel

Representative

Flash Data Integrator (FDI) Software Developer’s Kit

297874

FDI Interactive: Play with Intel’s Flash Data Integrator on Your PC

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical

documentation and tools.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Appendix A Program/Erase Flowcharts

Figure 15. Automated Word Programming Flowchart

Start

Bus Operation

Command

Program Setup

Program

Comments

Write

Data = 40H

Write 40H

Data = Data to Program

Addr = Location to Program

Write

Program Address/Data

Status Register Data Toggle

CE# or OE# to Update Status

Read

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read Status Register

Standby

Repeat for subsequent programming operations.

SR.7 = 1?

Yes

SR Full Status Check can be done after each program or after a sequence of

program operations.

Write FFH after the last program operation to reset device to read array mode.

Full Status

Check if Desired

Program Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus Operation

Standby

Command

Comments

Check SR.3

1 = V_PPLow Detect

SR.3 =

V_PPRange Error

Check SR.4

1 = V_PPProgram Error

Standby

SR.4 =

Check SR.1

1 = Attempted Program to

Locked Block - Program

Aborted

Standby

Programming Error

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

Attempted Program to

Locked Block - Aborted

SR.1 =

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases where multiple bytes are programmed before full status is checked.

If an error is detected, clear the status register before attempting retry or other

error recovery.

Program Successful

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 16. Program Suspend/Resume Flowchart

Bus

Operation

Command

Comments

Data = B0H

Start

Program

Suspend

Write

Addr = X

Write B0H

Data = 70H

Addr = X

Write

Read

Read Status

Status Register Data Toggle

CE# or OE# to Update Status

Write 70H

Addr = X

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Read Status Register

Check SR.2

Standby

Write

1 = Program Suspended

0 = Program Completed

SR.7 =

Data = FFH

Addr = X

Read Array

Read array data from block

other than the one being

programmed.

SR.2 =

Program Completed

Read

Program

Resume

Data = D0H

Addr = X

Write

Write FFH

Read Array Data

Done

Reading

Yes

Write D0H

Write FFH

Program Resumed

Read Array Data

0645_13

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 17. Automated Block Erase Flowchart

Start

Bus Operation

Command

Comments

Data = 20H

Write

Erase Setup

Addr = Within Block to Be

Erased

Write 20H

Data = D0H

Write

Read

Erase Confirm

Addr = Within Block to Be

Erased

Write D0H and

Block Address

Status Register Data Toggle

CE# or OE# to Update Status

Read Status Register

Suspend

Check SR.7

1 = WSM Ready

0 = WSM Busy

Erase Loop

Standby

Yes

SR.7 =

Suspend Erase

Repeat for subsequent block erasures.

Full Status Check can be done after each block erase or after a sequence of

block erasures.

Full Status

Check if Desired

Write FFH after the last write operation to reset device to read array mode.

Block Erase Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

Bus Operation

Command

Comments

Check SR.3

Standby

1 = V_PPLow Detect

SR.3 =

V_PPRange Error

Check SR.4,5

Standby

Both 1 = Command Sequence

Error

SR.4,5 =

Check SR.5

1 = Block Erase Error

Command Sequence

Error

Check SR.1

1 = Attempted Erase of

Locked Block - Erase Aborted

SR.5 =

Block Erase Error

SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases

where multiple bytes are erased before full status is checked.

Attempted Erase of

Locked Block - Aborted

SR.1 =

If an error is detected, clear the status register before attempting retry or other

error recovery.

Block Erase

Successful

0645_14

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 18. Erase Suspend/Resume Flowchart

Bus

Operation

Command

Erase Suspend

Read Status

Comments

Data = B0H

Start

Write

Addr = X

Write B0H

Data = 70H

Addr = X

Write

Read

Status Register Data Toggle

CE# or OE# to Update Status

Write 70H

Addr = X

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Read Status Register

Check SR.6

Standby

Write

1 = Erase Suspended

0 = Erase Completed

SR.7 =

Data = FFH

Addr = X

Read Array

Read array data from block

other than the one being

erased.

SR.6 =

Erase Completed

Read

Data = D0H

Addr = X

Write

Erase Resume

Write FFH

Read Array Data

Done

Reading

Yes

Write D0H

Write FFH

Erase Resumed

Read Array Data

0645_15

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 19. Locking Operations Flowchart

Bus

Operation

Command

Comments

Data = 60H

Start

Write

Config. Setup

Addr = X

Write 60H

(Configuration Setup)

Data= 01H (Lock Block)

D0H (Unlock Block)

2FH (Lockdown Block)

Addr=Within block to lock

Lock, Unlock,

or Lockdown

Write

01H, D0H, or 2FH

Write

Read

Data = 90H

(Optional)

Configuration Addr = X

Read

(Optional)

Block Lock

Status

Block Lock Status Data

Addr = Second addr of block

Write 90H

(Read Configuration)

Confirm Locking Change on

DQ₁, DQ₀. (See Block Locking

State Table for valid

Standby

(Optional)

combinations.)

Read Block Lock Status

Locking

Change

Confirmed?

Write FFh

(Read Array)

Locking Change

Complete

0645_16

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Figure 20. Protection Register Programming Flowchart

Start

Bus Operation

Write

Command

Comments

Protection Program

Setup

Data = C0H

Write C0H

(Protection Reg.

Program Setup)

Data = Data to Program

Addr = Location to Program

Write

Protection Program

Status Register Data Toggle

CE# or OE# to Update Status

Write Protect. Register

Address/Data

Read

Check SR.7

Standby

1 = WSM Ready

0 = WSM Busy

Read Status Register

Protection Program operations can only be addressed within the protection

error.

SR.7 = 1?

Yes

Repeat for subsequent programming operations.

SR Full Status Check can be done after each program or after a sequence of

program operations.

Full Status

Check if Desired

Write FFH after the last program operation to reset device to read array mode.

Program Complete

FULL STATUS CHECK PROCEDURE

Bus Operation

Standby

Command

Comments

SR.1 SR.3 SR.4

Read Status Register

Data (See Above)

V_PPLow

1, 1

Prot. Reg.

Prog. Error

Standby

SR.3, SR.4 =

SR.1, SR.4 =

V_PPRange Error

Locked:

Aborted

0,1

1,1

Standby

Protection Register

Programming Error

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

Attempted Program to

Locked Register -

Aborted

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases of multiple protection register program operations before full status is

checked.

SR.1, SR.4 =

If an error is detected, clear the status register before attempting retry or other

error recovery.

Program Successful

0645_17

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Appendix B CFI Query Structure

This appendix defines the data structure or “database” returned by the Common Flash Interface

(CFI) Query command. System software should parse this structure to gain critical information

such as block size, density, x8/x16, and electrical specifications. Once this information has been

obtained, the software will know which command sets to use to enable flash writes, block erases,

and otherwise control the flash component. The Query is part of an overall specification for

multiple command set and control interface descriptions called Common Flash Interface, or CFI.

B.1

Query Structure Output

The Query “database” allows system software to gain information for controlling the flash

component. This section describes the device’s CFI-compliant interface that allows the host system

to access Query data.

Query data are always presented on the lowest-order data outputs (DQ_0-7) only. The numerical

offset value is the address relative to the maximum bus width supported by the device. On this

family of devices, the Query table device starting address is a 10h, which is a word address for x16

devices.

For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in ASCII,

appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data

on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (DQ_0-7) and 00h in the high

byte (DQ_8-15).

At Query addresses containing two or more bytes of information, the least significant data byte is

presented at the lower address, and the most significant data byte is presented at the higher address.

In all of the following tables, addresses and data are represented in hexadecimal notation, so the

“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always

“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is

shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.

Table 19. Summary of Query Structure Output as a Function of Device and Mode

Device

Hex Offset

Code

ASCII Value

10:

11:

12:

“Q”

“R”

“Y”

Device Address

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 20. Example of Query Structure Output of x16 and x8 Devices

Word Addressing

Hex Code

Byte Addressing

Hex Code

Offset

–A

Value

Offset

Value

–D

A –A

D –D

7 0

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

...

0051

0052

“Q”

“R”

10h

11h

12h

13h

14h

15h

16h

17h

18h

...

“Q”

“R”

0059

“Y”

P_IDLO

P_IDHI

PLO

PrVendor

ID #

P_IDLO

P_IDHI

...

PrVendor

ID #

PrVendor

TblAdr

AltVendor

ID #

PHI

...

A_IDLO

A_IDHI

...

B.2

Query Structure Overview

The Query command causes the flash component to display the Common Flash Interface (CFI)

Query structure or “database.” The structure sub-sections and address locations are summarized

below.

Table 21. Query Structure⁽¹⁾

Offset

Sub-Section Name

Description

00h

Manufacturer Code

Device Code

01h

(BA+2)h⁽²⁾

04-0Fh

10h

Block Status Register

Block-specific information

Reserved

Reserved for vendor-specific information

Command set ID and vendor data offset

Device timing & voltage information

Flash device layout

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Primary Intel-Specific Extended

Query Table

Vendor-defined additional information specific to the

Primary Vendor Algorithm

P⁽³⁾

NOTES:

1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.

2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the

block size is 32 Kword).

3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

B.3

Block Lock Status Register

The Block Status Register indicates whether an erase operation completed successfully or whether

a given block is locked or can be accessed for flash program/erase operations.

Block Erase Status (BSR.1) allows system software to determine the success of the last block erase

operation. BSR.1 can be used just after power-up to verify that the V_CCsupply was not

accidentally removed during an erase operation. This bit is only reset by issuing another erase

operation to the block. The Block Status Register is accessed from word address 02h within each

block.

Table 22. Block Status Register

Offset

(BA+2)h⁽¹⁾

Length

Description

Address

Value

Block Lock Status Register

BA+2:

--00 or --01

BSR.0 Block Lock Status

0 = Unlocked

BA+2:

(bit 0): 0 or 1

1 = Locked

BSR.1 Block Lock-Down Status

0 = Not locked down

BA+2:

(bit 1): 0 or 1

1 = Locked down

BSR 2–7: Reserved for future use

BA+2:

(bit 2–7): 0

NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in

word mode.)

B.4

CFI Query Identification String

The Identification String provides verification that the component supports the Common Flash

Interface specification. It also indicates the specification version and supported vendor-specified

command set(s).

Table 23. CFI Identification

Hex

Code

Offset

Length

Description

Query-unique ASCII string “QRY“

Addr.

Value

10h

11:

12:

13:

14:

15:

16:

17:

18:

19:

1A:

--51

--52

--59

--03

--00

--35

--00

“Q”

“R”

“Y”

13h

15h

17h

19h

Primary vendor command set and control interface ID code.

16-bit ID code for vendor-specified algorithms

Extended Query Table primary algorithm address

Alternate vendor command set and control interface ID code

0000h means no second vendor-specified algorithm exists

Secondary algorithm Extended Query Table address.

0000h means none exists

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

B.5

System Interface Information

Table 24. System Interface Information

Hex

Code

Offset

Length

Description

Addr.

Value

logic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

1Bh

1B:

--27

--36

--B4

2.7 V

logic supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

1Ch

1Dh

1C:

1D:

3.6 V

[programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

11.4 V

[programming] supply maximum program/erase voltage

1Eh

1Fh

1Bh

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

1E:

1F:

1B:

--C6

--05

--27

12.6 V

32 µs

2.7 V

“n” such that typical single word program time-out = 2ⁿµs

logic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

logic supply maximum program/erase voltage

1Ch

1Dh

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

1C:

1D:

--36

--B4

3.6 V

[programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

11.4 V

[programming] supply maximum program/erase voltage

1Eh

1Fh

1Bh

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

1E:

1F:

1B:

--C6

--05

--27

12.6 V

32 µs

2.7 V

“n” such that typical single word program time-out = 2ⁿµs

logic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

logic supply maximum program/erase voltage

1Ch

1Dh

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

1C:

1D:

--36

--B4

3.6 V

[programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

11.4 V

20h

21h

22h

23h

24h

25h

26h

“n” such that typical max. buffer write time-out = 2ⁿµs

“n” such that typical block erase time-out = 2ⁿms

20:

21:

22:

23:

24:

25:

26:

--00

--0A

--00

--04

--00

--03

--00

n/a

1 s

“n” such that typical full chip erase time-out = 2ⁿms

n/a

“n” such that maximum word program time-out = 2ⁿtimes typical

“n” such that maximum buffer write time-out = 2ⁿtimes typical

“n” such that maximum block erase time-out = 2ⁿtimes typical

“n” such that maximum chip erase time-out = 2ⁿtimes typical

512 µs

n/a

8 s

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

B.6

Device Geometry Definition

Table 25. Device Geometry Definition

Code

See Table Below

Offset

Length

Description

27h

“n” such that device size = 2ⁿin number of bytes

Flash device interface: x8 async x16 async x8/x16 async

28:00,29:00 28:01,29:00 28:02,29:00

27:

28:

29:

2A:

2B:

28h

--01

--00

x16

2Ah

“n” such that maximum number of bytes in write buffer = 2ⁿ

Number of erase block regions within device:

1. x = 0 means no erase blocking; the device erases in “bulk”

2. x specifies the number of device or partition regions with one or

more contiguous same-size erase blocks.

2Ch

2Dh

2C:

--02

3. Symmetrically blocked partitions have one blocking region

4. Partition size = (total blocks) x (individual block size)

Erase Block Region 1 Information

2D:

2E:

2F:

30:

31:

32:

33:

34:

bits 0–15 = y, y+1 = number of identical-size erase blocks

bits 16–31 = z, region erase block(s) size are z x 256 bytes

31h

Erase Block Region 2 Information

bits 0–15 = y, y+1 = number of identical-size erase blocks

bits 16–31 = z, region erase block(s) size are z x 256 bytes

Device Geometry Definition

16 Mbit

32 Mbit

Address

–B

–T

–B

–T

27:

28:

29:

2A:

2B:

2C:

2D:

2E:

2F:

30:

31:

32:

33:

34:

--15

--01

--00

--02

--07

--00

--20

--00

--1E

--00

--01

--15

--01

--00

--02

--1E

--00

--01

--07

--00

--20

--00

--16

--01

--00

--02

--07

--00

--20

--00

--3E

--00

--01

--16

--01

--00

--02

--3E

--00

--01

--07

--00

--20

--00

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

B.7

Intel-Specific Extended Query Table

Certain flash features and commands are optional. The Intel-Specific Extended Query table

specifies this and other similar types of information.

Table 26. Primary-Vendor Specific Extended Query

Offset⁽¹⁾

P = 35h

Description

(Optional Flash Features and Commands)

Hex

Code

Length

Addr.

Value

(P+0)h

(P+1)h

(P+2)h

(P+3)h

(P+4)h

(P+5)h

(P+6)h

(P+7)h

(P+8)h

Primary extended query table

35:

36:

37:

38:

39:

3A:

3B:

3C:

3D:

--50

--52

--49

--31

--30

--66

--00

“P”

“R”

“I”

Unique ASCII string “PRI”

Major version number, ASCII

“1”

“0”

Minor version number, ASCII

Optional feature and command support (1=yes, 0=no)

bits 9–31 are reserved; undefined bits are “0.” If bit 31 is “1” then

another 31 bit field of optional features follows at the end of the bit-30

field.

bit 0 Chip erase supported

bit 0 = 0

Yes

bit 1 Suspend erase supported

bit 2 Suspend program supported

bit 3 Legacy lock/unlock supported

bit 4 Queued erase supported

bit 1 = 1

bit 2 = 1

bit 3 = 0

bit 4 = 0

bit 5 = 1

bit 6 = 1

bit 7 = 0

bit 8 = 0

bit 5 Instant individual block locking supported

bit 6 Protection bits supported

Yes

bit 7 Page mode read supported

bit 8 Synchronous read supported

Supported functions after suspend: read array, status, query

Other supported operations are:

(P+9)h

3E:

--01

bits 1–7 reserved; undefined bits are “0”

bit 0 Program supported after erase suspend

Block status register mask

bit 0 = 1

Yes

(P+A)h

(P+B)h

3F:

40:

--03

bits 2–15 are Reserved; undefined bits are “0”

bit 0 Block Lock-Bit Status register active

bit 1 Block Lock-Down Bit Status active

--00

bit 0 = 1

bit 1 = 1

Yes

logic supply highest performance program/erase voltage

(P+C)h

(P+D)h

bits 0–3 BCD value in 100 mV

bits 4–7 BCD value in volts

41:

--33

3.3 V

optimum program/erase supply voltage

bits 0–3 BCD value in 100 mV

bits 4–7 HEX value in volts

42:

--C0

12.0 V

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 27. Protection Register Information

Offset⁽¹⁾

P = 35h

Description

(Optional Flash Features and Commands)

Hex

Code

Length

Addr.

Value

Number of Protection register fields in JEDEC ID space.

“00h,” indicates that 256 protection bytes are available

(P+E)h

43:

44:

--01

--80

(P+F)h

Protection Field 1: Protection Description

80h

This field describes user-available One Time Programmable (OTP)

Protection register bytes. Some are pre-programmed with device-

unique serial numbers. Others are user programmable. Bits 0–15 point

to the Protection register Lock byte, the section’s first byte. The

following bytes are factory pre-programmed and user-programmable.

(P+10)h

45:

--00

00h

bits 0–7 = Lock/bytes JEDEC-plane physical low address

bits 8–15 = Lock/bytes JEDEC -plane physical high address

bits 16–23 = “n” such that 2ⁿ= factory pre- programmed bytes

bits 24–31 = “n” such that 2ⁿ= user programmable bytes

(P+11)h

46:

--03

8 byte

(P+12)h

(P+13)h

47:

48:

Reserved for future use

NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Appendix C Word-Wide Memory Map Diagrams

Table 28. 16-Mbit, and 32-Mbit Word-Wide Memory Flash Addressing (Sheet 1 of 2)

Top Boot

16 Mbit

Bottom Boot

16 Mbit

Size

(KW)

Size

(KW)

32 Mbit

FF000-FFFFF

FE000-FEFFF

FD000-FDFFF

FC000-FCFFF

FB000-FBFFF

FA000-FAFFF

F9000-F9FFF

F8000-F8FFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

00000-07FFF

1FF000-1FFFFF

1FE000-1FEFFF

1FD000-1FDFFF

1FC000-1FCFFF

1FB000-1FBFFF

1FA000-1FAFFF

1F9000-1F9FFF

1F8000-1F8FFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

F8000-FFFFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 28. 16-Mbit, and 32-Mbit Word-Wide Memory Flash Addressing (Sheet 2 of 2)

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

000000-007FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

07000-07FFF

06000-06FFF

05000-05FFF

04000-04FFF

03000-03FFF

02000-02FFF

01000-01FFF

00000-00FFF

088000-08FFFF

080000-087FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

07000-07FFF

06000-06FFF

05000-05FFF

04000-04FFF

03000-03FFF

02000-02FFF

01000-01FFF

00000-00FFF

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Appendix D Device ID Table

Table 29. Device ID

Read Configuration Address and Data

Item

Manufacturer Code

Address

Data

x16

00000

0089

Device Code

16 Mbit x 16-T

16 Mbit x 16-B

32 Mbit x 16-T

32 Mbit x 16-B

x16

00001

88C2

88C3

88C4

88C5

NOTE: Other locations within the configuration address space are reserved by Intel for future use.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Appendix E Protection Register Addressing

Table 30. Protection Register Addressing

Word-Wide Protection Register Addressing

Word

Use

LOCK

Both

Factory

User

NOTE: All address lines not specified in the above table must be 0 when accessing the Protection

21–

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Appendix F Mechanical and Shipping Media Details

F.1

Mechanical Specification

Figure 21. 68-Ball Stacked-CSP: 12 x 8 Matrix

A1 INDEX

MARK

S₂

S₁

10 11 12

Top View: Ball Down

Bottom View: Ball up

A₂

A₁

NOTE: 68- ball package consists of 8 x 12 solder ball matrix, 8 rows and 12 columns. Each row is identified by

a letter and the column by a number. Each ball location, thus, is designated by row & column

combination.

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

Table 31. Packaging Specifications

Millimeters

Nom

Inches

Nom

Sym

Min

Max

Min

Max

Package Height

1.20

0.30

0.92

0.325

9.90

7.90

1.30

0.35

0.97

0.40

10.00

8.00

1. 40

0.40

0.047

0.012

0.036

0.013

0.429

0.311

0.051

0.014

0.038

0.016

0.433

0.315

0.055

0.016

0.040

0.019

0.437

0.319

Standoff

Package Body Thickness

Ball Lead Diameter

1.02

0.475

10.10

8.10

Package Body Length – 16 Mbit/2 Mbit

Package Body Width – 16Mbit/2Mbit

Package Body Length –

11.90

13.90

7.90

12.00

14.00

12.10

14.10

8.10

0.469

0.547

0.311

0.472

0.551

0.476

0.555

0.319

32 Mbit/4 Mbit, 16 Mbit/4 Mbit

Package Body Length –

32 Mbit/8 Mbit

Package Body Width –

8.00

0.80

0.315

0.031

32 Mbit/4 Mbit, 32 Mbit/8 Mbit, 16 Mbit/4 Mbit

Pitch

Seating Plane Coplanarity

0.1

0.004

Corner to First Bump Distance – 16-Mbit/2-Mbit

1.10

0.50

1.20

0.60

1.30

0.0433

0.0197

0.0472

0.0236

0.0512

Corner to First Bump Distance – 16-Mbit/2-Mbit

0.70

0.0276

Corner to First Bump Distance –

32-Mbit/4-Mbit, 16-Mbit/4-Mbit

1.10

2.50

1.50

1.10

1.20

2.60

1.60

1.20

1.30

2.70

1.70

1.30

0.0433

0.098

0.0472

0.102

0.0512

0.106

Corner to First Bump Distance –

32-Mbit/8-Mbit

Corner to First Bump Distance –

32-Mbit/4-Mbit, 16-Mbit/4-Mbit

0.0591

0.0433

0.0630

0.0472

0.0669

0.0512

Corner to First Bump Distance –

32-Mbit/8-Mbit

Preliminary

28F1602C3, 28F1604C3, 28F3204C3, 28F3208C3

F.2

Media Information

Figure 22. Stacked CSP Device in Tray Orientation (8 mm x 10 mm and 8 mm x 12 mm

Device Pin 1

Tray Chamfer

NOTE: Drawing is not to scale and is only designed to show orientation of devices.

Figure 23. Stacked CSP Device in 24 mm Tape (8 mm x 10 mm and 8 mm x 12 mm)

Device Pin 1

Preliminary

RD28F1608VPPT110 [INTEL]

相关型号：

RD28F3202C3B100

RD28F3202C3B110

RD28F3202C3T100

RD28F3202C3T110

RD28F3202VCCB110

RD28F3202VCCT100

RD28F3202VCCT110

RD28F3202VPPT100

RD28F3204C3B70

RD28F3204C3T70

RD28F3204VPPB110

RD28F3204W30B70