RD38F4420LVYTQ0 [INTEL]
Memory Circuit, 16MX16, CMOS, PBGA88, 8 X 11 MM, 1.40 MM HEIGHT, QUAD, SCSP-88;
| 型号： | RD38F4420LVYTQ0 |
| 厂家： | 
INTEL |
| 描述： | Memory Circuit, 16MX16, CMOS, PBGA88, 8 X 11 MM, 1.40 MM HEIGHT, QUAD, SCSP-88 静态存储器 内存集成电路 |
| 文件： | 总50页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
£
Intel StrataFlash Wireless Memory
System (LV18/LV30 SCSP)
768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
Product Features
■ Device Architecture
■ Code Segment Flash
—Flash density: 64-, 128-, 256-Mbit
—PSRAM density: 32-, 64-, 128-Mbit
—SRAM density: 8-Mbit
—85 ns initial access at 1.8 V I/O
—25 ns async page read at 1.8 V I/O
—14 ns sync read (tCHQV) at 1.8 V I/O
—54 MHz CLK at 1.8 V I/O
■ Device Voltage
—VCC = 1.8 V, VCCQ = 1.8 V/3.0 V (Typ)
■ Device Packaging
—Hardware Read-While-Write/Erase
—Mult. 8-Mbit or 16-Mbit Partition Sizes
—88 balls (8 x 10 active ball matrix)
—Area: 8 x 10 mm or 8 x 11 mm
—Height: 1.0 mm to 1.4 mm
■ PSRAM Performance
—2-Kbit One-Time Programmable (OTP)
Protection Register
■ Data Segment Flash
—170 ns initial access at 1.8 V I/O
—55 ns async page read at 1.8 V I/O
—Software Read-While-Write/Erase
■ Common Flash Architecture
—Buffered EFP: 5 µs/Byte (Typ) per die
—Buffer Program: 7 µs/Byte (Typ) per die
—85 ns initial access, 30 ns async page
reads at 1.8 V I/O
—65 ns initial access, 18 ns async page
reads at 3.0 V I/O
■ SRAM Performance
—70 ns initial access at 1.8 or 3.0 V I/O
■ Quality and Reliability
—16-KWord parameter blocks (Top or
Bottom); 64-KWord main blocks
—Extended Temp: –25 °C to +85 °C
—Minimum 100-K flash block erase cycle
—0.13 µm ETOX¥ VIII flash technology
—Zero-latency block locking
—Absolute write protection with block
lock down using F-WP#
■ Flash Software
£
£
£
—Intel FDI, Intel PSM, and Intel VFM
—Common Flash Interface (CFI)
The Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP); 768-Mbit LVQ Family
with Asynchronous Static RAM device offers a high performance code and large embedded data
segment plus RAM combination in a common package with electrical QUAD+ ballout on 0.13
µm ETOX™ VIII flash technology. The code segment flash die features 1.8 V low-power
operations with flexible, multi-partition, dual operation Read-While-Write / Read-While-Erase,
asynchronous and synchronous burst reads at 54 MHz. The data segment flash die features 1.8 V
low-power operations optimized for cost sensitive asynchronous data applications. This device
integrates up to three flash dies, two PSRAM dies, and one SRAM die in a low-profile package
compatible with other SCSP families using the QUAD+ ballout package.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
253852-003
May 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
This datasheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation, 2004
2
Datasheet
Contents
Contents
1.0 Introduction....................................................................................................................................7
1.1
1.2
1.3
Nomenclature .......................................................................................................................7
Acronyms..............................................................................................................................8
Conventions..........................................................................................................................9
2.0 Functional Overview ...................................................................................................................10
2.1
2.2
2.3
2.4
Product Description ............................................................................................................10
Product Segment Unique Features ....................................................................................12
Product Configurations and Memory Partitioning ...............................................................12
Memory Map.......................................................................................................................15
3.0 Package Information ...................................................................................................................20
4.0 Ballout and Signal Descriptions ................................................................................................21
4.1
Signal Descriptions .............................................................................................................22
5.0 Maximum Ratings and Operating Conditions...........................................................................25
5.1
5.2
Absolute Maximum Ratings ................................................................................................25
Operating Conditions ..........................................................................................................26
6.0 Electrical Specifications .............................................................................................................27
6.1 DC Current Characteristics.................................................................................................27
7.0 AC Characteristics ......................................................................................................................29
7.1
7.2
7.3
7.4
7.5
Flash AC Characteristics ....................................................................................................29
SRAM AC Read Specifications...........................................................................................30
SRAM AC Write Specifications...........................................................................................31
PSRAM AC Read Specifications ........................................................................................34
PSRAM AC Write Specifications ........................................................................................36
8.0 Power and Reset Specifications ................................................................................................38
9.0 Design Guide: Operation Overview ...........................................................................................38
9.1
9.2
Bus Operations ...................................................................................................................38
Flash Device Commands and Command Definitions .........................................................40
10.0 Flash Read Operation .................................................................................................................40
11.0 Flash Program Operation ...........................................................................................................40
12.0 Flash Erase Operation ................................................................................................................41
13.0 Flash Suspend and Resume Operations...................................................................................41
14.0 Flash Block Locking and Unlocking Operations......................................................................41
15.0 Flash Protection Register Operation .........................................................................................41
16.0 Flash Configuration Operation...................................................................................................41
17.0 Dual Operation Considerations..................................................................................................41
Datasheet
3
Contents
18.0 PSRAM Operations...................................................................................................................... 42
18.1 PSRAM Power-up Sequence and Initialization................................................................... 42
18.2 PSRAM Mode Register....................................................................................................... 42
18.2.1 PSRAM Mode Register Setting .............................................................................43
18.2.2 Cautions for Setting PSRAM Mode Register ......................................................... 44
18.3 PSRAM Low-Power Mode..................................................................................................45
Appendix A Write State Machine ........................................................................................................ 46
Appendix B Common Flash Interface................................................................................................. 46
Appendix C Flash Flowcharts .............................................................................................................46
Appendix D Additional Information .................................................................................................... 47
Appendix E Ordering Information....................................................................................................... 48
4
Datasheet
Contents
Revision History
Date
Revision
Description
10/03r
-001
-002
Initial Release
In the Valid Combination Table: Deleted the TBD 5-die stack
option. Revised the Matrix table.
12/03
Removed UT-SCSP package references. Revised line items in
Table 1 and Table 22. Updated Section 3, Mechanical
Specifications and added the 11x13x1.4 mm SCSP package.
Corrected information in the Memory Map table, code and data
segments, bottom parameter. Also updated the top and bottom
parameter configurations figures and moved the Memory Map
and other related product information to section 2.0.
05/04
-003
Correct valid order table 1 and table 24. Correct memory map
figures and other general document clarifications.
Datasheet
5
Contents
6
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
1.0
Introduction
This document provides information about the Intel StrataFlash® Wireless Memory System (LV18/
LV30 SCSP); 768-Mbit LVQ Family with Asynchronous Static RAM device, including
information on the features, characteristics, operations, and specifications for:
• Code and data segment flash dies
• SRAM and PSRAM dies
The intent of this document is to provide information where this 768-Mbit LVQ Family with
Asynchronous Static RAM Stacked Chip Scale Package (SCSP) device differs from the Intel
StrataFlash® Wireless Memory System (LV18/LV30 SCSP); 1024-Mbit LV Family device. Refer
to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP; 1024-
Mbit LV Family Datasheet (order number 253854) for flash product details not included in this
document.
1.1
Nomenclature
0x
0b
Byte
k (noun)
Kb
Hexadecimal prefix
Binary prefix
8 bits
1 thousand
1024 bits
KB
1024 bytes
1024 words
1 million
1,048,576 bits
1,048,576 bytes
16 bits
Kword
M (noun)
Mb
MB
Word
1.8 V Core
1.8 V I/O
Asserted
Block
Device VCC (core) voltage range of 1.7 V – 1.95 V
Device VCCQ (Input/Output) voltage range of 1.7 V – 1.95 V
Signal with logical voltage level VIL, or enabled
Group of cells, bits, bytes or words within the flash memory array that
get erased with one erase instruction
Bottom parameter
Code segment
Data segment
Deasserted
Previously referred to as a bottom-boot device, a device with flash
parameter partition located at the lowest physical address of its memory
map for processor system boot up.
A segment that contains one or two flash memory dies optimized for
fast code or data reads. Each die features multi-partition synchronous
read-while-write or burst read-while-erase capability.
A segment contains one or two flash memory dies optimized for large
embedded data. Each die feature single-partition asynchronous read,
write, and erase operations.
Signal with logical voltage level VIH, or disabled
Datasheet
7
768-Mbit LVQ Family with Asynchronous Static RAM
Device
Die
An individual flash die or a flash + xRAM SCSP.
Individual physical flash die used in a stacked-CSP memory subsystem
device
High-Z
High Impedance
Low-Z
Driven
Main block
Main partition
Non-Array Reads
Any 64-Kword flash array block.
A flash partition containing only main blocks.
Flash reads which return flash Device Identifier, CFI Query, Protection
Register and Status Register information
Parameter block
Partition
Any 16-Kword flash array block.
A group of flash blocks that shares common status register read state.
A flash partition containing parameter and main blocks.
An operation to Write data to the flash array
Parameter partition
Program
Segment
A section of the SCSP memory subsystem divided for different
operating characteristics. The SCSP memory subsystem has three
segments: a code segment, a data segment, and an xRAM segment.
Subsystem
A stacked memory integration concept made up of multiple memory
dies arranged in Code, Data, and xRAM segments.
Top parameter
Previously referred to as a top-boot device, a device with flash
parameter partition located at the highest physical address of its
memory map for processor system boot up.
Write
Bus cycle operation at the inputs of the flash die, in which a command
or data are sent to the flash array
xRAM segment
A segment contains one or two xRAM memory dies. The xRAM
combinations could include SRAM, PSRAM, or LPSDRAM.
1.2
Acronyms
APS
Automatic Power Savings
Buffered Enhanced Factory Programming
Common Flash Interface
Command User Interface
Do Not Use
Buffered-EFP
CFI
CUI
DU
MLC technology
Multi-Level-Cell technology
8
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
ETOX
OTP
PLR
PR
EPROM Tunnel Oxide
One-Time Programmable
Protection Lock Register
Protection Register
RCR
RFU
RWE
RWW
SCSP
SR
Read Configuration Register
Reserved for Future Use (all unused active signals in a package ballout)
Read-While-Erase
Read-While-Write
Stacked Chip Scale Package
Status Register
SRD
WSM
Status Register Data
Write State Machine
1.3
Conventions
0x
0b
A5
Hexadecimal number prefix
Binary number prefix
Denotes one element of a signal group membership, in this case address
bit 5.
ADV#
Denotes a global signal of the device, Address Valid because there is no
die specific reference.
Clear
Logical zero (0)
DQ[15:0]
F[3:1]-CE#
Denotes a group of similarly named signals, such as data bus.
This is the method used to refer to more than one chip-enable or output
enable at the same time. When each is referred to individually, the
reference will be F1-CE# (for die #1), F2-CE# (for die #2), and F3-CE#
(for die #3). “F” denotes the flash specific signal and “CE#” is the root
signal name of the flash die. Other notation includes: “S” to denote
SRAM, “P” to denote PSRAM, “and “R” to denote common RAM type
signal names.
Set
Logical one (1)
SR[4]
Denotes an individual flash status register bit, in this case bit 4 of
SR[7:0].
VCC
VCC
Signal or voltage connection
Signal or voltage level
Datasheet
9
768-Mbit LVQ Family with Asynchronous Static RAM
2.0
Functional Overview
This section provides an overview of the code and embedded data segment features and
capabilities of the 768-Mbit LVQ Family with Asynchronous Static RAM device.
2.1
Product Description
The 768-Mbit LVQ Family with Asynchronous Static RAM device incorporates flash dies used as
code segment flash memory and large embedded data segment flash memory, along with xRAM
for a high performance, cost-effective high density memory system solution. This stacked device
uses the latest Intel StrataFlash® Wireless Memory System on 0.13 µm ETOX™ VIII process
technology.
The code segment is a high performance, multi-partition, synchronous burst-mode Read-While-
Write (RWW) or Read-While-Erase (RWE) flash memory die, while the large, embedded data
segment is a cost efficient, single-partition, asynchronous flash memory die.
The package for this device is available in a QUAD+ ballout, which supports flash only or flash +
PSRAM and/or SRAM stacked memory combinations. The SCSP in a QUAD+ ballout with a 0.8
mm ball pitch, 8x10 active ball matrix supports a memory subsystem up to 66 MHz on a x16-bit
bus width.
The 768-Mbit LVQ Family with Asynchronous Static RAM device consists of a 1.8 V flash
memory device with 1.8 V and 3.0 V I/O options. As shown in Figure 1, “LVQ18/LVQ30 Device
Family Block Diagram” on page 11, the device is available with a minimum of one flash die each
per code segment and data segment (flash die # 1 and flash die #2). An optional third flash die is
available for either the code or data segment. See Table 1, “Valid-Combination for LVQ Family
with Asynchronous Static RAM” on page 11.
Designed for low-voltage systems, the LVQ supports read operations with F-VCC at 1.8 V, and
erase and program operations with F-Vpp at 1.8 V. Buffered Enhanced Factory Programming
(Buffered-EFP) provides the fastest flash array programming performance, with elevated F-VPP at
9.0 V to increase factory throughput. With F-VPP at 1.8 V, F-VCC and F-VPP can be tied together
for a simple, ultra-low-power design. In addition to voltage flexibility, a dedicated F-VPP
connection provides complete data protection when F-Vpp ≤ VPPLK
.
The Intel StrataFlash® Wireless Memory System provides data security through its individual zero-
latency block lock capability. Each memory block can be unlocked, locked, or locked-down by
hardware or software control.
Individualized F-CE# control allows the user to manage which flash die is asserted, furthering the
flexibility of power management while controlling data integrity per segment with F-WP#. The
F[2:1]-OE# in LVQ products with QUAD+ ballout are common internally
10
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 1. LVQ18/LVQ30 Device Family Block Diagram
LVQ Family
Flash (Code/Data) Segment
F2-CE#
F2-OE#
F1-CE#
F1-OE#
Flash Die #2†
(128- or 256-Mbit)
Flash Die #1
(128- or 256-Mbit)
F1-VCC
F-WE#
F-RST#
F-WP#
F2-VCC
F3-CE#
Flash Die #3†
(128- or 256-Mbit)
ADV#
CLK
F-VPP
WAIT
VCCQ
VSS
DQ[15:0]
xRAM Segment
A[MAX:MIN]
P-VCC
P1-CS#
PSRAM Die #1
(32/64/128-
Mbit)
R-UB#
R-LB#
P-MODE/
P-CRE
R-OE#
R-WE#
P2-CS#
SRAM Die #1
S-VCC
S-CS1#
S-CS2
PSRAM Die #2
(64/128-Mbit)
(8-Mbit)
Note: †: Flash die #2 and die #3 can be configured either as a Code or a Data die option within the 768-Mbit LVQ
device family
Table 1. Valid-Combination for LVQ Family with Asynchronous Static RAM
Package
Size
(mm)
I//O
Flash Components:
RAM Components:
Density (Mbit) & Type
Package Package Valid Order Part
Notes
Voltage Density (Mbit) & Type
Ball Type Type
Number
RD38F4420LVYTQ0
RD38F4420LVYBQ0
256 L18 + 256 V18
8 SRAM
8x11x1.4 Leaded
SCSP
NOTE: For combinations not listed, please contact your local Intel sales representative for details.
Datasheet
11
768-Mbit LVQ Family with Asynchronous Static RAM
2.2
Product Segment Unique Features
The code segment of the 768-Mbit LVQ Family with Asynchronous Static RAM device includes
the following enhanced features unless specifically noted otherwise:
• 64 unique (Intel pre-programmed) identifier bits and 2,112 user-programmable OTP bits for
each code segment flash die.
• Traditional write, erase, and burst-mode read capabilities of Intel® Wireless flash memory.
• Simultaneous RWW/RWE operations, enabling a burst read operation in one partition while
simultaneous with program or erase operations in other partitions.
• Burst-read across partition boundaries, but not across segment dies within the subsystem.
Note: User application code is responsible for ensuring that burst-mode reads do not cross into a partition
that is in program or erase mode.
The embedded data segment includes the following features unless specifically noted otherwise:
• High Density offerings of up to 512 Mb designated specifically for large embedded data.
• Single partition asynchronous page-mode read operation, allowing for a cost-effective ideal
storage format.
• Read-while-program or read-while-erase operations can be accomplished with software
through program suspend and erase suspend operations.
2.3
Product Configurations and Memory Partitioning
By default, the first flash die is the first code segment flash die, a fast, eXecute-In-Place (XIP)
solution ideal for an instruction fetch application. This portion is the user-selected parameter
configuration option, made up of either a 128-Mbit flash die or a 256-Mbit flash die, each
containing one parameter partition and several main partitions. The parameter partition contains
four 16-KWord parameter blocks and seven 64-KWord main blocks; all main partitions consist of
eight 64-KWord main blocks.
The large, embedded data segment is a single partition asynchronous page-mode read device that
can be made up of multiple dies with densities of 128-Mbit or 256-Mbit. The single partition is
made up of four 16-Kword parameter blocks and 64-Kword main blocks. The data segment flash
die parameter configuration will always be the opposite of the code segment flash die parameter
configuration. See Table 3, “LVQ Flash Code and Data Die Stacked Configuration” on page 14 for
examples of configuration options.
The code and embedded data portions of the LVQ device are both asymmetrical in blocking. Each
memory block features zero-latency block locking. Data integrity is protected even further with the
optional use of F-VPP and F-WP# to implement block lock down.
The user has the choice of selecting either a top or a bottom parameter partition configuration for
the code segment flash die. Depending on the choice of configuration, the data segment flash die in
the LVQ device will be parametrically opposed. For instance, if the user selects top parameter
configuration for the code segment flash die, the data segment flash die in the package will be
configured as bottom parameter configuration, and vice-versa. This ensures the largest number of
contiguous main block addresses for software efficiency.
12
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
The xRAM segment can consist of up to two Pseudo-SRAM (PSRAM) dies and one SRAM die
with the following possible densities:
• The first PSRAM die can have a density of 64-Mbit or 128-Mbit.
• The second PSRAM die can have a density of 64-Mbit or 32-Mbit.
• The SRAM die has a density of 8-Mbit.
For the code segment, the 128-Mbit flash die has an 8-Mbit partition block and the 256-Mbit flash
die has a 16-Mbit partition block. The minimum code + data density combination for the LV18/
LV30 family is 384 Mbit.
Figure 2. Top Parameter Configuration Stacked Convention
Parameter Blocks
Code
(Top)
Code
(Top)
Code
(Top)
Code
(Top)
Main Blocks
Data
(Bottom)
Data
(Top)
Code
(Top)
Code
(Bottom)
Parameter Blocks
Data
(Bottom)
Data
(Bottom)
Data
(Top)
1 Code + 1 Data
Data
(Bottom)
1 Code + 2 Data
2 Code + 1 Data
2 Code + 2 Data
Datasheet
13
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 3. Bottom Parameter Configuration Stacked Convention
Data
(Top)
Data
(Top)
Data
(Top)
Data
(Bottom)
Parameter Blocks
Data
(Top)
Data
(Bottom)
Code
(Bottom)
Code
(Top)
Main Blocks
Code
Code
Code
Code
(Bottom)
(Bottom)
(Bottom)
(Bottom)
Parameter Blocks
1 Code + 1 Data
1 Code + 2 Data
2 Code + 1 Data
2 Code + 2 Data
Table 2. Pre-assigned Flash-CE# Definition for LVQ Device Family
Stacked Combo:
Code + Data
Flash Die #1
F1-CE# (Code)
F1-CE# (Code)
F1-CE# (Code)
Flash Die #2
F2-CE# (Data)
F2-CE# (Data)
F2-CE# (Code)
F2-CE# (Code)
Flash Die #3
N/A
Flash Die #4
N/A
N/A
Code + Data + Data
Code + Code + Data
F3-CE# (Data)
F3-CE# (Data)
F3-CE# (Data)
N/A
Code + Code + Data + Data F1-CE# (Code)
F4-CE# (Data)
Table 3. LVQ Flash Code and Data Die Stacked Configuration (Sheet 1 of 2)
Top and Bottom Parameter Stacked Configuration
Code Segment
Data Segment
Die Stack Configuration
1st Flash
Code Die
(user selected)
2nd Flash
Code Die
1st Flash Data
Die
2nd Flash
Data Die
Code only
Code + Data
Please contact your local Intel representative for details.
Top
Top
Top
Top
NA
NA
Bottom
Top
NA
Top
Code + Data + Data
Code + Code + Data
Code + Code + Data + Data
Bottom
NA
Top
Bottom
Top
Bottom
Bottom
14
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Table 3. LVQ Flash Code and Data Die Stacked Configuration (Sheet 2 of 2)
Top and Bottom Parameter Stacked Configuration
Code Segment
Data Segment
Die Stack Configuration
1st Flash
Code Die
(user selected)
2nd Flash
Code Die
1st Flash Data
Die
2nd Flash
Data Die
Code only
Code + Data
Please contact your local Intel representative for details.
Bottom
Bottom
Bottom
Bottom
NA
NA
Top
Bottom
Top
NA
Top
NA
Bottom
Code + Data + Data
Code + Code + Data
Code + Code + Data + Data
Bottom
Top
Bottom
Top
2.4
Memory Map
The 768-Mbit LVQ Family with Asynchronous Static RAM device is available in several density
and parameter configurations. The memory map is based on the stacking of individual flash die
density options of 128 Mbit or 256 Mbit. The memory map shows individual flash die
configurations and block/partition allocations.
The code segment flash die is made up of 128-Mbit dies or 256-Mbit dies, each containing one
parameter partition and several main partitions.
• The 128-Mbit memory array is divided into sixteen 8-Mbit partitions. Each die density
contains one parameter partition and fifteen main partitions. The 8-Mbit top or bottom
parameter partition contains four 16-Kword blocks and seven 64-Kword blocks. Each of the
remaining fifteen 8-Mbit main partitions contains eight 64-Kword blocks.
• The 256-Mbit memory array is divided into sixteen 16-Mbit partitions. Each device contains
one parameter partition and fifteen main partitions. The 16-Mbit top or bottom parameter
partition contains four 16-Kword blocks and fifteen 64-Kword blocks. Each of the remaining
fifteen 16-Mbit main partitions contains sixteen 64-Kword blocks.
The data segment flash die density is made up of 128-Mbit dies or 256-Mbit dies, each containing
a single partition architecture made up of four 16-Kword parameter blocks and 64-Kword main
blocks. The memory map and partitioning for various flash die combinations, top and bottom
parameters and are shown in the following tables:
Note: Only 128-Mbit and 256-Mbit flash die densities are used in three flash die SCSP combinations.
• Table 4, “Two Flash Dies (Top Parameter) SCSP Memory Map” on page 16
• Table 5, “Two Flash Dies (Bottom Parameter) SCSP Memory Map” on page 17
• Table 6, “Three Flash Dies (Top Parameter) SCSP Memory Map” on page 18
• Table 7, “Three Flash Dies (Bottom Parameter) SCSP Memory Map” on page 19
Datasheet
15
768-Mbit LVQ Family with Asynchronous Static RAM
Table 4. Two Flash Dies (Top Parameter) SCSP Memory Map
128-Mbit Flash
256-Mbit Flash
Bloc Address Range
Block Partition
Partition
Size
(Mbit)
Flash
Die#
Flash Die Type
Partitioning
Size
Size
(KW)
(Mbit)
Bloc
Address Range
16
130
7FC000-7FFFFF
258 FFC000-FFFFFF
Parameter Partition
(Partition 0)
16
64
127
126
7F0000-7F3FFF
7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
64
64
120
119
780000-78FFFF
770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
1
8
16
Main Partitions
(Partition 1-7)
64
64
64
63
400000-4FFFFF
3F0000-3FFFFF
128
800000-80FFFF
127 F70000-F7FFFF
Main Partitions
(Partition 8-15)
64
0
000000-00FFFF
7F0000-7FFFFF
0
000000-00FFFF
64
...
130
258 FF0000-FFFFFF
64
64
67
66
400000-40FFFF
3F0000-3FFFFF
131
800000-80FFFF
Single Partition
130 7F0000-7FFFFF
4x16 Kword
Parameter Blocks
64
64
11
10
080000-08FFFF
070000-07FFFF
19
18
100000-10FFFF
0F0000-0FFFFF
2
128
256
127x64 Kword Main
Blocks (128 Mb)
255x64 Kword Main
Blocks (256 Mb
64
16
4
3
010000-01FFFF
00C000-00FFFF
4
3
010000-01FFFF
00C000-00FFFF
16
0
000000-003FFF
0
000000-003FFF
16
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Table 5. Two Flash Dies (Bottom Parameter) SCSP Memory Map
128-Mbit Flash
256-Mbit Flash
Bloc Address Range
Block Partition
Partition
Size
(Mbit)
Flash
Die#
Flash Die Type
Partitioning
Size
Size
(KW)
(Mbit)
Bloc
Address Range
16
130
7FC000-7FFFFF
258 FFC000-FFFFFF
16
64
127
126
7F0000-7F3FFF
7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
Single Partition
4x16 Kword
Parameter Blocks
64
64
120
119
780000-78FFFF
770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
2
128
256
127x64 Kword Main
Blocks (128 Mb)
255x64 Kword Main
Blocks (256 Mb
64
64
64
63
400000-4FFFFF
3F0000-3FFFFF
128
800000-80FFFF
127 F70000-F7FFFF
64
0
000000-00FFFF
7F0000-7FFFFF
0
000000-00FFFF
64
...
130
258 FF0000-FFFFFF
Main Partitions
(Partition 8-15)
64
64
67
66
400000-40FFFF
3F0000-3FFFFF
131
800000-80FFFF
130 7F0000-7FFFFF
Main Partitions
(Partition 1-7)
64
64
11
10
080000-08FFFF
070000-07FFFF
19
18
100000-10FFFF
0F0000-0FFFFF
1
8
16
Parameter Partition
(Partition 0)
64
16
4
3
010000-01FFFF
00C000-00FFFF
4
3
010000-01FFFF
00C000-00FFFF
16
0
000000-003FFF
0
000000-003FFF
Datasheet
17
768-Mbit LVQ Family with Asynchronous Static RAM
Table 6. Three Flash Dies (Top Parameter) SCSP Memory Map
128-Mbit Flash
256-Mbit Flash
Bloc Address Range
Block Partition
Partition
Size
(Mbit)
Flash
Die#
Flash Die Type
Partitioning
Size
Size
(KW)
(Mbit)
Bloc
Address Range
16
130
7FC000-7FFFFF
258 FFC000-FFFFFF
Parameter Partition
(Partition 0)
16
64
127
126
7F0000-7F3FFF
7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
64
64
120
119
780000-78FFFF
770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
1
2
3
8
16
Main Partitions
(Partition 1-7)
64
64
64
63
400000-4FFFFF
3F0000-3FFFFF
128
800000-80FFFF
127 F70000-F7FFFF
Main Partitions
(Partition 8-15)
64
16
0
000000-00FFFF
7FC000-7FFFFF
0
000000-00FFFF
130
258 FFC000-FFFFFF
Parameter Partition
(Partition 0)
16
64
127
126
7F0000-7F3FFF
7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
64
64
120
119
780000-78FFFF
770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
8
16
Main Partitions
(Partition 1-7)
64
64
64
63
400000-4FFFFF
3F0000-3FFFFF
128
800000-80FFFF
127 F70000-F7FFFF
Main Partitions
(Partition 8-15)
64
0
000000-00FFFF
7F0000-7FFFFF
0
000000-00FFFF
64
...
130
258 FF0000-FFFFFF
64
64
67
66
400000-40FFFF
3F0000-3FFFFF
131
800000-80FFFF
Single Partition
130 7F0000-7FFFFF
4x16 Kword
Parameter Blocks
64
64
11
10
080000-08FFFF
070000-07FFFF
19
18
100000-10FFFF
0F0000-0FFFFF
128
256
127x64 Kword Main
Blocks (128 Mb)
255x64 Kword Main
Blocks (256 Mb
64
16
4
3
010000-01FFFF
00C000-00FFFF
4
3
010000-01FFFF
00C000-00FFFF
16
0
000000-003FFF
0
000000-003FFF
18
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Table 7. Three Flash Dies (Bottom Parameter) SCSP Memory Map
128-Mbit Flash
256-Mbit Flash
Blk# Address Range
Block Partition
Partition
Size
(Mbit)
Flash
Die Stack
Partitioning
Size
Size
Die# Configuration
(KW)
(Mbit)
Blk#
Address Range
16
130
7FC000-7FFFFF
258 FFC000-FFFFFF
16
64
127
126
7F0000-7F3FFF
7E0000-7EFFFF
255 FF0000-FF3FFF
254 FE0000-FEFFFF
Single Partition
4x16 Kword
Parameter Blocks
64
64
120
119
780000-78FFFF
770000-77FFFF
240 F00000-FFFFFF
239 EF0000-EFFFFF
3
128
256
127x64 Kword Main
Blocks (128 Mb)
255x64 Kword Main
Blocks (256 Mb
64
64
64
63
400000-4FFFFF
3F0000-3FFFFF
128
800000-80FFFF
127 F70000-F7FFFF
64
0
000000-00FFFF
7F0000-7FFFFF
0
000000-00FFFF
64
...
130
258 FF0000-FFFFFF
Main Partitions
(Partition 8-15)
64
64
67
66
400000-40FFFF
3F0000-3FFFFF
131
800000-80FFFF
130 7F0000-7FFFFF
Main Partitions
(Partition 1-7)
64
64
11
10
080000-08FFFF
070000-07FFFF
19
18
100000-10FFFF
0F0000-0FFFFF
2
8
16
Parameter Partition
(Partition 0)
64
16
4
3
010000-01FFFF
00C000-00FFFF
4
3
010000-01FFFF
00C000-00FFFF
16
0
000000-003FFF
7F0000-7FFFFF
0
000000-003FFF
64
...
130
258 FF0000-FFFFFF
Main Partitions
(Partition 8-15)
64
64
67
66
400000-40FFFF
3F0000-3FFFFF
131
800000-80FFFF
130 7F0000-7FFFFF
Main Partitions
(Partition 1-7)
64
64
11
10
080000-08FFFF
070000-07FFFF
19
18
100000-10FFFF
0F0000-0FFFFF
1
8
16
Parameter Partition
(Partition 0)
64
16
4
3
010000-01FFFF
00C000-00FFFF
4
3
010000-01FFFF
00C000-00FFFF
16
0
000000-003FFF
0
000000-003FFF
Datasheet
19
768-Mbit LVQ Family with Asynchronous Static RAM
3.0
Package Information
The 768-Mbit LVQ family with asynchronous static RAM is available in SCSP mechanical
package. The package type used is defined by the flash density option and the number of dies
stacked used in the device, as referenced in Table 23, “Valid-Combination for LVQ Family with
Asynchronous Static RAM” on page 49. For line items using SCSP QUAD+ package, refer to
Figure 4 for detail mechanical specifications.
Figure 4. SCSP QUAD+ Mechanical Specs (8x11x1.4 mm)
A1 Index
Mark
S1
8
7
6
5
4
3
2
1
2
3
4
5
6
7
8
1
S2
A
A
B
C
B
C
D
D
E
F
E
F
D
e
G
H
G
H
J
J
K
K
L
L
M
M
b
E
Top View - Ball Down
Bottom View - Ball Up
A
A2
A1
Y
Drawing not to scale.
Millimeters
Nom
Inches
Nom
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Symbol
Min
Max Notes
1.400
Min
Max
0.0551
A
A1
A2
b
D
E
0.200
0.0079
1.070
0.375
11.000
8.000
0.800
88
0.0421
0.0148
0.4331
0.3150
0.0315
88
0.325
10.900
7.900
0.425
11.100
8.100
0.0128
0.4291
0.3110
0.0167
0.4370
0.3189
e
N
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Y
S1
S2
0.100
1.300
1.200
0.0039
0.0512
0.0472
1.100
1.000
1.200
1.100
0.0433
0.0394
0.0472
0.0433
20
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
4.0
Ballout and Signal Descriptions
Combinations in the L18/L30 SCSP LQ family are available in an 88-ball (8x10 active ball matrix)
QUAD+ ballout with a ball pitch of 0.8 mm. Figure 5 shows the QUAD+ ballout. Refer to Figure
4, “SCSP QUAD+ Mechanical Specs (8x11x1.4 mm)” on page 20 for details.
Figure 5. QUAD+ Signal Ballout for LVQ Device Family
Pin 1
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
DU
DU
DU
A
B
C
D
E
F
A4
A5
A18
R-LB#
A17
A19
A23
VSS
VSS
F1-VCC
S-CS2
R-W E#
ADV#
F-W E#
DQ5
F2-VCC
CLK
A21
A22
A11
A12
A3
A24
F-VPP
F-W P#
F-RST#
DQ10
DQ3
P1-CS#
A20
A9
A13
A2
A7
A25
A10
A15
A1
A6
R-UB#
DQ2
A8
A14
A16
G
H
J
A0
DQ8
DQ13
DQ14
DQ6
W AIT
DQ7
DQ15
VCCQ
VSS
F2-CE#
F2-OE#
VCCQ
G
H
J
R-OE#
S-CS1#
F1-CE#
VSS
DQ0
DQ1
DQ12
DQ4
F1-OE#
P2-CS#
VSS
DQ9
DQ11
S-VCC
F1-VCC
P-Mode/ P-
CRE
K
L
F3-CE#
VCCQ
P-VCC
VSS
F2-VCC
VSS
K
L
VSS
M
DU
1
DU
2
DU
7
DU
8
M
3
4
5
6
Top View - Ball Side Down
Global Signals
De-Populated Balls
Flash Specific
Legend:
SRAM/PSRAM Specific
Do Not Use
Datasheet
21
768-Mbit LVQ Family with Asynchronous Static RAM
4.1
Signal Descriptions
Table 8 describes the active signals used on the 768-Mbit LVQ Family with Asynchronous Static
RAM device.
Table 8. Signal Descriptions (Sheet 1 of 3)
Symbol
Type
Description
ADDRESS: Global device signals for selected die.
Address inputs for all memory dies during read and write operations for x16 data bus.
•
•
•
•
•
256-Mbit Die : AMAX = A23
128-Mbit Die : AMAX = A22
64-Mbit Die : AMAX = A21
32-Mbit Die : AMAX = A20
8-Mbit Die : AMAX = A18
A[MAX:MIN]
Input
A0 is the lowest-order 16-bit wide address.
A[25:24] denote higher-order addresses for future device densities and should be
treated as an RFU. A[25:24] can be tied to a static V or V state.
IH
IL
DATA INPUT/OUTPUT: Global device signals for selected die.
Input/ Inputs data and commands during write cycles, outputs data during read cycles. Data
Output signals float when the device or its outputs are deselected.
DQ[15:0]
•
Data are internally latched during writes to the flash device.
CHIP ENABLE: Low-true input to enable the flash die.
F[3:1]-CE# low enable flash memory die. When asserted, flash internal control logic,
input buffers, decoders, and sense amplifiers are active. When deasserted, the
associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
•
F1-CE# selects or deselects flash die #1. F1-CE# is always the default Chip
Enable for the user defined parameter configured code die.
F[3:1]-CE#
Input
•
F2-CE# selects or deselects flash die #2 and is RFU on combinations with only
one flash die. F3-CE# selects or deselects flash die #3 and is RFU on stacked
combinations with only one or two flash dies.
•
If F[3:2]-CE# are unused, each can be pulled high to VCCQ through a 10K-ohm
resistor for future design flexibility.
SRAM CHIP SELECT: Low-true / High-true input (S-CS1# / S-CS2 respectively) to
enable the SRAM die.
When either/both SRAM Chip Select signals are asserted, SRAM internal control
logic, input buffers, decoders, and sense amplifiers are active. When either/both
SRAM chip selects are deasserted (S-CS1# = VIH or S-CS2 = VIL), the SRAM is
deselected and its power is reduced to standby levels.
S-CS1#
S-CS2
Input
•
S-CS1# and S-CS2 are available on stacked combinations with SRAM die and
are RFU on stacked combinations without SRAM die.
•
If S-CS1# and S-CS2 are unused, S-CS1# can be pulled high to VCCQ through
a 10K-ohm resistor, and S-CS2 can be tied to VSS, else can be left floated.
PSRAM CHIP SELECT: Low-true input to enable the PSRAM die.
P[2:1]-CS# low enable the PSRAM internal control logic, input buffers, decoders, and
sense amplifiers are active. When deasserted, the PSRAM is deselected and its
power is reduced to standby levels.
P[2:1]-CS#
Input
•
•
P1-CS# selects PSRAM die.
P2-CS# is unused and should be treated as an RFU. P2-CS# can be pulled high
to VCCQ through a 10K-ohm resistor for future design flexibility, else can be left
floated.
22
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Table 8. Signal Descriptions (Sheet 2 of 3)
FLASH OUTPUT ENABLE: Low-true input for selected flash die.
F[2:1]-OE# low enables the flash output buffers. F[2:1]-OE# high disables the flash
output buffers, and places the selected flash outputs and WAIT in High-Z.
F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die
#2 and flash die #3. F2-OE# is available on stacked combinations with two or three
flash dies else it is an RFU on stacked combinations with only one flash die.
F[2:1]-OE#
Input
•
If F2-OE# is unused, it can be pulled high to VCCQ through a 10K-ohm resistor
for future design flexibility.
RAM OUTPUT ENABLE: Low-true input for selected RAM die.
R-OE#-low enables the selected RAM output buffers. R-OE#-high disables the RAM
output buffers, and places the selected RAM outputs in High-Z.
R-OE#
F-WE#
R-WE#
Input
Input
Input
•
R-OE# is available on stacked combinations with PSRAM or SRAM die, and is
an RFU on flash-only stacked combinations.
FLASH WRITE ENABLE: Low-true input for selected flash die.
F-WE# low controls write operations to the selected flash die. Address and data are
latched on the rising edge of F-WE#.
•
F-WE# high disables the flash write operation, and places the selected flash
outputs in High-Z.
RAM WRITE ENABLE: Low-true input for selected RAM die.
R-WE# controls writes to the selected RAM die. R-WE# high disables the selected
RAM write operation, and places the selected RAM outputs in High-Z.
•
R-WE# is available on stacked combinations with PSRAM or SRAM die and is an
RFU on flash-only stacked combinations.
CLOCK: Synchronizes the flash die with the system bus clock in synchronous read
mode and increments the internal address generator.
•
•
During synchronous read operations, addresses are latched on the rising edge of
ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
CLK
Input
In asynchronous mode, addresses are latched on the rising edge ADV#, or are
continuously flow-through when ADV# is kept asserted.
WAIT: User configurable high-true or low-true output.
Indicates data is valid in synchronous array or non-array sync flash reads.
Configuration Register bit 10 (CR.10, WT) determines its polarity when asserted.
With F-CE# and F-OE# at V , WAIT’s active output is V or V . WAIT is high-Z if
IL
OL
OH
WAIT
Output
F-CE# or F-OE# is V
.
IH
•
In synchronous array or non-array flash read modes, WAIT indicates invalid data
when asserted and valid data when deasserted.
•
In asynchronous flash page read, and all flash write modes, WAIT is deasserted.
FLASH WRITE PROTECT: Low-true input for selected flash die.
F-WP# enables/disables the lock-down protection mechanism of the selected flash
die.
F-WP#
ADV#
Input
•
F-WP# low enables the lock-down mechanism where locked down blocks cannot
be unlocked with software commands.
•
F-WP# high disables the lock-down mechanism, allowing locked down blocks to
be unlocked with software commands.
ADDRESS VALID: Low-true input for selected flash die.
•
In synchronous flash read operations, addresses are latched on the rising edge
of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
Input
Input
•
In asynchronous flash read operations, addresses are latched on the rising edge
of ADV#, or are continuously flow-through when ADV# is kept asserted.
RAM UPPER / LOWER BYTE ENABLES: Low-true input for the selected RAM die.
During RAM read and write cycles, R-UB# low enables the RAM high order bytes on
DQ[15:8], and R-LB# low enables the RAM low-order bytes on DQ[7:0].
R-UB#
R-LB#
R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die
and are RFU on flash-only stacked combinations.
Datasheet
23
768-Mbit LVQ Family with Asynchronous Static RAM
Table 8. Signal Descriptions (Sheet 3 of 3)
FLASH RESET: Low-true input for the selected flash die.
F-RST# low initializes flash internal circuitry and disables flash operations. F-RST#
high enables flash operation. Exit from reset places the flash in asynchronous read
array mode.
F-RST#
Input
P-Mode/PSRAM MODE: Low-true input for selected asynchronous PSRAM die.
•
P-Mode is used to program the configuration register, and enter/exit Low Power
Mode of PSRAM die.
•
P-Mode is available on stacked combinations with asynchronous-only PSRAM
die.
P-Mode,
P-CRE
Input
P-CRE/PSRAM CONTROL REGISTER ENABLE : High-true input for selected
synchronous PSRAM die.
When P-CRE is high, write operations load the PSRAM Refresh Control Register (P-
RCR) or Bus Control Register (BCR).
•
•
P-CRE is applicable only on combinations with synchronous PSRAM die.
P-Mode, P-CRE is an RFU on stacked combinations without PSRAM die.
FLASH PROGRAM AND ERASE POWER: Valid F-V voltage on this ball enables
PP
flash program/erase operations.
Flash memory array contents cannot be altered when F-V (F-V
) < V
PPLK
PP
PEN
F-VPP,
Power (V
). Erase / program operations at invalid F-V (F-V
be attempted. Refer to flash discrete product datasheet for additional details.
) voltages should not
PENLK
PP
PEN
F-VPEN
•
F-VPEN (Erase/Program/Block Lock Enables) is not used in the L18/L30 SCSP
products.
FLASH CORE VOLTAGE : Flash core source voltage.
F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power to
the core logic of flash die #2 and flash die #3.
•
Write operations to the flash array are inhibited when F-V ≤ V
.
CC
CCLKO
F[2:1]-VCC
Power
Operations at invalid F-V voltages should not be attempted.
CC
•
•
Flash operations at invalid F-V voltages should not be attempted.
CC
F2-VCC is available on stacked combinations with two or three flash dies, and is
an RFU on stacked combinations with only one flash die.
SRAM POWER SUPPLY: Supplies power for SRAM operations.
S-VCC
P-VCC
Power
Power
S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked
combinations without SRAM die.
PSRAM POWER SUPPLY: Supplies power for PSRAM operations.
P-VCC is available on stacked combinations with PSRAM die, and is RFU on stacked
combinations without PSRAM die.
VCCQ
VSS
Power DEVICE I/O POWER: Supply power for the device input and output buffers.
Power DEVICE GROUND: Connect to system ground. Do not float any VSS connection.
RESERVED for FUTURE USE: Reserved for future device functionality/
enhancements. Contact Intel regarding the use of balls designated RFU.
RFU
DU
DO NOT USE: Do not connect to any other signal, or power supply; must be left
floating.
24
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
5.0
Maximum Ratings and Operating Conditions
5.1
Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only.
NOTICE: This document contains information available at the time of its release. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
Table 9. Absolute Maximum Ratings
Parameter
MIN
MAX
Unit
Notes
Temperature under Bias Expanded
Storage Temperature
–25
–55
+85
°C
°C
5
5
+125
Voltage On Any Signal (except F-V , V
F-V
PP,
CC
CCQ,
–0.5
+3.6
V
1,5
S-V , and P-V
CC
CC)
F-V Voltage
–0.2
–0.2
–0.2
–0.2
–
+2.50
+2.50
+3.60
+10.0
100
V
V
1,5
CC
1.8V I/O
3.0 V I/O
1,5
V
, P-V and S-V Voltage
CC CC
CCQ
V
1,5
F-V Voltage
V
1,2,3,5
4,5
PP
I
Output Short Circuit Current
mA
SH
NOTES:
1. All specified voltages are relative to V . Minimum DC voltage is –0.5 V on input/output signals, –0.2 V
SS
on V
and F-V signals. During transitions, this level may overshoot to –2.0 V for periods < 20 ns.
CCQ
PP
Maximum DC voltage on F-V is V + 0.5 V, which during transitions may overshoot to F-Vcc +2.0 V
CC
CC
for periods <20 ns. Maximum DC voltage on input/output signals and VCCQ is V
+0.5 V, which during
CCQ
transitions may overshoot to V
+ 2.0V for periods < 20ns.
CCQ
2. Maximum DC voltage on F-V may overshoot to +10.0 V for periods < 20 ns.
PP
3. Flash program/erase voltage (F-V ) is typically 1.7 V-2.0 V. F-Vpp can be connected to 8.50 V - 9.50 V
PP
for 1000 cycles on main blocks and 2500 cycles on parameter blocks, or for 80 hours maximum total.
Operation with 9.0 V program/erase voltage may reduce flash block cycling capability.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Absolute DC specifications applies to each flash and RAM die in the SCSP device.
Datasheet
25
768-Mbit LVQ Family with Asynchronous Static RAM
5.2
Operating Conditions
Caution: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond
the “Operating Conditions” may affect device reliability.
Table 10. Extended Temperature Operation
Flash + Flash Flash + PSRAM Flash + PSRAM + SRAM2
Symbol
Parameter
MIN
MAX
MIN
MAX
MIN
MAX
T
Operating Temperature
–25
+85
–25
+85
–25
+85
°C
C
F-V
Flash Supply Voltage
Flash I/O Voltage
1.7
2.2
2.0
3.3
1.7
2.7
2.0
3.1
1.7
2.7
2.0
3.1
V
V
CC
3.0 V I/O
1.8 V I/O
V
CCQ
P-V
S-V
PSRAM and SRAM Supply
Voltage
CC
CC
1.7
2.0
1.8
1.95
–
–
V
1
V
F-V Voltage Supply (Logic Level)
0.9
8.5
2
0.9
8.5
2
0.9
8.5
2
V
V
PPL
PP
1
V
Factory word programming F-V
9.5
9.5
9.5
PPH
PP
NOTES:
1. Flash program/erase voltage (F-V ) is typically 1.7 V-2.0 V. F-Vpp can be connected to 8.50 V - 9.50 V for 1000 cycles on
PP
main blocks and 2500 cycles on parameter blocks, or for 80 hours maximum total. Operation with 9.0 V program/erase
voltage may reduce flash block cycling capability.
2. SRAM is available only in 3.0 V I/O option.
26
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
6.0
Electrical Specifications
6.1
DC Current Characteristics
The DC current characteristics referenced in this document are for individual flash and RAM die in
the SCSP device. The total device current is determined by sum of the active and inactive currents
of each flash and RAM die in the SCSP device.
Note: Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for flash DC characteristics not included
in this document.
SRAM DC characteristics are shown in Table 11. PSRAM DC characteristics are shown in Table
12 on page 28.
NOTICE: Individual DC Characteristics of all dies in a SCSP device need to be considered
accordingly, depending on the SCSP device stacked combinations and operations.
Table 11. SRAM DC Characteristics
3.0 V SRAM
Parameter
Description
Test Conditions
Unit
MIN
MAX
3.3
S-V
Voltage Range
—
—
2.7
1.5
V
V
CC
V
S-V for Data Retention
—
DR
CC
Operating Current at minimum cycle
time
I
I
I
= 0 mA
= 0 mA
—
—
50
10
mA
mA
CC
IO
IO
Operating Current at maximum
cycle time (1 µs)
I
CC2
S-CS1# ≥ S-V -0.2V
CC
or S-CS2 ≤ V +0.2V
SS
I
I
Standby Current
—
—
25
µA
SB
Address/Data toggling at minimum
cycle time
Current in Data Retention mode
Output High Voltage
S-V = 1.5 V
12
—
µA
DR
CC
S-V
0.1
-
-
CC
V
I
= -100 µA
= 100 µA,
V
OH
OH
I
OL
V
Output Low Voltage
Input High Voltage
-0.1
0.1
V
V
OL
V
CCMIN
S-V
0.4
S-V
0.2
+
CC
CC
V
—
IH
V
*I
Input Low Voltage
—
-0.2
-1
0.6
+1
V
IL
Input Leakage Current
-0.2 < V < S-V +0.2 V
µA
IL
IN
CC
-0.2 < V < S-V +0.2 V
Input Leakage Current in Data
Retention Mode
IN
CC
*I
-1
+1
µA
LDR
S-V = V
CC
DR
NOTE: * Input leakage currents include High-Z output leakage for bi-directional buffers with tri-state outputs.
Datasheet
27
768-Mbit LVQ Family with Asynchronous Static RAM
Table 12. PSRAM DC Characteristics
P-V = 1.8 V to 1.95 V
P-V = 2.7 V to 3.1 V
CC
CC
Parameter Description
Test Conditions
Unit
MIN
Typ
MAX
MIN
Typ
MAX
Operating
Current at
minimum
cycle time
I
I
=0mA
OUT
—
—
—
35
—
—
45
mA
CC
P-CS# ≥ P-V
0.2V,P-Mode ≥
P-V -0.2V
-
32-Mbit
64-Mbit
90
100
—
—
90
100
150
µA
µA
CC
Standby
Current
I
SB1
N/A
110
CC
16-Mbit
—
—
—
—
60
50
40
20
70
60
50
30
—
—
—
—
—
—
—
—
—
60
50
40
20
90
80
70
60
20
70
60
µA
µA
µA
µA
µA
µA
µA
µA
µA
8-Mbit
4-Mbit
0-Mbit
16-Mbit
8-Mbit
4-Mbit
0-Mbit
32-
Mbit
50
Partial Array
Refresh
Current
P-CS# ≥ P-V
-
CC
30
0.2V,
I
SB2
110
100
90
(Standby
Mode 2)
P-Mode ≤ 0.2V
64-
Mbit
N/A
80
P-CS# ≥ P-V
-
32-Mbit
64-Mbit
= -0.5 mA
—
20
30
—
30
CC
Deep Power
Down
0.2V,
I
SBD
N/A
—
60
—
80
—
µA
P-Mode ≤ 0.2V
Output High
Voltage
V
I
0.8V
—
—
0.8V
CCQ
V
OH
OH
CCQ
Output Low
Voltage
V
I
= 1 mA
—
—
0.2V
—
—
—
—
0.2V
V
V
V
OL
OL
CCQ
CCQ
V
Input High
Voltage
V
+
CCQ
CCQ
0.3
V
0.8V
—
—
0.8V
CCQ
IH
CCQ
+ 0.3
Input Low
Voltage
V
*I
—
-0.3
0.2V
-0.3
0.2V
IL
IL
CCQ
CCQ
Input
Leakage
Current
V
= 0V to V
= 0V to V
–1.0
—
—
+1.0
+1.0
–1.0
—
—
+1.0
µA
µA
IN
CCQ
V
,
CCQ
I/O
Input/Output
Leakage
P-CS# = V or
IH
*I
–1.0
–1.0
+1.0
OL
R-WE# = V or
IH
Current
R-OE# = V
IH
NOTE: * V : Input voltage, V : Input/Output voltage.
IN
I/O
28
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
7.0
AC Characteristics
7.1
Flash AC Characteristics
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for flash DC characteristics not included
in this document.
Table 13. Device Test Loading Specification for worst case speed conditions
Test Configuration
CL (pF)
1.7 V Standard Test
30
Figure 6. AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
0V
NOTE: AC test inputs are driven at V
for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends
CCQ
at V
/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at F-V or R-V
.
CCQ
CC CC
= V
CC MIN
Figure 7. Transient Equivalent Testing Load Circuit
ZO = 50 Ohms
I/O
Output
CL =
30pf
50
Ohms
P_VCC/2 = VCCQ/2
NOTES:
1. See the following table for component values.
2. Test configuration component value for worst case speed conditions.
3. C includes jig capacitance.
L
Datasheet
29
768-Mbit LVQ Family with Asynchronous Static RAM
7.2
SRAM AC Read Specifications
Table 14. SRAM AC Read Specifications
#
Symbol
Parameter
MIN
MAX
Unit
Notes
R1
R2
R3
R3
R4
R5
R6
R7
R8
R9
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
70
–
–
–
–
–
5
0
0
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Output Delay
S-CS1# to Output Delay
70
70
70
35
70
–
AA
CO1
CO2
OE
S-CS2 to Output Delay
R-OE# to Output Delay
R-UB#, R-LB# to Output Delay
S-CS1# or S-CS2 to Output in Low-Z
R-OE# to Output in Low-Z
S-CS1# or S-CS2 to Output in High-Z
R-OE# to Output in High-Z
BA
1,2
1
LZ
–
OLZ
HZ
25
25
1,2,3
1,3
OHZ
Output Hold (from Address, S-CS1#,
S-CS2, or R-OE# Change, whichever
Occurs First)
R10
t
0
–
ns
OH
R11
t
t
R-UB#, R-LB# to Output in Low-Z
R-UB#, R-LB# to Output in High-Z
0
0
–
ns
ns
1
1
BLZ
R12
25
BHZ
NOTES:
1. Sampled, not 100% tested.
2. At any given temperature and voltage condition, t (MAX) is less than t (MAX) for a given device and
HZ
LZ
from device-to-device interconnection.
3. Timings of t and t are defined as the time at which the outputs achieve the open circuit conditions
HZ
OHZ
and are not referenced to output voltage levels.
30
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 8. SRAM Read Waveform
Device
Data Valid
Standby
Address Selection
VIH
Address Stable
R1
VIL
VIH
S-CS1#
VIL
VIH
S-CS2
R3
VIL
R2
R8
VIH
R- O E #
VIL
R9
VIH
R-W E#
VIL
R4
R7
R10
VOH
R6
R11
High Z
High Z
DATA
Valid Output
VOL
VIH
R12
R5
-
R UB#, R- LB#
VIH
7.3
SRAM AC Write Specifications
Table 15. SRAM AC Characteristics—Write Operations
#
Symbol Parameter
MIN
MAX
Unit
Notes
W1
t
Write Cycle Time
70
0
—
ns
1
3
1
WC
AS
Address Setup to R-WE# (S-CS1#) and R-
UB#,R-LB# Going Low
W2
t
—
ns
W3
W4
t
t
R-WE# (S-CS1#) Pulse Width
Data to Write Time Overlap
55
30
—
—
ns
ns
WP
DW
Address Setup to R-WE# (S-CS1#) Going
High
W5
W6
t
t
60
60
—
—
ns
ns
AW
S-CS1# (R-WE#) Setup to R-WE# (S-CS1#)
Going High
2
4
CW
W7
W8
t
t
Data Hold from R-WE# (S-CS1#) High
Write Recovery
0
0
—
—
ns
ns
DH
WR
R-UB#, R-LB# Setup to R-WE# (S-CS1#)
Going High
W9
t
60
—
ns
BW
NOTES:
1. A write occurs during the S-CS1# and R-WE# asserted overlap (t ). The write begins with the latest
WP
transition of S-CS1# and R-WE# going low (R-UB# and/or R-LB# already asserted). The write ends at the
earliest transition of S-CS1# or R-WE# going high.
2. t
is measured from S-CS1# going low to the end of a write.
CW
3. t is measured from address valid to the beginning of a write.
AS
WR
4. t
is measured from the end of a write to the address change; t
applied in case a write ends as S-
WR
CS1# or R-WE# going high.
Datasheet
31
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 9. SRAM Write Waveform
Device
Address Selection
Standby
VIH
Address Stable
ADDRESSES
S-CS1#
VIL
W1
VIH
W8
VIL
VIH
S-CS2
VIL
W6
VIH
VIL
VIH
VIL
R-OE#
R-WE#
W5
W3
W7
W4
VOH
VOL
High Z
High Z
Data In
W9
DATA
W2
VIH
VIH
R- UB#, R- LB#
Table 16. SRAM Data Retention Timing
Parameter
Description
MIN
MAX
Unit
t
t
Data Retention Set-up Time
0
–
–
ns
ns
SDR
Data Retention Recovery Time
70
RDR
32
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 10. SRAM Data Retention Waveform (S-CS1# Controlled)
tSDR
tRDR
Data Retention Mode
S-VCC
S-VCCmin
S-VIHmin
VDR
S-CS1#
VSS
Figure 11. SRAM Data Retention Waveform (S-CS2 Controlled)
tSDR
tRDR
Data Retention Mode
S-VCC
S-CS2
S-VCCMIN
VDR
VILMAX
VSS
Datasheet
33
768-Mbit LVQ Family with Asynchronous Static RAM
7.4
PSRAM AC Read Specifications
Table 17. PSRAM AC Read Specifications
P-V = 1.80 V to 1.95 V P-V = 2.7 V to 3.1 V
CC
CC
#
Symbol
Parameter
Unit Note
MIN
MAX
MIN
MAX
Read Cycle
R1
R2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
85*
–
–
85*
85*
65
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
RC
Address access time
65
AA
R3
P-CS# Low to Output Valid
–
–
65
CO
R4
R-OE# Low to Output Valid
–
65
85*
–
45
OE
R5
R-UB#, R-LB# Low to Output Valid
P-CS# Low to Output in Low-Z
R-OE# Low to Output in Low-Z
P-CS# High to Output in High-Z
R-OE# High to Output in High-Z
Output Hold from Address change
R-UB#, R-LB# Low to Output in Low-Z
R-UB#, R-LB# High to Output in High-Z
Address set to R-OE# low-level
R-OE# high-level to address hold
P-CS# high-level to address hold
R-LB#, R-UB# high-level to address hold
P-CS# low-level to R-OE# low-level
R-OE# low-level to P-CS# high-level
P-CS# high-level pulse width
–
–
65
5
BA
R6
10
5
–
10
5
–
LZ
R7
–
–
OLZ
HZ
R8
–
25
–
25
R9
–
25
–
25
OHZ
OH
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
5
–
5
–
5
–
5
–
BLZ
BHZ
ASO
OHAH
CHAH
BHAH
CLOL
OLCH
CP
–
25
–
25
0
–
0
–
1
-5
0
–
-5
0
–
–
–
1
1,2
3
0
–
0
–
0
10,000
0
10,000
60
10
10
–
–
45
10
10
–
–
–
–
–
–
R-UB#, R-LB# high-level pulse width
R-OE# high-level pulse width
BP
10,000
10,000
3
4
OP
Page Mode
PR1
PR2
t
t
Page Cycle Time
30
–
–
18
–
–
ns
ns
PC
PA
Page Mode Address Access Time
30
18
NOTES:
1. When R13 ≥ |R15|, |R16| and R19 ≥ 18 ns, the minimum value for R15 and R16 are -15 ns. (See also Figure 12,
“Conditions for Calculating the Minimum Value for R15 and R16” on page 35.)
2. R16 is specified from when both R-LB# and R-UB# become high-level.
3. R17and R21 (MAX) are applied while P-CS# is being hold at low-level.
4. See Figure 13, “AC Waveform for PSRAM Read Operations” on page 35.
5. * 32-Mbit 1.8V PSRAM initial read access timing specifications changed from 85 ns to 88 ns.
34
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 12. Conditions for Calculating the Minimum Value for R15 and R16
R15, R16
Address
R-UB#,R-LB#,
P-CS#
R-OE#
R13
Figure 13. AC Waveform for PSRAM Read Operations
R1
Vih
Address
Vil
R2
Vih
Vil
R3
R5
R4
P-CS#
R8
Vih
Vil
R-UB#,
R-LB#
R12
R9
Vih
Vil
R-OE#
R7
R11
R6
R10
Voh
Vol
Data
out
High-Z
Valid
Output
High-Z
NOTE: In a read cycle, P-Mode and R-WE# should be fixed to high-level.
Datasheet
35
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 14. AC Waveform for PSRAM 8-Word Page Read Operation
R1
Vih
A3-AMAX
Valid
Vil
Address
Vih
Vil
A0,A1,A2
P-CS#
000
001
111
R2
R3
PR1
R-OE#,
R-UB#,
R-LB#
PR2
R4
R9
Voh
Vol
High-Z
Data out
Qn
Qn+ 7
Qn+
6
NOTE: In a page read cycle, P-Mode and R-WE# should be fixed to high-level, and R-UB#, R-LB# are low-level.
7.5
PSRAM AC Write Specifications
Table 18. PSRAM AC Write Specifications
P-V = 1.80 V to 1.95 V P-V = 2.7 V to 3.1 V
CC
CC
#
Symbol
Parameter
Unit Note
MIN
MAX
MIN
MAX
W1
W2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
85
0
–
65
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
1,4
4
WC
Address Setup Time
–
–
AS
W3
Write Pulse Width
60
30
70
70
0
–
50
35
55
55
0
–
WP
W4
Data valid to Write End
–
–
4
DW
W5
Address valid to end of write
P-CS# to end of write
–
–
4
AW
W6
–
–
4
CW
W7
Data Hold time
–
–
4
DH
W8
Write Recovery
0
–
0
–
4
WR
W9
R-UB#, R-LB# Setup to end of Write
P-CS# high-level pulse width
R-UB#, R-LB# high-level pulse width
R-WE# high-level pulse width
R-OE# high-level to address hold
P-CS# high-level to address hold
R-UB#, R-LB# high-level to address hold
R-OE# high-level to R-WE# set
R-WE# high-level to R-OE# set
70
10
10
10
-5
0
–
55
10
10
10
-5
0
–
4
BW
W10
W11
W12
W13
W14
W15
W16
W17
NOTES:
–
–
1
CP
–
–
BP
–
–
WHP
OHAH
CHAH
BHAH
OES
OEH
–
–
–
–
1
0
–
0
–
1,2
0
10,000
10,000
0
10,000
10,000
3
10
10
1. When W2 ≥ |W14|, |W15| and W10 ≥ 18 ns, W14 and W15 (MIN) are -15 ns. (See also Figure 15, “Conditions for
Calculating the Minimum Value for W14 and W15” on page 37.)
2. W15 is specified from when both R-LB# and R-UB# become high-level.
3. W16 and W17 (MAX) are applied while P-CS# is being hold at low-level.
4. See Figure 16, “AC Waveform for PSRAM Write Operation” on page 37.
36
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 15. Conditions for Calculating the Minimum Value for W14 and W15
W14, W15
Address
R-UB#,R-LB#,
P-CS#
W10
R-WE#
W2
Figure 16. AC Waveform for PSRAM Write Operation
W1
Vih
Address
Vil
W2
W8
Vih
Vil
W6
P-CS#
W5
W9
Vih
Vil
R-UB#,
R-LB#
Vih
Vil
W3
R-WE#
Low-Z
Voh
W4
Valid Data In
W7
High-Z
High-Z
Data I/O
Vol
NOTES:
1. During address transition, at least one of the pins P-CS#, R-WE#, or both of R-UB# and R-LB# pins should
be deasserted.
2. Do not input data to the I/O pins while they are in an output state.
3. In a write cycle, P-Mode and R-OE# should be fixed to high-level.
4. Write operation is done during the overlap time of a low-level P-CS#, R-WE#, R-LB# and/or R-UB#.
Datasheet
37
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 17. PSRAM Mode Register Update—Timing Waveform
R1
R1
W1
W1
Address
Highest Address
Highest Address
Highest Address
Highest Address
Mode Register Setting
P-CS#
R-OE#
W8
W7
W8
W3
W3
R-WE#
W7
W4
W4
Data I/O
0000H
000XH
R-UB#, R-LB#
8.0
Power and Reset Specifications
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
9.0
Design Guide: Operation Overview
9.1
Bus Operations
With F-CE# low and F-RST# high, the flash dies are enabled for normal operations. The flash
device internally decodes upper address inputs to determine the accessed partition or block.
In an asynchronous read operation, addresses are latched when ADV# transition from VIL to VIH,
or continuously flows through if ADV# is held low. In synchronous-burst mode, addresses are
latched by the rising edge of ADV# or the next valid CLK edge when ADV# is low.
Table 19, “Flash + PSRAM + SRAM Bus Operations” summarizes the bus operations and voltage
levels that must be applied to individual flash die in each mode
Note: Each flash die within the 768-Mbit LVQ Family with Asynchronous Static RAM device shares
basic asynchronous read and write operations unless otherwise specified.
38
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Table 19. Flash + PSRAM + SRAM Bus Operations (Sheet 1 of 2)
Synchronous
Array and Non-
Array Read
Flash
DOUT
1,2,3,4
,5,6,9
H
H
H
L
L
L
H
H
H
L
L
H
H
L
Active
L
L
L
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
Asynchronous
Read
Flash
DOUT
1,2,3,4
,5,6,9
Deasserted
Deasserted
VPP1
or
VPP2
Flash
DIN
Write
H
3,4,6
Flash
Output Disable
Standby
H
H
L
L
H
X
H
H
X
H
X
X
H
X
X
High-Z
High-Z
High-Z
X
X
X
High-Z
High-Z
High-Z
4
4
4
High-Z
Flash
High-Z
Any xSRAM mode allowed
Flash
High-Z
Reset
Synchronous
Array and Non-
Array Read
Flash
Die #2
DOUT
1,2,3,4
,5,6,9
H
H
H
H
H
L
H
H
H
H
H
X
L
L
L
L
H
H
L
Deasserted
Deasserted
Deasserted
High-Z
L
L
X
X
H
H
H
X
X
X
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
Flash
Die #2
DOUT
1,2,3,4
,5,6,9
Async Read
Write
Vpp1
or
Vpp2
Flash
Die #2 3,4,6
DOUT
L
H
H
X
X
L
Flash#
2 High-
Z
Output Disable
Standby
L
H
X
X
X
X
X
High-Z
High-Z
High-Z
4
4
4
Flash
#2
High-Z
H
X
High-Z
Any xSRAM mode allowed
Flash
#2
High-Z
Reset
High-Z
PSRAM
DOUT
Read
X
X
H
H
L
L
X
X
X
X
High-Z
High-Z
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
L
L
L
X
1,3
3
PSRAM
DIN
Write
PSRAM
High-Z
Output Disable
H
4
PSRAM
High-Z
Any Flash or SRAM mode allowed
Standby
H
H
H
H
L
H
X
X
X
X
X
X
X
4
4
Low-Power
Mode
PSRAM
High-Z
H
Datasheet
39
768-Mbit LVQ Family with Asynchronous Static RAM
Table 19. Flash + PSRAM + SRAM Bus Operations (Sheet 2 of 2)
SRAM
DOUT
Read
X
X
X
X
X
X
High-Z
High-Z
X
X
X
X
L
L
L
H
H
H
X
X
X
H
H
H
L
H
H
H
L
L
L
1,3,8
3,8
SRAM
DIN
Write
SRAM
High-Z
Output Disable
H
X
3,8
SRAM
High-Z
Any Flash or PSRAM mode allowed
Standby
H
H
X
H
X
X
X
4,8
7,8
SRAM
High-Z
Data Retention
Same as SRAM Standby
NOTES:
1. WAIT is active during sync burst read when F-CE# and OE# are asserted. WAIT is High-Z if F-CE# or OE# is deasserted.
2. FX-CE# is F1-CE# for Flash #1, F2-CE# for Flash #2, and F3-CE# for Flash #3. FX-OE# is F1-OE# for Flash #1, and F2-
OE# for Flash #2.
3. For Flash, FX-OE# and F-WE# should never be asserted simultaneously. For PSRAM or SRAM, R-OE# and R-WE# should
never be asserted simultaneously.
4. X can be VIL or VIH for inputs and VPP1, VPP2, VPPLK or VPPH for F-Vpp.
5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].
6. Refer to Intel Strataflash® Wireless Memory System Datasheet for valid DIN during flash writes.
7. The SRAM can be placed into data retention mode by lowering S-VCC to the VDR limit when in standby mode.
8. P-Mode is high if PSRAM is in Standby. P-Mode is low if PSRAM is in Low-Power Mode. Please see Section 18.0, “PSRAM
Operations” on page 42 for more details on Standby and Low-Power Mode.
9. Data segment flash only operates in asynchronous mode, CLK is ignored and WAIT is deasserted.
9.2
Flash Device Commands and Command Definitions
Refer to the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP), 1024-Mbit LV Family
Datasheet (order number 253854) for complete descriptions of flash modes and commands, for
command bus-cycle definitions, and for flowcharts that illustrate operational routines.
Note: Each flash die within the 768-Mbit LVQ Family with Asynchronous Static RAM device shares
basic asynchronous read and write operations unless otherwise specified.
10.0
11.0
Flash Read Operation
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP);
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Program Operation
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP);
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
40
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
12.0
13.0
14.0
15.0
16.0
17.0
Flash Erase Operation
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP);
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Suspend and Resume Operations
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP);
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Block Locking and Unlocking Operations
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP);
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Protection Register Operation
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP);
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Flash Configuration Operation
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP);
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Dual Operation Considerations
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP);
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Datasheet
41
768-Mbit LVQ Family with Asynchronous Static RAM
18.0
PSRAM Operations
18.1
PSRAM Power-up Sequence and Initialization
The PSRAM functionality and reliability are independent of the power-up slew rate of the core P-
VCC. Any power-up slew rate is possible under use conditions.
The following power-up sequence and operation should be used before starting normal operation.
The PSRAM power-up sequence is represented in Figure 18. At power-up, hold P-Mode low for
the period of tVHMH and transition P-CS# from low to high before transitioning P-Mode to a logical
high. P-CS# and P-Mode must be held high for the period of tMHCL before normal PSRAM
operation is possible once the power up sequence is complete.
Figure 18. Timing Waveform for PSRAM Power-Up Sequence
Initialization
Normal Operation
P-CS#
tMHCL
tCHMH
P-Mode
tVHMH
P-Vcc
Vcc (MIN)
Table 20. PSRAM Initialization Timing
Parameter
Symbol
tVHMH
tCHMH
MIN
MAX
Unit
Power application to P-Mode low-level hold
P-CS# high-level to P-Mode high-level
50
0
–
–
µs
ns
Following power application, P-Mode high-
level hold to P-CS# low-level
tMHCL
200
–
µs
18.2
PSRAM Mode Register
The PSRAM die has an internal register that helps control the Low-Power Mode of the PSRAM.
This register is called the Mode Register. A fraction of the PSRAM array can be enabled for refresh
by setting the Mode Register. Available fixed, partial-refresh fraction densities are 16 Mbit, 8 Mbit,
4 Mbit and 0 Mbit for all density options. Once the refresh density has been set in the Mode
Register, these settings are retained until they are set again while applying the power supply.
However, the Mode Register setting will become undefined if the power is turned off; therefore, it
is important that the Mode Register is set again after power application.
42
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
18.2.1
PSRAM Mode Register Setting
Since the initial value of the PSRAM Mode Register at power application is undefined, the Mode
Register must be set after initialization at power application. When setting the density of partial
refresh, data is not guaranteed before entering the Low-Power Mode. (This is the same for reset.)
However, since Low-Power Mode is not entered unless P-Mode is a logical low, when partial
refresh is not used, it is not necessary to set the Mode Register. Also, when using page read without
using partial refresh, it is not necessary to set the Mode Register.
The PSRAM Mode Register setting can be entered by successively writing two specific data after
two continuous reads of the highest address. The Mode Register setting is a continuous four-cycle
operation: two read cycles and two writes cycles. See Table 21 for setting PSRAM Mode Register
command sequence. Figure 19, “PSRAM Mode Register Setting Flowchart” on page 44 shows the
steps in setting the Mode Register. Figure 17 on page 38 illustrates the timing waveform.
Table 21. Setting PSRAM Mode Register Command Sequence
Command
Sequence
1st Bus Cycle
(Read Cycle)
2nd Bus Cycle
(Read Cycle)
3rd Bus Cycle
(Write Cycle)
4th Bus Cycle
(Write Cycle)
Partial refresh
density
Address
Data
Address
Data
Address
Data
Address
Data
Highest
Address
Highest
Address
Highest
Address
Highest
Address
16-Mbit
8-Mbit
4-Mbit
0-Mbit
—
—
—
—
—
—
—
—
0x00
0x00
0x00
0x00
0x04
0x05
0x06
0x07
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Highest
Address
Datasheet
43
768-Mbit LVQ Family with Asynchronous Static RAM
Figure 19. PSRAM Mode Register Setting Flowchart
START
Read Highest Address
by Toggling both P-CS#
and R-OE#
No
Read Highest Address
by Toggling both P-CS#
and R-OE#
No
No
Write to Highest Address
Data=00H
No
No
No
Fail
Write to Highest Address
Data=xxH
Mode Register
setting exit
Begin Normal
Operation
NOTE: xxH=0x04, 0x05, 0x06 or 0x07
18.2.2
Cautions for Setting PSRAM Mode Register
For the PSRAM Mode Register setting, the internal counter status is judged by toggling P-CS# and
R-OE#. Therefore, toggle P-CS# at every cycle during entry (read cycle twice, write cycle twice),
and toggle R-OE# like P-CS# at the first and second read cycles. If incorrect addresses or data are
written, or are written in an incorrect order, the setting of the PSRAM Mode Register will be set
incorrectly.
When the highest address is read consecutively three or more times, the Mode Register setting
entries are not performed correctly.
Note: Immediately after the highest address is read, the setting of the Mode Register is not performed
correctly.
Perform the setting of the Mode Register after power application or after accessing other than the
highest address.
Once the refresh density has been set in the Mode Register, the setting is retained until it is reset
again while power is continuously applied. However, the Mode Register setting becomes
undefined if the power is turned off. The Mode Register must be reset after any power cycle.
44
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
18.3
PSRAM Low-Power Mode
In addition to the regular Standby mode with a full density data hold, Low-Power Mode performs
partial density data refresh or zero density data refresh.
The Low-Power Mode allows the user to turn off sections of the PSRAM die to save refresh
current. The PSRAM die is divided into four sections allowing certain sections to be refreshed with
P-Mode at a logical-low.
In regular Standby mode, both P-CS# and P-Mode are logical-high. But in Low-Power Mode, P-
Mode is a logical-low. In Low-Power Mode, if 0-Mbit setting is set as the density, it is necessary to
perform initialization the same way as after applying power in order to return to normal operation
from Low-Power Mode. Refer to Figure 18, “Timing Waveform for PSRAM Power-Up Sequence”
on page 42 for timing charts. When the density has been to set to 16 Mbit, 8 Mbit, or 4 Mbit in
Low-Power Mode, it is not necessary to perform initialization to return to normal operation from
Low-Power Mode. Refer to Figure 20, “PSRAM Low-Power Mode Entry/Exit (16-, 8-, 4-, 0-Mbit)
Waveform” for timing charts.
Figure 20. PSRAM Low-Power Mode Entry/Exit (16-, 8-, 4-, 0-Mbit) Waveform
P-Mode
P-CS#
Low Power Mode
(Partial Array Refresh/Zero Refresh)
tCHML
tMHCL1/tMHCL2
Table 22. PSRAM Low-Power Mode Entry/Exit Timing
Parameter
Description
MIN MAX Unit
tCHML
Low-Power Mode entry, P-CS# high-level to P-Mode# low-level
0
–
–
ns
ns
Low-Power Mode (16-, 8-, 4-Mbit hold) exit to normal operation, P-Mode
high-level to P-CS# low-level
1
tMHCL1
30
Low-Power Mode (0-Mbit data hold) exit to normal operation, P-Mode
high-level to P-CS# low-level
2
tMHCL2
200
–
µs
NOTES:
1. tMHCL1 is the time it takes to return to normal operation from Low-Power Mode (data hold: 16-, 8-, 4-Mbit).
2. tMHCL2 is the time it takes to return to normal operation from Low-Power Mode (0-Mbit data hold).
Datasheet
45
768-Mbit LVQ Family with Asynchronous Static RAM
Appendix A Write State Machine
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Appendix B Common Flash Interface
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
Appendix C Flash Flowcharts
Refer to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP;
1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document.
46
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Appendix D Additional Information
:
Order Number
Document
Intel StrataFlash® Wireless Memory System (LV 18/30 SCSP); 1024-Mbit LVX Family
Datasheet
253853
Intel StrataFlash® Wireless Memory System (LV 18/30 SCSP); 1024-Mbit LV Family
Datasheet
253854
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
2. For the most current information on Intel® Flash memory products, software and tools, visit our website at
http://developer.intel.com/design/flash.
S
Datasheet
47
768-Mbit LVQ Family with Asynchronous Static RAM
Appendix E Ordering Information
Figure 21 show the ordering information for the flash + RAM combinations for the 768-Mbit LVQ
Family with Asynchronous Static RAM devices.
Table 23, “Valid-Combination for LVQ Family with Asynchronous Static RAM” on page 49 for
the 768-Mbit LVQ Family with Asynchronous Static RAM devices.
Figure 21. Ordering Information for Flash + RAM Combinations
R D 3 8 F 4 4 2 0 L V Y B Q 0
Device Details
Package
0 = Original version of the products
i.e. for this specific example:
Speed (Code Die):
SCSP Packages:
y
RD = SCSP
y
90 ns async/14 ns sync for
256M flash @ F-VCC = 1.7 V - 2.0 V
85 ns async/14 ns sync for
Lead-Free SCSP Packages:
PF = SCSP
y
y
256M flash @ F-VCC = 1.8 V - 2.0 V
Speed (Data Die):
170 ns async @ F-VCC = 1.7 V - 2.0 V
55 ns tAPA
Flash Process Technology:
0.13 µm ETOX™ VIII Process
Product Line Designator
38F = Flash + xRAM Combination
Package Size:
8 x 11 x 1.4 mm
Flash Density
0 = No die
3 = 128-Mbit
4 = 256-Mbit
Pinout Indicator
RAM Density
0 = No die
Q = QUAD+ ballout
2 = 8-Mbit RAM
4 = 32-Mbit RAM
5 = 64-Mbit RAM
Parameter Location
B = Bottom Parameter
T = Top Parameter
Product Family
LV = Intel StrataFlash® Wireless Flash Memory System (LV18/LV30)
Voltage
Y = 1.8 Volt Core and I/O
Z = 3 Volt I/O, 1.8 Volt Core
48
Datasheet
768-Mbit LVQ Family with Asynchronous Static RAM
Table 23. Valid-Combination for LVQ Family with Asynchronous Static RAM
Package
Size
(mm)
I//O
Flash Components:
RAM Components:
Density (Mbit) & Type
Package Package Valid Order Part
Notes
Voltage Density (Mbit) & Type
Ball Type Type
Number
RD38F4420LVYTQ0
RD38F4420LVYBQ0
256 L18 + 256 V18
8 SRAM
8x11x1.4 Leaded
SCSP
NOTE: For combinations not listed, please contact your local Intel sales representative for details.
Datasheet
49
768-Mbit LVQ Family with Asynchronous Static RAM
50
Datasheet
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