RG82870P2/SL675 [INTEL]
Bus Controller, CMOS, PBGA567;
| 型号： | RG82870P2/SL675 |
| 厂家： | 
INTEL |
| 描述： | Bus Controller, CMOS, PBGA567 |
| 文件： | 总217页 (文件大小：1563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Intel® 82870P2 PCI/PCI-X 64-bit
Hub 2 (P64H2)
Datasheet
January 2003
Document Number: 290732-002
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Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® PCI/PCI-X 64-bit Hub 2 (P64H2) may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
www.intel.com
or call 1-800-548-4725
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2003, Intel Corporation
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Contents
1
Introduction ....................................................................................................................... 17
1.1
1.2
Related Documents.............................................................................................. 17
Intel® P64H2 Overview......................................................................................... 17
2
Signal Description ............................................................................................................. 19
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Hub Interface........................................................................................................ 21
PCI Bus Interface 64-bit Extension ...................................................................... 25
PCI Bus Interface Clocks and Reset.................................................................... 27
Interrupt Interface................................................................................................. 28
Hot Plug Interface................................................................................................. 29
SMBus Interface................................................................................................... 31
Miscellaneous Signals.......................................................................................... 31
Power and Reference Voltage Signals................................................................. 32
Pin Straps............................................................................................................. 32
3
Register Description.......................................................................................................... 34
3.1
3.2
Register Nomenclature and Access Attributes..................................................... 35
Hub Interface-to-PCI Bridge PCI Configuration Registers (Device 31 and 29).... 36
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
VID—Vendor ID Register (D29,31: F0) ................................................ 38
DID—Device ID Register (D29,31: F0)................................................. 38
PD_CMD—PCI Primary Device Command Register (D29,31: F0) ..... 38
PD_STS—PCI Primary Device Status Register (D29,31: F0).............. 40
RID—Revision ID Register (D29,31: F0).............................................. 41
CC—Class Code Register (D29,31: F0)............................................... 41
CLS—Cache Line Size Register (D29,31: F0) ..................................... 42
PMLT—Primary Master Latency Timer Register (D29,31: F0)............ 42
HEADTYP—Header Type Register (D29,31: F0)................................. 42
3.2.10 BNUM—Bus Number Register (D29,31: F0)........................................ 43
3.2.11 SMLT—Secondary Master Latency Timer (D29,31: F0) ...................... 43
3.2.12 IOBL_ADR—I/O Base and Limit Address Register D29,31: F04 ........ 44
3.2.13 SECSTS—Secondary Status Register (D29,31: F0)............................ 44
3.2.14 MBL_ADR—Memory Base and Limit Address Register (D29,31: F0) . 46
3.2.15 PMBL_ADR—Prefetchable Memory Base and Limit Address
Register (D29,31: F0) ........................................................................... 46
3.2.16 PREF_MEM_BASE_UPPER—Prefetchable Memory Base
Upper 32 Bit Address Register (D29,31: F0)........................................ 47
3.2.17 PREF_MEM_LIM_UPPER—Prefetchable Memory Limit
Upper 32 Bit Address Register (D29,31: F0)........................................ 47
3.2.18 IOBLU16_ADR—I/O Base and Limit Upper 16 Bit Address
Register (D29,31: F0) ........................................................................... 47
3.2.19 CAPP—Capabilities List Pointer Register (D29,31: F0) ....................... 48
3.2.20 INTR—Interrupt Information Register (D29,31: F0).............................. 48
3.2.21 BRIDGE_CNT—Bridge Control Register (D31: F0) ............................. 48
3.2.22 CNF—P64H2 Configuration Register (D29,31: F0).............................. 51
3.2.23 MTT—Multi-Transaction Timer Register (D29,31: F0)......................... 52
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3.2.24 STRP—PCI Strap Status Register (D29,31: F0).................................. 52
3.2.25 PX_CAPID—PCI-X Capabilities Identifier Register (D29,31: F0)........ 53
3.2.26 PX_SSTS—PCI-X Secondary Status Register (D29,31: F0) ............... 53
3.2.27 PX_BSTS—PCI-X Bridge Status Register (D29,31: F0)...................... 54
3.2.28 PX_USTC—PCI-X Upstream Split Transaction Control
Register (D29,31: F0) ........................................................................... 55
3.2.29 PX_DSTC—PCI-X Downstream Split Transaction Control
Register (D29,31: F0) ........................................................................... 55
3.2.30 RAS_STS—RAS Status Register (D29,31: F0).................................... 56
3.2.31 RAS_DI—RAS Data Integrity Codes Register (D29,31: F0) ................ 59
3.2.32 RAS_PH—RAS PCI Header Register (D29,31: F0)............................. 59
3.2.33 RAS_PAL—RAS PCI Address Low Register (D29,31: F0) .................. 60
3.2.34 RAS_PAH—RAS PCI Address High Register (D29,31: F0)................. 60
3.2.35 RAS_PDL—RAS PCI Data Low 32 Bits Register (D29,31: F0)........... 60
3.2.36 RAS_PDH—RAS PCI Data High 32 bits Register (D29,31: F0).......... 61
3.2.37 RAS_HH—RAS Hub Interface Header Register (D29,31: F0)............. 61
3.2.38 RAS_HAL—RAS Hub Interface Address Low 32 Bits
Register (D29,31: F0) ........................................................................... 61
3.2.39 RAS_HAH—RAS Hub Interface Address High 32 Bits
Register (D29,31: F0) ........................................................................... 62
3.2.40 RAS_HP—RAS Hub Interface Prefetch Horizon Register (D29,31: F0)62
3.2.41 RAS_D0—RAS Hub Interface DWord 0 Register (D29,31: F0).......... 62
3.2.42 RAS_D1—RAS Hub Interface DWord 1 Register (D29,31: F0).......... 63
3.2.43 RAS_D2—RAS Hub Interface DWord 2 Register (D29,31: F0).......... 63
3.2.44 RAS_D3—RAS Hub Interface DWord 3 Register (D29,31: F0).......... 63
3.2.45 ACNF—Additional P64H2 Configuration Register (D29,31: F0).......... 64
3.2.46 PCC—PCI Delay Compensation Control Register (D29,31: F0)......... 66
3.2.47 HCCR—Hub Interface Command/Control Register (D29,31: F0)....... 67
3.2.48 Prefetch Control Registers.................................................................... 68
3.2.48.1 PC33—Prefetch Control for 33 MHz
Register (D29,31: F0).......................................................... 68
3.2.48.2 PC66—Prefetch Control for 66 MHz
Register (D29,31: F0).......................................................... 68
3.2.48.3 PC100—Prefetch Control for 100 MHz
Register (D29,31: F0).......................................................... 69
3.2.48.4 PC133—Prefetch Control for 133 MHz
Register (D29,31: F0).......................................................... 69
3.3
Hot Plug Controller Registers (Device 31) ........................................................... 70
3.3.1
PCI Configuration Registers ................................................................. 70
3.3.1.1
3.3.1.2
3.3.1.3
3.3.1.4
3.3.1.5
3.3.1.6
3.3.1.7
3.3.1.8
VID—Vendor ID Register (Device 31)................................. 71
DID—Device ID Register (Device 31) ................................. 71
PCICMD—PCI Command Register (Device 31)................. 71
PCISTS—PCI Status Register (Device 31)......................... 72
RID—Revision ID Register (Device 31) .............................. 72
CC—Class Code Register (Device 31) ............................... 73
MBAR—Memory Base Register (Device 31) ...................... 73
MBARU—Memory Base Address (Upper 32-bits)
Register (Device 31)............................................................ 73
SVID—Subsystem Vendor ID Register (Device 31)............ 74
3.3.1.9
3.3.1.10 SID—Subsystem ID Register (Device 31)........................... 74
3.3.1.11 CAP_PTR—Capabilities Pointer Register (Device 31) ....... 74
3.3.1.12 INTR—Interrupt Information Register (Device 31).............. 75
3.3.1.13 SID—Slot ID Register (Device 31) ...................................... 75
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3.3.1.14 HPFC—Hot Plug Frequency Control Register
(Device 31).......................................................................... 75
3.3.1.15 MCNF—Miscellaneous Configuration Register
(Device 31).......................................................................... 76
3.3.1.16 FTR—Features Register (Device 31).................................. 78
3.3.1.17 SSEL—Slot Status Select Register (Device 31) ................. 78
3.3.1.18 SSTS—Slot Status Register (Device 31) ............................ 79
3.3.1.19 SERR—SERR Status Register (Device 31)........................ 80
3.3.1.20 MIDX—Alternate Memory Access Index Port Register
(Device 31).......................................................................... 80
3.3.1.21 MDTA—Alternate Memory Access Data Port Register
(Device 31).......................................................................... 81
3.3.1.22 XID—PCI-X Identifiers Register (Device 31)....................... 81
3.3.1.23 XCR—PCI-X Command Register (Device 31).................... 81
3.3.1.24 XSR—PCI-X Status Register (Device 31)........................... 82
3.3.1.25 ABAR—Alternate Base Register (Device 31)...................... 82
Memory Space Registers ..................................................................... 83
3.3.2
3.3.2.1
3.3.2.2
3.3.2.3
3.3.2.4
3.3.2.5
3.3.2.6
3.3.2.7
3.3.2.8
3.3.2.9
GPT—General Purpose Timer Register ............................. 84
SE—Slot Enable Register ................................................... 84
MCNF—Miscellaneous Configuration Register................... 85
LEDC—LED Control Register ............................................. 87
HMIC—Hot Plug Interrupt Input and Clear Register ........... 88
HMIR—Hot Plug Interrupt Mask Register ........................... 89
SIR—Serial Input Register .................................................. 90
GPO—General Purpose Output Register ........................... 90
HMIN—Hot Plug Non-Interrupt Inputs Register .................. 91
3.3.2.10 SID—Slot ID Register.......................................................... 91
3.3.2.11 SIRE—Switch Interrupt Redirect Enable Register .............. 91
3.3.2.12 SPE—Slot Power Enable Register...................................... 92
3.3.2.13 EMR—Extended Hot Plug Miscellaneous Register............. 93
3.4
I/OxAPIC Interrupt Controller Registers............................................................... 94
3.4.1 PCI Configuration Space Registers (Device 28 and 30)....................... 94
3.4.1.1
3.4.1.2
3.4.1.3
3.4.1.4
3.4.1.5
3.4.1.6
3.4.1.7
3.4.1.8
3.4.1.9
VID—Vendor ID Register (D28,30: F0)............................... 95
DID—Device ID Register (D28,30: F0) ............................... 95
PCICMD—PCI Device Command Register (D28,30: F0) ... 96
PCISTS—PCI Device Status Register (D28,30: F0)........... 97
RID—Revision ID Register (D28,30: F0)............................. 97
CC—Class Code Register (D28,30: F0) ............................. 98
HDR—Header (D28,30: F0)................................................ 98
MBAR—Memory Base Register (D28,30: F0)..................... 98
SS—Subsystem Identifier Register (D28,30: F0)................ 99
3.4.1.10 CAP_PTR—Capabilities Pointer Register (D28,30: F0)...... 99
3.4.1.11 ABAR—Alternate Base Address Register (D28,30: F0)...... 99
3.4.1.12 XID—PCI-X Identifier Register (D28,30: F0)..................... 100
3.4.1.13 XCR—PCI-X Command Register (D28,30: F0)................ 100
3.4.1.14 XSR—PCI-X Status Register (D28,30: F0)....................... 100
Direct Memory Space Registers......................................................... 101
3.4.2
3.4.2.1
3.4.2.2
3.4.2.3
3.4.2.4
IDX—Index Register (D28,30: F0) .................................... 101
WND—Window Register (D28,30: F0) ............................. 101
PAR—IRQ Pin Assertion Register (D28,30: F0) ............... 102
EOI—End of Interrupt Register (D28,30: F0).................... 102
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3.4.3
Indirect Memory Space Registers....................................................... 103
3.4.3.1
3.4.3.2
3.4.3.3
3.4.3.4
3.4.3.5
ID—APIC ID Register (D28,30: F0)................................... 103
VS—Version Register (D28,30: F0) .................................. 104
ARBID—Arbitration ID Register (D28,30: F0) ................... 104
BCFG—Boot Configuration Register (D28,30: F0) ........... 105
RDL—Redirection Table Low DWord Register
(D28,30: F0) ...................................................................... 105
RDH—Redirection Table High Register (D28,30: F0)....... 106
3.4.3.6
3.5
SMBus Interface................................................................................................. 107
3.5.1
3.5.2
CMDSTS—Command / Status Register............................................. 108
BNUM—Bus Number Register........................................................... 109
3.5.2.1
RNUM—Register Number.................................................................. 109
3.5.3.1 DATA—Data Register ....................................................... 110
CFG—SMBus Configuration Register ................................................ 110
DFNUM—Device / Function Number Register.................. 109
3.5.3
3.5.4
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Functional Description .................................................................................................... 112
4.1 PCI Interface ...................................................................................................... 112
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
Summary of Changes......................................................................... 112
Transaction Types .............................................................................. 113
Detection of 64-bit Environment ......................................................... 113
Data Bus............................................................................................. 114
Read Transactions.............................................................................. 115
Configuration Transactions................................................................. 115
Transaction Termination..................................................................... 118
Lock Cycles ........................................................................................ 119
Error Handling..................................................................................... 119
4.1.9.1
4.1.9.2
4.1.9.3
4.1.9.4
4.1.9.5
4.1.9.6
Address Parity Errors ........................................................ 120
Data Parity Errors.............................................................. 121
Hub Interface Configuration Write Transactions............... 121
Read Transactions from Hub Interface Targeting PCI...... 121
Read Transactions from PCI Targeting Hub Interface...... 121
Write Transactions on Hub Interface
(Intel® P64H2 As Hub Interface Target) ............................ 122
Write Transactions on Hub Interface
4.1.9.7
4.1.9.8
4.1.9.9
(Intel® P64H2 As Hub Interface Master)............................ 122
Write Transactions on PCI
(Intel® P64H2 As PCI Target)............................................ 122
Write Transactions on PCI
(Intel® P64H2 As PCI Master) ........................................... 122
4.1.9.10 System Errors.................................................................... 123
4.1.9.11 PCI SERR# Pin Assertion ................................................. 123
4.1.9.12 Other System Errors.......................................................... 123
4.2
PCI-X Interface................................................................................................... 124
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
Command Encoding........................................................................... 124
Attributes............................................................................................. 125
Burst Transactions.............................................................................. 125
Device Select Timing.......................................................................... 125
Wait States ......................................................................................... 126
Split Transactions ............................................................................... 126
4.2.6.1
4.2.6.2
4.2.6.3
Completer Attributes.......................................................... 126
Requirements for Accepting Split Completions................. 126
Split Completion Messages............................................... 126
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4.2.7
4.2.8
4.2.9
Arbitration Among Multiple Split Completions..................................... 127
Transaction Termination as a PCI-X Target....................................... 127
Arbitration ........................................................................................... 127
4.2.10 System Initialization ............................................................................ 128
4.2.11 Bridge Buffer Requirements ............................................................... 129
4.2.12 Cycle Translation Between Interfaces ................................................ 129
4.2.12.1 Conventional PCI to PCI-X / Hub Interface ....................... 129
4.2.12.2 PCI-X to Conventional PCI (peer) / Hub Interface............. 130
4.2.13 Locked Transactions .......................................................................... 130
4.2.14 Error Support ...................................................................................... 130
4.2.15 Transaction Termination Translation Between Interfaces.................. 130
4.2.15.1 Behavior of Hub Interface Initiated Cycles to
PCI/PCI-X Receiving Immediate Terminations ................. 131
4.2.15.2 Behavior of Hub Interface Initiated Cycles to
PCI-X Receiving Split Terminations .................................. 132
4.2.15.3 Hub Interface Action on Immediate Responses to
PCI-X Split Completions.................................................... 133
4.2.16 Configuration Transactions................................................................. 134
4.3
Hot Plug Controllers ........................................................................................... 135
4.3.1
System Architecture............................................................................ 135
4.3.1.1
4.3.1.2
4.3.1.3
4.3.1.4
4.3.1.5
4.3.1.6
4.3.1.7
4.3.1.8
4.3.1.9
Output Control................................................................... 135
Input Control...................................................................... 136
Stutter Mode...................................................................... 136
Serial Input Stream............................................................ 137
Serial Output Stream......................................................... 140
Power Sequencing ............................................................ 143
Arbitration.......................................................................... 146
Power-on and Reset Initialization...................................... 146
PCI Card Initialization........................................................ 147
4.3.1.10 Changing PCI Frequency/Modes ...................................... 147
Pin Multiplexing in Single and Dual Slot Modes.................................. 148
Single Slot Mode PCI Bus Effects ...................................................... 150
4.3.2
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
Driving Bus To Ground When PCI Card is
Disconnected..................................................................... 150
Aborting Outbound PCI Cycles When Card is
Disconnected..................................................................... 151
Special Note on M66EN in Single Slot Mode .................... 151
4.3.4
4.3.5
Generating SCI Instead of Interrupt.................................................... 151
Disabling the Hot Plug Controller........................................................ 151
4.4
Addressing ......................................................................................................... 152
4.4.1
4.4.2
I/O Window Addressing...................................................................... 152
Memory Window Addressing.............................................................. 153
4.4.2.1
4.4.2.2
Memory Base and Limit Address Registers...................... 153
Prefetchable Memory Base and Limit Address
Registers, Upper 32-bit Registers .................................... 153
4.4.3
4.4.4
VGA Addressing ................................................................................. 154
Configuration Addressing ................................................................... 155
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4.5
Transaction Ordering ......................................................................................... 156
4.5.1
4.5.2
4.5.3
4.5.4
Comparison of Rules vs A PCI–PCI Bridge........................................ 156
Ordering Relationships ....................................................................... 156
Hub Interface Fence Special Cycle .................................................... 157
Master Abort / Target Abort Completions on Hub Interface ............... 157
4.5.4.1
4.5.4.2
4.5.4.3
4.5.4.4
Behavior of Hub Interface Initiated Cycles to
PCI/PCI-X Receiving Immediate Terminations ................. 157
Behavior of Hub Interface Initiated Cycles PCI-X
Receiving Split Terminations............................................. 158
Hub Interface Action on Immediate Responses to
PCI-X Split Completions.................................................... 159
Behavior of PCI/PCI-X Initiated Cycles to Hub Interface... 159
4.6
4.7
I/OxAPIC Interrupt Controller (Device 30 and 28).............................................. 160
4.6.1
Interrupt Insertion................................................................................ 160
4.6.1.1
4.6.1.2
Pin Interrupts..................................................................... 160
Message Signaled Interrupts (MSI)................................... 160
4.6.2
Interrupt Delivery................................................................................. 160
4.6.2.1 Front-Side Interrupt Delivery ............................................. 160
4.6.3
4.6.4
Buffer Flushing.................................................................................... 162
Boot Interrupt...................................................................................... 162
SMBus Interface................................................................................................. 163
4.7.1
SMBus Signaling................................................................................. 163
4.7.1.1
4.7.1.2
4.7.1.3
4.7.1.4
4.7.1.5
Waveforms........................................................................ 164
Architecture ....................................................................... 166
Data Transfer Examples ................................................... 168
Configuration Space Registers.......................................... 169
Memory Space Registers.................................................. 169
4.7.2
Configuration Access Arbitration ........................................................ 170
4.8
4.9
System Setup..................................................................................................... 171
4.8.1
4.8.2
Clocking.............................................................................................. 171
Component Reset............................................................................... 172
4.8.2.1
4.8.2.2
4.8.2.3
Software PCI Reset........................................................... 172
RSTIN#.............................................................................. 173
PowerOK........................................................................... 173
4.8.3
I/OxAPIC System Assumptions.......................................................... 174
Reliability, Availability, and Serviceability (RAS)................................................. 175
4.9.1
4.9.2
4.9.3
4.9.4
4.9.5
Error Types......................................................................................... 176
Error Logging...................................................................................... 176
Logged Errors..................................................................................... 178
Allowable Error Combinations for RAS_STS...................................... 178
Data Poisoning ................................................................................... 179
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5
Electrical Characteristics................................................................................................. 180
5.1
DC Voltage and Current Characteristics............................................................ 180
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
Intel® P64H2 DC Characteristics ........................................................ 180
Input Characteristic Signal Association .............................................. 181
DC Input Characteristics..................................................................... 181
DC Characteristic Output Signal Association ..................................... 182
DC Output Characteristics.................................................................. 183
Other DC Characteristics.................................................................... 183
5.1.6.1
5.1.6.2
Hub Interface 2.0 DC Characteristics................................ 184
PCI Interface DC Characteristics
(5 V Signaling Environment).............................................. 185
PCI Interface DC Characteristics
5.1.6.3
(3.3 V Signaling Environment)........................................... 186
PCI-X Interface DC Characteristics................................... 186
PCI Hot Plug DC Characteristics....................................... 187
Input Clock DC Characteristics ......................................... 187
Output Clock DC Characteristics ...................................... 188
5.1.6.4
5.1.6.5
5.1.6.6
5.1.6.7
5.2
AC Characteristics and Timing........................................................................... 189
5.2.1
PCI Interface Timing........................................................................... 189
5.2.1.1
5.2.1.2
PCI Clock Characteristics ................................................. 191
PCI Clock Uncertainty ....................................................... 192
5.2.2
PCI-X Interface Timing ....................................................................... 193
5.2.2.1
5.2.2.2
5.2.2.3
5.2.2.4
PCI-X Clock Characteristics.............................................. 195
PCI-X Clock Uncertainty.................................................... 196
P64H2 Clock Timings........................................................ 197
Spread Spectrum Clocking ............................................... 200
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Ballout and Package Information.................................................................................... 201
6.1 Package Information .......................................................................................... 210
6.1.1 Package Trace Lengths for Hub Interface.......................................... 213
Testability........................................................................................................................ 215
7.1
7.2
7.3
XOR Power Up Strap ......................................................................................... 215
XOR Test Chain Test......................................................................................... 215
Pins Excluded from XOR Chain Testing ............................................................ 217
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Figures
Figure 1. Intel® P64H2 Signal Block Diagram................................................................... 20
Figure 2. Type 1 to Type 0 Translation ........................................................................... 116
Figure 3. Serial Input 6-slot Stutter Mode ....................................................................... 137
Figure 4. Intel P64H2 Appearance to Software .............................................................. 155
Figure 5. Basic SMBus Transfer Waveform ................................................................... 164
Figure 6. Start (S) / Repeat Start (Sr) Signaling ............................................................. 164
Figure 7. Stop (P) Signaling............................................................................................ 164
Figure 8. ACK (A) Signaling............................................................................................ 165
Figure 9. NACK (N) Signaling ......................................................................................... 165
Figure 10. Stack View of SMBus Register Space........................................................... 166
Figure 11. Flow Diagram for SMBus............................................................................... 167
Figure 12. Intel® P64H2 Busy ......................................................................................... 168
Figure 13. Intel® P64H2 Busy ......................................................................................... 168
Figure 14. Reading A Register........................................................................................ 169
Figure 15. 66 MHz PCLK Skew ...................................................................................... 172
Figure 16. PCI Output Timing ......................................................................................... 190
Figure 17. PCI Input Timing............................................................................................ 190
Figure 18. PCI Clock Waveforms ................................................................................... 191
Figure 19. PCI Clock Skew............................................................................................. 192
Figure 20. PCI-X Output Timing...................................................................................... 194
Figure 21. PCI-X Input Timing ........................................................................................ 194
Figure 22. PCI-X 3.3 V Clock Waveform ........................................................................ 195
Figure 23. PCI-X Clock Skew ......................................................................................... 196
Figure 24. Intel® P64H2 Ballout (Left Side)..................................................................... 202
Figure 25. Intel® P64H2 Ballout (Right Side) .................................................................. 203
Figure 26. 567-Ball FCBGA Package Dimensions (Top View)....................................... 210
Figure 27. 567-Ball FCBGA Package Dimensions (Bottom View).................................. 211
Figure 28. 567-Ball FCBGA Solder Balls Detail.............................................................. 212
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Tables
Table 1. Hub Interface ...................................................................................................... 21
Table 2. PCI Bus Interface A Signals................................................................................ 21
Table 3. PCI Bus Interface B Signals................................................................................ 23
Table 4. PCI Bus Interface 64-bit Extension Interface A Signals...................................... 25
Table 5. PCI Bus Interface 64-bit Extension Interface B Signals...................................... 26
Table 6. PCI Bus Interface Clocks and Reset Interface A Signals ................................... 27
Table 7. PCI Bus Interface Clocks and Reset Interface B Signals ................................... 27
Table 8. Interrupt Interface Signals................................................................................... 29
Table 9. Hot Plug Interface A Signals............................................................................... 29
Table 10. Hot Plug Interface B Signals............................................................................. 30
Table 11. SMBus Interface Signals................................................................................... 31
Table 12. Miscellaneous Signals ...................................................................................... 31
Table 13. Power and Reference Voltage Signals ............................................................. 32
Table 14. Normal Functional Pin Straps ........................................................................... 32
Table 15. Hub Interface-to-PCI Bridges Address Map (D31,29, F0) ................................ 36
Table 16. Hot Plug Controller PCI Configuration Address Map (Device 31)..................... 70
Table 17. Hot Plug Controller Memory Space Register Map............................................ 83
Table 18. I/OxAPIC PCI Configuration Space Register Map............................................ 94
Table 19. I/OxAPIC Memory Space Register Map ......................................................... 101
Table 20. I/OxAPIC Indirect Memory Space Register Address Map .............................. 103
Table 21. SMBus Register Address Map........................................................................ 107
Table 22. Intel® P64H2 PCI Transactions....................................................................... 113
Table 23. Command Encoding ....................................................................................... 124
Table 24. Intel® P64H2 Implementation of Requester Attribute Fields .......................... 125
Table 25. DEVSEL# Timing............................................................................................ 125
Table 26. Intel® P64H2 Implementation Completion Attribute Fields.............................. 126
Table 27. Split Completion Abort Registers.................................................................... 126
Table 28. M66EN and PCIXCAP Encoding .................................................................... 128
Table 29. PCI-X Initialization Pattern .............................................................................. 128
Table 30. Conventional PCI to PCI-X / Hub Interface..................................................... 129
Table 31. PCI-X to Conventional PCI (peer) / Hub Interface.......................................... 130
Table 32. Immediate Terminations of Completion Required Cycles to PCI/PCI-X......... 131
Table 33. Immediate Terminations of Posted Write Cycles to PCI/PCI-X...................... 131
Table 34. Split Terminations of Completion Required Cycles to PCI-X.......................... 132
Table 35. Response to PCI-X Split Completions ............................................................ 133
Table 36. Terminations of Completion Requited Cycles to Hub Interface...................... 133
Table 37. Stutter Logic Modes........................................................................................ 136
Table 38. Shift Register Data.......................................................................................... 140
Table 39. Serial Mode Output Shift-Out SR Bit Order .................................................... 142
Table 40. Power Up Timings (CBF Mode)...................................................................... 143
Table 41. Power Down Timings (CBF Mode) ................................................................. 144
Table 42. Power Up Timings (CBL Mode) ...................................................................... 145
Table 43. Power Down Timings (CBL Mode).................................................................. 146
Table 44. Registers Not Reset with a Secondary Bus Reset.......................................... 146
Table 45. Hot Plug Mode Settings .................................................................................. 148
Table 46. Hot Plug Mode Signals.................................................................................... 149
Table 47. Hot Plug Mode Reset Values.......................................................................... 149
Table 48. PCI Functions/Devices Table.......................................................................... 155
Table 49. Ordering Rules for a PCI-PCI Bridge.............................................................. 156
Table 50. Immediate Terminations of Completion Required Cycles to PCI/PCI-X......... 157
Intel® 82870P2 P64H2 Datasheet
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Table 51. Immediate Terminations of Posted Write Cycles to PCI/PCI-X...................... 158
Table 52. Split Terminations of Completion Required Cycles to PCI-X.......................... 158
Table 53. Hub Interface Response to PCI-X Split Completion Terminations of
Completion Required Cycles ................................................................................... 159
Table 54. Terminations of Completion Required Cycles to Hub Interface...................... 159
Table 55. System Bus Delivery Address Format ............................................................ 161
Table 56. System Bus Delivery Data Format.................................................................. 161
Table 57. SMBus Address Configuration........................................................................ 163
Table 58. P64H2 Clocking .............................................................................................. 171
Table 59. Determining PCI/PCI-X Bus Frequency.......................................................... 173
Table 60. Hot Plug Mode and Final Bus State................................................................ 173
Table 61. RAS_STS Register (offset 60h) Values.......................................................... 179
Table 62. Intel® P64H2 DC Voltage Characteristics ....................................................... 180
Table 63. Intel® P64H2 DC Current Characteristics ....................................................... 180
Table 64. DC Characteristics Input Signal Association .................................................. 181
Table 65. DC Input Characteristics................................................................................. 181
Table 66. DC Characteristic Output Signal Association ................................................. 182
Table 67. DC Output Characteristics.............................................................................. 183
Table 68. Other DC Characteristics................................................................................ 183
Table 69. DC Characteristics for Hub Interface Common Clock Signaling .................... 184
Table 70. DC Characteristics for Hub Interface Source Synchronous Signaling............ 185
Table 71. DC Characteristics for PCI 5 V Signaling........................................................ 185
Table 72. DC Characteristics for PCI 3.3 V Signaling..................................................... 186
Table 73. DC Characteristics for PCI-X.......................................................................... 186
Table 74. PCI Hot Plug Slot Power Requirements ......................................................... 187
Table 75. DC Characteristics for Input Clock Signals..................................................... 187
Table 76. DC Characteristics for Output Clock Signals.................................................. 188
Table 77. PCI Interface Timing (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%, Tcase=0°C to
105°C)...................................................................................................................... 189
Table 78. PCI Clock Characteristics (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0 °C to 105 °C)............................................................................................. 191
Table 79. PCI Clock Skew Parameters (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0°C to 105°C)............................................................................................... 192
Table 80. PCI-X General Timing Parameters (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0°C to 105°C)............................................................................................... 193
Table 81. PCI-X Clock Timings (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%, Tcase=0°C to
105°C)...................................................................................................................... 195
Table 82. PCI-X Clock Uncertainty Parameters (HI_VREF = 5 V + 5%, VCC = 3.3 V
+ 5%, Tcase=0°C to 105°C) .................................................................................... 196
Table 83. P64H2 Clock Timings (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%, Tcase=0°C to
105°C)...................................................................................................................... 197
Table 84. Intel® P64H2 Ballout Listed Alphabetically by Signal Name............................ 204
Table 85. Intel® P64H2 Hub Interface Package Trace Lengths...................................... 213
Table 86. XOR Power Up Strap (Sampled during RESET)............................................ 215
Table 87. XOR Chain Table (Chains 1–6) ...................................................................... 215
Table 88. Pins Excluded from XOR Chain Testing......................................................... 217
12
Intel® 82870P2 P64H2 Datasheet
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Revision History
Revision
Description
Date
-001
-002
Initial Release.
Incorporated changes from P64H2 Spec Update Rev 001-007
February 2002
January 2003
Intel® 82870P2 P64H2 Datasheet
13
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14
Intel® 82870P2 P64H2 Datasheet
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Intel® 82870P2 P64H2 Features
Primary bus (the Hub Interface)
Hot Plug Controller
ꢀ
ꢀ
16 bit data interface
8x clock modes
64-bit and 32-bit addressing support
Parity/ECC Support
66 MHz base clock
1 interface per PCI bus segment
Parallel support for 1 and 2 slot systems,
updates for PCI-X support.
Buffer Architecture (per interface)
ꢀ
4 KB of data, split into four 1024-byte
buffers, for inbound read requests from
PCI / PCI-X agents.
Parallel Termination
Secondary bus (2 PCI Bus Interfaces)
ꢀ
1.5 KB for inbound write transactions.
128 bytes for outbound read completions
16 outbound commands for completions and
requests.
16 inbound commands (posted and non-
posted)
PCI Specification, Revision 2.2 compliant
PCI-PCI Bridge Specification, Revision 1.1
compliant
PCI-X Specification, Revision 1.0 compliant
66 MHz 64bit, 3.3 V PCI bus (5 V Tolerant)
6 REQ/GNT per PCI bus segment (Internal
arbiter only)
Decoupled operation from Hub interface
64 bit addressing for inbound and outbound
transactions
I/O APIC
ꢀ
1 interface per PCI bus segment
Supports up to 24 interrupts (16 pins) per
interface
Serial interface for future PCG product
Compatible with both IA-32 and IA-64
Boot interrupt output
Supports outbound LOCK# cycles
Fast Back-to-Back capable Bus parking on
Hub Interface
Bus parking on last PCI agent
Test/Debug
ꢀ
Pilot Mode to monitor internals
Head-to-Head Mode to test two P64H2s tied
together with no MCH
Up to 4 active and 4 pending inbound
delayed transactions, and 1 outbound
delayed transaction per interface
Fair arbitration algorithm between each PCI
interface for ownership of Hub Interface
based upon the maximum bandwidth
requirements on each interface
PCI Bus B (with APIC B and Hot Plug
Controller B) can be hidden for a product
sku via a fuse
Other features
ꢀ
Peer-to-peer memory writes between PCI
segments with fence ordering
Trapping of address / command for first
cycle with parity/ECC errors.
Parity protection of SRAM data
SMBus Interface
ꢀ
Full read/write access to all Configuration
and Memory registers
No accesses to PCI bus or Hub Interface
Intel® 82870P2 P64H2 Datasheet
15
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Intel® 82870P2 P64H2 System Block Diagram
Processor
Processor
System Bus
8-Bit HI1.5
266 MB/s
System
Memory
Intel®
ICH3-S
MCH
16-Bit Hub
Interface
(1 GB/s)
16-Bit Hub
Interface
(1 GB/s)
16-Bit Hub
Interface
(1 GB/s)
Intel®
P64H2
P64H2
P64H2
PCI
or
PCI-X
PCI
or
PCI-X
PCI
or
PCI-X
PCI
or
PCI-X
PCI
or
PCI-X
PCI
or
PCI-X
PC
I
PC
I
PC
I
PC
I
PC
I
PC
I
Slo
t
Slo
t
Slo
t
Slo
t
Slo
t
Slo
t
Note: The two P64H2 secondary PCI buses can be independently
configured as either PCI or PCI-X buses (66 MHz to 133 MHz).
Sys_Blk
16
Intel® 82870P2 P64H2 Datasheet
Introduction
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1 Introduction
The Intel® 82870P2 PCI/PCI-X 64 Hub 2 (P64H2) is a peripheral chip that performs PCI bridging
functions between hub interface and the PCI Bus. On the primary bus, the P64H2 utilizes a 16-bit
data bus to interface with the hub interface, and on the secondary bus the P64H2 supports two
64-bit PCI bus interfaces. Either one of the secondary PCI bus interfaces can be configured to
operate in PCI or PCI-X mode. Each PCI interface contains an I/O APIC with 24 interrupts and a
hot plug controller supporting each PCI bus segment.
1.1
Related Documents
Document
Doc Number / Location
PCI Local Bus Specification, Revision 2.0
http://www.pcisig.com/specifications
/conventional_pci
PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0
PCI Hot Plug Specification, Revision 1.0
http://www.pcisig.com/specifications
/pci_x
http://www.pcisig.com/specifications
/pci_hot_plug
PCI-to-PCI Bridge Architecture Specification, Revision 1.1
System Management Bus (SMBus) Specification, Revision 2.0
http://www.pcisig.com/specifications
/pci_to_pci_bridge_architecture
http://www.smbus.org/specs/
1.2
Intel® P64H2 Overview
Primary Bus (the Hub Interface)
The Primary bus is the hub interface between the MCH and P64H2. This 16-bit data interface
provides support for 32-bit and 64-bit addressing. The base clock is 66 MHz.
Secondary Bus (2 PCI Bus Interfaces)
The P64H2 has two PCI Bus interfaces (PCI Bus A and PCI Bus B). In this document these buses
are referred to as the secondary buses. These interfaces can be independently configured as either
a PCI Bus or PCI-X Bus. PCI Bus extensions are also provided. There is 64-bit addressing
outbound, with the capability to assert DAC. Full 64 bit addressing inbound is supported. The
inbound packet size is based on the cache line size of the platform.
I/O space can be programmed to 1 KB granularity. If inbound reads are retried, they will be moved
to the side so that posted writes and completion packets can pass. I/O reads and writes on PCI will
no longer be forwarded to the hub interface, nor will they be forwarded to the other PCI interface.
Intel® 82870P2 P64H2 Datasheet
17
Introduction
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The PCI Bus interface is compliant with the PCI Local Bus Specification, Revision 2.2. The PCI-X
interface is compliant with the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0.
PCI-X provides enhancements over PCI that enable faster and more efficient data transfers. For
PCI Mode, the P64H2 supports PCI bus frequencies of 33 MHz and 66 MHz. For the PCI-X
mode, the P64H2 supports PCI bus frequencies of 66 MHz, 100 MHz, and 133 MHz. Four PCI
bus slots are supported at 33 MHz and 66 MHz, two slots are supported at 100 MHz, and one slot
is supported at 133 MHz.
Hot Plug Controller
The P64H2 hot plug controller allows PCI card removal, replacement, and addition without
powering down the system. The P64H2 hot plug controller resides in Function 0 of the secondary
bus device 31. It supports three to six PCI slots through an input/output serial interface when
operating in Serial Mode, and one to two slots through an input/output parallel interface when
operating in Parallel Mode. The input serial interface is polling and is in continuous operation. The
output serial interface is “demand” and acts only when requested. These serial interfaces run at
about 8.25 MHz regardless of the speed of the PCI bus. In parallel mode, the P64H2 performs the
serial-to-parallel conversion internally, so the serial interface cannot be observed. However,
internally the hot plug controller always operates in a serial mode.
I/O APIC
The P64H2 contains two I/O APIC controllers (I/OxAPIC where x=A or B), both of which reside
on the primary bus. The intended use of these controllers is to have the interrupts from PCI Bus A
connected to the interrupt controller on device 28, and have the interrupts on PCI Bus B connected
to the interrupt controller on device 30.
SMBus Interface
The System Management Bus (SMBus) is a two-wire interface through which various system
devices (e.g., the P64H2) can communicate with each other and with the rest of the system. It is
based on the principles of I2C.
The SMBus controller has access to all internal registers. It can perform reads and writes from all
registers through the particular interface’s configuration space. Hot plug and I/O APIC memory
spaces are accessible through their respective configuration spaces. The reason for the SMBus
interface is to access registers when the system may be unstable or locked, which can result with
broken queues. Any register access through SMBus must be able to proceed while the system is
stuck.
18
Intel® 82870P2 P64H2 Datasheet
Signal Description
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2 Signal Description
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when
the signal is at a low voltage level. When “#” is not present after the signal name the signal is
asserted when at the high voltage level.
Note: Some interfaces are divided into Interface A and Interface B. In these cases the signal names use
the letter “A” or “B” to signify the interface (interface A or interface B). For example, in the PCI
Bus interface, PAAD[31:0] refer to the AD bus signals on PCI Bus A and PBAD[31:0] refer to the
AD bus signals on PCI Bus B. When a description applies to both interface A and interface B, a
lower case “x” may be used in the signal name (e.g., PxAD[31:0]).
The following notations are used to describe the signal type:
P
Power pin
I
Input pin
O
I/O
Output pin
Bi-directional Input/Output pin
Intel® 82870P2 P64H2 Datasheet
19
Signal Description
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Figure 1. Intel® P64H2 Signal Block Diagram
CLK66
CLK200 / CLK200#
HI_[21:0]
PBAD[31:0]
PBC/BE[3:0]#
PBPAR
PBDEVSEL#
PBFRAME#
PBIRDY#
PBTRDY#
PBSTOP#
PBPERR#
PBSERR#
PSTRBF
Hub
Interface
PSTRBS
PUSTRBF
PUSTRBS
HI_RCOMP
HI_VREF
PCI
B
HI_VSWING
PBREQ[5:0]#
PBGNT[5:0]#
PBM66EN
PB_133EN
PBPCIXCAP
PBPLOCK#
PAAD[31:0]
PAC/BE[3:0]#
PAPAR
PADEVSEL#
PAFRAME#
PAIRDY#
PBAD[63:32]
PBC/BE[7:4]#
PBPAR64
PBREQ64#
PBACK64#
PATRDY#
PASTOP#
PAPERR#
PASERR#
PCI
A
PCI Bus
Interface
B
(64-Bit
Expansion)
PAREQ[5:0]#
PAGNT[5:0]#
PAM66EN
PA_133EN
PAPCIXCAP
PAPLOCK#
PCI Bus
Interface
B
(Clocks and
Reset)
PBPCLKO[6:0]
PBPCLKI
PBPCIRST#
PAAD[63:32]
PAC/BE[7:4]#
PAPAR64
PAREQ64#
PAACK64#
PCI Bus
Interface
A
(64-Bit
Expansion)
HPB_SIC
HPB_SIL#
HPB_SID
HPB_SOR#
HPB_SORR#
HPB_SOC
HPB_SOL
HPB_SOLR
HPB_SOD
HPB_SLOT[2:0]
Hot Plug
Interface
B
PAPCLKO[6:0]
PAPCLKI
PCI Bus
Interface
A
(Clocks and
Reset)
PAPCIRST#
BPCLK100
BPCLK133
HPA_SIC
HPA_SIL#
HPA_SID
SDTA
SCLK
SMBus
Interface
HPA_SOR#
HPA_SORR#
HPA_SOC
HPA_SOL
HPA_SOLR
HPA_SOD
PAIRQ[15:0]
PBIRQ[15:0]
BT_INTR#
APICCLK
Hot Plug
Interface
A
Interrupt
Interface
APICD[1:0]
HPA_SLOT[2:0]
RASERR#
TEST#
RSTIN#
PWROK
TPO
Misc.
Signals
blk_p64h2
20
Intel® 82870P2 P64H2 Datasheet
Signal Description
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2.1
Hub Interface
Table 1. Hub Interface
Signal
Type
Description
CLK66
I
Hub Interface Clock In: This is a 66 MHz clock input.
200 MHz Differential Clock Input: This clock pair is a 200 MHz clock
input.
CLK200/CLK200#
HI_[21:0]
I
I/O
I/O
Hub Interface Signals:
Hub Interface Strobe: One of two differential strobe signal pairs used to
transmit and receive lower data packet over the hub interface.
PSTRBF
Hub Interface Strobe Complement: One of two differential strobe signal
pairs used to transmit and receive lower data packet over the hub interface.
PSTRBS
I/O
I/O
Hub Interface Upper Strobe: One of two differential strobe signal pairs
used to transmit and receive upper data packet over the hub interface.
PUSTRBF
Hub Interface Upper Strobe Complement: One of two differential strobe
signal pairs used to transmit and receive upper data packet over the hub
interface.
PUSTRBS
I/O
HI_RCOMP
HI_VREF
I/O
Hub Interface Compensation: Used for I/O buffer compensation.
Hub Interface Reference Voltage: See Section 2.8.
I
I
HI_VSWING
Hub Interface Reference Swing Voltage: See Section 2.8.
Table 2. PCI Bus Interface A Signals
Signal
Type
Description
PCI Address/Data: These signals are a multiplexed address and data bus.
During the address phase or phases of a transaction, the initiator drives a
physical address on PAAD[31:0]. During the data phases of a transaction, the
initiator drives write data, or the target drives read data.
PAAD[31:0]
I/O
Bus Command and Byte Enables: These signals are a multiplexed command
field and byte enable field. During the address phase or phases of a transaction,
the initiator drives the transaction type on PAC/BE[3:0]#. For both read and
write transactions, the initiator drives byte enables on PAC/BE[3:0]# during the
data phases.
PAC/BE[3:0]#
PAPAR
I/O
I/O
Parity: Even parity calculated on 36 bits (PAAD[31:0] plus PAC/BE[3:0]#). It is
calculated on all 36 bits, regardless of the valid byte enables. It is driven
identically to the PAAD[31:0] lines, except it is delayed by exactly one PCI
clock.
Device Select: The Intel® P64H2 asserts PADEVSEL# to claim a PCI
transaction. As a target, the P64H2 asserts PADEVSEL# when a PCI master
peripheral attempts an access to an internal address or an address destined for
the hub interface. As an initiator, PADEVSEL# indicates the response to a
P64H2-initiated transaction on the PCI bus. PADEVSEL# is tri-stated from the
leading edge of PCIRST#. PADEVSEL# remains tri-stated by the P64H2 until
driven as a target.
PADEVSEL#
PAFRAME#
I/O
I/O
Frame: FRAME# is driven by the Initiator to indicate the beginning and duration
of an access. While PAFRAME# is asserted, data transfers continue. When
FRAME# is negated, the transaction is in the final data phase.
Intel® 82870P2 P64H2 Datasheet
21
Signal Description
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Signal
Type
Description
Initiator Ready: PAIRDY# indicates the ability of the initiator to complete the
current data phase of the transaction. A data phase is completed when both
PAIRDY# and PATRDY# are sampled asserted.
PAIRDY#
I/O
Target Ready: PATRDY# indicates the ability of the target to complete the
current data phase of the transaction. A data phase is completed when both
PATRDY# and PAIRDY# are sampled asserted. PATRDY# is tri-stated from the
leading edge of PCIRST#. PATRDY# remains tri-stated by the P64H2 until
driven as a target.
PATRDY#
I/O
Stop: PASTOP# indicates that the target is requesting an initiator to stop the
current transaction.
PASTOP#
PAPERR#
I/O
I/O
Parity Error: PAPERR# is driven by an external PCI device when it receives
data that has a parity error. Driven by the P64H2 when, as an initiator it detects
a parity error during a read transaction and as a target during write transactions.
System Error: PASERR# can be pulsed active by any PCI device that detects
a system error condition except the P64H2. The P64H2 samples PASERR# as
an input and conditionally forwards it to the hub interface.
PASERR#
I
I
PCI Requests: PAREQ[5:0]# supports up to six masters on the PCI bus. The
P64H2 accepts six request inputs, PAREQ[5:0]# into its internal bus arbiter. The
P64H2 request input to the arbiter is an internal signal.
PAREQ[5:0]#
PCI Grants: PAGNT[5:0]# supports up to six masters on the PCI bus. The
arbiter can assert one of the six bus grant outputs, to indicate that an initiator
can start a transaction on the PCI Bus.
PAGNT[5:0]#
O
PAGNT [3] - 66/200 MHz Clocking Strap: When this pin is sampled high (logic
1) on PWROK, the P64H2 uses the 200 MHz differential clock. When this pin is
sampled low (logic 0) on PWROK, the P64H2 uses the 66 MHz clock input.
66 MHz Enable: This input signal from the PCI Bus indicates the speed of the
PCI Bus. If it is high, the bus speed is 66 MHz; if it is low, the bus speed is
33 MHz. This signal will be used to generate the appropriate clock (33 MHz or
66 MHz) on the PCI Bus.
If Hot plug is enabled, the PCI bus will power-up as 33 MHz PCI and the P64H2
will drive this pin low. Also, if software ever writes 00 to the PFREQ Register,
the P64H2 will drive this pin low.
PAM66EN
I/O
If Hot plug is not enabled at power-up or if software never writes 00 to the
PFREQ Register, the P64H2 tri-states this pin. Additionally, if the hot plug mode
is single slot with no glue, the P64H2 tri-states this pin, regardless of the setting
of the PFREQ Register. The system board will pull this pin to a logic 1.
Enable PCI-X at 133 MHz for PCI Bus A: This pin, when high, allows the
PCI-X segment to run at 133 MHz when PA_PCIXCAP is sampled high. When
low, the PCI-X segment will only run at 100 MHz when PA_PCIXCAP is
sampled high.
PA_133EN
PAPCIXCAP
PAPLOCK#
I
I
PCI-X Capable: This signal indicates whether all devices on the PCI bus are
PCI-X devices, so that the P64H2 can switch into PCI-X mode.
PCI Lock: This signal indicates an exclusive bus operation and may require
multiple transactions to complete. The P64H2 asserts PLOCK# when it is doing
exclusive transactions on PCI. PLOCK# is ignored when PCI masters are
granted the bus. The P64H2 does not propagate locked transactions upstream.
O
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Intel® 82870P2 P64H2 Datasheet
Signal Description
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Table 3. PCI Bus Interface B Signals
Signal
Type
Description
PCI Address/Data: These signals are a multiplexed address and data bus.
During the address phase or phases of a transaction, the initiator drives a
physical address on PBAD[31:0]. During the data phases of a transaction, the
initiator drives write data, or the target drives read data.
PBAD[31:0]
I/O
Bus Command and Byte Enables: These signals are a multiplexed command
field and byte enable field. During the address phase or phases of a
transaction, the initiator drives the transaction type on PBC/BE[3:0]#. For both
read and write transactions, the initiator drives byte enables on PBC/BE[3:0]#
during the data phases.
PBC/BE[3:0]#
PBPAR
I/O
I/O
Parity: Even parity calculated on 36 bits (AD[31:0] plus PBC/BE[3:0]#). It is
calculated on all 36 bits, regardless of the valid byte enables. It is driven
identically to the PBAD[31:0] lines, except it is delayed by exactly one PCI
clock.
Device Select: The Intel® P64H2 asserts PBDEVSEL# to claim a PCI
transaction. As a target, the P64H2 asserts PBDEVSEL# when a PCI master
peripheral attempts an access to an internal address or an address destined
for the hub interface. As an initiator, PBDEVSEL# indicates the response to a
P64H2-initiated transaction on the PCI bus. PBDEVSEL# is tri-stated from the
leading edge of PCIRST#. PBDEVSEL# remains tri-stated by the P64H2 until
driven as a target.
PBDEVSEL#
I/O
Frame: PBFRAME# is driven by the Initiator to indicate the beginning and
duration of an access. While PBFRAME# is asserted, data transfers continue.
When PBFRAME# is negated, the transaction is in the final data phase.
PBFRAME#
PBIRDY#
I/O
I/O
Initiator Ready: PBIRDY# indicates the ability of the initiator to complete the
current data phase of the transaction. A data phase is completed when both
PBIRDY# and PBTRDY# are sampled asserted.
Target Ready: PBTRDY# indicates the ability of the target to complete the
current data phase of the transaction. A data phase is completed when both
PBTRDY# and PBIRDY# are sampled asserted. PBTRDY# is tri-stated from
the leading edge of PCIRST#. PBTRDY# remains tri-stated by the P64H2 until
driven as a target.
PBTRDY#
I/O
Stop: PBSTOP# indicates that the target is requesting an initiator to stop the
current transaction.
PBSTOP#
PBPERR#
I/O
I/O
Parity Error: PBPERR# is driven by an external PCI device when it receives
data that has a parity error. It is driven by the P64H2 when, as an initiator it
detects a parity error during a read transaction and as a target during write
transactions.
System Error: PBSERR# can be pulsed active by any PCI device that detects
a system error condition except the P64H2. The P64H2 samples PBSERR# as
an input and conditionally forwards it to the hub interface.
PBSERR#
I
I
PCI Requests: PBREQ[5:0]# supports up to six masters on the PCI bus. The
P64H2 accepts six request inputs into its internal bus arbiter. The P64H2
request input to the arbiter is an internal signal.
PBREQ[5:0]#
PCI Grants: PBGNT[5:0]# supports up to six masters on the PCI bus. The
arbiter can assert one of the six bus grant outputs to indicate that an initiator
can start a transaction on the PCI bus.
PBGNT[5:0]#
O
Intel® 82870P2 P64H2 Datasheet
23
Signal Description
R
Signal
Type
Description
66 MHz Enable: This input signal from the PCI bus indicates the speed of the
PCI bus. If it is high then the bus speed is 66 MHz and if it is low, the bus
speed is 33 MHz. This signal will be used to generate the appropriate clock
(33 MHz or 66 MHz) on the PCI bus.
If Hot plug is enabled, the PCI bus will power-up as 33 MHz PCI and the
P64H2 will drive this pin low. Also, if software writes 00 to the PFREQ Register,
the P64H2 will drive this pin low.
PBM66EN
I/O
If Hot plug is not enabled at power-up or if software never writes 00 to the
PFREQ Register, the P64H2 tri-states this pin. Additionally, if the hot plug
mode is single slot with no glue, the P64H2 tri-states this pin, regardless of the
setting of the PFREQ Register. The system board will pull this pin to a logic 1.
Enable PCI-X at 133MHz for PCI Bus B: This pin, when high, allows the
PCI-X segment to run at 133 MHz when PBPCIXCAP is sampled high. When
low, the PCI-X segment will only run at 100 MHz when PBPCIXCAP is sampled
high.
PB_133EN
I
I
PCI-X Capable: Indicates whether all devices on the PCI bus are PCI-X
devices, so that the P64H2 can switch into PCI-X mode.
PBPCIXCAP
PCI Lock: This signal indicates an exclusive bus operation and may require
multiple transactions to complete. The P64H2 asserts PLOCK# when it is
doing exclusive transactions on PCI. PLOCK# is ignored when PCI masters
are granted the bus. The P64H2 does not propagate locked transactions
upstream.
PBPLOCK#
O
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Intel® 82870P2 P64H2 Datasheet
Signal Description
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2.2
PCI Bus Interface 64-bit Extension
There are two sets of PCI Bus extension signals; one for PCI Bus A and one for PCI Bus B.
Table 4. PCI Bus Interface 64-bit Extension Interface A Signals
Signal
Type
Description
PCI Address/Data: These signals are a multiplexed address and data bus. This
bus provides an additional 32 bits to the PCI bus. During the data phases of a
transaction, the initiator drives the upper 32 bits of 64-bit write data, or the
target drives the upper 32 bits of 64-bit read data, when PAREQ64# and
PAACK64# are both asserted. When not driven, PAAD[63:00] are pulled up to a
valid logic level through external resistors. For a 5 V environment use a 2.7 kΩ
resistor, in a 3.3 V environment use an 8.2 KΩ resistor.
PAAD[63:32]
I/O
Bus Command and Byte Enables (Upper 4 bits): These signals are a
multiplexed command field and byte enable field. For both read and write
transactions, the initiator will drive byte enables for the PAAD[63:32] data bits
on PAC/BE[7:4]# during the data phases when PAREQ64# and PAACK64# are
both asserted.
PAC/BE[7:4]#
I/O
I/O
When not driven, PAC/BE[7:4]# is pulled up to a valid logic level through
external resistors. In a 5 V environment use a 2.7 kΩ resistor; in a 3.3 V
environment use a 8.2 kΩ resistor
PCI Interface Upper 32-bits Parity: This signal carries the even parity of the
36 bits of PAAD[63:32] and PAC/BE[7:4]# for both address and data phases.
When not driven, PAPAR64 is pulled up to a valid logic level through external
resistors.
PAPAR64
PCI interface Request 64-bit Transfer: This signal is asserted by the initiator
to indicate that the initiator is requesting a 64-bit data transfer. It has the same
timing as PAFRAME#. When the Intel® P64H2 is the initiator, this signal is an
output. When the P64H2 is the target, this signal is an input.
PAREQ64#
PAACK64#
I/O
I/O
PCI Interface Acknowledge 64-bit Transfer: This signal is asserted by the
target only when PAREQ64# is asserted by the initiator. It indicates the target’s
ability to transfer data using 64 bits. It has the same timing as PADEVSEL#.
Intel® 82870P2 P64H2 Datasheet
25
Signal Description
R
Table 5. PCI Bus Interface 64-bit Extension Interface B Signals
Signal
Type
Description
PCI Address/Data: These signals are a multiplexed address and data bus. This
bus provides an additional 32 bits to the PCI bus. During the data phases of a
transaction, the initiator drives the upper 32 bits of 64-bit write data, or the target
drives the upper 32 bits of 64-bit read data, when PBREQ64# and PBACK64#
are both asserted.
PBAD[63:32]
I/O
When not driven, PBAD[63:00] are pulled up to a valid logic level through
external resistors. In a 5 V environment use a 2.7 kΩ resistor; in a 3.3 V
environment use a 8.2 kΩ resistor
Bus Command and Byte Enables (Upper 4 bits): These signals are a
multiplexed command field and byte enable field. For both read and write
transactions, the initiator will drive byte enables for the PBAD[63:32] data bits
on PAC/BE[7:4]# during the data phases when PBREQ64# and PBACK64# are
both asserted.
PBC/BE[7:4]#
I/O
I/O
When not driven, PAC/BE[7:4]# are pulled up to a valid logic level through
external resistors. In a 5 V environment use a 2.7 kΩ resistor; in a 3.3 V
environment use a 8.2 kΩ resistor
PCI Interface Upper 32-bits Parity: This signal carries the even parity of the
36 bits of PBAD[63:32] and PBC/BE[7:4]# for both address and data phases.
When not driven, PBPAR64 is pulled up to a valid logic level through external
resistors.
PBPAR64
PCI interface request 64-bit Transfer: This signal is asserted by the initiator to
indicate that the initiator is requesting a 64-bit data transfer. It has the same
timing as PBFRAME#. When the Intel® P64H2 is the initiator, this signal is an
output. When the P64H2 is the target, this signal is an input.
PBREQ64#
PBACK64#
I/O
I/O
PCI interface acknowledge 64-bit Transfer: This signal is asserted by the
target only when PBREQ64# is asserted by the initiator. It indicates the target’s
ability to transfer data using 64 bits. It has the same timing as PBDEVSEL#.
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Intel® 82870P2 P64H2 Datasheet
Signal Description
R
2.3
PCI Bus Interface Clocks and Reset
There are two sets of PCI Bus clock and reset signals: one for PCI Bus A and one for PCI Bus B.
Table 6. PCI Bus Interface Clocks and Reset Interface A Signals
Signal
Type
Description
PCI Clock Output: These signals provide 33/66/100/133 MHz clock for a PCI
device. PAPCLKO6 is connected to the PAPCLKI input. It must be externally
connected.
PAPCLKO[6:0]
O
PCI Clock In: This signal is connected to an output of the low skew PCI clock
buffer tree. It is used by the PLL to synchronize the PCI clock driven from
PCLKOUT to the clock used for the internal PCI logic.
PAPCLKI
I
PCI Reset: The Intel® P64H2 asserts PCIRST# to reset devices that reside on
the secondary PCI bus. The P64H2 asserts PCIRST# due to one of the
following events:
PAPCIRST#
O
• RSTIN#
• Setting the PCI Reset (bit 6) in the Bridge Control Register.
Bypass Clock – 100 MHz: This clock input can be up to 100 MHz, and will be
driven by the P64H2 as the PCI-X clock if in bypass mode and the PCI-X
frequency is supposed to be 100 MHz.
BPCLK100
BPCLK133
I
I
Bypass Clock – 133 MHz: This clock input can be up to 133 MHz, and will be
driven by the P64H2 as the PCI-X clock if in bypass mode and the PCI-X
frequency is supposed to be 133 MHz.
Intel® 82870P2 P64H2 Datasheet
27
Signal Description
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Table 7. PCI Bus Interface Clocks and Reset Interface B Signals
Signal
Type
Description
PCI Clock Output: These signals provide the 33/66/100/133 MHz clock for a
PCI device. PBPCLKO6 is connected to the PBPCLKI input.
PBPCLKO[6:0]
O
PCI Clock In: This signal is connected to an output of the low skew PCI clock
buffer tree. It is used by the PLL to synchronize the PCI clock driven from
PCLKOUT to the clock used for the internal PCI logic.
PBPCLKI
I
PCI Reset: The Intel® P64H2 asserts PCIRST# to reset devices that reside on
the secondary PCI bus. The P64H2 asserts PCIRST# due to one of the
following events:
PBPCIRST#
O
• RSTIN#
• Setting the PCI Reset (bit 6) in the Bridge Control Register.
Note: Platforms that are ACPI Compliant may encounter a noise/spike glitch on PCIRST# upon entering a
sleep state. The noise spike approaches Vih minimum levels that may cause PCI-X devices to inadvertently
exit the sleep state prematurely, the LOM (LAN on motherboard) configuration register contents are
discarded, which prevents the system to respond from a true LAN event and wake up.
To prevent the noise spike from occurring on the PCIRST# signal, the 1.8 voltage input to the P64H2 has to
drop with or before the 3.3 voltage rail. The 1.8V can be derived from 3.3V to ensure this timing
requirement is met.
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Intel® 82870P2 P64H2 Datasheet
Signal Description
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2.4
Interrupt Interface
This section lists the interrupt interface signals. There are two sets of IRQ interrupt signals;
PAIRQ[15:0] for PCI Bus A and PBIRQ[15:0] for PCI Bus B.
Table 8. Interrupt Interface Signals
Signal
Type
Description
Interrupt Request Bus A: The PIRQ# lines from PCI interrupts PIRQ[A:D] can
be routed to these interrupt lines. PAIRQ[15:0] are connected to an I/OxAPIC
that resides on PCI bus A (pins [15:0]).
PAIRQ[15:0]
I
Interrupt Request Bus B: The PIRQ# lines from PCI interrupts PIRQ[A:D] can
be routed to these interrupt lines. PBIRQ[15:0] are connected to an I/OxAPIC
that resides on PCI bus B (pins [15:0]).
PBIRQ[15:0]
BT_INTR#
I
Boot Interrupt: This open drain output is a logical OR of all interrupt request
inputs from both I/OxAPICs. These pins may be connected to the ICH to support
connecting boot devices behind the Intel® P64H2 to an 8259.
O
Each interrupt is qualified with the mask. If the interrupt is masked, it goes out
on the BT_INTR# pin.
APIC Clock: This clock is 16.66667 MHz and is the APIC bus clock. The
frequency of this clock can be raised to as high as 33 MHz to support FRC
mode on dual-processor systems.
APICCLK
I
APIC Data: These bi-directional open drain signals are used to send and
receive data over the APIC bus. As inputs the data is valid on the rising edge of
APICCLK. As outputs, new data is driven from the rising edge of the APICCLK.
APICD[1:0]
I/O
2.5
Hot Plug Interface
There are two sets of hot plug interface signals; one for PCI Bus A and one for PCI Bus B.
Table 9. Hot Plug Interface A Signals
Signal
Type
Description
Serial Input Clock: This signal is normally high. It pulses low to shift
external serial input shift register data one bit position. (The shift
registers should be similar to standard “74x165” series).
HPA_SIC
O
Serial Input Load: This signal is normally high. It pulses low to
synchronously parallel load external serial input shift registers on the next
rising edge of HPA_SIC.
HPA_SIL#
HPA_SID
O
I
Serial Input Data: Data shifted in from external logic on HPA_SIC.
Serial Output Non-Reset Latch Clear: This signal is normally high. It
asynchronously clears the power-enable, clock-enable, slot bus-enable,
and LED latches.
HPA_SOR#
O
Serial Output Reset Latch Clear: This signal is normally high. It
asynchronously clears the PCI slot reset latches.
HPA_SORR#
O
Intel® 82870P2 P64H2 Datasheet
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Signal Description
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Signal
Type
Description
Serial Output Clock: This signal is normally high. It pulses low to shift
internal serial output shift register data one bit position. (The shift
registers should be similar to standard “74x164” series).
HPA_SOC
O
Serial Output Non-Reset Latch Load: This signal is normally high. It
pulses low to clock external latches (power-enable, clock-enable, slot
bus-enable, and LED latches). The high edge acts as the clock.
HPA_SOL
O
Serial Output Reset Latch Load: This signal is normally high. It pulses
high to clock external latches (Reset latches) reading the serial output
shift registers. The high edge acts as the clock.
HPA_SOLR
HPA_SOD
O
O
Serial Output Data: Data is shifted out to external logic on HPA_SOC.
Number of Hot Plug Slots: Input strap to denote number of hot plug
slots. The straps should be pulled high or low to indicate a binary
encoded value, the number of hot plug slots in the system. They should
be pulled up to 3.3 V or down to Ground with an 8.2 kΩ resistor.
HPA_SLOT [2:0]
I
Table 10. Hot Plug Interface B Signals
Signal
Type
Description
Serial Input Clock: This signal is normally high. It pulses low to shift
external serial input shift register data one bit position. (The shift
registers should be similar to standard “74x165” series).
HPB_SIC
O
Serial Input Load: This signal is normally high. It pulses low to
synchronously parallel load external serial input shift registers on the next
rising edge of HPB_SIC.
HPB_SIL#
HPB_SID
O
I
Serial Input Data: Data shifted in from external logic on HPB_SIC.
Serial Output Non-Reset Latch Clear: This signal is normally high. It
asynchronously clears the power-enable, clock-enable, slot bus-enable,
and LED latches.
HPB_SOR#
O
Serial Output Reset Latch Clear: This signal is normally high. It
asynchronously clears the PCI slot reset latches.
HPB_SORR#
HPB_SOC
O
O
Serial Output Clock: This signal is normally high. It pulses low to shift
internal serial output shift register data one bit position. (The shift
registers should be similar to standard “74x164” series).
Serial Output Non-Reset Latch Load: This signal is normally high. It
pulses low to clock external latches (power-enable, clock-enable, slot
bus-enable, and LED latches). The high edge acts as the clock.
HPB_SOL
O
Serial Output Reset Latch Load: This signal is normally high. It pulses
high to clock external latches (Reset latches) reading the serial output
shift registers. The high edge acts as the clock.
HPB_SOLR
HPB_SOD
O
O
Serial Output Data: Data shifted out to external logic on HPB_SOC.
Number of Hot Plug Slots: Input strap to denote number of hot plug
slots. The straps should be pulled high or low to indicate a binary
encoded value, the number of hot plug slots in the system. They should
be pulled up to 3.3 V or down to ground with an 8.2 kΩ resistor.
HPB_SLOT [2:0]
I
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Intel® 82870P2 P64H2 Datasheet
Signal Description
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2.6
SMBus Interface
Table 11. SMBus Interface Signals
Signal
Type
Description
SMBus Data: SMBus Data Pin. External pull-up required, refer to SMBus 2.0
specification.
SDTA
I/OD
SMBus Clock: SMBus Clock Pin. External pull-up required, refer to SMBus 2.0
specification.
SCLK
I/OD
2.7
Miscellaneous Signals
Table 12. Miscellaneous Signals
Signal
Type
Description
RAS Error: This pin indicates that a Reliability, Availability, and Serviceability
error has been logged. This is an active low signal that is a logical OR of all the
Reliability, Availability, and Serviceability error events. If one of these errors is
active, the pin is low. If none are active, then the pin is tri-stated. RASERR#
should be tied high to 3.3 V though an 8.2 kΩ pull-up resistor.
RASERR#
O
Intel Test Mode: This signal must be tied high to 3.3 V though an 8.2 kΩ
resistor for normal operation.
TEST#
I
I
Reset In: When asserted, this signal asynchronously resets the P64H2 logic
and asserts PCIRST# active output from each PCI interface. This signal is
typically connected to the PCIRST# output of the ICH.
RSTIN#
Power is OK: This signal is used to determine whether the hot plug controller
for a particular interface is in single-slot, dual-slot, or serial mode.
PWROK
TPO
I
I
Test Point 0: This signal is connect to VCC3.3 through an 8.2 kΩ pull-up
resistor.
Intel® 82870P2 P64H2 Datasheet
31
Signal Description
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2.8
Power and Reference Voltage Signals
Table 13. Power and Reference Voltage Signals
Signal
VCC
Description
Core Reference Voltage: This is the voltage for core (1.8 V nominal).
3.3 V Reference Voltage: This is the voltage for PCI I/O (3.3 V nominal).
1.8 V Reference Voltage: This is the voltage for hub interface I/O (1.8 V nominal).
VCC3.3
VCC1.8
5 V Reference Voltage: This is the reference voltage for 5 V-tolerance on PCI inputs
(5.0 V nominal).
VCC5REF
VSS
Ground: Ground for all VCC rails.
Hub Interface Reference Voltage: This is the reference voltage for the hub interface
inputs (nominally 0.350 V).
HI_VREF
Hub Interface RCOMP Reference Voltage: This is the reference voltage for the hub
interface RCOMP circuit (nominally 0.800 V).
HI_VSWING
2.9
Pin Straps
The following signals are used for static configuration. These signals are sampled when PWROK
goes high and then return to normal usage afterward.
Table 14. Normal Functional Pin Straps
Strap Pin
PA_133EN
Function
When high, bus A is capable of 133 MHz. When low, bus A is only capable of
100 MHz.
When high, bus B is capable of 133 MHz. When low, bus B is only capable of
100 MHz.
PB_133EN
Number of hot plug slots on bus A. “000” will hide the hot plug controller from
software.
HPA_SLOT[2:0]
HPB_SLOT[2:0]
Number of hot plug slots on bus B. “000” will hide the hot plug controller from
software.
PAGNT[5:4]
PBGNT[5:4]
SMBus strap address.
When high, the P64H2 uses the 200 MHz differential clock. When low, Intel® P64H2
uses the 66 MHz clock.
PAGNT3
PBGNT3
When high, hub interface RCOMP is disabled. When low, RCOMP is enabled.
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Intel® 82870P2 P64H2 Datasheet
Signal Description
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Intel® 82870P2 P64H2 Datasheet
33
Register Description
R
3 Register Description
The Intel® P64H2 contains registers for its hub interface to PCI bridges, hot plug controller,
IOAPIC controller, and SMBus interface. This chapter describes these registers. A detailed bit
description is provided. For register access description, refer to Section 4.4.
PCI Configuration Registers
The P64H2 contains three PCI Devices that reside in Function 0—Hub Interface-to-PCI Bridge
(Device 31 and 29), I/O APIC devices (Device 28 and 30), and the hot plug controller
(Device 31).
• Hub Interface-to-PCI Bridge (D31, 29: F0). This portion of the P64H2 implements the
buffering and control logic between PCI and the hub interface. The PCI bus arbitration is
handled by these PCI devices. The PCI decoder in this device must decode the ranges for hub
interface to the MCH. This register set also provides support for Reliability, Availability, and
Serviceability (RAS). Device 31 is intended for the Hub Interface to PCI A Bridge and device
29 is intended for Hub Interface to PCI B Bridge.
• I/OxAPIC Devices (D28, 30: F0). The P64H2 implements a variation of the APIC known as
the I/OxAPIC. There are two I/OxAPIC devices on the P64H2 and they reside on the primary
bus. Device 28 is intended to be used with interrupts from PCI Bus A and Device 30 is
intended to be used with interrupts on PCI Bus B.
• Hot Plug Controller (Device 31: F0). There are two hot plug controllers; one for PCI Bus A
and one for PCI Bus B. These controllers reside on the secondary PCI bus.
The P64H2 supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism #1 in the PCI specification. Refer to Section 4.1.6 for information on
accessing the P64H2 PCI configuration registers.
Memory-Mapped Registers
• I/OxAPIC. In addition to the PCI Configuration Registers mentioned above, the I/OxAPIC
memory-mapped registers are located in the processor memory space located by the MBAR
Register (PCI offset 10h) and MBARU Register (PCI offset 14h). MBAR and MBARU are
located in the I/OxAPIC PCI Configuration space.
• Hot Plug Controller. In addition to the PCI Configuration Registers mentioned above, the
hot plug controller memory-mapped registers are located in the processor memory space
located by the MBAR Register (PCI offset 10h). MBAR is located in the hot plug controller
PCI Configuration space.
SMBus Port Registers
• SMBus interface. The SMBus does not have any PCI configuration registers. These registers
are only accessible via the SMBus port (see Section 3.5).
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Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.1
Register Nomenclature and Access Attributes
Symbol
RO
Description
Read Only. If a register is read only, writes to this register have no effect.
Read/Write. A register with this attribute can be read and written
R/W
R/W/L
R/WC
Read/Write/Lock. A register with this attribute can be read, written, and Locked.
Read/Write Clear. A register bit with this attribute can be read and written. However, a
write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
R/WO
L
Read/Write Once. A register bit with this attribute can be written to only once after power
up. After the first write, the bit becomes read only.
Lock. A register bit with this attribute becomes Read Only after a lock bit is set.
Reserved
Bits
Some of the Intel® P64H2 registers described in this section contain reserved bits. These
bits are labeled "Reserved”. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. On writes, software must ensure that the values
of reserved bit positions are preserved. That is, the values of reserved bit positions must
first be read, merged with the new values for other bit positions and then written back.
Note the software does not need to perform read, merge, and write operations for the
configuration address register.
Reserved
Registers
In addition to reserved bits within a register, the P64H2 contains address locations in the
configuration space that are marked "Reserved. When a “Reserved” register location is
read, a random value can be returned. (“Reserved” registers can be 8-, 16-, or 32-bit in
size). Registers that are marked as “Reserved” must not be modified by system software.
Writes to “Reserved” registers may cause system failure.
Default
Value Upon
Reset
Upon a Full Reset, the P64H2 sets its internal configuration registers to predetermined
default states. The default state represents the minimum functionality feature set required
to successfully bring up the system. Hence, it does not represent the optimal system
configuration. It is the responsibility of the system initialization software (usually BIOS) to
properly determine the operating parameters and optional system features that are
applicable, and to program the P64H2 registers accordingly.
Intel® 82870P2 P64H2 Datasheet
35
Register Description
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3.2
Hub Interface-to-PCI Bridge PCI Configuration
Registers (Device 31 and 29)
Table 15 lists the registers contained in this section. The register descriptions that follow are
arranged by address as indicated in Table 15.
Note: The Hub Interface-to-PCI Bridge does not perform function decode.
Table 15. Hub Interface-to-PCI Bridges Address Map (D31,29, F0)
Address
Symbol
Register Name
Vendor Identification
Default
Access
Offset
00–01h
02–03h
04–05h
06–07h
08h
VID
DID
8086h
1460h
0000h
0030h
04h
RO
RO
Device Identification
PD_CMD
PD_STS
RID
PCI Primary Device Command
PCI Primary Device Status
Revision Identification
Class Code
R/W
R/W
RO
09–0Bh
0Ch
CC
060400h
00h
RO
CLS
Cache Line Size
R/W
R/W
RO
0Dh
PMLT
Primary Master Latency Timer
Header Type
00h
0Eh
HEADTYP
BNUM
SMLT
01h
18–1Ah
1Bh
Bus Number
000000h
00h
R/W
R/W
R/W
R/W
R/W
Secondary Master Latency Timer
I/O Base and Limit Address
Secondary Status
1C–1Dh
1E–1Fh
20–23h
IOBL_ADR
SECSTS
MBL_ADR
0000h
02A0h
00000000h
Memory Base and Limit Address
Prefetchable Memory Base and Limit
Address
24–27h
28–2Bh
2C–2Fh
PMBL_ADR
00010001h
00000000h
00000000h
R/W
R/W
R/W
PREF_MEM_
BASE_UPPER
Prefetchable Memory Base Upper 32 Bit
Address
PREF_MEM_
LIM_UPPER
Prefetchable Memory Limit Upper 32 Bit
Address
30–33h
34h
IOBLU16_ADR
I/O Base and Limit Upper 16 Bit Address
Capabilities List Pointer
Reserved
00000000h
05h
RO
RO
—
CAPP
—
35–3Bh
3C–3Dh
3E–3Fh
40–41h
42h
—
INTR
Interrupt Information
Bridge Control
0000h
0000h
0000h
00h
RO
R/W
R/W
R/W
RO
—
BRIDGE_CNT
CNF
Intel P64H2 Configuration
Multi-Transaction Timer
PCI Strap Status
MTT
44–47h
48–4Fh
STRP
—
00000000h
—
Reserved
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Intel® 82870P2 P64H2 Datasheet
Register Description
R
Address
Offset
Symbol
Register Name
Default
Access
50h
51h
PX_CAPID
—
PCI-X Capabilities Identifier
Reserved
07h
—
RO
—
52–53h
PX_SSTS
PCI-X Secondary Status
0003h
R/W
000100F8h/
000100E8h
54–57h
58–5Bh
5C–5Fh
PX_BSTS
PX_USTC
PX_DSTC
PCI-X Bridge Status
RO
R/W
R/W
PCI-X Upstream Split Transaction Control
0000FFFFh
0000FFFFh
PCI-X Downstream Split Transaction
Control
60–62h
63h
RAS_STS
—
RAS Status
xxxxxxh
—
R/W
—
Reserved
64–66h
67–6Bh
6C–6Dh
6E–6Fh
70–73h
74–77h
78–7Bh
7C–7Fh
80–83h
84–87h
88–8Bh
8C–8Fh
90–93h
94–97h
98–9Bh
9C–9Dh
E0–E3h
E4–E5h
E6–EFh
F0–F3h
F8–F9h
FA–FBh
FC–FDh
FE–FFh
RAS_DI
—
RAS Data Integrity Codes
Reserved
xxxxxxh
—
RO
—
RAS_PH
—
RAS PCI Header
xxxxh
RO
—
Reserved
—
RAS_PAL
RAS_PAH
RAS_PDL
RAS_PDH
RAS_HH
RAS_HAL
RAS_HAH
RAS_HP
RAS_D0
RAS_D1
RAS_D2
RAS_D3
ACNF
RAS PCI Address Low
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxh
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
—
RAS PCI Address High
RAS PCI Data Low 32 bits
RAS PCI Data High 32 bits
RAS Hub Interface Header
RAS Hub Interface Address Low 32 Bits
RAS Hub Interface Address High 32 Bits
RAS Hub Interface Prefetch Horizon
RAS Hub Interface DWord 0
RAS Hub Interface DWord 1
RAS Hub Interface DWord 2
RAS Hub Interface DWord 3
Additional P64H2 Configuration
PCI Compensation Control
Reserved
0000000Fh
0000h
PCC
—
—
HCCR
Hub Interface Command/Control
Prefetch Control for 33 MHz
Prefetch Control for 66 MHz
Prefetch Control for 100 MHz
Prefetch Control for 133 MHz
00000000h
1212h
R/W
R/W
R/W
R/W
R/W
PC33
PC66
3323h
PC100
PC133
7B7Bh
BFFFh
Intel® 82870P2 P64H2 Datasheet
37
Register Description
R
3.2.1
3.2.2
3.2.3
VID—Vendor ID Register (D29,31: F0)
Offset:
Default Value: 8086h
00–01h
Attribute:
Size:
RO
16 bits
This register contains the vendor identification.
Bits
Description
15:00
Vendor ID (VID). 16-bit vendor ID assigned to Intel VID=8086h.
DID—Device ID Register (D29,31: F0)
Offset:
Default Value: 1460h
02–03h
Attribute:
Size:
RO
16 bits
This register contains the device identification.
Bits
Description
15:00
Device ID (DID). Device number of the Intel® P64H2 hub interface to PCI bridge. DID=1460h.
PD_CMD—PCI Primary Device Command Register
(D29,31: F0)
Offset:
Default Value: 0000h
04–05h
Attribute:
Size:
R/W
16 bits
This register controls how the device behaves on the primary interface and is the same as all other
devices, with the exception of the VGA Palette Snoop bit. As this component is a bridge,
additional command information is located in a separate register called "Bridge Control" located at
offset 3Eh.
38
Intel® 82870P2 P64H2 Datasheet
Register Description
R
Bits
Description
15:10
Reserved.
Fast Back-to-back Enable (FBE)—RO. Hardwired to 0. This bit has no meaning on the hub
interface.
9
SERR# Enable (SEE)—R/W. This bit controls the enable for DO_SERR special cycle on the hub
interface
8
7
0 = Disable special cycle.
1 = Enable special cycle.
Wait Cycle Control (WCC)—RO. Reserved. Hardwired to 0.
Parity Error Response Enable (PERE)—R/W. This bit controls the P64H2’s response when a
parity / multi-bit ECC error is detected on the hub interface.
6
0 = Disable. The P64H2 ignores these errors on the hub interface.
1 = Enable. The P64H2 reports these errors on the hub interface and sets the DPD bit in the
PD_STS Register.
5
4
3
VGA Palette Snoop Enable (VGA_PSE)—RO. Reserved. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0. The P64H2 does not
generate memory write and invalidate transactions, as the hub interface does not have a
corresponding transfer type.
Special Cycle Enable (SCE)—RO. Reserved.
Bus Master Enable (BME)—R/W. This bit controls the P64H2’s ability to act as a master on the
hub interface when forwarding memory transactions from PCI.
2
0 = Disable. The P64H2 does not respond to any memory transactions on the PCI interface that
target the hub interface.
1 = Enable.
Memory Space Enable (MSE)—R/W. This bit controls the P64H2’s response as a target to
memory accesses on the hub interface that address a device behind the P64H2.
1
0
0 = Disable. The P64H2 does not respond to Memory or I/O transactions on the PCI bus and
does not initiate I/O or memory transactions on the hub interface.
1 = Enable. The P64H2 is allowed to accept cycles from PCI to be passed to the hub interface
I/O Space Enable (IOSE)—R/W. This bit controls the P64H2’s response as a target to I/O
transactions on the primary interface that addresses a device that resides behind the P64H2.
0 = Disables the P64H2 from responding to I/O transactions initiated on the hub interface.
1 = Enables the P64H2 to respond to I/O transaction initiated on the hub interface
Intel® 82870P2 P64H2 Datasheet
39
Register Description
R
3.2.4
PD_STS—PCI Primary Device Status Register (D29,31: F0)
Offset:
Default Value: 0030h
06–07h
Attribute:
Size:
R/WC, RO
16 bits
Bits
Description
Detected Parity Error (DPE)—R/WC.
0 = No address parity error, data parity error, or mulit-bit ECC error detected.
1 = Intel® P64H2 detected an address parity, data parity, or multi-bit ECC error on the hub
interface. This bit gets set even if the Parity Error Response (bit 6 of the PCI Primary Device
Command Register) is not set. Note that each bridge will set this bit, regardless of address.
15
Note: Software clears this bit by writing a 1 to it.
Signaled System Error (SSE)—R/WC.
0 = No SERR# is reported to the hub interface
1 = SERR# is reported to the hub interface via the DO_SERR special cycle.
Note: Software clears this bit by writing a 1 to it.
Received Master Abort (RMA)—R/WC.
14
13
0 = No Master Abort status received.
1 = P64H2 is acting as master on the hub interface and receives a completion packet with
master abort status.
Note: Software clears this bit by writing a 1 to it.
Received Target Abort (RTA)—R/WC.
0 = No target abort status received.
12
1 = P64H2 is acting as master on the hub interface and receives a completion packet with target
abort status.
Note: Software clears this bit by writing a 1 to it.
Signaled Target Abort (STA)—R/WC.
0 = No target abort status generated.
11
1 = P64H2 generates a completion packet with target abort status.
Note: Software clears this bit by writing a 1 to it.
DEVSEL# Timing (DVT)—RO. Hardwired to 00. These bits have no meaning on the hub
interface. Fast decode timing is reported.
10:9
Data Parity Error Detected (DPD)—R/WC.
0 = No data parity error or multi-bit ECC error detected.
1 = P64H2 receives a completion packet from the hub interface from a previous request, and
detects a parity or multi-bit ECC error, and the Parity Error Response bit in the PCI Primary
Device Command Register (offset 04h, bit 6) is set.
8
7
Note: Software clears this bit by writing a 1 to it.
Fast Back-to-Back Capable (FBC)—RO. Hardwired to 0. This bit has no meaning on the hub
interface.
40
Intel® 82870P2 P64H2 Datasheet
Register Description
R
Bits
Description
6
Reserved
66 MHz Capable (C66)—RO. Hardwired to 1. This bit has no meaning on the hub interface, but
is set to be true in case of any software dependencies on bandwidth calculations.
5
Capabilities List Enable (CAPE)—RO. This bit indicates that the P64H2 contains the
capabilities pointer in the bridge. The register at offset 34h (Capabilities List Pointer) indicates
the offset for the first entry in the linked list of capabilities.
4
3:0
Reserved
3.2.5
RID—Revision ID Register (D29,31: F0)
Offset:
Default Value: 04h
08h
Attribute:
Size:
RO
8 bits
Bits
Description
Revision ID (RID). This field indicates the stepping of the Intel® P64H2:
7:0
03h = B0 Stepping
04h = B1 stepping
3.2.6
CC—Class Code Register (D29,31: F0)
Offset:
Default Value: 060400h
09–0Bh
Attribute:
Size:
RO
24 bits
This contains the class code, sub class code, and programming interface for the device.
Bits
Description
Base Class Code (BCC).
06h = Bridge device.
23:16
Sub Class Code (SCC).
04h = Type of PCI-PCI bridge.
Programming Interface (PIF).
15:8
7:0
00h = Standard (non-subtractive) PCI-PCI bridge.
Intel® 82870P2 P64H2 Datasheet
41
Register Description
R
3.2.7
CLS—Cache Line Size Register (D29,31: F0)
Offset:
Default Value: 00h
0Ch
Attribute:
Size:
R/W
8 bits
This register indicates the cache line size of the system.
Bits
Description
7:0
Cache Line Size (CLS). The value in this field is used by the Intel® P64H2 to determine the size
of packets on the hub interface. This read/write register specifies the system cacheline size in
units of DWords.
08h = 32-byte line (8 DWords).
10h = 64-byte line
20h = 128-byte line.
Any value outside this range will default to a 64-byte line. When the P64H2 is creating read and
write requests to the hub interface, this value is used to partition the requests such that multiple
snoops for the same line are avoided in the memory subsystem.
3.2.8
PMLT—Primary Master Latency Timer Register
(D29,31: F0)
Offset:
Default Value: 00h
0Dh
Attribute:
Size:
R/W
8 bits
This register does not apply to the hub interface and is maintained as R/W for software
compatibility.
Bits
Description
7:3
2:0
Time Value (TV). Read / write used for software compatibility only.
Reserved
3.2.9
HEADTYP—Header Type Register (D29,31: F0)
Offset:
Default Value: 01h
0Eh
Attribute:
Size:
RO
8 bits
This register determines how the rest of the configuration space is laid out.
Bits
Description
Multi-Function Device (MFD). This bit returns 0 to indicate the bridge is a single-function
device.
7
Header Type (HTYPE). This field defines the layout of addresses 10h through 3Fh in PCI
configuration space. This field reads as 01h to indicate that the register layout conforms to the
standard PCI-to-PCI bridge layout.
6:0
42
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.2.10
BNUM—Bus Number Register (D29,31: F0)
Offset:
Default Value: 000000h
18–1Ah
Attribute:
Size:
R/W
24 bits
This contains the primary, secondary, and maximum subordinate bus number registers.
Bits
Description
Subordinate Bus Number (SBBN). This field indicates the highest PCI bus number below this
bridge. Any type 1 configuration cycle on the hub interface whose bus number is greater than the
secondary bus number and less than or equal to the subordinate bus number will be run as a
type 1 configuration cycle on the PCI bus.
23:16
Secondary Bus Number (SCBN). This field indicates the bus number of PCI to which the
secondary interface is connected. Any type 1 configuration cycle matching this bus number will
be translated to a type 0 configuration cycle and run on the PCI bus.
15:08
7:0
Primary Bus Number (PBN). This field indicates the bus number of the hub interface. Any type
1 configuration cycle with a bus number less than this number will not be accepted by this portion
of the P64H2 (in other words, it still may match the other bridge).
3.2.11
SMLT—Secondary Master Latency Timer (D29,31: F0)
Offset:
Default Value: 00h
1Bh
Attribute:
Size:
R/W
8 bits
This timer controls the amount of time that the P64H2 will continue to burst data on its secondary
interface. The counter starts counting down from the assertion of PxFRAME#. If the grant is
removed, then the expiration of this counter will result in the deassertion of PxFRAME#. If the
grant has not been removed, then the P64H2 may continue ownership of the bus. Secondary
latency timer’s default value should be 64 in PCI-X mode (Section 8.6.1 of the PCI-X Addendum
to the PCI Local Bus Specification, Revision 1.0).
Bits
Description
Secondary Latency Timer (TV). This 5-bit value indicates the number of PCI clocks, in 8-clock
increments, that the P64H2 remains as a master of the PCI bus if another master is requesting
use of the PCI bus.
7:3
2:0
Reserved
Intel® 82870P2 P64H2 Datasheet
43
Register Description
R
3.2.12
IOBL_ADR—I/O Base and Limit Address Register
D29,31: F04
Offset:
Default Value: 0000h
1C–1Dh
Attribute:
Size:
R/W, RO
16 bits
This register defines the base and limit (aligned to a 4 KB boundary) of the I/O area of the bridge.
Accesses from the hub interface that are within the ranges specified in this register will be sent to
PCI if the I/O space enable bit is set. Accesses from PCI that are outside the ranges specified will
master abort.
Bits
Description
I/O Limit Address Bits [15:12] (IOLA)—R/W. Defines the top address of an address range to
determine when to forward I/O transactions from one interface to the other. These bits
correspond to address lines 15:12 for 4 KB alignment. Bits [11:0] are assumed to be FFFh.
15:12
I/O Limit Address Bits [11:10] (IOLA1K)—R/W, RO. When the EN1K bit is set in the Intel®
P64H2 Configuration register (CNF), these bits become read/write and are compared with I/O
address bits [11:10] to determine the 1 KB limit address.
11:10
When the EN1K bit is cleared, this field becomes read only.
I/O Limit Addressing Capability (IOLC)—RO. Hardwired to 00. This indicates support for only
16-bit I/O addressing.
9:8
7:4
I/O Base Address Bits [15:12] (IOBA)—R/W. This filed defines the bottom address of an
address range to determine when to forward I/O transactions from one interface to the other.
These bits correspond to address lines 15:12 for 4 KB alignment. Bits [11:0] are assumed to be
000h.
I/O Base Address Bits [11:10] (IOBA1K)—R/W, RO. When the EN1K bit is set in the P64H2
Configuration register (CNF), these bits become read/write and are compared with I/O address
bits [11:10] to determine the 1 KB base address. When the EN1K bit is 0, this field becomes read
only.
3:2
1:0
I/O Base Addressing Capability (IOBC)—RO. Hardwired to 00. This indicates support for only
16-bit I/O addressing.
3.2.13
SECSTS—Secondary Status Register (D29,31: F0)
Offset:
Default Value: 02A0h
1E–1Fh
Attribute:
Size:
R/WC, RO
16 bits
Bits
Description
Detected Parity Error (DPE)—R/WC.
0 = No address or data parity error detected.
15
1 = Intel® P64H2 detects an address or data parity error on the PCI bus. This bit gets set even
if the Parity Error Response bit (bit 0 of offset 3E–3Fh) is not set.
Note: Software clears this bit by writing a 1 to it.
44
Intel® 82870P2 P64H2 Datasheet
Register Description
R
Bits
Description
Received System Error (RSE)—R/WC.
0 = No SERR# received.
14
1 = P64H2 sets this bit when a SERR# assertion is received on PCI.
Note: Software clears this bit by writing a 1 to it.
Received Master Abort (RMA)—R/WC.
0 = No master abort received.
1 = P64H2 is acting as an initiator on the PCI bus and the cycle is master-aborted. For hub
interface packets that have completion required, this should also cause a target abort
completion status to be returned and set the Signaled Target Abort bit in the PCI Primary
Device Status (PD_STS) Register.
13
Note: Software clears this bit by writing a 1 to it.
Received Target Abort (RTA)—R/WC.
0 = No target abort received.
1 = P64H2 is acting as an initiator on PCI and a cycle is target-aborted on PCI. For "completion
required" hub interface packets, this event should force a completion status of "target abort"
on the hub interface, and set the Signaled Target Abort in the PCI Primary Device Status
(PD_STS) Register.’
12
Note: Software clears this bit by writing a 1 to it.
Signaled Target Abort (STA)—R/WC.
0 = No target abort signaled.
11
1 = P64H2 is acting as a target on the PCI Bus and signals a target abort.
Note: Software clears this bit by writing a 1 to it.
DEVSEL# Timing (DVT)—RO. Hardwired to 01. This field indicates that the P64H2 responds in
medium decode time to all cycles targeting the hub interface.
10:9
Data Parity Error Detected. (DPD)—R/WC.
0 = No data parity error detected.
1 = P64H2 sets this bit when all of the following is true:
• The P64H2 is the initiator on PCI.
8
• PxPERR# is detected asserted or a parity error is detected internally
• The Parity Error Response Enable bit in the Bridge Control Register (bit 0, offset 3Eh) is
set.
Note: Software clears this bit by writing a 1 to it.
Fast Back-to-Back Capable (FBC)—RO. Hardwired to 1; indicates that the secondary interface
of the P64H2 can receive fast back-to-back cycles.
7
6
Reserved
66 MHz Capable (C66)—RO. Hardwired to 1; indicates the secondary interface of the bridge is
66 MHz capable.
5
4:0
Reserved
Intel® 82870P2 P64H2 Datasheet
45
Register Description
R
3.2.14
MBL_ADR—Memory Base and Limit Address Register
(D29,31: F0)
Offset:
20–23h
Attribute:
Size:
R/W
32 bits
Default Value: 00000000h
This register defines the base and limit (aligned to a 1 MB boundary) of the prefetchable memory
area of the bridge. Accesses from the hub interface that are within the ranges specified in this
register will be sent to PCI if the memory space enable bit is set.
If the bus master enable bit is set, accesses from PCI that are outside the ranges specified in this
register will be forwarded to the hub interface.
Bits
Description
Memory Limit (ML). These bits are compared with bits [31:20] of the incoming address to
determine the upper 1 MB aligned value (exclusive) of the range. The incoming address must be
less than this value.
31:20
19:16
15:4
3:0
Reserved
Memory Base (MB). These bits are compared with bits [31:20] of the incoming address to
determine the lower 1 MB aligned value (inclusive) of the range. The incoming address must be
greater than or equal to this value.
Reserved
3.2.15
PMBL_ADR—Prefetchable Memory Base and Limit
Address Register (D29,31: F0)
Offset:
24–27h
Attribute:
Size:
R/W, RO
32 bits
Default Value: 00010001h
This register defines the base and limit (aligned to a 1 MB boundary) of the prefetchable memory
area of the bridge. Accesses from the hub interface that are within the ranges specified in this
register will be sent to PCI if the memory space enable bit is set.
If the bus master enable bit is set, accesses from PCI that are outside the ranges specified in this
register are forwarded to the hub interface.
Bits
Description
Prefetchable Memory Limit (PML)—R/W. These bits are compared with bits [31:20] of the
incoming address to determine the upper 1 MB aligned value (exclusive) of the range. The
incoming address must be less than this value.
31:20
64-bit Indicator (IS64L)—RO. Indicates that 32-bit addressing is supported for the limit. This
value must be in agreement with the IS64B field.
19:16
15:4
3:0
Prefetchable Memory Base (PMB)—R/W. These bits are compared with bits [31:20] of the
incoming address to determine the lower 1 MB aligned value (inclusive) of the range. The
incoming address must be greater than or equal to this value.
64-bit Indicator (IS64B)—RO. Indicates that 32-bit addressing is supported for the limit. This
value must be in agreement with the IS64L field.
46
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.2.16
3.2.17
3.2.18
PREF_MEM_BASE_UPPER—Prefetchable Memory Base
Upper 32 Bit Address Register (D29,31: F0)
Offset:
28–2Bh
Attribute:
Size:
R/W
32 bits
Default Value: 00000000h
This defines the upper 32 bits of the prefetchable address base register.
Bits
Description
Prefetchable Memory Base Upper Portion (PMBU). All bits are read/writeable; the Intel®
P64H2 supports full 64-bit addressing.
31:0
PREF_MEM_LIM_UPPER—Prefetchable Memory Limit
Upper 32 Bit Address Register (D29,31: F0)
Offset:
2C–2Fh
Attribute:
Size:
R/W
32 bits
Default Value: 00000000h
This defines the upper 32 bits of the prefetchable address limit register.
Bits
Description
Prefetchable Memory Limit Upper Portion (PMLU). All bits are read/writeable; the Intel®
P64H2 supports full 64-bit addressing.
31:0
IOBLU16_ADR—I/O Base and Limit Upper 16 Bit Address
Register (D29,31: F0)
Offset:
30–33h
Attribute:
Size:
RO
32 bits
Default Value: 00000000h
Since I/O is limited to 64 KB, this register is reserved and not used.
Bits
Description
31:16
15:0
I/O Base High 16 Bits (IOBH). Reserved
I/O Limit High 16 Bits (IOLH). Reserved
Intel® 82870P2 P64H2 Datasheet
47
Register Description
R
3.2.19
CAPP—Capabilities List Pointer Register (D29,31: F0)
Offset:
Default Value: 50h
34h
Attribute:
Size:
RO
8 bits
This register contains the pointer for the first entry in the capabilities list.
Bits
Description
Capabilities Pointer (PTR). This field indicates that the pointer for the first entry in the
capabilities list is at 50h in configuration space.
7:0
3.2.20
INTR—Interrupt Information Register (D29,31: F0)
Offset:
Default Value: 0000h
3C–3Dh
Attribute:
Size:
RO
16 bits
This register contains information on interrupts on the bridge.
Bits
Description
15:08
Interrupt Pin (PIN). Bridges do not support the generation of interrupts.
Interrupt Line (LINE). The Intel® P64H2 Bridge does not generate interrupts, so this is reserved
as 00h.
07:00
3.2.21
BRIDGE_CNT—Bridge Control Register (D31: F0)
Offset:
Default Value: 0000h
3E–3Fh
Attribute:
Size:
R/W, R/WC
16 bits
This register provides extensions to the PCI Primary Device Command Register that are specific to
a bridge. The Bridge Control Register provides many of the same controls for the secondary
interface that are provided by the PCI Primary Device Command Register for the primary
interface. Some bits affect operation of both interfaces of the bridge.
Bits
Description
15:12
Reserved
Discard Timer SERR# Enable (DTSE)—R/W. This bit controls the generation of SERR# on the
primary interface in response to a timer discard on the secondary interface.
11
0 = Do not generate SERR# on a secondary timer discard
1 = Generate SERR# in response to a secondary timer discard
48
Intel® 82870P2 P64H2 Datasheet
Register Description
R
Bits
Description
Discard Timer Status (DTS)—R/WC.
0 = Secondary discard timer has Not expired.
10
1 = Secondary discard timer expires (there is no discard timer for the primary interface).
Note: Software clears this bit by writing a 1 to it.
Secondary Discard Timer (SDT)—R/W. This bit sets the maximum number of PCI clock cycles
that the P64H2 waits for an initiator on PCI to repeat a delayed transaction request. The counter
starts once the delayed transaction completion is at the head of the queue. If the master has not
repeated the transaction at least once before the counter expires, the P64H2 discards the
transaction from its queues.
9
0 = The PCI master timeout value is between 215 and 216 PCI clocks.
1 = The PCI master timeout value is between 210 and 211 PCI clocks
Primary Discard Timer (PDT)—R/W. Not relevant to the hub interface. This bit is R/W for
software compatibility only.
8
7
Fast Back-to-Back Enable (FBE)—RO. The P64H2 cannot generate fast back-to-back cycles on
the PCI bus from hub interface-initiated transactions.
Secondary Bus Reset (SBR)—R/W This bit controls PCIRST# assertion on PCI.
0 = P64H2 deasserts PCIRST#.
6
5
4
1 = P64H2 asserts PCIRST#. When PCIRST# is asserted, the data buffers between the hub
interface and PCI and the PCI bus are initialized back to reset conditions. The hub interface
and the configuration registers are not affected.
Master Abort Mode (MAM)—R/W. This bit controls the P64H2’s behavior when a master abort
occurs on either interface.
Master Abort on the hub interface
0 = The P64H2 asserts PxTRDY# on PCI/PCI-X. It drives all 1s for reads, and discards data on
writes.
1 = The P64H2 returns a target abort on PCI/PCI-X.
Master Abort PCI/PCI-X (Completion required packets only)
0 = Normal completion status will be returned on the hub interface.
1 = Target abort completion status will be returned on the hub interface.
VGA 16-bit Decode Enable—R/W. This bit enables the bridge to provide 16-bits decoding of
VGA I/O address precluding the decode of VGA alias addresses every 1 KB. This bit requires the
VGA enable bit (bit 3 of this register) to be set 1.
0 = Disable
1 = Enable.
Intel® 82870P2 P64H2 Datasheet
49
Register Description
R
Bits
Description
VGA Enable (VGAE)—R/W. This bit modifies the P64H2’s response to VGA compatible address.
0 = When the bit is 0, memory and I/O addresses on the secondary interface between the
ranges shown below will be forwarded to the hub interface.
1 = P64H2 forwards the following transactions from the hub interface to PCI regardless of the
value of the I/O Base and Limit Address Registers. The transactions are qualified by the
Memory Enable bit and I/O Enable bit in the PCI Primary Device Command Register
(offset 04–05h).
3
Memory addresses: 000A0000h–000BFFFFh
I/O addresses:
3B0h–3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of
the address must be 0, and bits [15:10] of the address are ignored
(i.e., aliased).
ISA Enable (IE)—R/W. This bit modifies the response by the bridge to ISA I/O addresses. This
only applies to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in
the first 64 KB of PCI I/O space.
0 = Disable.
2
1 = Enable. The bridge will block any forwarding from primary to secondary of I/O transactions
addressing the last 768 bytes in each 1 KB block (offsets 100h to 3FFh). This bit has no
effect on transfers originating on the secondary bus as the P64H2 does not forward I/O
transactions across the bridge.
SERR# Enable (SE)—R/W. This bit controls the forwarding of secondary interface SERR#
assertions on the primary interface.
0 = Disable
1 = Enable. P64H2 will send a hub interface DO_SERR special cycle when all of the following
are true:
1
•
•
•
SERR# is asserted on the secondary interface.
This bit is set
The SERR# Enable bit in the PCI Primary Device Command Register (offset 04–05h) is
set.
Parity Error Response Enable (PERE)—R/W. This bit control’s the P64H2’s response to
address and data parity errors on the secondary interface.
0
0 = Disable. The bridge must ignore any parity errors that it detects and continue normal
operation. The P64H2 must generate parity even if parity error reporting is disabled.
1 = Enable. Parity errors reported on the secondary interface.
50
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.2.22
CNF—P64H2 Configuration Register (D29,31: F0)
Offset:
Default Value: 0000h
40–41h
Attribute:
Size:
R/W
16 bits
Bits
Description
Disable PCLKOUT [5:0] (DPCLK)—R/W.
0 = Enable.
15:10
1 = Disable. Disables a PCI clock output that is not used in the system. Bit 15 refers to
PCLKOUT5, bit 14 to PCLKOUT4, etc. When disabled, the PCLKOUT pin is tri-stated.
Enable I/O Space to 1 KB Granularity (EN1K)—R/W.
0 = Disable
9
8
1 = Enable. I/O space is decoded to 1 KB instead of the 4 KB limit that currently exists in the I/O
base and I/O limit registers. It does this by redefining bits [11:10] and bits [3:2] of the
IOBL_ADR Register (offset 1Ch) to be read/write, and enables them to be compared with
the I/O address bits [11:10] to determine if they are within the bridge’s I/O range.
PCI Mode (PMODE)—R/W.
0 = Bus is in PCI mode.
1 = Bus is operating in PCI-X mode.
PCI Frequency (PFREQ)—R/W. This field determines the frequency the PCI bus operates. After
software determines the busses capabilities, it sets this value and the PMODE (bit 8 of this
register) to the desired frequency and resets the PCI bus.
00 = 33 MHz (Only valid if PMODE is 0)
01 = 66 MHz
7:6
10 = 100 MHz (Only valid if PMODE is 1)
11 = 133 MHz (Only valid if PMODE is 1)
Invalid combinations should not be written by software. Results will be indeterminate.
Restreaming Disable (RSDIS)—R/W.
0 = Enable.
5
1 = Disable. This bridge of the P64H2 will no longer perform restreaming. This bit only applies
when the bridge is in PCI mode, and not when the bridge is in PCI-X mode. When the PCI
transaction ends, either due to a PCI master removing PxFRAME# or the P64H2 asserting
PxSTOP#, the P64H2 will discard all data in the prefetch buffer.
Prefetch Policy (PP)—R/W. This field controls how the P64H2 prefetches data on behalf of PCI
masters.
4:3
0x = Allow prefetching on memory read multiple (MRM)
1x = Disable all prefetching
Intel® 82870P2 P64H2 Datasheet
51
Register Description
R
Bits
Description
Delayed Transaction Depth (DTD)—R/W. This bit controls the number and size of P64H2’s
delayed transaction butters. This bit should be left at its default of 0b.
2
0 = 4 Delayed Transaction Buffers (each 1024 bytes) when 33/66 MHz;
2 Delayed Transaction Buffers (each 2048 bytes) when 100/133 MHz
1 = 4 Delayed Transaction Buffers, each at 1024 bytes at all frequencies
Maximum Delayed Transactions (MDT)—R/W. This field controls the maximum number of
delayed transactions the P64H2 is allowed to have.
1:0
00 = 4 active, 4 pending
10 = 2 active, 2 pending
01 = 1 active, 1 pending
11 = Reserved
3.2.23
MTT—Multi-Transaction Timer Register (D29,31: F0)
Offset:
Default Value: 00h
42h
Attribute:
Size:
R/W
8 bits
This register controls the amount of time that the P64H2’s arbiter allows a PCI initiator to perform
multiple back-to-back transactions on the PCI bus. The number of clocks programmed in the
Multi-Transition Timer represents the guaranteed time slice (measured in PCI clocks) allotted to
the current agent, after which the arbiter will grant another agent that is requesting the bus.
Bits
Description
Timer Count Value (MTC). This field specifies the amount of time that grant remains asserted to
a master continuously asserting its request for multiple transfers. This field specifies the count in
an 8-clock (PCI clock) granularity.
7:3
2:0
Reserved
3.2.24
STRP—PCI Strap Status Register (D29,31: F0)
Offset:
44h–47h
Attribute:
Size:
RO
32 bits
Default Value: 00000000h
This register indicates the states of various straps for this PCI interface.
Bit
Description
31:2
Reserved
HPCAP. This bit indicates the state of the HPx_SLOT straps for this interface.
0 = Strap is 000
1
0
1 = Strap is 001 through 111
EN133. This bit indicates the state of the Px_EN133 strap for this interface.
52
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.2.25
PX_CAPID—PCI-X Capabilities Identifier Register
(D29,31: F0)
Offset:
Default Value: 07h
50h
Attribute:
Size:
RO
8 bits
This register identifies this item in the Capabilities list as a PCI-X register set. It returns 07h when
read.
Bits
Description
7:0
Identifier (ID). This field has a value of 07h that indicates this is a PCI-X capabilities list.
3.2.26
PX_SSTS—PCI-X Secondary Status Register (D29,31: F0)
Offset:
Default Value: 0003h
52–53h
Attribute:
Size:
R/WC, RO
16 bits
This is the PCI-X command register, which controls various modes of the bridge.
Bits
Description
15:9
Reserved
Secondary Clock Frequency (SCF)—RO. This field is set with the frequency of the secondary
bus.
Bits
000
001
010
011
1xx
Max Frequency
PCI Mode
66 MHz
Clock Period
N/A
8:6
15
100 MHz
10
133 MHz
7.5
Reserved
Reserved
Split Request Delayed. (SRD)—RO. Hardwired to 0. This bit is intended to be set by a bridge if
it cannot forward a transaction on the secondary bus to the primary bus because there is not
enough room within the limit specified in the Split Transaction Commitment Limit field in the
Downstream Split Transaction Control Register. The Intel® P64H2 never sets this bit.
5
4
Split Completion Overrun (SCO)—RO. Hardwired to 0. This bit is intended to be set if a bridge
terminates a Split Completion on the secondary bus with retry or Disconnect at the next ADB
because its buffers are full. The P64H2 never sets this bit.
Unexpected Split Completion (USC)—R/WC.
0 = No unexpected split completion received.
1 = This bit is set if an unexpected split completion with a requester ID equal to the P64H2’s
secondary bus number, device number 00h, and function number 0 is received on the
secondary interface.
3
Note: Software clears this bit by writing a 1 to it.
Intel® 82870P2 P64H2 Datasheet
53
Register Description
R
Bits
Description
Split Completion Discarded (SCD)—R/WC.
0 = No split completion discarded.
2
1 = P64H2 discarded a split completion moving toward the secondary bus because the
requester would not accept it.
Note: Software clears this bit by writing a 1 to it.
133 MHz Capable (C133)—RO. Hardwired to 1; indicates that the P64H2’s secondary interface
is capable of 133 MHz operation in PCI-X mode.
1
0
64-bit Device (D64)—RO. Hardwired to 1; indicates the width of the secondary bus as 64-bits.
3.2.27
PX_BSTS—PCI-X Bridge Status Register (D29,31: F0)
Offset:
54–57h
Attribute:
RO
Default Value: 000100F8h (PCI Bus A) Size:
000100E8h (PCI Bus B)
32 bits
This register identifies PCI-X capabilities and current operating mode of the bridge.
Bits
Description
31:22
Reserved
Split Request Delayed (SRD). Hardwired to 0. This bit is not supported by the Intel® P64H2,
because it will never be in a position where it cannot issue a request.
21
20
Split Completion Overrun (SCO). Hardwired to 0. This bit is not set by the P64H2 because the
P64H2 never requests on the hub interface more data than it has room to receive.
Unexpected Split Completion (USC). Hardwired to 0. This does not apply to the hub interface,
which is the primary interface.
19
18
17
Split Completion Discarded (SCD). Hardwired to 0. This does not apply to the hub interface.
133 MHz Capable (C133). Hardwired to 0. This bit indicates that the bridge’s primary interface is
capable of 133 MHz operation in PCI-X mode.
64-bit Device (D64). Hardwired to 1. The hub interface is a 64-bit interface (in Hub Interface2.0,
it really is 128-bits). This field really does not apply to the hub interface, but is set to 1 to be safe
in case some software gets written.
16
15:8
Bus Number (BNUM). This field is an alias to the PBN field of the BNUM register at offset 18h.
Device Number (DNUM). This field provides read only bits for PCI-X
For PCI Bus A, this field defaults to 1Fh (device 31).
7:3
2:0
For PCI Bus B, this field defaults to 1Dh (device 29).
Function Number (FNUM). This field provides additional read only bits for PCI-X. These bits are
typically used by PCI-X diagnostic software.
54
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.2.28
PX_USTC—PCI-X Upstream Split Transaction Control
Register (D29,31: F0)
Offset:
58–5B
Attribute:
Size:
R/W, RO
32 bits
Default Value: 0000FFFFh
This register controls the behavior of the P64H2’s buffers for forwarding Split Transactions from
the secondary bus to the hub interface.
Bits
Description
Split Transaction Limit (STL)—R/W. This field is not used by the Intel® P64H2 for modifying its
"commitment" level. The P64H2 internal launch algorithms keep buffers from being over
allocated. These read/write bits are provided for PCI-X diagnostic software.
31:16
Split Transaction Capacity (STC)—RO. The P64H2 essentially has infinite capacity, because
its launch algorithm keeps buffers from overrunning.
15:0
3.2.29
PX_DSTC—PCI-X Downstream Split Transaction Control
Register (D29,31: F0)
Offset:
5C–5Fh
Attribute:
Size:
R/W, RO
32 bits
Default Value: 0000FFFFh
This register controls behavior of the P64H2 buffers for forwarding Split Transactions from the
hub interface to the secondary bus.
Bits
Description
Split Transaction Limit (STL)—R/W. This field is not used by the Intel® P64H2 for modifying its
"commitment" level. P64H2 internal launch algorithms keep buffers from being over allocated.
31:16
Split Transaction Capacity (STC)—RO. The P64H2 essentially has infinite capacity, because
its launch algorithm keeps buffers from overrunning.
15:0
Intel® 82870P2 P64H2 Datasheet
55
Register Description
R
3.2.30
RAS_STS—RAS Status Register (D29,31: F0)
Offset:
Default Value: xxxxxxh
60–62h
Attribute:
Size:
R/W, R/WC, RO
24 bits
This register contains information relating to internal errors (soft errors) or errors on the hub
interface and PCI for this bridge. Note that all RAS registers are not reset and are sticky through
reset. Initialization software must clear bits [5:0] and bits [13:8] of this register at power-on reset
to assure that no false errors are logged by system management logic.
Bits
Description
PCI Agent of Failure (PAGT)—RO. This filed indicates which agent was active when the PCI
failure occurred. This field is only valid if the AEP, DEP, or DEBO bits in this register are set.
000 = REQ0
001 = REQ1
010 = REQ2
011 = REQ3
100 = REQ4
101 = REQ5
110 = Reserved
111 = P64H2
23:21
Hub Interface Failure Agent (HAGT)—RO. This bit indicates which one of the hub interface
agents is the cause of the failure. This bit is only valid when the AEHM, AEHS, DEBI, DEHM, or
DEHS bits are set. This bit is only visible from device 31.
20
0 = P64H2 generated the failing request.
1 = MCH generated the failing request.
Reserved
19:16
15
Enable Non-fatal Errors (ENFE)—R/W. This bit enables bits 8 to 13 and bits 0 and 2 if bit 14 is
set to participate in generating RASERR#. This bit has no effect on logging of errors. When
cleared, if bits 8 to 13 are set or bits 0 and 2 if bit 14 is set, RASERR# is not generated.
Data Parity Errors are Non-Fatal (DPENF)—R/W. This bit does not affect data parity errors
from internal buffers that are always fatal errors. The DPENF bits must be programmed to the
same value for both bridges. The Intel® P64H2 hub interface logic will use only the value from
device 31.
14
0 = PCI data parity errors and hub interface parity/multi-bit ECC data errors are treated as fatal
errors. (default)
1 = PCI data parity errors and hub interface data parity/multi-bit ECC errors are treated as non-
fatal errors.
Hub Interface Target Abort (HTA)—R/WC. This bit is only visible from device 31.
0 = No hub interface target abort received.
13
1 = P64H2 generated a request on the hub interface and received a target abort.
Note: Software clears this bit by writing a 1 to it.
56
Intel® 82870P2 P64H2 Datasheet
Register Description
R
Bits
Description
Hub Interface Master Abort (HMA)—R/WC. This bit is only visible from device 31.
0 = No hub interface master abort received.
12
1 = Intel® P64H2 generated a request on the hub interface and received a master abort
completion.
Note: Software clears this bit by writing a 1 to it.
PCI Target Abort (PTA)—R/WC.
0 = No PCI target abort received.
1 = P64H2 generated a cycle on PCI and received a target abort from a PCI target. It does not
set it for generating target aborts, because the only time this occurs is if there was a master
abort on the peer PCI agent or on the hub interface. In the case of peer PCI, the PRMA bit
will be set in the peer interface, and in the case of the hub interface, the HMA bit will have
been set.
11
Note: Software clears this bit by writing a 1 to it.
PCI Received Master Abort (PRMA)—R/WC.
0 = No master abort received.
10
1 = This bit indicates that the P64H2 generated a cycle on PCI and received a master abort.
Note: Software clears this bit by writing a 1 to it.
Single-bit ECC Address Error in from the Hub Interface (AEHS)—R/WC. This bit is only
visible from device 31.
0 = No single-bit ECC address error detected.
9
1 = Packet arrived on the hub interface that had a single-bit ECC error in the command phase
(address / header).
Note: Software clears this bit by writing a 1 to it.
Single-bit ECC Data error in from the Hub Interface (DEHS)—R/WC. This bit is only visible
from device 31.
0 = No single-bit ECC data error detected.
8
7
1 = P64H2 generated a cycle on the hub interface with a single-bit ECC error, or received a
packet on the hub interface with a single-bit ECC error.
Note: Software clears this bit by writing a 1 to it.
Reserved
Register Data Parity Error (RDPE)—R/WC.
0 = No register data parity error detected.
1 = Write with data parity error happens to any internal register (configuration or memory
mapped or I/O mapped) associated with this bridge. This includes the bridge registers, hot
plug registers, and APIC registers. This bit is not set if P64H2 is not the consumer of the
data and is simply forwarding the bad data across the bridge.
6
5
Note: Software clears this bit by writing a 1 to it.
Address parity error in from PCI (AEP)—R/WC.
0 = No address parity error detected.
1 = Address parity error was detected on PCI.
Note: Software clears this bit by writing a 1 to it.
Intel® 82870P2 P64H2 Datasheet
57
Register Description
R
Bits
Description
Address Parity / Multi-bit ECC Error in from the Hub Interface (AEHM)—R/WC. This bit is
only visible from device 31.
0 = No address parity / multi-bit ECC error detected.
4
1 = Packet arrived on the hub interface that had a parity / multi-bit ECC error in the command
phase (address / header).
Note: Software clears this bit by writing a 1 to it.
Inbound Data Parity from Internal Buffers (DEBI)—R/WC.
0 = No inbound data soft error detected.
3
2
1
1 = Soft error was detected in the internal buffer on data flowing inbound from a PCI cycle.
Note: Software clears this bit by writing a 1 to it.
Data Parity in from PCI (DEP)—R/WC.
0 = No data parity error calculated.
1 = Data parity error was calculated on an P64H2 read from PCI or a write from PCI
Note: Software clears this bit by writing a 1 to it.
Outbound Data Parity Error from Internal Buffers (DEBO)—R/WC.
0 = No outbound data soft error detected.
1 = Soft error occurred in the internal SRAM on data headed outbound to PCI.
Note: Software clears this bit by writing a 1 to it.
Data Parity / Multi-bit ECC Error in from the Hub Interface (DEHM)—R/WC. This bit is only
visible from device 31.
0 = No data parity / multi-bit ECC error detected.
0
1 = P64H2 received a packet on the hub interface with a data parity / multi-bit ECC error.
Note: Software clears this bit by writing a 1 to it.
58
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.2.31
RAS_DI—RAS Data Integrity Codes Register (D29,31: F0)
Offset:
Default Value: xxxxxxh
64–66h
Attribute:
Size:
RO
24 bits
This register contains the ECC and parity bit information from the failed cycle.
Bits
Description
23:19
Reserved
PCI-X Attribute Parity (PP). This bit represents the parity detected in the attribute phase of a
request and completion. When the Intel® P64H2 is driving, it is the value driven. When the
P64H2 is receiving, it is the value captured.
18
17
PCI Address High (PAH). This bit represents the parity detected in the second phase (upper
32-bits) of a dual address cycle. It is forced to 0 if the address was a single address cycle. When
the P64H2 is driving, it is the value driven. When the P64H2 is receiving, it is the value captured.
PCI Address Low (PAL). For PCI-X requests and all PCI cycles, this bit represents the parity
detected in the first phase (lower 32-bits) of a dual address cycle, or just the address of a regular
address cycle. For PCI-X completions, this bit represents the first clock (requester attributes)
driven in the completion cycle. When the P64H2 is driving, it is the value driven. When the
P64H2 is receiving, it is the value captured.
16
Hub Interface Data Integrity (HDI). This field is only visible from device 31.This field is only
valid if the AEHS, AEHM, DEHM, DEHS, or DEBI bits are set in the RAS_STS Register (60h).
This field contains the captures the hub interface ECC or parity code of the failure. Only bit '0' is
used if in parity mode for Hub Interface2.0.
15:0
If the type of error is an address error, then this is the code for the header that failed. If the type
of error is a data error, then this is the code for the data that failed.
3.2.32
RAS_PH—RAS PCI Header Register (D29,31: F0)
Offset:
Default Value: xxxxh
6C–6Dh
Attribute:
Size:
RO
16 bits
This register contains the PCI header information from a PCI failure. The bits in this register are
only valid if the AEP, DEP, PRTA, PRMA, or DEBO bits are set in the RAS_STS Register (60h).
Bits
Description
15:12
11:8
Reserved
PCI Command (PCMD). This field logs the command of the PCI bus when there is a failure.
PCI Byte Enables (PBE). This field contains the 8-byte enables, which are part of the error. If
the cycle was only in 32-bit mode, then only the low 4 bits are valid.
7:0
Intel® 82870P2 P64H2 Datasheet
59
Register Description
R
3.2.33
RAS_PAL—RAS PCI Address Low Register (D29,31: F0)
Offset:
Default Value: xxxxxxxxh
70–73h
Attribute:
Size:
RO
32 bits
This register contains the low 32 bits of address from the PCI header.
Bits
Description
Address - low 32 bits (ADR). This field is only valid if the AEP, DEP, PRTA, PRMA, or DEBO
bits are set in the RAS_STS Register (60h).
31:0
3.2.34
RAS_PAH—RAS PCI Address High Register (D29,31: F0)
Offset:
Default Value: xxxxxxxxh
74–77h
Attribute:
Size:
RO
32 bits
This register contains the upper 32 bits of address from the PCI cycle.
Bits
Description
Address - High 32 bits (ADR). This field is only valid if the AEP, DEP, PRTA, PRMA, or DEBO
bits are set in the RAS_STS Register (60h). If an address parity error occurred during a single
address cycle, then these bits will be forced to 0s. Reliability Availability Serviceability software
must assume that if these bits are 0s, the cycle was a single address cycle.
31:0
3.2.35
RAS_PDL—RAS PCI Data Low 32 Bits Register
(D29,31: F0)
Offset:
Default Value: xxxxxxxxh
78–7Bh
Attribute:
Size:
RO
32 bits
This register provides the low 32 bits of data from the PCI cycle.
Bits
Description
PCI Data - low 32 bits. (DTA). This field is only valid if the AEP, DEP, PRTA, PRMA, or DEBO
bits are set in the RAS_STS Register (60h). This field will contain the 32-bit value driven during
the attribute phase on all attribute parity errors. This field is not valid for parity errors that occur
during the address phase.
31:0
60
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.2.36
RAS_PDH—RAS PCI Data High 32 bits Register
(D29,31: F0)
Offset:
Default Value: xxxxxxxxh
7C–7Fh
Attribute:
Size:
RO
32 bits
This register contains the upper 32 bits of PCI data.
Bits
Description
PCI Data – High 32 bits (DTA). This field is only valid if the AEP, DEP, PRTA, PRMA, or DEBO
bits are set in the RAS_STS Register (60h).
31:0
3.2.37
RAS_HH—RAS Hub Interface Header Register (D29,31: F0)
Offset:
Default Value: xxxxxxxxh
80–83h
Attribute:
Size:
RO
32 bits
This register contains information from the first 32 bits of the hub interface header packet. This
represents the entire header as seen on the hub interface – including reserved bits. This field is
only visible from device 31.
Bits
Description
Header (HDR). This field contains the 32-bit header of the hub interface packet. It is only valid if
the AEHM, AEHS, DEHM, DEHS, DEBI, HTA, or HMA bits are set in the RAS_STS Register
(60h).
31:0
3.2.38
RAS_HAL—RAS Hub Interface Address Low 32 Bits
Register (D29,31: F0)
Offset:
Default Value: xxxxxxxxh
84–87h
Attribute:
Size:
RO
32 bits
This register contains information related to the low 32-bits of the hub interface packet address.
This represents the entire address as seen on the hub interface – including bits [1:0].
Bits
Description
Low 32-bits of Address (ADR). This field is only visible from device 31. The field contains the
low 32-bits of the address from the hub interface packet. On read completion packets, where no
address is sent on the hub interface, the address from the perceived destination (based upon the
Hub ID / Pipe ID) is used. This field is only valid if the AEHM, AEHS, DEHM, DEHS, HTA, or
HMA bits are set in the RAS_STS Register (60h).
31:0
Intel® 82870P2 P64H2 Datasheet
61
Register Description
R
3.2.39
RAS_HAH—RAS Hub Interface Address High 32 Bits
Register (D29,31: F0)
Offset:
Default Value: xxxxxxxxh
88–8Bh
Attribute:
Size:
RO
32 bits
This register contains information from the high 32 bits of the hub interface packet address.
Bits
Description
High 32-bits of Address (ADR). This field is only visible from device 31. The field contains the
high 32-bits of the address from the hub interface header. On read completion packets, where
the hub interface agent transmits no address, the perceived destination (based upon the Hub
ID / Pipe ID) is used. This field is only valid if the AEHM, AEHS, DEHM, DEHS, HTA, or HMA
bits are set in the RAS_STS Register (60h).
31:0
3.2.40
RAS_HP—RAS Hub Interface Prefetch Horizon Register
(D29,31: F0)
Offset:
Default Value: xxxxxxxxh
8C–8Fh
Attribute:
Size:
RO
32 bits
This register contains the information from the prefetch horizon field of the packet. This represents
the entire 32-bit field, not just the valid bits from the horizon.
Bits
Description
Prefetch Hint (Hint). This field is only visible from device 31. The field contains the prefetch hint
transmitted on the hub interface. Even though only various bits of this field are valid as prefetch
hint, since ECC and parity are calculated over the entire range, all bits must be captured when
there is an error. This field is only valid if the AEHM, AEHS, DEHM, DEHS, HTA, or HMA bits are
set in the RAS_STS Register (60h).
31:0
3.2.41
RAS_D0—RAS Hub Interface DWord 0 Register
(D29,31: F0)
Offset:
Default Value: xxxxxxxxh
90–93h
Attribute:
Size:
RO
32 bits
Bits
Description
DWord 0 (D0). This field is only visible from Device 31. The field contains the 1st DWord of data
received from the hub interface. This field is only valid if the DEHM or DEHS bits are set in the
RAS_STS Register (60h).
31:0
62
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.2.42
3.2.43
3.2.44
RAS_D1—RAS Hub Interface DWord 1 Register
(D29,31: F0)
Offset:
Default Value: xxxxxxxxh
94–97h
Attribute:
Size:
RO
32 bits
Bits
Description
DWord 1 (D1). This field is only visible from Device 31. The field contains the 2nd DWord of data
received from the hub interface. This field is only valid if the DEHM or DEHS bits are set in the
RAS_STS Register (60h).
31:0
RAS_D2—RAS Hub Interface DWord 2 Register
(D29,31: F0)
Offset:
Default Value: xxxxxxxxh
98–9Bh
Attribute:
Size:
RO
32 bits
Bits
Description
DWord 2 (D2). This field is only visible from Device 31. The field contains the 3rd DWord of data
received from the hub interface. This field is only valid if the DEHM or DEHS bits are set in the
RAS_STS Register (60h).
31:0
RAS_D3—RAS Hub Interface DWord 3 Register
(D29,31: F0)
Offset:
Default Value: xxh
9C–9Dh
Attribute:
Size:
RO
16 bits
Bits
Description
DWord 3 (D3). This field is only visible from Device 31. The field contains the 4th DWord of data
received from the hub interface. This field is only valid if the DEHM or DEHS bits are set in the
RAS_STS Register (60h).
15:00
Intel® 82870P2 P64H2 Datasheet
63
Register Description
R
3.2.45
ACNF—Additional P64H2 Configuration Register
(D29,31: F0)
Offset:
E0–E3h
Attribute:
Size:
R/W
32 bits
Default Value: 0000000Fh
Bits
Description
31:16
Reserved
Write Starvation Enable (WSE). Only the value from PCI Bus A (device 31) will be used.
0 = No write starvation control logic will be activated.
15
1 = The Intel® P64H2 will activate logic to prevent write, read, completion, and other posted
request starvation of PCI devices.
Read Starvation Enable (RSE). Only the value from PCI Bus A (device 31) will be used.
0 = No read starvation control logic will be activated.
1 = The P64H2 will activate logic to prevent read starvation of PCI devices.
Reserved
14
13:12
Disable RCOMP Calibration Pattern Detection Logic (DISRCPD). The P64H2 has logic to end
the RCOMP calibration when a pattern of 1-0-1-0-1 is detected.
11
0 = The pattern detection is disabled and the RCOMP calibration does not end when a pattern of
1-0-1-0-1 is detected. (default)
1 = Enables the pattern detection logic to potentially end calibration early.
Reserved
10
9
Outbound First Data. Only the value from PCI bus A (Device 31) will be used.
1 = If this bit is 1 and the P64H2 is running in Hub Interface 2.0 mode, the P64H2 will enqueue
it’s read completion and write request command with the first DWord of data in a 64 byte
cache line.
Outbound Bypass. Only the value from PCI bus A (Device 31) will be used.
1 = If this bit is 1 and the P64H2 is running in Hub Interface 2.0 mode, the P64H2 will bypass it’s
outbound read and write command queues and write/read completion data queue if they are
empty.
8
7
6
Inbound Bypass. Only the value from PCI bus A (Device 31) will be used.
1 = P64H2 bypasses its inbound read command queue, if empty.
Peer Memory Read Enable (PMRE). Both bridges must program this bit to the same value;
however, the value from PCI A (device 31) will be used for all devices, except device 30.
0 = Normal operation. Peer memory reads are not allowed and all memory reads from the PCI
bridge will be sent to the hub interface regardless of address.
Inbound Pending Queue Bypass.
5
1 = P64H2 bypasses its read pending queue, if empty. This bit can only be set to 1 if in PCI
mode.
64
Intel® 82870P2 P64H2 Datasheet
Register Description
R
Bits
Description
Synchronous PXPCLKI to CLK66 (SYNCPH).
0 = PCI/PCI-X input clock will be considered asynchronous.
1 = If 1, the PCI/PCI-X input clock, PXPCLKI, will be considered a synchronous clock relative to
the hub interface input clock, CLK66.
4
Note: This bit must not be set to 1 if operating in 100 MHz or 133 MHz mode. It may be set to 0
if operating at 33 MHz or 66 MHz mode and if the clock meets the requirements laid out
in Section 4.8.
Maximum Outstanding Requests (MAXR). Only the value from PCI bus A (Device 31) will be
used. This field specifies the maximum number of completion required requests the P64H2 can
issue on the hub interface.
0000 = 1 request
0001 = 2 requests
0010 = 3 requests
…
3:0
1111 = 16 requests (default)
Intel® 82870P2 P64H2 Datasheet
65
Register Description
R
3.2.46
PCC—PCI Delay Compensation Control Register
(D29,31: F0)
Offset:
Default Value: 0000h
E4–E5h
Attribute:
Size:
R/W
16 bits
This register controls PCI buffer delay compensation. There is one register per PCI interface.
Bits
Description
15:14
Oscillator Control (OSC). This field controls the compensation delay oscillator.
Compensation Decoder Shift (CDS). This field shifts the output of the compensation decoder.
00 = No shift (default)
13:12
11:10
01 = Increase delay by 1
10 = Increase delay by 2
11 = Decrease delay by 1
PCI-X Bias Control (XBC). This field controls PCI-X Capability Detect Biases.
00 = No Shift (default)
01 = Lower references
10 = Increase references
11 = Further increase
Compensation Disable (CD). This bit disables the compensation logic.
9
8
0 = Enable
1 = Disable
Bypass Enable (BE). This bit enables the bypass values in bits [7:0] of this register to be used
instead of the internally generated compensation value.
0 = Disable
1 = Enable
Bypass Value (BV). This field contains the bypass value to be used to override the internal
compensation value when bypass is enabled through bit 8 of this register (the Bypass Enable
bit). When the Bypass Enable bit is 0, a read of these bits reflect the current state of the
compensation circuit.
7:0
66
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.2.47
HCCR—Hub Interface Command/Control Register
(D29,31: F0)
Offset:
F0–F3h
Attribute:
Size:
R/W, RO
32 bits
Default Value: 00000000h
Bits
Description
31:20
19:16
15:06
Reserved
Hub Interface Time Slice (HITS)—R/W. Only the value from PCI bus A (Device 31) will be used.
This field sets the hub interface arbiter time-slice value with a 4 base-clock granularity. A value of
0h means that the time-slice is immediately expired and that the Intel® P64H2 will allow the other
master's request to be serviced after every message.
Reserved
ECC Mode (ECC)—RO. Only the value from PCI bus A (Device 31) is valid. This bit indicates
whether the P64H2 is operating in ECC mode or in parity mode. It is set at reset based upon the
ECC negotiation.
5
4
0 = Parity Mode
1 = ECC mode
Reserved
Maximum Data Size (MAXD)—R/W. Only the value from PCI bus A (Device 31) will be used.
This field specifies the maximum size write a master should request in a single burst, as well as
the maximum optimal size read completion a target should return.
3:1
0
000 = 32 Bytes
001 = 64 Bytes
Others = 128 Bytes
Reserved
Intel® 82870P2 P64H2 Datasheet
67
Register Description
R
3.2.48
Prefetch Control Registers
The four prefetch control registers contain prefetch parameters. Each parameter is in 64-byte cache
line quantities. BIOS programs the values in these registers on power up. The values in the
registers are 0-based where a 0000b means 64 bytes, a 0001b means 128 bytes, etc.
Note: There is a fifth parameter in the prefetch algorithm called “D”. D is the delay to wait before
sending a Subsequent Request (RS) if prior Subsequent Requests (RS) still have not brought the
prefetch buffers above the Subsequent Threshold (TS). Its value is in PCI clocks and is the RS
field in the prefetch control registers with the value 111 appended to the beginning of the number
(i.e., RS:111). For example, IF RS = 0101b, then D = 0101111b.
Note: For Memory Read (MR) and Memory Read Line (MRL) commands in PCI, no prefetching is
performed. A fetch of 1 cache line (based on the cache line size register) is performed and when it
drains, the delayed transaction is complete. A new delayed transaction will be established if the
master wished the burst to continue.
3.2.48.1
PC33—Prefetch Control for 33 MHz Register (D29,31: F0)
Offset:
Default Value: 1212h
F8–F9h
Attribute:
Size:
R/W
16 bits
Bits
Description
Subsequent Threshold (TS). This field represents the subsequent threshold size in 64-byte
cache lines.
15:12
11:8
Subsequent Request (RS). This field represents the subsequent request size in 64-byte cache
lines.
7:4
3:0
Initial Threshold (TI). This field represents the initial threshold size in 64-byte cache lines.
Initial Request (RI). This field represents the initial request size in 64-byte cache lines.
3.2.48.2
PC66—Prefetch Control for 66 MHz Register (D29,31: F0)
Offset:
Default Value: 3323h
FA–FBh
Attribute:
Size:
R/W
16 bits
Bits
Description
Subsequent Threshold (TS). This field represents the subsequent threshold size in 64-byte
cache lines.
15:12
11:8
Subsequent Request (RS). This field represents the subsequent request size in 64-byte cache
lines.
7:4
3:0
Initial Threshold (TI). This field represents the initial threshold size in 64-byte cache lines.
Initial Request (RI). This field represents the initial request size in 64-byte cache lines.
68
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.2.48.3
PC100—Prefetch Control for 100 MHz Register (D29,31: F0)
Offset:
Default Value: 7B7Bh
FC–FDh
Attribute:
Size:
R/W
16 bits
Bits
Description
Subsequent Threshold (TS). This field represents the subsequent threshold size in 64-byte
cache lines.
15:12
11:8
Subsequent Request (RS). This field represents the subsequent request size in 64-byte cache
lines.
7:4
3:0
Initial Threshold (TI). This field represents the initial threshold size in 64-byte cache lines.
Initial Request (RI). This field represents the initial request size in 64-byte cache lines.
3.2.48.4
PC133—Prefetch Control for 133 MHz Register (D29,31: F0)
Offset:
Default Value: BFFFh
FE–FFh
Attribute:
Size:
R/W
16 bits
Bits
Description
Subsequent Threshold (TS). This field represents the subsequent threshold size in 64-byte
cache lines.
15:12
11:8
Subsequent Request (RS). This field represents the subsequent request size in 64-byte cache
lines.
7:4
3:0
Initial Threshold (TI). This field represents the initial threshold size in 64-byte cache lines.
Initial Request (RI). This field represents the initial request size in 64-byte cache lines.
Intel® 82870P2 P64H2 Datasheet
69
Register Description
R
3.3
Hot Plug Controller Registers (Device 31)
The P64H2 hot plug controller allows PCI card removal, replacement and addition without
powering down the system. There are two hot plug controllers that are located on the secondary
bus; one for PCI Bus A and the other for PCI Bus B. The hot plug controller contains both PCI
Configuration registers and memory space registers. The MBAR Register (PCI offset 10h) and
MBARU Register (PCI offset 14h) provide the base address for the memory space registers.
3.3.1
PCI Configuration Registers
Table 16. Hot Plug Controller PCI Configuration Address Map (Device 31)
Address
Offset
Access
Symbol
Register Name
Default
00–01h
02–03h
04–05h
06–07h
08h
VID
DID
Vendor ID
Device ID
8086h
1462h
00h
RO
RO
PCICMD
PCISTS
RID
PCI Command
R/W, RO
R/WC, RO
RO
PCI Status
0230h
11h
Revision ID
09–0Bh
10–13h
14–17h
2C–2Dh
2E–2Fh
34h
CC
Class Code
840h
RO
MBAR
MBARU
SVID
Memory Base
0000000Ch
00000000h
0000h
0000H
64h
R/W, RO
R/W
Memory Base Upper 32-bits
Subsystem Vendor ID
Subsystem ID
R/WO
R/WO
RO
SID
CAP_PTR
INTR
Capabilities Pointer
Interrupt Information
Slot ID
3C–3Dh
40h
0100h
00h
R/W, RO
R/W
SID
41h
HPFC
Ho Plug Frequency Control
00h
R/W
R/W, R/WO,
RO
42–43h
MCNF
Miscellaneous Configuration
00X3h
44–45h
46h
FTR
SSEL
SSTS
SERR
MIDX
MDTA
XID
Features
0000h
00H
R/W
R/W
RO
Slot Status Select
Slot Status
47h
XXh
48–4Ah
50h
SERR Status
00h
R/WC
R/W
R/W
RO
Alternate Memory Access Index Port
Alternate Memory Access Data Port
PCI-X Identifiers
00h
54–57h
64–65h
66–67h
68–6Bh
80–81H
00000000h
0007h
0000h
0003XXF8h
0000h
XCR
PCI-X Command
PCI-X Status
RO
XSR
RO
ABAR
Alternate Base
R/W
70
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.1.1
3.3.1.2
3.3.1.3
VID—Vendor ID Register (Device 31)
Offset:
Default Value: 8086h
00–01h
Attribute:
Size:
RO
16 bits
Bits
Description
15:0
Vendor ID (VID): Indicates that Intel was the vendor of this controller.
DID—Device ID Register (Device 31)
Offset:
Default Value: 1462h
02–03h
Attribute:
Size:
RO
16 bits
Bits
Description
15:0
Device Identifier (DID): Indicates the device number of this controller.
PCICMD—PCI Command Register (Device 31)
Offset:
Default Value: 00h
04–05h
Attribute:
Size:
R/W, RO
16 bits
Bits
Description
15:10
9
Reserved
Fast Back-to-Back Enable (FBE)—RO. Hardwired to 0. Reserved.
PxSERR# Enable (SEE)—R/W.:
0 = Disable. (Default)
8
7
6
1 = Enable. Intel® P64H2 hot plug controller is allowed to generate PxSERR# on any event that is
enabled for PxSERR# generation.
Wait Cycle Enable (WCC)—RO. Reserved.
Parity Error Response Enable (PEE)—R/W.
0 = Disable. (Default)
1 = Enable. P64H2 hot plug controller will generate PxSERR# when a data parity error is detected
and SEE (bit 8) is set.
5
4
3
2
VGA Palette Snooping Enable (VGA)—RO. Hardwired to 0. Reserved.
Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0. Reserved.
Special Cycle Enable (SCE)—RO. Hardwired to 0. Reserved.
Bus Master Enable (BME)—R/W.: Hardwired to 0. Reserved.
Memory Space Enable: (MSE)—R/W.
0 = Disable. (Default)
1
0
1 = Enable. Memory space registers are accessible through the memory address range set by
MBAR and MBARU.
IO Space Enable: (IOSE)—RO. Hardwired to 0. Reserved.
Intel® 82870P2 P64H2 Datasheet
71
Register Description
R
3.3.1.4
PCISTS—PCI Status Register (Device 31)
Offset:
Default Value: 0230h
06–07h
Attribute:
Size:
R/WC, RO
16 bits
This register reports the status of PCI events generated by the hot plug controller.
Bits
Description
Detected Parity Error (DPE)—R/WC.
0 = No parity error detected.
15
1 = Intel® P64H2 hot plug controller detected a data parity error.
Note: Software clears this bit by writing a 1 to it.
Signaled System Error (SSE)—R/WC.
0 = No SERR# generated.
14
1 = P64H2 hot plug controller generates SERR#.
Note: Software clears this bit by writing a 1 to it.
Received Master Abort (RMA)—RO. Hardwired to 0; Reserved.
Received Target Abort (RTA)—RO. Hardwired to 0; Reserved.
Signaled Target Abort (STA)—RO. Hardwired to 0; Reserved.
13
12
11
DEVSEL timing (DVT)—RO. Hardwired to 10; indicates that the hot plug controller responds in
medium decode time.
10:9
8
7:6
5
Data Parity Detected (DPD)—RO. Hardwired to 0; Reserved
Reserved
66 MHz Capable (C66)—RO. Hardwired to 1; controller is capable of operating at 66 MHz.
Capabilities List Exists (CLIST)—RO. Hardwired to 1; indicates that this device supports a
capabilities list. The pointer to the first item is located at offset 34h.
4
3:0
Reserved
3.3.1.5
RID—Revision ID Register (Device 31)
Offset:
Default Value: 04h
08h
Attribute:
Size:
RO
8 bits
Indicates the revision of the hot plug controller.
Bits
Description
Revision ID (RID). This filed indicates the stepping of the Intel® P64H2.
7:0
03h = B0 Stepping
04h = B1 Stepping
72
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.1.6
CC—Class Code Register (Device 31)
Offset:
Default Value: 840h
09–0Bh
Attribute:
Size:
RO
24 bits
This register contains the base class, sub-class, and programming interface codes.
Bits
Description
Base Class Code (BCC).
23:16
08h = Generic system peripheral class device.
Sub Class Code (SCC).
15:8
7:0
04h = Generic PCI hot plug controller.
Programming Interface (PIF). The hot plug controller has no programming interface.
3.3.1.7
MBAR—Memory Base Register (Device 31)
Offset:
10–13h
Attribute:
Size:
R/W, RO
32 bits
Default Value: 0000000Ch
This register is used by the hot plug logic to request a 256-byte prefetchable memory space that
can be located anywhere in the 64-bit address space. Once programmed, the memory registers will
respond at this address. Bits 31:4 will be the lower 32-bits of the address. Offset 14h contains the
upper 32-bits of the base address.
Bits
Description
31:8
Base Address (BAR)—R/W. This field can be any value.
Memory Space Size (SIZE)—RO. Hardwired to 0; indicates 256-bytes of address space is
requested.
7:4
3
Prefetchable (PF)—RO. Hardwired to 1; indicates that the memory space is prefetchable.
Memory location (LOC)—RO. Hardwired to 10; the memory space can be located anywhere in
the 64-bit address space.
2:1
0
Indicator (IND)—RO. Hardwired to 0; indicates that the BAR is for memory space.
3.3.1.8
MBARU—Memory Base Address (Upper 32-bits) Register (Device 31)
Offset:
14–17h
Attribute:
Size:
R/W
32 bits
Default Value: 00000000h
Bits
Description
Upper 32-bits of Address (ADDR): These bits determine bits 63:32 of the base address.
31:0
Intel® 82870P2 P64H2 Datasheet
73
Register Description
R
3.3.1.9
SVID—Subsystem Vendor ID Register (Device 31)
Offset:
Default Value: 0000h
2C–2Dh
Attribute:
Size:
R/WO
16 bits
This value is used to identify the vendor of the subsystem.
Bits
Description
Subsystem Vendor ID (SSVID). This is written by BIOS. This field should be programmed
during bootup. Once written, this register becomes read only.
15:0
3.3.1.10
SID—Subsystem ID Register (Device 31)
Offset:
Default Value: 0000h
2E–2Fh
Attribute:
Size:
R/WO
16 bits
This value is used to identify a particular subsystem.
Bits
Description
Subsystem ID (SSID). This is written by BIOS. This field should be programmed during bootup.
Once written, this register becomes read only.
15:0
3.3.1.11
CAP_PTR—Capabilities Pointer Register (Device 31)
Offset:
Default Value: 64h
34h
Attribute:
Size:
RO
8 bits
Bits
Description
Pointer Value (PTR). This field indicates that offset 64h is the offset of the first capabilities item
in the capabilities list.
7:0
74
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.1.12
INTR—Interrupt Information Register (Device 31)
Offset:
Default Value: 0100h
3C–3Dh
Attribute:
Size:
R/W, RO
16 bits
This register contains information about how the P64H2 hot plug controller generates interrupts.
Note that internally, the controller interrupt is connected to the IRQ23# input of the APIC on the
same bus (A or B).
Bits
Description
Interrupt Pin (IPIN)—RO. This field indicates that the hot plug controller generates the INTA#
pin.
15:8
Interrupt Line (ILINE)—R/W. This field is programmed to indicate which interrupt line (vector)
the interrupt is connected to. No hardware action is taken on this register.
7:0
3.3.1.13
SID—Slot ID Register (Device 31)
Offset:
Default Value: 00h
40h
Attribute:
Size:
R/W
8 bits
This register indicates which slots in the system support hot plug. This register is aliased with a
register of the same name in memory space. No hardware action is taken by these bits.
Bits
Description
Lowest Device Number (DEV). This field provides the PCI device number for the first slot that
supports hot plug.
7:4
Number of Hot Plug Slots (NUM). This field provides the number of hot plug slots in the
system.
3:0
3.3.1.14
HPFC—Hot Plug Frequency Control Register (Device 31)
Offset:
Default Value: 00h
41h
Attribute:
Size:
R/W
8 bits
Bits
Description
7:4
3
Reserved. This field is R/W for software compatibility
Reserved. Read only
Frequency Select (FS). The Intel® P64H2 hot plug controller always uses a 66 MHz core clock
for its timings. These register bits are maintained as R/W for software compatibility.
2:0
Intel® 82870P2 P64H2 Datasheet
75
Register Description
R
3.3.1.15
MCNF—Miscellaneous Configuration Register (Device 31)
Offset:
Default Value: 00x3h
42–43h
Attribute:
Size:
R/W, R/WO, RO
8 bits
This register contains various miscellaneous information about the hot plug controller’s operation.
Bits
Description
Change Device ID (CDID)—R/WO. Not implemented. Bit is read/write for software compatibility.
Default = 0
15
Inhibit Hot Plug (IHP)—R/WO. Default = 0
14
13
1 = Prevents the hot plug memory map from being accessed. In this mode, reads to memory
registers will always return 0 and writes will have no effect.
Power Fault Enable (PFE)—R/W.
0 = Disable (Default)
1 = Enable. This bit must be set to enable SERR# on power-fault generation as well as scanning
power-fault latches. This bit is also mapped in the MCNF Register in memory space offset
02h, bit 10. In 2-slot or 1-slot parallel modes, the Intel® P64H2 will asynchronously
disconnect a slot's bus, clock, power, and assert the slot's PCIRST#, when the slot's power
fault signal is asserted. In any serial mode, logic must exist on the motherboard to perform
these asynchronous disconnects. Clearing this bit will also clear the internal power-fault
latches.
Auto Power-Down Disable Lock Enable (APDL)—R/WO.
0 = Disable (default)
12
11:8
7
1 = Enable. The auto-power-down disable bit of the hot plug miscellaneous register in memory
space becomes unchangeable and read only. This bit is write-once and cannot be changed
until RSTIN# assertion.
Reserved
PCI Configuration Space Access Enable (PCFE)—R/W.
0 = Disable (Default)
1 = Enable. When set, this bit enables configuration space access to memory space registers
using an index register and 32-bit data access port, located at configuration offsets 50h and
54h, respectively.
Dummy Cycle Enable (DCE)—R/W. Not implemented. This bit has no functionality, but is
maintained as read/write for software compatibility. (Default=0)
6
5
PCI-X Mode (MODE)—RO. This bit indicates the mode of the PCI-X bus it is connected to. The
default is determined by the PCI-X bus mode.
76
Intel® 82870P2 P64H2 Datasheet
Register Description
R
Bits
Description
Inhibit Bus Connect (IBC)—R/W. This bit controls the method in which cards will be powered up
following a cold boot.
0 = Hot plug slots will be fully enabled (Default). That is, the slots will be powered on, connected
to the bus and brought out of reset when the system software writes to configuration offset
43h.
4
1 = Hot plug slots will only be powered on when system software writes to configuration offset
43h. This feature can be used to more efficiently determine the state of the slot input pins
such as M66EN or PCIXCAP pins. Otherwise, the bus must be set to 33 MHz and a lengthy
power up sequence must be executed before the state of the slots can be inspected. After
the power enable only (no bus connect) power-up sequence, system software clears this bit
and writes to 43h again to fully enable the slots. The OOB bit is monitored to determine
when power sequences are complete.
Enable Master Abort Detection SERR (EMAS)—R/W.
3
2
0 = Disable (Default).
1 = SERR is generated when a PCI memory or I/O cycle is aborted by the PCI initiator.
Reserved
Enable CBL Power Sequencing Mode (CBLE)—R/W. When operating in one slot mode with no
isolation switches, software must not set this bit to 1 and must always use CBF mode.
1
0
0 = Disable. The power sequence state machine will connect the bus first. In CBF mode, bus
connect occurs before reset deassertion when powering up a slot.
1 = Enable. (Default)
On / Off Busy Status (OOB)—RO.
1 = Indicates the ON/OFF state machine is running. After RSTIN# is negated, this bit remains
set until the P64H2 updates the slot power, bus/clock enable, and reset controls for the first
time after software completes the initial write to configuration register offset 43h. (Default)
Note: This bit is the same as bit 8 in MCNF Register in memory space (offset 02h).
Intel® 82870P2 P64H2 Datasheet
77
Register Description
R
3.3.1.16
FTR—Features Register (Device 31)
Offset:
Default Value: 0000h
44–45h
Attribute:
Size:
R/W
16 bits
This is a read/write register with no functionality.
Bits
Description
15:0
Reserved
3.3.1.17
SSEL—Slot Status Select Register (Device 31)
Offset:
Default Value: 00h
46h
Attribute:
Size:
R/W
8 bits
Bits
Description
7:3
Reserved
Select (SEL). This 3-bit field selects a group of status information from one of six slots. Status for
the slot number selected is then accessible via the Slot Status Register. When this field is 000,
the Slot Status Register is said to be in “composite mode”.
000 = Composite for all Slots
001 = Slot A
010 = Slot B
2:0
011 = Slot C
100 = Slot D
101 = Slot E
110 = Slot F
111 = Reserved
78
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.1.18
SSTS—Slot Status Register (Device 31)
Offset:
Default Value: xxh
47h
Attribute:
Size:
RO
8 bits
Bits
Description
7
6
Reserved
PCIXCAP2 Status (P2S). This bit reflects the state of the hot plug PCIXCAP2 input for the
selected slot. In composite mode, this bit is an AND of all PCIXCAP2 status bits.
PCIXCAP1 Status (P1S). This bit reflects the state of the hot plug PCIXCAP1 input for the
selected slot. In composite mode, this bit is an AND of all PCIXCAP1 status bits.
5
4
3
2
1
0
M66EN Status (MS). This bit reflects the state of the hot plug M66EN input for the selected slot.
In composite mode, this bit is an AND of all M66EN bits.
PRSNT[1]# Status (T1S). This bit reflects the state of the hot plug PRSNT[1]# input for the
selected slot. In composite mode, this bit is an AND of all PRSNT[1]# status bits.
PRSNT[2]# Status (T2S). This bit reflects the state of the hot plug PRSNT[2]# input for the
selected slot. In composite mode, this bit is an AND of all PRSNT[2]# status bits.
Power Fault# Status (PFS). This bit reflects the state of the hot plug power fault input for the
selected slot. In composite mode, this bit is an AND of all Power Fault# status bits.
Slot Switch Status (SSS). This bit reflects the state of the hot plug switch for the selected slot.
(0 means switch closed). In composite mode, this bit is an AND of all slot switch status bits.
Intel® 82870P2 P64H2 Datasheet
79
Register Description
R
3.3.1.19
SERR—SERR Status Register (Device 31)
Offset:
Default Value: 00h
48–4Ah
Attribute:
Size:
R/WC
24 bits
Bits
Description
Arbiter Time-out SERR Status (ATS).
0 = No SERR was generated. (default)
23
1 = Indicates that a SERR was generated due to an arbitration time-out.
Note: Software clears this bit by writing a 1 to it.
Reserved
22:14
Power Fault SERR Status (PFS).
0 = These bits can be cleared by writing logic 1 to the bit. Should a conventional power fault
change interrupt also be pending for this slot, clearing the SERR status bit for the slot has
no effect on conventional PCI interrupts. (default)
1 = These 6 bits are mapped to SERR status bits for each slot and are set to logic 1 for the
respective slot (slot A is associated with the LSB) if a power fault occurs while a slot is
connected to the bus or PCI clock. For this function to be enabled, the power fault function
enable bit and the SERR on power fault bit must also be set in the memory mapped Hot
plug Miscellaneous Register.
13:8
Note: Software clears these bits by writing a 1 to it.
Reserved
7:6
5:0
Slot Switch Change Status (SCS).
0 = Clearing the SERR status bit for a slot also clears the interrupt pending latch and allows new
switch scan data to appear in the hot plug Interrupt Input and Clear Register (HMIC).
(default)
1 = These 6 bits are mapped to SERR status bits for each slot and are set to logic 1 for the
respective slot (slot A is associated with the LSB) if a switch changes state when the switch
interrupt redirect bit for that slot is also set and the associated interrupt mask bit is logic O.
Note: Software clears this bit by writing a 1 to it.
3.3.1.20
MIDX—Alternate Memory Access Index Port Register (Device 31)
Offset:
Default Value: 00h
50h
Attribute:
Size:
R/W
8 bits
When the "Enable PCI Configuration Space Access to Hot plug Registers" bit in the
Miscellaneous Hot Plug Configuration Register is set to 1, this register becomes functional.
Otherwise, this register is reserved, read only (0s).
Bits
Description
7:2
1:0
Memory Access Index (IDX). This field contains the memory register to access by the data port.
Reserved
80
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.1.21
MDTA—Alternate Memory Access Data Port Register (Device 31)
Offset:
54–57h
Attribute:
Size:
R/W
32 bits
Default Value: 00000000h
When the "Enable PCI Configuration Space Access to Hot Plug Registers" bit in the
Miscellaneous Hot Plug Configuration Register is set, this register becomes functional. Otherwise,
this register is reserved, read only (0s).
Bits
Description
Memory Access Port (DTA): This field contains hot plug read data from the offset in the index
register at offset 50h, and is the location for hot plug write data.
31:0
3.3.1.22
XID—PCI-X Identifiers Register (Device 31)
Offset:
Default Value: 0007h
64–65h
Attribute:
Size:
RO
16 bits
Bits
Description
15:8
7:0
Next Pointer (XNPTR): This field points to the next capabilities list pointer (empty)
Capability ID (XCID): Capabilities ID indicates PCI-X.
3.3.1.23
XCR—PCI-X Command Register (Device 31)
Offset:
Default Value: 0000h
66–67h
Attribute:
Size:
RO
16 bits
Bits
Description
15:0
Reserved
Intel® 82870P2 P64H2 Datasheet
81
Register Description
R
3.3.1.24
XSR—PCI-X Status Register (Device 31)
Offset:
68–6Bh
Attribute:
Size:
RO
32 bits
Default Value: 0003xxF8h
Bits
Description
31:21
20
Reserved
Device Complexity. Hardwired to 0; indicates that this is a simple device.
Unexpected Split Completion. Hardwired to 0. This device will never see an unexpected split
completion, as it never generates any master cycles besides posted writes for MSI.
19
18
17
16
Split Completion Discarded. Hardwired to 0; this device does not support Split Completion.
133 MHz Capable. Hardwired to 1; indicates this device is 133 MHz capable.
64-bit Device. Hardwired to 1; indicates that this is a 64-bit device.
Bus Number. These bits indicate the bus number of the bus segment for this device. This value
will match the ‘secondary bus number’ field from the attached bridge. (Default = xxh)
15:8
7:3
Device Number. Hardwired to 1Fh; reflects the device number that has been hard-coded for the
device.
Function Number. Hardwired to 000b; reflects the function number that has been hard-coded for
the device.
2:0
3.3.1.25
ABAR—Alternate Base Register (Device 31)
Offset:
Default Value: 0000h
80–81h
Attribute:
Size:
R/W
16 bits
This register selects an alternate base register location for the memory working registers. The base
starts at FECX_YZ00h, where "X", "Y", and "Z" are written into bits 11:0. Bit 15 enables this
range. If enabled, decode of the memory space at FECX_YZ00h is performed, even if the memory
space enable bit in the PCI header is not set.
Bits
Description
Enable (EN): This bit enables decode range at FECXYZ00 to FECX_YZFF.
15
0 = Disable. (default)
1 = Enable.
SCI Enable (SCI EN): This bit enables SCI to be generated as opposed to interrupt. When
interrupts are unmasked and are to be sent, the value of this bit will be checked before sending
the interrupt on. If this bit is 0, a normal interrupt (pin or MSI) will be generated. If this bit is 1, an
SCI pin will be generated. The pin is active low.
14
0 = Disable. (default)
1 = Enable.
13:12
11:8
7:4
Reserved
Address Compare [19:16] (X): This field is compared against address bits 19:16.
Address Compare [15:12] (Y): This field is compared against address bits 15:12.
Address Compare [11:8] (Z): This field is compared against address bits 11:8.
3:0
82
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.2
Memory Space Registers
This section provides the memory space registers for the hot plug controller. The MBAR Register
(PCI offset 10h) and MBARU Register (PCI offset 14h) provide the base address for the memory
space registers. The address offset listed in Table 17 are offset from this base address.
Table 17. Hot Plug Controller Memory Space Register Map
Address
Symbol
Register Name
General Purpose Timer
Default
Access
Offset
00h
01h
GPT
SE
00h
00h
R/W
R/W
Slot Enable
R/W, RO,
R/WC
02–03h
MCNF
Miscellaneous Configuration
00h
04–07h
08–0Bh
0C–0Fh
10–11h
13h
LEDC
HMIC
HMIR
SIR
LED Control
00h
00h
FFh
00h
00h
00h
00h
00h
00h
00h
R/W
R/WC
R/W
Hot Plug Interrupt Input and Clear
Hot Plug Interrupt Mask
Serial Input Register
R/W, RO
R/W
GPO
HMIN
SID
General Purpose Output
Hot Plug Non-Interrupt Inputs
Slot ID
14–17h
28h
RO
R/W
2Ch
SIRE
SPE
Switch Interrupt Redirect Enable
Slot Power Enable
R/W
2Dh
R/W
32–33h
EMR
Extended Hot Plug Miscellaneous
R/W
Intel® 82870P2 P64H2 Datasheet
83
Register Description
R
3.3.2.1
GPT—General Purpose Timer Register
Offset:
Default Value: 00h
00h
Attribute:
Size:
R/W
8 bits
This 8-bit register has no functionality but is preserved as read/write for software compatibility.
Bits
Description
7:0
Reserved, maintained for software compatibility
3.3.2.2
SE—Slot Enable Register
Offset:
Default Value: 00h
01h
Attribute:
Size:
R/W
8 bits
These bits control the enabling and disabling of slots. If this register has been changed before the
SOGO bit in the Hot Plug Miscellaneous Register is set, then a four-phase output sequence is used
to set the states of the RESET#, CLKEN#, BUSEN# and PWREN signals to the slots after the
write to set SOGO is completed.
If the value of one of these bits changes from 0 to 1 when SOGO is set, the four-step slot enable
sequence is used to power up the slot. If a stored bit changes from 1 to 0, the four-step slot disable
sequence is used to power down that slot. If some bits have changed from 0 to 1, and others
change from 1 to 0 when SOGO bit is set, the appropriate slots are disabled first. After the disable
sequence has been executed, an enable sequence is executed to enable the appropriate slots. These
bits cannot be written to 1 as long as the corresponding slot switch is open.
The current value of this register can be read back at any time, but may not indicate the current
state of the slots if the SOGO bit has not yet been written.
Bits
Description
7:6
Reserved
Enable Slot (ES)—R/W, RO. When set, the slot is to be enabled. Bit 5 corresponds to slot F, bit
4 to slot E, etc. until bit 0, which corresponds to slot A. These bits are R/W only for slots enabled
by the HPx_SLOT[2:0] power on straps. Otherwise, they are RO for the disabled slots. These bits
are also RO for a slot when it’s associated switch input is in an open state.
5:0
84
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.2.3
MCNF—Miscellaneous Configuration Register
Offset:
Default Value: 00h
02–03h
Attribute:
Size:
R/W, RO, R/WC
16 bits
This register contains various miscellaneous functions related to the hot plug controller.
Bits
Description
15
133 MHz Prescaler Indicator—RO. Hardwired to 0. This bit has no functionality in the P64H2.
Enable SERR on Power Fault (ESPF)—R/W.
0 = Disable. (default)
1 = Enable. When this bit is set, the assertion of a slot power fault pin causes SERR to be
asserted provided that:
14
•
•
SERR is enabled in the PCI configuration header Command Register, and
The slot is fully powered on or is at least past the clock connect phase of a power-up
sequence.
Bit 10 (PFE) of this register must also be set to enable this function. Power faults can also
be programmed to generate interrupts independent of this bit, using the HMIR register.
Scan Power Fault Latches Enable (SPFLE)—R/W. The HMIC Register reflects the internal
latched version of the scan-in power fault bits (from the power fault latches) rather than the actual
scanned in power fault bits. Bit 10 (PFE) of this register must be set for this function to work.
13
12
1 = Setting this bit to 1 when bit 10 (PFE) is 0 forces byte two of the HMIC to always read 1.
Input Scan Complete (ISC)—R/W.
0 = This bit is cleared at the conclusion of the next scan in sequence. (default)
1 = This bit can be written to 1 to ensure that fresh data is available when the input scan logic
reads input bytes [7:0].
66 MHz Enable (M66)—RO. When this bit is set, the hot plug controller clock source is 66 MHz.
0 = Disable (default)
11
10
1 = Enable. This bit is hardwired to 1 for P64H2.
Power Fault Enable (PFE)—R/W. This bit is mapped to bit 13 of the Miscellaneous
Configuration Register (PCI configuration space). Refer to the description of the PFE bit in the
MCNF Register in PCI configuration space for usage of this bit. (default=0)
Auto-Power Down Disable (APD)—R/W.
0 = Enable. (default)
9
8
1 = Disable. Disables powering down a slot when the slot switch is opened without first going
through software to power down the slot.
On/Off Busy (OOB)—RO. This bit is the same as bit 0 in the MCNF Register in PCI
configuration space (offset 42h).
0 = Not running (default)
1 = Indicates the ON/OFF state machine is running. After RSTIN# is negated, this bit remains
set until the Intel® P64H2 updates the slot power, bus/clock enable, and reset controls for
the first time after software completes the initial write to the MCNF Register in PCI
configuration space.
Intel® 82870P2 P64H2 Datasheet
85
Register Description
R
Bits
Description
Parallel Mode (PM)—RO. Hardwired to 0. This bit is irrelevant for the P64H2 and is 0 even
though the hot plug controller is sometimes operating in parallel mode.
7
Bus Frequency Range (BFR)—R/W. Not implemented. This bit is maintained as read/write for
software compatibility.
6
Arbitration Timer Timeout (ATT)—R/WC.
0 = No arbitration timer timeout. (default)
5
1 = The P64H2 was forced to complete a power-up or power-down cycle without getting a grant
from the arbiter.
Note: Software clears this bit by writing a 1 to it.
Dummy Cycle Enable (DCE). Not implemented. The P64H2 does not execute dummy cycles.
This bit is read/write for software compatibility.
4
3
Interrupt Pending (IP)—RO.
0 = When the interrupt is cleared, the bit is set to 0. (default)
1 = This bit is set after an interrupt is generated from the General Interrupt Inputs.
Shift Output Interrupt Pending / Clear (SOIP)—R/WC.
0 = No interrupt was generated by SOGO. (default)
2
1
0
1 = Indicates that an interrupt was generated by SOGO changing from 1 to 0 while the SOIE bit
was set.
Note: Software clears this bit by writing a 1 to it.
Shift Output Interrupt Enable (SOIE)—R/W.
0 = Disable. (default)
1 = Enable. An interrupt is generated when SOGO changes from 1 to 0.
Shift Output Go / Busy Status (SOGO)—R/W. Writing this bit to 1 from 0 causes the serial
outputs to be updated from the latest contents of the LED, RST#, Slot Enable, Slot Power
Enable, and General Purpose Output registers. Writing 0 to this bit or writing 1 while it is 1 has no
effect. (default=0)
When read, this bit indicates the busy status of the shift output logic. When 0, the output shift is
complete.
86
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.2.4
LEDC—LED Control Register
Offset:
Default Value: 00h
04–07h
Attribute:
Size:
R/W
32 bits
This register controls the two LEDs on each slot. There are two bits for each LED control. When
the P64H2 executes an auto power-down, all four LED bits corresponding to that slot will be
cleared. Below is the bit placement per slot. In all cases, the green LED is the power indicator and
the amber LED is the attention indicator.
• 00 = Off
• 01 = Blink Phase A
• 10 = Blink Phase B
• 11 = On
The LEDs are initialized by RSTIN#, not by PCIRST#. Both LEDs for a slot initialize to 0 if slot
is opened or if slot is not supported.
To change the state of an LED for a slot, write the LEDC register with the appropriate setting for
each slot, and then perform a write to SOGO in the MCNF Register in memory space.
Bits
Description
31:30
Reserved
Amber LED MSB (AMM). MSB of the Amber LED. Bit 29 corresponds to slot F, bit 28 to slot E,
etc. until bit 24, which corresponds to slot A. These bits are R/W only for slots enabled by the
HPx_SLOT[2:0] power on straps. Otherwise, they are RO for the disabled slots.
29:24
23:22
21:16
15:14
13:8
7:6
Reserved
Amber LED LSB (AML). LSB of the Amber LED. Bit 21 corresponds to slot F, bit 20 to slot E,
etc. until bit 16, which corresponds to slot A. These bits are R/W only for slots enabled by the
HPx_SLOT[2:0] power on straps. Otherwise, they are RO for the disabled slots.
Reserved
Green LED MSB (GNM). MSB of the Green LED. Bit 13 corresponds to slot F, bit 12 to slot E,
etc. until bit 8, which corresponds to slot A. These bits are R/W only for slots enabled by the
HPx_SLOT[2:0] power on straps. Otherwise, they are RO for the disabled slots.
Reserved
Green LED LSB (GNL). LSB of the Green LED. Bit 5 corresponds to slot F, bit 4 to slot E, etc.
until bit 0, which corresponds to slot A. These bits are R/W only for slots enabled by the
HPx_SLOT[2:0] power on straps. Otherwise, they are RO for the disabled slots.
5:0
Intel® 82870P2 P64H2 Datasheet
87
Register Description
R
3.3.2.5
HMIC—Hot Plug Interrupt Input and Clear Register
Offset:
Default Value: 00h
08–0Bh
Attribute:
Size:
R/WC
32 bits
This register is used to read the current state of the general interrupt inputs when no interrupt is
pending. When one of the below inputs changes state (either high-to-low or low-to-high) and that
bit is not masked in the HMIR Register, an interrupt is generated and the state of that interrupting
input is latched in this register. The value in the register then represents the latched state of that
interrupting input. A write of 1 to this register in the bit positions of any bits that have changed
clears the interrupt and allows the register to be updated with the current state of that input signal.
Note: Unimplemented slots may have interrupt bits set in these registers; therefore, software should mask
the corresponding locations in the mask register.
Note: The reset value of this register is 0; however, this may change after the first scan in sequence
which may be before software is able to access this register.
Note: The bits that pertain to disabled slots (not enabled by HPx_SLOT[2:0] power on straps) reflect the
value of the last enabled slot. For example, if slots 3, 4, 5, 6 are disabled, their corresponding bits
in this register will match the bit value for slot 2.
Bits
Description
31:30
Reserved
PRSNT1# (SP1). Present Signal 1 from the PCI slot connector. This signal is the latched state of
the PRSNT1# pin when the pin changes state and causes an interrupt. When 0, the slot present
bit is active (0). Bit 29 represents slot F, bit 28 represents slot E, etc. until bit 24, which
represents slot A.
29:24
23:22
21:16
Reserved
PRSNT2# (SP2). Present Signal 2 from the PCI slot connector. This signal is the latched state of
the PRSNT2# pin when the pin changes state and causes an interrupt. When 0, the slot present
bit is active (0). Bit 21 represents slot F, bit 20 represents slot E, etc. until bit 16, which
represents slot A.
15:14
13:8
7:6
Reserved
FAULT# (SF). Power Fault from the motherboard. This signal is the latched state of the FAULT#
pin when the pin changes state and causes an interrupt. When 0, the power fault is active (0).
Bit 13 represents slot F, bit 12 represents slot E, etc. until bit 8, which represents slot A.
Reserved
Switch (SS). Slot Switch from the chassis. This signal is the latched state of the switch pin when
the pin changes state and causes an interrupt. When 0, the slot switch is closed (0). Bit 5
represents slot F, bit 4 represents slot E, etc. until bit 0, which represents slot A.
5:0
88
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.2.6
HMIR—Hot Plug Interrupt Mask Register
Offset:
Default Value: FFh
0C–0Fh
Attribute:
Size:
R/W
32 bits
Each bit in this register corresponds to the HMIC register. If the mask bit for an input into that
register is set, no interrupt is generated.
Bits
Description
31:30
Reserved. Default = 11b
PRSNT1# Mask (SP1). Present Signal 1 mask. Default = 3Fh
0 = Not masked
29:24
23:22
21:16
15:14
13:8
7:6
1 = Masked. The corresponding slot present bit interrupt is masked. (default)
Reserved. Default = 11b
PRSNT2# Mask (SP2). Present Signal 2 mask. Default = 3Fh
0 = Not masked
1 = Masked. The corresponding slot present bit interrupt is masked. (default)
Reserved. Default = 11b
FAULT# Mask (SF). Power Fault mask. Default = 3Fh
0 = Not masked
1 = Masked. The corresponding power fault interrupt bit is masked. (default)
Reserved. Default = 11b
Switch Mask (SS). Slot Switch mask. Default = 3Fh
0 = Not masked
5:0
1 = Masked. The corresponding slot switch interrupt bit is masked. (default)
Intel® 82870P2 P64H2 Datasheet
89
Register Description
R
3.3.2.7
SIR—Serial Input Register
Offset:
Default Value: 00h
10–11h
Attribute:
Size:
R/W, RO
16 bits
This register allows for the scanning of additional serial input data on the hot plug serial input
stream. The purpose is to provide a mechanism for accessing additional general-purpose or user-
defined input data. Note that this is only possible when operating in Serial mode. To read a byte
from the scan chain, first write the appropriate number to the Serial Input Byte Pointer register,
wait for the Serial Input Busy Status to indicate that the shift is complete, then read the Serial Input
Data register. A write to the Serial Input Byte Pointer is ignored if the Serial Input Busy Status bit
already indicates that a shift is in progress. The value in the Data register is unpredictable while
the shift is in progress. Once the shift is complete, the Data register remains unchanged until the
Byte Pointer is written again.
The scan in process for the SID byte (pointed to by SIBP) will start whenever a write to any byte
of the DWord at memory offset 10h is detected.
Note: This register has no purpose when the hot plug controller is operating in 1-slot or 2-slot parallel
mode, because the input serial data stream is internal to P64H2.
Bits
Description
Serial Input Busy Status (SIBS).
15
1 = This bit is set to 1 when this register is written and remains 1 until the selected byte has
been shifted into the Serial Input Data register.
14:13
12
Reserved
Reserved for Future Expansion (RSVD). Reserved for future expansion of the serial input chain
length.
Serial Input Byte Pointer (SIBP). Read as written. Writing any value n causes the serial input
logic to load the external shift registers and shift (N+1)*8 times, so that byte N is shifted into the
Serial Input Data register.
11:8
7:0
Serial Input Data (SID). This register is updated from the external shift registers every time the
Serial Input Register is written. If the pointer points to an internal shift register (values 3–0), the
register value is a copy of the appropriate internal shift register input state.
3.3.2.8
GPO—General Purpose Output Register
Offset:
Default Value: 00h
13h
Attribute:
Size:
R/W
8 bits
This register contains the general-purpose outputs that are shifted out at the front of a serial out
sequence. Note that this register has no purpose when the hot plug controller is operating in 1-slot
or 2-slot parallel mode, because the output serial data stream is internal to P64H2.
Bits
Description
General Purpose Output (GPO). The bits in this register are reflected in the internal serial
output register, along with the other serial outputs bits.
7:0
90
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.2.9
HMIN—Hot Plug Non-Interrupt Inputs Register
Offset:
Default Value: 00h
14–17h
Attribute:
Size:
RO
32 bits
This register reflects the current state of bytes 4 through 7 of the serial input chain. Changes in the
states of these bits cannot be enabled to generate interrupts. The Input Scan Complete bit of the
MCNF Register in memory space determines if this register contains fresh data.
Bits
Description
31:22
Reserved
PCIXCAP2 Status. Using these bits, software can determine if a new card installed in a slot is
capable of running at 133 MHz PCI-X mode or only 66 MHz PCI-X mode, assuming the slot can
be run in PCI-X mode (by reading bits[13:8]. Bit 21 represents slot F, Bit 20 represents slot E,
etc.
21:16
15:14
13:8
7:6
Reserved
PCIXCAP1 Status. Using these bits, software can determine if a new card installed in a slot is
capable of running in PCI-X mode. Bit 13 represents slot F, Bit 12 represents slot E, etc.
Reserved
Slot is 66 MHz Capable (M66EN). Using these bits, software can determine if a new card
installed in a slot is capable of running at 66 MHz. Bit 5 represents slot F, Bit 4 represents slot E,
etc. until Bit 0, which represents slot A.
5:0
3.3.2.10
SID—Slot ID Register
Offset:
Default Value: 00h
28h
Attribute:
Size:
R/W
8 bits
This register indicates which slots in the system support hot plug. It has no influence on the
behavior of the logic. The contents of this register should be maintained by the OS/BIOS and
should always be identical to the contents of the register of the same name in configuration space.
Bits
Description
7:4
3:0
Starting Slot Number (SSN). Starting physical slot number that supports hot plug.
Number of Slots (NUM). Number of hot plug slots controlled by the Intel® P64H2.
3.3.2.11
SIRE—Switch Interrupt Redirect Enable Register
Offset:
Default Value: 00h
2Ch
Attribute:
Size:
R/W
8 bits
These bits redirect slot switch change interrupts to SERR# instead of an interrupt.
Bits
Description
Reserved. This field is R/W for legacy compatibility.
7:6
Slot Interrupt Redirect Enable (RE). Bit 5 represents slot F, Bit 4 slot E, etc. until Bit 0, which
represents slot A. When set, switch change interrupts to cause the SERR# pin to be asserted.
5:0
Intel® 82870P2 P64H2 Datasheet
91
Register Description
R
3.3.2.12
SPE—Slot Power Enable Register
Offset:
Default Value: 00h
2Dh
Attribute:
Size:
R/W
8 bits
These bits enable and disable slot power by controlling the states of PWREN. If this register has
been changed before the Serial Output Go bit in the MCNF Register in memory space is set, a one-
pass sequence is used to set the appropriate states of the PWREN.
The state of this register is stored each time the Serial Output Go (SOGO) bit in the MCNF
Register is set. If the stored value of one of these bits changes from 0 to 1 when SOGO is set,
PWREN for that slot is set. If a stored bit changes from 1 to 0, PWREN for that slot is cleared.
The current value of this register can be read back at any time, but may not indicate the current
state of the slots if the SOGO bit has not yet been written. After SOGO is written and has been
cleared by the controller, the state of this register will indicate the power state of all the slots.
Note that the bits that pertain to disabled slots (not enabled by HPx_SLOT[2:0] power on straps)
will reflect the value of the last enabled slot. For example, if slots 3, 4, 5, 6 are disabled, their
corresponding bits in this register will match the bit value for slot 2.
Another behavior to note is that writes to disable slots via the Slot Enable register at memory
offset 01h will also clear corresponding slot bits in this register. However, writes to this register
will not modify corresponding slot bits in the Slot Enable Register. Also writes of 0 to this register
are blocked if the slot has already been fully powered on and connected to the PCI bus.
This register is normally used by software to apply power to a card to determine its PCI-X
capabilities (via the card’s M66EN and PCIXCAP pins). Writes to this register should be followed
by writes to the Slot Enable register once software has determined the M66EN and PCIXCAP pin
values for newly inserted cards. After this register is written and followed by a SOGO write, the
on/off state machine will run a one-pass sequence to apply power to the card. Note that the
controller will wait 500 ms before clearing the SOGO bit, giving the new card’s power supply time
to stabilize. However, this 500 ms timer is not functional for successive writes to the SPE Register.
After software writes to SPE and then to SOGO, software is required to then write to the SE
Register and then SOGO to connect the new cards if they are capable of running on the PCI-X bus.
If a card is not capable of running on the PCI-X bus, then software should write to SPE and SOGO
to power it down. Software should not perform a second SPE/SOGO write combination to power
up a second card immediately after the first SPE/SOGO writes - the 500 ms timer will not be
functional at this point.
Bits
Description
7:6
Reserved. Read only
Enable Power (EP).
0 = Disable. (default)
5:0
1 = Enable. When set, the slot is to be powered. Bit 5 corresponds to slot F, bit 4 to slot E, etc.
until bit 0, which corresponds to slot A. These bits are R/W only for slots enabled by the
HPx_SLOT[2:0] power on straps. Otherwise, they are RO for the disabled slots. These bits
are also RO for a slot when it’s associated switch input is in an open state.
92
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.3.2.13
EMR—Extended Hot Plug Miscellaneous Register
Offset:
Default Value: 00h
32–33h
Attribute:
Size:
R/W
16 bits
This register contains additional miscellaneous functions related to the hot plug controller.
Bits
Description
15:3
Reserved
Arbiter Timeout SERR Enable (ATSE).
0 = Disable. (default)
2
1
1 = Causes a SERR to be generated when an arbiter timeout occurs. This event is indicated in
both the Arbiter Timer Timeout (ATT) bit in the MCNF Register in memory space and Arbiter
Timeout SERR Status (ATS) bit in the SERR Status Register in PCI configuration space.
Arbiter Timeout Interrupt Enable (ATIE).
0 = Disable. (default)
1 = Causes an interrupt to be generated when an arbiter timeout occurs. Writing 1 to the Arbiter
Timer Timeout (ATT) bit (MCNF Register in memory space) clears this interrupt.
Inhibit Arbiter Timeouts (IAT).
0 = Power sequencing state machine starts a timer when it requests the bus (bus requests
occur for most phases of power sequencing). If the arbiter takes too long to return bus grant
to the Hot plug logic, an arbiter timeout occurs and the power sequence phase executes
without bus ownership. (default)
0
1 = Causes the power sequence logic to wait for the bus grant forever. The auto-power down
feature (opening a slot switch) does NOT successfully cause the slot to be powered off,
which presents a potential risk to a system whose bus is hung. Even though this bit is set,
an SERR or interrupt can be generated when an arbiter timeout would have occurred (see
bits 17 and 18).
Intel® 82870P2 P64H2 Datasheet
93
Register Description
R
3.4
I/OxAPIC Interrupt Controller Registers
The P64H2 contains two I/O APIC controllers (I/OxAPIC where x is either A or B), both reside
on the primary bus. The intended use of these controllers is to have the interrupts from PCI bus A
connected to the interrupt controller on device 28, and have the interrupts on PCI bus B connected
to the interrupt controller on device 30. The I/OxAPIC controllers contain PCI Configuration
registers (See Section 3.4.1) and memory space registers (see Sections 3.4.2 and 3.4.3).
3.4.1
PCI Configuration Space Registers (Device 28 and 30)
Table 18. I/OxAPIC PCI Configuration Space Register Map
Address
Symbol
Register Name
Vendor ID Register
Default
Attribute
Offset
00–01h
02–03h
04–05h
VID
DID
8086h
1461h
0000h
RO
RO
Device ID Register
PCICMD
PCI Device Command Register
R/W, RO
R/W, RO,
R/WC
06–07h
PCISTS
PCI Device Status Register
0030h
08h
RID
CC
Revision ID Register
Class Code Register
Header
11h
080020h
00000000h
00000000h
—
RO
RO
RO
R/W
—
09–0Bh
0C–0Fh
10–13h
14–2Bh
2C–2Fh
30–33h
34h
HDR
MBAR
—
Memory Base Register
Reserved
SS
Subsystem Identifiers
Reserved
00000000h
—
R/W
—
—
CAP_PTR
—
Capabilities Pointer
Reserved
50h
RO
—
35–3Fh
40–41h
42–4Fh
50–51h
52h
—
ABAR
—
Alternate Base Address Register
Reserved
0000h
—
R/W
—
XID
PCI-X Identifiers
PCI-X Command Register
Reserved
0007h
00h
RO
RO
—
XCR
—
53h
—
000300F0h
(bus A)
000300E0h
(bus B)
54–57h
XSR
PCI-X Status Register
RO
80h
Alias of memory space registers at 00h, 10h, 20h, and 40h
94
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.4.1.1
VID—Vendor ID Register (D28,30: F0)
Offset:
Default Value: 8086h
00–01h
Attribute:
Size:
RO
16 bits
This register contains the Vendor Identifiers.
Bits
Description
15:0
Vendor ID (VID). 16-bit field, which indicates that Intel is the vendor. VID=8086
3.4.1.2
DID—Device ID Register (D28,30: F0)
Offset:
Default Value: 1461h
02–03h
Attribute:
Size:
RO
16 bits
This register contains the Device Identifiers.
Bits
Description
15:0
Device ID (DID). Indicates device number assigned to this controller. DID=1461h
Intel® 82870P2 P64H2 Datasheet
95
Register Description
R
3.4.1.3
PCICMD—PCI Device Command Register (D28,30: F0)
Offset:
Default Value: 0000h
04–05h
Attribute:
Size:
R/W, RO
16 bits
This register controls how the device behaves.
Bits
Description
15:10
9
Reserved
Fast Back-to-Back Enable (FBE)—RO. Hardwired to 0; Reserved
SERR# Enable (SEE)—R/W. This bit controls the enable for the DO_SERR special cycle on the
hub interface.
8
0 = Disable special cycle. (default)
1 = Enable special cycle.
7
6
Wait Cycle Control (WCC)—RO. Hardwired to 0; Reserved
Parity Error Response Enable (PERE)—R/W. This bit enables checking of parity.
0 = Disable (default)
1 = Enable
5
4
3
VGA Palette Snoop Enable (VGA_PSE)—RO. Hardwired to 0; Reserved
Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0; Reserved
Special Cycle Enable (SCE)—RO. Hardwired to 0; Reserved
Bus Master Enable (BME)—R/W. This bit controls the I/OxAPIC’s ability to act as a master on
the hub interface when forwarding system bus interrupt messages.
2
0 = Disable (default)
1 = Enable
Memory Space Enable (MSE)—R/W. This bit controls the I/OxAPIC’s response as a target to
memory accesses that address the I/OxAPIC.
1
0
0 = Disable (default)
1 = Enable
I/O Space Enable (IOSE)—RO. Hardwired to 0; Reserved
96
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.4.1.4
PCISTS—PCI Device Status Register (D28,30: F0)
Offset:
Default Value: 0030h
06–07h
Attribute:
Size:
R/W, RO, R/WC
16 bits
None of the bits in the I/OxAPIC status register are read/write.
Bits
Description
Detected Parity Error (DPE)—R/WC.
0 = No parity error detected. (default)
15
1 = Indicates that a parity error was detected on cycles targeting the I/OxAPIC.
Note: Software clears this bit by writing a 1 to it.
Signaled System Error (SSE)—R/WC.
0 = No SERR# reported. (default)
14
1 = SERR# is reported to the hub interface via the DO_SERR special cycle.
Note: Software clears this bit by writing a 1 to it.
13
12
Received Master Abort (RMA)—RO. Hardwired to 0; Reserved
Received Target Abort (RTA)—RO. Hardwired to 0; Reserved.
Signaled Target Abort (STA)—RO. Hardwired to 0; Reserved.
DEVSEL# Timing (DT)—RO. Fast decode is performed by the I/OxAPIC.
Master Data Parity Error (MDPE)—RO. Hardwired to 0; Reserved.
11
10:9
8
Fast Back-to-Back Capable (FBC)—RO. Hardwired to 0; Reserved as not fast back-to-back
capable.
7
6
5
Reserved
66 MHz Capable (C66)—RO. Hardwired to 1; 66 MHz capable.
Capabilities List Enable (CAPE)—RO. Hardwired to 1; This bit indicates that the Intel® P64H2
contains the capabilities pointer in the I/OxAPIC. Offset 34h indicates the offset for the first entry
in the linked list of capabilities.
4
3:0
Reserved
3.4.1.5
RID—Revision ID Register (D28,30: F0)
Offset:
Default Value: 04h
08h
Attribute:
Size:
RO
8 bits
Bits
Description
Revision ID (RID). Indicates the step of the I/OxAPIC in the Intel® P64H2.
7:0
03h = B0 Stepping
04h = B1 Stepping
Intel® 82870P2 P64H2 Datasheet
97
Register Description
R
3.4.1.6
CC—Class Code Register (D28,30: F0)
Offset:
Default Value: 080020h
09–0Bh
Attribute:
Size:
RO
24 bits
This register contains the base class, sub-class and programming interface codes.
Bits
Description
Base Class Code (BCC).
08h = Generic system peripheral.
Sub Class Code (SCC).
23:16
15:8
7:0
00h = Generic peripheral is an interrupt controller.
Programming Interface (PIF).
20h = Interrupt peripheral is an I/OxAPIC.
3.4.1.7
HDR—Header (D28,30: F0)
Offset:
0C–0Fh
Attribute:
Size:
RO
32 bits
Default Value: 00000000h
This is additional header information related to the I/OxAPIC.
Bits
Description
31:24
Built In Self Test (BIST). Reserved
Header Type (HTYPE). This indicates that it is a type 00 header (normal PCI device) and that it
is a single function device.
23:16
15:8
7:0
Latency Timer (LAT). Reserved
Cache Line Size (CLS). Reserved
3.4.1.8
MBAR—Memory Base Register (D28,30: F0)
Offset:
10–13h
Attribute:
Size:
R/W, RO
32 bits
Default Value: 00000000h
This register contains the APIC Base Address for the APIC memory space.
Bits
Description
31:12
11:4
3
Address (ADDR)—R/W. These bits determine the base address of the I/OxAPIC
Reserved
Prefetchable (PF)—RO. Hardwired to 0; indicates that the BAR is not prefetchable.
Location (LOC)—RO. Hardwired to 00; indicates that the address can be located anywhere in
the 32-bit address space.
2:1
0
Space Indicator (SI)—RO. Hardwired to 0; indicates that the BAR is in memory space.
98
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.4.1.9
SS—Subsystem Identifier Register (D28,30: F0)
Offset:
2C–2Fh
Attribute:
Size:
R/WO
32 bits
Default Value: 00000000h
This register is initialized to logic 0 by the assertion of PCIRST#. This register can be written only
once after PCIRST# deassertion.
Bits
Description
31:16
15:0
Subsystem ID (SSID)—R/WO. Write once field for sub-system ID.
Subsystem Vendor ID (SSVID)—R/WO. Write once field for holding the subsystem vendor ID.
3.4.1.10
CAP_PTR—Capabilities Pointer Register (D28,30: F0)
Offset:
Default Value: 50h
34h
Attribute:
Size:
RO
8 bits
Bits
Description
Capabilities Pointer (PTR). This field indicates that the pointer for the first entry in the
capabilities list is at 50h in PCI configuration space.
7:0
3.4.1.11
ABAR—Alternate Base Address Register (D28,30: F0)
Offset:
Default Value: 0000h
40–41h
Attribute:
Size:
R/W
16 bits
This register contains an alternate base address in the legacy APIC range. This range can co-exist
with the BAR Register range. This range is needed for operating systems that support the APIC
but do not yet support remapping the APIC anywhere in the 4 GB address space.
Bits
Description
I/OxAPIC Alternate Range Enable (EN). When set, the range FECXYZ00 to FECXYZFF is
enabled as an alternate access method to the I/OxAPIC registers. Bits ’XYZ’ are defined below.
15
0 = Disable (default)
1 = Enable
14:12
11:8
Reserved
Base Address [19:16] (XBAD). These bits determine the high order bits of the I/O APIC address
map. When a memory address is recognized by the P64H2, which matches FECXYZ00 or
FECXYZ10, the Intel® P64H2 will respond to the cycle and access the internal I/OxAPIC.
Base Address [15:12] (YBAD). These bits determine the low order bits of the I/OxAPIC address
map. When a memory address is recognized by the P64H2, which matches FECXYZ00 or
FECXYZ10, the P64H2 will respond to the cycle and access the internal I/OxAPIC.
7:4
3:0
Base Address [11:8] (ZBAD). These bits determine the low order bits of the I/OxAPIC address
map. When a memory address is recognized by the P64H2, which matches FECXYZ00 or
FECXYZ10, the P64H2 will respond to the cycle and access the internal I/OxAPIC.
Intel® 82870P2 P64H2 Datasheet
99
Register Description
R
3.4.1.12
XID—PCI-X Identifier Register (D28,30: F0)
Offset:
Default Value: 0007h
50–51h
Attribute:
Size:
RO
16 bits
Bits
Description
15:8
7:0
Next Pointer (XNPTR). Points to the next capabilities list pointer (empty)
Capability ID (XCID). Capabilities ID indicates PCI-X.
3.4.1.13
XCR—PCI-X Command Register (D28,30: F0)
Offset:
Default Value: 0000h
52h
Attribute:
Size:
RO
16 bits
Bits
Description
15:0
Reserved
3.4.1.14
XSR—PCI-X Status Register (D28,30: F0)
Offset:
54–57h
Attribute:
Size:
RO
32 bits
Default Value: 000300F0h (bus A)
000300E0h (bus B)
Bits
Description
31:21
20
Reserved
Device Complexity. Hardwired to 0; indicates that this is a simple device.
Unexpected Split Completion. This device will never see an unexpected split completion, as it
never generates any master cycles besides posted writes for MSI.
19
18
17
16
Split Completion Discarded. This device does not support Split Completion.
133MHz Capable. Hardwired to 1; indicates this device is 133 MHz capable.
64-bit Device. Hardwired to 1; indicates that this is a 64-bit device.
Bus Number. Indicate the bus number of the bus segment for this device. This value will match
the ‘primary bus number’ field from the attached bridge.
15:8
Device Number. Reflects the device number that has been hard-coded for the device. This
number will be
7:3
2:0
1Eh (30) = I/O APIC A
1Ch (28) = IO APIC B
Function Number. Reflects the function number for the device.
100
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.4.2
Direct Memory Space Registers
These I/OxAPIC registers are located in processor memory space. The IDX and WND Registers
are used to access the I/OxAPIC’s Indirect Memory Space registers (see Section 3.4.3). The offset
addresses listed in Table 19 are offset from the base address programmed in the MBAR Register
(PCI offset 10h).
Table 19. I/OxAPIC Memory Space Register Map
Offset
Address
Symbo
l
Full Name
Default
00h
10–13h
20h
IDX
WND
PAR
EOI
Index Register
00h
00000000h
xxh
Window Register
IRQ Pin Assertion Register
EOI Register
40h
xxh
3.4.2.1
IDX—Index Register (D28,30: F0)
Offset:
Default Value: 00h.
00h
Attribute:
Size:
R/W
8 bits
The Index Register selects which indirect register appears in the window register to be
manipulated by software. Software programs this register to select the desired APIC internal
register.
Bits
Description
7:0
Index (IDX). Indirect register to access.
3.4.2.2
WND—Window Register (D28,30: F0)
Offset:
10–13h
Attribute:
Size:
R/W
32 bits
Default Value: 00000000h
This is a 32-bit register specifying the data to be read or written to the register pointed to by the
Register Select Register. This register can be accessed in byte quantities.
Bits
Description
Window (WND). Data to be written to the indirect register on writes, and location of register data
from the indirect register on reads.
31:0
Intel® 82870P2 P64H2 Datasheet
101
Register Description
R
3.4.2.3
PAR—IRQ Pin Assertion Register (D28,30: F0)
Offset:
Default Value: xxh
20h
Attribute:
Size:
R/W
8 bits
The IRQ Pin Assertion Register is present to provide a mechanism to scale the number of interrupt
inputs into the I/Ox APIC without increasing the number of dedicated input pins. When a device
that supports this interrupt assertion protocol requires interrupt service, that device will issue a
write to this register. Bits [4:0] written to this register contain the IRQ number for this interrupt.
The only valid values are 0–23.
Bits
Description
7:0
Assertion (PAR). Virtual pin to be asserted (active high).
3.4.2.4
EOI—End of Interrupt Register (D28,30: F0)
Offset:
Default Value: xxh
40h
Attribute:
Size:
WO
8 bits
The EOI register is present to provide a mechanism to maintain the level triggered semantics for
level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/OxAPIC will check the lower 8 bits written to this
register, and compare it with the vector field for each entry in the I/O Redirection Table. When a
match is found, the Remote_IRR bit for that I/O Redirection Entry is cleared.
Note that if multiple I/O Redirection entries, for any reason, assign the same vector for more than
one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.
Bits
Description
7:0
End of Interrupt (EOI). Vector to be cleared by the EOI.
102
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.4.3
Indirect Memory Space Registers
These registers are accessed indirectly using the IDX and WND Registers (see Section 3.4.2). To
access the indirect memory space, an 8-bit value is written to the IDX Register (i.e., address offset
shown in Table 20); this is a "pointer" to a 32-bit memory location. The 32-bit value can then be
read from the WND Register.
Table 20. I/OxAPIC Indirect Memory Space Register Address Map
Address
Offset
Symbol
Full Name
Default
Attribute
00h
01h
02h
03h
10h
11h
ID
VS
APIC ID
00000000h
00178020h
00000000h
00000000h
00010000h
00000000h
R/W
RO
Version
ARBID
BCFG
RDL
Arbitration ID
Boot Configuration
RO
R/W
R/W
R/W
Redirection Table Low DWord
Redirection Table High DWord
RDH
3.4.3.1
ID—APIC ID Register (D28,30: F0)
Offset:
00h
Attribute:
Size:
R/W
32 bits
Default Value: 00000000h
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is
derived from its I/O APIC ID. This register is reset to zero on power up reset.
Bits
Description
31:28
27:24
23:0
Reserved
APIC ID (APICID). Software must program this value before using the APIC.
Reserved
Intel® 82870P2 P64H2 Datasheet
103
Register Description
R
3.4.3.2
VS—Version Register (D28,30: F0)
Offset:
01h
Attribute:
Size:
RO
32 bits
Default Value: 00178020h
This register contains information related to this I/OxAPIC for driver / OS software.
Bits
Description
31:24
Reserved
Maximum Redirection Entries (MAX). This is the entry number of the highest entry in the
redirection table. It is equal to the number of interrupt inputs minus one. This field is hardwired to
17h to indicate 24 interrupts. (Default=17h)
23:16
15
IRQ Assertion Register Supported (PRQ). This bit is set to 1 to indicate that this version of the
I/OxAPIC implements the IRQ Assertion register and allows PCI devices to write to it to cause
interrupts. (Default=01h)
14:8
7:0
Reserved
Version (VS). This identifies the implementation version. This field is hardwired to 20h to indicate
this is an I/OxAPIC. (Default=20h)
3.4.3.3
ARBID—Arbitration ID Register (D28,30: F0)
Offset:
02h
Attribute:
Size:
RO
32 bits
Default Value: 00000000h
This register contains the bus arbitration priority for the APIC, and is loaded when the APIC ID
Register is loaded. A rotating priority scheme is used for APIC bus arbitration. The winner of the
arbitration becomes the lowest priority agent and assumes an arbitration ID of 0. All other agents,
except the agent whose arbitration ID is Fh, increment their arbitration IDs by one. The agent
whose ID was 15 takes the winner’s arbitration ID and increments it by one.
Arbitration IDs are changed only for messages that are transmitted successfully, except in the case
of Low Priority messages, where the arbitration ID is changed even if the message was not
successfully transmitted. A message is transmitted successfully if no checksum error or acceptance
error was reported for that message. The APIC Arbitration ID register is always loaded with APIC
ID during a "level triggered INIT with deassert" message.
Bits
Description
31:28
27:24
23:0
Reserved
Arbitration ID (ARBID). This 4-bit field contains the I/OxAPIC Arbitration ID.
Reserved
104
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.4.3.4
BCFG—Boot Configuration Register (D28,30: F0)
Offset:
03h
Attribute:
Size:
R/W
32 bits
Default Value: 00000000h
The Boot Configuration contains information that is only supposed to be accessed by BIOS and is
not for OS use. It contains bits that must be programmed before the OS takes control of interrupts.
Bits
Description
31:1
Reserved
Delivery Type (DT). Software sets this bit to 1 to indicate that the delivery mechanism is as a
front-side bus message and not the APIC serial bus.
0
3.4.3.5
RDL—Redirection Table Low DWord Register (D28,30: F0)
Offset:
10–13h
Attribute:
Size:
R/W, RO
32 bits
Default Value: 00010000h
The information in this register is sent on the system bus to address a local APIC. There is one of
these registers for every interrupt. The first interrupt (pin 0) has this entry at offset 10h. The
second interrupt at 12h, third at 14h, etc. until the final interrupt (interrupt 23) at 3Eh.
Bits
Description
31:17
Reserved
Disable Flushing (DFLSH). This bit is maintained for any potential software compatibility. The
Intel® P64H2 does not perform a flushing action, regardless of the setting of this bit. (default=0)
18
17
Disable Flushing Bit—R/W. This bit is maintained for software compatibility. The P64H2 will
perform no flushing action, regardless of the setting of this bit. Thus, An APICFlush/APICAck is
NOT generated before sending the interrupt. (default=0)
Mask (MSK)—R/W.
0 = An edge or level on this interrupt pin results in the delivery of the interrupt to the destination.
16
15
1 = Interrupts are not delivered nor held pending. Setting this bit after the interrupt is accepted
by a local APIC has no effect on that interrupt. (default)
Trigger Mode (TM)—R/W. This field indicates the type of signal on the interrupt pin that triggers
an interrupt.
0 = Edge sensitive (default)
1 = Level sensitive.
Remote IRR (RIRR)—RO. This bit is used for level-triggered interrupts; this bit’s meaning is
undefined for edge triggered interrupts.
14
0 = EOI message is received from a local APIC. (default)
1 = For level triggered interrupts, this bit is set when Local APIC/s accept the level interrupt sent
by the I/OxAPIC.
Intel® 82870P2 P64H2 Datasheet
105
Register Description
R
Bits
Description
Interrupt Input Pin Polarity (IP)—R/W. This bit specifies the polarity of each interrupt signal
connected to the interrupt pins.
13
0 = Active high. (default)
1 = Active low.
Delivery Status (DS)—RO. This field contains the current status of the delivery of this interrupt.
It is read only. Writes to this bit have no effect.
12
11
0 = Idle; no activity for this interrupt (default)
1 = Pending; interrupt has been injected, but delivery is held up due the inability of the receiving
APIC unit to accept the interrupt at this time.
Destination Mode (DSTM)—R/W. This field determines the interpretation of the Destination
field.
0 = Physical; Destination APIC ID is identified by RDH bits [59:56]. (default)
1 = Logical; Destination is identified by matching bits [63:56] with the Logical Destination in the
Destination Format Register and Logical Destination Register in each local APIC.
Delivery Mode (DELM)—R/W. This field specifies how the APICs listed in the destination field
should act when the interrupt is received. Certain Delivery Modes will only operate as intended
when used in conjunction with a specific trigger mode. These encodings are described in more
detail in each serial message. The encodings are:
000 = Fixed: Trigger Mode can be edge or level. (default)
001 = Lowest Priority: Trigger Mode can be edge or level.
010 = SMI/PMI: Not supported
011 = Reserved
10:8
100 = NMI: Not supported
101 = INIT: Not supported
110 = Reserved
111 = ExtINT: Not supported
Vector (VCT)—R/W. This field contains the interrupt vector for this interrupt. Values range
between 10h and FEh. (default=00h)
7:0
3.4.3.6
RDH—Redirection Table High Register (D28,30: F0)
Offset:
11h
Attribute:
Size:
R/W
32 bits
Default Value: 00000000h
The information in this register is sent on the system bus to address a local APIC. There is one
RDH Register for every interrupt. The first interrupt (pin 0) has this entry at offset 11h. The
second interrupt at 13h, third at 15h, etc. until the final interrupt (interrupt 23) at 3Fh.
Bits
Description
31:24
23:16
15:0
Destination ID (DID). This information is transferred in bits [19:12] of the address.
Extended Destination ID (EDID). These are bits [11:4] of the address.
Reserved
106
Intel® 82870P2 P64H2 Datasheet
Register Description
R
3.5
SMBus Interface
The SMBus interface does not have PCI configuration registers. The SMBus address is set upon
PWROK by sampling PAGNT[5:4] and PBGNT[5:4].
The SMBus controller has access to all internal registers. The generation of cycles on the hub
interface or PCI are not supported transactions, and undefined results may occur if they are
attempted. It can perform reads and writes from all registers through the particular interface’s
configuration space. Hot plug and I/OxAPIC memory spaces are accessible through their
respective configuration spaces.
The following registers are only accessible through the SMBus port.
Table 21. SMBus Register Address Map
Address
Symbol
Offset
Name
Default
Attribute
00h
01h
CMDSTS
BNUM
DFNUM
RNUM
DATA
Command / Status Register
Bus Number
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
02h
Device / Function Number
Register Number
00h
03h
00h
04–07h
FFh
Data Register
00000000h
00h
CFG
SMBus Configuration (Default = 00h)
Intel® 82870P2 P64H2 Datasheet
107
Register Description
R
3.5.1
CMDSTS—Command / Status Register
Offset:
Default Value: 00h
00h
Attribute:
Size:
R/W, RO
8 bits
When written, this is the Command Register. When read, this is the Status Register. All
configuration accesses from the SMBus port are initiated by writing to this register. While a
command is in progress, all future writes or reads will be NACK’d by the P64H2 to avoid having
registers overwritten.
Bits
Description
Error (ERR)—RO.
0 = No error (default)
7
1 = Indicates that the previous command terminated abnormally. This bit will be set if a master
or target abort occurred on the SMBus initiated access.
6:4
3
Reserved
Configuration Accesses Enable (EN)—R/W.
1 = Enable. Must be set to 1 to enable the configuration accesses from the SMBus Port.
0 = Disable. (default)
Command (CMD)—R/W. These bits represent the command that is to be performed. The
encodings are as follows:
000 = NOP: Normal Power-up State for the register. (default)
001 = Write Byte: Writes the byte in the Data Register bits [7:0] to the configuration location
specified by the Bus Number, Device/Function and Register Number registers.
010 = Write Word: Writes the bytes in the Data Register bits [15:0] to the configuration location
specified by the Bus Number, Device/Function and Register Number registers. The
Register Number [0] bit is ignored for this operation, all word writes must be aligned on a
word boundary.
2:0
011 = Write DWord: Writes the bytes in the Data Register [31:0] to the configuration location
specified by the Bus Number, Device/Function and Register Number registers. The
Register Number [1:0] bits are ignored for this operation, all DWord writes must be aligned
on a DWord boundary.
100 = Read DWord: Reads the configuration location specified by the Bus Number,
Device/Function and Register Number registers to the Data Register [31:0]. The Register
Number [1:0] bits are ignored for this operation, all DWord reads must be aligned on a
DWord boundary.
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3.5.2
BNUM—Bus Number Register
Offset:
Default Value: 00h
01h
Attribute:
Size:
R/W
8 bits
This register should be programmed with the Bus Number of the desired configuration register.
The Status Register should be checked to make sure that there is not a command currently in
progress, before writing to this register. Writing to this register when the ’Busy’bit in the Status
Register is asserted will have indeterminate effects.
Bits
Description
7:0
Number (NUM). This field indicates the bus number to access.
3.5.2.1
DFNUM—Device / Function Number Register
Offset:
Default Value: 00h
02h
Attribute:
Size:
R/W
8 bits
This register should be programmed with the Device Number and Function Number of the desired
configuration register. The Status Register should be checked to make sure that there is not a
command currently in progress, before writing to this register. Writing to this register when the
’Busy’bit in the Status Register is asserted will have indeterminate effects.
Bits
Description
7:3
2:0
Device Number (DEV). This field provides the Device number of device to access.
Function Number (FNC). This field provides the Function number of device to access.
3.5.3
RNUM—Register Number
Offset:
Default Value: 00h
03h
Attribute:
Size:
R/W
8 bits
This register should be programmed with the Register Number of the desired configuration
register. The Status Register should be checked to make sure that there is not a command currently
in progress, before writing to this register. Writing to this register when the ’Busy’bit in the Status
Register is asserted will have indeterminate effects.
Bits
Description
7:0
Number (NUM). Indicates the register number to access
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Register Description
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3.5.3.1
DATA—Data Register
Offset:
04–07h
Attribute:
Size:
R/W
32 bits
Default Value: 00000000h
This register is used to read or write data to the desired configuration register. At the completion
of a Read command, this register contains the data from the selected configuration register. For
reads, the data register will always return 32 bits and will always be aligned on a DWord
boundary.
Before issuing a write command this register should be written with the desired write data. For a
byte write, only the D[7:0] data will be written to the desired configuration register. For a word
write, only the D[15:0] data will be written to the desired configuration register. The register
number must be word aligned for word writes. For a DWord write, all 32 bits of data will be used.
The register number must be DWord aligned.
The Status Register should be checked to make sure that there is not a command currently in
progress, before writing to this register. Writing to this register when the Busy bit in the Status
Register is asserted will have indeterminate effects.
Bits
Description
31:24
23:16
15:8
7:0
Byte 3 (B3). Data bits [31:24]
Byte 2 (B2). Data bits [23:16]
Byte 1 (B1). Data bits [15:8]
Byte 0 (B0). Data bits [7:0]
3.5.4
CFG—SMBus Configuration Register
Offset:
Default Value: 00h
FFh
Attribute:
Size:
R/W
8 bits
This register contains various configuration options for the SMBus controller. When this register
is accessed, an internal configuration cycle on SMBus is not launched.
Bits
Description
7:1
Reserved
ICH Block Mode.
0
1 = Indicates that the Intel® P64H2 SMBus controller should accept commands as if they were
ICH block mode commands.
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4 Functional Description
This chapter describes the PCI and PCI-X interfaces, hot plug controller, PCI transaction ordering,
I/OxAPIC controller, and system setup. Reliability, Availability, and Serviceability (RAS) is also
described.
4.1
PCI Interface
The P64H2 has two PCI interfaces (PCI Interface A and PCI Interface B). This section describes
the PCI interface on each P64H2 Bridge. These interfaces also support PCI-X. Refer to Section
4.2 for PCI-X interface operation.
4.1.1
Summary of Changes
The PCI interface of the 82870P2 P64H2 is similar to the PCI interface for the 82806AA P64H.
P64H2 enhancements include:
• 64-bit addressing outbound, with the capability to assert Dual Address Cycles (DAC).
• Full 64 bit addressing inbound from 44 bits on P64H.
• Inbound packet size based upon cache line size of the platform.
• I/O space can be programmed to 1 KB granularity through the EN1K bit of the CNF Register.
• If inbound reads are retried, they will be moved to the side so that posted writes and
completion packets can pass.
• I/O reads and writes on PCI will no longer be forwarded to the hub interface, nor will they be
forwarded to the other PCI interface.
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4.1.2
Transaction Types
Table 22 lists the PCI transactions supported by the P64H2. As a PCI master, the P64H2 has full
access to the 64-bit address space and can generate dual address cycles (DAC). As a target, the
P64H2 can accept dual address cycles up to the full 64-bit address space. The P64H2 supports the
linear increment address mode only for bursting memory transfers (indicated when the low 2
address bits are equal to 0). If either of these address bits is nonzero, the P64H2 disconnects the
transaction after the first data transfer.
The P64H2 decodes all PCI cycles in medium PxDEVSEL# timing.
Table 22. Intel® P64H2 PCI Transactions
Intel® P64H2 As
Intel® P64H2 As
Type of Transaction
Type of Transaction
Master
Target
Master
Target
Interrupt
acknowledge
0000
No
Yes
Yes
No
No
No
1000
Reserved1
Reserved1
No
No
No
No
No
0001
0010
Special cycle
1001
1010
Configuration
Read
I/O read
Yes
Configuration
Write
0011
0100
0101
0110
I/O write
Yes
No
No
No
1011
1100
1101
1110
1111
Yes
No
No
Memory Read
Multiple
Reserved1
Reserved1
Memory read
Memory write
Yes
Yes
Yes
Yes
Dual Address
Cycle
No
No
Yes
No
Memory Read
Line
Yes
Yes
Yes
Yes
Memory Write
and Invalidate
0111
No
NOTES:
1. The P64H2 never initiates a PCI transaction with a reserved command code and ignores reserved
command codes as a target.
4.1.3
Detection of 64-bit Environment
The P64H2 drives PxREQ64# low during PCIRST# on each PCI interface to signal that the bus is
a 64-bit bus.
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4.1.4
Data Bus
For supplying data, the P64H2 drives the following in the data phase:
• The low 32 bits of data on PxAD[31:0]
• The low four byte enable bits on PxC/BE[3:0]#
• The high 32 bits of data on PxAD[63:32] (64-bit data phases only)
• The high four byte enable bits on PxC/BE[7:4]# (64-bit data phases only)
As a PCI master, when the P64H2 drives PxREQ64# and detects PxACK64# asserted in the same
clock that it detects PxDEVSEL# asserted, every data phase then consists of 64 bits and eight byte
enable bits.
On write transactions, when the P64H2 does not detect PxACK64# asserted in the same clock that
it detects PxDEVSEL# asserted, it redirects all data to PxAD[31:0] and byte enables to
PxC/BE[3:0]#. For 64-bit memory-write transactions that end at an odd DWord boundary, the
P64H2 drives the byte enable bits to 1, and drive random but stable data on PxAD[63:32].
On read transactions, the P64H2 drives 8 bits of byte enables on PxC/BE[7:0]#. It generates byte
enables from hub interface byte enables, with the upper DWord driven on PxC/BE[7:4]#. If
PxACK64# is not sampled active with PxDEVSEL# active, then the P64H2 downshifts the all byte
enables PxC/BE[3:0]#.
The P64H2 does not assert PxREQ64# when initiating a transfer under the following conditions:
• The P64H2 is initiating an I/O transaction
• The P64H2 is initiating a configuration transaction
• The P64H2 is initiating a special cycle transaction
• A 1-DWord or 2-DWord transaction is being performed
• If the address of the hub interface initiated transaction is not QWord aligned
As a PCI target, the P64H2 does not assert PxACK64# when PxREQ64# was not asserted by the
initiator.
Posted
Posted write forwarding is used for memory write and for memory write-and-invalidate
transactions. When the P64H2 decodes a memory write transaction for the hub interface, it asserts
PxDEVSEL# and PxTRDY# in the same clock, provided that enough buffer space is available in
the posted data queue. The P64H2 adds no target wait states.
The P64H2 disconnects a write transaction when:
• The initiator terminates the transaction by deasserting PxFRAME# and PxIRDY#
• A 4 KB page boundary is reached
• The posted write data buffer fills up
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Non-Posted
Delayed write forwarding is not used. It is only for I/O write transactions. Since the P64H2 does
not support I/O write transactions across a bridge, these cycles all result in a master abort. Note
that configuration cycles are not allowed to cross a bridge as indicated in the PCI-to-PCI Bridge
Architecture Specification, Revision 1.1.
Fast Back-to-Back
The P64H2 allows fast back-to-back write transactions on PCI.
4.1.5
Read Transactions
Prefetchable
Any memory read multiple command on PCI that are decoded by the P64H2 are prefetched on the
hub interface. Prefetching may be optionally disabled if bit 4 of the P64H2 Configuration Register
(offset 40–41h) is set. The P64H2 does not prefetch past a 4 KB page boundary.
Delayed
All memory read transactions are delayed read transactions. When the P64H2 accepts a delayed
read request, it samples the address, command, and address parity. This information is entered into
the delayed transaction queue. All I/O transactions will master abort.
4.1.6
Configuration Transactions
Type 0 configuration transactions are issued when the intended target resides on the same PCI bus
as the initiator. A Type 0 configuration transaction is identified by the configuration command and
the lowest 2 bits of the address set to 00b.
Type 1-configuration transactions are issued when the intended target resides on another PCI bus,
or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is
identified by the configuration command and the lowest 2 address bits set to 01b.
The register number is found in both Type 0 and Type 1 formats and gives the DWord address of
the configuration register to be accessed. The function number is also included in both Type 0 and
Type 1 formats and indicates which function of a multifunction device is to be accessed. For
single-function devices, this value is not decoded. Type 1 configuration transaction addresses also
include a 5-bit field designating the device number that identifies the device on the target PCI bus
that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to
which the transaction is targeted.
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Type 0 Accesses to the Intel® P64H2
The configuration space of the bridge in the P64H2 is accessed by a Type 0 configuration
transaction on the hub interface. The bridge configuration space (as well as the I/OxAPIC and hot
plug configuration spaces) cannot be accessed from PCI. The P64H2 responds to a Type 0
configuration transaction when the following conditions are met by the hub interface address:
• The bus command is a configuration read or configuration write transaction
• Low 2 address bits AD[1:0] must be 00b
• The device number matches one of the P64H2 devices (31–27)
Type 1 to Type 0 Translation
The P64H2 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on
the hub interface and is intended for a device attached directly to the secondary bus. The P64H2
must convert the configuration command to a Type 0 format so that the secondary bus device can
respond to it. This translation is done only for cycles that originate on the hub interface and target
PCI.
The P64H2 translates a Type 1 configuration transaction into a Type 0 transaction under the
following conditions:
• The bus command is a Configuration read or write transaction.
• The low 2 address bits on PxAD [1:0] are 01b.
• The bus number in address field PxAD [23:16] is equal to the value in the secondary bus
number register in P64H2 configuration space.
The resulting Type 0 address to be driven on PCI is shown in Figure 2 Device numbers are
decoded to generate a single 1 in address bits [31:16]. If the device number is greater than 16, all
bits are 0.
Figure 2. Type 1 to Type 0 Translation
31
16 15 11 10 7 6
2 1 0
HI Address
Reserved ’0’
Only one ’1’
Dev ID Fnc Register 01
PCI Address
0000 Fnc Register 00
Translation_type1-type0
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Type 1 to Type 1 Forwarding
The P64H2 forwards a type 1-configuration cycle unchanged to the PCI bus under the following
conditions.
• The bus command is a configuration read or write transaction
• The low 2 address bits are equal to 01b
• The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus
number register and the upper limit (inclusive) in the subordinate bus number register
Type 1 to type 1 forwarding is only done for cycles from the hub interface to PCI.
Type 1 to Special Cycle Forwarding
The P64H2 translates a type 1 configuration write transaction on the hub interface into a special
cycle on PCI, but does not translate a type 1 configuration access on PCI to a special cycle on the
hub interface. A cycle to be translated has the following attributes in the address:
• The low 2 address bits on PxAD[1:0]are equal to 01b
• The device number in address bits PxAD[15:11] is equal to 11111b
• The function number in address bits PxAD[10:8] is equal to 111b
• The register number in address bits PxAD[7:2] is equal to 000000b
• The bus number is equal to the value in the secondary bus number register in configuration
space
• The bus command is a Configuration Write command
The address and data are forwarded unchanged. Devices ignore the address and decode only the
bus command. The data phase contains the special cycle message. The transaction will master
abort, but results in a normal completion on the opposite bus (normal completion status on the hub
interface TRDY# on PCI). If more than one data transfer is requested, the P64H2 responds with a
target disconnect operation during the first data phase.
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4.1.7
Transaction Termination
Normal Master Termination
As a PCI master, the P64H2 uses normal termination if PxDEVSEL# is returned by the target
within five clock cycles of PxFRAME# assertion. It terminates a transaction when the following
conditions are met:
• All write data for the transaction is transferred from the P64H2 data buffers to the target.
• The master latency timer expires and the P64H2’s bus grant is de-asserted.
Master Abort Termination
If a P64H2-initiated transaction is not responded to with PxDEVSEL# within five clocks of
PxFRAME# assertion, the P64H2 terminates the transaction with a master abort. The P64H2 sets
the received master abort bit in the status register corresponding to the target bus.
Note: When the P64H2 performs a Type 1 to special cycle translation, a master abort is the expected
termination for the special cycle on the target bus. In this case, the master abort received bit is not
set, and the Type 1 con-figuration transaction is disconnected after the first data phase.
Target Termination Received by the Intel® P64H2
When the P64H2 receives a retry or disconnect response from a target, it will re-initiate the
transfer with the remaining length. If the P64H2 receives a target abort, and the cycle requires
completion on the hub interface, the P64H2 will return the target abort code to the hub interface as
the completion status.
Target Termination Initiated by the Intel® P64H2
The P64H2 returns a target retry to an initiator for memory read transactions when any of the
following conditions is met:
• A new transaction for delayed transaction queue.
• The request has already been queued, but has not completed on the hub interface.
• The delayed transaction queue is full, and the transaction cannot be queued.
• A LOCK transaction has been established from the hub interface to PCI.
The P64H2 disconnects an initiator when one of the following conditions is met:
• The P64H2 cannot accept any more write data
• The P64H2 has no more read data to deliver
• If the memory address is non-linear
The P64H2 returns a target abort to PCI when the cycle master aborted or target aborted on the
hub interface.
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4.1.8
Lock Cycles
A lock is established when a memory read from the hub interface that targets PCI with the lock bit
set, and at least one byte enable active, is responded to with a PxTRDY# by a PCI target. The
P64H2 does not support a split-lock request when no byte enables are asserted on the initial locked
read request. The bus is unlocked when the Unlock Special Cycle is sent on the hub interface.
When the bus is locked, if a memory cycle originates on PCI that is outside the range of the
memory windows, the cycle is retried. No I/O cycles that are destined across the bridge are
accepted, whether the bus is locked or not, and will master abort.
Once the bus is locked, any hub interface cycle to PCI will be driven with the PxLOCK# pin, even
if that particular cycle is not locked. This should not occur; this is because under lock, peer-to-peer
accesses should be blocked.
When one PCI bus segment is locked, the other is still free to accept cycles (i.e., that bus is not
locked). However, these cycles must not be allowed to proceed on the hub interface or the locked
PCI segment. Therefore, once the PCI bus is locked, no more cycles must proceed onto the hub
interface from the non-locked PCI segment, or from the I/OxAPICs.
4.1.9
Error Handling
The P64H2 checks and generates ECC or parity on the hub interface and parity on the PCI
interfaces. Parity errors must always be reported to some system level software, typically the
device driver or the OS. This section describes how a standard PCI bridge handles these errors.
For enhanced error detection, see Section 4.9.
To support error reporting on the PCI bus, the P64H2 implements the following:
• PxPERR# and PxSERR# signals on PCI
• DO_SERR special cycle on the hub interface
• Primary Device Status Register (PD_STS Register, offset 06–07h) and Secondary Status
Register (SECSTS Register, offset 1E–1Fh)
The P64H2 does not have the PERR# or SERR# pins on the hub interface. Further, the P64H2 is
not capable of generating NMI, SMI, or INTR. If enabled, the P64H2 reports the error using the
hub interface DO_SERR special cycle. The device receiving this cycle must forward that cycle to
a device that can generate the error condition (NMI, SMI, SCI) to the processor.
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4.1.9.1
Address Parity Errors
The P64H2 checks address parity for all transactions on both the hub interface and PCI buses, for
all address and all bus commands. Address parity errors are very serious and may abort further
data transfers, depending on the direction of the transfer and the setting of the Parity Error
Response bit (PD_STS Register).
When the P64H2 detects a parity error or multiple-bit ECC error in the header section of a hub
interface packet, it:
• Sets the Detected Parity Error bit (bit 15) in the PD_STS Register (offset 06–07h) if the
address is targeting the device. The bridge devices will log address parity errors independent
of the target address.
• Initiates the DO_SERR special cycle, and sets the signaled system error bit (bit 14) in the
PD_STS Register (offset 06–07h), if the Parity Error Response bit (bit 6) in the PCI Device
Command Register (PD_CMD, offset 04–05h) is set and SERR# is enabled.
• Will attempt to interpret the cycle as best as it can and will forward it with an address parity
error tag to the internal logic where it will abort internally. If a device is not enabled to
respond to parity errors, it will ignore the address parity error (except for setting the Detected
Parity Error bit) and if the address targets that device, accept the cycle and respond as if there
was no address parity error. The cycle will be forwarded to PCI with good address parity if
the cycle targets a bridge and it is not enabled to respond to parity errors.
If a single bit ECC error is detected during the header section, it is corrected and none of the above
occurs.
When the P64H2 detects an address parity error on the PCI interface, the following events occur:
• The P64H2 sets the detected parity error bit (bit 15) in the Secondary Status Register
(offset 1E–1Fh).
• If the parity error response bit (bit 0) is 0 in the Bridge Control Register (offset 3E–3Fh), the
address parity errors are ignored. The cycles would be treated as if no error was observed.
• If the parity error response bit is set and the address parity error is observed on memory
cycles, then the cycle is accepted as if the address was correct; Delayed Transactions
established for memory reads and data posted for memory writes. The cycles are forwarded to
the hub interface with correct address parity.
The P64H2 initiates the DO_SERR special cycle on the hub interface and sets the signaled system
error bit in the PCI Primary Device Status (PD_STS) Register, if all of the following conditions
are met:
• The SERR# enable bit is set in the PCI Primary Device Command Register.
• The parity error response bit is set in the Bridge Control Register.
• The SERR# enable bit is set in the Bridge Control Register.
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4.1.9.2
Data Parity Errors
Unlike address parity errors, data parity errors are not considered as severe and transactions are
not aborted. The following sections describe the sequence of events when a data parity error is
detected for the following transactions:
• Configuration Write Transactions
• Read Transactions (inbound and outbound)
• Posted Write Transaction
4.1.9.3
Hub Interface Configuration Write Transactions
When the P64H2 detects a data parity error during a Type 0 configuration write transaction to one
of the P64H2 configuration spaces, the P64H2:
• Does not write the data to the configuration register if parity error response is enabled.
• Sets the Detected Parity Error bit (bit 15) in the PD_STS Register (offset 06–07h) of the
target (APIC, hot plug, bridge).
• Initiates the DO_SERR special cycle and sets the signaled system error bit (bit 14) in the
PD_STS Register, if the Parity Error Response Enable bit (bit 6) in the PD_CMD Register
(offset 04–05h) is set.
4.1.9.4
Read Transactions from Hub Interface Targeting PCI
When the P64H2 detects a read data parity error on the PCI bus from a hub interface initiated
read, it:
• Sets the Detected Parity Error bit (bit 15) in the Secondary Status Register (offset 1E–1Fh).
• Sets the Data Parity Detected bit (bit 8) in the Secondary Status Register (offset 1E–1Fh), if
the secondary interface parity error response bit (bit 0) is set in the Bridge Control Register
(offset 3E–3Fh).
• Forces bad parity or a multi-bit ECC error with the data back to the initiator on the hub
interface.
4.1.9.5
Read Transactions from PCI Targeting Hub Interface
When the P64H2 detects a data parity or multi-bit ECC error on a hub interface completion packet
from a previous memory read request on PCI, the P64H2:
• Sets the Detected Parity Error bit (bit 15) in the PD_STS Register (offset 06–07h).
• Sets the Data Parity Detected bit (bit 8) in the PD_STS Register (offset 06–07h) and generates
the DO_SERR special cycle, if the Primary Interface Parity Error Response bit (bit 6) is set in
the PD_CMD Register (offset 04–05h).
• Forwards the bad parity with the data back to PCI.
If a single bit ECC error is detected, it is corrected and none of the above occurs.
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4.1.9.6
Write Transactions on Hub Interface (Intel® P64H2 As Hub Interface
Target)
When the P64H2 detects a data parity or multi-bit ECC error on a hub interface write request, it:
• Sets the Data Parity Error Detected bit (bit 15) in the PD_STS Register
(offset 06–07h) of the target interface (APIC, hot plug, PCI bridge primary).
• If decoded by the bridge, it forwards the bad parity with the data to PCI. If the cycle is
decoded by the APIC or the hot plug controller, (memory writes only), does not perform the
write.
• Initiates the DO_SERR special cycle and sets the Signaled System Error bit (bit 14) in the
PD_STS Register, if the Parity Error Response bit (bit 6) is set in the PD_CMD Register.
If a single bit ECC error is detected, it is corrected and none of the above occurs.
4.1.9.7
4.1.9.8
Write Transactions on Hub Interface (Intel® P64H2 As Hub Interface
Master)
There is no way of detecting that the MCH detected a parity error from a hub interface posted
write from PCI. Therefore, no action is taken by the P64H2.
Write Transactions on PCI (Intel® P64H2 As PCI Target)
When the P64H2 detects a data parity error on a PCI write, it:
• Asserts PERR# two cycles after the data transfer, if the secondary interface parity error
response bit is set in the Bridge Control Register.
• Sets the secondary interface Parity Error Detected bit in the Secondary Status Register.
• Forces bad parity or a multi-bit ECC error condition to the primary bus.
4.1.9.9
Write Transactions on PCI (Intel® P64H2 As PCI Master)
When a data parity error is reported on the PCI bus from a hub interface or PCI peer initiated write
request by the target’s assertion of PERR#, the P64H2:
• Sets the Detected Parity Detected bit (bit 8) in the Secondary Status Register (offset 1E–1Fh),
if the secondary interface parity error response bit is set in the bridge control register.
• Initiates DO_SERR special cycle and sets the Signaled System Error bit in the PD_STS
Register, if all of the following conditions are met:
• The SERR# enable bit is set in the PD_CMD Register.
• The Secondary Interface Parity Error Response bit is set in the Bridge Control Register.
• The Primary Interface Parity Error Response bit is set in the PD_CMD Register.
• The P64H2 did not detect the parity error on the hub interface (i.e., the parity error was not
forwarded from the hub interface).
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4.1.9.10
4.1.9.11
System Errors
PCI SERR# Pin Assertion
When PxSERR# is sampled asserted, the P64H2 sets the received system error bit in the secondary
status register. It generates the DO_SERR special cycle if:
• The SERR# Forward Enable bit is set in the Bridge Control Register, and
• The Primary SERR# Enable bit is set in the PD_CMD Register.
4.1.9.12
Other System Errors
The P64H2 also conditionally initiates the DO_SERR special cycle for any of the following
reasons:
• Parity error reported on target bus during write transactions
• Master timeout on delayed transaction if the Primary SERR# Enable bit is set and SERR# due
to Timeout Enable bit (bit 11 of offset 3E–3Fh) is set.
• The MAM bit (Master Abort Mode) is set in the Bridge Control Register and a posted write
from the hub interface results in a master abort on PCI, or a posted write from one PCI
interface results in a master abort on the other PCI interface. (No indication is given back on
the hub interface if a posted PCI write fails on the hub interface – the MCH must handle this
condition).
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4.2
PCI-X Interface
Both of the P64H2 PCI interfaces support PCI-X. This section does not describe the PCI-X
protocol. Rather, it describes the P64H2 behavior in areas of the specification that are open to
interpretation. For a detailed description, refer to the PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0.
Unless otherwise noted in this section, the P64H2 follows all rules of the PCI-X Addendum to the
PCI Local Bus Specification, Revision 1.0.
4.2.1
Command Encoding
Table 23 lists the PCI-X commands supported by the P64H2.
Table 23. Command Encoding
Intel P64H2 As
Intel P64H2 As
Type of Transaction
Type of Transaction
Master
Target
Master
Target
Interrupt
0000
Alias to Memory
Read Block
No
No
1000
No
No
Yes
acknowledge
Alias to Memory
Write Block
0001
0010
Special cycle
I/O read
No
No
No
1001
1010
Yes
No
Configuration
Read
Yes
Yes
Configuration
Write
0011
0100
0101
I/O write
Reserved
Reserved
Yes
No
No
No
No
1011
1100
1101
Yes
Yes
Yes
No
Yes
Yes
Split Completion
Dual Address
Cycle
No
Memory Read
DWord
Memory Read
Block
0110
0111
Yes
Yes
Yes
Yes
1110
1111
Yes
No
Yes
Yes
Memory Write
Block
Memory Write
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4.2.2
Attributes
Table 24 describes how the P64H2 fills in attribute fields where the PCI-X Addendum to the PCI
Local Bus Specification, Revision 1.0 leaves some implementation leeway.
Table 24. Intel® P64H2 Implementation of Requester Attribute Fields
Attribute
Function
As a target, this bit is forwarded with the transaction to allow the MCH to not snoop the
transaction. It goes to bit 1 in the TD Attribute field of the hub interface packet. It is not
generated by the Intel® P64H2 as a master from a hub interface packet. The P64H2
takes no action on this bit.
No Snoop (NS)
This bit allows relaxed ordering of transactions, which the P64H2 does not permit. This
bit is forwarded in the P64H2 and is never generated on PCI-X from a hub interface
packet.
Relaxed
Ordering (RO)
Since the P64H2 only has one outstanding request on PCI-X at a time, this field is
always set to 0.
Tag
From the hub interface, this is based upon the length field from the hub interface, which
is DWord based.
Byte Counts
4.2.3
4.2.4
Burst Transactions
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0 allows burst transactions
to cross page (in the P64H2’s case, this is 4 KB) and 4 GB address boundaries. As a PCI-X
master, the P64H2 will always end the transaction at a 4 KB boundary. As a PCI-X target, the
P64H2 will allow a burst past a 4 KB page boundary.
The P64H2 never issues an immediate response as a target for a burst read command, but it must
be ready with 128 bytes of data space (an ADQ) as an initiator. If it does not have this space
available, it does not issue the transaction.
Device Select Timing
PCI-X targets are required to claim transactions by asserting PxDEVSEL# as shown in Table 25.
The P64H2 always responds as a type A target.
Table 25. DEVSEL# Timing
Decode Speed
PCI-X
1 clock after address phase(s)
2 clocks after address phase(s)
3 clocks after address phase(s)
4 clocks after address phase(s)
5 clocks after address phase(s)
6 clocks after address phase(s)
Not Supported
Decode A
Decode B
Decode C
N/A
Subtractive
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4.2.5
Wait States
The P64H2 never generates wait states as a target; it ends the transfer.
4.2.6
Split Transactions
4.2.6.1
Completer Attributes
Table 26. Intel® P64H2 Implementation Completion Attribute Fields
Attribute
Function
This bit is used for diagnostic purposes. The Intel® P64H2 never
sets this bit.
Byte Count Modified (BCM)
The P64H2 only sets this bit if a memory read command from PCI-
X master or target aborted on the hub interface.
Split Completion Error (SCE)
Split Completion Message (SCM)
This bit shadows the SCE bit.
4.2.6.2
4.2.6.3
Requirements for Accepting Split Completions
The P64H2 asserts PxDEVSEL# and discards the data if the Requester ID matches the bridge, but
the tag does not match that of any outstanding requests from this device, or if the byte count
exceeds that of the split request.
The hub interface accepts more than one completion required request from the hub interface, but
only one will be pending on any PCI/PCI-X interface at a time.
Split Completion Messages
The P64H2 can only generate error messages for cycles that cross the bridge that master or target
abort. No DWord cycles will cross the bridge that requires completion (i.e., I/O cycles). Therefore,
the P64H2 can only generate a “PCI-X Bridge Error” completion message for the memory read
commands as indicated in Table 27.
Table 27. Split Completion Abort Registers
Index
Message
00h
01h
Master-Abort: The Intel® P64H2 encountered a Master-Abort on the destination bus.
Target-Abort: The P64H2 encountered a Target-Abort on the destination bus.
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4.2.7
Arbitration Among Multiple Split Completions
The P64H2 will fairly arbitrate amongst all active split completions such that each completion will
get a fair shot at running on PCI. If there are multiple completions waiting to use PCI, the P64H2
will internally arbitrate based upon its MLT value, even if no other agents are requesting on the
bus. Therefore, the P64H2 will end one transaction when its MLT expires, reload, and start
another transaction.
If any particular transaction runs out of data and there are other active transactions to run, the
P64H2 will also switch to the next agent, even if the MLT has not expired for that transaction.
Finally, the prefetch algorithm will be altered such that several transactions can be active at one
time. See Section 3.2.48 for more information on prefetch algorithms.
4.2.8
Transaction Termination as a PCI-X Target
Retry
The P64H2 will retry a cycle when the Split Request queue is full. (i.e. we already have 4 current
and 4 pending Split Transactions). It will always have room to accept a split completion as it has a
dedicated buffer for split completions. It will also retry a cycle when the bus is locked. The P64H2
stores no state from the transaction on a retry.
Split Response
All cycles that cross the bridge receive a split response termination, if they are not retried.
Master-Abort
Any I/O transaction that would cross from PCI-X to either the hub interface or the peer bridge are
not decoded and result in a master abort to the PCI-X initiator.
4.2.9
Arbitration
The P64H2 always parks on the last agent to use PCI. This allows PCI devices operating as a
single stream to stay on the PCI bus for the duration of their transfer.
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4.2.10
System Initialization
Encoding on the PxM66EN and PxPCIXCAP pin as shown below identifies the capabilities of the
system. The following tables are included from the PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0 for easy reference.
Table 28. M66EN and PCIXCAP Encoding
PxM66EN
Ground
PxPCIXCAP
Ground
PCI Capability
PCI-X Capability
33 MHz
66 MHz
33 MHz
66 MHz
33 MHz
66 MHz
Not capable
Not capable
Not connected
Ground
Ground
Pull-down
PCI-X 66 MHz
PCI-X 66 MHz
PCI-X 133 MHz
PCI-X 133 MHz
Not connected
Ground
Pull-down
Not connected
Not connected
Not connected
Table 29. PCI-X Initialization Pattern
Clock Period
(ns)
Clock Freq
(MHz)
PxDEVSEL#
PxSTOP#
PxTRDY#
Mode
Max
Min
Min
Max
PCI 33
PCI 66
PCI-X
PCI-X
PCI-X
PCI-X
PCI-X
PCI-X
PCI-X
∞
30
15
15
10
7.5
0
33
33
66
Deasserted
Deasserted
Deasserted
30
20
15
10
Deasserted
Deasserted
Deasserted
Asserted
Deasserted
Asserted
Asserted
Deasserted
Asserted
50
66
66
100
133
Asserted
100
Deasserted
Deasserted
Asserted
Deasserted
Asserted
Asserted
Reserved
Asserted
Deasserted
Asserted
Asserted
Asserted
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4.2.11
Bridge Buffer Requirements
The P64H2 always has 128 bytes (1 ADQ) available for accepting memory write, split completion,
and immediate read data. The P64H2 contains 1.5 KB of data total for inbound transactions.
The P64H2 PCI-X interface terminates all memory transactions (Memory Read DWord, Memory
Read Block, and Alias to Memory Read Block) that address the MCH with a Split Response.
Other split transaction commands are not decoded by the P64H2.
The P64H2 does not implement any split completion buffer allocation algorithm as listed in the
PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0. This is not necessary. The
P64H2 never requests, on the hub interface, more than it has buffer space for on returns, and does
not initiate a cycle from the hub interface that it cannot accept as a return. The bridge rules of the
specification already allow the PCI-X interface to retry split completions if the bridge is
temporarily full.
Therefore, the split transaction control registers are not used by the P64H2.
Cycle Translation Between Interfaces
Conventional PCI to PCI-X / Hub Interface
4.2.12
4.2.12.1
Table 30. Conventional PCI to PCI-X / Hub Interface
Conventional PCI Command
PCI-X as Target
Hub Interface as Target
I/O Read / Write
Master Abort at source (not supported)
Master Abort at source (not supported)
Configuration Read / Write
Memory Read, Memory read line,
memory read multiple
Forward to hub interface unless
the peer mode test bit is set
Memory Read
Memory Write
Memory Write
Memory Write
Memory Write
Memory Write and Invalidate
Memory Write
The attribute phase on the PCI-X transfer has the following characteristics:
• The P64H2 uses the primary bus number as its Bus Number
• Sets the Device Number and Function Number fields to 0
• Clears the Relaxed Order or No Snoop attribute bits on transactions forwarded from a
conventional bus.
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4.2.12.2
PCI-X to Conventional PCI (peer) / Hub Interface
Table 31. PCI-X to Conventional PCI (peer) / Hub Interface
PCI-X Command
I/O Read / Write
PCI as Target
Hub Interface as Target
Master Abort at source (not supported)
Master Abort at source (not supported)
Configuration Read / Write
Memory Read DWord, Memory
Read Block
Forward to hub interface unless
the peer mode test bit is set
Memory Read
Memory Write
Memory Write, Memory Write Block
Memory Write
4.2.13
4.2.14
Locked Transactions
The P64H2 is not locked until the target has completed at least the first data phase as an
Immediate Transaction or a Split Transaction (target signals Split Response).
Error Support
General
As a PCI-X target, the P64H2 bridge responds as specified in the PCI-X Addendum to the PCI
Local Bus Specification, Revision 1.0, except that all memory read transactions that leave this
bridge and target the other bridge will be set to the hub interface, unless the peer mode test bit is
set.
Special Parity Error Rule for Split Response
If the P64H2 calculates a data parity error when a target signals Split Response for a read
transaction, it records the error as described in Section 5.4.1 of the PCI-X Addendum to the PCI
Local Bus Specification, Revision 1.0. Furthermore, if the P64H2 is enabled to assert PERR# on
the secondary bus and enabled to assert SERR# on the hub interface, it must generate a DO_SERR
packet on the hub interface.
4.2.15
Transaction Termination Translation Between Interfaces
Though the P64H2’s primary bus is the hub interface, from a register and software perspective, the
hub interface is a PCI-X bus and the P64H2 is a PCI-X bridge that supports a secondary bus
configured as either PCI or PCI-X.
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0 (Section 8.7.1.5) modified
the behavior of a bridge from that specified in the PCI-to-PCI Bridge Architecture Specification,
Revision 1.1 regarding returning completions on the primary bus when the secondary bus
transaction terminates in either a master abort or target abort. In general, the PCI-X Addendum to
the PCI Local Bus Specification, Revision 1.0 does not honor the Master Abort Mode bit for
cycles requiring completions and returns to the primary bus the termination that occurred on the
secondary bus without any translation.
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The following sections describe the behavior of the P64H2 on both the hub interface and PCI/PCI-
X Bus under various termination conditions. For specific information as to why the P64H2’s PCI,
PCI-X, or hub interface generates a specific termination, see the specific sections on the interface
above.
4.2.15.1
Behavior of Hub Interface Initiated Cycles to PCI/PCI-X Receiving
Immediate Terminations
The behavior described for completion required cycles is independent of the setting of the Master
Abort Mode bit and is independent of whether the cycle is exclusive (locked) or not. The P64H2
will return all 1s on data bytes for a read completion that terminates in either Master Abort or
Target Abort.
Table 32. Immediate Terminations of Completion Required Cycles to PCI/PCI-X
PCI/PCI-X
Termination
Hub Interface Completion
Status Register Bits Set
Successful
Successful
Mater Data Parity Error (Sec) 1
Received Mater Abort (Sec)
Mater Abort
Target Abort
Master Abort
Target Abort
Received Target Abort (Sec)
Signaled Target Abort (Pri)
Master Data Parity Error (Sec) 1
NOTES:
1. The Master Data Parity Error bit is set only if a data parity error was encountered on the PCI/PCI-X Bus.
Table 33. Immediate Terminations of Posted Write Cycles to PCI/PCI-X
PCI/PCI-X
Termination
MAM Bit
Hub Interface
Cycle
Status Register Bits Set
Successful
N/A
1
None
None
Master Abort
Do_SERR 1
Received Master Abort (Sec)
Signaled System Error (Pri) 1
Master Abort
Target Abort
0
None
Received Master Abort (Sec)
N/A
DO_SERR 1
Received Target Abort (Sec)
Signaled System Error (Pri) 1
NOTES:
1. The DO_SERR cycle and setting of the Signaled System Error bit only occur if the SERR#
enabled in the Primary Command Register is set.
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4.2.15.2
Behavior of Hub Interface Initiated Cycles to PCI-X Receiving Split
Terminations
The behavior described in the following table is independent of the Master Abort Mode bit and
whether or not the cycle is exclusive (locked) or not. P64H2 will return all 1s on all data bytes for
a read completion that terminates in either Master Abort or Target Abort on the hub interface.
Note that when a target or master abort is returned on the hub interface, the attached PCI/PCI-X
bus is not locked. This is of special importance to the completion messages of data parity error,
byte count out of range, write data parity error, device specific, and reserved / illegal codes.
P64H2 must not lock its bus on these errors, even though they are not explicitly master or target
aborts on the PCI-X interface.
Table 34. Split Terminations of Completion Required Cycles to PCI-X
PCI-X Split
Termination
Message
Hub Interface
Completion
Status Register Bits Sets
Class Index
Successful
0
00h
Successful
• Master Data Parity Error (Sec), if
encountered
Master Abort
Target Abort
1
1
00h
01h
Master Abort
Target Abort
• Received Master Abort (Sec)
• Received Target Abort (Sec)
• Signaled Target Abort (Pri)
Write Data Parity Error
1
02h
Target Abort
• Master Data Parity Error (Sec)
• Signaled Target Abort (Pri)
Byte Count Out of Range
Write Data Parity Error
2
2
00h
01h
Target Abort
Target Abort
• Signaled Target Abort (Pri)
• Master Data Parity Error (Sec)
• Signaled Target Abort (Pri)
Device Specific
Reserved/Illegal
2
8Xh
Target Abort
Target Abort
• Signaled Target Abort (Pri)
• Signaled Target Abort (Pri)
Others
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4.2.15.3
Hub Interface Action on Immediate Responses to PCI-X Split
Completions
Table 35 indicates what the P64H2 will do if it is returning a split completion to PCI-X from a
normal hub interface completion and receives an immediate response indicating an error. Table 36
indicates the behavior of PCI/PCI-X Initiated Cycles to Hub Interface.
Table 35. Response to PCI-X Split Completions
Split Completion
Termination
Hub Interface Cycle
Status Register Bits
Successful
None
• None
Master Abort
DO_SERR 1
DO_SERR 1
• Received Master Abort (Sec)
• Split Completion Discarded (Sec)
• Signaled System Error (Pri) 1
Target Abort
• Received Target Abort (Sec)
• Split Completion Discarded (Sec)
• Signaled System Error (Pri) 1
NOTES:
1. The DO_SERR cycle and setting of the Signaled System Error bit only occur if the SERR# enabled in
the Primary Command Register is set.
Table 36. Terminations of Completion Requited Cycles to Hub Interface
Hub Interface Termination
PCI Completion
Successful
Status Register Bits Set
• None
Successful
Master Abort (PCI)
Target Abort 1
• Received Master Abort (Pri)
• Signaled Target Abort (Sec)
Master Abort (PCI-X)
Target Abort
Split Master Abort 2
• Received Master Abort (Pri)
Target Abort (PCI) 1
• Received Target Abort (Pri)
• Signaled Target Abort (Sec)
Split Target Abort (PCI-X) 2
Master and Target Abort
Target Abort (PCI) 1
• Received Master Abort (Pri)
• Received Target Abort (Pri)
• Signaled Target Abort (Sec)
Split Target Abort (PCI-X) 2
NOTES:
1. The P64H2 will only signal Target Abort if the error has been logged from the hub interface before the
initial connect by PCI or when the PCI master reconnects after a previous disconnect. If the P64H2
receives an abort on the hub interface in the middle of a read completion stream, it will not interrupt the
stream to signal Target Abort.
2. The P64H2 will issue a Split Completion Error Message with either Master Abort or Target Abort for the
remaining completion sequence if an abort is detected on the hub interface. If several bytes of data are
returned successfully from the hub interface and have not yet been sent back on PCI-X, when the abort
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is detected on the hub interface, the P64H2 will stop the current sequence for that data (if it was
running) and generate the Split Completion Error Message.
4.2.16
Configuration Transactions
Type 0 configuration transactions are issued when the intended target resides on the same PCI-X
bus as the initiator. A Type 0 configuration transaction is identified by the configuration command
and the lowest 2 bits of the address set to 00b.
Type 1-configuration transactions are issued when the intended target resides on another PCI-X
bus, or when a special cycle is to be generated on another PCI-X bus. A Type 1 configuration
command is identified by the configuration command and the lowest 2 address bits set to 01b.
The register number is found in both Type 0 and Type 1 formats and gives the DWord address of
the configuration register to be accessed. The function number is also included in both Type 0 and
Type 1 formats and indicates which function of a multifunction device is to be accessed. For
single-function devices, this value is not decoded. Type 1 configuration transaction addresses also
include a 5-bit field designating the device number that identifies the device on the target PCI-X
bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI-X
bus to which the transaction is targeted.
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4.3
Hot Plug Controllers
The P64H2 hot plug controller allows PCI card removal, replacement, and addition without
powering down the system. In this section the standard specification signal names are used for the
hot plug signal names and PCI signal names. For actual P64H2 signal names, the letters “A” and
“B” are used in the signal names to distinguish between PCI Interface A and PCI Interface B.
4.3.1
System Architecture
The P64H2 hot plug controller resides in Function 0 of the secondary bus device 31. It supports
three to six PCI slots through an input/output serial interface when operating in Serial Mode, and 1
to 2 slots through an input/output parallel interface when operating in Parallel Mode. The input
serial interface is polling and is in continuous operation. The output serial interface is “demand”
and acts only when requested. These serial interfaces run at about 8.25 MHz regardless of the
speed of the PCI bus. In parallel mode, the P64H2 performs the serial to parallel conversion
internally, so the serial interface cannot be observed. However, internally the hot plug controller
always operates in a serial mode.
4.3.1.1
Output Control
The output interface is responsible for driving seven bits per slot (plus 8 general purpose output
bits in serial mode).
• POWER ENABLE: Connected to an analog component designed to regulate current and
voltage of the slot, and generates a (power) fault signal when an abnormal condition is
detected.
• CLOCK ENABLE#, BUS ENABLE#: Connects the PCI bus and clock signal of the slot to
the system bus PCI bus via FET isolation switches.
• RESET#: Connected to the PCIRST# pin of the slot.
• AMBER and GREEN LEDs: Connected to LEDs on the chassis to indicate a slot’s status to
the user.
• General Purpose Outputs: (only in Serial Mode)
The general-purpose output bits are set using bits 0 through 7 of the General Purpose Output
Register (Offset 13h) in memory space. The other output bits are set by the hot plug controller
based on the Slot Power Enable Register (Offset 2Dh) and the Slot Enable Register (Offset 01h) in
memory space.
In a well-behaved environment, the output sequences are initiated by software. However, the hot
plug controller can act without software intervention to disable power to a slot and turn off its
LEDs, if a PCI card is being removed from a powered PCI slot.
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4.3.1.2
Input Control
The input interface captures eight inputs from each slot:
• SLOT SWITCH: Determines whether a slot should be powered. Connected to the slot switch
on the chassis.
• FAULT#: Over-current / Under-volt indication: When asserted, the P64H2, if enabled,
immediately asserts reset and disconnects the slot from the bus.
• PRSNT1# and PRSNT2#: Signals which determine whether or not a card is installed and to
budget system power. These inputs are connected to the PRSNT1# and PRSNT2# pins on the
PCI card.
• M66EN: Determines if a card can be added to the bus without reducing the clock frequency
of the PCI bus.
• PCIXCAP1 and PCIXCAP2: Determines if a slot is PCI-X capable, and if so, whether it can
operate at 133 MHz.
• 1 User-Defined Input: Stored in the Hot plug Non-Interrupt Inputs Register (although
marked as reserved bits 24 through 29.). This is available only in Serial Mode.
4.3.1.3
Stutter Mode
Stutter mode minimizes the amount of external hardware required to implement fewer than six
slots. The stutter mode used corresponds to the number of slots supported by the system. Stutter
mode selection is determined by HP_SLOT[2:0], as shown in Table 37.
Table 37. Stutter Logic Modes
HP_SLOT[2:0]
# of
Slots
Inputs
Outputs
000
001
010
011
100
101
110
111
Hot Plug Disabled
Parallel Mode—No Stutter
Parallel Mode—No Stutter
3
4
5
6
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Reserved (Hot plug Disabled)
Figure 3 shows how 6-slot stutter mode serial inputs are sampled. The serial clock stutters at bit
positions 6 and 7, but internally the bit shifted last (bit 5 in this example) is sampled as the next
successively stuttered bits (bit 6 and 7 in this example). This is why in some registers (e.g., the
memory register HMIC) bits for disabled slots take their values from the last enabled slot.
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Figure 3. Serial Input 6-slot Stutter Mode
HP_SIC
HP_SIL#
HP_SID
0
1
2
3
4
5
6
7
8
9
10 11
hotplug_6-slot_stutter
4.3.1.4
Serial Input Stream
The serial input stream constantly runs once the P64H2 is out of reset (RSTIN# deasserted). Under
normal operation, the input stream consists of a repeating series of 8 bytes of serial data. Note,
however, that because of stutter logic, some of these serial input bits are not shifted out of the
external shift registers (see previous section). It is possible to extend the serial input stream length
to 16 bytes through the use of the Serial Input Register.
The first 4-bytes of the serial input stream are interrupting inputs. The remaining 4-bytes are non-
interrupting inputs. Because only six-slots are supported by the P64H2, only 24 of the 32
interrupting inputs are available. Each slot has six inputs. The first group of inputs function as the
slot switches. The second group are slot power fault indicators. The remaining 12 interrupt-
capable inputs are the slot card present bits.
A change on any of the switch inputs initiates a 15 ms glitch filter timer. If a change is detected on
any slot switch input, the switch input is re-scanned 32 times within a 15 ms time interval. If the
switches remain stable for 32 samples, the HMIC is updated to reflect the change in state. If any
switch is still changing state, the glitch filter counter is cleared and the sequence restarts. If not
masked, a switch change interrupt is also generated after the HMIC changes state. The interrupt
function can be masked using the HMIR, but the HMIC always reflects a state change.
A change on any of the non-switch inputs causes an immediate change in the state of the HMIC.
An interrupt is also generated unless masked in the HMIR. After a non-switch input changes state,
further updates to all other non-switch bits of the HMIC is inhibited for an 8 ms de-bounce period.
This prevents a rapid succession of interrupts from being generated before software has time to
react.
In summary, an interrupt is generated and the interrupt pending bit is set in the MCNF Register in
memory space if all of the following are true:
• An interrupt is not already pending, and
• A switch input changes state and remains in its new state at the end of the glitch filter time
period, or a non-switch interrupting input has changed state at the beginning of the de-bounce
period, and
• The interrupt mask bit for that input is cleared (logic 0).
If an interrupt bit changes state in the HMIC and is not masked, the value is frozen in then HMIC
until acknowledged by writing 1 to this bit position. In the case of an unmasked non-switch input
already causing an interrupt to be generated, if the de-bounce timer expires and the interrupt has
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not been serviced (acknowledged), a single change in the state of an input could occur and be
posted (or buffered). The buffered value of this bit cannot be observed until the prior interrupt is
acknowledged.
Non-interrupting inputs follow at bytes 4–15. The P64H2 continually scans bytes 4–7 and stores
this data in the Hot plug Non-Interrupt Input Register. The timing of non-interrupt input scanning
for bytes 4–7 is identical to that of interrupt-capable inputs. Since scan timing cannot be easily
predicted, the memory register bit MCNF[12] status bit allows software to determine when an
eight-byte scan sequence is complete.
The current state of any of the inputs from bytes 0–15 can also be read one byte at a time through
the Serial Input Byte Pointer and Data Registers. When the byte pointer is written, the P64H2's
next scan in sequence continues shifting data in, until the appropriate byte is latched in the data
port. When the Serial Input Byte Pointer has been written, the Serial Input Busy Status bit
indicates when shifting of the selected input byte is complete. The value read from the data port is
unpredictable if it is read before shifting is complete. Bytes 8–15 can be accessed only using the
Serial Input Byte Pointer and Data port. Note that bytes 8–15 are not stuttered during scan in.
The shift clock frequency is a divide by 8 of the hub interface clock used to clock the hot plug
unit, and is approximately 8.25 MHz. External shift registers are loaded when HP_SIL# is
asserted. Shift registers can be loaded either synchronously or asynchronously. They are clocked
on the rising edge of the shift clock (HP_SIC). The serial data input pin (HP_SID) to the P64H2 is
sampled on the succeeding rising edge of the HP_SIC.
Slot Switch
The presence of logic 0 on these pins indicates that the slot is closed and can be powered on. A
logic 1 indicates that the slot should immediately be powered off. The P64H2, if enabled, auto-
powers down any slot whose switch input changes from 0 to 1, if the slot is currently powered on.
The P64H2 also powers off the LEDs for that slot.
Slot Fault
The power fault input is connected to an external device for each slot that provides the following
functions:
• Limits in-rush current to the slot so that common power rails supplying power to other slots
and system board devices do not droop or glitch as slot power is switched on.
• Detects over-current, under-voltage, and over-voltage conditions on each supply rail.
• Immediately removes power from the slot when a fault is detected so that the power supply to
other system components and slots is not adversely affected.
• Immediately isolates the slot from the bus and resets the slot so that input protection diodes on
the un-powered card do not present an excessive load on bus signals. This function is
controlled by the P64H2 when operating in one of the Parallel Modes.
• Indicates faults to the P64H2 by driving the respective slot fault pin to logic 0.
When P64H2 detects a slot fault, either on the input serial stream, or the parallel mode fault inputs,
the internal power fault latches will latch this event for each slot. The internal power fault latches
will always latch the power fault inputs, regardless of the state of SPFLE in the MCNF Register in
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memory space. If power faults are disabled via the PFE bit in the MCNF Register (memory or PCI
configuration space), the power fault latches will never see power fault events.
The HMIC Register can be programmed to reflect either the slot power fault inputs (parallel or
serial), or the output of the internal power fault latches. This is done by setting/clearing the SPFLE
bit in the MCNF Register in memory space.
The internal power fault latches can be reset by either removing power from the appropriate slot,
or by clearing the PFE bit (this clears all power fault latches).
When running in 1-slot or 2-slot parallel mode, the parallel mode power fault inputs are
immediately latched by the internal power fault latches. The outputs of these latches are then used
to asynchronously disconnect the slot power, bus enable, and clock enable, as well as assert the
slot reset. This “gating logic” remains active as long as the internal power fault latch is active.
These latches can be cleared by software initiating a slot disable cycle, thus disconnecting power
to the slot and thus clearing the power fault latch. A slot disable cycle can also be initiated by
hardware via an auto power down event caused by opening a slot switch.
Downstream cycles targeting a PCI bus segment during a hot plug device’s power fault event on
that bus could cause a system hang if the slot is not yet disabled by the hot plug controller. The hot
plug controller should initiate a slot disable cycle (via software or hardware) to disable the slot and
clear the power fault latches before any cycles are allowed to run on the PCI bus.
Note: The power fault latches can be cleared by clearing the PFE bit and this will cause the “gating
logic” to be removed. This will cause the slot power, bus enable, clock enable to all be
asynchronously enabled, and the slot reset asynchronously disabled. This is not desired behavior
and should be avoided.
PRSNT#[2:1]
These pins are provided so that software can detect the presence of a board and keep a tally of the
total amount of power used by hot plug slots. They can generate an interrupt when they change
state.
M66EN
In hot plug systems, M66EN is slot-specific. When HPx_SLOT[2:0] is not 000, the system
initially powers up at 33 MHz, and all hot plug slots are scanned by system software. If the
M66EN bits are all high for the closed slots, then software can reset the system for 66 MHz
operation, and turn on power to the cards.
PCIXCAP1/2
PCIXCAP1 and 2 represent a “serialized” version of the three-state PCIXCAP pin present on each
slot. PCIXCAP1 represents whether the PCIXCAP pin was ground or not ground (i.e., PCI-X
capable), and PCIXCAP2 represents whether the PCIXCAP pin was low (66 MHz only) or high
(133 MHz capable). The system initially powers up at 33 MHz PCI, and all hot plug slots are
scanned. If the system is capable, the bus is reset to run in the appropriate PCI-X mode.
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Input Shift Register Assignments
Three pins control the serial stream: HPSIL#, HPSIC and HPSID. The P64H2 always scans in at
least eight bytes. The assignments are shown in Table 38.
Table 38. Shift Register Data
Bit
Byte 0
Byte 1
Byte 2
Byte 3
0
Slot A switch
(0 = closed)
Slot A fault#
(0 = fault)
Slot A PRSNT2#
Slot A PRSNT1#
1
2
3
4
5
6
7
Slot B switch
Slot C switch
Slot B fault#
Slot C fault#
Slot B PRSNT2#
Slot C PRSNT2#
Slot D PRSNT2#
Slot E PRSNT2#
Slot F PRSNT2#
Stutter (not used)
Stutter (not used)
Slot B PRSNT1#
Slot C PRSNT1#
Slot D PRSNT1#
Slot E PRSNT1#
Slot F PRSNT1#
Stutter (not used)
Stutter (not used)
Slot D switch
Slot D fault#
Slot E switch
Slot E fault#
Slot F switch
Slot F fault#
Stutter (not used)
Stutter (not used)
Stutter (not used)
Stutter (not used)
Bit
Byte 4
Byte 5
Byte 6
Byte 7
0
1
2
3
4
5
6
7
Slot A M66EN
Slot B M66EN
Slot C M66EN
Slot D M66EN
Slot E M66EN
Slot F M66EN
Stutter (not used)
Stutter (not used)
Slot A PCIXCAP1
Slot B PCIXCAP1
Slot C PCIXCAP1
Slot D PCIXCAP1
Slot E PCIXCAP1
Slot F PCIXCAP1
Stutter (not used)
Stutter (not used)
Slot A PCIXCAP2
Slot B PCIXCAP2
Slot C PCIXCAP2
Slot D PCIXCAP2
Slot E PCIXCAP2
Slot F PCIXCAP2
Stutter (not used)
Stutter (not used)
User Defined Input
User Defined Input
User Defined Input
User Defined Input
User Defined Input
User Defined Input
Stutter (not used)
Stutter (not used)
4.3.1.5
Serial Output Stream
Reading and writing the internal serial output control registers does not automatically initiate
output shifting. The shift output process is initiated by writing the SOGO bit in the MCNF
Register in memory space to 1. When this bit is set, it is not reset until the external shift registers
and latches are in their proper state. If the SOGO bit is written to 0 or 1 while the SOGO bit is set,
the write is ignored.
Although blinking of LEDs requires the use of the serial output logic, the operation of the SOGO
bit is unaffected by this. If an update for a blink was already in progress when the SOGO bit was
written, it may increase the amount of time that the SOGO bit remains set. The SOGO bit state
reflects only the state of software-originated shift output events and not those triggered by
hardware. Note that the OOB bit will reflect the state of the on/off state machine which controls
shift out events, regardless of whether they are hardware or software initiated events.
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The on/off state machine executes a shift for any of the following reasons:
• The SOGO bit was set by software (even if no slot enable bits have changed state).
• A Hot plug slot switch has opened (provided that the respective slot is on).
• At least one LED has been programmed to blink and the blink timer has expired.
• A PCI configuration space write to byte offset 43h after RSTIN# deassertion. (The system
ROM firmware usually does this early, after or while configuring the MCNF Register in
configuration space).
The LED control outputs are updated with a single pass through the output shift registers. The
PWREN, RESET#, CLKEN#, and BUSEN# bits, however, require multiple passes. The shift
sequence changes depending on which bits have been set or reset in the Slot Enable Register when
the SOGO bit is set:
• No Slot Enable bits have changed: The serial outputs are updated in a single pass.
• At least one Slot Enable bit has changed from 0 to 1 when SOGO is set: Executes a slot
enable sequence.
• At least one Slot Enable bit has changed from 1 to 0: Executes a slot disable sequence.
• Some Slot Enable bits have changed from 0 to 1 and some have changed from 1 to 0:
Executes two sequences – first a disable sequence then an enable sequence.
The SOGO bit can be configured to generate an interrupt when it changes from 1 to 0 through the
SOIE bit in the MCNF Register.
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Shift Register Assignments
GPO[7:0] are shifted out before the reset enables. This is done to support a system that does not
need the GPOA outputs. For a system using less than six slots, stutter logic can be utilized to
reduce the number of output shift registers and latches. Serial mode output shifting is shown in
Table 39.
Table 39. Serial Mode Output Shift-Out SR Bit Order
SR Bit
Function
SR Bit
Function
SR Bit
Function
0
1
gpo7
gpo6
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
ambled 1
grnled 2
ambled 2
grnled 3
ambled 3
grnled 4
ambled 4
grnled 5
ambled 5
grnled 6
ambled 6
busen 1
busen 2
busen 3
busen 4
30
31
32
33
34
35
36
37
38
39
40
41
42
43
busen 5
busen 6
clken 1
clken 2
clken 3
clken 4
clken 5
clken 6
pwren 1
pwren 2
pwren 3
pwren 4
pwren 5
pwren 6
2
gpo5
3
gpo4
4
gpo3
5
gpo2
6
gpo1
7
gpo0
8
reset# 1
reset# 2
reset# 3
reset# 4
reset# 5
Reset# 6
grnled 1
9
10
11
12
13
14
LEDs
Each slot has a green and amber LED for communicating slot status to the user. Each LED has 4
states (ON, OFF, BLINK PHASE A, and BLINK PHASE B) controlled by the LED Control
Register (LEDC).
A single timer controls blinking for all LEDs and is hardwired to 1 Hz at a 50% duty cycle,
derived from the PCI clock frequency. Phase A is on for the first half of each one-second period
and phase B is on for the second half.
When a switch for a slot indicates that the slot has been opened, both LEDs are turned off by the
P64H2. The LEDs can later be programmed by software to turn on or blink the LEDs, whether or
not the slot is open. It is the responsibility of software to insure that the LEDs never indicate that a
slot is powered down when the slot has power.
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GPO
General-purpose outputs are used for non-slot specific system functions. These outputs are part of
the serial output chain but are not affected by the number of slots detected on HP_SLOT[2:0].
4.3.1.6
Power Sequencing
Each slot uses 4 control signals to enable and disable PCI-X cards: PWREN, CLKEN#, BUSEN#
and RESET#. Power sequencing can be performed in one of two ways, as selected by the CBLE
(Connect Bus Last Enable) bit in the MCNF Register in PCI configuration space. If CBLE is
cleared, the PCI bus is connected before the slot reset is deasserted. If CBLE is set, the PCI bus is
connected after the slot reset has been deasserted.
Any slot can be individually powered on by setting the appropriate bit of the Slot Power Enable
register. These bits affect only the state of the PWREN pin for that slot; they do not affect the
clock, connection to the bus, or slot reset.
Power Up (CBF Mode)
When a slot is to be turned on in CBF mode, the outputs are updated in the following sequence:
2. Assert PWREN, but keep BUSEN# and CLKEN# deasserted and RESET# asserted. Shift the
new pattern to the shift registers.
3. Clock the parallel latch HP_SOL. The new values for LEDs are clocked out at this point as
well.
4. With PWREN asserted, assert CLKEN# bit but leave BUSEN# deasserted and RESET#
asserted. Shift the new pattern to the shift registers.
5. Wait for 500 ms for power to stabilize.
6. Arbitrate for an idle bus, and clock the parallel latch HP_SOL.
7. With PWREN and CLKEN# asserted, assert BUSEN# to connect the bus, and deassert
RESET# Shift the new pattern to the shift registers.
8. Wait for 500 ms for expansion card clocks to stabilize.
9. Arbitrate for an idle bus time, and clock the parallel latch HP_SOL. However, since
HP_SOLR is not clocked, the RESET# pin remains asserted to the device.
10. Wait for 330 ns.
11. Clock the parallel latch HP_SOLR, to negate reset.
Table 40. Power Up Timings (CBF Mode)
Timing Event
Minimum1
Maximum
Units
PWREN Assertion to CLKEN# Assertion
CLKEN# Assertion to BUSEN# Assertion
BUSEN# Assertion to RESET# Deassertion
500
500
330
505
505
330
ms
ms
ns
NOTES:
1. Arbitration latency affects the minimum time.
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Power Down (CBF Mode)
When a slot is to be turned off in the CBF mode, the outputs are updated in the following
sequence:
1. Assert RESET# and negate the BUSEN# but leave CLKEN# asserted and PWREN asserted.
Shift the new pattern to the shift registers.
2. Arbitrate for an idle bus and clock the parallel latch HP_SOLR, which asserts RESET# to the
card. Since HP_SOL is not clocked, BUSEN# stays asserted.
3. Wait 330 ns and clock the parallel latch HP_SOL to assert BUSEN#.
4. With RESET# asserted and BUSEN# deasserted, deassert CLKEN# but leave PWREN
asserted. Shift the new pattern to the shift registers.
5. Arbitrate for an idle bus, and clock the parallel latch HP_SOL.
6. With RESET# asserted and BUSEN# and CLKEN# deasserted, deassert PWREN. Shift the
new pattern to the shift registers.
7. Clock the parallel latch HP_SOL.
Table 41. Power Down Timings (CBF Mode)
Timing Event
Minimum1
Maximum
Units
RESET# Assertion to BUSEN# Deassertion
BUSEN# De-assertion to CLKEN# Deassertion
CLKEN# De-assertion to PWEREN Deassertion
330
330
ns
us
us
5.468
5.438
14.445
14.415
NOTES:
1. Arbitration latency affects the minimum time.
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Power Up (CBL Mode)
When a slot is to be turned on in CBL mode (power-up default), the outputs are updated in the
following sequence:
1. Assert PWREN, but keep BUSEN# and CLKEN# deasserted and RESET# asserted. Shift the
new pattern to the shift registers.
2. Clock the parallel latch HP_SOL. The new values for LEDs are clocked out at this point as
well.
3. With PWREN asserted, assert CLKEN# bit but leave BUSEN# deasserted and RESET#
asserted. Shift the new pattern to the shift registers.
4. Wait for 500 ms for power to stabilize.
5. Arbitrate for an idle bus, and clock the parallel latch HP_SOL.
6. With PWREN and CLKEN# asserted, assert BUSEN# to connect the bus, and deassert
RESET# Shift the new pattern to the shift registers.
7. Wait for 500 ms for expansion card clocks to stabilize.
8. Clock the parallel latch HP_SOLR, to negate reset. However, since HP_SOL is not clocked,
the BUSEN# pin remains deasserted to the device.
9. Wait for 500 ms.
10. Arbitrate for an idle bus time, and clock the parallel latch HP_SOL.
Table 42. Power Up Timings (CBL Mode)
Timing Event
Minimum1
Maximum
Units
PWREN Assertion to CLKEN# Assertion
CLKEN# Assertion to RESET# Deassertion
RESET# De-assertion to BUSEN# Assertion
500
500
500
505
505
505
ms
ms
ms
NOTES:
1. Arbitration latency affects the minimum time.
Power Down (CBL Mode)
When a slot is to be turned off in CBL mode (power-up default), the outputs are updated in the
following sequence:
1. Assert RESET# and negate the BUSEN# but leave CLKEN# asserted and PWREN asserted.
Shift the new pattern to the shift registers.
2. Arbitrate for an idle bus and clock the parallel latch HP_SOL, which asserts BUSEN# to the
card. Since HP_SOLR is not clocked, RESET# stays asserted.
3. Wait 330 ns and clock the parallel latch HP_SOLR to assert RESET#.
4. With RESET# asserted and BUSEN# deasserted, deassert CLKEN# but leave PWREN
asserted. Shift the new pattern to the shift registers.
5. Arbitrate for an idle bus and clock the parallel latch HP_SOL.
6. With RESET# asserted and BUSEN# and CLKEN# deasserted, deassert PWREN. Shift the
new pattern to the shift registers.
7. Clock the parallel latch HP_SOL.
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Table 43. Power Down Timings (CBL Mode)
Timing Event
Minimum1
Maximum
Units
BUSEN# Deassertion to RESET# Assertion
RESET# Assertion to CLKEN# De-assertion
CLKEN# Deassertion to PWREN De-assertion
330
330
ns
us
us
5.468
5.438
14.445
14.415
NOTE: Arbitration latency affects the minimum time.
4.3.1.7
4.3.1.8
Arbitration
The hot plug controller requests a hold from the P64H2 arbiter at various stages of enabling or
disabling slots. This is performed to prevent glitches that might occur while switching bus signals
from affecting the rest of the system. When a request to the P64H2 arbiter occurs from the hot
plug function, the P64H2 arbitrates to hot plug at the next convenient opportunity and suppresses
grants to external masters. When the bus is idle, hot plug is granted and it performs its operations.
Power-on and Reset Initialization
All registers in the P64H2 hot plug controller are reset by the primary bus reset pin (RSTIN#). The
secondary bus reset will reset most of the controller’s registers, except for the few listed in
Table 44.
Table 44. Registers Not Reset with a Secondary Bus Reset
Memory Registers
General Purpose Timer Register (offset 00h)
Slot Enable Register (offset 01h)
LED Control Register (offset 04h)
HMIC Register (offset 08h)
HMIR Register (offset 0Ch)
SIR Register (offset 10h)
GPO Register (offset 13h)
HMIN Register (offset 14h)
Slot Power Register (offset 2Dh)
Configuration Registers
Subsystem ID Register (offset 2Ch)
MCNF Register (offset 42h); CBL control bit (bit 1).
On a RSTIN# assertion, the slot-specific output controls are set to the following states:
• RESET# is asserted.
• BUSEN# is deasserted (disconnected from the bus).
• CLKEN# is deasserted (PCI clock disconnected from the bus).
• PWREN is deasserted (slot power is removed).
• All green and amber LED outputs are set to OFF.
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4.3.1.9
PCI Card Initialization
The hot plug controller and the system board must guarantee that PCI-X cards are properly
initialized when brought out of reset. PCI cards may have to sample the REQ64# line when
PCIRST# is deasserted to determine if they are on a 64-bit data bus or not, as well as the M66EN
pin to determine the speed of the PCI bus. PCI-X cards are additionally required to sample the
DEVSEL#, STOP#, and TRDY# pins to determine the PCI-X mode of the bus. The state of all
these signals together is called the initialization pattern when PCIRST# is deasserted.
When the hot plug controller is operating in CBF mode, there is no additional hardware required
to guarantee that the PCI-X cards will correctly sample the initialization pattern. The P64H2 will
begin driving the initialization pattern when the HPx_SOL signal goes low during the bus enable
step of the CBF power up sequence. P64H2 will guarantee that this pattern is held active through
the rising edge of HPx_SOLR, which will deassert PCIRST# to the slot. The PCI-X card will see
the pattern driven on its pins 330ns before the rising edge of the card’s PCIRST#, which is the time
between the slot’s bus enable and reset deassertion.
When the hot plug controller is operating in CBL mode, the board designer must add additional
logic to guarantee that the PCI-X cards will see the proper initialization pattern on the rising edge
of PCIRST#, and that the pattern meets the timings specified in the PCI Local Bus Specification,
Revision 2.2, and the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0.
4.3.1.10
Changing PCI Frequency/Modes
When HPx_SLOT[2:0] for a PCI interface is not 000, the PCI bus is expected to power up
operating at 33 MHz PCI. If software determines that the inserted slots are PCI-X capable, or PCI
capable at 66 MHz, the PCI bus may be reset to operate in the new mode.
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4.3.2
Pin Multiplexing in Single and Dual Slot Modes
When operating in a single slot or dual-slot environment, it is required that the controller be in the
Parallel Mode of operation, thus avoiding placement of de-serialization glue. In a single slot
environment, it is not necessary to carry the logic required to electrically isolate a slot. The mode
of operation for an interface is based on sampling of the HPx_SLOT[2:0] pins on PWROK.
Table 45 lists the modes.
Table 45. Hot Plug Mode Settings
HPx_SLOT[2:0]
Hot Plug Mode
000
001
010
011
100
101
110
111
Hot Plug Disabled
1-slot (no glue)
2-slot (parallel)
3-slot (serial)
4-slot (serial)
5-slot (serial)
6-slot (serial)
Reserved
When in one of the parallel modes of operation, the hot plug controller directly controls the
isolation logic and hot plug I/Os through parallel pins instead of a serial stream. In Table 46 the
‘signal’ column refers to the name of the pin when in dual slot mode, and the ‘bus A’ and ‘bus B’
columns represent the P64H2 pins that are to be used for these modes. Note that when the
controller is operating in 1-slot mode parallel mode, the output pins for the second slot will be kept
in their reset state. These output pins are HPx_SOR#, HPx_SIC, HPx_SID, PxGNT[4:3], and
HPx_SOLR ("x" is for either bus "A" or "B").
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Table 46. Hot Plug Mode Signals
Multiplexed With
Multiplexed With
Signal
Type
Signal
Type
Bus A
Bus B
Bus A
Bus B
HXSWITCHA
HXFAULTA#
HXPRSNT2A#
HXPRSNT1A#
HXM66ENA
I
I
PAIRQ15
PAIRQ14
PBIRQ15
PBIRQ14
HXSWITCHB
HXFAULTB#
HXPRSNT2B#
HXPRSNT1B#
HXM66ENB
I
I
PAIRQ10
PAIRQ9
PBIRQ10
PBIRQ9
I
PAIRQ13
PBIRQ13
I
PAIRQ8
PBIRQ8
I
PAIRQ12
PBIRQ12
I
PAREQ5
PBREQ5
I
PAIRQ11
PBIRQ11
I
PAREQ4
PBREQ4
HXPCIXCAP1A
HXPCIXCAP2A
HXRESETA#
HXGNLEDA
I
HPA_SLOT21
HPA_SLOT11
PAGNT53
HPB_SLOT21
HPB_SLOT11
PBGNT53
HXPCIXCAP1B
HXPCIXCAP2B
HXRESETB#
HXGNLEDB
I
PAREQ3
PBREQ3
I
I
HPA_SLOT01
HPA_SOR#3
HPA_SIC3
HPA_SID2
PAGNT43
PAGNT33
HPA_SOLR3
HPB_SLOT01
HPB_SOR#3
HPB_SIC3
HPB_SID2
PBGNT43
PBGNT33
HPB_SOLR3
O
O
O
O
O
O
O
O
O
O
O
O
HPA_SOC3
HPA_SOL3
HPA_SORR#3
HPA_SIL#3
HPA_SOD3
HPB_SOC3
HPB_SOL3
HPB_SORR#3
HPB_SIL#3
HPB_SOD3
HXAMLEDA
HXBUSENA#
HXCLKENA#
HXPWRENA
HXAMLEDB
HXBUSENB#
HXCLKENB#
HXPWRENB
NOTES:
1. HPx_SLOT[N] are pull-ups/pull-downs. When in two slot parallel mode, the external logic that decodes
the three-state value of PCIXCAP from the card must actively drive these signals to either logic 1 or
logic 0 to overcome the value of the pull-up/pull-down, must be tri-stated during reset and while the card
is not connected to avoid damaging the slot count value.
2. HPx_SID must be pulled down on the system board when configuring the P64H2 for 2-slot mode so that
the LED for slot B on busses A and B will remain off during reset.
3. The P64H2 must drive the following signals to the following states in case the system is set up for 2-slot
mode so that LEDs are in the appropriate state (off) and the Q-switches remain disconnected. Note that
the placement of the signals should be such that the value driven by the P64H2 in 2-slot mode is the
same value it would have driven if in serial mode.
Table 47. Hot Plug Mode Reset Values
Signals
Reset Value
PxGNT[5::3]
HPx_SOC
HPx_SIC
011
0
0
HPx_SOL
0
HPx_SOLR
HPx_SOD
HPx_SORR#
HPx_SOR#
HPx_SIL#
0
0
1
0
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4.3.3
Single Slot Mode PCI Bus Effects
When in single slot mode, the PCI bus operates differently when no cards are plugged into the
system. This is because in a single-slot environment, no isolation logic (Q-switches) is on the
board. This section lists those differences.
4.3.3.1
Driving Bus To Ground When PCI Card is Disconnected
When in single slot mode, all PCI signals are to be driven to ground when the PCI card is
disconnected. The signals that must be driven to ground are the following:
• PxAD[63:0], PxC/BE[7:0]#, PxPAR, PxPAR64, PxREQ64#, PxACK64#
• PxFRAME#, PxIRDY#, PxTRDY#, PxSTOP#, PxDEVSEL#, PxLOCK#
• PxGNT[5:0]#
• PxREQ[5:0]#
• PxPERR#, PxSERR#
• PxPCLKO[5:0] (Only driven to ground if enabled through the bridge – otherwise these
outputs remain high. PxPCLKO6 is not driven to ground because it is the connected back to
PxPCLKI).
• HxRESETA# (Slot specific reset from parallel hot plug control signal interface).
• PxIRQ[7:0]
These signals will be driven back to their normal PCI levels at various times in the clock
connection process. When a card is reconnected to the bus, it follows the following algorithm:
• Power is applied to the card. This does not affect any of the PCI signals that are now being
driven to ground.
• After a variable period of time, the clock is connected to the card. When this occurs,
PxPCLKO[5:0] will no longer be driven to ground, but will toggle normally (assuming that
BIOS has not disabled that particular PxPCLKO pin). In hot plug terms, this is the equivalent
of the “CLKEN#” signal.
• After another variable period of time, the bus is connected to the card. When this occurs, The
remaining signals listed above which were driven to ground will be driven to new signal
values, except for the slot reset, which will continue to be driven to ground. The new signal
values are listed below:
PxAD[63:0], PxC/BE[7:0]#, PxPAR, PxPAR64: These signals are driven to some value
(low or high) depending on internal state. (PAR and PAR64 are driven one PCI-X clock
after the other lines are driven.)
PxREQ64#: This signal is driven low to indicate to card that it is connected to a 64-bit
wide data bus.
PxFRAME#, PxIRDY#, PxLOCK#, PxREQ[2:0]#, PxGNT[2:0]#, PxPERR#, PxSERR#,
PxACK64#: These signals are driven high for one PCI-X clock, then tri-stated.
PxTRDY#, PxSTOP#, PxDEVSEL#: In PCI mode, these signals are driven high for one
PCI clock, then tri-stated. In PCI-X mode, these signals are driven to the PCI-X
initialization pattern associated with the current PCI-X bus speed.
PxIRQ[7:0]: Tri-states.
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In hot plug terms, this is the equivalent of the “BUSEN#” signal.
• After a final variable period of time, the card is taken out of reset. When this occurs, the slot
reset pin (HxRESETA#) will be continuously driven high. In hot plug terms, this is the
equivalent of the “PCIRST#” signal to the PCI-X card.
Note that when the controller is operating in single slot mode, there is no provision to run in CBL
(connect bus last) mode. The controller must be programmed to run in connect bus first mode
(CBF mode).
4.3.3.2
Aborting Outbound PCI Cycles When Card is Disconnected
When a PCI-X card is not present in a multi-slot system, it has been isolated. This means that all
cycles destined for that particular card (peer traffic or other processor-based traffic) will master
abort on the PCI bus because no PxDEVSEL# will be driven. To be consistent in a single-slot
system, the P64H2 must master abort cycles that are destined for that PCI bus when the card is
disconnected.
Therefore, the PCI interface / buffer interface will have to internally master abort all outbound
transactions destined for that PCI bus until the PCI-X card has been fully powered up, connected
to the bus and out of reset. This will be seen as a primary bus master abort in the system, and this
will not be reflected in the Received Master Abort (RMA) bit in the bridge configuration registers.
4.3.3.3
Special Note on M66EN in Single Slot Mode
In single slot mode, the P64H2 never drives the PxM66EN pin. This is because there is no
isolation logic on PxM66EN, and if the P64H2 drove PxM66EN to ground to indicate the bus was
operating in 33 MHz mode, it could not sample the PxM66EN capabilities from the card to
determine whether the card was 66 MHz capable.
4.3.4
Generating SCI Instead of Interrupt
If the hot plug controller is programmed to generate an SCI instead of an interrupt by setting bit 14
of the ABAR Register, all sources of interrupt will be instead routed to a new SCI pin. This pin is
multiplexed onto PAIRQ7. All logic functions the same as for interrupts – if the interrupt source is
masked, no SCI is generated.
4.3.5
Disabling the Hot Plug Controller
If the HPx_SLOT[2:0] pins are strapped to 000 or 111 when PWROK goes high, the hot plug
controller will be disabled. In this mode, all hot plug output pins (serial mode pins) are driven to 0.
Also, the hot plug controller will not accept configuration or memory read/write transactions. The
controller will essentially "disappear" from the system.
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4.4
Addressing
4.4.1
I/O Window Addressing
This section describes the I/O window that can be set up in the bridge. (Section 4.4.3 outlines the
I/O cycles in the VGA range). The register bits listed below also modify the response by the
P64H2 to I/O transactions:
• I/O Base and Limit Address Registers
• I/O Enable bit in the PCI Primary Device Command (PD_CMD) Register
• Master Enable bit in the PCI Primary Device Command (PD_CMD) Register
• Enable 1 KB granularity in the P64H2 Configuration Register
To enable outbound I/O transactions, the I/O Enable bit (bit 0) must be set in the PD_CMD
Register in the P64H2 configuration space (offset 04–05h). If the I/O Enable bit is not set, all I/O
transactions initiated on the hub interface will receive a master abort completion. No inbound I/O
transactions may cross the bridge and are therefore master aborted.
The P64H2 implements one set of I/O Base and Limit Address Registers in configuration space
that define an I/O address range for the bridge. Hub interface I/O transactions with addresses that
fall inside the range defined by the I/O Base and Limit Address Registers are forwarded to PCI,
and PCI I/O transactions with addresses that fall outside this range are master aborted.
Setting the base address to a value greater than that of the limit address turns off the I/O range.
When the I/O range is turned off, no I/O transactions are forwarded to PCI even if the I/O enable
bit is set. The I/O range has a minimum granularity of 4 KB and is aligned on a 4 KB boundary.
The maximum I/O range is 64 KB. This range may be lowered to 1 KB granularity by setting the
EN1K bit in the P64H2 Configuration Register at offset 40h.
The base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at
address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The
bottom 4 bits are read only; returning value 0h to indicate that the P64H2 supports 16-bit I/O
addressing. Bits [1:0] of the base address are assumed to be 0,which naturally aligns the base
address to a 4 KB boundary. The I/O base upper 16 bits register at offset 30h is reserved. Reset
initializes the value of the I/O base address to 0000h.
The I/O limit register consists of an 8-bit field at offset 1Dh and a16-bit field at offset 32h. The top
4 bits of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits are read only,
returning value 0h to indicate that 16-bit I/O addressing is supported. Bits [11:0] of the limit
address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4 KB I/O
address block. The 16 bits contained in the I/O limit upper 16 bits register at offset 32h are
reserved. Reset initializes the value of the I/O limit address to 0FFFh.
Note: If the EN1K bit is set in the P64H2 Configuration Register, the Base and Limit Registers are
changed such that the top 6 bits of the 8-bit field define bits [15:10] of the I/O base/limit address,
and the bottom 2 bits read only as 0h to indicate support for 16-bit I/O addressing. Bits [9:0] are
assumed to be 0 (for the base register) and 1 (for the limit register), which naturally aligns the
address to a 1 KB boundary.
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4.4.2
Memory Window Addressing
This section describes the memory windows that can be set up in the bridge. (Section outlines
memory cycles in the VGA range. The register bits listed below also modify the P64H2 response
to memory transactions:
• Memory-mapped I/O Base and Limit Registers
• Prefetchable Memory Base and Limit Registers
• Prefetchable Memory Base and Limit Upper 32 bits Register
• Memory Enable bit in the PCI Primary Device Command Register
• Master Enable bit in the PCI Primary Device Command Register
To enable outbound memory transactions, the Memory Space Enable bit (bit 1) in the PD_CMD
Register must be set (offset 04–05h). To enable inbound memory transactions, the Master Enable
bit (bit 2) in the PD_CMD Register must be set (offset 04–05h). The P64H2 will not prefetch data
from PCI devices. The P64H2 supports 64 bits of addressing (DAC cycles) on both interfaces.
4.4.2.1
Memory Base and Limit Address Registers
The Memory Base Address and Memory Limit Address Registers define an address range that the
P64H2 uses to determine when to forward memory commands. The P64H2 forwards a memory
transaction from the hub interface to PCI if the address falls within the range, and forwards it from
PCI to the hub interface (or the peer bridge) if the address is outside the range (provided that they
do not fall into the prefetchable memory range (see Section 4.4.2.2). This memory range supports
32-bit addressing only, (addresses 4 GB) and supports 1 MB granularity and alignment.
This range is defined by a 16-bit base address register at offset 20h in configuration space and a
16-bit limit address register at offset 22h. The top 12 bits of each of these registers correspond to
bits [31:20] of the memory address. The low 4 bits are hardwired to GND. The low 20 bits of the
base address are assumed to be all 0s, which results in a natural alignment to a 1 MB boundary.
The low 20 bits of the limit address are assumed to be all 1s, which results in an alignment to the
top of a 1 MB block.
Note: Setting the base to a value greater than that of the limit turns off the memory range.
4.4.2.2
Prefetchable Memory Base and Limit Address Registers,
Upper 32-bit Registers
The prefetchable memory base and address registers, along with their upper 32-bit counterparts,
define an additional address range that the P64H2 uses to forward accesses. The P64H2 forwards a
memory transaction from the hub interface to PCI if the address falls within the range, and
forwards transactions from PCI to the hub interface (or the peer bridge) if the address is outside
the range and do not fall into the regular memory range (see Section 4.4.2.1). This memory range
supports 64-bit addressing, and supports 1 MB granularity and alignment.
This lower 32-bits of the range are defined by a 16-bit base register at offset 24h in configuration
space and a 16-bit limit register at offset 28h. The top 12 bits of each of these registers correspond
to bits [31:20] of the memory address. The low 4 bits are hardwired to VCC, indicating 64-bit
address support. The low 20 bits of the base address are assumed to be all 0s, which results in a
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natural alignment to a 1 MB boundary. The low 20 bits of the limit address are assumed to be all
1s, which results in an alignment to the top of a 1 MB block.
The upper 32-bits of the range are defined by a 32-bit base register at offset 28h in configuration
space, and a 32-bit limit register at offset 2Ch.
Note: Setting the entire base (with upper 32-bits) to a value greater than that of the limit turns off the
memory range.
4.4.3
VGA Addressing
When a VGA-compatible device exists behind a P64H2 bridge, the VGA Enable bit (bit 3) in the
Bridge Control Register must be set (offset 3E–3Fh). If this bit is set, the P64H2 forwards all
transactions addressing the VGA frame buffer memory and VGA I/O registers from the hub
interface to PCI, regardless of the values of the P64H2 base and limit address registers. The
P64H2 will not forward VGA frame buffer memory accesses to the hub interface regardless of the
values of the memory address ranges. However, the I/O Enable and Memory Enable bits in the
PD_CMD Register must still be set. When the bit is cleared, the P64H2 forwards transactions
addressing the VGA frame buffer memory and VGA I/O registers from the hub interface to PCI if
the defined memory address ranges enable forwarding. All accesses to the VGA frame buffer
memory are forwarded from PCI to the hub interface if the defined memory address ranges enable
forwarding. However, the master enable bit must still be set. The VGA I/O addresses are never
forwarded to the hub interface.
The VGA frame buffer consists of the following memory address range:
000A_0000h–00B_FFFFh
The VGA I/O addresses consist of the I/O addresses 3B0h–3BBh and 3C0h–3DFh. These I/O
addresses are aliased every 1 KB throughout the first 64 KB of I/O space. This means that address
bits [9:0] (3B0h–3BBh and 3C0h–3DFh) are decoded, [15:10] are not decoded and can be any
value, and address bits [31:16] must be all 0s.
Note: If software sets the VGA enable bit in one bridge, the ISA enable bit must be set in the other
bridge.
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4.4.4
Configuration Addressing
Figure 4 and Table 48 show how the P64H2 appears to configuration software.
Figure 4. Intel P64H2 Appearance to Software
Hub Interface
Logical PCI Bus
P-2-P
Bridge A
P-2-P
Bridge B
Hot Plug
I/Ox APIC
Hot Plug
I/Ox APIC
Physical PCI Bus
Physical PCI Bus
P64H2_SW_view
Table 48. PCI Functions/Devices Table
PCI
Device
PCI
Function
Function
Hub Interface ID
PCI Bus
0 (Hub
Interface)
PCI Bus A
PCI Bus B
0
1
31 (1Fh)
29 (1Dh)
30 (1Eh)
28 (1Ch)
0
0
0
0
0 (Hub
Interface)
0 (Hub
Interface)
I/OxAPIC A
I/OxAPIC B
0 (master writes only)
1 (master writes only)
0 (Hub
Interface)
Hot Plug Controller A
Hot Plug Controller B
None (no master cycles)
None (no master cycles)
1 (PCI A)
1 (PCI B)
31 (1Fh)
31 (1Fh)
0
0
Note that the SMBus controller does not appear to software. This function does not have a space
visible to software. The devices are organized such that the bridge and APIC are 1 bit apart in their
device number.
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4.5
Transaction Ordering
4.5.1
Comparison of Rules vs A PCI–PCI Bridge
When a PCI segment is in PCI (PCI-X) mode, the P64H2 follows the producer-consumer model of
a PCI – PCI bridge. Table 49 is taken from Appendix E of the PCI Local Bus Specification,
Revision 2.2 for PCI, and Section 8.4.4 of the PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0. The “bolded” entries represent differences from that table, and an
explanation of the differences.
Table 49. Ordering Rules for a PCI-PCI Bridge
Delayed
(Split) Read
Request
Delayed
(Split) Write
RequestD
Delayed
(Split) Read
Completion
Delayed (Split)
Write
Posted
Write
Row pass Col?
CompletionD
Posted Write
No
No
Yes
Yes
Yes
Yes
Delayed (Split)
Read Request
YesA
NoC
NoC
YesA
NoC
NoC
NoC
NoD
NoC
NoC
YesC
YesC
YesC
YesC
YesB
NoD
NoC
NoC
YesC
YesC
YesC
YesC
Delayed (Split)
Write Request
No
No
Delayed (Split)
Read Completion
Yes
Yes
Yes
Yes
Delayed (Split)
Write Completion
NoC
Table Legend:
A. Subsequent requests only (prefetches). All inbound initial requests are in order.
B. Multiple non-posted requests from MCH must complete in order.
C. In a bridge these are allowed to be yes/no.
D. In a bridge these are allowed to be yes/no. The P64H2 will not accept inbound write
requests that are not posted (I/O writes, configuration writes).
4.5.2
Ordering Relationships
Ordering relationships are established for the following classes of transactions crossing the
P64H2:
• The P64H2 does not combine separate write transactions into a single write transaction.
• The P64H2 does not merge bytes on separate write transactions to the same DWord address.
• The P64H2 does not collapse sequential write transactions to the same address into a single
write transaction – the PCI Local Bus Specification, Revision 2.0 does not permit this
operation.
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4.5.3
4.5.4
Hub Interface Fence Special Cycle
When the P64H2 performs a memory write transaction from one PCI bus to its peer PCI bus, the
MCH component needs to be notified. This is because the MCH has separate pipes for requests
originating on each bus (inbound transactions are routed to one of two pipes, based upon the
bridge’s Hub ID). For almost all cases, this is acceptable, as the traffic patterns on each PCI bus
are unrelated. In a peer-to-peer scenario, this is not valid.
Master Abort / Target Abort Completions on Hub Interface
Though the P64H2’s primary bus is the hub interface, from a register and software perspective, the
hub interface is a PCI-X bus and the P64H2 is a PCI-X bridge that supports a secondary bus
configured as either PCI or PCI-X.
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0 Section 8.7.1.5 modified
the behavior of a bridge from that specified in the PCI-to-PCI Bridge Architecture Specification,
Revision 1.1 regarding returning completions on the primary bus when the secondary bus
transaction terminates in either a master abort or target abort. In general, the PCI-X Addendum to
the PCI Local Bus Specification, Revision 1.0 does not honor the Master Abort Mode bit for
cycles requiring completions, and returns to the primary bus the termination that occurred on the
secondary bus without any translation.
4.5.4.1
Behavior of Hub Interface Initiated Cycles to PCI/PCI-X Receiving
Immediate Terminations
The behavior described for completion required cycles is independent of the setting of the Master
Abort Mode bit, and is independent of whether the cycle is exclusive (locked) or not. The P64H2
returns all 1s on data bytes for a read completion that terminates in either Master Abort or Target
Abort.
Table 50. Immediate Terminations of Completion Required Cycles to PCI/PCI-X
PCI/PCI-X Termination
Hub Interface Completion
Successful
Status Register Bits Set
Successful
• Master Data Parity Error (Sec) 1
• Received Master Abort (Sec)
• Received Target Abort (Sec)
• Signaled Target Abort (Pri)
• Master Data Parity Error (Sec) 1
Master Abort
Master Abort
Target Abort
Target Abort
NOTES:
1. The Master Data Parity Error bit is set only if a data parity error was encountered on the PCI/PCI-X bus.
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Table 51. Immediate Terminations of Posted Write Cycles to PCI/PCI-X
PCI/PCI-X Termination
MAM Bit
Hub Interface Cycle
Status Register Bits Set
• None
Successful
N/A
None
• Received Master Abort (Sec)
• Signaled System Error (Pri) 1
• Received Master Abort (Sec)
• Received Target Abort (Sec)
• Signaled System Error (Pri) 1
Master Abort
Master Abort
Target Abort
1
0
DO_SERR 1
None
N/A
DO_SERR 1
NOTES:
1. The SO_SERR cycle and setting of the Signaled System Error bit only occur if the SERR# Enabled in
the PCI Primary Device Command Register is set.
4.5.4.2
Behavior of Hub Interface Initiated Cycles PCI-X Receiving Split
Terminations
The behavior described in Table 52 is independent of the Master Abort Mode bit and whether or
not the cycle is exclusive (locked) or not. P64H2 will return all 1s on all data bytes for a read
completion that terminates in either Master Abort or Target Abort on the hub interface. Note that
when a target or master abort is returned on the hub interface, the attached PCI/PCI-X bus is not
locked. This is of special importance to the completion messages of “data parity error”, “byte
count out of range”, “write data parity error”, “device specific”, and reserved/illegal codes. P64H2
must not lock its bus on these errors, even though they are not explicitly master or target aborts on
the PCI-X interface.
Table 52. Split Terminations of Completion Required Cycles to PCI-X
Message
Hub Interface
PCI-X Split Termination
Completion
Status Register Bits Set
Class
Index
• Master Data Parity Error
(Sec), if encountered
Successful
0
1
00h
00h
Successful
Master Abort
Master Abort
• Received Master Abort (Sec)
• Received Target Abort (Sec)
• Signaled Target Abort (Pri)
Target Abort
1
01h
Target Abort
• Master Data Parity Error
(Sec)
Write Data Parity Error
Byte Count Out Of Range
Write Data Parity Error
1
2
2
02h
00h
01h
8Xh
Target Abort
Target Abort
Target Abort
• Signaled Target Abort (Pri)
• Signaled Target Abort (Pri)
• Master Data Parity Error
(Sec)
• Signaled Target Abort (Pri)
• Signaled Target Abort (Pri)
• Signaled Target Abort (Pri)
Device Specific
Reserved/Illegal
2
Target Abort
Target Abort
Others
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4.5.4.3
Hub Interface Action on Immediate Responses to PCI-X Split
Completions
Table 53 indicates what the P64H2 does if it is returning a split completion to PCI-X form a
normal hub interface completion and receives an immediate response indicating some kind of
error.
Table 53. Hub Interface Response to PCI-X Split Completion Terminations of Completion
Required Cycles
Split Completion
Termination
Hub Interface Cycle
Status Register Bits
Successful
None
• None
• Received Master Abort (Sec)
• Split Completion Discarded (Sec)
• Signaled System Error (Pri) 1
• Received Target Abort (Sec)
• Split Completion Discarded (Sec)
• Signaled System Error (Pri) 1
Master Abort
DO_SERR 1
DO_SERR 1
Target Abort
NOTES:
1. The SO_SERR cycle and setting of the Signaled System Error bit only occur if the SERR# Enabled in
the PCI Primary Device Command Register is set.
4.5.4.4
Behavior of PCI/PCI-X Initiated Cycles to Hub Interface
Table 54. Terminations of Completion Required Cycles to Hub Interface
Hub Interface Termination
PCI Completion
Successful
Status Register Bits Set
• None
Successful
• Received Master Abort (Pri)
• Signaled Target Abort (Sec)
• Received Master Abort (Pri)
• Received Target Abort (Pri)
• Signaled Target Abort (Sec)
• Received Master Abort (Pri)
• Received Target Abort (Pri)
• Signaled Target Abort (Sec)
Master Abort (PCI)
Master Abort (PCI-X)
Target Abort
Target Abort1
Split Master Abort2
Target Abort (PCI)1
Split Target Abort (PCI-X)2
Target Abort (PCI)1
Master and Target Abort
Split Target Abort (PCI-X)2
NOTES:
1. The P64H2 will only signal Target Abort if the error has been logged from the hub interface before the
initial connect by PCI or when the PCI master reconnects after a previous disconnect. If the P64H2
receives an abort on the hub interface in the middle of a read completion stream it will not interrupt the
stream to signal Target Abort.
2. The P64H2 will issue a Split Completion Error Message with either Master Abort or Target Abort for the
remaining completion sequence if an abort is detected on the hub interface. If several bytes of data
returned successfully from the hub interface, and have not yet been sent back on PCI-X, when the abort
is detected on the hub interface the P64H2 will stop the current sequence for that data (if it was
running), and generate the Split Completion Error Message.
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4.6
I/OxAPIC Interrupt Controller (Device 30 and 28)
The P64H2 contains two I/OxAPIC controllers (where x=A or B for PCI Bus A or PCI Bus B),
both of which reside on the primary bus. The intended use of these controllers is to have the
interrupts from PCI bus A connected to the interrupt controller on device 28, and have the
interrupts on PCI bus B connected to the interrupt controller on device 30.
4.6.1
Interrupt Insertion
Interrupts can be delivered to the P64H2 in one of two fashions – either as a pin or a directed
memory write (MSI).
4.6.1.1
Pin Interrupts
Interrupts delivered by a pin can be either in level or edge mode, and may be either active high or
active low. Since this I/OxAPIC is connected to a PCI bus, it’s most likely configuration will be as
active low level, which will match the PCI pin polarity and functionality.
Each pin is collected by the P64H2, synchronized into the 66 MHz clock domain, and scheduled
for delivery if it is unmasked.
Note: The P64H2 has 16 interrupt pins per PCI segment. These pins are connected to redirection table
entries 15 – 0. The hot plug controller is hard-wired to redirection table entry 23 of the APIC on
device 28 (PCI bus A). All other interrupts are only addressable through MSI commands. The
unused pins on the I/OxAPIC unit must be connected to VCC3.3 to ensure the boot interrupt
works correctly.
4.6.1.2
Message Signaled Interrupts (MSI)
In this mode of operation, PCI devices are given a write path directly to the pin assertion register
(memory offset 20h) in the I/OxAPIC that causes the interrupt. Upon accepting the write, the
P64H2 will send the interrupt message to the processor (if the interrupt is unmasked). Interrupts
associated with the PCI Message-based interrupt method must be in edge-triggered mode, but the
level setting (active high or active low) is irrelevant.
4.6.2
Interrupt Delivery
The P64H2 I/OxAPIC can deliver interrupts to the processor through the system bus (via the hub
interface).
4.6.2.1
Front-Side Interrupt Delivery
Interrupt delivery is performed by the P64H2 writing (via the hub interface) directly to a memory
location located in a processor. Software enables the mode by setting the DT bit in the ID
Register.
When operating in this mode, when the IRR bit is set for an interrupt, the P64H2 will perform a
memory write on the hub interface, as seen in Table 55 and Table 56.
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Table 55. System Bus Delivery Address Format
Bit
Description
31:20
19:12
FEEh
Destination ID. This will be the same as bits [63:56] of the I/O Redirection Table entry for the
interrupt associated with this message.
Enhanced Destination ID. This will be the same as bits 55:48 of the I/O Redirection Table entry
for the interrupt associated with this message. If the system bus does not support 64-bit
addressing, these bits are reserved.
11:4
Redirection Hint. The processor host bridge (system bus) uses this bit to allow the interrupt
message to be redirected.
0 = The message will be delivered to the agent (processor) listed in bits 19:4.
1 = The message will be delivered to an agent with a lower interrupt priority
3
The Redirection Hint bit will be a 1 if bits 10:8 in the Delivery Mode field associated with
corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the Redirection Hint bit
will be 0.
Destination Mode. This bit is used only the Redirection Hint bit is set to 1. If the Redirection Hint
bit and the Destination Mode bit are both set to 1, the logical destination mode is used, and the
redirection is limited only to those processors that are part of the logical group as based on the
logical ID.
2
1:0
00
Table 56. System Bus Delivery Data Format
Bit
Description
31:16
15
0000h
Trigger Mode. 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O Redirection Table
for that interrupt.
Delivery Status. 1 = Assert, 0 = Deassert. If using edge-triggered interrupts, then bit will always
be 1, since only the assertion is sent. If using level-triggered interrupts, then this bit indicates the
state of the interrupt input.
14
13:12
11
00
Destination Mode. 1 = Logical, 0 = Physical. Same as the corresponding bit in the Redirection
Table
Delivery Mode. This is the same as the corresponding bits in the I/O Redirection Table for that
interrupt.
10:8
7:0
Vector. This is the same as the corresponding bits in the I/O Redirection Table for that interrupt.
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4.6.3
Buffer Flushing
When the P64H2 receives an interrupt request, it will internally flush its buffers to DRAM. This is
necessary because the I/OxAPIC sits on the primary bus, but the data it affects was delivered on
the secondary bus, and this data may not have made it out of the P64H2 by the time the interrupt
arrives.
In serial mode this is not an issue, because the PCI device driver must do a read, which will force a
flush on the read return, but in front side bus mode, the PCI device driver will not do this read.
Therefore, the front side bus message that the APIC delivers must not go around the posted PCI
data in the internal buffer. This is accomplished by doing an internal flush.
In no circumstances will the P64H2 generate the APIC_FLUSH_REQ hub interface special cycle.
4.6.4
Boot Interrupt
The P64H2 contains a single interrupt output. This is necessary for systems that do not support the
APIC and for boot. The output of the P64H2 is the BT_INTR# pin.
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4.7
SMBus Interface
The SMBus interface does not have any PCI configuration registers. The SMBus address is set
upon PWROK by sampling PAGNT[5:4] and PBGNT[5:4]. When the pins are sampled, the
resulting P64H2 address will be as shown in Table 57.
Table 57. SMBus Address Configuration
Bit
Value
7
6
5
4
3
2
1
1
1
PAGNT5
0
PAGNT4
PBGNT5
PBGNT4
The SMBus controller has access to all internal registers. The generation of cycles on the hub
interface or PCI is not supported transactions, and undefined results may occur if they are
attempted. It can perform reads and writes from all registers through the particular interface’s
configuration space. Hot plug and I/OxAPIC memory spaces are accessible through their
respective configuration spaces.
4.7.1
SMBus Signaling
The SMBus interface includes a pair of signals: SCL (clock) and SDA (serial data). SCL provides
the timing mechanism for data transfers. The SMBus master always drives SCL. SDA carries the
data as driven by the sending device (sender), which can be the initiator or the target.
An initiator starts a transfer over the SMBus when it is free. Details of how initiators arbitrate are
not described here. The current initiator communicates to the desired target through a unique
seven-bit address to the target, sent MSb to LSb. All devices monitor the generated address after
detecting the start condition. Once seven address bits are received, all targets compare the received
address with their own and the target slave finds a match.
The next data bit from the initiator indicates the transfer direction. A value of 1 indicates that the
target needs to transfer data to the initiator (read). Data transfers over SMBus are performed in
8-bit chunks. Data is transferred from MSb to LSb.
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4.7.1.1
Waveforms
The timing relationship between SDA and SCL is shown in Figure 5. Note that the SDA value
must be valid through the duration of SCL being in the high state.
Figure 5. Basic SMBus Transfer Waveform
SCL
SDA
Valid
Valid
Valid
SMBus_Transfer
Start Phase
A start condition is generated when SMBus is idle to indicate that its state is changing to busy. The
start condition occurs when SDA transitions from high-to-low while SCL remains high. The
SMBus protocol also allows a master to “Repeat Start”, meaning that a new transfer is started by
the same master, without a stop condition.
Figure 6. Start (S) / Repeat Start (Sr) Signaling
SCL
SDA
SMBus_Transfer_Start
Stop Phase
A stop condition is generated when SMBus is busy to indicate that its state is changing to idle. The
Stop condition occurs when SDA transitions from low-to-high while SCL remains high.
Figure 7. Stop (P) Signaling
SCL
SDA
A stop bit can occur at any point in a data stream. It is not guaranteed to occur after an ACK from
a target (as later waveforms will show). The P64H2 must be able to accept a stop condition at any
time and clean up.
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ACK/NACK
For every 8 bits of data transfer (including address and direction), the receiving agent must
respond with ACK or NACK. An ACK is requires SDA = 0 during SCL = 1 (see Figure 8). A
NACK requires SDA = 1 during SCL = 1 (see Figure 9).
Figure 8. ACK (A) Signaling
SCL
SDA
SMBus_ACK
Figure 9. NACK (N) Signaling
SCL
SDA
SMBus_nack
During a write cycle, the P64H2 must drive an ACK after the address/direction phase, and after the
data phase. During a read cycle, the P64H2 must drive an ACK/NACK after the address/direction
phase, and (if ACKed) the initiator must drive an ACK/NACK after the P64H2 returns its 8 bits of
data.
Wait States
The receiver (initiator or target) can add wait states, after driving ACK for receiving the last byte,
by driving the SCL line low. Further data transfers are delayed until the receiver stops driving SCL
low. It is expected the P64H2 will drive the SCL line low after receiving data on writes until the
write is complete, and after receiving the direction bit on reads until the read data is ready.
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4.7.1.2
Architecture
The P64H2 SMBus register interface appears to an SMBus master as a stack. The first register in
the stack is at offset 00h, and is the Command Register; the second register is at offset 01h, and is
the bus number register, etc. as shown in Figure 10.
Figure 10. Stack View of SMBus Register Space
Offset
111
110
101
100
011
010
001
Register
Data 3
Data 2
Data 1
Data 0
Register Number
Device / Function Number
Bus Number
Register Index
000
Command / Status
smbus_reg_space
The internal stack has the following characteristics:
• Every write cycle must start with a write to the stack pointer, called “Register Index” in
Figure 10.
• The act of receiving a STOP indication on the SMBus from the master causes the P64H2 to
perform the command encoded in the Command Register to internal configuration register
pointed to by the Bus Number, Device/Function Number, and Register Number Registers. If
the action programmed in the Command Register is a write, then the data registers are also
used. The P64H2 should make no assumption that all bytes will be received. In other words,
on a word write, BIOS should not expect to receive the command, bus number,
device/function number, register number, and then two data bytes. The master could stop at
any byte or within any byte, and the P64H2 must run the cycle with the data it has currently
collected.
• Once a cycle has started the register index stack pointer is no longer considered valid
(i.e., if 4 bytes were written, it is not guaranteed that the pointer is now 4 bytes from its
previous location).
• When a read is attempted, the P64H2 expects 4 bytes to be returned. However, if it receives a
NACK from the master on one if its bytes, it will issue a STOP on the bus and end the
transfer. The first byte returned will start from the current register index.
• When the P64H2 is busy with a command (read or write), it will issue NACKs on the bus on
any subsequent command. It is expected that the master will come back.
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These attributes are shown in Figure 11.
Figure 11. Flow Diagram for SMBus
Begin
Start + Slave Address
+ Direction Received
End
Intel®
P64H2
Hit?
Wait for Stop or
Start Repeat Bits
No
Yes
Write
Direction?
Yes
Yes
No
Send NACK
Busy?
Register Index
No
Received
Send ACK
Send byte pointed to
by Register Index
(note 1)
Stop
Received?
Yes
Ack
Received?
No
Send ACK,
Perform Operation
in Command
Register
Increment Ponter
No
Yes
Start
Repeat
Yes
Received?
No
Last Byte?
No
Yes
Receive Next
Byte, write into
Register Pointed
to by Index
Send STOP
Bit
Register (Note 2)
Send ACK,
End
Increment Pointer
smbus_flow
Note:
1. If this is the first byte of the read, and the P64H2 is in ICH mode (bit 0 of offset FFh set), then
the first data the P64H2 will return is 04h, and the Index Register does not increment.
Subsequent data will be the data pointed to by the Index Register.
2. If this is the first byte received after the index, and the P64H2 is in ICH mode (bit 0 of FFh
set), then the first data the P64H2 receives will be the byte count from the ICH - the P64H2
should discard this data and not increment the index register. Subsequent data will be real
data.
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4.7.1.3
Data Transfer Examples
For the following figures, the following terminology is used:
Start Bit
Sr Start Repeat Bit
S
W
R
A
N
P
Write Command
Read Command
Acknowledge
Retry / not Acknowledge
Stop Bit
The term “Clear” boxes indicate phases of the cycle driven by the initiator, and shaded boxes
indicate phases of the cycle driven by the P64H2.
In Figure 12 an initiator targets the P64H2 with a write, which retries the cycle. Since all read
cycles will first be set up with a write to the register index stack pointer, the P64H2 will only be
busy on a write cycle. For example, if a command had been written indicating a DWord read from
a bus/device-function/register number, the P64H2 will be busy doing the read when the subsequent
write comes into the Register Index.
Figure 12. Intel® P64H2 Busy
S
Slave Address
W
N
P
smbus_busy
In Figure 13 an initiator targets the P64H2 with a write to a P64H2 register. The P64H2 accepts
the cycle, and the master sends the Command Register, Bus Number Register, Device/Function
Number Register, Register Number Register, and data bytes in subsequent bytes. In this example,
the master is sending two bytes (to data 0 and data 1) because the command register was a “word
write”.
The master could have written more or fewer bytes – in the case of a word write, it is not
guaranteed that the master will send both bytes or even all the address information.
Figure 13. Intel® P64H2 Busy
S
Slave Address
W
A
A
A
A
0000_0000 (Register Index)
Bus Number
A
A
A
A
Command
Device/Function Number
Data Byte 0
Register Number
Data Byte 1
P
smbus_busy_1
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In other examples not shown here, the SMBus master may not necessarily program all registers as
shown in the above figure. For example, if a master is performing a series of DWord writes to the
same device (same bus number, device number, and function number), the SMBus master will
write the register index to “03h” (register number) and start with the register number, then its data.
There is no need for it to reprogram the command, bus number, or device/function number
because these are not changing.
In Figure 14 an initiator targets the P64H2 with a write to the Index Register (in this case the data
offset 04h, then does a start repeat with a read. The P64H2 will return data as long as the master
ACKs.
When writing a register in ICH mode, the first byte after the index register will be the byte count.
It should be discarded on writes, and a value of 04h returned on reads, and the index pointer
should not be incremented for this byte.
Figure 14. Reading A Register
S
Slave Address
W
R
A
A
A
A
0000_0100 (Register Index)
Data from Index
A
A
A
Sr
Slave Address
Data from (Index + 1)
Data from (Index + 3)
Data from (Index + 2)
... Data from (Index + N)
N
smbus_reading_A
4.7.1.4
4.7.1.5
Configuration Space Registers
PCI Configuration space registers are accessed directly by programming the bus number, device
number, and register number fields with the appropriate data. The bridge and I/OxAPICs are on
the primary bus, and the hot plug controllers are on the secondary bus.
Memory Space Registers
Accessing memory space registers is a little more complicated. The SMBus protocol implemented
by the server management chips can only access configuration space. As a result, memory space
needs to be accessed indirectly. The hot plug and I/OxAPIC functions, therefore, have aliases in
configuration space to allow these indirect accesses to their memory space registers. See the hot
plug and I/OxAPIC chapters for how the memory space aliases work.
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4.7.2
Configuration Access Arbitration
If the processor is currently accessing a device, the SMBus cannot access the device (i.e., the first
in wins the arbitration). The other agent is stalled until the first agent finishes. The micro-
architecture of this area is critical. The reason for the SMBus interface is to access registers when
the system may be unstable or locked, which can result with broken queues. Any register access
through SMBus must be able to proceed while the system is stuck.
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4.8
System Setup
4.8.1
Clocking
In addition to 33 MHz and 66MHz PCI output clocking, the P64H2 requires 100 MHz and
133 MHz outputs to support PCI-X. Table 58 shows the P64H2 clock domains.
Table 58. P64H2 Clocking
Clock Domain
Frequency
Source
Usage
Main Clock
Generator
Hub Interface
66 MHz
Hub interface core
Hub interface data transfers. Not externally
visible. Internal only to hub interface devices.
Generated by internal PLL from the hub interface
clock.
Hub Interface
Data
266 MHz /
533 MHz
Internal
Internal
External
133/100/66/
33 MHz
PCI
APIC
PCI Bus. These only go to external PCI Bus.
Used for the Intel® P64H2 interrupt messages.
Typically will be 16.6667 MHz, but can be 33MHz
for FRC mode. Only used for P6 FSB platforms.
Tied high otherwise.
16–33 MHz
Source
Synchronous
This pin is controlled by the driver of the SMBus
interface, and will run between 10 and 100 kHz.
SMBus
KHz
The PCI/PCI-X input clock for each interface, PxPCLKI, can be considered to have a synchronous
relationship to the hub interface input clock (CLK66) provided the following three conditions are
met.
• The PxPCLKI input is connected to the PxPCLKO6 PCI clock output, and
• The PxPCLKI input meets the Tskew (min) and Tskew (max) timing relative to CLK66.
• The PxPCLKI is running at 33 or 66 MHz.
If the above three conditions are met for an interface, configuration offset E0h bit 4 can be set to a
1 and the PCI clock and the hub interface clock will be treated as synchronous clocks to reduce
data latency.
If the input PxPCLKI is driven from an external clock driver and not PxPCLKO0, or if Tskew (min)
and Tskew (max) are not met, or if the PCI-X bus frequency is 100 MHz or 133 MHz, BIOS should
leave configuration offset E0h bit 4 at its reset value of 0 and the clocks will be considered
asynchronous.
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Figure 15. 66 MHz PCLK Skew
Tskew
(max)
Tskew
(min)
CLK66
66 MHz PXPCLKI
Tskew (min)
66 MHz PXPCLKI
Tskew (max)
Clk_skew_66mhz
4.8.2
Component Reset
It may take the P64H2 logic up to 128 ms after primary reset deassertion and up to 2 ms after
secondary bus reset deassertion for the PCI buffers to be fully compensated. System BIOS timings
must guarantee that no PCI cycles are attempted on the P64H2 PCI bus during these times.
There are three varieties of reset that could be performed on the P64H2. They are listed from
highest level of reset to the lowest level of reset.
1. PWROK: When this reset is used, RSTIN# must also be asserted. This reset determines the
hot plug mode of operation (no hot plug, single-slot, dual-slot, and multi-slot). This signal
must go inactive at least 1 ms before RSTIN# goes inactive to ensure the PCI bus is in the
proper mode.
2. RSTIN#: This signal is typically connected to the PCIRST# output of the ICHx but can come
from any source. When this pin is asserted, all logic (except the RAS register bits) in the
P64H2 is reset. This reset also causes the PCIRST# output of each PCI interface to be
asserted. The hot plug mode of operation is not affected by this reset.
3. Software setting the PCI Reset bit (bit 6) in the Bridge Control Register: This causes
PCIRST# output of the particular interface to be reset. The hot plug mode, hub interface,
configuration registers, RAS bits, and peer PCI interface are not affected by the assertion of
this bit.
4.8.2.1
Software PCI Reset
This reset is also caused upon an RSTIN# reset (Section 4.8.2.2) and PowerOK reset. This reset
exists to reset a hung PCI bus, and to change PCI bus frequency. On the active edge of this reset,
the P64H2 changes the PxPCLKO[5:0] frequency to that dictated by bits 8:6 of PCI configuration
offset 40h in the bridge being reset.
If the PCI bus is in single-slot mode and the card is disconnected, the bus is driven to ground as
described in Section 4.3.3.
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4.8.2.2
RSTIN#
This reset also occurs upon a PowerOK reset. This reset causes the P64H2 to set the initial
frequency for each PCI bus (based on Table 59).
Table 59. Determining PCI/PCI-X Bus Frequency
Hot Plug Exists?1
Px_133EN
PxM66EN
PxPCIXCAP
Bus Mode
Yes
Don’t Care
Don’t Care
Don’t Care
Don’t Care
0
Don’t Care
0
Don’t Care
PCI 33
PCI 33
0
0
1
PCI 66
No
Don’t Care
Don’t Care
Don’t Care
Low
1
PCI-X 66
PCI-X 100
PCI-X 133
1
1
NOTES:
1. See Section 4.8.2.3 to see how hot plug existence is determined.
4.8.2.3
PowerOK
The primary purpose of this reset is to determine the hot plug mode. While this reset is active
(low), the hot plug mode is unknown, and could be single-slot with no isolation logic. To avoid
damage to the system, each PCI bus is driven to ground until PowerOK goes inactive, sampling
HPx_SLOT[2:0].
It may take the P64H2 up to 128 ms after primary reset deassertion and up to 2 ms after secondary
bus reset deassertion for the PCI buffers to be fully compensated. System BIOS timings must
guarantee that no PCI cycles are attempted on the P64H2 PCI bus during these times.
When this pin goes inactive, HPx_SLOT[2:0] are sampled to determine the hot plug mode and
final bus state (see Table 60).
Table 60. Hot Plug Mode and Final Bus State
HPx_SLOT[2:0]
Hot Plug Exists?
PCI Bus Action
000
001
No
Release
Yes
Yes
Continue driving to ground
Release
010–111
As this reset must be performed in conjunction with RSTIN# being asserted, the PCI busses
behave as described in Section 4.8.2.2. However, since the bus is driven to ground until the hot
plug mode is determined (hot plug either does not exist or exists but not in single-slot mode), the
bus must first be put in a state where it looks IDLE.
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4.8.3
I/OxAPIC System Assumptions
The I/OxAPICs in the P64H2 reside on the primary PCI bus. Therefore, it is conceivable that
devices on either bus may talk to either I/OxAPIC. However, special precautions must be made.
For devices that operate in “pin mode”, where a pin signals the interrupt, the interrupt pins that
reside on PCI bus A (PAIRQ[15:0]) must be routed to devices on PCI bus A or bridges that reside
behind PCI bus A. Similarly, interrupt pins that reside on PCI bus B (PBIRQ[15:0]) must be
routed to devices on PCI bus B or bridges that reside behind PCI bus B. This is because the
respective I/OxAPICs only perform buffer flushing for the PCI bus where interrupts are collected.
For devices in “MSI mode”, it is irrelevant how the interrupts are mapped. A device on PCI bus B
is allowed to perform an MSI to the I/OxAPIC on PCI bus A. This is because the MSI will
perform the buffer flush action on its respective bus.
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4.9
Reliability, Availability, and Serviceability (RAS)
It is important for the P64H2 to log error information in server environments, such that software
has the ability to recover from the error. Errors fall into two classes:
• Integrity errors on busses (PCI/ hub interface)
• Soft errors inside of the component (in the case of the P64H2, the data RAMs).
When logging the error, it is important that the first one be logged. Chances are, when you receive
an error, you are about to receive multiple errors; therefore, it is important to know where the error
chain began. Thus, the logic associated with logging errors will have a “lock down” feature to it.
Once an error is detected, it is logged and no other errors will be logged until the first error is
cleared.
RAS logging will be simplified into four rules, and two new terms. The new terms are:
• Context Data:The address/data of the cycle that caused the error. For example, on a cycle
that is split, the context address is the address of the cycle on the original request, not on the
completion.
• Live Data:The value of the pins (address, data, byte enables, header) of the error.
The rules are:
• Cycle Errors: Target Abort and Master Abort are cycle errors. In these types of errors, the
context data is stored along with the error indication. This is stored as opposed to live data
because there is nothing fundamentally wrong with the live data – it is the context data that
resulted in the error.
• Address Parity Errors: Live data is stored in these types of errors, because the P64H2 does
not have enough information as to what the intended address was supposed to be, and the live
data is needed to decode the parity error.
• Data Parity Errors: Live data is stored for the erroneous data, and context address is stored
for the address. The live data is needed to decode the parity error, and the context address is
needed in case software can recover.
• The hub interface stores errors only as a receiver, where PCI stores errors as a receiver and a
generator. Hub interface errors can be simplified because the same RAS functionality in the
P64H2 is also in the MCH, and the burden can be shared, while PCI cards do not have the
same level of RAS so the P64H2 must keep more information around.
The RAS feature bits are sticky through reset. Therefore, the registers at offset 60h of each hub
interface to PCI bridge (device 31 and 30), bits 5:0 and 13:8, which signify RAS events, are not
cleared. BIOS must clear these at system power up.
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4.9.1
Error Types
P64H2 errors are classified into two categories, those that are considered fatal and those that are
considered non-fatal.
The non-fatal class of errors are:
• Cycles that are Target or Master Aborted on the hub interface and PCI.
• Single bit ECC errors (command or data) on the hub interface.
The fatal class of errors are:
• Data and Command errors on outbound cycles from the hub interface.
• Data and Command errors on inbound cycles from PCI.
• Data errors that are a result of failures on the internal SRAM for outbound cycles.
• Data errors that are a result of failures on the internal SRAM for inbound cycles.
When an error is logged, the RASERR# pin will be driven active. This pin will remain active until
software clears the status bit that caused the error. This pin is a level mode pin. It is simply an OR
of the status bits shown in bits [13:8] and bits [5:0] of the RAS_STS Register (offset 60h).
Non-fatal errors can be optionally disabled, by clearing the ENFE bit in the RAS_STS Register
(bit 15 of offset 60h). If this bit is cleared, non-fatal errors do not set the RASERR# pin, although
the errors are still logged and the status bit set. This disable allows less intelligent system
management controllers, which may simply reboot the system on an error, from rebooting the
system due to a master abort or single bit ECC error.
4.9.2
Error Logging
When the first error is caught on an interface, subsequent errors for the error class for that bridge
are not recorded. However, errors on the other bridge can still be recorded. Additionally, if a non-
fatal error occurs on the bridge, then is followed later by a fatal error on that same bridge, the fatal
error overrides the non-fatal error, and the fatal error is logged. However, a non-fatal error cannot
override a previous non-fatal error.
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All errors are logged in PCI configuration space for the bridge, at offsets 60h to 8Fh. All bits in
these registers are sticky through reset. Bits [5:0] of offset 60h are the fatal error class status bits,
and bits [13:8] of offset 60h are the non-fatal error class status bits. One and only one of these bits
may be set at any time. These bits must be cleared by BIOS upon a power-up reset, to ensure that
at power-up there are no errors logged. By making these bits sticky through reset, if an SERR# is
signaled and the system reboots, causing PCIRST# to be asserted, the error will remain intact.
• Software (either from platform BIOS or a system management controller using SMBus) must
deal with fatal errors that override non-fatal errors. The following algorithm is suggested. This
is not to imply a solution set, but to show how the hardware provided allows software to
determine the exact error: Check the non-fatal status bits (bits [13:8] of offset 60h) to see if it
is a non-fatal error. If one of these bits is set, set a variable to remember that this error could
be overridden. The P64H2 hardware will ensure that only one of these bits is set.
• Check the fatal status bits (bits [5:0] of offset 60h) to see if it is a non-fatal error. If one of
these bits is set, clear the “could be overridden” variable. This implies that between the time
software read the non-fatal status bits and the fatal status bits, a fatal error occurred that
overrode the non-fatal error. Hardware will ensure that only one of these bits is set.
• Read the RAS registers to determine the address and data of the error, based upon the status
bits.
• If the “could be overridden” status bit is set, read the fatal error status bits again. If one of
these is now set, it means between the time software started reading the RAS registers and
now, a fatal error occurred. The RAS registers cannot be trusted because they could have been
overwritten. Re-read the RAS registers.
• Clear the status bit that caused the failure by writing a 1.
Below is a summary list of the rules for the types of errors logged by the P64H2:
• For hub interface, the logged errors are:
Outbound Write/Read ECC error on header: Corrupted header
Outbound Write ECC Error on data: Good header and corrupted data
Inbound Read Completion Error on completion header: Corrupted completion header
Inbound Read Completion Error on completion data: Good request (not completion)
header and corrupted data
• For PCI, the logged errors are:
Outbound Write/Read Parity Error on address attributes: Corrupted address/attributes
Outbound Write Parity Error on data: Good address and corrupted data
Inbound Read Completion Error on completion address attributes: Corrupted completion
address/attributes
Inbound Read Completion Error on completion data: Good request (not completion)
address/attributes and corrupted data
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4.9.3
Logged Errors
For the hub interface, the logged errors are:
• Outbound Write/Read ECC Error on Header: Corrupted Header.
• Outbound Write ECC Error on Data: Good Header and Corrupted Data.
• Inbound Read Completion Error on Completion Header: Corrupted Completion Header.
• Inbound Read Completion Error on Completion Data: Good Request (not completion) Header
and Corrupted Data.
For PCI, the logged errors are:
• Outbound Write/Read Parity Error on Address/Attributes: Corrupted Address/Attributes.
• Outbound Write Parity Error on Data: Good Address and Corrupted Data.
• Inbound Read Completion Error on Completion Address/Attributes: Corrupted Completion
Address/Attributes.
• Inbound Read Completion Error on Completion Data: Good Request (not completion)
Address/Attributes and Corrupted Data.
4.9.4
Allowable Error Combinations for RAS_STS
One PCI error (fatal or non-fatal), and one hub interface error (fatal or non-fatal) may occur at the
same time. For example, two cycles could target the P64H2 from different interfaces (one from the
hub interface and one from PCI, and both have errors detected on the same clock. Due to this,
there may be two bits set in the RAS_STS Register. They are:
• One of HTA, HMA, AEHS, DEHS, AEHM, DEHM, DEBO
• One of PTA, PRMA, AEP, DEP, DEBI
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Table 61 provides valid values in the RAS_STS Register (offset 60h). All entries marked as
“invalid” mean that the event is invalid for this particular RAS_STS bit.
Table 61. RAS_STS Register (offset 60h) Values
Error Bit Set
Allowable Values
Notes
Name
Bit
HAGT (bit 20)
PAGT (bits 23:21)
HTA
HMA
PTA
13
12
11
0, 1
0, 1
Invalid
Invalid
Invalid
000 – 101, 111
Intel® P64H2 can only receive a master abort
on PCI, it cannot generate one.
PRMA
10
Invalid
111
AEHS
DEHS
AEP
9
8
5
4
1
Invalid
Invalid
1
Invalid
1
000 – 101
Invalid
P64H2 will not generate an address parity error.
AEHM
If a failure occurs internal to the P64H2 heading
towards the hub interface (or the peer PCI),
then the P64H2 is the failure agent.
DEBI
DEP
3
2
1
0
0
Invalid
000 – 101
111
P64H2 will not generate a data parity error,
unless the data is being poisoned from a failure
due to DEBO or DEHM. Therefore, the error will
already have been logged.
Invalid
Invalid
1
If a failure occurs internal to the P64H2 heading
towards PCI from the hub interface or a PCI
peer, then the P64H2 is the failure agent.
DEBO
DEHM
P64H2 will not generate a data parity error,
unless the data is being poisoned due to DEBI
or DEP. Therefore, the error will already have
been logged.
Invalid
4.9.5
Data Poisoning
When an error is logged by the P64H2, that error will still proceed to its final interface. However,
the data shall remain poisoned throughout the transfer (except in the case of single bit ECC errors).
Therefore, a multi-bit ECC error on the hub interface will result in a parity error on PCI, a parity
error on PCI will result in a forced multi-bit ECC error on the hub interface, and an error on the
internal SRAM will cause a parity / multi-bit ECC error at its destination interface.
Intel® 82870P2 P64H2 Datasheet
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5 Electrical Characteristics
This chapter provides DC and AC electrical characteristics for various P64H2 interfaces.
5.1
DC Voltage and Current Characteristics
5.1.1
Intel® P64H2 DC Characteristics
Table 62. Intel® P64H2 DC Voltage Characteristics
Symbol
VCC1.8
Parameter
Min
Typ
Max
Unit
P64H2 Core and HI2.0 I/O supply
VCC1.8 Transient Tolerance
PCI Bus Interface
1.71
1.8
1.89
± 5%
3.465
± 5%
5.25
2.1
V
V
VCC1.8 Transient
VCC3.3
3.135
Y
3.3
5.0
V
VCC3.3 Transient
VCC5REF
VCC3.3 Transient Tolerance
5V Reference for PCI Bus
P64H2 Core and HI2.0 I/O
Transient Core Tolerance
Thermal Design Power
V
4.75
V
VCC1.8dI/dt
VCC3.3dI/dt
PTDP
A/ns
A/ns
W
1.32
4.6
Table 63. Intel® P64H2 DC Current Characteristics
Voltage at PCI/PCI-X Interface
ICCMax Sustained
1.8 V at 33 MHz PCI (both segments)
1970 mA
2170 mA
2550 mA
2660 mA
930 mA
1.8 V at 66 MHz PCI/PCI-X (both segments)
1.8 V at 100 MHz PCI-X (both segments)
1.8 V at 133 MHz PCI-X (both segments)
3.3 V at 33 MHz PCI 6 loads (both segments)
3.3 V at 66 MHz PCI 2 loads (both segments)
3.3 V at 66 MHz PCI-X 4 loads (both segments)
3.3 V at 100 MHz PCI-X 2 loads (both segments)
3.3 V at 133 MHz PCI-X 1 load (both segments)
690 mA
1300 mA
1050 mA
770 mA
In most cases a thermal heat spreader will be required for the P64H2. For more information, refer
to the appropriate chipset thermal design guide.
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5.1.2
Input Characteristic Signal Association
Table 64. DC Characteristics Input Signal Association
Symbol
Signals
Interrupt Signals: PAIRQ[15:0], PBIRQ[15:0]
VIH1/VIL1
PCI Signals: PAAD[63:0], PAC/BE[7:0]#, PAPAR, PADEVSEL#, PAFRAME#, PAIRDY#,
PATRDY#, PASTOP#, PBSTOP#, PAPERR#, PBPERR#, PASERR#, PBSERR#,
PAREQ[5:0]#, PBREQ[5:0]#, PAM66EN, PBM66EN, PA_133EN, PB_133EN, PAPCIXCAP,
PBPCIXCAP, PAPAR64, PBPAR64, PAREQ64#, PBREQ64#, PAACK64#, PBACK64#
Hot plug Signals: HPA_SID, HPB_SID, HPA_SLOT[2:0], PB_SLOT[2:0]
P64H2 Clock Signals (3.3 V Only): CLK66, PACLKI, PBCLKI, PBCLK100, PBCLK133
Miscellaneous Signals: PWROK, RSTIN#
Others: TEST# (3.3 V only)
VIH2/VIL2
VIH3/VIL3
VIH4/VIL4
VIH5/VIL5
VIH6/VIL6
Hub Interface Signals: HI_[21:0], PSTRBF, PUSTRBF, PSTRBS, PUSTRBS
CPU Signals: APICD[1:0]
SMB Signals: SDTA, SCLK
APIC Signal: APICCLK
P64H2 Hub Interface Clock Signals: CLK200/CLK200#
5.1.3
DC Input Characteristics
Table 65. DC Input Characteristics
5 V Signal
Min
3.3 V Signal
Max
Symbol
VIL1
Parameter
Input Low Voltage
Max
Min
Unit
-0.5
2.0
0.8
-0.5
0.35VCC
VCC +0.5
VREF–0.1
V
V
V
V
V
V
V
V
V
V
V
V
VIH1
VIL2
VIH2
VIL3
VIH3
VIL4
VIH4
VIL5
VIH5
VIL6
VIH5
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
VCC+0.5
0.5VCC
VREF+0.1
-0.5
0.6
VCC + 0.5
0.6
1.2
-0.5
2.1
VCC + 0.5
0.7
-0.5
1.7
2.626
0.55
0.75
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5.1.4
DC Characteristic Output Signal Association
Table 66. DC Characteristic Output Signal Association
Symbol
Signals
VOH1/VOL1
Interrupt Signals: BT_INTR#
PCI Signals: PAAD[63:0], PAC/BE[7:0]#, PAPAR, PADEVSEL#, PAFRAME#,
PAIRDY#, PATRDY#, PASTOP#, PBSTOP#, PAPERR#, PBPERR#, PAM66EN,
PBM66EN, PAGNT[5:0]#, PBGNT[5:0]#, PAPLOCK#, PBPLOCK#, PAPAR64,
PBPAR64, PAREQ64#, PBREQ64#, PAACK64#, PBACK64#
P64H PCI Clock Signals (3.3 V Only): PAPCLKO[6:0], PBPCLKO[6:0], PAPCIRST#,
PBPCIRST#
Hot Plug Signals: HPA_SIC, HPB_SIC, HPA_SIL#, HPB_SIL#, HPA_SOR#,
HPB_SOR#, HPA_SORR#, HPB_SORR#, HPA_SOC, HPB_SOC, HPA_SOL,
HPB_SOL, HPA_SOLR, HPB_SOLR, HPA_SOD, HPB_SOD
Miscellaneous Signals: RASERR#
VOH2/VOL2
VOH3/VOL3
VOH4/VOL4
Hub Interface B Signals: HLB[19:0], PSTRBF, PUSTRBF, PSTRBS, PUSTRBS
Processor Signals: APICD[1:0]
SMBus Signals: SDTA, SCLK
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5.1.5
DC Output Characteristics
Table 67. DC Output Characteristics
5 V Signal
3.3 V Signal
Symbol
Parameter
Min
Max
0.55
Min
Max
Unit
Notes
VOL1
Output Low Voltage
0.1VCC
V
(5 V) Iout = 6 mA
(3.3 V) Iout = 1500 uA
(5 V) Iout = -2 mA
(3.3 V) Iout = -500 uA
Iol = 1.0mA
VOH1
Output High Voltage
2.4
0.6
0.9VCC
V
VOL2
VOH2
VOL3
VOH3
VOL4
VOH4
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
0.05
1.2
V
V
V
V
V
V
Ioh = -0.6/ HI_Rcomp mA
IOL4=14 mA
0.45
2.625
0.4
Open Drain
IOL5=14 mA
N/A
Open Drain
5.1.6
Other DC Characteristics
Table 68. Other DC Characteristics
Symbol
Parameter
Min
Max
Unit
Notes
VCC5REF
VCC3.3
VCC1.8
HI_VREF
IREF
Intel® P64H2 Reference Voltage
Core Voltage
3.0
3.0
5.25
3.6
V
V
Hub Interface Voltage
1.7
1.9
V
Hub Interface Reference Voltage
HI_VREF pin input current
Input Leakage Current
0.343
0.357
± 50
V
0.35V ± 5%
uA
uA
IIL
+ 10
PCI signals,
0 < Vin < VCC
FC = 1 MHz
CIN
Input Pin Capacitance
8
pF
COUT
CCLK
Output Pin Capacitance
10
12
pF
pF
FC = 1 MHz
P64H2 Clock Pin Capacitance
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Electrical Characteristics
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5.1.6.1
Hub Interface 2.0 DC Characteristics
Hub Interface 2.0 is optimized to operate with a nominal VCC of between 1.00 V and 1.80 V
based on a constant amplitude signaling voltage of 0.8 V, referenced to VSS. The parameters in
Table 69 are the requirements for the common clock and source synchronous modes of the hub
interface.
Table 69. DC Characteristics for Hub Interface Common Clock Signaling
Symbol
Parameter
Min
Max
Units
Condition
Notes
VCC
I/O Supply Voltage
Input High Voltage
1.71
1.89
V
V
1
V
HI_VREF
+ 0.1
IH
V
Input Low Voltage
HI_VREF
– 0.1
V
uA
V
IL
I
Input Leakage
Current
150
750
1.2
0<VIN<VIH(max)
IL
V
Output High Voltage
0.60
I
= -0.6/ HI_RCOMP mA
2
OH
out
48 Ω ≤ HI_RCOMP ≤ 62 Ω
= 1.0 mA
V
Output Low Voltage
-0.3
5
0.05
5
V
I
2
3
OL
out
C
in
Input Pin
Capacitance
pF
CCLK
CLK Pin
8
pF
3
Capacitance
NOTES:
1. VCC only specifies the voltage at the hub interface; component supply voltages are independent of
VCC. Component I/O buffers must be powered only from VCC. VCC for both hub interface compliant
master and hub interface compliant target must be driven from the same power rail.
2. The minimum VOL and maximum VOH values are not acceptable nominal DC operating points. They
represent the absolute maximum allowed voltage allowed on the pin (i.e., VOH due to incomplete
impedance updates on the drivers and terminator).
3. Absolute maximum pin capacitance for hub interface input is 8 pF (except for CLK66).
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Table 70. DC Characteristics for Hub Interface Source Synchronous Signaling
Sym
VCC
Parameter
Min
Max
Units
Condition
Notes
I/O Supply Voltage
1.71
1.89
V
V
HI_VREF
Input reference
voltage
0.326
0.375
HI_VREF =
(0.7*VCC/3.6) ± 2%
1
1
IREF
HI_VREF pin input
current
± 50
uA
VIH
VIL
IIL
Input High Voltage
Input Low Voltage
Input leakage Current
Output High Voltage
HI_VREF+ 0.1
V
V
HI_VREF– 0.1
150
750
1.2
uA
V
0<VIN<VIH(max)
I = -0.6/HI_RCOMP mA
VOH
0.60
out
48Ω ≤ HI_RCOMP ≤ 62Ω
I = 1.0 mA
out
VOL
Output Low Voltage
-0.3
0.05
V
NOTES:
1. Hub interface requires differential input receivers to achieve the tight timing tolerances needed for
533 MT/S. Nominal value of HI_VREF is 0.350 V which can be designed with 2% resistor to achieve the
specified min and max values. The value of HI_VREF is intended to specify near the center point of the
VIL/VIH range.
5.1.6.2
PCI Interface DC Characteristics (5 V Signaling Environment)
Table 71 summarizes the DC characteristics for 5 V signaling.
Table 71. DC Characteristics for PCI 5 V Signaling
Sym
Parameter
Supply Voltage
Min
Max
Units
Condition
Notes
VCC
VIH
VIL
4.75
2.0
5.25
VCC +0.5
0.8
V
V
Input High Voltage
Input Low Voltage
-0.5
V
IIH
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
Output Low Voltage
70
µA
µA
V
Vin = 2.7
1
IIL
-70
Vin = 0.5
1
VOH
VOL
2.4
Iout = -2 mA
0.55
V
Iout = 3 mA,
6 mA
2
Cin
Cclk
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
10
12
8
pF
pF
pF
5
CIDSEL
3
NOTES:
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up resistors
must have 6 mA; the latter include, PxFRAME#, PxTRDY#, PxIRDY#, PxDEVSEL#, PxSTOP#,
PxSERR#, PxPERR#, PxLOCK#, and, when used, PxAD[63:32], PxC/BE[7:4]#, PxPAR64, PxREQ64#,
and PxACK64#.
3. Lower capacitance on this input-only pin allows for non-resistive coupling to PxAD[xx].
Intel® 82870P2 P64H2 Datasheet
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Electrical Characteristics
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5.1.6.3
PCI Interface DC Characteristics (3.3 V Signaling Environment)
Table 72 summarizes the DC characteristics for 3.3 V signaling.
Table 72. DC Characteristics for PCI 3.3 V Signaling
Symbol
Parameter
Supply Voltage
Min
Max
Units
Condition
Notes
VCC
VIH
3.135
0.5VCC
-0.5
3.465
V
V
Input High Voltage
VCC +0.5
0.3VCC
VIL
Input Low Voltage
V
VIPU
IIL
Input Pull-up Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
0.7VCC
V
±10
µA
V
0 < Vin < VCC
Iout = -500 µA
Iout = 1500 µA
1
VOH
VOL
Cin
0.9VCC
0.1VCC
V
10
12
8
pF
pF
pF
Cclk
CIDSEL
5
4
NOTES:
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
2. Lower capacitance on this input-only pin allows for non-resistive coupling at PxAD[xx].
5.1.6.4
PCI-X Interface DC Characteristics
Table 73 shows the DC characteristics for PCI-X mode.
Table 73. DC Characteristics for PCI-X
Sym
Parameter
Supply Voltage
Min
Max
Units
Condition
Notes
VCC
VIH
3.135
0.5VCC
-0.5
3.465
V
V
Input High Voltage
VCC +0.5
0.35VCC
VIL
Input Low Voltage
V
VIPU
IIL
Input Pull-up Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
0.7VCC
V
±10
µA
V
0 < Vin < VCC
Iout = -500 µA
Iout = 1500 µA
1
VOH
VOL
Cin
0.9VCC
0.1VCC
V
8
8
8
PF
PF
PF
2
3
Cclk
CIDSEL
5
NOTES:
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
2. Absolute maximum pin capacitance for PCI/PCI-X input except CLK and IDSEL.
3. For conventional PCI only, lower capacitance on this input-only pin allows for non-resistive coupling to
Px_AD[xx]. PCI-X configuration transactions drive the AD bus four clocks before PxFRAME# asserts.
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5.1.6.5
PCI Hot Plug DC Characteristics
Table 74. PCI Hot Plug Slot Power Requirements
Supply
Voltage
Maximum
Operating
Current1
Maximum Adapter Card
Decoupling
Minimum
Supply Voltage
Skew Rate
Maximum
Supply Voltage
Skew Rate
Capacitance
+5 V
+3.3 V
+12 V
-12 V
5 A
3000 µF
3000 µF
300 µF
150 µF
25 V/s
16.5 V/s
60 V/s
3300 V/s
3300 V/s
33000 V/s
66000 V/s
7.6 A
500 mA
100 mA
60 V/s
NOTE: Combined maximum power drawn by all supply voltages in any one slot must not exceed 25 W.
5.1.6.6
Input Clock DC Characteristics
Table 75. DC Characteristics for Input Clock Signals
Symbol
Parameter
Input Low Voltage
Min
Max
Units
BPCLK66
BPCLK66
BPCLK200
BPCLK200
BPCLK100
BPCLK100
BPCLK133
BPCLK133
APICCLK
-0.5
2.0
0.8
VCC3.3 + 0.5
0.55
V
V
V
V
V
V
V
V
V
V
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
-0.2
0.75
-0.5
2.0
1.45
0.8
VCC3.3 + 0.5
0.8
-0.5
2.0
VCC3.3 + 0.5
0.7
-0.5
1.7
APICCLK
2.625
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5.1.6.7
Output Clock DC Characteristics
Table 76. DC Characteristics for Output Clock Signals
Symbol
Parameter
Output Low Voltage
Min
Max
Units
Condition
CLK33
CLK33
0.4
V
V
V
V
V
V
V
V
Iol = 1 mA
Ioh= -1 mA
Iol = 1 mA
Ioh= -1 mA
Iol = 1 mA
Ioh= -1 mA
Iol = 1 mA
Ioh= -1 mA
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
2.4
2.4
2.4
2.4
CLK66
0.4
0.4
0.4
CLK66
CLK100
CLK100
CLK133
CLK133
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5.2
AC Characteristics and Timing
5.2.1
PCI Interface Timing
Table 77. PCI Interface Timing (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%, Tcase=0qC to 105qC)
66 MHz
Max
33 MHz
Max
Symbol
Parameter
Min
Min
Units
Notes
Tval
PxPCLKO[6:0] to Signal Valid Delay- bused
signals
2
6
6
2
11
12
ns
1, 2, 6
Tval(ptp)
PxPCLKO[6:0] to Signal Valid Delay-point-to-
point signals
2
2
2
2
ns
1, 2, 6
Ton
Toff
Tsu
Float to Active Delay
Active to Float Delay
ns
ns
ns
1, 6, 7
1, 7
14
28
Input Setup Time to PxPCLKO[6:0]-Bused
signals
3
5
7
2, 3, 8
Tsu(ptp)
Input Setup Time to PxPCLKO[6:0]; point-to-
point
10,12
ns
2, 3
Th
Input Hold Time from PxPCLKO[6:0]
Reset Active Time after power stable
0
1
0
1
ns
ms
µs
3
4
4
Trst
Trst-clk
Reset Active Time after PxPCLKO[6:0]
stable
100
100
Trst-off
Trrsu
Trrh
Reset Active to output float delay
PxREQ64# to RSTIN# setup time
RSTIN# to REQ64# hold Time
40
50
40
50
ns
ns
4, 5
10Tcyc
10Tcyc
0
225
5
0
225
5
ns
Trhfa
Trhff
RSTIN# high to first configuration access
RSTIN# high to first FRAME# Assertion
clocks
clocks
NOTES:
1. SeeFigure 16. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc
2. PxREQ[5:0]# and PxGNT[5:0]# are point-to-point signals and have different input setup times than do
bused signals. PxGNT[5:0]# and PxREQ[5:0]# have a setup of 5 ns at 66 MHz. All other signals are
bused.
.
3. See Figure 17.
4. If PxM66EN is asserted, PxPCLKO[6:0] is stable when it meets the requirements in the PCI Local Bus
Specification, Revision 2.2. RSTIN# is asserted and deasserted asynchronously with respect to
PxPCLKO[6:0].
5. All output drivers must be floated when RSTIN# is active.
6. When PxM66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton may be
reduced to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when PxM66EN is
deasserted.
7. For purposes of active/float timing measurements, the Hi-Z or “off” state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification.
8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals
at the same time. Refer to the PCI Local Bus Specification for more details.
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Figure 16. PCI Output Timing
Vth
Vtl
PxPCLKO[6:0]
Vtest
Tval
Output
Delay
VTfall
Tval
VTrise
Output
Delay
Tri-State
Output
Ton
Toff
Time_PCI-out-measCond
Figure 17. PCI Input Timing
Vth
Vtl
PxPCLKO[6:0]
Vtest
Tsu
Th
Vth
Vtl
inputs
valid
Input
Vtest
Vtest
Vmax
Time_PCI-in-measCond
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5.2.1.1
PCI Clock Characteristics
The clock waveform must be delivered to each PCI component in the system. Figure 18 shows the
clock waveform and required measurement points for both 5 V and 3.3 V signaling environments.
Table 78 summarizes the clock specifications.
Figure 18. PCI Clock Waveforms
5 Volt Clock
2.4 V
2.0 V
1.5 V
0.8 V
2 V, p-to-p
(minimum)
0.4 V
Tcyc
3.3 Volt Clock
Thigh
0.6 Vcc
Tlow
0.5 Vcc
0.4 Vcc
0.3 Vcc
0.4 Vcc, p-to-p
(minimum)
0.2 Vcc
Time_PCI-Clocks
Table 78. PCI Clock Characteristics (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0 qC to 105 qC)
66 MHz
Max
33 MHz
Max
Sym
Tcyc
Parameter
Min
Min
Units
Notes
PxPCLKO[6:0] cycle time
PxPCLKO[6:0] high time
PxPCLKO[6:0] low time
PxPCLKO[6:0] slew rate
Modulation frequency
Frequency spread
15
6
30
30
11
11
1
Infinity
ns
ns
1,3
Thigh
Tlow
6
ns
—
1.5
30
-1
4
33
0
4
V/ns
kHz
%
2
Fmod
Fspread
—
—
NOTES:
1. In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz.
PxPCLKO[6:0] requirements vary depending on whether the clock frequency is above 33 MHz.
- Device operational parameters at frequencies at or under 33 MHz will conform to the PCI Local Bus
Specification, Revision 2.2 in Chapter 4. The clock frequency may be changed at any
time during the operation of the system so long as the clock edges remain “clean” (monotonic) and
the minimum cycle and high and low times are not violated. The clock may only be stopped in a low
state. A variance on this specification is allowed for components designed for use on the system
planar only. Refer to PCI Local Bus Specification Revision 2.2 for more information.
- For clock frequencies between 33 MHz and 66 MHz, the clock frequency may not change except
while RSTIN# is asserted or when spread spectrum clocking (SSC) is used to reduce EMI emissions
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met
across the minimum peak-to-peak portion of the clock waveform as shown in Figure 19.
3. The minimum clock period must not be violated for any single clock cycle (i.e., accounting for all system
jitter).
Intel® 82870P2 P64H2 Datasheet
191
Electrical Characteristics
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5.2.1.2
PCI Clock Uncertainty
The maximum allowable clock skew including jitter is 1 ns. This specification applies not only at a
single threshold point, but also at all the points on the clock edge that fall in the switching range
defined in Table 79 and Figure 19. The maximum skew is measured between any two components,
not between connectors.
Note: The system designer must address an additional source of clock skew. This clock skew occurs
between two components that have clock input trip points at opposite ends of the VIL – VIH range.
In certain circumstances, this can add to the clock skew measurement as described here. In all
cases, total clock skew must be limited to the specified number.
Table 79. PCI Clock Skew Parameters (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0qC to 105qC)
Symbol
Vtest
66 MHz 3.3 V Signaling
0.4 VCC
33 MHz 3.3 V Signaling
0.4 VCC
Units
V
Tskew
1 (max)
2 (max)
ns
Figure 19. PCI Clock Skew
Vih
Clock @ Device 1
Vtest
Vil
Tskew
Tskew
Tskew
Vih
Vil
Clock @ Device 2
Vtest
PCIX_clk_uncertainty
192
Intel® 82870P2 P64H2 Datasheet
Electrical Characteristics
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5.2.2
PCI-X Interface Timing
Table 80. PCI-X General Timing Parameters (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0qC to 105qC)
PCI-X 133
PCI-X 66
Sym
Tval
Parameter
Min
Max
Min
Max
Units
Notes
PxPCLKO[6:0] to Signal Valid
Delay-bused signals
0.7
0.7
0
3.8
0.7
0.7
0
3.8
ns
1, 2, 3,
10, 11
Tval(ptp)
Ton
PxPCLKO[6:0] to Signal Valid
Delay-point to point signals
3.8
7
3.8
7
ns
ns
1, 2, 3,
10, 11
Float to Active Delay
1, 7, 10,
11
Toff
Tsu
Active to Float Delay
ns
ns
1, 7, 11
3, 4, 8
Input Setup Time to
PxPCLKO[6:0]-Bused signals
1.2
1.2
0.5
1
1.7
1.7
0.5
1
Tsu(ptp)
Th
Input Setup Time to
PxPCLKO[6:0]-point to point
ns
ns
3, 4
4
Input Hold Time from
PxPCLKO[6:0]
Trst
Reset Active Time after power
stable
ms
µs
5
Trst-clk
Reset Active Time after
PxPCLKO[6:0] stable
100
100
5
Trst-off
Trrsu
Reset Active to output float delay
40
50
40
50
ns
ns
5, 6
PxREQ64# to RSTIN# setup
time
10
10
Trrh
RSTIN# to PxREQ64# hold Time
0
0
ns
Trhfa
RSTIN# high to first configuration
access
227
227
clocks
Trhff
RSTIN# high to first PxFRAME#
Assertion
5
5
clocks
Tpvrh
Tprsu
Power valid to RSTIN# high
100
10
100
10
ms
PCI-X initialization pattern to
RSTIN# setup time
clocks
Tprh
RSTIN# to PCI-X initialization
pattern hold time
0
0
50
0
0
50
ns
ns
9
Trlcx
Delay from RSTIN# low to
PxPCLKO[6:0] frequency change
NOTES:
1. Refer to Figure 20. For timing and measurement condition details, refer to the PCI-X Addendum to the
PCI Local Bus Specification document.
2. Minimum times are measured at the package pin (not the test point).
Intel® 82870P2 P64H2 Datasheet
193
Electrical Characteristics
R
3. Setup time for point-to-point signals applies to PxREQ[5:0]# and PxGNT[5:0]# only. All other signals are
bused.
4. See the timing measurement conditions in Figure 21.
5. RST# is asserted and deasserted asynchronously with respect to PxPCLKO[6:0].
6. All output drivers must be floated when RSTIN# is active.
7. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification
8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals
at the same time.
9. Maximum value is also limited by delay to the first transaction (Trhfa). The PCI-X initialization pattern
control signals after the rising edge of RSTIN# must be deasserted no later than two clocks before the
first PxFRAME# and must be floated no later than one clock before PxFRAME# is asserted.
10. A PCI-X device is permitted to have the minimum values shown for Tval, Tval(ptp) ,and Ton only in PCI-X
mode. In conventional mode, the device must meet the requirements specified in the PCI Local Bus
Specification, Revision 2.2 for the appropriate clock frequency.
11. Device must meet this specification independent of how many outputs switch simultaneously.
Figure 20. PCI-X Output Timing
Vth
Vtl
PxPCLKO[6:0]
Vtest
Tval
Output
Delay
Vtfall
Tval
Vtrise
Output
Delay
Tri-State
Output
Ton
Toff
Time_PCIX-out-measCond
Figure 21. PCI-X Input Timing
Vth
Vtl
PxPCLKO[6:0]
Vtest
Tsu
Th
V_th
V_tl
inputs
valid
Vtest
Vtest
Vmax
Input
Time_PCIX-in-measCond
194
Intel® 82870P2 P64H2 Datasheet
Electrical Characteristics
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5.2.2.1
PCI-X Clock Characteristics
Clock measurement conditions are the same for PCI-X devices as for conventional PCI devices in
a 3.3 V signaling environment except for voltage levels specified in Table 81.
The same spread-spectrum clocking techniques are allowed in PCI-X as for 66 MHz conventional
PCI. If a device includes a PLL, that PLL must track the input variations of spread-spectrum
clocking specified in Table 81.
Figure 22. PCI-X 3.3 V Clock Waveform
Tcyc
Thigh
0.6 Vcc
Tlow
0.5 Vcc
0.4 Vcc
0.3 Vcc
0.4 Vcc, p-to-p
(minimum)
0.2 Vcc
Time_PCIX-3_3VClock
Table 81. PCI-X Clock Timings (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%, Tcase=0qC to 105qC)
PCI-X 133
PCI-X 66
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
Tcyc
Thigh
Tlow
—
PxPCLKO[6:0] cycle time
PxPCLKO[6:0] high time
PxPCLKO[6:0] low time
PxPCLKO[6:0] slew rate
7.5
3
20
15
6
30
ns
ns
1, 3, 4
3
6
ns
1.5
4
1.5
4
V/ns
2, 4
Spread Spectrum Requirements
fmod
Modulation frequency
Frequency spread
30
-1
33
0
30
-1
33
0
kHz
%
fspread
NOTES:
1. For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum
limits except while RSTIN# is asserted.
2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown
in Figure 23.
3. The minimum clock period must not be violated for any single clock cycle (i.e., accounting for all system
jitter).
4. All PCI-X 133 devices must also be capable of operating in PCI-X 66. All PCI-X devices must be
capable of operating in conventional PCI 33 mode and optionally are capable of conventional PCI 66
mode.
Intel® 82870P2 P64H2 Datasheet
195
Electrical Characteristics
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5.2.2.2
PCI-X Clock Uncertainty
The maximum allowable clock uncertainty including jitter is shown in Table 82 and Figure 23.
This specification applies, not only at a single threshold point, but also at all points on the clock
edge between VIL and VIH. For add-in cards, the maximum skew is measured between component
pins not between connectors.
Table 82. PCI-X Clock Uncertainty Parameters (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0qC to 105qC)
Symbol
PCI-X
Conventional
PCI 66 (ref)
3.3 V Signaling Conventional
PCI 33 (ref)
Units
Vtest-clk
Tskew
0.4VCC
0.4VCC
0.4VCC
V
0.4 (max)
0.8 (max)
1.6 (max)
ns
Figure 23. PCI-X Clock Skew
Vih
Vil
Clock @ Device 1
Vtest
Tskew
Tskew
Tskew
Vih
Vil
Clock @ Device 2
Vtest
PCIX_clk_uncertainty
196
Intel® 82870P2 P64H2 Datasheet
Electrical Characteristics
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5.2.2.3
P64H2 Clock Timings
1.8V to CLK66 Sequencing Requirement –
1.8V needs to be valid before CLK66 begins to toggle. This can be guaranteed by gating the
CK408 clocks using a power good signal from the 1.8V regulator. Current designs will need to
implement the BIOS workaround defined in the P64H2 BIOS Spec Update. New board designs
should adhere to the hardware power sequencing requirement outlined in the next version of the
Intel Xeon Processor with 512K L2 Cache and Intel E7500 and Intel E7501 Chipset Compatible
Platform Design Guide v1.9 and the Intel Xeon Processor with 512 KB L2 Cache and Intel E7500
Chipset Platform Design Guide Update v1.1.
Failure to meet these requirements may result in:
•
•
•
•
The PLL not locking
Erratic behavior of PCI/PCI-X output clocks (i.e. runt pulses, multiple pulses)
Reads to the P64H2 and PCI/PCI-X failing
PCI/PCI-X cards not enumerating correctly
Failure to meet this requirement will NOT result in data corruption or an unreliable system. If this
issue is encountered, the system will fail to boot.
Table 83. P64H2 Clock Timings (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%, Tcase=0qC to 105qC)
Symbol
CLK66
Parameter
Min
Max
Units
Notes
Tperiod
Thigh
Tlow
Trise
Tfall
CLK period
15.0
4.95
4.55
0.5
15.3
N/A
N/A
2.0
ns
ns
1,2
CLK high time
CLK low time
CLK rise time
CLK fall time
3
4
5
5
5
5
ns
ns
0.5
2.0
ns
—
Rising edge rate
Falling edge rate
1.0
4.0
V/ns
V/ns
—
1.0
4.0
CLK200
Tperiod
Trise
Tfall
—
Average Period
5.0
300
300
5.2
600
600
20%
0.76
200
55
ns
ps
ps
6
Rise time across 600 mV
Fall time across 600 mV
Rise/Fall Matching
7,8
7,8
7,9
—
Cross point at 1 V
0.51
45
V
ps
%
Tccjitter
—
Cycle to Cycle jitter
Duty Cycle
—
Maximum voltage allowed at input
Minimum voltage allowed at input
1.45
-200
V
—
mV
Intel® 82870P2 P64H2 Datasheet
197
Electrical Characteristics
R
Symbol
Parameter
Rising edge ringback
Min
Max
Units
Notes
TVring_rise
0.85
V
V
TVring_fall
Falling edge ring back
0.35
CLK100
Tperiod
Trise
Tfall
—
Average Period
10.0
300
300
10.2
600
600
20%
0.76
200
55
ns
ps
ps
6
Rise time across 600 mV
Fall time across 600 mV
Rise/Fall Matching
7,8
7,8
7,9
—
Cross point at 1 V
0.51
45
V
ps
%
V
Tccjitter
—
Cycle to Cycle jitter
Duty Cycle
—
Maximum voltage allowed at input
Minimum voltage allowed at input
Rising edge ringback
Falling edge ring back
1.45
-200
—
mV
V
—
0.85
—
0.35
V
198
Intel® 82870P2 P64H2 Datasheet
Electrical Characteristics
R
Symbol
CLK133
Parameter
Min
Max
Units
Notes
Tperiod
Trise
Tfall
—
Average Period
7.5
300
300
7.65
600
600
20%
0.76
200
55
ns
ps
ps
6
Rise time across 600 mV
Fall time across 600 mV
Rise/Fall Matching
7,8
7,8
7,9
—
Cross point at 1V
0.51
45
V
ps
%
V
Tccjitter
—
Cycle to Cycle jitter
Duty Cycle
—
Maximum voltage allowed at input
Minimum voltage allowed at input
Rising edge ringback
Falling edge ring back
1.45
-200
—
mV
V
—
0.85
—
0.35
V
CLK33
Tperiod
Thigh
Tlow
—
CLK period
30.0
12.0
12.0
1.0
N/A
N/A
N/A
4.0
4.0
2.0
2.0
ns
ns
1,2
3
CLK high time
CLK low time
Rising edge rate
Falling edge rate
CLK rise time
CLK fall time
ns
4
V/ns
V/ns
ns
5
—
1.0
5
Trise
0.5
5
Tfall
0.5
ns
5
APICCLK
fioap
Thigh
Tlow
Trise
Tfall
Operation Frequency
High time
14.32
12
33.33
36
MHz
ns
Low time
12
36
ns
Rise time
1.0
1.0
5.0
5.0
ns
Fall time
ns
NOTES:
1. Period, jitter, offset and skew measured on rising edge @ 1.5 V for 3.3 V clocks.
2. The average period over any 1 us period of time must be greater than the minimum specified period.
3. Thigh is measured at 2.4 V for non-host outputs.
4. Tlow is measured at 0.4 V for all outputs.
5. For 3.3 V clocks Trise and Tfall are measured as a transition through the threshold region Vol = 0.4 V and
Voh = 2.4 V (1 mA) JEDEC Specification.
6. Measured at crossing point.
7. Measured from Vol = 0.2 V to Voh = 0.8 V.
8. Still simulating to determine [0.2–0.8 V] or [0.3–0.9 V].
9. Determined as a fraction of 2*(Trise – Tfall) / (Trise + Tfall).
Intel® 82870P2 P64H2 Datasheet
199
Electrical Characteristics
R
5.2.2.4
Spread Spectrum Clocking
Spread spectrum clocking can be used on the P64H2 to reduce energy. Spread Spectrum clocking
is a common technique used by system designers to meet FCC emissions, where the frequency is
deliberately shifted around to spread the energy off of the peak. The following is to be observed
when using Spread Spectrum clocking:
1. All device timings (including jitter, skew, min/max clock period, output rise/fall time) MUST
meet the existing non-spread spectrum specifications.
2. All non-spread Host and PCI functionality must be maintained in the spread spectrum mode
(includes all power management functions).
3. The minimum clock period cannot be violated. The preferred method is to adjust the spread
technique to not allow for modulation above the nominal frequency. This technique is often
called “down-spreading”. The modulation profile in a modulation period can be expressed as:
1
(1 − δ ) fnom + 2 fm
(1 + δ ) fnom − 2 fm
δ
fnom
fnom
t
when 0 < t <
;
2 fm
f =
1
1
δ
t
when
< t <
,
2 fm
fm
where:
fnom is the nominal frequency in the non-SSC mode
fm is the modulation frequency
fm is the modulation amount
t is time.
200
Intel® 82870P2 P64H2 Datasheet
Ballout and Package Information
R
6 Ballout and Package Information
This section provides ballout and package information. Figure 24 and Figure 25 provide graphical
illustrations of how the signals map to the ballout on the package. Table 84 provides the ball list
arranged alphabetically by signal name. Section 6.1 provides the package dimensions and Section
6.1.1 provides the package trace lengths.
Intel® 82870P2 P64H2 Datasheet
201
Ballout and Package Information
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Figure 24. Intel® P64H2 Ballout (Left Side)
24
23
22
21
20
19
18
17
PAAD49
PAAD48
VSS
16
15
PAAD41
VSS
14
PAAD36
PAAD35
VSS
13
AD
AC
AB
AA
Y
VCC5REF
VSS
PAAD05
PAAD04
VSS
VSS
PACBE6#
VSS
PAAD62
PAAD61
VSS
VSS
PAAD53
VSS
VSS
PAAD00
PAAD57
PAAD56
VSS
PAAD45
PAAD44
VSS
PBAD31
PBAD30
VSS
PAAD08
PACBE0#
VSS
PAACK64# PACBE5#
PAAD52
PAAD51
VSS
PAAD40
PAAD39
VSS
PAAD03
PAAD02
VSS
VSS
PAREQ64#
PACBE7#
VSS
PACBE4#
VSS
PAAD60
PAAD59
VSS
PAAD47
PAAD46
VCC3.3
PAPCLKI
VCC3.3
VCC3.3
VSS
PAAD34
PAAD33
VCC3.3
PAAD32
VSS
PAAD55
PAAD54
VCC3.3
PAAD09
PAAD13
VCC3.3
PAAD43
PAAD42
VCC3.3
VCC3.3
VCC3.3
VSS
PBAD29
PBAD28
VCC3.3
VCC3.3
VCC3.3
VSS
W
V
PAAD07
PAAD06
VSS
PAPAR64
PAAD63
VSS
PAAD50
VCC1.8
VCC3.3
PAAD12
PAPAR
PAAD38
PAAD37
VSS
PAAD01
PAAD11
VSS
PAAD58
PAM66EN
VSS
U
PAAD10
PAAD15
VSS
T
PACBE1#
PAAD14
VSS
VSS
R
PASTOP# PAPLOCK#
PAPERR# PASERR#
VCC1.8
VCC1.8
VSS
VCC1.8
VCC1.8
VSS
P
VSS
PAIRDY# PAPCIXCAP
VSS
PATRDY# PADEVSEL#
VCC3.3
PAFRAME#
PAAD18
VCC3.3
PAAD25
PAAD30
VCC3.3
PAREQ0#
PAGNT2#
BPCLK133
SDATA
VSS
VSS
VSS
N
VSS
PAAD21
PAAD24
VSS
PAAD17
VSS
PAAD16
PAAD20
VSS
VSS
PAAD19
PAAD23
VSS
PACBE2#
VCC3.3
PAAD22
PAAD26
VCC3.3
VCC3.3
VCC3.3
VSS
VCC3.3
VCC3.3
VSS
VCC1.8
VCC1.8
VSS
M
L
VSS
VSS
VSS
PACBE3#
PAAD28
VSS
VCC1.8
VCC1.8
VSS
VCC1.8
VCC1.8
VSS
K
PAAD29
PAAD27
VSS
VSS
VSS
J
PAPCLKO2 PAPCLKO1
PAPCLKO0 PAAD31
VCC3.3
VCC3.3
VCC1.8
Reserved
VSS
VCC3.3
VCC3.3
VCC1.8
VCC1.8
HI_21
VSS
VCC1.8
VCC1.8
HI_17
VCC1.8
VSS
H
VSS
PAPCLKO6 PAPCLKO5
VSS
PAPCLKO4 PAPCLKO3
VSS
VSS
G
F
PAREQ2#
PAREQ5#
VSS
PAGNT1#
VSS
PAREQ1#
VSS
PAGNT0#
PAREQ3#
BPCLK100
VCC1.8
VCC1.8
VSS
VCC1.8
VSS
PAGNT4#
PAREQ4# PAGNT3#
PWROK RSTIN#
E
PAPCIRST# PA133EN
HPB_SIL# HPB_SLOT2
PAGNT5#
VSS
PUSTRBF
VSS
D
HPA_SID HPA_SLOT2 HPA_SOL
HPA_SIL# HPA_SLOT1 HPA_SOLR
RASERR#
VSS
HI_13
VSS
HI_10
VSS
C
HPB_SOD HPB_SLOT1 HPB_SOL
SCLK
HI_15
VSS
PUSTRBS
VSS
B
HPB_SID HPB_SLOT0 HPB_SOLR HPA_SIC
VSS
HPA_SOD
HPA_SOR#
TEST#
VSS
HI_12
VSS
HI_9
A
HPB_SOC
HPB_SIC HPB_SORR# HPB_SOR# HPA_SLOT0 HPA_SOC HPA_SORR#
23 22 21 20 19 18
HI_14
16
HI_11
14
VSS
24
17
15
13
202
Intel® 82870P2 P64H2 Datasheet
Ballout and Package Information
R
Figure 25. Intel® P64H2 Ballout (Right Side)
12
11
PBCBE3#
PBAD23
VSS
10
VSS
9
PBCBE2#
VSS
8
7
6
5
4
3
2
1
PBTRDY#
VSS
PBAD15
VSS
PBAD10
PBM66EN
VSS
VSS
PBAD03
VSS
PBREQ64#
PBCBE7#
VSS
VSS
AD
AC
AB
AA
Y
VSS
PBAD27
PBAD26
VSS
PBAD19
PBAD18
VSS
PBDEVSEL# PBCBE1#
PBAD07
PBAD06
VSS
PBPAR64
PBAD63
VSS
PBFRAME#
PBIRDY#
VSS
VSS
PBSTOP#
PBPLOCK#
VCC3.3
PBPCLKI
VCC3.3
VCC3.3
VSS
PBPAR
VSS
PBAD14
PBAD13
VSS
PBAD02
PBAD01
VSS
PBAD22
PBAD21
VCC3.3
PBAD20
VSS
PBAD09
PBAD08
VSS
PBCBE6#
PBCBE5#
VSS
PBAD17
PBAD16
VCC3.3
VSS
PBPERR#
PBSERR#
VCC3.3
PBAD05
PBAD04
VSS
PBAD62
PBAD61
VSS
PBAD25
PBAD24
VCC3.3
VCC3.3
VSS
PBPCIXCAP
VCC1.8
VCC3.3
VCC3.3
VSS
PBAD12
PBAD11
VCC3.3
PBAD52
PBAD47
VCC3.3
PBAD39
PBAD34
VCC3.3
PBAD00
PBACK64#
VSS
W
V
PBCBE0#
PBAD57
VSS
PBCBE4#
PBAD59
VSS
PBAD56
PBAD51
VCC3.3
PBAD58
PBAD53
VSS
PBAD60
PBAD55
VSS
U
VSS
VSS
PBAD54
PBAD49
VSS
T
VCC1.8
VCC1.8
VSS
VCC1.8
VCC1.8
VSS
PBAD48
PBAD43
VSS
PBAD50
PBAD45
VSS
R
VSS
VSS
VSS
PBAD42
PBAD38
VCC3.3
PBAD44
PBAD40
VSS
PBAD46
P
VCC1.8
VCC1.8
VSS
VCC3.3
VCC3.3
VSS
VCC3.3
VCC3.3
VSS
PBAD41
PBAD36
VSS
N
VSS
VSS
PBAD35
PBAD37
PBAD32
VSS
M
L
VCC1.8
VCC1.8
VSS
VCC1.8
VCC1.8
VSS
PBPCLKO2
PBPCLKO1 PBPCLKO0
VSS
PBREQ2# PBGNT1#
PBGNT4# PBREQ4# PBGNT3#
PBAD33
PBPCLKO3
VSS
VSS
VSS
VSS
PBREQ0# PBPCLKO6
PBPCLKO5 PBPCLKO4
VSS PBREQ1#
K
VCC1.8
VCC1.8
HI_18
VCC1.8
HI_8
VCC3.3
VCC3.3
VCC1.8
HI_RCOMP
VSS
VCC3.3
VCC3.3
HI_19
VCC1.8
HI_2
VCC1.8
CLK66
VCC1.8
CLK200#
VSS
PBGNT0#
PBREQ3#
J
VSS
VSS
PB133EN
CLK200
PAIRQ7
PAIRQ6
PAIRQ5
PAIRQ4
PAIRQ3
PAIRQ2
6
PBGNT2#
H
HI_16
HI_VREF
VSS
HI_VSWING
VCC1.8
HI_5
VSS
PBGNT5# PBREQ5# PBPCIRST# VCC5REF
G
F
PAIRQ13
PAIRQ12
PAIRQ11
PAIRQ10
PAIRQ9
PAIRQ8
5
PAIRQ15
PAIRQ14
VSS
PBIRQ4
PBIRQ3
PBIRQ2
PBIRQ1
PBIRQ0
APICCLK
3
PBIRQ10
PBIRQ9
PBIRQ8
PBIRQ7
PBIRQ6
PBIRQ5
2
PBIRQ15
PBIRQ14
PBIRQ13
PBIRQ12
PBIRQ11
E
VSS
HI_7
VSS
HI_4
VSS
PAIRQ1
VSS
D
HI_20
VSS
VSS
PSTRBF
VSS
VSS
HI_1
BTINTR#
APICD1
APICD0
4
C
HI_6
HI_3
VSS
PAIRQ0
VSS
B
PSTRBS
10
VSS
HI_0
A
12
11
9
8
7
1
Intel® 82870P2 P64H2 Datasheet
203
Ballout and Package Information
R
Table 84. Intel® P64H2 Ballout Listed Alphabetically by Signal Name
Signal
Ball #
Signal
Ball #
Signal
Ball #
APICCLK
APICD0
APICD1
BPCLK100
BPCLK133
BTINTR#
CLK200
CLK200#
CLK66
HI_0
A3
A4
HI_VREF
HI_VSWING
HPA_SIC
F11
G10
B21
D21
C21
A20
C20
D20
A19
B19
D19
C19
B18
A18
A23
B24
D24
B23
C23
D23
A24
C24
C22
B22
A21
A22
E23
AB22
AC22
V23
Y23
AA23
PAAD4
PAAD5
AC23
AD23
V24
W24
AB24
U19
U22
U23
T18
B4
PAAD6
E19
E18
C4
HPA_SID
PAAD7
HPA_SIL#
HPA_SLOT0
HPA_SLOT1
HPA_SLOT2
HPA_SOC
HPA_SOD
HPA_SOL
HPA_SOLR
HPA_SOR#
HPA_SORR#
HPB_SIC
PAAD8
PAAD9
G6
PAAD10
PAAD11
PAAD12
PAAD13
PAAD14
PAAD15
PAAD16
PAAD17
PAAD18
PAAD19
PAAD20
PAAD21
PAAD22
PAAD23
PAAD24
PAAD25
PAAD26
PAAD27
PAAD28
PAAD29
PAAD30
PAAD31
PAAD32
PAAD33
PAAD34
PAAD35
F7
H7
A8
T19
HI_1
C8
T21
HI_2
E8
T22
HI_3
B9
N21
N22
M18
M20
M21
M23
L19
HI_4
D9
HI_5
E10
B11
D11
E12
B13
D13
A14
B15
D15
A16
C16
G11
G13
G12
G8
HI_6
HPB_SID
HI_7
HPB_SIL#
HPB_SLOT0
HPB_SLOT1
HPB_SLOT2
HPB_SOC
HPB_SOD
HPB_SOL
HPB_SOLR
HPB_SOR#
HPB_SORR#
PA133EN
HI_8
HI_9
HI_10
L20
HI_11
L23
HI_12
K18
K19
K21
K22
K24
J18
HI_13
HI_14
HI_15
HI_16
HI_17
HI_18
PAACK64#
PAAD0
J20
HI_19
V14
Y14
AA14
AC14
HI_20
C12
E16
F9
PAAD1
HI_21
PAAD2
HI_RCOMP
PAAD3
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Intel® 82870P2 P64H2 Datasheet
Ballout and Package Information
R
Signal
Ball #
Signal
Ball #
Signal
Ball #
PAAD36
PAAD37
PAAD38
PAAD39
PAAD40
PAAD41
PAAD42
PAAD43
PAAD44
PAAD45
PAAD46
PAAD47
PAAD48
PAAD49
PAAD50
PAAD51
PAAD52
PAAD53
PAAD54
PAAD55
PAAD56
PAAD57
PAAD58
PAAD59
PAAD60
PAAD61
PAAD62
PAAD63
PACBE0#
PACBE1#
PACBE2#
PACBE3#
PACBE4#
AD14
V15
PACBE5#
PACBE6#
PACBE7#
PADEVSEL#
PAFRAME#
PAGNT0#
PAGNT1#
PAGNT2#
PAGNT3#
PAGNT4#
PAGNT5#
PAIRDY#
PAIRQ0
AB21
AD21
W22
P19
N18
G19
G22
F18
F20
F23
E22
P23
B7
PAPCLKI
PAPCLKO0
PAPCLKO1
PAPCLKO2
PAPCLKO3
PAPCLKO4
PAPCLKO5
PAPCLKO6
PAPERR#
PAPLOCK#
PAREQ0#
PAREQ1#
PAREQ2#
PAREQ3#
PAREQ4#
PAREQ5#
PAREQ64#
PASERR#
PASTOP#
PATRDY#
PB133EN
PBACK64#
PBAD0
V17
J21
J23
J24
H19
H20
H22
H23
R21
R23
G18
G21
G24
F19
F21
F24
Y22
R20
R24
P20
H6
W15
AA15
AB15
AD15
W16
Y16
AB16
AC16
Y17
AA17
AC17
AD17
W18
AA18
AB18
AD18
W19
Y19
PAIRQ1
D7
PAIRQ10
PAIRQ11
PAIRQ12
PAIRQ13
PAIRQ14
PAIRQ15
PAIRQ2
C5
D5
E5
F5
E4
F4
AB19
AC19
V20
A6
PAIRQ3
B6
V3
PAIRQ4
C6
W3
Y20
PAIRQ5
D6
PBAD1
AA3
AB3
AD3
W4
AA20
AC20
AD20
V21
PAIRQ6
E6
PBAD2
PAIRQ7
F6
PBAD3
PAIRQ8
A5
PBAD4
PAIRQ9
B5
PBAD5
Y4
AA24
T24
PAM66EN
PAPAR
U20
R18
W21
E24
P22
PBAD6
AB4
AC4
Y5
PBAD7
N19
PAPAR64
PAPCIRST#
PAPCIXCAP
PBAD8
L22
PBAD9
AA5
AD5
AA21
PBAD10
Intel® 82870P2 P64H2 Datasheet
205
Ballout and Package Information
R
Signal
Ball #
Signal
Ball #
Signal
Ball #
PBAD11
PBAD12
PBAD13
PBAD14
PBAD15
PBAD16
PBAD17
PBAD18
PBAD19
PBAD20
PBAD21
PBAD22
PBAD23
PBAD24
PBAD25
PBAD26
PBAD27
PBAD28
PBAD29
PBAD30
PBAD31
PBAD32
PBAD33
PBAD34
PBAD35
PBAD36
PBAD37
PBAD38
PBAD39
PBAD40
PBAD41
PBAD42
PBAD43
PBAD44
V6
W6
PBAD45
PBAD46
P2
P1
PBGNT5#
PBIRDY#
PBIRQ0
G4
AA9
B3
C3
F2
AA6
AB6
AD6
W10
Y10
AB10
AC10
V11
Y11
AA11
AC11
V12
W12
AA12
AB12
W13
Y13
AB13
AC13
L2
PBAD47
R6
PBAD48
R5
PBIRQ1
PBAD49
R3
PBIRQ10
PBIRQ11
PBIRQ12
PBIRQ13
PBIRQ14
PBIRQ15
PBIRQ2
PBAD50
R2
B1
C1
D1
E1
F1
PBAD51
T7
PBAD52
T6
PBAD53
T4
PBAD54
T3
PBAD55
T1
D3
E3
F3
PBAD56
U7
PBIRQ3
PBAD57
U5
PBIRQ4
PBAD58
U4
PBIRQ5
A2
B2
C2
D2
E2
Y8
AC5
AB7
AC1
G2
W9
V8
L4
PBAD59
U2
PBIRQ6
PBAD60
U1
PBIRQ7
PBAD61
W1
Y1
PBIRQ8
PBAD62
PBIRQ9
PBAD63
AB1
V5
PBLOCK#
PBM66EN
PBPAR
PBCBE0#
PBCBE1#
PBCBE2#
PBCBE3#
PBCBE4#
PBCBE5#
PBCBE6#
PBCBE7#
PBDEVSEL#
PBFRAME#
PBGNT0#
PBGNT1#
PBGNT2#
PBGNT3#
PBGNT4#
AC7
AD9
AD11
V2
PBPAR64
PBPCIRST#
PBPCIXCAP
PBPCLKI
PBPCLKO0
PBPCLKO1
PBPCLKO2
PBPCLKO3
PBPCLKO4
PBPCLKO5
PBPCLKO6
PBPERR#
PBREQ0#
L1
M6
M5
Y2
M3
AA2
AC2
AC8
AB9
J2
M2
L5
N7
L7
N6
K1
K3
K4
K6
Y7
K7
N4
N3
J5
P7
H1
P5
H3
P4
H5
206
Intel® 82870P2 P64H2 Datasheet
Ballout and Package Information
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Signal
Ball #
Signal
Ball #
Signal
Ball #
PBREQ1#
PBREQ2#
PBREQ3#
PBREQ4#
PBREQ5#
PBREQ64#
PBSERR#
PBSTOP#
PBTRDY#
PSTRBF
PSTRBS
PUSTRBF
PUSTRBS
PWROK
RASERR#
RSTIN#
SCLK
J3
VCC
VCC
N13
P10
P11
P14
P15
R10
R11
R14
R15
V9
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
J16
J17
J19
L6
J6
H2
VCC
H4
VCC
G3
VCC
L18
M7
AD2
W7
AA8
AD8
C10
A10
E14
C14
E21
D17
E20
C18
D18
B17
F17
G17
J7
VCC
VCC
M8
VCC
M9
VCC
M16
M17
M19
N8
VCC
VCC
V18
F8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
F10
F12
F13
F15
F16
G7
N9
N16
N17
P6
P18
R7
SDATA
TEST#
TP0
G9
R19
T8
G14
G15
G16
H12
H13
J12
J13
H8
VCC
T9
VCC
T12
T13
T16
T17
U6
VCC
K10
K11
K14
K15
L10
L11
L14
L15
M12
M13
N12
VCC
VCC
VCC
VCC
U8
VCC
H9
U9
VCC
H16
H17
H18
J8
U12
U13
U16
U17
U18
VCC
VCC
VCC
VCC
J9
Intel® 82870P2 P64H2 Datasheet
207
Ballout and Package Information
R
Signal
Ball #
Signal
Ball #
Signal
Ball #
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC5REF
VCC5REF
VSS
V7
V10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AC9
AC12
AC15
AC18
AC21
AC24
AD1
AD4
AD7
AD10
AD16
AD19
AD22
B8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E11
E13
E15
E17
F14
F22
G5
V13
V16
V19
W8
W11
W14
W17
AD24
G1
G20
G23
H10
H11
H14
H15
H21
H24
J1
A7
VSS
A9
VSS
A13
VSS
A15
B10
B12
B14
B16
B20
C7
VSS
A17
VSS
AA1
AA4
AA7
AA10
AA13
AA16
AA19
AA22
AB2
AB5
AB8
AB11
AB14
AB17
AB20
AB23
AC3
AC6
J4
VSS
J10
J11
J14
J15
J22
K2
VSS
VSS
VSS
C9
VSS
C11
C13
C15
C17
D4
VSS
VSS
K5
VSS
K8
VSS
K9
VSS
D8
K12
K13
K16
K17
K20
K23
L3
VSS
D10
D12
D14
D16
D22
E7
VSS
VSS
VSS
VSS
VSS
VSS
E9
L8
208
Intel® 82870P2 P64H2 Datasheet
Ballout and Package Information
R
Signal
Ball #
Signal
Ball #
Signal
Ball #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L9
L12
L13
L16
L17
L21
L24
M4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P9
P12
P13
P16
P17
P21
P24
R1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T23
U3
U10
U11
U14
U15
U21
U24
V1
M10
M11
M14
M15
M22
N2
R4
R8
V4
R9
V22
W2
W5
W20
W23
Y3
R12
R13
R16
R17
R22
T2
N5
N10
N11
N14
N15
N20
N23
P3
Y6
T5
Y9
T10
T11
T14
T15
T20
Y12
Y15
Y18
Y21
Y24
P8
Intel® 82870P2 P64H2 Datasheet
209
Ballout and Package Information
R
6.1
Package Information
The 567-ball FCBGA package dimensions for the P64H2 are shown in Figure 26, Figure 27, and
Figure 28. For thermal solutions, refer to the Intel® 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2)
Thermal and Mechanical Design Guidelines.
Figure 26. 567-Ball FCBGA Package Dimensions (Top View)
Handling
Exclusion
Area
Die
Keepout
Area
0.550 in.
0.350 in.
Intel®
P64H2
Die
21.00 mm
17.00 mm
0.550 in.
0.350 in.
31.00 mm
17.00 mm
21.00 mm
31.00 mm
Pkg_567-Ball_Top
NOTE: Dimensions in millimeters and inches.
210
Intel® 82870P2 P64H2 Datasheet
Ballout and Package Information
R
Figure 27. 567-Ball FCBGA Package Dimensions (Bottom View)
AD
AC
AB
AA
Y
W
V
U
T
31.000 ±0.100
- A -
R
P
N
4X 0.635
M
L
K
J
4X 15.500
H
G
F
E
D
C
B
23X 1.270
+
1
+
2
A
4
8
10
12
14
16
18
22
24
6
20
17
15
5
7
11
13
3
9
19
23
21
23X 1.270
8X 14.605
(0.895)
29.2100
31.00 ±0.100
0.200
- B -
A
Pkg_567-Ball_Bot
NOTE: Dimensions in millimeters.
Intel® 82870P2 P64H2 Datasheet
211
Ballout and Package Information
R
Figure 28. 567-Ball FCBGA Solder Balls Detail
Detail
J
Scale 5:1
0.74 + 0.025
0.100 + 0.025
DIE SOLDER
BUMPS
H
UNDERFILL
EPOXY
FC BGA Substrate
Detail
H
Scale 5:1
1.100 + 0.100
0.600 + 0.100
DIE
J
BGA Solder Balls
1.940 + 0.150
Pkg_FCBGA_Solderballs
NOTE: Dimensions in millimeters.
212
Intel® 82870P2 P64H2 Datasheet
Ballout and Package Information
R
6.1.1
Package Trace Lengths for Hub Interface
Table 85. Intel® P64H2 Hub Interface Package Trace Lengths
Signal
Intel® P64H2 Ball
Length (inches)
HI_0
HI_1
A8
C8
0.532
0.453
0.392
0.487
0.367
0.307
0.442
0.321
0.270
0.420
0.300
0.476
0.450
0.331
0.501
0.416
0.171
0.161
0.148
0.251
0.367
0.297
0.564
0.408
0.366
0.273
HI_2
E8
HI_3
B9
HI_4
D9
HI_5
E10
B11
D11
E12
B13
D13
A14
B15
D15
A16
C16
G11
G13
G12
G8
HI_6
HI_7
HI_8
HI_9
HI_10
HI_11
HI_12
HI_13
HI_14
HI_15
HI_16
HI_17
HI_18
HI_19
HI_20
HI_21
PSTRB1
PSTRB0
PSTRB1#
PSTRB0#
C12
E16
A10
C10
C14
E14
NOTE: Package trace lengths are measured from pad-to-pin.
Intel® 82870P2 P64H2 Datasheet
213
Ballout and Package Information
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214
Intel® 82870P2 P64H2 Datasheet
Testability
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7 Testability
The P64H2 supports an XOR Chain test mode.
7.1
XOR Power Up Strap
Table 86. XOR Power Up Strap (Sampled during RESET)
Pin
Description
PAIRQ12
XOR Test mode is activated if strap is pulled up to 3.3 V.
7.2
XOR Test Chain Test
This is the XOR Chain test mode. This test mode is used to check the connectivity of the pins and
to measure the VIH and VIL of the pins. The pins on the P64H2 have been divided into six XOR
chains. Table 87 shows the arrangement of these pins from first to last for every chain. This means
that the enables of the buffers are turned off so that the pins can be exercised to verify the XOR
chains.
Table 87. XOR Chain Table (Chains 1–6)
Chain#1
PBC/BE6#
Chain#2
PBPCLKO2
Chain#3
HI_19
Chain#4
Chain#5
PAAD29
Chain#6
PAAD62
HPA_SOC
HPA_SORR#
HPA_SOR#
HPA_SOD
RASERR#
HPB_SOR#
HPA_SLOT0
SCLK
PBAD56
PBAD0
PBGNT3#
PBPCLKO6
PBPCIRST#
PBREQ0#
PBREQ5#
PBGNT1#
PBREQ4#
PBGNT4#
PBREQ2#
PBGNT5#
PB_133EN
PBIRQ10
PBIRQ15
PBIRQ4
HI_RCOMP
HI_16
HI_2
PAFRAME#
PAAD21
PAAD44
PAAD48
PAAD53
PAAD39
PAAD49
PAAD32
PAAD41
PAAD45
PAAD40
PAAD35
PAAD33
PAAD34
PAAD36
PBAD31
PBAD4
PAAD24
PBAD12
PBC/BE5#
PBAD11
PBACK64#
PBAD62
PBC/BE0#
PBAD61
PBAD51
PBC/BE4#
PBAD58
PBAD52
HI_4
PAC/BE2#
PAAD17
HI_5
HI_1
PAAD16
HI_18
HI_0
PAPCIXCAP
PAIRDY#
PATRDY#
PASTOP#
PADEVSEL#
PAC/BE1#
PAPLOCK#
PAPERR#
HPA_SIC
SDTA
PSTRBS
HI_7
HPA_SIL#
HPB_SORR#
HPA_SOLR
HPA_SLOT1
TP0
PSTRBF
HI_3
HI_16
HI_6
Intel® 82870P2 P64H2 Datasheet
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Testability
R
Chain#1
PBAD59
Chain#2
PBIRQ14
Chain#3
HI_8
Chain#4
Chain#5
PAAD15
Chain#6
HPB_SLOT0
HPA_SOL
HPB_SLOT1
HPA_SLOT2
HPB_SLOT2
HPA_SID
PBC/BE3#
PBAD28
PBAD19
PBAD23
PBAD29
PBC/BE2#
PBAD30
PBTRDY#
PBAD18
PBAD27
PBFRAME#
PBAD26
PBC/BE1#
PBDEVSEL#
PBAD24
PBAD15
PBAD25
PBPAR
PBAD57
PBAD60
PBAD53
PBAD47
PBAD54
PBAD48
PBAD49
PBAD55
PBAD42
PBAD50
PBAD43
PBAD45
PBAD46
PBAD44
PBAD41
PBAD40
PBAD37
PBAD36
PBAD39
PBAD33
PBAD38
PBAD32
PBAD34
PBAD35
PBPCLKO4
PBPCLKO0
PBPCLKO5
PBGNT_B0
PBPCLKO3
PBGNT_B2
PBPCLKO1
PBREQ1#
PBREQ3#
PAIRQ15
PBIRQ13
PBIRQ9
PBIRQ3
PBIRQ8
PAIRQ14
PBIRQ7
PBIRQ12
PBIRQ2
PBIRQ11
PAIRQ12
PBIRQ5
PBIRQ6
PAIRQ13
PBIRQ1
PAIRQ11
PBIRQ0
PAIRQ7
BT_INTR#
PAIRQ10
APICD0
APICD1
PAIRQ6
PAIRQ9
PAIRQ5
PAIRQ3
PAIRQ8
PAIRQ4
PAIRQ2
PAIRQ1
PAIRQ0
HI_10
PASERR#
PAAD6
HI_9
HI_17
PAAD11
PAPAR
PUSTRBS
PD11
PAAD_1
PAAD14
PAAD7
PUSTRBF
HI_13
HPB_SIL#
PAREQ_B3
PAGNT_B2
PAREQ_B0
PAGNT_B3
PAAD_30
HI_12
PAAD10
PAAD13
PAC/BE7#
PAM66EN
PAC/BE0#
PAAD63
PAAD12
PAAD2
HI_14
HI_21
HI_15
PAREQ4#
PAPCLKO4
PAGNT0#
PAGNT5#
PAPCLKO3
PAGNT1#
PAREQ1#
PAAD25
PAAD9
PAREQ64#
PAPAR64
PAAD58
PAAD3
PBAD10
PBAD22
PBM66EN
PBAD21
PBAD3
PA_133EN
PAREQ2#
PAPCIRST#
PAGNT4#
PAPCLKO6
PAREQ5#
PAPCLKO1
PAPCLKO0
PAPCLKO5
PAPCLKO2
PAAD31
PAAD54
PAACK64#
PAAD8
PBAD14
PBAD20
PBAD7
PAAD59
PAAD55
PAAD50
PAAD60
PAC/BE4#
PAAD51
PAAD4
PBAD17
PBAD13
PBREQ64#
PBAD16
PBAD6
PAAD23
PAAD42
PAAD0
PBIRDY#
PBAD2
PAAD22
PAAD26
PAC/BE5#
PAAD46
PBC/BE7#
PBSTOP#
PAAD18
216
Intel® 82870P2 P64H2 Datasheet
Testability
R
Chain#1
Chain#2
Chain#3
Chain#4
PAAD27
Chain#5
PAAD5
Chain#6
PBPAR64
PAAD19
PAC/BE3#
PAAD28
PAAD20
PAAD47
PAAD61
PAAD56
PAAD38
PAC/BE6#
PAAD37
PAAD57
PAAD52
PAAD43
PBPCIXCAP
PBAD9
PBAD63
PBPLOCK#
PBAD1
PBPERR#
PBAD5
PBAD8
PBSERR#
Output of Each Chain is Visible on the Following Pins
HPB_SID HPB_SIC HPB_SOD
HPB_SOL
HPB_SOC
HPB_SOLR
7.3
Pins Excluded from XOR Chain Testing
Table 88 lists the pins that are excluded from XOR chain testing:
Table 88. Pins Excluded from XOR Chain Testing
PIN
Type
Description
Hub Interface input clock
CLK66
I
I
I
I
I
I
I
I
I
I
I
TEST#
Test mode activation pin
PCI reset pin
RSTIN#
PWROK
CLK200
CLK200#
Power OK
BPCLK100
BPCLK133
APICCLK
PAPCLKI
PBPCLKI
Intel® 82870P2 P64H2 Datasheet
217
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