RH80530GZ009512/SL5CL

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Mobile Intel^®Pentium^®III Processor-M

Datasheet

January 2003

Order Number: 298340-006

Introduction

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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended

for use in medical, life saving, or life sustaining applications.

The information provided in this report, and related materials and presentations, are intended to illustrate the effects of certain design variables as

determined by modeling, and are neither a recommendation nor endorsement of any specific system-level design practices or targets. The model results

are based on a simulated notebook configuration, and do not describe or characterize the properties of any specific, existing system design. A detailed

description of the simulated notebook configuration is available upon request.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future

definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Mobile Intel® Pentium® III Processor-M may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

www.intel.com

or call 1-800-548-4725

Intel®, Pentium®, and Intel® SpeedStep®, and MMX™ technology are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the

United States and other countries.

*Other names and brands may be claimed as the property of others.

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Contents

1.

Introduction .................................................................................................................................... 11

1.1

1.2

1.3

1.4

Overview .............................................................................................................. 12

State of the Data.................................................................................................. 12

Terminology ......................................................................................................... 13

References........................................................................................................... 13

2.

Mobile Intel Pentium III Processor-M Features.............................................................................. 14

2.1

New Features in the Mobile Pentium III Processor-M ......................................... 14

2.1.1 133-MHz PSB With AGTL Signaling....................................................... 14

2.1.2 512-K On-die Integrated L2 Cache......................................................... 14

2.1.3 Data Prefetch Logic ................................................................................ 14

2.1.4 Differential Clocking................................................................................ 14

2.1.5 Deeper Sleep State................................................................................. 15

2.1.6 Signal Differences Between the Mobile Pentium III Processor (in

BGA2 and Micro-PGA2 Packages) and the Mobile Intel Pentium III

Processor-M............................................................................................ 15

2.2

Power Management............................................................................................. 15

2.2.1 Clock Control Architecture ...................................................................... 15

2.2.2 Normal State........................................................................................... 15

2.2.3 Auto Halt State........................................................................................ 16

2.2.4 Quick Start State..................................................................................... 17

2.2.5 HALT/Grant Snoop State........................................................................ 18

2.2.6 Deep Sleep State.................................................................................... 18

2.2.7 Deeper Sleep State................................................................................. 18

2.2.8 Operating System Implications of Low-power States............................. 19

2.2.9 Enhanced Intel SpeedStep Technology ................................................. 19

AGTL Signals....................................................................................................... 19

Mobile Intel Pentium III Processor-M CPUID....................................................... 20

2.3

2.4

3.

Electrical Specifications ................................................................................................................. 21

3.1

Processor System Signals................................................................................... 21

3.1.1 Power Sequencing Requirements .......................................................... 22

3.1.2 Test Access Port (TAP) Connection....................................................... 23

3.1.3 Catastrophic Thermal Protection ............................................................ 23

3.1.4 Unused Signals....................................................................................... 23

3.1.5 Signal State in Low-power States........................................................... 23

3.1.5.1

3.1.5.2

3.1.5.3

System Bus Signals.............................................................. 23

CMOS and Open-drain Signals ............................................ 24

Other Signals ........................................................................ 24

3.2

3.3

Power Supply Requirements ............................................................................... 24

3.2.1 Decoupling Guidelines............................................................................ 24

3.2.2 Voltage Planes........................................................................................ 25

3.2.3 Voltage Identification............................................................................... 25

System Bus Clock and Processor Clocking......................................................... 26

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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3.4

3.5

3.6

3.7

Enhanced Intel SpeedStep Technology...............................................................26

Maximum Ratings.................................................................................................27

DC Specifications .................................................................................................27

AC Specifications .................................................................................................37

3.7.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC

Specifications ..........................................................................................37

4.

System Signal Simulations.............................................................................................................53

4.1

System Bus Clock (BCLK) and PICCLK DC Specifications and AC Signal

Quality Specifications ...........................................................................................53

AGTL AC Signal Quality Specifications................................................................55

Non-AGTL Signal Quality Specifications..............................................................56

4.3.1 PWRGOOD, VTTPWRGD Signal Quality Specifications........................57

4.3.1.1.1 VTTPWRGD Noise Parameter Specification...........57

4.2

4.3

4.3.1.2

VTTPWRGD Transition Parameter Recommendation..........58

4.3.1.2.1 Transition Region.....................................................58

4.3.1.2.2 Transition Time ........................................................58

4.3.1.2.3 Noise........................................................................58

5.

Mechanical Specifications ..............................................................................................................60

5.1

5.2

5.3

Socketable Micro-FCPGA Package .....................................................................60

Surface Mount Micro-FCBGA Package................................................................64

Signal Listings ......................................................................................................68

6.

7.

V_CCThermal Specifications ............................................................................................................75

6.1 Thermal Diode......................................................................................................76

Processor Initialization and Configuration......................................................................................78

7.1

Description............................................................................................................78

7.1.1 Quick Start Enable...................................................................................78

7.1.2 System Bus Frequency ...........................................................................78

7.1.3 APIC Enable............................................................................................78

Clock Frequencies and Ratios .............................................................................78

7.2

8.

Processor Interface ........................................................................................................................79

8.1

8.2

Alphabetical Signal Reference .............................................................................79

Signal Summaries ................................................................................................89

Appendix A. PLL RLC Filter Specification...................................................................................................91

A1.

A2.

A3.

A4.

Introduction..........................................................................................................91

Filter Specification ...............................................................................................91

Recommendation for Mobile Systems.................................................................92

Comments ...........................................................................................................93

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Figures

Figure 1. Clock Control States.......................................................................................... 17

Figure 2. PLL RLC Filter ................................................................................................... 25

Figure 3. VTTPWRGD System-Level Connections .......................................................... 26

Figure 4. Illustration of V_CCStatic and Transient Tolerances (VID = 1.40 V) .................. 31

Figure 5. Illustration of Deep Sleep V_CCStatic and Transient Tolerances (VID Setting

= 1.40 V)............................................................................................................ 32

Figure 6. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform............. 44

Figure 7. Differential BCLK/BCLK# Waveform (Common Mode)..................................... 44

Figure 8. BCLK/BCLK# Waveform (Differential Mode)..................................................... 45

Figure 9. Valid Delay Timings........................................................................................... 45

Figure 10. Setup and Hold Timings .................................................................................. 46

Figure 11. Cold/Warm Reset and Configuration Timings ................................................. 46

Figure 12. Power-on Sequence and Reset Timings......................................................... 47

Figure 13. Power Down Sequencing and Timings (VCC Leading)................................... 48

Figure 14.Power Down Sequencing and Timings (V_CCTLeading).................................... 49

Figure 15.Test Timings (Boundary Scan)......................................................................... 50

Figure 16. Test Reset Timings.......................................................................................... 50

Figure 17. Quick Start/Deep Sleep Timing (BCLK Stopping Method).............................. 51

Figure 18. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method)......................... 51

Figure 19. Enhanced Intel SpeedStep Technology/Deep Sleep Timing .......................... 52

Figure 20. BCLK (Single Ended)/PICCLK Generic Clock Waveform ............................... 54

Figure 21. Maximum Acceptable Overshoot/Undershoot Waveform ............................... 55

Figure 22. VTTPWRGD Noise Specification .................................................................... 59

Figure 23. Socketable Micro-FCPGA Package – Top and Bottom Isometric Views ........ 61

Figure 24. Socketable Micro-FCPGA Package – Top and Side View.............................. 62

Figure 25. Socketable Micro-FCPGA Package – Bottom View........................................ 63

Figure 26. Micro-FCBGA Package – Top and Bottom Isometric Views ........................... 65

Figure 27. Micro-FCBGA Package – Top and Side Views............................................... 66

Figure 28. Micro-FCBGA Package – Bottom View........................................................... 67

Figure 29. Pin/Ball Map – Top View.................................................................................. 68

Figure 30. PLL Filter Specifications .................................................................................. 92

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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Tables

Table 1. New and Revised Mobile Intel Pentium III Processor-M Signals........................15

Table 2. Clock State Characteristics .................................................................................19

Table 3. Mobile Pentium III Processor-M CPUID..............................................................20

Table 4. Mobile Pentium III Processor-M CPUID Cache and TLB Descriptors ................20

Table 5. System Signal Groups.........................................................................................21

Table 6. Recommended Resistors for Mobile Intel Pentium III Processor-M Signals.......22

Table 7. Mobile Intel Pentium III Processor-M VID Values ...............................................25

Table 8. Mobile Intel Pentium III Processor-M Absolute Maximum Ratings .....................27

Table 9. Power Specifications for Mobile Intel Pentium III Processor-M¹..........................28

Table 10. V_CCTolerances for the Mobile Intel Pentium III Processor-M: VID = 1.40 V

(Performance Mode) and 1.15 V (Battery Optimized Mode) ............................30

Table 11. V_CCTolerances for the Mobile Intel Pentium III Processor-M in the Deep Sleep

State: VID = 1.40 V (Performance Mode) and 1.15 V (Battery Optimized

Mode).................................................................................................................32

Table 12. V_CCTolerances for the Low Voltage Mobile Intel Pentium III Processor-M:

VID = 1.15 V (Performance Mode) and 1.05 V (Battery Optimized Mode) .......33

Table 13. V_CCTolerances for the Low Voltage Mobile Intel Pentium III Processor-M in

the Deep Sleep State: VID = 1.15 V (Performance Mode) and 1.05 V (Battery

Optimized Mode)...............................................................................................33

Table 14. V_CCTolerances for the Ultra Low Voltage Mobile Intel Pentium III

Processor-M: VID = 1.1 V (Performance Mode) and 0.95 V (Battery Optimized

Mode) ................................................................................................................34

Table 15. V_CCTolerances for the Ultra Low Voltage Mobile Intel Pentium III

Processor-M in the Deep Sleep State: VID = 1.1 V (Performance Mode) and

0.95 V (Battery Optimized Mode) ......................................................................34

Table 16. AGTL Signal Group DC Specifications..............................................................35

Table 17. AGTL Bus DC Specifications ............................................................................35

Table 18. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC

Specifications.....................................................................................................36

Table 19. System Bus Clock AC Specifications (Differential) ...........................................37

Table 20. System Bus Clock AC Specifications (133 MHz, Single Ended) ......................38

Table 21. System Bus Clock AC Specifications (100 MHz, Single Ended) ......................38

Table 22. Valid Mobile Intel Pentium III Processor-M Frequencies ..................................39

Table 23. AGTL Signal Groups AC Specifications............................................................40

Table 24. CMOS and Open-drain Signal Groups AC Specifications^{.................................................}40

Table 25. Reset Configuration AC Specifications and Power On/Power Down Timings..41

Table 26. APIC Bus Signal AC Specifications...................................................................42

Table 27. TAP Signal AC Specifications ...........................................................................43

Table 28. Quick Start/Deep Sleep AC Specifications .......................................................43

Table 29. Enhanced Intel SpeedStep Technology AC Specifications...............................44

Table 30. BCLK (Differential) DC Specifications and AC Signal Quality Specifications...53

Table 31. BCLK (Single Ended) DC Specifications and AC Signal Quality

Specifications.....................................................................................................53

Table 32. PICCLK DC Specifications and AC Signal Quality Specifications ....................54

Table 33. 133-MHz AGTL Signal Group Overshoot/Undershoot Tolerance at the

Processor Core..................................................................................................56

Table 34. 100-MHz AGTL Signal Group Overshoot/Undershoot Tolerance at the

Processor Core..................................................................................................56

Table 35. Non-AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor

Core ...................................................................................................................57

Table 36. VTTPWRGD Noise Parameter Specification ....................................................57

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Table 37. VTTPWRGD Transition Parameter Recommendation ..................................... 58

Table 38. Socketable Micro-FCPGA Package Specification............................................ 60

Table 39. Micro-FCBGA Package Mechanical Specifications.......................................... 64

Table 40. Signal Listing in Order by Pin/Ball Number....................................................... 69

Table 41. Signal Listing in Order by Signal Name............................................................ 72

Table 42. Voltage and No-Connect Pin/Ball Locations..................................................... 74

Table 43. Power Specifications for Mobile Intel Pentium III Processor-M ........................ 75

Table 44. Thermal Diode Interface ................................................................................... 77

Table 45. Thermal Diode Specifications........................................................................... 77

Table 46. BSEL[1:0] Encoding.......................................................................................... 82

Table 47. Input Signals ..................................................................................................... 89

Table 48. Output Signals .................................................................................................. 89

Table 49. Input/Output Signals (Single Driver) ................................................................. 90

Table 50. Input/Output Signals (Multiple Driver)............................................................... 90

Table 51. PLL Filter Inductor Recommendations ............................................................. 92

Table 52. PLL Filter Capacitor Recommendations........................................................... 92

Table 53. PLL Filter Resistor Recommendations ............................................................. 93

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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Revision History

Revision

001

002

Description

Date

July 2001

October 2001

Initial release

Revision 2.0 Updates include:

•

Added new mobile Intel^®Pentium^®III Processor-M 1.2 GHz

•

Added new Low Voltage mobile Intel Processor-M 800/533, 800A/500,

750/450, 733/466 MHz speeds

•

Added new Ultra Low Voltage mobile Intel Processor-M 700/300 MHz

speed

•

Updated Processor Specifications (Tables 9, 12-15, 42)

Load lines updated

Updated Section 5 and tables 36, 37 with additional package details

Updated references

003

Revision 3.0 Updates include:

January 2002

•

Added new Low Voltage mobile Intel Processor-M 866/533, 850/500,

MHz speeds

•

Added new Ultra Low Voltage mobile Intel Processor-M 750/350,

733/400 MHz speeds

•

Updated Processor Specifications (Tables 9, 12-15, 42)

•

Added Specification Clarification for VTTPWRGD in Table 25, Figure

22 and Section 4.3.1

•

Added CMOSREF resistor divider recommendations to Section 7

Updated references

004

June 2002

Revision 4.0 Updates include:

•

Target Processor Frequencies updated

Updated Section 5 and corrected/updated Tables 36 and 37

Added VTTPWRGD Spec Clarification to Table 25 and Section 4.3.1

Updated Section 7 with CMOSREF resistor divider recommendations

from RDDP

•

Updated CMOSREF description in Section 8.1

Updated the Intel^®SpeedStep^®technology mark

005

006

September 2002

January 2003

Revision 5.0 Updates include:

•

Target Processor Frequencies updated

Updated Table 9 and Table 43

Revision 6.0 Updates include:

•

Target Processor Frequencies updated

Updated Table 9 and Table 43

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Mobile Intel^®Pentium ^®III Processor-M Datasheet

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Mobile Intel^®Pentium^®Processor-M

Product Features

Supports Enhanced Intel^®SpeedStep^®

technology with the following

Processor core/bus speeds:

Ultra Low Voltage processors support

Enhanced Intel^®SpeedStep^®technology

with the following Processor core/bus

speeds:



1.333 GHz/133 MHz (Maximum

Performance Mode) and 800/133 MHz

(Battery Optimized Mode)



933/133 MHz (Maximum

Performance Mode) and 400/133

MHz (Battery Optimized Mode)

900/100 MHz (Maximum

1.266 GHz/133 MHz (Maximum

Performance Mode) and 800/133 MHz

(Battery Optimized Mode)

Performance Mode) and 400/100

MHz (Battery Optimized Mode)

866/133 MHz (Maximum

1.200 GHz/133 MHz (Maximum

Performance Mode) and 800/133 MHz

(Battery Optimized Mode)

Performance Mode) and 400/133

MHz (Battery Optimized Mode)

850/133 MHz (Maximum

1.133 GHz/133 MHz (Maximum

Performance Mode) and 733/133 MHz

(Battery Optimized Mode)

Performance Mode) and 400/133

MHz (Battery Optimized Mode)

800/133 MHz (Maximum

1.066 GHz/133 MHz (Maximum

Performance Mode) and 733/133 MHz

(Battery Optimized Mode)

Performance Mode) and 400/133

MHz (Battery Optimized Mode)

800/100 MHz (Maximum

1.000 GHz/133 MHz (Maximum

Performance Mode) and 733/133 MHz

(Battery Optimized Mode)

Performance Mode) and 400/100

MHz (Battery Optimized Mode)

Low Voltage processors support Enhanced

Intel SpeedStep technology with the following

Processor core/bus speeds:

Feature Highlights

Supports the Intel Architecture with

Dynamic Execution



1.00GHz/133 MHz (Maximum

Performance Mode) and 533/133 MHz

(Battery Optimized Mode)

933/133 MHz (Maximum Performance

Mode) and 533/133 MHz (Battery

Optimized Mode)

On-die primary 16-Kbyte instruction cache

and 16-Kbyte write-back data cache

On-die second level cache (512-Kbyte)

with Advanced Transfer Cache

Architecture

Data Prefetch Logic

866/133 MHz (Maximum Performance

Mode) and 533/133 MHz (Battery

Optimized Mode)

Integrated AGTL termination

Integrated math co-processor

Micro-FCPGA and Micro-FCBGA

packaging technologies

800/133 MHz (Maximum Performance

Mode) and 533/133 MHz (Battery

Optimized Mode)



Supports thin form factor notebook

designs

850/100 MHz (Maximum Performance

Mode) and 500/100 MHz (Battery

Optimized Mode)



Exposed die enables more efficient

heat dissipation

Fully compatible with previous Intel

microprocessors



800A/100 MHz (Maximum Performance

Mode) and 500/100 MHz (Battery

Optimized Mode)

Binary compatible with all

applications

Support for MMX™ technology

Support for Streaming SIMD

Extensions



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Power Management Features



Quick Start, Deep Sleep, and Deeper

Sleep modes provide low power

dissipation

On-die thermal diode

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Mobile Intel^®Pentium ^®III Processor-M Datasheet

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1. Introduction

Using Intel’s advanced 0.13-micron process technology with copper interconnect, the Mobile Intel^®

Pentium^®III Processor-M offers high-performance and low-power consumption. The Mobile Intel

Pentium III Processor-M (hereafter referred to as “the processor”) is based on the same core as existing

Mobile Intel^®Pentium^®III Processors. Key performance features include Internet Streaming SIMD

instructions, an Advanced Transfer Cache architecture, and a processor system bus speed of 133 MHz.

These features are offered in Micro-FCPGA packages for socketable boards and Micro-FCBGA

packages for surface mount boards.

The Low Voltage Mobile Intel Pentium III Processor-M will support both a 133-MHz and a 100-MHz

bus speed. The Ultra Low Voltage Mobile Intel Pentium III Processor-M will support both 133-MHz

and 100-MHz (see product features section for specific supported frequencies) bus speed. The Low

Voltage and Ultra Low Voltage Mobile processors will be available only in the Micro-FCBGA

package. All of these technologies make outstanding performance possible for mobile PCs in a variety

of shapes and sizes.

The processor, when used in conjunction with the Intel SpeedStep^®technology applet, supports

Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and

frequency between two performance modes based on CPU demand. This occurs by switching the bus

ratios, core operating voltage, and core processor speeds without resetting the system. The processor

also features a new ultra low power state called Deeper Sleep.

The 512-kB integrated L2 cache based on the Advanced Transfer Cache architecture runs at full speed

and is designed to help improve performance. It complements the system bus by providing critical data

faster and reducing total system power consumption. The processor also features Data Prefetch Logic

that speculatively fetches data to the L2 cache, resulting in improved performance. The Mobile

Pentium III Processor-M’s 64-bit wide Assisted Gunning Transceiver Logic (AGTL) system bus

provides a glue-less, point-to-point interface for a memory controller hub.

This document covers the electrical, mechanical, and thermal specifications for the following:

•

The Mobile Pentium III Processor-M is offered at the following frequencies and voltages

(Maximum Performance mode/Battery Optimized mode): 1.333 GHz/800 MHz, 1.266 GHz/800

MHz, 1.200 GHz/800 MHz, 1.133 GHz/733 MHz, 1.066 GHz/733 MHz, and 1.000 GHz/733

MHz at 1.40 V/1.15 V.

•

The Low Voltage Mobile Intel Pentium III Processor-M is offered at the following frequencies and

voltages (Maximum Performance mode/Battery Optimized mode): 1.00 GHz/533 MHz, 933/533

MHz, 866/533 MHz, 800/533 MHz, 850/500 MHz, and 800A/500 MHz at 1.15 V/1.05 V.

The Ultra Low Voltage Mobile Pentium III Processor-M is offered at the following frequency and

voltage (Maximum Performance mode/Battery Optimized mode): 933/400 MHz, 900/400 MHz,

866/400 MHz, 850/400 MHz, 800/400 MHz at 1.10 V/0.95 V.

Unless explicitly stated, all references to the Mobile Pentium III Processor-M in this document also

apply to the Low Voltage and Ultra Low Voltage Mobile Pentium III Processor-M.

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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Introduction

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1.1

Overview

•

Performance features

— Supports the Intel Architecture with Dynamic Execution

— Supports the Intel Architecture MMX™ technology

— Supports Streaming SIMD Extensions for enhanced video, sound, and 3D performance

— Supports Enhanced Intel SpeedStep Technology

— Integrated Intel Floating Point Unit compatible with the IEEE 754 standard

— Data Prefetch Logic

•

On-die primary (L1) instruction and data caches

— 4-way set associative, 32-byte line size, 1 line per sector

— 16-Kbyte instruction cache and 16-Kbyte write-back data cache

— Cacheable range controlled by processor programmable registers

On-die second level (L2) cache

— 8-way set associative, 32-byte line size, 1 line per sector

— Operates at full core speed

— 512-Kbyte ECC protected cache data array

AGTL system bus interface

— 64-bit data bus, 100-MHz and 133-MHz operation

— Uniprocessor, two loads only (processor and chipset)

— Integrated termination

Processor clock control

— Quick Start for low power, low exit latency clock “throttling”

— Deep Sleep mode for lower power dissipation

— Deeper Sleep mode for lowest power dissipation

Thermal Diode for measuring processor temperature

1.2

State of the Data

All information in this document is the best available information at the time of publication. Revisions

of this document will be provided on an as-required basis in the Mobile Intel^®Pentium^®III Processor

and Mobile Intel^®Pentium^®III Processor-M Specification Update.

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1.3

1.4

Terminology

Term

Definition

#

A “#” symbol following a signal name indicates that the signal is active low. This means that when the signal

is asserted (based on the name of the signal) it is in an electrical low state. Otherwise, signals are driven in

an electrical high state when they are asserted. In state machine diagrams, a signal name in a condition

indicates the condition of that signal being asserted

!

Indicates the condition of that signal not being asserted. For example, the condition “!STPCLK# and HS” is

equivalent to “the active low signal STPCLK# is unasserted (i.e., it is at 1.5 V) and the HS condition is true.”

L

H

0

Electrical low signal levels

Electrical high signal levels

Logical low. For example, BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# = “1010” =

“LHLH” also refers to a hexadecimal “A.”

1

Logical high. For example, BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# = “1010” =

“LHLH” also refers to a hexadecimal “A.”

TBD

X

Specifications that are yet to be determined and will be updated in future revisions of the document.

Don’t care condition

References

•

P6 Family of Processors Hardware Developer’s Manual (Order Number 244001-001)

Intel^®Architecture Optimization Reference Manual (Order Number 245127-001)

Intel^®Architecture Software Developer’s Manual

— Volume I: Basic Architecture (Order Number 245470)

— Volume II: Instruction Set Reference (Order Number 245471)

— Volume III: System Programming Guide (Order Number 245472)

•

CK-408 (CK-Titan) Clock Synthesizer/Driver Specification (Contact your Intel Field Sales

Representative)

Mobile Intel^®Pentium^®III Processor-M I/O Buffer Models, IBIS Format (Contact your Intel

Field Sales Representative)

Intel^®830 Chipset Family: 82830 Graphics and Memory Controller Hub (GMCH-M) Datasheet

(Order Number 298338-003)

Intel^®830 Chipset Family: Intel^®830 Chipset Platform Design Guide (Order Number 298339-

003)

Intel^®830 Chipset Family: Intel^®82801CAM I/O Controller Hub 3 (ICH3-M) Datasheet (Order

Number 290716-001)

Intel^®Mobile Voltage Positioning -II (IMVP-II) Design Guide (Contact your Intel Field Sales

Representative)

Mobile Intel^®Pentium^®III Processor-M /440MX Platform Design Guide (Contact your Intel

Field Sales Representative)

Intel^®Processor Identification and the CPUID Instruction Application Note AP-485 (Order

Number 241618-020)

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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2. Mobile Intel Pentium III Processor-M

Features

2.1

New Features in the Mobile Pentium III

Processor-M

2.1.1

133-MHz PSB With AGTL Signaling

The Mobile Pentium III Processor-M uses Assisted GTL (AGTL) signaling on the PSB interface. The

main difference between AGTL and GTL+ used on previous Intel processors is V_CCT= 1.25 V for

AGTL versus 1.5 V for GTL+. The lower voltage swing enables high performance at lower power.

The Low Voltage Mobile Pentium III Processor-M will support 100-MHz and 133-MHz bus

frequencies. The Ultra Low Voltage Mobile Pentium III Processor-M will support both 100-MHz and

133-MHz bus frequencies (see product features for specific supported frequencies).

2.1.2

2.1.3

512-K On-die Integrated L2 Cache

The 512-K, on die, integrated L2 cache on the Mobile Pentium III Processor-M is double the L2 cache

size on the mobile Pentium III processor. The L2 cache runs at the processor core speed and the

increased cache size provides superior processing power.

Data Prefetch Logic

The Mobile Pentium III Processor-M features Data Prefetch Logic that speculatively fetches data to the

L2 cache before an L1 cache request occurs. This reduces transactions between the cache and system

memory reducing or eliminating bus cycle penalties, resulting in improved performance. The

processor also includes extensions to memory order and reorder buffers that boost performance.

2.1.4

Differential Clocking

The Mobile Intel Pentium III Processor-M is the first mobile Intel processor to support Differential

Clocking. Differential clocking requires the use of two complementary clocks: BCLK and BCLK#.

Benefits of differential clocking include easier scaling to lower voltages, reduced EMI, and less jitter.

All references to BCLK in this document apply to BCLK# also even if not explicitly stated. The

Mobile Intel Pentium III Processor-M will also support Single Ended Clocking. The processor will

configure itself for differential or single ended clocking based on the waveforms detected on the

BCLK and BCLK#/CLKREF signal lines.

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2.1.5

2.1.6

Deeper Sleep State

The Deeper Sleep State is a new low power state on the Mobile Intel Pentium III Processor-M. It is

functionally identical to the Deep Sleep State but at a lower voltage. More details are provided in

Section 2.2.7.

Signal Differences Between the Mobile Pentium III

Processor (in BGA2 and Micro-PGA2 Packages) and

the Mobile Intel Pentium III Processor-M

A list of new and changed signals is shown in Table 1.

Table 1. New and Revised Mobile Intel Pentium III Processor-M Signals

Signals

Function

BCLK, BCLK# Differential host clk signals.

CLKREF

BSEL[1:0]

DPSLP#

NCTRL

Host Clock reference signal in Single Ended Clocking mode.

Signals are output only instead of I/O. Please refer to the Appendix for details.

Deep Sleep pin (replaces SLP# pin on the Pentium III processor).

AGTL output buffer pull down impedance control.

VID[4:0]

Voltage Identification (different implementation from Pentium III processor). Please refer to

Section 3.2.3 for details.

VTTPWRGD Power Good signal for VCCT, which indicates that, the VID signals are stable. Please refer to

Figure 3 for VTTPWRGD system level connections.

2.2

Power Management

2.2.1

Clock Control Architecture

The Mobile Pentium III Processor-M clock control architecture (Figure 1) has been optimized for

leading edge mobile computer designs. The clock control architecture consists of six different clock

states: Normal, Auto Halt, Quick Start, HALT/Grant Snoop, Deep Sleep, and Deeper Sleep states. The

Auto Halt state provides a low-power clock state that can be controlled through the software execution

of the HLT instruction. The Quick Start state provides a very low power and low exit latency clock

state that can be used for hardware controlled “idle” computer states. The Deep Sleep and Deeper

Sleep states provide extremely low-power states that can be used for “Power-On-Suspend” computer

states, which is an alternative to shutting off the processor’s power. The exit latency of the Deep Sleep

state is 30 µsec in the Mobile Pentium III Processor-M. Performing state transitions not shown in

Figure 1 is neither recommended nor supported. Table 2 provides the clock state characteristics, which

are described in detail in the following sections.

2.2.2

Normal State

The Normal state of the processor is the normal operating mode where the processor’s core clock is

running and the processor is actively executing instructions.

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2.2.3

Auto Halt State

This is a low-power mode entered by the processor through the execution of the HLT instruction. A

transition to the Normal state is made by a halt break event (one of the following signals going active:

NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, or SMI#).

Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to the

Quick Start state. Deasserting STPCLK# will cause the processor to return to the Auto Halt state

without issuing a new Halt bus cycle.

The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management

Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state. See the Intel^®

Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide for more

information. No Halt bus cycle is issued when returning to the Auto Halt state from the System

Management Mode (SMM).

The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have been

flushed, the processor will return to the Auto Halt state without issuing a Halt bus cycle. Transitions in

the A20M# and PREQ# signals are recognized while in the Auto Halt state.

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Figure 1. Clock Control States

STPCLK#¹

BCLK stopped

or DPSLP#

Normal

2

Quick Start

Deep Sleep

(!STPCLK# and !HS)

or RESET#

HS=false

BCLK on

and !DPSLP#

STPCLK#¹

core

halt

break

snoop

voltage

core

HLT

snoop

occurs

serviced

raised

!STPCLK#

and HS

instruction¹

voltage

reduced

snoop

occurs

Auto Halt

HS=true

HALT/Grant

Snoop

Deeper

Sleep

snoop

serviced

V0001-02

NOTES:

1. State transition does not occur until the Stop Grant or Auto Halt acknowledge bus cycle completes

Halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

HLT – HLT instruction executed

HS – Processor Halt State

2. Restrictions apply to the use of both methods of entering Deep Sleep. See Deep Sleep state description for details.

2.2.4

Quick Start State

The processor is required to be configured for the Quick Start state by strapping the A15# signal low.

More details are provided in Section 7.1. In the Quick Start state the processor is only capable of acting

on snoop transactions generated by the system bus priority device. Because of its snooping behavior,

Quick Start can only be used in a uniprocessor (UP) configuration.

A transition to the Deep Sleep state can be made by stopping the clock input to the processor or

asserting the DPSLP# signal. A transition back to the Normal state (from the Quick Start state) is made

only if the STPCLK# signal is deasserted.

While in the Quick Start state the processor is limited in its ability to respond to input. It is incapable

of latching any interrupts, servicing snoop transactions from symmetric bus masters or responding to

FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond

properly to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal

changes, then the behavior of the processor will be unpredictable. No serial interrupt messages may

begin or be in progress while the processor is in the Quick Start state.

RESET# assertion will cause the processor to immediately initialize itself, but the processor will stay

in the Quick Start state after initialization until STPCLK# is deasserted.

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2.2.5

2.2.6

HALT/Grant Snoop State

The processor will respond to snoop transactions on the system bus while in the Auto Halt or Quick

Start state. When a snoop transaction is presented on the system bus the processor will enter the

HALT/Grant Snoop state. The processor will remain in this state until the snoop has been serviced and

the system bus is quiet. After the snoop has been serviced, the processor will return to its previous

state. If the HALT/Grant Snoop state is entered from the Quick Start state, then the input signal

restrictions of the Quick Start state still apply in the HALT/Grant Snoop state, except for those signal

transitions that are required to perform the snoop.

Deep Sleep State

The Deep Sleep state is a very low power state the processor can enter while maintaining its context.

The Deep Sleep state is entered by stopping the BCLK and BCLK# inputs to the processor, or by

asserting the DPSLP# signal while it is in the Quick Start state. Note that either one of the methods

can be used to enter Deep Sleep but not both at the same time. When BCLK and BCLK# are stopped,

they must obey the DC levels specified in Table 30 and Table 31.

The processor will return to the Quick Start state from the Deep Sleep state when the BCLK and

BCLK# inputs are restarted or the DPSLP# signal is deasserted. Due to the PLL lock latency, there is a

delay of up to 30 µsec after the clocks have started before this state transition happens. PICCLK may

be removed in the Deep Sleep state. PICCLK should be designed to turn on when BCLK and BCLK#

turn on or DPSLP# is deasserted when transitioning out of the Deep Sleep state.

2.2.7

Deeper Sleep State

The Deeper Sleep state is the lowest power state the processor can enter while maintaining its context.

It is functionally identical to the Deep Sleep State but at a lower voltage. The processor transitions to

the Deeper Sleep state from the Deep Sleep when the voltage regulator lowers the core voltage. The

VID signals for the Deeper Sleep State are supplied to the voltage regulator through control from the

I/O Controller Hub component. For more details on how this is implemented on the Mobile Intel

Pentium III Processor-M /Intel 830 platform, please refer to the Intel^®82801CAM I/O Controller Hub

3 (ICH3-M) Datasheet and contact your Intel Field Sales Representative for details on Intel Mobile

Voltage Positioning – II (IMVP-II) implementation. For details on how Deeper Sleep is implemented

on 440MX chipset based systems using the Intel SpeedStep technology Control Logic Plus (ISSCL+)

component, please refer to the Mobile Intel^®Pentium^®III Processor-M/440MX Platform Design

Guide.

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Table 2. Clock State Characteristics

Clock State

Exit Latency

Snooping?

System Uses

Normal

N/A

Yes

Normal program execution

Auto Halt

Quick Start

S/W controlled entry idle mode

10 µsec

Through snoop, to

HALT/Grant Snoop state:

immediate

Yes

H/W controlled entry/exit mobile throttling

Supports snooping in the low power states

Through STPCLK#, to

Normal state: 10 µsec

HALT/Grant

Snoop

A few bus clocks after

snoop completion

Yes

No

Deep Sleep

H/W controlled entry/exit mobile powered-on

suspend support

30 µsec

Deeper Sleep

Platform Dependent

No

H/W controlled entry/exit mobile powered-on

suspend support

100 µsec (recommended)

2.2.8

2.2.9

Operating System Implications of Low-power States

The time-stamp counter and the performance monitor counters are not guaranteed to count in the

Quick Start state. The local APIC timer and performance monitor counter interrupts should be disabled

before entering the Deep Sleep state or the resulting behavior will be unpredictable.

Enhanced Intel SpeedStep Technology

The Mobile Intel Pentium III Processor-M supports Enhanced Intel SpeedStep technology. Enhanced

Intel SpeedStep technology allows the processor to switch automatically between two core frequencies

based on CPU demand, without resetting the processor or changing the system bus frequency. The

processor has two bus ratios programmed into it instead of one, and the GHI# signal controls which

one is used. After reset, the processor will start in the lower of its two core frequencies, the Battery

Optimized mode. An operating mode transition to the high core frequency can be made by putting the

processor into the Deep Sleep state, raising the core voltage, setting GHI# low, and returning to the

Normal state. This puts the processor into the “Maximum performance” mode. Reversing these steps

transitions the processor back to the low-core frequency. Please contact your Intel Field Sales

Representative for details on how Enhanced Intel SpeedStep technology can be implemented with the

Mobile Intel Pentium III Processor-M, Intel 830MP chipset, or its equivalent and the Intel SpeedStep

technology applet.

2.3

AGTL Signals

The Mobile Pentium III Processor-M system bus signals use a variation of the low-voltage swing GTL

signaling technology. The AGTL system bus depends on incident wave switching and uses flight time

for timing calculations of the AGTL signals, as opposed to capacitive derating. Intel recommends

analog signal simulation of the system bus including trace lengths. Contact your field sales

representative to receive the IBIS models for the Mobile Pentium III Processor-M.

The AGTL system bus of the Mobile Pentium III Processor-M is designed to support high-speed data

transfers with multiple loads on a long bus that behaves like a transmission line. This termination is

provided on the processor core (except for the RESET# signal).

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2.4

Mobile Intel Pentium III Processor-M CPUID

When the CPUID version information is loaded with EAX=01H, the EAX and EBX registers contain

the values shown in Table 3. After a power-on RESET, the EDX register contains the processor

version information (type, family, model, stepping). Please refer to the Intel Processor Identification

and the CPUID Instruction Application Note AP-485 for more details. Table 4 shows the CPUID

Cache and TLB descriptor values after the L2 cache is initialized.

Table 3. Mobile Pentium III Processor-M CPUID

EAX[31:0]

EBX[7:0]

Brand ID

Reserved [31:14] Type [13:12] Family [11:8] Model [7:4] Stepping [3:0]

X

0

6

B

X

06

Table 4. Mobile Pentium III Processor-M CPUID Cache and TLB Descriptors

Cache and TLB Descriptors

01H, 02H, 03H, 04H, 08H, 0CH, 83H

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3. Electrical Specifications

3.1

Processor System Signals

Table 5 lists the processor system signals by type. All AGTL signals are synchronous with the BCLK

and BCLK# signals. All TAP signals are synchronous with the TCK signal except TRST#. All CMOS

input signals can be applied asynchronously.

Table 5. System Signal Groups

Group Name

Signals

AGTL Input

AGTL Output

AGTL I/O

BPRI#, DEFER#, RESET#, RSP#

PRDY#

A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,

BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#,

RP#, RS[2:0]#, TRDY#

1.5 V CMOS Input

1.8 V CMOS Input

A20M#, DPSLP#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#,

STPCLK#

PWRGOOD

1.5 V Open Drain Output FERR#, IERR#

3.3 V Open Drain Output BSEL[1:0], VID[4:0]

1.25 V input

Clock

GHI#, VTTPWRGD

BCLK, BCLK# (Differential Mode)

BCLK (Single Ended Mode)

PICCLK

2.5 V Clock Input

APIC Clock

APIC I/O

PICD[1:0]

Thermal Diode

TAP Input

THERMDC, THERMDA

TCK, TDI, TMS, TRST#

TDO

TAP Output

Power/Other

CLKREF, CMOSREF, EDGECTRLP, NC, NCTRL, PLL1, PLL2, RTTIMPEDP, V_CC

V_CCT, V_REF, V_SS,

,

NOTES:

1. V_CCis the power supply for the core logic.

2. PLL1 and PLL2 are power/ground for the PLL analog section. See Section 3.2.2 for details.

3. V_CCTis the power supply for the system bus buffers.

4. V_REFis the voltage reference for the AGTL input buffers.

5. V_SSis system ground.

The APIC data and TAP outputs are Open-drain and should be pulled up to 1.5 V using resistors with

the values shown in Table 6. If Open-drain drivers are used for input signals, then they should also be

pulled up to the appropriate voltage using resistors with the values shown in Table 6.

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Table 6. Recommended Resistors for Mobile Intel Pentium III Processor-M Signals

Mobile Intel Pentium III Processor-M Signal ^{1, 2}

Recommended

Resistor Value (Ω)

No pull-up

GHI# ³

10 pull-down

14 pull-up

BREQ0#⁴

NCTRL

39 pull-up

TMS

39 pull-down

56.2 pull-up

56.2 pull-down

110 pull-down

150 pull-up

TCK

PRDY#, RESET#⁵

RTTIMPEDP

EDGECTRLP

PICD[1:0], TDO

PREQ#, TDI

200-300 pull-up

500 pull-down

1 K pull-up

TRST#

BSEL[1:0], TESTHI, VID[4:0], VTTPWRGD

TESTLO

1 K pull-down

1.5 K pull-up

3 K pull-up

FERR#, IERR#, PWRGOOD

FLUSH#

Additional Pullup/Pulldown Resistor Recommendations⁷

270 pull-up

680 pull-up

1.5 K pull-up

NOTES:

SMI#

STPCLK#

A20M#, DPSLP#, INIT#, IGNNE#, LINT0/INTR, LINT1/NMI

1. The recommendations above are only for signals that are being used. These recommendations are maximum

values only; stronger pull-ups may be used. Pull-ups for the signals driven by the chipset should not violate the

chipset specification. Refer to Section 3.1.4 for the required pull-up or pull-down resistors for signals that are not

being used.

2. Open-drain signals must never violate the undershoot specification in Section 4.3. Use stronger pull-ups if there

is too much undershoot.

3. GHI# has an on-die pull-up to V_CCT

.

4. A pull-down on BREQ0# is an alternative to having the central agent to drive BREQ0# low at reset.

5. A 56.2 Ω 1% terminating resistor connected to V_CCTis required.

6. The following signals are actively driven high by the ICH3-M component and do not need external pull up

resistors on ICH3-M based platforms: A20M#, DPSLP#, INIT#, IGNNE#, LINT0/INTR, LINT1/NMI, SMI#,

STPCLK#.

7. These pull up recommendations apply to systems on which these signals are not actively pulled high such as

those utilizing the 82443MX chipset.

3.1.1

Power Sequencing Requirements

Unlike the Mobile Pentium III Processor, the Mobile Intel Pentium III Processor-M has specific power

sequencing requirements. The power on sequencing and timings are shown in Figure 12 and Table 25.

Power down timing requirements are shown in Figure 13, Figure 14, and Table 25. The V_CCpower

plane must not rise too fast. At least 200 µsec (T_R) must pass from the time that V_CCis at 10% of its

nominal value until the time that V_CCis at 90% of its nominal value. The recommended V_CCrise and

fall times for Enhanced Intel SpeedStep technology and Deeper Sleep transitions are 100 µsec (max).

For more details, please refer to the Intel^®Mobile Voltage Positioning -II (IMVP-II) Design Guide.

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3.1.2

Test Access Port (TAP) Connection

The TAP interface is an implementation of the IEEE 1149.1 (“JTAG”) standard. Due to the voltage

levels supported by the TAP interface, Intel recommends that the Mobile Intel Pentium III Processor-M

and the other 1.5-V JTAG specification compliant devices be last in the JTAG chain after any devices

with 3.3-V or 5.0-V JTAG interfaces within the system. A translation buffer should be used to reduce

the TDO output voltage of the last 3.3/5.0 V device down to the 1.5-V range that the Mobile Intel

Pentium III Processor-M can tolerate. Multiple copies of TMS and TRST# must be provided, one for

each voltage level.

A Debug Port and connector may be placed at the start and end of the JTAG chain containing the

processor, with TDI to the first component coming from the Debug Port and TDO from the last

component going to the Debug Port. There are no requirements for placing the Mobile Intel Pentium III

Processor-M in the JTAG chain, except for those that are dictated by voltage requirements of the TAP

signals.

3.1.3

3.1.4

Catastrophic Thermal Protection

The Mobile Intel Pentium III Processor-M does not support catastrophic thermal protection or the

THERMTRIP# signal. An external thermal sensor must be used to protect the processor and the system

against excessive temperatures. If the external thermal sensor detects a processor junction temperature

of 101°C (maximum), both the V_CCand V_CCTsupplies to the processor must be reduced to at least 50%

of the nominal values within 500 ms, and Intel recommends turning them off completely within 1

second to prevent damage to the processor. Processor temperature must be monitored in all states

including low power states.

Unused Signals

All signals named NC must be unconnected. Unused AGTL inputs, outputs and bi-directional signals

should be unconnected. Unused CMOS active low inputs should be connected to 1.5 V and unused

active high inputs should be connected to V_SS. Unused Open-drain outputs should be unconnected.

When tying any signal to power or ground, a resistor will allow for system testability. For unused

signals, Intel suggests that 1.5-kΩ resistors are used for pull-ups and 1.0-kΩ resistors are used for pull-

downs.

PICCLK must be driven with a clock that meets specification and the PICD[1:0] signals must be pulled

up separately to 1.5 V with 150-Ω resistors, even if the local APIC is not used.

If the TAP signals are not used then the inputs should be pulled to ground with 1-kΩ resistors and

TDO should be left unconnected.

3.1.5

Signal State in Low-power States

3.1.5.1

System Bus Signals

All of the system bus signals have AGTL input, output, or input/output drivers. Except when servicing

snoops, the system bus signals are tri-stated and pulled up by the termination resistors. Snoops are not

permitted in the Deep Sleep and Deeper Sleep states.

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3.1.5.2

3.1.5.3

CMOS and Open-drain Signals

The CMOS input signals are allowed to be in either the logic high or low state when the processor is in

a low-power state. In the Auto Halt state these signals are allowed to toggle. These input buffers have

no internal pull-up or pull-down resistors and system logic can use CMOS or Open-drain drivers to

drive them.

The Open-drain output signals have open drain drivers and external pull-up resistors are required. One

of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and pulled-up)

when the processor is functioning normally. The FERR# output can be either tri-stated or driven to V_SS

when the processor is in a low-power state depending on the condition of the floating-point unit. Since

this signal is a DC current path when it is driven to V_SS, Intel recommends that the software clears or

masks any floating-point error condition before putting the processor into the Deep Sleep state.

Other Signals

The system bus clocks (BCLK, BCLK#) must be driven in all of the low-power states except the Deep

Sleep state. The APIC clock (PICCLK) must be driven whenever BCLK and BCLK# are driven.

Otherwise, it is permitted to turn off PICCLK by holding it at V_SS. BCLK and BCLK# should be obey

the DC levels in Table 30 (for Differential Clocking) and Table 31 (for Single Ended Clocking).

In the Auto Halt state, the APIC bus data signals (PICD[1:0]) may toggle due to APIC bus messages.

These signals are required to be tri-stated and pulled-up when the processor is in the Quick Start or

Deep Sleep states.

3.2

Power Supply Requirements

3.2.1

Decoupling Guidelines

The Mobile Intel Pentium III Processor-M Micro-FCPGA package has twelve 0805IDC, 1-µF surface

mount decoupling capacitors. Eight capacitors are on the V_CCsupply and four capacitors are on V_CCT.

For the Micro-FCBGA package, there are six 0.68-µF capacitors on V_CCand two 0.68-µF capacitors

on V_CCT. In addition to the package capacitors, sufficient board level capacitors are also necessary for

power supply decoupling. These guidelines are as follows:

•

High and Mid Frequency VCC decoupling – Place twenty-four 0.22-µF 0603 capacitors directly

under the package on the solder side of the motherboard using at least two vias per capacitor

node. Ten 10-µF X7 6.3 V 1206-size ceramic capacitors should be placed around the package

periphery near the balls. Trace lengths to the vias should be designed to minimize inductance.

Avoid bending traces to minimize ESL.

•

High and Mid Frequency VCCT decoupling – Place ten 1-µF X7R 0603 ceramic capacitors close

to the package. Via and trace guidelines are the same as above.

Bulk VCC decoupling – Minimum of 1200-µF capacitance with Equivalent Series Resistance

(ESR) less than or equal to 3.5 mΩ.

Bulk VCCT decoupling – Platform dependent but recommendation for Intel 830 Chipset Family

based systems is minimum of 660 µF with ESR less than or equal to 7 mΩ.

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3.2.2

Voltage Planes

All V_CCand V_SSpins/balls must be connected to the appropriate voltage plane. All V_CCTand V_REF

pins/balls must be connected to the appropriate traces on the system electronics. In addition to the main

V_CC, V_CCT, and V_SSpower supply signals, PLL1 and PLL2 provide analog decoupling to the PLL

section. PLL1 and PLL2 should be connected according to Figure 2. Do not connect PLL2 directly to

V_SS. Appendix A contains the RLC filter specification.

Figure 2. PLL RLC Filter

L1

R1

PLL1

PLL2

V_CCT

C1

V0027-01

3.2.3

Voltage Identification

There are five voltage identification balls/pins on the Mobile Intel Pentium III Processor-M. These

signals can be used to support automatic selection of V_CCvoltages. They are needed to cleanly support

voltage specification variations on current and future processors. VID[4:0] are defined in Table 7. The

voltages specified in the VID table are the Battery Optimized Mode V_CCvoltages. The VID[4:0]

signals are open drain on the processor and need pullup resistors to 3.3 V on the motherboard. Please

refer to the mobile VR guidelines provided by Intel for additional information.

Table 7. Mobile Intel Pentium III Processor-M VID Values

VID[4:0]

V_CC(V)

VID[4:0]

V_CC(V)

VID[4:0]

V_CC(V)

VID[4:0]

V_CC(V)

00000

00001

00010

00011

00100

00101

00110

00111

1.750

1.700

1.650

1.600

1.550

1.500

1.450

1.400

01000

01001

01010

01011

01100

01101

01110

01111

1.350

1.300

1.250

1.200

1.150

1.100

1.050

1.000

10000

10001

10010

10011

10100

10101

10110

10111

0.975

0.950

0.925

0.900

0.875

0.850

0.825

0.800

11000

11001

11010

11011

11100

11101

11110

11111

0.775

0.750

0.725

0.700

0.675

0.650

0.625

0.600

Figure 3 shows the system level connections for the VTTPWRGD signal. Please refer to the

appropriate VR and system level guidelines provided by Intel for more details.

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Figure 3. VTTPWRGD System-Level Connections

Vcct

Processor

Voltage Regulator

Vcct

1k

Vttpwrgd

(output)

Vttpwrgd

(input)

3.3V

100k

10k

Clock Generator

Vttpwrgd#

(input)

1.2V to 3.3V Level Shifter

3.3

3.4

System Bus Clock and Processor Clocking

The BCLK and BCLK# clock inputs directly control the operating speed of the system bus interface.

All system bus timing parameters are specified with respect to the crossing point of the rising edge of

the BCLK input and falling edge of the BCLK# input. The Mobile Intel Pentium III Processor-M core

frequency is a multiple of the BCLK frequency. The processor core frequency is configured during

manufacturing. The configured bus ratio is visible to software in the Power-on configuration register.

See Section 7.2 for details.

Multiplying the bus clock frequency is necessary to increase performance while allowing for easier

distribution of signals within the system. Clock multiplication within the processor is provided by the

internal Phase Lock Loop (PLL), which requires constant frequency BCLK, BCLK# inputs. During

Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to acquire the phase

of BCLK and BCLK#. This time is called the PLL lock latency, which is specified in Section 3.7, AC

timing parameters T18 and T47.

Enhanced Intel SpeedStep Technology

The Mobile Intel Pentium III Processor-M supports Enhanced Intel SpeedStep technology, which

enables the processor to operate in two modes, the Maximum Performance mode or the Battery

Optimized mode. Each frequency and voltage pair identifies the operating mode. The voltage provided

to the processor must meet the core voltage specification for the current operating mode. If an

operating mode transition is made, then the system logic must direct the voltage regulator to regulate to

the voltage specification of the other mode. After reset, the processor will start in the lower of its two

core frequencies, so the core voltage must meet the lower voltage specification. Any RESET# assertion

will force the processor to the lower frequency, and the core voltage must behave appropriately. INIT#

assertions ("soft" resets) and APIC bus INIT messages do not change the operating mode of the

processor. Some electrical and thermal specifications are for a specific voltage and frequency. The

Mobile Intel Pentium III Processor-M will meet the electrical and thermal specifications specific to the

current operating mode, and it is not guaranteed to meet the electrical and thermal specifications

specific to the opposite operating mode. The timing specifications must be met when performing an

operating mode transition.

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3.5

Maximum Ratings

Table 8 contains the Mobile Intel Pentium III Processor-M stress ratings. Functional operation at the

absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a

clock while subjected to these conditions. Functional operating conditions are provided in the AC and

DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore,

although the processor contains protective circuitry to resist damage from static electric discharge, one

should always take precautions to avoid high static voltages or electric fields.

Table 8. Mobile Intel Pentium III Processor-M Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

°C

Notes

Note 1

T_Storage

V_CC(Abs)

V_CCT

Storage Temperature

–40 85

Supply Voltage with respect to V_SS

–0.5 1.75

–0.3 1.75

–0.3 2.0

–0.3 2.4

–0.3 3.3

V

System Bus Buffer Voltage with respect to V_SS

System Bus Buffer DC Input Voltage with respect to V_SS

1.25V Buffer DC Input Voltage with respect to V_SS

1.5V Buffer DC Input Voltage with respect to V_SS

1.8V Buffer DC Input Voltage with respect to V_SS

2.0V Buffer DC Input Voltage with respect to V_SS

2.5V Buffer DC Input Voltage with respect to V_SS

VID ball/pin DC Input Voltage with respect to V_SS

VID Current

V

V_{IN GTL}

V_IN125

V_IN15

V

Notes 2, 3

Note 4

Note 5

Note 6

Note 7

Note 9

Note 8

V

V_IN18

V

V_IN20

V

V_IN25

V

V_INVID

—

3.465

V

I_VID

-0.3 3.6

mA

NOTES:

1. The shipping container is only rated for 65°C.

2. Parameter applies to the AGTL signal groups only. Compliance with both V_{IN GTL}specifications is required.

3. The voltage on the AGTL signals must never be below –0.3 or above 1.75 V with respect to ground.

4. Parameter applies to CLKREF, GHI#, TESTHI, VTTPWRGD signals.

5. Parameter applies to CMOS, Open-drain, APIC, TESTLO and TAP bus signal groups only.

6. Parameter applies to PWRGOOD signal.

7. Parameter applies to PICCLK signal.

8. Parameter applies to each VID pin/ball individually.

9. Parameter applies to BCLK signal in Single Ended Clocking Mode.

3.6

DC Specifications

Table 9 through Table 18 list the DC specifications for the Mobile Intel Pentium III Processor-M.

Specifications are valid only while meeting specifications for the junction temperature, clock

frequency, and input voltages. The junction temperature range for all DC specifications is 0°C to

100°C. Care should be taken to read all notes associated with each parameter. Unlike the Mobile

Pentium III Processor, the V_cctolerances for the Mobile Intel Pentium III Processor-M are not specified

as a percentage of nominal. The tolerances are instead specified in the form of load lines for the static

and transient cases in Table 10 through Table 15. Illustration of the load lines is shown in Figure 4 and

Figure 5.

Mobile Intel^®Pentium ^®III Processor-M Datasheet

27

Electrical Specifications

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Table 9. Power Specifications for Mobile Intel Pentium III Processor-M¹

Symbol

Parameter

Min

Typ

Max Unit

Notes

V_CC

Transient V_CCfor core logic

Battery Optimized Mode

0.95

1.05

1.15

V

Notes 10, 11

Maximum Performance Mode

1.10

1.15

1.40

V_CC,DC

Static V_CCfor core logic

Battery Optimized Mode

0.95

1.05

1.15

V

Notes 10, 11

Maximum Performance Mode

1.10

1.15

1.40

V_CCDPRSLP

Transient V_CCfor core logic during Deeper Sleep 0.785 0.85 0.900

0.80 0.85 0.880

V_CCfor System Bus Buffers, Transient tolerance 1.138 1.25 1.362

V

A

Note 11

V_{CCDPRSLP, DC}Static V_CCfor core logic during Deeper Sleep

Note 11

V_CCT

V_CCT,DC

I_CC

± 9%, Notes 8,11

±5%, Notes 2,11

Note 4

V_CCfor System Bus Buffers, Static tolerance

Current for V_CCat core frequency

1.188 1.25 1.312

300 MHz & 0.95 V

350 MHz & 0.95 V

400 MHz & 0.95 V

450 MHz & 1.05 V

466 MHz & 1.05 V

500 MHz & 1.05 V

533 MHz & 1.05 V

700 MHz & 1.10 V

733 MHz & 1.10 V

750 MHz & 1.10 V

800 MHz & 1.10 V

850 MHz & 1.10 V

866 MHz & 1.10 V

900 MHz & 1.10 V

933 MHz & 1.10 V

667 MHz & 1.15 V

733 MHz & 1.15 V

750 MHz & 1.15 V

800 MHz & 1.15 V

850 MHz & 1.15 V

866 MHz & 1.15 V

933 MHz & 1.15 V

1.000 GHz & 1.15 V

866 MHz & 1.40 V

933 MHz & 1.40 V

1.000 GHz & 1.40 V

1.066 GHz & 1.40 V

1.133 GHz & 1.40 V

1.200 GHz & 1.40 V

1.266 GHz & 1.40 V

1.333 GHz & 1.40 V

3.98

4.28

Notes 4, 12

4.58

6.08

6.19

6.38

6.61

7.58

Notes 4, 12

7.58

8.25

8.38

8.43

8.57

8.90

9.39

9.47

9.57

10.21

10.32

10.50

10.94

15.87

16.45

16.83

17.46

18.11

18.69

18.92

I_CCT

Current for V_CCT

2.7

A

Notes 3, 4

Note 4

I_CC,AH

Processor Auto Halt current at

28

Mobile Intel^®Pentium ^®III Processor-M Datasheet

Electrical Specifications

R

Symbol

Parameter

Min

Typ

Max Unit

Notes

0.95 V

1.05 V

1.10 V

1.15 V

1.40 V

1.88

3.36

3.09

4.52

8.85

Notes 4, 12

I_CC,QS

Processor Quick Start current at

A

Note 4

0.95 V

1.05 V

1.10 V

1.15 V

1.40 V

1.82

3.22

2.91

4.30

8.53

Notes 4, 12

I_CC,DSLP

Processor Deep Sleep Leakage current at

Note 4

0.95 V

1.05 V

1.10 V

1.15 V

1.40 V

1.70

3.01

2.65

3.99

8.04

Notes 4, 12

I_CC,DPRSLP

I_CC,DPRSLPULV

I_LVID

Processor Deeper Sleep Leakage current

VID leakage current

1.70

1.27

0.5

A

Note 5

A

Notes 5, 12

Note 9

mA

A/µs

dI_CC/dt

V_CCpower supply current slew rate

400

Notes 6, 7

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. Processors will comply

with the I_{CCx max}specification for the current mode of operation.

,

2. Static voltage regulation includes: DC output initial voltage set point adjust, output ripple and noise, temperature

and warm up.

3.

4. I_{CCx max}

15, V_{CCT max}

I

_CCTis the current supply for the system bus buffers, including the on-die termination.

specifications are specified at V_CCstatic (typical) derived from the tolerances in Table 10 through Table

, Tjmax, and under maximum signal loading conditions.

,

5. Maximum I_CC,DPRSLPspecified at V_CC= 0.85 V.

6. Based on simulations and averaged over the duration of any change in current. Use to compute the maximum

inductance and reaction time of the voltage regulator. This parameter is not tested.

7. Maximum values specified by design/characterization at nominal V_CCand V_CCT

8. V_CCxmust be within this range under all operating conditions, including maximum current transients. V_CCxmust

return to within the static voltage specification, V_{CCx DC}, within 100 µs after a transient event.

.

,

9. VID leakage current is < 100 µA for VID voltages under 3.0 V.

10. Typical V_CCindicates the VID encoded voltage. Voltage supplied must conform to the load line specification

shown in Table 10 through Table 15.

11. Voltages are measured at the processor socket pin for the Micro-FCPGA part and at the package ball on the

Micro-FCBGA part.

12. This specification applies only to the Ultra Low Voltage Mobile Intel Pentium III Processor-M.

Mobile Intel^®Pentium ^®III Processor-M Datasheet

29

Electrical Specifications

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Table 10. V_CCTolerances for the Mobile Intel Pentium III Processor-M: VID = 1.40 V (Performance

Mode) and 1.15 V (Battery Optimized Mode)

Performance Mode

Battery Optimized Mode

I_CC(A)

V_CC(V)

I_CC(A)

V_CC(V)

Static

Transient

Typ

1.400

1.396

1.392

1.388

1.384

1.380

1.376

1.372

1.368

1.364

1.360

1.356

1.352

1.348

1.344

1.340

1.336

1.332

1.328

1.324

1.320

1.316

1.312

1.308

Min

Max

Min

Max

Typ

Min

Max

Min

Max

0.0

1.0

1.375

1.371

1.367

1.363

1.359

1.355

1.351

1.347

1.343

1.339

1.335

1.331

1.327

1.323

1.319

1.315

1.311

1.307

1.303

1.299

1.295

1.291

1.287

1.283

1.425

1.421

1.417

1.413

1.409

1.405

1.401

1.397

1.393

1.389

1.385

1.381

1.377

1.373

1.369

1.365

1.361

1.357

1.353

1.349

1.345

1.341

1.337

1.333

1.355

1.351

1.347

1.343

1.339

1.335

1.331

1.327

1.323

1.319

1.315

1.311

1.307

1.303

1.299

1.295

1.291

1.287

1.283

1.279

1.275

1.271

1.267

1.263

1.445

1.441

1.437

1.433

1.429

1.425

1.421

1.417

1.413

1.409

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

1.135

1.131

1.127

1.123

1.119

1.115

1.111

1.107

1.103

1.099

1.095

1.091

1.087

1.083

1.079

1.110

1.106

1.102

1.098

1.094

1.900

1.086

1.082

1.078

1.074

1.070

1.066

1.062

1.058

1.054

1.160 1.090

1.156 1.086

1.152 1.082

1.148 1.078

1.144 1.074

1.140 1.070

1.136 1.066

1.132 1.062

1.128 1.058

1.124 1.054

1.120 1.050

1.116 1.046

1.112 1.042

1.108 1.038

1.104 1.034

1.180

1.176

1.172

1.168

1.164

1.160

1.156

1.152

1.148

1.144

1.140

1.136

1.132

1.128

1.124

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

11.0

12.0

13.0

14.0

15.0

16.0

17.0

18.0

19.0

20.0

21.0

22.0

23.0

1.405 10.0

1.401 11.0

1.397 12.0

1.393 13.0

1.389 14.0

1.385

1.381

1.377

1.373

1.369

1.365

1.361

1.357

1.353

30

Mobile Intel^®Pentium ^®III Processor-M Datasheet

Electrical Specifications

R

Figure 4. Illustration of V_CCStatic and Transient Tolerances (VID = 1.40 V)

1.500

Transient Maximum

1.450

Static Maximum

1.400

1.350

1.300

1.250

1.200

1.150

Static Typical

Static Minimum

Transient Minimum

Icc (A)

Mobile Intel^®Pentium ^®III Processor-M Datasheet

31

Electrical Specifications

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Table 11. V_CCTolerances for the Mobile Intel Pentium III Processor-M in the Deep Sleep State: VID

= 1.40 V (Performance Mode) and 1.15 V (Battery Optimized Mode)

Performance Mode

Battery Optimized Mode

I_CC(A)

V_CC(V)

I_CC(A)

V_CC(V)

Static

Transient

Min

Typ

1.338

1.334

1.330

1.326

1.322

1.318

1.314

1.310

1.306

Min

1.313

1.309

1.305

1.301

1.297

1.293

1.289

1.285

1.281

Max

Min

Max

Typ

1.084

1.080

1.076

1.072

1.068

1.064

1.060

Min

Max

1.129

1.125

1.121

1.117

1.113

1.109

1.105

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

1.363

1.359

1.355

1.351

1.347

1.343

1.339

1.335

1.331

1.293

1.289

1.285

1.281

1.277

1.273

1.269

1.265

1.261

1.383

1.379

1.375

1.371

1.367

1.363

1.359

1.355

1.351

0.0

1.0

2.0

3.0

4.0

5.0

6.0

1.059

1.055

1.051

1.047

1.043

1.039

1.035

1.109

1.105

1.101

1.097

1.093

1.089

1.085

1.039

1.035

1.031

1.027

1.023

1.019

1.015

Figure 5. Illustration of Deep Sleep V_CCStatic and Transient Tolerances (VID Setting = 1.40 V)

1.430

Transient Maximum

Static Maximum

Static Typical

1.380

1.330

1.280

1.230

1.180

Transient Minimum

Static Minimum

0

1

2

3

4

5

6

7

8

Icc (A)

32

Mobile Intel^®Pentium ^®III Processor-M Datasheet

Electrical Specifications

R

Table 12. V_CCTolerances for the Low Voltage Mobile Intel Pentium III Processor-M: VID = 1.15 V

(Performance Mode) and 1.05 V (Battery Optimized Mode)

Performance Mode

Battery Optimized Mode

I_CC(A)

V_CC(V)

I_CC(A)

V_CC(V)

Static

Transient

Typ

1.150

1.146

1.142

1.138

1.134

1.130

1.126

1.122

1.118

1.114

1.110

1.106

1.102

1.098

1.094

1.090

Min

1.125

1.121

1.117

1.113

1.109

1.105

1.101

1.097

1.093

1.089

1.085

1.081

1.077

1.073

1.069

1.065

Max

Min

Max

Typ

Min

Max

Min

Max

0.0

1.0

1.175

1.171

1.167

1.163

1.159

1.155

1.151

1.147

1.143

1.139

1.135

1.131

1.127

1.123

1.119

1.115

1.105

1.101

1.097

1.093

1.089

1.085

1.081

1.077

1.073

1.069

1.065

1.061

1.057

1.053

1.049

1.045

1.195

1.191

1.187

1.183

1.179

1.175

1.171

1.167

1.163

1.159

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

1.036

1.032

1.028

1.024

1.020

1.016

1.012

1.008

1.004

1.000

0.996

1.011

1.007

1.003

0.999

0.995

0.991

0.987

0.983

0.979

0.975

0.971

1.061

1.057

1.053

1.049

1.045

1.041

1.037

1.033

1.029

1.025

1.021

0.991

0.987

0.983

0.979

0.975

0.971

0.967

0.963

0.959

0.955

0.951

1.081

1.077

1.073

1.069

1.065

1.061

1.057

1.053

1.049

1.045

1.041

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

11.0

12.0

13.0

14.0

15.0

1.155 10.0

1.151

1.147

1.143

1.139

1.135

Table 13. V_CCTolerances for the Low Voltage Mobile Intel Pentium III Processor-M in the Deep

Sleep State: VID = 1.15 V (Performance Mode) and 1.05 V (Battery Optimized Mode)

Performance Mode

Battery Optimized Mode

I_CC(A)

V_CC(V)

I_CC(A)

V_CC(V)

Static

Transient

Typ

1.114

1.110

1.106

1.102

1.098

1.094

1.090

Min

1.089

1.085

Max

1.139

1.135

Min

Max

Typ

1.016

1.012

1.008

1.004

1.000

0.996

Min

Max

Min

Max

0.0

1.0

2.0

3.0

4.0

5.0

6.0

1.069

1.065

1.061

1.057

1.053

1.049

1.045

1.159

1.155

1.151

1.147

1.143

1.139

1.135

0.0

1.0

2.0

3.0

4.0

5.0

0.991

0.987

0.983

0.979

0.975

0.971

1.041

1.037

1.033

1.029

1.025

1.021

0.958

0.954

0.950

0.946

0.942

0.938

1.061

1.057

1.053

1.049

1.045

1.041

1.081 1.131

1.077

1.073

1.069

1.065

1.127

1.123

1.119

1.115

Mobile Intel^®Pentium ^®III Processor-M Datasheet

33

Electrical Specifications

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Table 14. V_CCTolerances for the Ultra Low Voltage Mobile Intel Pentium III Processor-M: VID = 1.1

V (Performance Mode) and 0.95 V (Battery Optimized Mode)

Performance Mode

Battery Optimized Mode

I_CC(A)

V_CC(V)

I_CC(A)

V_CC(V)

Static

Transient

Typ

1.100

1.096

1.092

1.088

1.084

1.080

1.076

1.072

1.068

1.064

1.060

1.056

1.052

1.048

Min

Max

Min

Max

Typ

Min

Max

Min

Max

0.0

1.0

1.075

1.071

1.067

1.063

1.059

1.055

1.051

1.047

1.043

1.039

1.035

1.031

1.027

1.023

1.125

1.121

1.117

1.113

1.109

1.105

1.101

1.097

1.093

1.089

1.085

1.081

1.077

1.073

1.055

1.051

1.047

1.043

1.039

1.035

1.031

1.027

1.023

1.019

1.015

1.011

1.007

1.003

1.145

1.141

1.137

1.133

1.129

1.125

1.121

1.117

1.113

1.109

1.105

1.101

1.097

1.093

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0.938

0.934

0.930

0.926

0.922

0.918

0.914

0.910

0.906

0.913

0.909

0.905

0.901

0.897

0.893

0.889

0.885

0.881

0.963

0.959

0.955

0.951

0.947

0.943

0.939

0.935

0.931

0.893

0.889

0.885

0.881

0.877

0.873

0.869

0.865

0.861

0.983

0.979

0.975

0.971

0.967

0.963

0.959

0.955

0.951

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

11.0

12.0

13.0

Table 15. V_CCTolerances for the Ultra Low Voltage Mobile Intel Pentium III Processor-M in the

Deep Sleep State: VID = 1.1 V (Performance Mode) and 0.95 V (Battery Optimized Mode)

Performance Mode

Battery Optimized Mode

I_CC(A)

V_CC(V)

I_CC(A)

V_CC(V)

Static

Transient

Typ

Min

Max

Min

Max

Typ

Min

Max

Min

Max

0.0

1.0

2.0

3.0

4.0

5.0

1.068

1.064

1.060

1.056

1.052

1.048

1.043

1.039

1.035

1.031

1.027

1.023

1.093

1.089

1.085

1.081

1.077

1.073

1.023

1.019

1.015

1.011

1.007

1.003

1.113

1.109

1.105

1.101

1.097

1.093

0.0

1.0

2.0

3.0

4.0

0.922

0.918

0.914

0.910

0.906

0.897

0.893

0.889

0.885

0.881

0.947

0.943

0.939

0.935

0.931

0.865

0.861

0.857

0.853

0.849

0.967

0.963

0.959

0.955

0.951

34

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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R

Table 16. AGTL Signal Group DC Specifications

Symbol

Parameter

Min

-0.15

Max

Unit

Notes

V_IL

V_IH

Input Low Voltage

V_REF-0.2

V

Input High Voltage

V_REF+0.2 V_CCT

V

See V_CCT,maxin Table 9

Note 2

V_OH

Output High Voltage

—

V

R_ON

I_L

Output Low Drive Strength

Leakage Current for Inputs, Outputs and I/Os

16.67

100

Ω

Note 1

µA

NOTES:

1. Specification applies to leakage high only, for pins with on die R_TT, (0 < V_IN/OUT≤ V_CCT).

2. Refer to IBIS models for I/V characteristics.

Table 17. AGTL Bus DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

Note 1

V_CCT

Bus Termination Voltage

1.25

V

V_REF

R_TT

Input Reference Voltage

Bus Termination Strength

²/₃V_CCT– 2% ²/₃V_CCT²/₃V_CCT+ 2% V

±2%, Note 2

50

56

65

On-die R_TT, Note 3

Ω

NOTES:

1. Please refer to Table 9 for minimum and maximum values.

2.

3. The RESET# signal does not have an on-die R_TT. It requires an off-die 56.2 Ω ±1% terminating resistor

connected to V_CCT

V_REFshould be created from V_CCTby a voltage divider.

.

Mobile Intel^®Pentium ^®III Processor-M Datasheet

35

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Table 18. CLKREF, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes

V_IL15

Input Low Voltage, 1.5 V CMOS

–0.15

V_CMOSREFmin

– 300 mV

V

V_IL18

V_IH15

Input Low Voltage, 1.8 V CMOS

Input High Voltage, 1.5 V CMOS

–0.36

0.36

2.0

V

Notes 1, 2

V_CMOSREFmax

250 mV

+

Note 11

V_IH15PICD

Input High Voltage, 1.5 V PICD[1:0]

V_CMOSREFmax

200 mV

2.0

V

Note 12

V_IH18

V_OH15

V_OH33

V_OL33

V_OL

Input High Voltage, 1.8 V CMOS

Output High Voltage, 1.5 V CMOS

Output High Voltage, 3.3 V signals

Output Low Voltage, 3.3 V signals

Output Low Voltage

1.44

N/A

2.0

V

Notes 1, 2

1.615

3.465

0.8

V

All outputs are Open-drain

3.3V + 5%

V

0.3

V

Note 9

Note 4

Note 10

Note 7

Note 8

Note 3

Note 6

Note 5

V_CMOSREFCMOSREF Voltage

V_CLKREFCLKREF Voltage

0.90

1.10

1.312

0.4

V

1.187

V

V_ILVTTPWRInput Low Voltage, VTTPWRGD

V_IHVTTPWRInput High Voltage, VTTPWRGD

V

1.0

10

V

V_ILGHI

V_IHGHI

R_ON

I_OL

Input Low Voltage, GHI#

Input High Voltage, GHI#

0.2

V

30

Ω

mA

µA

Output Low Current

I_L

Leakage Current for Inputs, Outputs

and I/Os

±100

NOTES:

1. Parameter applies to the PWRGOOD signal only.

2.

V

_ILx,minand V_IHx,maxonly apply when BCLK, BCLK# and PICCLK are stopped. PICCLK should be stopped in the

low state. See Table 30 and Table 31 for DC levels when BCLK and BCLK# are stopped.

3. Measured at 9 mA.

4.

V

_CMOSREFshould be created from a stable 1.5-V supply using a voltage divider. It must track the voltage supply

to maintain noise immunity. The same 1.5-V supply should be used to power the chipset CMOS I/O buffers that

drive these signals.

5. (0 ≤ _VIN/OUT≤ V_IHx,max).

6. Specified as the minimum amount of current that the output buffer must be able to sink. However, V_OL,maxcannot

be guaranteed if this specification is exceeded.

7. Parameter applies to VTTPWRGD signal only.

8. Parameter applies to GHI# signal only.

9. Applies to non-AGTL signals except BCLK, PWRGOOD, PICCLK, BSEL[1:0], VID[4:0].

10. ±5% DC tolerance. CLKREF must be generated from the same 2.5-V supply used to generate the BCLK signal.

AC Tolerance must be less than –40 dB at 1 MHz. The CLKREF DC spec only applies to platforms supporting

single-ended clocking.

11. Applies to all TAP and CMOS signals (not to APIC signals).

12. Applies to PICD[1:0].

36

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Electrical Specifications

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3.7

AC Specifications

3.7.1

System Bus, Clock, APIC, TAP, CMOS, and Open-

drain AC Specifications

All system bus AC specifications for the AGTL signal group are relative to the crossing point of the

rising edge of the BCLK input and falling edge of the BCLK# input. All AGTL timings are referenced

to V_REFfor both “0” and “1” logic levels unless otherwise specified. All APIC, TAP, CMOS, and

Open-drain signals except PWRGOOD are referenced to 1.0 V. All minimum and maximum

specifications are at points within the power supply ranges shown in Table 9 through Table 15 and

junction temperatures (Tj) in the range 0°C to 100°C. Tj must be less than or equal to 100°C for all

functional processor states.

Table 19. System Bus Clock AC Specifications (Differential) ¹

Symbol

Parameter

Min

Typ

Max Unit Figure

Notes

System Bus Frequency

133

MH

z

T1

BCLK Period - average

7.5

7.3

7.7

ns

ps

8

Note 2

T1abs

T2

BCLK Period – Instantaneous minimum

BCLK Cycle to Cycle Jitter

BCLK Rise Time

Note 2

200

467

550

467

550

0.76

325

55%

Notes 2, 3, 4

Notes 2, 6, 8

Notes 2, 6, 9

Notes 2, 6, 8

Notes 2, 6, 9

Note 7

T5

175

0.51

T6

BCLK Fall Time

ps

8

Vcross for 1V swing

Rise/Fall Time Matching

BCLK Duty Cycle

V

7

8

ps

Note 5

45%

Note 2

NOTES:

1. All AC timings for AGTL and CMOS signals are referenced to the BCLK and BCLK# crossing point.

2. Measured on differential waveform: defined as (BCLK - BCLK#).

3. Not 100% tested. Specified by design/characterization.

4. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that the clock driver be

designed to meet a period stability specification into a test load of 10 to 20 pF. This should be measured on the

rising edge of adjacent BCLKs at the BCLK, BCLK# crossing point. The jitter present must be accounted for as

a component of BCLK skew between devices. Period difference is measured around 0 V crossing points.

5. Measurement taken from common mode waveform, measure rise/fall time from 0.41 to 0.86 V. Rise/fall time

matching is defined as “the instantaneous difference between maximum BCLK rise (fall) and minimum BCLK#

fall (rise) time, or minimum BCLK rise (fall) and maximum BCLK# fall (rise) time ”. This parameter is designed to

guard waveform symmetry.

6. Rise time is measured from -0.35 V to 0.35 V and fall time is measured from 0.35 V to -0.35 V.

7. Measured on common mode waveform - includes every rise/fall crossing.

8. Measured at the package ball for the Micro-FCBGA package.

9. Measured at the socket pin for the Micro-FCPGA package.

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Electrical Specifications

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Table 20. System Bus Clock AC Specifications (133 MHz, Single Ended) ¹

Symbol

Parameter

Min

Max Unit

Figure

Notes

System Bus Frequency

BCLK Period

133

MHz

T1S

7.5

7.65

ns

6

Note 2

T1Sabs BCLK Period – Instantaneous

Minimum

7.25

T2S

T3S

BCLK Period Stability

BCLK High Time

BCLK Low Time

BCLK Rise Time

BCLK Fall Time

±250 ps

Notes 2, 3, 4

at>2.0V

at<0.5V

Note 5

1.4

0.4

ns

6

T4S

T5S

1.6

ns

T6S

Note 5

NOTES:

1. All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25 V.

2. Period, jitter, skew and offset measured at 1.25 V.

3. Not 100% tested. Specified by design/characterization.

4. Measured on the rising edge of adjacent BCLKs at 1.25 V. The jitter present must be accounted for as a

component of BCLK skew between devices.

5. Measured between 0.5 V and 2.0 V.

Table 21. System Bus Clock AC Specifications (100 MHz, Single Ended)¹

Symbol

Parameter

Min

Typ

Max

Unit

Figure

Notes

System Bus Frequency

BCLK Period

100

10

MHz

T1S1

ns

6

Note 2

T1S1abs BCLK Period – Instantaneous

Minimum

9.75

T2S1

T3S1

BCLK Period Stability

BCLK High Time

BCLK Low Time

BCLK Rise Time

BCLK Fall Time

±250 ps

Notes 2, 3, 4

at>2.0 V

at<0.5 V

Note 5

2.70

2.45

0.4

ns

6

T4S1

T5S1

1.6

ns

T6S1

0.4

Note 5

NOTES:

1. All AC timings for AGTL and CMOS signals are referenced to the BCLK rising edge at 1.25 V.

2. Period, jitter, skew and offset measured at 1.25 V.

3. Not 100% tested. Specified by design/characterization.

4. Measured on the rising edge of adjacent BCLKs at 1.25 V. The jitter present must be accounted for as a

component of BCLK skew between devices.

5. Measured between 0.5 V and 2.0 V.

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Electrical Specifications

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Table 22. Valid Mobile Intel Pentium III Processor-M Frequencies

BCLK Frequency

(MHz)

Frequency Multiplier

Core Frequency

(MHz)

Power-on Configuration

Bits [27,25:22]

100

133

3

3.5

4

300

350

400

450

500

700

750

800

850

400

466

533

667

733

800

866

933

1000

1066

1133

1200

1266

1333

0, 0001

0, 0101

0, 0010

0, 0110

0, 0000

0, 1001

0, 1101

0, 1010

1, 0110

0, 0001

0, 0101

0, 0010

0, 0000

0, 0100

0, 1011

0, 1111

0, 1001

0, 1101

0, 1010

1, 0110

1, 0000

1, 0100

1, 1011

4.5

5

7

7.5

8

8.5

3

3.5

4

5

5.5

6

6.5

7

7.5

8

8.5

9

9.5

10.0

NOTE: While other combinations of bus and core frequencies are defined, operation at frequencies other than

those listed above will not be validated by Intel and are not guaranteed. The frequency multiplier is

programmed into the processor when it is manufactured and it cannot be changed.

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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Electrical Specifications

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Table 23. AGTL Signal Groups AC Specifications¹

R_TT= 56 Ω internally terminated to V_CCT; V_REF= ²/₃V_CCT; load = 50 ohms

Symbol

Parameter

Min

Max

Unit

Figure

Notes

T7

AGTL Output Valid Delay

AGTL Input Setup Time

0.40

3.25 ns

ns

9

T8

0.95

1.30

1

10

Notes 2, 3, 6

Note 7

T9

AGTL Input Hold Time

RESET# Pulse Width

ns

10

Note 4

T10

1

ms

11,12

Note 5

NOTES:

1. All AC timings for AGTL signals are referenced to the crossing point of the BCLK rising edge and the BCLK#

falling edge for Differential Clocking and to the BCLK rising edge at 1.25 V for Single Ended Clocking. All AGTL

signals are referenced at V

frequencies.

. Unless other specified, all timings apply to both 100 and 133 MHz bus

REF

2. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.

3. Specification is for a minimum 0.40-V swing from Vref-200 mV to Vref+200 mV.

4. Specification is for a maximum 0.8-V swing from Vcct-0.8 V to Vcct.

5. After V , V

, and BCLK, BCLK# become stable and PWRGOOD is asserted.

CC

CCT

6. Applies to processors supporting 133-MHz bus clock frequency except Ultra Low Voltage processors.

7. Applies to processors supporting 100-MHz bus clock frequency and Ultra Low Voltage processors supporting

133-MHz bus clock frequency.

Table 24. CMOS and Open-drain Signal Groups AC Specifications^{1, 2}

Symbol

Parameter

Min Max Unit

Figure

Notes

T14

1.5V Input Pulse Width, except PWRGOOD and

LINT[1:0]

2

BCLKs 11

Active and inactive

states

T14B

T15

LINT[1:0] Input Pulse Width

6

2

BCLKs 11

12

Note 3

PWRGOOD Inactive Pulse Width

Note 4, 5

µs

NOTES:

1. All AC timings for CMOS and Open-drain signals are referenced to the crossing point of the BCLK rising edge

and BCLK# falling edge for Differential Clocking and to the rising edge of BCLK at 1.25V for Single Ended

Clocking. All CMOS and Open-drain signals are referenced at 1.0 V.

2. Minimum output pulse width on CMOS outputs is 2 BCLKs.

3. This specification only applies when the APIC is enabled and the LINT1 or LINT0 signal is configured as an

edge triggered interrupt with fixed delivery, otherwise specification T14 applies.

4. When driven inactive, or after V_CC, V_CCTand BCLK, BCLK# become stable. PWRGOOD must remain below

V_IL18,MAXuntil all the voltage planes meet the voltage tolerance specifications in Table 9 through Table 15 and

BCLK, BCLK# have met the BCLK, BCLK# AC specifications in Table 30 and Table 31 for at least 2 µs.

PWRGOOD must rise error-free and monotonically to 1.8 V.

5. If the BCLK Settling Time specification (T60) can be guaranteed at power-on reset then the PWRGOOD

Inactive Pulse Width specification (T15) is waived and BCLK may start after PWRGOOD is asserted.

PWRGOOD must still remain below V_IL18,maxuntil all the voltage planes meet the voltage tolerance

specifications.

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Table 25. Reset Configuration AC Specifications and Power On/Power Down Timings

Symbol

Parameter

Min Typ Max Unit Figure

Notes

11

T16

Reset Configuration Signals (A[15:5]#,

BREQ0#, FLUSH#, INIT#, PICD0) Setup

Time

4

BCLKs

Before deassertion of

RESET#

11

12

T17

T18

Reset Configuration Signals (A[15:5]#,

2

1

20

BCLKs

ms

After clock that

BREQ0#, FLUSH#, INIT#, PICD0) Hold Time

deasserts RESET#

RESET#/PWRGOOD Setup Time

Before deassertion of

RESET# ¹

T18A

T18B

T18C

VCCT to VTTPWRGD Setup Time

VCC to PWRGOOD Setup Time

ms

µs

12

10

BSEL, VID valid time before VTTPWRGD

assertion

1

T18D

T18E

T19A

RESET# inactive to Valid Outputs

RESET# inactive to Drive Signals

1

4

BCLK 11

BCLKs 11

Time from VCC(nominal)-12% to PWRGOOD

low

0

ns

13

VCC(nominal) is the VID

voltage setting

T19B

T19C

T20A

T20B

T20C

T20D

All outputs valid after PWRGOOD low

0

ns

13

14

All inputs required valid after PWRGOOD low 0

Time from VCCT-12% to VTTPWRGD low

All outputs valid after VTTPWRGD low

0

All inputs required valid after VTTPWRGD low 0

VID, BSEL signals valid after VTTPWRGD

low

0

T20E

VTTPWRGD Transition Time

100

Measurement from 300

mV to 900 mV. Amount

of noise (glitch) less

than 100 mV. See

µs

Section 4.3.1 for details

NOTE: At least 1 ms must pass after PWRGOOD rises above V_IH18minand BCLK, BCLK# meet their AC timing

specification until RESET# may be deasserted.

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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Electrical Specifications

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Table 26. APIC Bus Signal AC Specifications ¹

Symbol

Parameter

Min

Max

33.3

500

Unit

Figure

Notes

Note 2

T21

T22

PICCLK Frequency

PICCLK Period

2

MHz

ns

30

6

T23

T24

T25

T26

T27

T28

T29

PICCLK High Time

PICCLK Low Time

PICCLK Rise Time

PICCLK Fall Time

PICD[1:0] Setup Time

PICD[1:0] Hold Time

10.5

0.25

8.0

ns

6

9

8

at>1.6 V

at<0.4 V

(0.4 V – 1.6 V)

(1.6 V – 0.4 V)

Note 3

3.0

2.5

1.5

Note 3

Notes 3, 4

PICD[1:0] Valid Delay (Rising

Edge)

8.7

PICD[1:0] Valid Delay (Falling

1.5

12.0

Edge)

NOTES:

1. All AC timings for APIC signals are referenced to the PICCLK rising edge at 1.0 V. All CMOS signals are

referenced at 1.0 V.

2. The minimum frequency is 2 MHz when PICD0 is at 1.5 V at reset Referenced to PICCLK Rising Edge.

3. For Open-drain signals, Valid Delay is synonymous with Float Delay.

4. Valid delay timings for these signals are specified into 150 Ω to 1.5 V and 0 pF of external load. For real system

timings these specifications must be derated for external capacitance at 105 ps/pF.

42

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Table 27. TAP Signal AC Specifications¹

Symbol

Parameter

Min Max Unit Figure

Notes

T30

T31

T32

T33

T34

TCK Frequency

—

16.67 MHz

TCK Period

60

—

ns

6

TCK High Time

TCK Low Time

TCK Rise Time

25.0

≥ V_CMOSREF+0.2 V, Note 2

≤ V_CMOSREF-0.2 V, Note 2

(V_CMOSREF-0.2 V) –

(V_CMOSREF+0.2 V),

Notes 2, 3

5.0

T35

TCK Fall Time

ns

6

(V_CMOSREF+0.2 V) –

(V_CMOSREF-0.2 V) ,

Notes 2, 3

T36

T37

TRST# Pulse Width

40.0

5.0

ns

16

15

Asynchronous, Note 2

Note 4

TDI, TMS Setup Time

T38

TDI, TMS Hold Time

14.0

Note 4

T39

TDO Valid Delay

1.0 10.0 ns

25.0 ns

Notes 5, 6

T40

TDO Float Delay

Notes 2, 5, 6

Notes 5, 7, 8

Notes 2, 5, 7, 8

Notes 4, 7, 8

T41

All Non-Test Outputs Valid Delay

All Non-Test Outputs Float Delay

All Non-Test Inputs Setup Time

All Non-Test Inputs Hold Time

2.0 25.0 ns

25.0 ns

T42

T43

5.0

ns

T44

13.0

NOTES:

1. All AC timings for TAP signals are referenced to the TCK rising edge at 1.0 V. All TAP and CMOS signals are

referenced at 1.0 V.

2. Not 100% tested. Specified by design/characterization.

3. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.

4. Referenced to TCK rising edge.

5. Referenced to TCK falling edge.

6. Valid delay timing for this signal is specified into 150 Ω terminated to 1.5 V and 0 pF of external load. For real

system timings these specifications must be derated for external capacitance at 105 ps/pF.

7. Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO, and TMS).

These timings correspond to the response of these signals due to boundary scan operations.

8. During Debug Port operation use the normal specified timings rather than the TAP signal timings.

Table 28. Quick Start/Deep Sleep AC Specifications¹

Symbol

Parameter

Min Max Unit

Figure

Notes

T45

Quick Start Cycle Completion to Clock Stop or

DPSLP# assertion

100

BCLKs 17, 18

T46

T47

Quick Start Cycle Completion to Input Signals Stable

Deep Sleep PLL Lock Latency

0

17, 18

µs

ns

0

8

30

17, 18

Note 2

T48

STPCLK# Hold Time from PLL Lock

T49

Input Signal Hold Time from STPCLK# Deassertion

BCLKs 17, 18

NOTES:

1. Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.

2. The BCLK, BCLK# Settling Time specification (T60) applies to Deep Sleep state exit under all conditions.

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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Electrical Specifications

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Table 29. Enhanced Intel SpeedStep Technology AC Specifications

Symbol

Parameter

Min Max Unit Figure

Notes

T57

GHI# Setup Time from BCLK Restart or DPSLP# 150

deassertion

ns

19

Note 1

T58

T59

GHI# Hold Time from BCLK Restart or DPSLP# 30

deassertion

19

µs

GHI# Sample Delay

BCLK Settling Time

10

19

µs

T60

150

ns

Notes 2, 3

NOTES:

1. GHI# is ignored until 10 µs after BCLK, BCLK# stop or DPSLP# assertion, the setup and hold window must

occur after this time.

2. BCLK, BCLK# must meet the BCLK AC specification from within 150 ns of turning on (rising above V_IL,BCLK).

3. This specification applies to the exit from the Deep Sleep state whether or not an Enhanced Intel SpeedStep

technology operating mode transition occurs.

Figure 6. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform

T

h

T

r

V_H

V_TRIP

CLK

V_L

T

f

T

l

T

p

D0003-01

NOTES:

T =T5S, T5S1, T34, T25 (Rise Time)

r

f

T =T6S, T6S1, T35, T26 (Fall Time)

T =T3S, T3S1, T32, T23 (High Time)

h

T =T4S, T4S1, T33, T24 (Low Time)

l

T =T1S, T1S1, T31, T22 (Period)

p

V_TRIP=1.25V for BCLK (Single Ended);1.0V for PICCLK; 1.0V for TCK

V_L=0.5V for BCLK (Single Ended);0.4V for PICCLK; (V_CMOSREF-0.2V) for TCK

V_H=2.0V for BCLK (Single Ended);1.6V for PICCLK; (V_CMOSREF+0.2V) for TCK

Figure 7. Differential BCLK/BCLK# Waveform (Common Mode)

V2,V3 (max)

BCLK#

Vcross

BCLK

V1,V3 (min)

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Figure 8. BCLK/BCLK# Waveform (Differential Mode)

T1

V_{IH_DIFF}

V4

0V

V5

V_{Il_DIFF}

T5

T6

Figure 9. Valid Delay Timings

Vc

Tx

CLK

T_X

V

Valid

Signal

T_PW

D0004-00

NOTES:

T

= T7, T11, T29 (Valid Delay)

= T14, T14B (Pulse Width)

x

pw

V

= V

for AGTL signal group; 1.0 V for CMOS, Open-drain, APIC, and TAP signal groups

REF

Vc = Crossing point of BCLK rising edge and BCLK# falling edge for BCLK references (Differential Clock)

1.25 V (Single Ended Clock)

=

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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Electrical Specifications

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Figure 10. Setup and Hold Timings

Vc

CLK

Ts

T

h

V Valid

Signal

D0005-00

NOTES:

T = T8, T12, T27 (Setup Time)

s

h

T = T9, T13, T28 (Hold Time)

V = V

for AGTL signals; 1.0V for CMOS, APIC, and TAP signals

REF

Vc = Crossing point of BCLK rising edge and BCLK# falling edge for BCLK references (Differential Clock)

= 1.25V (Single Ended Clock)

Figure 11. Cold/Warm Reset and Configuration Timings

V

C

BCLK

T

u

T

t

RESET#

V

T

v

T

x

w

Configuration

(A[15:5], BREQ0#,

FLUSH#, INIT#,

PICD0)

Valid

T

y

PICD[1:0]

AGTL/non-AGTL

outputs

Valid

T

z

Non-configuration

inputs

Active

D0006-02

NOTES:

T = T9 (AGTL Input Hold Time)

t

u

T = T8 (AGTL Input Setup Time)

T = T10 (RESET# Pulse Width)

v

T = T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Setup Time)

w

T = T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Hold Time)

x

Ty = T18D (RESET# inactive to Valid Outputs)

Tz = T18E (RESET# inactive to Drive Signals)

Vc= Crossing point of BCLK rising edge and BCLK# falling edge (Differential Clock)

= 1.25V (Single Ended Clock)

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Figure 12. Power-on Sequence and Reset Timings

BCLK/BCLK#

V_CCT

T

d

V_IHVTTPWR,min

VTTPWRGD

V_ILVTTPWR,max

T

e

VID[4:0]/

Valid

BSEL[1:0]

CMOSREF/

CLKREF/V_REF

V_CC

PWRGOOD

RESET#

T

a

T

c

V_IH18,min

V_IL18,max

T

b

V0040-00

NOTES:

T_a= T15 (PWRGOOD Inactive Pulse Width)

T_b= T18 (RESET#/PWRGOOD Setup Time)

T_c= T18B (Setup time from V

valid until PWRGOOD assertion)

valid to VTTPWRGD assertion)

CC

T_d= T18A (Setup time from V

CCT

T_e= T18C(VID, BSEL valid time before VTTPWRGD assertion)

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Figure 13. Power Down Sequencing and Timings (VCC Leading)

V_CCT,V_REF

V_CCMOS,

CMOSREF,

CLKREF

VID[4:0]

BSEL[1:0]

VTTPWRGD

VCC-12%

VCC

BCLK/BCLK#

Valid

PICCLK

T_a

V

PWRGOOD

RESET#

IL18

PICD[1:0]

Valid

T_b

AGTL OUTPUTS

OTHER CMOS OUTPUTS

ALL INPUTS

T_c

V0044-00

NOTES:

T_a= T19A (Time from VCC(nominal)-12% to PWRGOOD low)

T_b= T19B (All outputs valid after PWRGOOD low)

T_c= T19C (All inputs required valid after PWRGOOD low)

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Figure 14.Power Down Sequencing and Timings (V_CCTLeading)

V_CCT-12%

V_CCT,V_REF

V_CMOS,

CMOSREF,

CLKREF

T_a

VTTPWRGD

V

ILVTTPWR

VID[4:0]

Valid

BSEL[1:0]

VCC

T_b,T T_d

c,

BCLK/BCLK#

Valid

PICCLK

PWRGOOD

RESET#

PICD[1:0]

Valid

AGTL OUTPUTS

OTHER CMOS OUTPUTS

ALL INPUTS

V0045-00

NOTES:

T_a= T20A (Time from VCCT-12% to VTTPWRGD low)

T_b= T20B (All outputs valid after VTTPWRGD low)

T_c= T20C (All inputs required valid after VTTPWRGD low)

T_d= T20D (VID, BSEL signals valid after VTTPWRGD low)

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Figure 15.Test Timings (Boundary Scan)

TCK

T

v

T

w

0.75V

TDI, TMS

T

r

T

s

Input

Signals

T

x

T

u

TDO

T

y

T

z

Output

Signals

D0008-01

NOTES:

T =T43 (All Non-Test Inputs Setup Time)

r

s

T =T44 (All Non-Test Inputs Hold Time)

T =T40 (TDO Float Delay)

u

T =T37 (TDI, TMS Setup Time)

v

T =T38 (TDI, TMS Hold Time)

w

T =T39 (TDO Valid Delay)

x

T =T41 (All Non-Test Outputs Valid Delay)

y

T =T42 (All Non-Test Outputs Float Delay)

z

Figure 16. Test Reset Timings

0.75V

TRST#

T

q

D0009-01

NOTE:

T =T36 (TRST# Pulse Width)

q

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Electrical Specifications

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Figure 17. Quick Start/Deep Sleep Timing (BCLK Stopping Method)

Normal

Quick Start

Deep Sleep

Stopped

Normal

Quick Start

BCLK

T_v

STPCLK#

T_y

T_x

CPU bus

DPSLP#

stpgnt

T_z

T_w

Changing

Compatibility

Signals

Frozen

V00102-00

NOTES:

T =T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay)

v

w

T =T46 (Setup Time to Input Signal Hold Requirement)

T =T47 (Deep Sleep PLL Lock Latency)

x

T =T48 (PLL lock to STPCLK# Hold Time)

y

T =T49 (Input Signal Hold Time)

z

Figure 18. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method)

Normal

Quick Start

Deep Sleep

Normal

Quick Start

BCLK

T_v

STPCLK#

T_y

T_x

CPU bus

DPSLP#

stpgnt

T_z

T_w

Changing

Compatibility

Signals

Frozen

V00103-00

NOTES:

T =T45 (Stop Grant Acknowledge Bus Cycle Completion to DPSLP# assertion)

v

w

T =T46 (Setup Time to Input Signal Hold Requirement)

T =T47 (Deep Sleep PLL Lock Latency)

x

T =T48 (PLL lock to STPCLK# Hold Time)

y

T =T49 (Input Signal Hold Time)

z

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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Figure 19. Enhanced Intel SpeedStep Technology/Deep Sleep Timing

BCLK on

(in spec)

BCLK on and DPSLP# de-asserted

BCLK on

BCLK off or

DPSLP#

(out of spec)

asserted

Vc

BCLK

V

ILBC

LK

T_x

T_s

Vghi

T_y

T_h

GHI#

V0036-00

NOTES:

T =T57 (GHI# Setup Time from BCLK Restart)

s

h

T =T58 (GHI# Hold Time from BCLK Restart)

T =T59 (GHI# Sample Delay)

x

T =T60 (BCLK Settling Time)

y

Vc = Crossing point of BCLK rising edge and BCLK# falling edge (Differential Clocking)

= 1.25 V (Single Ended Clocking)

Vghi = GHI# reference voltage = V_CCT/2

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4. System Signal Simulations

Systems must be simulated using IBIS models to determine if they are compliant with this

specification. All references to BCLK signal quality also apply to BCLK# for Differential Clocking.

4.1

System Bus Clock (BCLK) and PICCLK DC

Specifications and AC Signal Quality

Specifications

Table 30. BCLK (Differential) DC Specifications and AC Signal Quality Specifications

Symbol

Parameter

Min

-0.2

0.92 1.45

Max

Unit Figure

Notes

V1

V_IL,BCLK

V_IH,BCLK

0.35

V

7

8

Note 1

V2

V3

V4

V5

V_INAbsolute Voltage Range

BCLK Rising Edge Ringback

BCLK Falling Edge Ringback

-0.2

1.45

Undershoot/Overshoot, Note 2

0.35

Note 3

Note 4

-0.35

1.45

V_{BCLK_DPSLP}BCLK Voltage in Deep Sleep

State

0.4

0

V_{BCLK#_DPSLP}BCLK# Voltage in Deep Sleep

State

V_{BCLK_DPSLP}

- 0.2V

V

Note 4

NOTES:

1. The clock must rise/fall monotonically between VIL,BCLK and VIH,BCLK .

2. These specifications apply only when BCLK, BCLK# are running.

3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) voltage the

differential waveform can go to after passing the VIH_DIFF (rising) or VIL_DIFF (falling) levels. VIL_DIFF (max)

= -0.57 V, VIH_DIFF (min) = 0.57 V.

4.

Applies when BCLK and BCLK# are stopped in Deep Sleep State.

Table 31. BCLK (Single Ended) DC Specifications and AC Signal Quality Specifications

Symbol

Parameter

Min Max Unit

Figure

Notes

V1

V_IL,BCLK

V_IH,BCLK

0.3

3.1

0.5

V

20

Note 1

V2

V3

2.2

-0.5

2.0

20

V_INAbsolute Voltage Range

BCLK Rising Edge Ringback

BCLK Falling Edge Ringback

Undershoot/Overshoot, Note 2

Absolute Value, Note 3

V4

V5

NOTES:

1. The clock must rise/fall monotonically between V_IL,BCLKand V_IH,BCLK. BCLK must be stopped in the low state.

2. These specifications apply only when BCLK is running. BCLK may not be above V_IH,BCLK,maxor below V_IL,BCLK,min

for more than 50% of the clock cycle.

3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute

voltage the BCLK signal can go to after passing the V_IH,BCLK(rising) or V_IL,BCLK(falling) voltage limits.

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Table 32. PICCLK DC Specifications and AC Signal Quality Specifications

Symbol

Parameter

Min Max Unit Figure

Notes

V1

V_IL20

V_IH20

0.4

V

20

Note 1

V2

V3

1.6

-0.5 2.4

Note 1

V_INAbsolute Voltage Range

Undershoot, Overshoot, Note 2

Absolute Value, Note 3

V4

V5

PICCLK Rising Edge Ringback 1.6

PICCLK Falling Edge Ringback

0.4

NOTES:

1. The clock must rise/fall monotonically between V_IL20and V_IH20

.

2. These specifications apply only when PICCLK is running. See the DC specifications for when PICCLK is

stopped. PICCLK may not be above V_IH20,maxor below V_IL20,minfor more than 50% of the clock cycle.

3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute

voltage the PICCLK signal can go to after passing the V_IH20(rising) or V_IL20(falling) voltage limits.

Figure 20. BCLK (Single Ended)/PICCLK Generic Clock Waveform

V3_max

V4

V2

V1

V5

V3_min

V0012-01

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4.2

AGTL AC Signal Quality Specifications

Ringback specifications for the AGTL signals are as follows:

Ringback below V_REF,max+ 200 mV is not authorized during low to high transitions. Ringback above

V_REF,min– 200 mV is not authorized during high to low transitions.

Overshoot and undershoot specifications are documented in Table 33 and Table 34 and illustrated in

Figure 21.

Figure 21. Maximum Acceptable Overshoot/Undershoot Waveform

Time Dependant Overshoot

Max

Vss

Min

Time Dependant Undershoot

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Table 33. 133-MHz AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core

Allowed Pulse Duration (ns) [Tj=100C]

Max V_CCT+ Overshoot/Undershoot

Magnitude (volts)

Activity Factor = 0.01 Activity Factor = 0.1

Activity Factor = 1

1.78

1.73

1.68

1.63

1.58

1.53

1.48

1.5

3.5

7.2

15

0.15

0.35

0.72

1.5

0.015

0.035

0.072

0.15

15

3.2

6.5

0.32

0.65

15

14

1.40

NOTES:

1. Under no circumstances should the sum of the Max V_CCTand absolute value of the Overshoot/Undershoot

voltage exceed 1.78 V.

2. Activity factor of 1 represents the same toggle rate as the 133-MHz clock.

3. Ringbacks below V_CCTcannot be subtracted from overshoots. Lesser undershoot does not allocate longer or

larger overshoot.

4. Ringbacks above ground cannot be subtracted from undershoots. Lesser overshoot does not allocate longer or

larger undershoot.

5. System designers are encouraged to follow Intel provided AGTL layout guidelines.

6. All values are specified by design characterization and are not tested.

Table 34. 100-MHz AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core

Allowed Pulse Duration (ns) [Tj=100C]

Max V_CCT+ Overshoot/Undershoot

Magnitude (volts)

Activity Factor = 0.01 Activity Factor = 0.1

Activity Factor = 1

1.78

1.73

1.68

1.63

1.58

1.53

1.48

1.6

4.5

9.5

20

0.16

0.45

0.95

2.0

0.016

0.045

0.095

0.2

20

4.2

8.5

0.42

0.85

1.9

20

19

NOTES:

1. Under no circumstances should the sum of the Max V_CCTand absolute value of the Overshoot/Undershoot

voltage exceed 1.78 V.

2. Activity factor of 1 represents the same toggle rate as the 100-MHz clock.

3. Ringbacks below V_CCTcannot be subtracted from overshoots. Lesser undershoot does not allocate longer or

larger overshoot.

4. Ringbacks above ground cannot be subtracted from undershoots. Lesser overshoot does not allocate longer or

larger undershoot.

5. System designers are encouraged to follow Intel provided AGTL layout guidelines.

6. All values are specified by design characterization and are not tested.

4.3

Non-AGTL Signal Quality Specifications

Signals driven to the Mobile Intel Pentium III Processor-M should meet signal quality specifications to

ensure that the processor reads data properly and that incoming signals do not affect the long-term

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reliability of the processor. The overshoot and undershoot specifications for non-AGTL signals are

shown in Table 35. Ringback must not exceed the CMOS V_IHand V_ILspecification levels in Table 18.

Table 35. Non-AGTL Signal Group Overshoot/Undershoot Tolerance at the Processor Core

Allowed Pulse Duration (ns) [Tj=100C]

Max V_Cmos+ Overshoot/Undershoot

Magnitude (volts)

Activity Factor = 0.01 Activity Factor = 0.1 Activity Factor = 1

2.38

2.33

2.28

2.23

2.18

2.13

2.08

6.5

13

29

60

0.65

1.3

2.9

6

0.065

0.13

0.29

0.6

12

26

1.2

2.6

56

5.6

NOTES:

1. V_CMOS(nominal) = 1.5 V.

2. Under no circumstances should the sum of the Max V_CMOSand absolute value of the Overshoot/Undershoot

voltage exceed 2.38 V.

3. Activity factor of 1 represents a toggle rate of 33 MHz.

4. System designers are encouraged to follow Intel provided non-AGTL layout guidelines.

5. All values are specified by design characterization, and are not tested.

4.3.1

PWRGOOD, VTTPWRGD Signal Quality Specifications

The processor requires PWRGOOD to be a clean indication that clocks and the power supplies (V_CC,

V

_CCT, etc.) are stable and within their specifications. Clean implies that the signal will remain below

_IL18and without errors from the time that the power supplies are turned on, until they come within

specification. The signal will then transition monotonically to a high (1.8 V) state. The VTTPWRGD

signal must also transition monotonically.

The VTTPWRGD signal is an input to the processor used to determine that the VTT power is stable

and the VID and BSEL signals should be driven to their final state by the processor. To ensure the

processor correctly reads this signal, it must meet the requirements shown in Table 36 while the signal

is in its transition region of 300 mV to 900 mV. Also, VTTPWRGD should only enter the transition

region once, after VTT is at nominal values, for the assertion of the signal.

4.3.1.1.1

VTTPWRGD Noise Parameter Specification

Table 36. VTTPWRGD Noise Parameter Specification

Parameter

Specification

Amount of noise (glitch)

Less than 100 mV

In addition, the VTTPWRGD signal should have reasonable transition time through the transition

region. A sharp edge on the signal transition will minimize the chance of noise causing a glitch on this

signal. Intel recommends the following transition time for the VTTPWRGD signal.

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4.3.1.2

VTTPWRGD Transition Parameter Recommendation

Table 37. VTTPWRGD Transition Parameter Recommendation

Parameter

Recommendation

Transition time (300 mV to 900 mV)

Less than or equal to 100 µs

In addition, the VTT_PWRGD signal should have reasonable transition time through the transition

region. A sharp edge on the signal transition will minimize the chance of noise causing a glitch on this

signal. Intel recommends the following transition time for the VTT_PWRGD signal.

4.3.1.2.1

Transition Region

The transition region covered by this requirement is 300 mV to 900 mV. Once the VTTPWRGD signal

is in that voltage range, the processor is more sensitive to noise, which may be present on the signal.

The transition region when the signal first crosses the 300 mV voltage level and continues until the last

time it is below 900 mV.

4.3.1.2.2

4.3.1.2.3

Transition Time

The transition time is defined as the time the signal takes to move through the transition region. A

100-µs transition time will ensure that the processor receives a good transition edge.

Noise

The signal quality of the VTTPWRGD signal is critical to the correct operation of the processor. Every

effort should be made to ensure this signal is monotonic in the transition region. If noise or glitches are

present on this signal, the noise or glitches must be kept to less than 100 mV of a voltage drop from the

highest voltage level received to that point. This glitch must remain less than 100 mV until the

excursion ends by the voltage returning to the highest voltage previously received. Please see Figure

22 for an example graph of this situation and requirements.

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Figure 22. VTTPWRGD Noise Specification

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Mechanical Specifications

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5. Mechanical Specifications

5.1

Socketable Micro-FCPGA Package

The Mobile Intel Pentium III Processor-M is packaged in a 478-pin Micro-FCPGA package. The Low

Voltage and Ultra Low Voltage processors will not be available in this package. The mechanical

specifications for the socketable package are provided in Table 38. Figure 23 through Figure 25

illustrate different views of the package.

Table 38. Socketable Micro-FCPGA Package Specification

Symbol

Parameter

Min

1.81

4.69

1.95

Max

2.03

5.15

2.11

Unit

A

Overall height, top of die to package seating plane

Overall height, top of die to PCB surface, including socket(1)

mm

-

A1

A2

A3

B

D

E

Pin length

Die height

0.854

Pin-side capacitor height

Pin diameter

Package substrate length

Package substrate width

Die length

-

1.25

0.36

35.1

3

0.28

34.9

D1

11.18

10.82

4

3

E1

Die width

mm

7.20

6.85

4

e

K

K1

Pin pitch

Package edge keep-out

Package corner keep-out

1.27

5

7

mm

K3

-

N

Pdie

W

Pin-side capacitor boundary

Pin tip radial true position

Pin count

Allowable pressure on the die for thermal solution

Package weight

14

<=0.254

478

mm

each

kPa

g

-

689

4.5

Package Surface Flatness

0.286

mm

NOTES:

1. All dimensions are subject to change.

2. Overall height with socket is based on design dimensions of the Micro-FCPGA package and socket with no

thermal solution attached. Values were based on design specifications and tolerances. This dimension is

subject to change based on socket design, OEM motherboard design, or OEM SMT process.

3. Dimension for CPUID = 0x06B1.

4. Dimension for CPUID = 0x06B4.

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Figure 23. Socketable Micro-FCPGA Package - Top and Bottom Isometric Views

PACKAGE KEEPOUT

CAPACITOR AREA

DIE

LABEL

TOP VIEW

BOTTOM VIEW

Mobile Intel^®Pentium ^®III Processor-M Datasheet

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Mechanical Specifications

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Figure 24. Socketable Micro-FCPGA Package - Top and Side View

SUBSTRATE KEEPOUT ZONE

DO NOT CONTACT PACKAGE

INSIDE THIS LINE

7 (K1)

8 places

0.286

5 (K)

4 places

A

1.25 MAX

(A3)

D1

35 (D)

Ø 0.32 (B)

478 places

A2

E1

2.03 0.08

±

35 (E)

(A1)

PIN A1 CORNER

NOTE: All dimensions in millimeters. Values shown are for reference only. See Table 36 for specific details.

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Figure 25. Socketable Micro-FCPGA Package - Bottom View

14 (K3)

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

14 (K3)

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21 23

25

25X 1.27

(e)

2

4

6

8

10 12 14 16 18 20 22 24 26

25X 1.27

(e)

NOTE: All dimensions in millimeters. Values shown are for reference only. See Table 36 for specific details.

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5.2

Surface Mount Micro-FCBGA Package

The Mobile Intel Pentium III Processor-M will also be available in a surface mount, 479-ball Micro-

FCBGA package. The Low Voltage and Ultra Low Voltage processors will be available only in this

package. Mechanical specifications are shown in Table 39. Figure 26 through Figure 28 illustrate

different views of the package.

The Micro-FCBGA package may have capacitors placed in the area surrounding the die. Since the die-

side capacitors are electrically conductive, and only slightly shorter than the die height, care should be

taken to avoid contacting the capacitors with electrically conductive materials. Doing so may short the

capacitors and possibly damage the device or render it inactive. The use of an insulating material

between the capacitors and any thermal solution should be considered to prevent capacitor shorting.

Table 39. Micro-FCBGA Package Mechanical Specifications

Symbol

Parameter

Min

2.27

Max

2.77

0.854

0.78

35.1

Unit

A

A2

b

D

E

Overall height, as delivered (1)

Die height

mm

Ball diameter

Package substrate length

Package substrate width

Die length

34.9

35.1

3

D1

11.18

4

10.82

3

E1

Die width

mm

7.20

6.85

4

e

N

K

K1

K2

S

--

Pdie

Ball pitch

Ball count

1.27

479

5

mm

each

mm

kPa

g

Keep-out outline from edge of package

Keep-out outline at corner of package

Capacitor keep-out height

Package edge to first ball center

Solder ball coplanarity

7

-

0.7

1.625

0.2

Allowable pressure on the die for thermal solution

Package weight

-

689

W

4.5

NOTES:

1. All dimensions are subject to change.

2. Overall height as delivered. Values were based on design specifications and tolerances. Final height after

surface mount depends on OEM motherboard design and SMT process.

3. Dimension for CPUID = 0x06B1.

4. Dimension for CPUID = 0x06B4.

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Figure 26. Micro-FCBGA Package – Top and Bottom Isometric Views

PACKAGE KEEPOUT

CAPACITOR AREA

DIE

LABEL

TOP VIEW

BOTTOM VIEW

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Figure 27. Micro-FCBGA Package – Top and Side Views

SUBSTRATE KEEPOUT ZONE

7 (K1)

8 places

DO NOT CONTACT PACKAGE

INSIDE THIS LINE

0.20

A

5 (K)

4 places

A2

D1

35 (D)

Ø 0.78 (b)

479 places

K2

E1

35 (E)

PIN A1 CORNER

NOTE: All dimensions in millimeters. Values shown are for reference only. See Table 37 for specific details.

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Figure 28. Micro-FCBGA Package - Bottom View

1.625 (S)

4 places

AF

AE

AD

AC

AB

AA

Y

1.625 (S)

4 places

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

13 15 17

11

10 12 14 16 18

5

7

9

19 21 23 25

22 24 26

25X 1.27

(e)

2

4

6

8

20

25X 1.27

(e)

NOTE: All dimensions in millimeters. Values shown are for reference only. See Table 37 for specific details.

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5.3

Signal Listings

Figure 29 is a top-side view of the ball or pin map of the Mobile Intel Pentium III Processor-M with the

voltage balls/pins called out. Table 40 lists the signals in ball/pin number order. Table 41 lists the

signals in signal name order.

Figure 29. Pin/Ball Map - Top View

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

A

B

A

B

A10# VREF

NC

A31# BREQ0# A23#

A27#

A20#

A24#

VSS

NC

A35#

VSS

A26#

A34#

A33#

A32#

D0#

D2#

D1#

D15#

VSS

D9#

D4#

D7#

VSS

D5#

VREF

D17#

VCCT

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

D8#

VSS

NC

D10#

D18#

VSS

D3#

D11#

D14#

D20#

D13#

D23#

D21#

VSS

D24#

VSS

D22#

VSS

D36#

VSS

VCCT

VSS

NC

VSS

A16#

VSS

NC

A25#

A28#

A13#

VSS

NC

A17#

VSS

A21#

VSS

A18#

VSS RESET# VSS

C

VCCT A19# VCCT A22# VCCT A30# VCCT A29# VCCT BERR# VCCT

D6#

VCC

VSS

VCC

VCCT D12# VCCT

D30#

NC

D

VSS

VCCT

VSS

VCCT

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VCCT

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCCT

INIT#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

E

VTT

NC TESTHI

D16#

VSS

D19#

D27#

D32#

PWRGD

F

NC

A9#

A12#

A4#

A3#

VSS

A5#

VSS

A7#

VSS

A14#

G

A15# VCCT

VCCT D25#

H

A8#

VSS

D26#

D29# VREF

J

A11# VCCT

VCCT D34#

VSS

D33#

VSS

D45#

VSS

D41#

VSS

D57#

VSS

D46#

VSS

D53#

VSS

D38#

D35#

D42#

D48#

D37#

NC

K

A6#

VSS

D31#

L

REQ4# BNR# REQ1# VCCT GHI#

VCCT D28#

M

N

M

N

VSS

PLL1

API#

VSS

NC

RSP#

VCC

NC

VSS

VCCT

VSS

D39#

NC

TESTLO

VREF PLL2

P

NC

VSS

NC

D49#

R

REQ0# BPRI# VID4

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VCCT D43#

D44#

D51#

D40#

D55#

D54#

D60#

D50#

T

REQ2# VSS DEFER# RP#

VSS

D47#

U

REQ3# HITM# RS2#

VSS

VCCT D52#

V

RS1#

VSS LOCK# VCCT

VSS

D63#

W

Y

W

Y

TRDY# AERR# DBSY# VSS

VCCT D59#

DRDY# VSS

RS0#

VSS

D58#

TESTLO

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

VREF

VID0

HIT#

VSS

ADS# VCCT

VCC

VSS

VCC

TDI

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

NC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCCT D62#

PWR

AP0#

VSS

D61#

D56# VREF

GOOD

BCLK VID1 A20M# VCCT

VCCT DEP3# VSS DEP6#

BCLK# /

CMOS

REF

VSS

SMI#

NC

VCCT IGNNE# TCK

TDO VCCT

VCCT LINT0 NCTRL PICD1 VCCT PICD0 VCCT BPM1# BPM0#

NC

DEP7# DEP1# DEP5#

CLKREF

VSS

RTT

VID2 VCCT STPCLK# VSS

VSS

NC

VSS

NC

VSS BSEL0 VSS

CMOS

LINT1

VSS

NC

VCCT

NC

VSS

BP3#

VSS PRDY# VSS DEP0# DEP2# VSS

IMPEDP

EDGE

VCCT VCCT

VID3 IERR# FLUSH# FERR# TMS DPSLP# VREF BSEL1 TESTHI

THRMDATHRMDC TRST#

PREQ# PICCLK VREF BP2# BINIT# DEP4# VSS

VSS

REF

CTRLP

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

NOTE: A2 pin is de-populated on Micro-FCPGA package.

VCC

VSS VCCT Other

68

Mobile Intel^®Pentium ^®III Processor-M Datasheet

Mechanical Specifications

R

Table 40. Signal Listing in Order by Pin/Ball Number

No.

Signal Name

No.

Signal Name

No.

D7

Signal Name

VSS

No.

E22

Signal Name

VSS

A3

A10#

B18

VSS

A4

A5

VREF

NC

B19

B20

B21

B22

B23

B24

B25

B26

C1

D4#

VSS

D8

D9

VCC

VSS

E23

E24

E25

E26

F1

D16#

D23#

VSS

D19#

NC

A6

A7

A31#

BREQ0#

A23#

A27#

A24#

NC

D17#

VSS

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

E1

VCC

VSS

A8

A9

D18#

D14#

D24#

VSS

VCC

VSS

F2

VSS

A14#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

D21#

D36#

D27#

A9#

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B1

VCC

VSS

F3

F4

A35#

A26#

A33#

A32#

D0#

NC

VCC

VSS

F5

F6

C2

A16#

A28#

NC

C3

C4

C5

VCC

VSS

VCC

VSS

VCC

D3#

D13#

D22#

NC

F7

F8

F9

VCCT

A19#

VCCT

A22#

VCCT

A30#

VCCT

A29#

VCCT

BERR#

VCCT

D6#

VCCT

D12#

VCCT

D5#

VCCT

NC

D2#

D15#

D9#

C6

C7

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

G1

C8

C9

D7#

VREF

D8#

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

D10#

D11#

VSS

VCCT

NC

E2

TESTHI

VTTPWRGD

VCCT

VCC

VCCT

VCC

VSS

E3

E4

E5

E6

B2

VSS

B3

B4

A25#

VSS

E7

E8

B5

B6

A17#

VSS

E9

VCC

VSS

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

B7

B8

A21#

VSS

VCC

VSS

B9

A20#

VSS

D20#

VSS

VCC

VSS

G2

G3

A5#

B10

B11

B12

B13

B14

B15

B16

B17

A15#

VCCT

VCC

VSS

VCC

VSS

VCCT

D25#

A18#

VSS

D30#

NC

VCC

VSS

G4

G5

A34#

VSS

D2

D3

VSS

A13#

VSS

VCCT

VCC

VSS

G6

G21

G22

G23

G24

RESET#

VSS

D4

D5

VCC

VSS

D1#

D6

VCC

Mobile Intel^®Pentium ^®III Processor-M Datasheet

69

Mechanical Specifications

R

No.

G25

Signal Name

VSS

No.

L4

Signal Name

No.

P23

Signal Name

VSS

No.

V2

Signal Name

VSS

VCCT

GHI#

VSS

VCC

VSS

VCCT

D28#

VSS

D42#

TESTLO

VSS

RSP#

VCC

VSS

VCC

VSS

D39#

D45#

D48#

VREF

PLL2

PLL1

NC

G26

H1

D32#

A12#

VSS

L5

L6

P24

P25

P26

R1

D49#

D41#

NC

REQ0#

BPRI#

VID4

VSS

V3

V4

LOCK#

VCCT

VSS

H2

H3

L21

L22

L23

L24

L25

L26

M1

V5

V6

A8#

VCC

H4

H5

VSS

R2

R3

V21

V22

V23

V24

V25

V26

W1

VSS

VCC

H6

VCC

VSS

R4

R5

VSS

H21

H22

H23

H24

H25

H26

J1

VCC

D63#

D46#

D55#

TRDY#

AERR#

DBSY#

VSS

VCC

VSS

R6

VSS

VCC

M2

R21

R22

R23

R24

R25

R26

T1

D26#

D29#

VREF

A4#

M3

M4

M5

VSS

VCCT

D43#

VSS

D44#

REQ2#

VSS

W2

W3

M6

W4

W5

J2

A7#

M21

M22

M23

M24

M25

M26

N1

VCC

J3

J4

A11#

VCCT

VCC

VSS

W6

VSS

VCC

T2

W21

W22

W23

W24

W25

W26

Y1

J5

J6

T3

T4

DEFER#

RP#

VSS

VCCT

D59#

VSS

J21

J22

J23

J24

J25

J26

K1

VCC

VSS

T5

T6

VSS

VCC

VCCT

D34#

VSS

D38#

A3#

N2

N3

T21

T22

T23

T24

T25

T26

U1

VSS

VCC

D54#

DRDY#

VSS

RS0#

TESTLO

VSS

N4

N5

VSS

Y2

Y3

VCC

VSS

VCC

VSS

VCCT

NC

VSS

D37#

NC

D47#

D57#

D51#

REQ3#

HITM#

RS2#

VSS

N6

Y4

Y5

K2

VSS

N21

N22

N23

N24

N25

N26

P1

K3

K4

A6#

VSS

Y6

VCC

VSS

U2

Y21

Y22

Y23

Y24

Y25

Y26

AA1

AA2

AA3

AA4

AA5

AA6

K5

K6

VSS

VCC

VSS

VCC

VSS

D31#

D33#

D35#

REQ4#

BNR#

REQ1#

U3

U4

VCC

VSS

K21

K22

K23

K24

K25

K26

L1

U5

U6

VCC

VSS

D58#

D53#

D60#

VREF

HIT#

ADS#

VCCT

VCC

P2

P3

VSS

API#

NC

U21

U22

U23

U24

U25

U26

V1

VCC

VSS

P4

P5

VCCT

D52#

VSS

D40#

RS1#

NC

P6

P21

P22

VCC

VSS

VCC

L2

L3

VSS

70

Mobile Intel^®Pentium ^®III Processor-M Datasheet

Mechanical Specifications

R

No.

AA7

Signal Name

VCC

No.

Signal Name

No.

Signal Name

TDO

No.

Signal Name

AB22 VCC

AB23 VSS

AB24 D61#

AB25 D56#

AB26 VREF

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

AE26 VSS

AA8

AA9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCCT

D62#

VSS

D50#

VID0

VSS

AP0#

PWRGOOD

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCCT

NC

AF1

AF2

AF3

AF4

AF5

AF6

AF7

AF8

AF9

AF10

AF11

VCCT

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AB1

VCCT

LINT0

NCTRL

PICD1

VCCT

PICD0

VCCT

BPM1#

BPM0#

NC

VID3

IERR#

FLUSH#

FERR#

TMS

DPSLP#

VREF

AC1

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AC9

BCLK

VID1

A20M#

VCCT

VCC

VSS

BSEL1

TESTHI

VCC

VSS

VCC

AF12 CMOSREF

DEP7#

DEP1#

DEP5#

VSS

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

THRMDA

THRMDC

TRST#

EDGECTRLP

NC

AC10 VSS

AC11 VCC

AC12 VSS

AC13 VCC

AC14 VSS

AC15 VCC

AC16 VSS

AC17 VCC

AC18 VSS

AC19 VCC

AC20 VSS

AC21 VCC

AC22 VSS

AC23 VCCT

AC24 DEP3#

AC25 VSS

AC26 DEP6#

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AE2

VID2

AE3

AE4

VCCT

STPCLK#

VSS

INIT#

VSS

NC

PREQ#

PICCLK

VREF

AE5

AE6

AB2

AB3

AB4

AE7

AE8

BP2#

NC

BINIT#

DEP4#

VSS

AB5

AB6

AE9

VSS

NC

AE10

AE11

AE12

AE13

AE14

AE15

AB7

AB8

VSS

BSEL0

VSS

LINT1

VSS

RTTIMPEDP

VSS

VCCT

VSS

BP3#

VSS

PRDY#

VSS

DEP0#

DEP2#

VSS

AB9

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

BCLK#/CLKREF AE16

VSS

SMI#

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

NC

CMOSREF

VCCT

TDI

VCCT

IGNNE#

AD10 TCK

Mobile Intel^®Pentium ^®III Processor-M Datasheet

71

Mechanical Specifications

R

Table 41. Signal Listing in Order by Signal Name

No.

Signal Name

Signal Buffer Type

No.

Signal Name

BINIT#

Signal Buffer Type

K1

A3#

AGTL I/O

1.5V CMOS Input

AGTL I/O

Clock Input

AF23

L2

AF22

AGTL I/O

J1

G2

A4#

A5#

BNR#

BP2#

AGTL I/O

K3

J2

A6#

A7#

AE20 BP3#

AD22 BPM0#

AD21 BPM1#

R2

A7

AGTL I/O

H3

G1

A8#

A9#

AGTL I/O

AGTL Input

AGTL I/O

3.3V CMOS Output

CMOS Reference Voltage

AGTL I/O

BPRI#

A3

J3

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

A28#

A29#

A30#

A31#

A32#

A33#

A34#

A35#

A20M#

ADS#

AERR#

AP0#

AP1#

BCLK

BREQ0#

AE12 BSEL0

H1

D3

AF10

AD5

AF12

A16

B17

A17

D23

B19

C20

C16

A20

A22

A19

A23

A24

C18

D24

B24

A18

E23

B21

B23

E26

C24

F24

D25

E24

B25

G24

H24

F26

L24

BSEL1

CMOSREF

D0#

F3

G3

C2

D1#

AGTL I/O

B5

B11

C6

D2#

D3#

AGTL I/O

D4#

D5#

AGTL I/O

B9

B7

C8

D6#

D7#

AGTL I/O

A8

A10

B3

A13

A9

C3

D8#

D9#

AGTL I/O

D10#

D11#

D12#

D13#

D14#

D15#

D16#

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

D26#

D27#

D28#

AGTL I/O

C12

C10

A6

AGTL I/O

A15

A14

B13

A12

AC3

AA3

W2

AB3

P3

AGTL I/O

AC1

AD1

C14

AGTL I/O

BCLK#/CLKREF Clock Input

BERR# AGTL I/O

AGTL I/O

72

Mobile Intel^®Pentium ^®III Processor-M Datasheet

Mechanical Specifications

R

No.

H25

Signal Name

D29#

Signal Buffer Type

No.

Signal Name

DEP4#

Signal Buffer Type

AGTL I/O

AGTL Input

AGTL I/O

AF24

AGTL I/O

C26

K24

G26

K25

J24

K26

F25

N26

J26

M24

U26

P25

L26

R24

R26

M25

V25

T24

M26

P24

D30#

D31#

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

D41#

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

AD26 DEP5#

AC26 DEP6#

AD24 DEP7#

AGTL I/O

Y1

DRDY#

DPSLP#

EDGECTRLP

FERR#

FLUSH#

GHI#

AF8

AF16

AF6

AF5

L5

AA2

U2

AF4

AD9

AE6

1.5V CMOS Input

AGTL Control

1.5V Open Drain Output

1.5V CMOS Input

1.25V CMOS Input

AGTL I/O

HIT#

HITM#

IERR#

IGNNE#

INIT#

AGTL I/O

1.5V Open Drain Output

1.5V CMOS Input

AGTL I/O

1.5V CMOS Input

AGTL impedance control

2.0V APIC Clock Input

1.5V Open Drain I/O

PLL Analog Voltage

AGTL Output

AD15 INTR/LINT0

V3 LOCK#

AE14 NMI/LINT1

AD16 NCTRL

AF20

PICCLK

AD19 PICD0

AD17 PICD1

AA26 D50#

T26

U24

Y25

W26

V26

D51#

D52#

D53#

D54#

D55#

N3

N2

PLL1

PLL2

AE22 PRDY#

AF19

AB4

R1

PREQ#

PWRGOOD

REQ0#

REQ1#

REQ2#

REQ3#

REQ4#

RESET#

RP#

1.5V CMOS Input

1.8V CMOS Input

AGTL I/O

AB25 D56#

T25

Y24

W24

Y26

D57#

D58#

D59#

D60#

L3

T1

AGTL I/O

U1

L1

AGTL I/O

AB24 D61#

AA24 D62#

B15

T4

AGTL Input

AGTL I/O

V24

W3

T3

AE24 DEP0#

AD25 DEP1#

AE25 DEP2#

AC24 DEP3#

D63#

DBSY#

DEFER#

Y3

V1

RS0#

RS1#

AGTL I/O

U3

M5

RS2#

RSP#

AGTL I/O

AGTL Input

AE16 RTTIMPEDP

AD3

AE4

AGTL Pull-up Control

1.5V CMOS Input

SMI#

STPCLK#

Mobile Intel^®Pentium ^®III Processor-M Datasheet

73

Mechanical Specifications

R

No.

AD10 TCK

AD7 TDI

AD11 TDO

Signal Name

Signal Buffer Type

No.

Signal Name

VID1

Signal Buffer Type

1.5V JTAG Clock Input AC2

Voltage Identification

JTAG Input

JTAG Output

AE2

AF3

R3

VID2

VID3

Voltage Identification

E2

TESTHI

Test Use Only

Thermal Diode Anode

VID4

Voltage Identification

AF11

M1

Y4

TESTHI

TESTLO

THERMDA

THERMDC

TMS

TRDY#

TRST#

VID0

A4

VREF

AGTL Reference Voltage

VCCT power good signal

A21

N1

AF13

AF14

AF7

W1

AF9

Thermal Diode Cathode AF21

JTAG Input

AGTL I/O

AA1

AB26 VREF

AF15

AB1

JTAG Input

Voltage Identification

H26

E3

VREF

VTTPWRGD

Table 42. Voltage and No-Connect Pin/Ball Locations

Signal

Name

Pin/Ball Numbers

NC

A2, A5, A11, B1, C1, C4, C22, D1, D26, E1, F1, N4, N24, P1, P4, P5, P26, AD4, AD13, AD23,

AE8, AE10, AF17, AF18

VCC

D6, D8, D10, D12, D14, D16, D18, D20, D22, E5, E7, E9, E11, E13, E15, E17, E19, E21, F6, F8,

F10, F12, F14, F16, F18, F20, F22, G5, G21, H6, H22, J5, J21, K6, K22, L21, M6, M22, N5, N21,

P6, P22, R5, R21, T6, T22, U5, U21, V6, V22, W5, W21, Y6, Y22, AA5, AA7, AA9, AA11, AA13,

AA15, AA17, AA19, AA21, AB6, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AB22, AC5,

AC7, AC9, AC11, AC13, AC15, AC17, AC19, AC21

VCCT

VSS

A26, C5, C7, C9, C11, C13, C15, C17, C19, C21, D5, E4, E6, G4, G23, J4, J23, L4, L23, N23,

R23, U23, V4, W23, AA4, AA23, AC4, AC23, AD6, AD8, AD12, AD14, AD18, AD20, AE3, AE18,

AF1, AF2

A25, B2, B4, B6, B8, B10, B12, B14, B16, B18, B20, B22, B26, C23, C25, D2, D4, D7, D9, D11,

D13, D15, D17, D19, D21, E8, E10, E12, E14, E16, E18, E20, E22, E25, F2, F4, F5, F7, F9, F11,

F13, F15, F17, F19, F21, F23, G6, G22, G25, H2, H4, H5, H21, H23, J6, J22, J25, K2, K4, K5,

K21, K23, L6, L22, L25, M2, M3, M4, M21, M23, N6, N22, N25, P2, P21, P23, R4, R6, R22, R25,

T2, T5, T21, T23, U4, U6, U22, U25, V2, V5, V21, V23, W4, W6, W22, W25, Y2, Y5, Y21, Y23,

AA6, AA8, AA10, AA12, AA14, AA16, AA18, AA20, AA22, AA25, AB2, AB5, AB7, AB9, AB11,

AB13, AB15, AB17, AB19, AB21, AB23, AC6, AC8, AC10, AC12, AC14, AC16, AC18, AC20,

AC22, AC25, AD2, AE1, AE5, AE7, AE9, AE11, AE13, AE15, AE17, AE19, AE21, AE23, AE26,

AF25, AF26

NOTE: A2 pin is de-populated on the Micro-FCPGA package.

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6. V_CCThermal Specifications

In order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat pipe, or

other heat transfer system) must make firm contact to the exposed processor die. The processor die

must be clean before the thermal solution is attached or the processor may be damaged.

Table 43 provides the Thermal Design Power (TDP) dissipation and the minimum and maximum T_J

temperatures for the Mobile Intel Pentium III Processor-M. The thermal solution should be designed to

ensure the junction temperature never exceeds the 100°C T_Jspecification while operating at the

Thermal Design Power. Additionally, a secondary failsafe mechanism in hardware should be provided

to shutdown the processor at 101°C to prevent permanent damage, as described in Section 3.1.3. TDP

is a thermal design power specification based on the worst case power dissipation of the processor

while executing publicly available software under normal operating conditions at nominal voltages.

Contact your Intel Field Sales Representative for further information.

Table 43. Power Specifications for Mobile Intel Pentium III Processor-M

Symbol

Core Frequency/Voltage

Thermal Design Power

Unit

Notes

TDP

Thermal Design Power at

W

At 100°C, Note 1

300 MHz & 0.95 V

350 MHz & 0.95 V

400 MHz & 0.95 V

450 MHz & 1.05 V

466 MHz & 1.05 V

500 MHz & 1.05 V

533 MHz & 1.05 V

700 MHz & 1.10 V

733 MHz & 1.10 V

750 MHz & 1.10 V

800 MHz & 1.10 V

850 MHz & 1.10 V

866 MHz & 1.10 V

900 MHz & 1.10 V

933 MHz & 1.10 V

667 MHz & 1.15 V

733 MHz & 1.15 V

750 MHz & 1.15 V

800 MHz & 1.15 V

850 MHz & 1.15 V

866 MHz & 1.15 V

933 MHz & 1.15 V

1.000 GHz & 1.15 V

866 MHz & 1.40 V

933 MHz & 1.40 V

1.000 GHz & 1.40 V

1.066 GHz & 1.40 V

1.133 GHz & 1.40 V

1.200 GHz & 1.40 V

1.266 GHz & 1.40V

1.333 GHz & 1.40V

3.3

3.5

Notes 1, 4

3.8

5.7

5.8

5.9

6.1

7.0

Notes 1, 4

7.0

8.9

9.3

9.4

9.25

10.0

10.1

10.5

11.0

19.5

20.1

20.5

21.0

21.8

22.0

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VCC Thermal Specifications

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Symbol

P_AH

Parameter

Auto Halt power at

Min

Max

Unit

Notes

W

At 50°C, Note 2

0.95 V

1.05 V

1.10 V

1.15 V

1.40 V

1.0

2.0

1.9

3.0

7.0

Notes 2, 4

P_QS

Quick Start power at

W

At 50°C, Note 2

0.95 V

1.05 V

1.10 V

1.15 V

1.40 V

0.9

1.8

1.7

2.7

6.5

Notes 2, 4

P_DSLP

Deep Sleep power at

0.95 V

At 35°C, Note 2

Notes 2, 4

0.7

1.3

1.6

2.0

4.8

1.05 V

Notes 2, 4

1.10 V

Notes 2, 4

1.15 V

1.40 V

P_DPRSLP

Deeper Sleep power

at 0.85 V

At 35°C, Note 2

At 35°C, Notes 2, 4

Note 3

0.62

W

P_DPRSLPULVDeeper Sleep power

at 0.85 V

T_J

0.47

100

W

°C

Junction Temperature

0

NOTES:

1. TDP is defined as the worst case power dissipated by the processor while executing publicly available software

under normal operating conditions at nominal voltages that meet the load line specifications. The TDP number

shown is a specification based on Icc(maximum) and indirectly tested by Icc(maximum) testing. TDP definition

is synonymous with the Thermal Design Power (typical) specification referred to in previous Intel datasheets.

The Intel TDP specification is a recommended design point and is not representative of the absolute maximum

power the processor may dissipate under worst case conditions.

2. Not 100% tested. These power specifications are determined by characterization of the processor currents at

higher temperatures and extrapolating the values for the temperature indicated.

3. T_Jis measured with the on-die thermal diode.

4. This specification applies only to the Ultra Low Voltage Mobile Intel Pentium III Processor-M.

6.1

Thermal Diode

The Mobile Intel Pentium III Processor-M has an on-die thermal diode that can be used to monitor the

die temperature (TJ). A thermal sensor located on the motherboard, or a stand-alone measurement kit,

may monitor the die temperature of the processor for thermal management or instrumentation

purposes. Table 44 and Table 45 provide the diode interface and specifications.

Note:

The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the

temperature of the hottest location on the die. This is due to inaccuracies in the thermal sensor, on-die

temperature gradients between the location of the thermal diode and the hottest location on the die, and

time based variations in the die temperature measurement. Time based variations can occur when the

sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the T_J

temperature can change.

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Table 44. Thermal Diode Interface

Signal Name

Pin/Ball Number

Signal Description

THERMDA

THERMDC

AF13

AF14

Thermal diode anode

Thermal diode cathode

Table 45. Thermal Diode Specifications

Symbol

Parameter

Min

Typ

Max Unit

Notes

n

Diode Ideality Factor (5-150uA)

Diode Ideality Factor (5-300uA)

1.0011 1.0067 1.0122

1.0003 1.0091 1.0178

Notes 1, 2, 3, 4, 6

Notes 1, 2, 3, 5, 6

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support

or recommend operation of the thermal diode when the processor power supplies are not within their specified

tolerance range.

2. Characterized at 100°C.

3. Not 100% tested. Specified by design/characterization.

4. Specified for Forward Bias Current = 5 µA (min) and 150 µA (max).

5. Specified for Forward Bias Current = 5 µA (min) and 300 µA (max).

6. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation:

Where I_s= saturation current, q = electronic charge, V_d= voltage across the diode, k = Boltzmann Constant,

and T = absolute temperature (Kelvin).

qV_D









nkT

I

^FW= I

S

⋅ e

−1





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7. Processor Initialization and

Configuration

7.1

Description

The Mobile Intel Pentium III Processor-M has some configuration options that are determined by

hardware and some that are determined by software. The processor samples its hardware configuration

at reset on the active-to-inactive transition of RESET#. The P6 Family of Processors Developer’s

Manual describes these configuration options. Some of the configuration options for the Mobile Intel

Pentium III Processor-M are described in the remainder of this section.

7.1.1

Quick Start Enable

Quick Start enabling is mandatory on the Mobile Intel Pentium III Processor-M by strapping A15# low.

When the STPCLK# signal is asserted it will enter the Quick Start state when A15# is sampled active

on the RESET# signal’s active-to-inactive transition. The Quick Start state supports snoops from the

bus priority device but it does not support symmetric master snoops nor is the latching of interrupts

supported. A “1” in bit position 5 of the Power-on Configuration register indicates that the Quick Start

state has been enabled.

7.1.2

System Bus Frequency

The current generation Mobile Intel Pentium III Processor-M will only function with a system bus

frequency of 133 MHz. The Low Voltage Mobile Intel Pentium III Processor-M will support both 100-

MHz and 133-MHz bus frequencies. The Ultra Low Voltage Mobile Intel Pentium III Processor-M

will support both 100-MHz and 133-MHz bus frequencies (see product features section for specific

supported frequencies). Bit positions 18 to 19 of the Power-on Configuration register indicates at

which speed a processor will run.

7.1.3

APIC Enable

The processor APIC must be hardware enabled by pulling the PICD[1:0] signals separately up to 1.5 V

and supplying an active PICCLK to the processor. Software can be used to disable the APIC if it is not

being used, after PICD[1:0] are sampled high when RESET# is deasserted and the processor has

started executing instructions.

7.2

Clock Frequencies and Ratios

The Mobile Intel Pentium III Processor-M uses a clock design in which the bus clock is multiplied by a

ratio to produce the processor’s internal (or “core”) clock. The ratio used is programmed into the

processor during manufacturing. The bus ratio programmed into the processor is visible in bit positions

22 to 25 and 27 of the Power-on Configuration register. Table 22 shows the 5-bit codes in the Power-

on Configuration register and their corresponding bus ratios.

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8. Processor Interface

8.1

Alphabetical Signal Reference

A[35:3]# (I/O – AGTL)

The A[35:3]# (Address) signals define a 2³⁶-byte physical memory address space. When ADS# is

active, these signals transmit the address of a transaction; when ADS# is inactive, these signals

transmit transaction information. These signals must be connected to the appropriate pins/balls of both

agents on the system bus. The A[35:24]# signals are protected with the AP1# parity signal, and the

A[23:3]# signals are protected with the AP0# parity signal.

On the active-to-inactive transition of RESET#, each processor bus agent samples A[35:3]# signals to

determine its power-on configuration. See P6 Family of Processors Developer’s Manual for details.

A20M# (I - 1.5 V Tolerant)

If the A20M# (Address-20 Mask) input signal is asserted, the processor masks physical address bit 20

(A20#) before looking up a line in any internal cache and before driving a read/write transaction on the

bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary.

Assertion of A20M# is only supported in Real mode.

ADS# (I/O - AGTL)

The ADS# (Address Strobe) signal is asserted to indicate the validity of a transaction address on the

A[35:3]# signals. Both bus agents observe the ADS# activation to begin parity checking, protocol

checking, address decode, internal snoop or deferred reply ID match operations associated with the

new transaction. This signal must be connected to the appropriate pins/balls on both agents on the

system bus.

AERR# (I/O - AGTL)

The AERR# (Address Parity Error) signal is observed and driven by both system bus agents, and if

used, must be connected to the appropriate pins/balls of both agents on the system bus. AERR#

observation is optionally enabled during power-on configuration; if enabled, a valid assertion of

AERR# aborts the current transaction.

If AERR# observation is disabled during power-on configuration, a central agent may handle an

assertion of AERR# as appropriate to the error handling architecture of the system.

AP[1:0]# (I/O - AGTL)

The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#, A[35:3]#,

REQ[4:0]# and RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. A correct parity signal is high if

an even number of covered signals is low and low if an odd number of covered signals are low. This

allows parity to be high when all the covered signals are high. AP[1:0]# should be connected to the

appropriate pins/balls on both agents on the system bus.

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BCLK, BCLK# (I)

The BCLK and BCLK# signals determines the system bus frequency.

On systems with Differential Clocking, both system bus agents must receive these signals to drive their

outputs and latch their inputs on the BCLK rising edge and BCLK# falling edge. All external timing

parameters are specified with respect to the crossing point of the BCLK rising edge and BCLK# falling

edge.

On systems with Single Ended Clocking, both system bus agents must receive the BCLK signal to

drive their outputs and latch their inputs on the BCLK rising edge. All external timing parameters are

specified with respect to the BCLK signal. The BCLK# signal functions as the CLKREF input.

BERR# (I/O - AGTL)

The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol

violation. It may be driven by either system bus agent and must be connected to the appropriate

pins/balls of both agents, if used. However, the Mobile Intel Pentium III Processor-Ms do not observe

assertions of the BERR# signal.

BERR# assertion conditions are defined by the system configuration. Configuration options enable the

BERR# driver as follows:

•

Enabled or disabled

Asserted optionally for internal errors along with IERR#

Asserted optionally by the request initiator of a bus transaction after it observes an error

Asserted by any bus agent when it observes an error in a bus transaction

BINIT# (I/O - AGTL)

The BINIT# (Bus Initialization) signal may be observed and driven by both system bus agents and

must be connected to the appropriate pins/balls of both agents, if used. If the BINIT# driver is enabled

during the power-on configuration, BINIT# is asserted to signal any bus condition that prevents

reliable future information.

If BINIT# is enabled during power-on configuration, and BINIT# is sampled asserted, all bus state

machines are reset and any data which was in transit is lost. All agents reset their rotating ID for bus

arbitration to the state after reset, and internal count information is lost. The L1 and L2 caches are not

affected.

If BINIT# is disabled during power-on configuration, a central agent may handle an assertion of

BINIT# as appropriate to the Machine Check Architecture (MCA) of the system.

BNR# (I/O - AGTL)

The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent that is unable to

accept new bus transactions. During a bus stall, the current bus owner cannot issue any new

transactions.

Since multiple agents may need to request a bus stall simultaneously, BNR# is a wired-OR signal that

must be connected to the appropriate pins/balls of both agents on the system bus. In order to avoid

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wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is

activated on specific clock edges and sampled on specific clock edges.

BP[3:2]# (I/O - AGTL)

The BP[3:2]# (Breakpoint) signals are the System Support group Breakpoint signals. They are outputs

from the processor that indicate the status of breakpoints.

BPM[1:0]# (I/O - AGTL)

The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals. They

are outputs from the processor that indicate the status of breakpoints and programmable counters used

for monitoring processor performance.

BPRI# (I - AGTL)

The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the system bus. It must

be connected to the appropriate pins/balls on both agents on the system bus. Observing BPRI# active

(as asserted by the priority agent) causes the processor to stop issuing new requests, unless such

requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of

its requests are completed and then releases the bus by deasserting BPRI#.

BREQ0# (I/O - AGTL)

The BREQ0# (Bus Request) signal is a processor Arbitration Bus signal. The processor indicates that it

wants ownership of the system bus by asserting the BREQ0# signal.

During power-up configuration, the central agent must assert the BREQ0# bus signal. The processor

samples BREQ0# on the active-to-inactive transition of RESET#. Optionally, this signal may be

grounded with a 10-Ω resistor.

BSEL[1:0] (O – 3.3 V Tolerant)

The BSEL[1:0] (Select Processor System Bus Speed) signal is used to configure the processor for the

system bus frequency. The chipset and system clock generator also uses the BSEL signals. The

VTTPWRGD signal informs the processor to output the BSEL signals. During power up the BSEL

signals will be indeterminate for a small period of time. The chipset and clock generator should not

sample the BSEL signals until the VTTPWRGD signal is asserted. The assertion of the VTTPWRGD

signal indicates that the BSEL signals are stable and driven to a final state by the processor. Please

refer to Figure 12 for the timing relationship between the BSEL and VTTPWRGD signals.

Table 46 shows the encoding scheme for BSEL[1:0]. The only supported system bus frequency for the

Mobile Intel Pentium III Processor-M is 133 MHz. The Low Voltage Mobile Intel Pentium III

Processor-M will support both 100-MHz and 133-MHz bus frequencies. The Ultra Low Voltage

Mobile Intel Pentium III Processor-M will support both 100-MHz and 133-MHz bus frequencies (see

product features for specific supported frequencies). If another frequency is used then the processor is

not guaranteed to function properly.

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Table 46. BSEL[1:0] Encoding

BSEL[1:0]

System Bus Frequency

01

11

100 MHz

133 MHz

CLKREF (Analog)

The CLKREF (System Bus Clock Reference) signal provides a reference voltage to define the trip

point for the BCLK signal on platforms supporting Single Ended Clocking. This signal should be

connected to a resistor divider to generate 1.25 V from the 2.5-V supply. A minimum of 1-uF

decoupling capacitance is recommended on CLKREF. On systems with Differential Clocking, the

CLKREF pin functions as the BCLK# input.

CMOSREF (Analog)

The CMOSREF (CMOS Reference Voltage) signal provides a DC level reference voltage for the

CMOS input buffers. CMOSREF must be generated from a stable 1.5-V supply (830 chipset family),

2.5 V (440MX chipset family) and must meet the VCMOSREF specification. The same 1.5V (830

chipset family) or 2.5 V (440MX chipset family) supply should be used to power the chipset CMOS

I/O buffers that drive the CMOS signals. The Thevenin equivalent impedance of the VCMOSREF

generation circuits must be less than 0.5 Kꢀ/1 Kꢀ (i.e., top resistor 500 ꢀ, bottom resistor 1 Kꢀ) for

830 chipset family. The Thevenin equivalent impedance of the VCMOSREF generation circuits must

be less than 0.75 Kꢀ/0.5 Kꢀ (i.e., top resistor 750 ꢀ, bottom resistor 500 ꢀ) for Intel 440MX chipset

family. Please refer to the platform design guidelines for other resistor divider recommendations.

D[63:0]# (I/O - AGTL)

The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between both

system bus agents, and must be connected to the appropriate pins/balls on both agents. The data driver

asserts DRDY# to indicate a valid data transfer.

DBSY# (I/O - AGTL)

The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the system

bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This

signal must be connected to the appropriate pins/balls on both agents on the system bus.

DEFER# (I - AGTL)

The DEFER# (Defer) signal is asserted by an agent to indicate that the transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed

memory agent or I/O agent. This signal must be connected to the appropriate pins/balls on both agents

on the system bus.

DEP[7:0]# (I/O - AGTL)

The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data bus.

They are driven by the agent responsible for driving D[63:0]#, and must be connected to the

appropriate pins/balls on both agents on the system bus if they are used. During power-on

configuration, DEP[7:0]# signals can be enabled for ECC checking or disabled for no checking.

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DRDY# (I/O - AGTL)

The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid

data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle clocks.

This signal must be connected to the appropriate pins/balls on both agents on the system bus.

DPSLP# (I - 1.5 V Tolerant)

The DPSLP# (Deep Sleep) signal, when asserted in the Quick Start state, causes the processor to enter

the Deep Sleep state. In order to return to the Quick Start state BCLK, BCLK# must be running and

the DPSLP# pin must be deasserted.

EDGCTRLP (I-Analog)

The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the AGTL output

buffers. Connect the signal to V_SSwith a 110-Ω, 1% resistor.

FERR# (O - 1.5 V Tolerant Open-drain)

The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-

point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and it is included for

compatibility with systems using DOS-type floating-point error reporting.

FLUSH# (I - 1.5 V Tolerant)

When the FLUSH# (Flush) input signal is asserted, the processor writes back all internal cache lines in

the Modified state and invalidates all internal cache lines. At the completion of a flush operation, the

processor issues a Flush Acknowledge transaction. The processor stops caching any new data while the

FLUSH# signal remains asserted.

On the active-to-inactive transition of RESET#, each processor bus agent samples FLUSH# to

determine its power-on configuration.

GHI# (I - 1.25 V)

The GHI# signal controls the selection of the operating mode bus ratio in a Mobile Intel Pentium III

Processor-M. This signal is latched on exit from the Deep Sleep state and determines which of two bus

ratios is selected for operation. This signal is ignored when the processor is not in the Deep Sleep state.

This signal has an on-die pull-up to V_CCTand should be driven with an Open-drain driver with no

external pull-up.

HIT# (I/O - AGTL), HITM# (I/O - AGTL)

The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results,

and must be connected to the appropriate pins/balls on both agents on the system bus. Either bus agent

can assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be

continued by reasserting HIT# and HITM# together.

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IERR# (O - 1.5 V Tolerant Open-drain)

The IERR# (Internal Error) signal is asserted by the processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the system bus. This

transaction may optionally be converted to an external error signal (e.g., NMI) by system logic. The

processor will keep IERR# asserted until it is handled in software or with the assertion of RESET#,

BINIT, or INIT#.

IGNNE# (I - 1.5 V Tolerant)

The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error

and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor

freezes on a non-control floating-point instruction if a previous instruction caused an error. IGNNE#

has no affect when the NE bit in control register 0 (CR0) is set.

INIT# (I - 1.5 V Tolerant)

The INIT# (Initialization) signal is asserted to reset integer registers inside the processor without

affecting the internal (L1 or L2) caches or the floating-point registers. The processor begins execution

at the power-on reset vector configured during power-on configuration. The processor continues to

handle snoop requests during INIT# assertion. INIT# is an asynchronous input.

If INIT# is sampled active on RESET#'s active-to-inactive transition, then the processor executes its

built-in self test (BIST).

INTR (I - 1.5 V Tolerant)

The INTR (Interrupt) signal indicates that an external interrupt has been generated. INTR becomes the

LINT0 signal when the APIC is enabled. The interrupt is maskable using the IF bit in the EFLAGS

register. If the IF bit is set, the processor vectors to the interrupt handler after completing the current

instruction execution. Upon recognizing the interrupt request, the processor issues a single Interrupt

Acknowledge (INTA) bus transaction. INTR must remain active until the INTA bus transaction to

guarantee its recognition.

LINT[1:0] (I - 1.5 V Tolerant)

The LINT[1:0] (Local APIC Interrupt) signals must be connected to the appropriate pins/balls of all

APIC bus agents, including the processor and the system logic or I/O APIC component. When APIC is

disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes

NMI, a non-maskable interrupt. INTR and NMI are backward compatible with the same signals for the

Pentium processor. Both signals are asynchronous inputs.

Both of these signals must be software configured by programming the APIC register space to be used

either as NMI/INTR or LINT[1:0] in the BIOS. If the APIC is enabled at reset, then LINT[1:0] is the

default configuration.

LOCK# (I/O - AGTL)

The LOCK# (Lock) signal indicates to the system that a sequence of transactions must occur

atomically. This signal must be connected to the appropriate pins/balls on both agents on the system

bus. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first

transaction through the end of the last transaction.

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When the priority agent asserts BPRI# to arbitrate for bus ownership, it waits until it observes LOCK#

deasserted. This enables the processor to retain bus ownership throughout the bus locked operation and

guarantee the atomicity of lock.

NC (No Connect)

All signals named NC (No Connect) must be left unconnected.

NCTRL (I - Analog)

The NCTRL signal provides the AGTL pull down impedance control. The processor samples this

input to determine the N-channel pull-down device strength when it is the driving agent. An external

14 ꢀ (1% tolerance) pull-up resistor to V_CCTis required for this signal. Please refer to platform design

guide for implementation details.

NMI (I - 1.5 V Tolerant)

The NMI (Non-Maskable Interrupt) indicates that an external interrupt has been generated. NMI

becomes the LINT1 signal when the APIC is disabled. Asserting NMI causes an interrupt with an

internally supplied vector value of 2. An external interrupt-acknowledge transaction is not generated. If

NMI is asserted during the execution of an NMI service routine, it remains pending and is recognized

after the IRET is executed by the NMI service routine. At most, one assertion of NMI is held pending.

NMI is rising edge sensitive.

PICCLK (I – 2.0 V Tolerant)

The PICCLK (APIC Clock) signal is an input clock to the processor and system logic or I/O APIC that

is required for operation of the processor, system logic, and I/O APIC components on the APIC bus.

PICD[1:0] (I/O - 1.5 V Tolerant Open-drain)

The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC

bus. They must be connected to the appropriate pins/balls of all APIC bus agents, including the

processor and the system logic or I/O APIC components. If the PICD0 signal is sampled low on the

active-to-inactive transition of the RESET# signal, then the APIC is hardware disabled. For the

Mobile Intel Pentium III Processor-M, the APIC is required to be hardware enabled as described in

Section 7.1.3

PLL1, PLL2 (Analog)

The PLL1 and PLL2 signals provide isolated analog decoupling is required for the internal PLL. See

Section 3.2.2 for a description of the analog decoupling circuit.

PRDY# (O - AGTL)

The PRDY# (Probe Ready) signal is a processor output used by debug tools to determine processor

debug readiness.

PREQ# (I - 1.5 V Tolerant)

The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processor.

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85

Processor Interface

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PWRGOOD (I – 1.8 V Tolerant)

PWRGOOD (Power Good) is a 1.8-V tolerant input. The processor requires this signal to be a clean

indication that clocks and the power supplies (V_CC, V_CCT, etc.) are stable and within their

specifications. Clean implies that the signal will remain low, (capable of sinking leakage current) and

without glitches, from the time that the power supplies are turned on, until they come within

specification. The signal will then transition monotonically to a high (1.8V) state. Figure 12 through

Figure 14 illustrate the relationship of PWRGOOD to other system signals. PWRGOOD can be driven

inactive at any time, but clocks and power must again be stable before the rising edge of PWRGOOD.

It must also meet the minimum pulse width specified in Table 24 (Section 3.7) and be followed by a

1 ms RESET# pulse. PWRGOOD may be asserted before BCLK is active (please refer to Table 24,

Note 5).

The PWRGOOD signal, which must be supplied to the processor, is used to protect internal circuits

against voltage sequencing issues. The PWRGOOD signal should be driven high throughout boundary

scan operation.

REQ[4:0]# (I/O - AGTL)

The REQ[4:0]# (Request Command) signals must be connected to the appropriate pins/balls on both

agents on the system bus. They are asserted by the current bus owner when it drives A[35:3]# to define

the currently active transaction type.

RESET# (I - AGTL)

Asserting the RESET# signal resets the processor to a known state and invalidates the L1 and L2

caches without writing back Modified (M state) lines. For a power-on type reset, RESET# must stay

active for at least 1 ms after V_CCand BCLK, BCLK# have reached their proper DC and AC

specifications and after PWRGOOD has been asserted. When observing active RESET#, all bus agents

will deassert their outputs within two clocks. RESET# is the only AGTL signal that does not have on-

die AGTL termination. A 56.2-Ω, 1% terminating resistor connected to V_CCTis required.

A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-on

configuration. The configuration options are described in Section 4 and in the P6 Family of Processors

Developer’s Manual.

Unless its outputs are tri-stated during power-on configuration, after an active-to-inactive transition of

RESET#, the processor optionally executes its built-in self-test (BIST) and begins program execution

at reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the appropriate pins/balls

on both agents on the system bus.

RP# (I/O - AGTL)

The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on

ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on the

system bus.

A correct parity signal is high if an even number of covered signals is low and low if an odd number of

covered signals are low. This definition allows parity to be high when all covered signals are high.

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Mobile Intel^®Pentium ^®III Processor-M Datasheet

Processor Interface

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RS[2:0]# (I/O - AGTL)

The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for

completion of the current transaction) and must be connected to the appropriate pins/balls on both

agents on the system bus.

RSP# (I - AGTL)

The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for

completion of the current transaction) during assertion of RS[2:0]#. RSP# provides parity protection

for RS[2:0]#. RSP# should be connected to the appropriate pins/balls on both agents on the system bus.

A correct parity signal is high if an even number of covered signals are low, and it is low if an odd

number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also high

since it is not driven by any agent guaranteeing correct parity.

RTTIMPEDP (I-Analog)

The RTTIMPEDP (R_TTImpedance/PMOS) signal is used to configure the on-die AGTL termination.

Connect the RTTIMPEDP signal to V_SSwith a 56.2-Ω, 1% resistor.

SMI# (I - 1.5 V Tolerant)

The SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a

System Management Interrupt, the processor saves the current state and enters System Management

Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program

execution from the SMM handler.

STPCLK# (I - 1.5 V Tolerant)

The STPCLK# (Stop Clock) signal, when asserted, causes the processor to enter a low-power Quick

Start state. The processor issues a Stop Grant Acknowledge special transaction and stops providing

internal clock signals to all units except the bus and APIC units. The processor continues to snoop bus

transactions and service interrupts while in the Quick Start state. When STPCLK# is deasserted and

other conditions in are met, the processor restarts its internal clock to all units and resumes execution.

The assertion of STPCLK# has no affect on the bus clock.

TCK (I - 1.5 V Tolerant)

The TCK (Test Clock) signal provides the clock input for the test bus (also known as the test access

port).

TDI (I - 1.5 V Tolerant)

The TDI (Test Data In) signal transfers serial test data to the processor. TDI provides the serial input

needed for JTAG support.

TDO (O - 1.5 V Tolerant Open-drain)

The TDO (Test Data Out) signal transfers serial test data from the processor. TDO provides the serial

output needed for JTAG support.

Mobile Intel^®Pentium ^®III Processor-M Datasheet

87

Processor Interface

R

TESTHI[2:1] (I - 1.25 V Tolerant)

The TESTHI[2:1] (Test input High) signals are used during processor test and need to be pulled high

during normal operation.

TESTLO[2:1] (I - 1.5 V Tolerant)

The TESTLO[2:1] (Test input Low) signals are used during processor test and needs to be pulled to

ground during normal operation.

THERMDA, THERMDC (Analog)

The THERMDA (Thermal Diode Anode) and THERMDC (Thermal Diode Cathode) signals connect

to the anode and cathode of the on-die thermal diode.

TMS (I - 1.5 V Tolerant)

The TMS (Test Mode Select) signal is a JTAG support signal used by debug tools.

TRDY# (I/O - AGTL)

The TRDY# (Target Ready) signal is asserted by the target to indicate that the target is ready to receive

write or implicit write-back data transfer. TRDY# must be connected to the appropriate pins/balls on

both agents on the system bus.

TRST# (I - 1.5 V Tolerant)

The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The Mobile Intel Pentium III

Processor-M does not self-reset during power on; therefore, it is necessary to drive this signal low

during power-on reset.

VID[4:0] (O – Open-drain)

The VID[4:0] (Voltage ID) pins/balls can be used to support automatic selection of power supply

voltages. Please refer to Section 3.2.2 for details.

VREF (Analog)

The VREF (AGTL Reference Voltage) signal provides a DC level reference voltage for the AGTL

input buffers. A voltage divider should be used to divide V_CCTby ²/₃. Resistor values of 1.00 kΩ and

2.00 kΩ are recommended. Decouple the VREF signal with three 0.1-µF high-frequency capacitors

close to the processor.

VTTPWRGD (I – 1.25 V)

The VTTPWRGD signal informs the processor to output the VID signals. During power up, the VID

signals will be in an indeterminate state for a small period of time. The voltage regulator should not

sample and/or latch the VID signals until the VTTPWRGD signal is asserted. The assertion of the

VTTPWRGD signal indicates that the VID signals are stable and are driven to the final state by the

processor. Please refer to Figure 12 for the power up sequence, Table 25 for VTTPWRGD transition

time and Section 4.3.1 for VTTPWRGD signal quality specifications.

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Mobile Intel^®Pentium ^®III Processor-M Datasheet

Processor Interface

R

8.2

Signal Summaries

Table 47. Input Signals

Name

Active Level

Clock

Signal Group

Qualified

A20M#

BCLK

BCLK#

BPRI#

DEFER#

DPSLP#

FLUSH#

GHI#

IGNNE#

INIT#

INTR

LINT[1:0]

NMI

NCTRL

PICCLK

PREQ#

PWRGOOD

RESET#

RSP#

Low

High

Low

High

Low

High

Low

High

Asynch

—

CMOS

Always

System Bus

Implementation

CMOS

Always

BCLK

Asynch

—

Asynch

BCLK

Asynch

—

Always

Quick Start state

Always

CMOS

Deep Sleep state

Always

System Bus

CMOS

APIC

Always

APIC disabled mode

APIC enabled mode

APIC disabled mode

CMOS

APIC

Always

Implementation

System Bus

CMOS

SMI#

STPCLK#

TCK

Implementation

JTAG

TDI

TCK

JTAG

TMS

TCK

JTAG

TRST#

VTTPWRGD

Low

High

Asynch

JTAG

Power/Other

Table 48. Output Signals

Name

Active Level

Clock

Signal Group

BSEL[1:0]

FERR#

IERR#

High

Low

High

Asynch

BCLK

Open-drain

Implementation

JTAG

PRDY#

TDO

TCK

VID[4:0]

Asynch

Power/Other

Mobile Intel^®Pentium ^®III Processor-M Datasheet

89

Processor Interface

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Table 49. Input/Output Signals (Single Driver)

Name

Active Level

Clock

Signal Group

Qualified

A[35:3]#

ADS#

Low

BCLK

System Bus

ADS#, ADS#+1

Always

ADS#, ADS#+1

Always

AP[1:0]#

BREQ0#

BP[3:2]#

BPM[1:0]#

D[63:0]#

DBSY#

DEP[7:0]#

DRDY#

LOCK#

Always

DRDY#

Always

DRDY#

Always

REQ[4:0]#

RP#

RS[2:0]#

TRDY#

ADS#, ADS#+1

Always

Response phase

Table 50. Input/Output Signals (Multiple Driver)

Name

Active Level

Clock

Signal Group

Qualified

AERR#

BERR#

BINIT#

BNR#

Low

High

BCLK

PICCLK

System Bus

APIC

ADS#+3

Always

HIT#

HITM#

PICD[1:0]

90

Mobile Intel^®Pentium ^®III Processor-M Datasheet

Appendix A. PLL RLC Filter Specification

R

Appendix A. PLL RLC Filter Specification

A1.

Introduction

All Mobile Intel Pentium III Processor-Ms have internal PLL clock generators, which are analog in

nature and require quiet power supplies for minimum jitter. Jitter is detrimental to a system; it

degrades external I/O timings as well as internal core timings (i.e. maximum frequency). The PLL

RLC filter specifications for the Mobile Intel Pentium III Processor-M are the same as those for the

Mobile Pentium III Processor. The general desired topology is shown in Figure 2. Excluded from the

external circuitry are parasitics associated with each component.

A2.

Filter Specification

The function of the filter is two fold. It protects the PLL from external noise through low-pass

attenuation. It also protects the PLL from internal noise through high-pass filtering. In general, the

low-pass description forms an adequate description for the filter.

The AC low-pass specification, with input at V_CCTand output measured across the capacitor, is as

follows:

•

< 0.2-dB gain in pass band

< 0.5-dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements)

34-dB attenuation from 1 MHz to 66 MHz

28-dB attenuation from 66 MHz to core frequency

The filter specification (AC) is graphically shown in Figure 29.

Other requirements:

•

Use a shielded type inductor to minimize magnetic pickup

The filter should support a DC current of at least 30 mA

The DC voltage drop from V_CCTto PLL1 should be less than 60 mV, which in practice implies

series resistance of less than 2 Ω. This also means that the pass band (from DC to 1 Hz)

attenuation below 0.43 dB for V_CCT= 1.25 V.

Mobile Intel^®Pentium ^®III Processor-M Datasheet

91

Appendix A. PLL RLC Filter Specification

R

Figure 30. PLL Filter Specifications

0.2 dB

0 dB

x dB

Forbidden

zone

-28 dB

Forbidden

zone

-34 dB

DC

Passband

x = 20.log[(Vcct-60 mV)/ Vcct]

1 Hz

fpeak

1 MHz

66 MHz

fcore

High Frequency

Band

NOTES:

Diagram is not to scale

No specification for frequencies beyond fcore.

Fpeak, if existent, should be less than 0.05 MHz.

A3.

Recommendation for Mobile Systems

The following LC components are recommended. The tables will be updated as other suitable

components and specifications are identified.

Table 51. PLL Filter Inductor Recommendations

Inductor

Part Number

Value Tol

SRF Rated I

DCR

Min Damping R Needed

L1

TDK MLF2012A4R7KT

10% 35 MHz 30 mA

4.7 µH

0.56 Ω (1Ω

0 Ω

max)

L2

L3

Murata LQG21N4R7K10

Murata LQG21C4R7N00

10% 47 MHz 30 mA

30% 35 MHz 30 mA

4.7 µH

0.7 Ω (+/-50%)

0.3 Ω max

0 Ω

0.2 Ω (assumed)

NOTE: Minimum damping resistance is calculated from 0.35 Ω – DCR_min. From vendor provided data, L1 and L2

DCR_minis 0.4 Ω and 0.5 Ω respectively, qualifying them for zero required trace resistance. DCR_minfor L3 is

not known and is assumed to be 0.15 Ω. Products with equivalent specifications may also be used.

Table 52. PLL Filter Capacitor Recommendations

Capacitor

Part Number

Value

33 µF

Tolerance

20%

ESL

2.5 nH

Unknown

ESR

C1

C2

Kemet T495D336M016AS

AVX TPSD336M020S0200

0.225 Ω

0.2 Ω

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Mobile Intel^®Pentium ^®III Processor-M Datasheet

Appendix A. PLL RLC Filter Specification

R

Table 53. PLL Filter Resistor Recommendations

Resistor

Part Number

Value

Tolerance

Power

R1

Various

10%

1/16 W

1 Ω

To satisfy damping requirements, total series resistance in the filter (from V_CCTto the top plate of the

capacitor) must be at least 0.35 Ω. This resistor can be in the form of a discrete component, or routing,

or both. For example, if the picked inductor has minimum DCR of 0.25 Ω, then a routing resistance of

at least 0.10 Ω is required. Be careful not to exceed the maximum resistance rule (2 Ω). For example,

if using discrete R1, the maximum DCR of the L should be less than 2.0 - 1.1 = 0.9 Ω, which precludes

using L2 and possibly L1.

Other routing requirements include:

•

The capacitor should be close to the PLL1 and PLL2 pins, with less than 0.1 Ω per route (These

routes do not count towards the minimum damping resistance requirement).

•

The PLL2 route should be parallel and next to the PLL1 route (minimize loop area).

The inductor should be close to the capacitor; any routing resistance should be inserted between

VCCT and the inductor.

•

Any discrete resistor should be inserted between V_CCTand the inductor.

A4.

Comments

•

A magnetically shielded inductor protects the circuit from picking up external flux noise. This

should provide better timing margins than with an unshielded inductor.

•

A discrete or routed resistor is required because the LC filter by nature has an under-damped

response, which can cause resonance at the LC pole. Noise amplification at this band, although

not in the PLL-sensitive spectrum, could cause a fatal headroom reduction for analog circuitry.

The resistor serves to dampen the response. Systems with tight space constraints should consider

a discrete resistor to provide the required damping resistance. Too large of a damping resistance

can cause a large IR drop, which means less analog headroom and lower frequency.

•

Ceramic capacitors have very high self-resonance frequencies, but they are not available in large

capacitance values. A high self-resonant frequency coupled with low ESL/ESR is crucial for

sufficient rejection in the PLL and high frequency band. The recommended tantalum capacitors

have acceptably low ESR and ESL.

The capacitor must be close to the PLL1 and PLL2 pins; otherwise the value of the low ESR

tantalum capacitor is wasted. Note the distance constraint should be translated from the 0.1-Ω

requirement.

Mobile Intel^®Pentium ^®III Processor-M Datasheet

93


型号：	RH80530GZ009512/SL5CL
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 1200MHz, CMOS, PPGA478 外围集成电路
文件：	总93页 (文件大小：1934K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RH80530GZ009512/SL5CL [INTEL]

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