S80296SA40 [INTEL]
Microcontroller, 16-Bit, 8096 CPU, 40MHz, CMOS, PQFP100, QFP-100;
| 型号： | S80296SA40 |
| 厂家： | 
INTEL |
| 描述： | Microcontroller, 16-Bit, 8096 CPU, 40MHz, CMOS, PQFP100, QFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总40页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
80296SA COMMERCIAL
CHMOS 16-BIT MICROCONTROLLER
■ 50 MHz Operation†
■ Chip-select Unit
— 6 Chip-select Pins
■ 6 Mbytes of Linear Address Space
■ 512 Bytes of Register RAM
■ 2 Kbytes of Code/Data RAM
■ Register-register Architecture
— Dynamic Demultiplexed/Multiplexed
Address/Data Bus for Each
Chip Select
— Programmable Wait States
(0–15) for Each Chip Select
■ Footprint and Functionally Compatible
Upgrade for the 8XC196NP and
80C196NU
— Programmable Bus Width
(8- or 16-bit) for Each Chip Select
■ Optional Phase-locked Loop (PLL)
— Programmable Address Range for
Each Chip Select
Circuitry with 2x or 4x Clock Multiplier
■ 32 I/O Port Pins
■ Event Processor Array (EPA) with
4 High-speed Capture/Compare
Channels
■ 19 Interrupt Sources, 14 with
Programmable Priorities
■ 4 External Interrupt Pins and NMI Pin
■ Multiply and Accumulate Executes in
80 ns Using the 40-bit Hardware
Accumulator
■ 2 Flexible 16-bit Timer/Counters with
Quadrature Counting Capability
■ 880 ns 32/16 Unsigned Division
■ 100-pin QFP Package
■ 3 Pulse-width Modulator (PWM)
Outputs with High Drive Capability
■ Full-duplex Serial Port with Dedicated
■ Complete System Development
Baud-rate Generator
Support
†
40 MHz standard; 50 MHz is Speed Premium
■ High-speed CHMOS Technology
The 80296SA is a member of Intel’s 16-bit MCS® 96 microcontroller family. The 80296SA features 6 Mbytes
of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation. The device has hardware and instructions to support
various digital signal processing algorithms.
NOTE
This datasheet contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have
the latest datasheet before finalizing a design.
COPYRIGHT © INTEL CORPORATION, 1997
January 1997
Order Number: 272748-003
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel dis-
claims any express or implied warranty, relating to sale and/or use of Intel products including liability or war-
ranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or
other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining
applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel liter-
ature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-548-4725
CONTENTS
80296SA Commercial
CHMOS 16-bit Microcontroller
1.0 Product Overview................................................................................................................ 1
2.0 Nomenclature Overview...................................................................................................... 2
3.0 Pinout.................................................................................................................................. 3
4.0 Signals ................................................................................................................................ 6
5.0 Address Map..................................................................................................................... 13
6.0 Electrical Characteristics................................................................................................... 14
6.1 DC Characteristics........................................................................................................ 14
6.2 AC Characteristics........................................................................................................ 18
6.2.1 Relationship of XTAL1 to CLKOUT .......................................................................18
6.2.2 Explanation of AC Symbols ...................................................................................19
6.2.3 AC Characteristics — Multiplexed Bus Mode ........................................................20
6.2.3.1 System Bus Timings, Multiplexed Bus ......................................................22
6.2.3.2 READY Timing, Multiplexed Bus ...............................................................23
6.2.4 AC Characteristics — Demultiplexed Bus Mode ...................................................24
6.2.4.1 System Bus Timings, Demultiplexed Bus ..................................................26
6.2.4.2 READY Timing, Demultiplexed Bus ..........................................................27
6.2.4.3 80296SA Deferred Bus Timing Mode ........................................................28
6.2.5 HOLD#, HLDA# Timings .......................................................................................29
6.2.6 AC Characteristics — Serial Port, Synchronous Mode 0 ......................................30
6.2.7 External Clock Drive ..............................................................................................31
7.0 Thermal Characteristics .................................................................................................... 33
8.0 80296SA Errata................................................................................................................. 33
9.0 Datasheet Revision History............................................................................................... 33
FIGURES
1.
2.
3.
4.
5.
6.
7.
8.
9.
80296SA Block Diagram ......................................................................................................1
The 80296SA Family Nomenclature ....................................................................................2
80296SA 100-pin QFP Package..........................................................................................3
ICC versus Frequency in Reset ...........................................................................................17
Effect of Clock Mode on CLKOUT......................................................................................18
System Bus Timings, Multiplexed Bus Mode .....................................................................22
Example READY Timings at 50 MHz, Multiplexed Bus, BUSCONx = 1 Wait State...........23
System Bus Timings, Demultiplexed Bus Mode.................................................................26
Example READY Timings at 50 MHz, Demultiplexed Bus, BUSCONx = 1 Wait State......27
10. Deferred Bus Mode Timing Diagram..................................................................................28
11. HOLD#, HLDA# Timing Diagram .......................................................................................29
12. Serial Port Waveform — Synchronous Mode 0..................................................................30
13. External Clock Drive Waveforms........................................................................................31
14. AC Testing Input and Output Waveforms During 5.0 Volt Testing.....................................32
15. Float Waveforms During 5.0 Volt Testing...........................................................................32
PRELIMINARY
iii
CONTENTS
TABLES
1.
2.
3.
4.
5.
6.
7.
8.
9.
Description of Product Nomenclature ..................................................................................2
80296SA 100-pin QFP Pin Assignment...............................................................................4
80296SA 100-pin QFP Pin Assignment Arranged by Functional Categories ......................5
Signal Descriptions ..............................................................................................................6
80296SA Address Map ......................................................................................................13
DC Characteristics Over Specified Operating Conditions..................................................14
AC Timing Symbol Definitions............................................................................................19
AC Characteristics the 80C296SA Will Meet, Multiplexed Bus Mode................................20
AC Characteristics the External Memory System Must Meet, Multiplexed Bus Mode.......21
10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode ...........................24
11. AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode ..25
12. HOLD#, HLDA# Timings....................................................................................................29
13. Serial Port Timing — Synchronous Mode 0.......................................................................30
14. External Clock Drive...........................................................................................................31
15. Thermal Characteristics .....................................................................................................33
iv
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
1.0 PRODUCT OVERVIEW
The 80296SA is a member of Intel’s 16-bit MCS® 96 microcontroller family. The 80296SA features 6 Mbytes
of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation. The device has hardware and instructions to support
various digital signal processing algorithms.
Code/Data
RAM
(2 Kbytes)
Port 3
Memory Addr Bus (24)
Baud-
rate
Generator
SIO
Memory Data Bus (16)
Chip-select
Unit
Bus Control Signals
Port 2
Bus
Controller
A19:16
A15:0
Peripheral
Bus
Interface
AD15:0
PWM
Port 4
Aligner
Queue
Instruction
Sequencer
Interrupt
Controller
Timer 1
Timer 2
EPA
Source 1 Addr (24)
Source 1 Data (16)
Source 2 Addr (24)
Source 2 Data (16)
Port 1
Memory
Interface
Unit
Register File
(3-port RAM)
ALU
Destination Addr (24)
Destination Data (16)
A3175-02
Figure 1. 80296SA Block Diagram
PRELIMINARY
1
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
2.0 NOMENCLATURE OVERVIEW
X
XX
8
X
X
XXXXX XX
A2815-01
Figure 2. The 80296SA Family Nomenclature
Table 1. Description of Product Nomenclature
Parameter
Options
Description
no mark
Commercial operating temperature range (0°C to 70°C)
with Intel standard burn-in.
Temperature and Burn-in Options
Packaging Options
Program–memory Options
Process Information
Product Family
S
0
QFP
Without ROM
CHMOS
—
no mark
296SA
40
40 MHz
50 MHz
Device Speed
50
2
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
3.0 PINOUT
V
AD0
NC
RESET#
NMI
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SS
A18 / EPORT.2
A19 / EPORT.3
WR# / WRL#
RD#
BHE# / WRH#
ALE
INST
READY
RPD
ONCE
NC
A0
A1
V
CC
V
9
SS
A2
A3
A4
A5
A6
A7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PLLEN2
V
V
A8
S80296SA
CC
SS
V
A9
CC
V
A10
A11
A12
A13
A14
A15
SS
PLLEN1
P3.0 / CS0#
P3.1 / CS1#
P3.2 / CS2#
P3.3 / CS3#
View of component as
mounted on PC board
V
V
SS
SS
P3.4 / CS4#
P3.5 / CS5#
P3.6 / EXTINT2
NC
XTAL1
XTAL2
V
P2.7 / CLKOUT
V
P2.6 / HLDA#
P2.5 / HOLD#
SS
P3.7 / EXTINT3
P1.0 / EPA0
CC
V
CC
A3155-02
Figure 3. 80296SA 100-pin QFP Package
PRELIMINARY
3
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 2. 80296SA 100-pin QFP Pin Assignment
Pin
1
Name
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
EXTINT2/P3.6
NC (see Note)
EXTINT3/P3.7
EPA0/P1.0
VCC
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
HOLD#/P2.5
HLDA#/P2.6
VCC
Pin
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Name
AD0
RD#
2
NC (see Note)
RESET#
NMI
WR#/WRL#
EPORT.3/A19
EPORT.2/A18
VSS
3
4
CLKOUT/P2.7
VSS
5
NC (see Note)
A0
6
EPA1/P1.1
EPA2/P1.2
EPA3/P1.3
T1CLK/P1.4
T1DIR/P1.5
VCC
XTAL2
XTAL1
VSS
VCC
7
A1
EPORT.1/A17
EPORT.0/A16
AD15
8
VCC
9
VSS
A15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A2
A14
AD14
A3
A13
AD13
A4
T2CLK/P1.6
VSS
A12
AD12
A5
A11
AD11
A6
T2DIR/P1.7
PWM0/P4.0
PWM1/P4.1
PWM2/P4.2
P4.3
A10
AD10
A7
A9
AD9
VCC
A8
VSS
VSS
VSS
AD8
PLLEN1
CS0#/P3.0
CS1#/P3.1
CS2#/P3.2
CS3#/P3.3
VSS
VCC
VCC
VCC
PLLEN2
ONCE
RPD
AD7
VSS
AD6
TXD/P2.0
RXD/P2.1
EXTINT0/P2.2
BREQ#/P2.3
EXTINT1/P2.4
AD5
READY
INST
AD4
AD3
CS4#/P3.4
CS5#/P3.5
ALE
AD2
BHE#/WRH#
100 AD1
NOTE: For compatibility with future products, tie pin 5 to VCC and leave pins 2 and 27 unconnected.
4
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 3. 80296SA 100-pin QFP Pin Assignment Arranged by Functional Categories
Address & Data
Address & Data
Name Pin
Input/Output
Name
Power & Ground
(continued)
Name
Pin
87
86
85
84
Pin
19
20
21
22
24
25
29
31
32
33
83
82
79
78
48
49
50
51
52
54
26
28
43
40
41
42
47
34
35
37
39
46
Name
Pin
A0
6
7
AD12
AD13
AD14
AD15
CS0#/P3.0
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
8
A1
CS1#/P3.1
CS2#/P3.2
CS3#/P3.3
CS4#/P3.4
CS5#/P3.5
EPA0/P1.0
EPA1/P1.1
EPA2/P1.2
EPA3/P1.3
EPORT.0
EPORT.1
EPORT.2
EPORT.3
P2.2
16
30
36
44
53
68
81
93
9
A2
10
11
12
13
14
15
66
65
64
63
62
61
60
59
83
82
79
78
1
A3
A4
Bus Control & Status
A5
Name
Pin
74
75
49
51
52
73
76
72
77
A6
ALE
A7
BHE#/WRH#
BREQ#
HOLD#
HLDA#
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
17
23
38
45
55
58
67
80
91
INST
RD#
READY
WR#/WRL#
P2.3
Processor Control
Name Pin
CLKOUT
P2.4
P2.5
54
48
50
26
28
4
P2.6
EXTINT0
EXTINT1
EXTINT2
EXTINT3
NMI
P2.7
P3.6
No Connection
Name
100
99
98
97
96
95
94
92
90
89
88
P3.7
Pin
2
P4.3
NC
NC
NC
PWM0/P4.0
PWM1/P4.1
PWM2/P4.2
RXD/P2.1
T1CLK/P1.4
T1DIR/P1.5
T2CLK/P1.6
T2DIR/P1.7
TXD/P2.0
5
ONCE
70
3
27
RESET#
RPD
71
57
56
18
69
XTAL1
XTAL2
PLLEN1
PLLEN2
PRELIMINARY
5
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
4.0 SIGNALS
Table 4. Signal Descriptions
Name
A15:0
Type
Description
I/O
System Address Bus
These address pins provide address bits 0–15 during the entire external memory
cycle during both multiplexed and demultiplexed bus modes.
A19:16
I/O
Address Pins 16–19
These address pins provide address bits 16–19 during the entire external memory
cycle during both multiplexed and demultiplexed bus modes, supporting extended
addressing of the 1-Mbyte address space.
NOTE: Internally, there are 24 address bits; however, only 20 external address
pins (A19:0) are implemented. The internal address space is 16 Mbytes
(000000–FFFFFFH) and the external address space is 1 Mbyte (00000–
FFFFFH). The microcontroller resets to FF2080H.
A19:16 share package pins with EPORT.3:0.
Address/Data Lines
AD15:0
ALE
I/O
O
These pins provide a multiplexed address and data bus. During the address phase
of the bus cycle, address bits 0–15 are presented on the bus and can be latched
using ALE or ADV#. During the data phase, 8- or 16-bit data is transferred.
AD7:0 share package pins with P3.7:0. AD15:8 share package pins with P4.7:0.
Address Latch Enable
This active-high output signal is asserted only during external memory cycles. ALE
signals the start of an external bus cycle and indicates that valid address information
is available on the system address/data bus (A19:16 and AD15:0 for a multiplexed
bus; A19:0 for a demultiplexed bus).
An external latch can use this signal to demultiplex address bits 0–15 from the
address/data bus in multiplexed mode.
BHE#
O
Byte High Enable†
During 16-bit bus cycles, this active-low output signal is asserted for word and high-
byte reads and writes to external memory. BHE# indicates that valid data is being
transferred over the upper half of the system data bus. Use BHE#, in conjunction
with address bit 0 (A0 for a demultiplexed address bus, AD0 for a multiplexed
address/data bus), to determine which memory byte is being transferred over the
system bus:
BHE#
AD0 or A0 Byte(s) Accessed
0
0
1
0
1
0
both bytes
high byte only
low byte only
BHE# shares a package pin with WRH#.
†
Chip configuration register 0 (CCR0) determines whether this pin functions as
BHE# or as WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
6
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. Signal Descriptions (Continued)
Name
BREQ#
Type
Description
O
Bus Request
This active-low output signal is asserted during a hold cycle when the bus controller
has a pending external memory cycle. When the bus-hold protocol is enabled
(WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the
configuration selected through the port configuration registers (P2_MODE, P2_DIR,
and P2_REG). An attempt to change the pin configuration is ignored until the bus-
hold protocol is disabled (WSR.7 is cleared).
The microcontroller can assert BREQ# at the same time as or after it asserts
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted.
BREQ# shares a package pin with P2.3.
Clock Output
CLKOUT
O
Output of the internal clock generator. The CLKOUT frequency is ½ the internal
operating frequency (f). CLKOUT has a 50% duty cycle.
CLKOUT shares a package pin with P2.7.
Chip-select Lines 0–5
CS5:0#
O
The active-low output CSx# is asserted during an external memory cycle when the
address to be accessed is in the range programmed for chip select x or chip select
x+1 if remapping is enabled. If the external memory address is outside the range
assigned to the six chip selects, no chip-select output is asserted and the bus
configuration defaults to the CS5# values.
Immediately following reset, CS0# is automatically assigned to the range FF2000–
FF20FFH.
CS5:0# share package pins with P3.5:0.
EPA3:0
I/O
I/O
Event Processor Array (EPA) Capture/Compare Channels
High-speed input/output signals for the EPA capture/compare channels. For high-
speed PWM applications, the outputs of two EPA channels (either EPA0 and EPA1
or EPA2 and EPA3) can be remapped to produce a PWM waveform on a shared
output pin.
EPA3:0 share package pins with P1.3:0.
EPORT.3:0
Extended Addressing Port
This is a standard 4-bit, bidirectional port.
EPORT.3:0 share package pins with A19:16.
PRELIMINARY
7
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. Signal Descriptions (Continued)
Name
Type
Description
EXTINT3:0
I
External Interrupts
These programmable interrupts are controlled by the EXTINT_CON register. This
register controls whether the interrupt is edge-triggered or level-sensitive and
whether a rising edge/high level or falling edge/low level activates the interrupt.
In standby and powerdown modes, asserting the EXTINTx signal causes the device
to resume normal operation. The interrupt does not need to be enabled, but the pin
must be configured as a special-function input. If the EXTINTx interrupt is enabled,
the CPU executes the interrupt service routine. Otherwise, the CPU executes the
instruction that immediately follows the command that invoked the power-saving
mode.
In idle mode, asserting any enabled interrupt causes the device to resume normal
operation.
EXTINT0 shares a package pin with P2.2, EXTINT1 shares a package pin with
P2.4, EXTINT2 shares a package pin with P3.6, and EXTINT3 shares a package pin
with P3.7.
HLDA#
HOLD#
INST
O
Bus Hold Acknowledge
This active-low output indicates that the CPU has released the bus as the result of
an external device asserting HOLD#. When the bus-hold protocol is enabled
(WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of the
configuration selected through the port configuration registers (P2_MODE, P2_DIR,
and P2_REG). An attempt to change the pin configuration is ignored until the bus-
hold protocol is disabled (WSR.7 is cleared).
HLDA# shares a package pin with P2.6.
Bus Hold Request
I
An external device uses this active-low input signal to request control of the bus.
When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can
function only as HOLD#, regardless of the configuration selected through the port
configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change
the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is
cleared).
HOLD# shares a package pin with P2.5.
Instruction Fetch
O
When high, INST indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle of an external
instruction fetch. INST is low for data accesses, including interrupt vector fetches
and chip configuration byte reads. INST is low during internal memory fetches.
8
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. Signal Descriptions (Continued)
Name
NMI
Type
Description
I
Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt.
NMI has the highest priority of all interrupts except trap and unimplemented opcode.
Assert NMI for greater than one state time to guarantee that it is recognized.
If NMI is held high during and immediately following reset, the microcontroller will
execute the NMI interrupt service routine when code execution begins. To prevent
an inadvertent NMI interrupt vector, the first instruction (at F2080H) must clear the
NMI pending interrupt bit.
ANDB INT_PEND1, #7FH.
During idle mode, a rising edge on NMI causes the microcontroller to exit idle mode
and branch to the interrupt service routine.
ONCE
I
On-circuit Emulation
Holding ONCE high during the rising edge of RESET# places the microcontroller
into on-circuit emulation (ONCE) mode. This mode puts all pins, except READY,
RESET#, ONCE, and NMI, into a high-impedance state, thereby isolating the
microcontroller from other components in the system. The value of ONCE is latched
when the RESET# pin goes inactive. While the microcontroller is in ONCE mode,
you can debug the system using a clip-on emulator.
To exit ONCE mode, reset the microcontroller by pulling the RESET# signal low. To
prevent inadvertent entry into ONCE mode, connect the ONCE pin to VSS
.
P1.7:0
P2.7:0
I/O
I/O
Port 1
This is a standard, 8-bit, bidirectional port that shares package pins with individually
selectable special-function signals.
Port 1 shares package pins with the following signals: P1.0/EPA0, P1.1/EPA1,
P1.2/EPA2, P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR.
Port 2
This is a standard, 8-bit, bidirectional port that shares package pins with individually
selectable special-function signals.
Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD,
P2.2/EXTINT0, P2.3/BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and
P2.7/CLKOUT.
P3.7:0
P4.3:0
I/O
I/O
Port 3
This is a standard, 8-bit, bidirectional port that shares package pins with individually
selectable special-function signals.
Port 3 shares package pins with the following signals: P3.0/CS0#, P3.1/CS1#,
P3.2/CS2#, P3.3/CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and
P3.7/EXTINT3.
Port 4
Port 4 is a standard, 4-bit, bidirectional I/O port with high-current drive capability.
Port 4 shares package pins with the following signals: P4.0/PWM0, P4.1/PWM1,
and P4.2/PWM2. P4.3 has a dedicated package pin.
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Table 4. Signal Descriptions (Continued)
Name
Type
Description
PLLEN2:1
I
Phase-locked Loop 1 and 2 Enable
These input pins enable the on-chip clock multiplier feature and select either the
doubled or the quadrupled clock speed:
PLLEN2
PLLEN1
Mode
0
0
1
1
0
1
0
1
1x mode; PLL disabled; f = FXTAL1
2x mode; PLL enabled; f = 2FXTAL1
Reserved †
4x mode; PLL enabled; f = 4FXTAL1
† CAUTION: This reserved combination causes the device to enter an unsupported
test mode.
PWM2:0
O
Pulse Width Modulator Outputs
These are PWM output pins with high-current drive capability. The duty cycle and
frequency-pulse-widths are programmable.
PWM2:0 share package pins with P4.2:0.
Read
RD#
O
I
Read-signal output to external memory. RD# is asserted during external memory
reads.
READY
Ready Input
This active-high input can be used to insert wait states in addition to those
programmed in chip configuration byte 0 (CCB0) and the bus control x register
(BUSCONx).
CCB0 is programmed with the minimum number of wait states (0, 5, 10, 15) for an
external fetch of CCB1, and BUSCONx is programmed with the minimum number of
wait states (0–15) for all external accesses to the address range assigned to the
chip-select x channel.
If the programmed number of wait states is greater than zero and READY is low
when this programmed number of wait states is reached, additional wait states are
added until READY is pulled high. If the programmed number of wait states is equal
to zero, hold the READY pin high. Programming the number of wait states equal to
zero and holding the READY pin low produces unpredictable results.
RESET#
I/O
Reset
A level-sensitive reset input to, and an open-drain system reset output from, the
microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-
down transistor connected to the RESET# pin for 16 state times.
In the powerdown, standby, and idle modes, asserting RESET# causes the
microcontroller to reset and return to normal operating mode. If the phase-locked
loop (PLL) clock circuitry is enabled, you must hold RESET# low for at least 2 ms to
allow the PLL to stabilize before the internal CPU and peripheral clocks are enabled.
After a reset, the first instruction fetch is from FF2080H.
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Table 4. Signal Descriptions (Continued)
Name
RPD
Type
Description
I
Return from Powerdown
Timing pin for the return-from-powerdown circuit.
If your application uses powerdown mode, connect a capacitor between RPD and
V
SS if either of the following conditions are true.
•
•
the internal oscillator is the clock source
the phase-locked loop (PLL) circuitry is enabled (see PLLEN2:1 signal
description)
The capacitor causes a delay (at least 2 ms) that enables the oscillator and PLL
circuitry to stabilize before the internal CPU and peripheral clocks are enabled.
Refer to the “Special Operating Modes” chapter of the 80296SA Microcontroller
User’s Manual for details on selecting the capacitor.
The capacitor is not required if your application uses powerdown mode and if both
of the following conditions are true.
•
•
an external clock input is the clock source
the phase-locked loop circuitry is disabled
If your application does not use powerdown mode, leave this pin unconnected.
Receive Serial Data
RXD
I/O
In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as
either an input or an open-drain output for data.
RXD shares a package pin with P2.1.
Timer 1 External Clock
T1CLK
I
External clock for timer 1. Timer 1 increments (or decrements) on both rising and
falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature
counting mode.
and
External clock for the serial I/O baud-rate generator input (program selectable).
T1CLK shares a package pin with P1.4.
T2CLK
T1DIR
T2DIR
I
I
I
Timer 2 External Clock
External clock for timer 2. Timer 2 increments (or decrements) on both rising and
falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature
counting mode.
T2CLK shares a package pin with P1.6.
Timer 1 External Direction
External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high and
decrements when it is low. Also used in conjunction with T1CLK for quadrature
counting mode.
T1DIR shares a package pin with P1.5.
Timer 2 External Direction
External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and
decrements when it is low. It is also used in conjunction with T2CLK for quadrature
counting mode.
T2DIR shares a package pin with P1.7.
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Table 4. Signal Descriptions (Continued)
Name
TXD
Type
Description
O
Transmit Serial Data
In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is
the serial clock output.
TXD shares a package pin with P2.0.
VCC
VSS
PWR Digital Supply Voltage
Connect each VCC pin to the digital supply voltage.
GND Digital Circuit Ground
These pins supply ground for the digital circuitry. Connect each VSS pin to ground
through the lowest possible impedance path.
Write†
WR#
O
This active-low output indicates that an external write is occurring. This signal is
asserted only during external memory writes.
WR# shares a package pin with WRL#.
†
Chip configuration register 0 (CCR0) determines whether this pin functions as
WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
WRH#
O
Write High†
During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes
and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for
all write operations.
WRH# shares a package pin with BHE#.
†
Chip configuration registrer 0 (CCR0) determines whether this pin functions as
BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
WRL#
O
Write Low†
During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes
and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for
all write operations.
WRL# shares a package pin with WR#.
†
Chip configuration register 0 (CCR0) determines whether this pin functions as
WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
XTAL1
XTAL2
I
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator, internal phase-locked loop circuitry, and the internal
clock generators. The internal clock generators provide the peripheral clocks, CPU
clock, and CLKOUT signal. When using an external clock source instead of the on-
chip oscillator, connect the clock input to XTAL1. The external clock signal must
meet the VIH specification for XTAL1.
O
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses
an external clock source instead of the on-chip oscillator.
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Table 5. 80296SA Address Map
5.0 ADDRESS MAP
Hex
Address
Addressing Modes for
Description (Note 1, Note 2)
Data Accesses
FFFFFF External device (memory or I/O) in 1-Mbyte mode (CCB1.1=0)
Extended
Extended
Extended
Extended
—
FFF800
A copy of internal code RAM in 64-Kbyte mode (CCB1.1=1)
FFF7FF
FF2080
External program memory (Note 3)
FF207F
FF2000
External special-purpose memory (CCBs and interrupt vectors)
External device (memory or I/O) connected to address/data bus
Reserved for in-circuit emulators
FF1FFF
FF0400
FF03FF
FF0000
FEFFFF Overlaid memory (reserved for future devices);
—
0F0000
locations xF0000–xF03FFH are reserved for in-circuit emulators
0EFFFF
010000
External device (memory or I/O) connected to address/data bus
Extended
00FFFF Internal code RAM (code or data); can be windowed by WSR1. In Indirect, indexed, extended,
00F800
64-Kbyte mode, code RAM is identically mapped into page FFH.
windowed direct
00F7FF
00F000
External device (memory or I/O) connected to address/data bus;
can be windowed by WSR1
Indirect, indexed, extended,
windowed direct
00EFFF
002000
External device (memory or I/O) connected to address/data bus
Indirect, indexed, extended
001FFF
001F00
Internal peripheral special-function registers (SFRs);
can be windowed by WSR or WSR1
Indirect, indexed, extended,
windowed direct
001EFF
001C00
Reserved (future SFR expansion)
—
001BFF
000400
External device (memory or I/O) connected to address/data bus
Reserved (future register file expansion)
Indirect, indexed, extended
—
0003FF
000200
0001FF
000100
Upper register file (general-purpose register RAM)
can be windowed by WSR or WSR1
Indirect, indexed, extended
windowed direct
0000FF
00001A
Direct, indirect, indexed,
extended
Lower register file (general-purpose register RAM)
Lower register file (stack pointer and CPU SFRs)
000019
000000
Direct
NOTES:
1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.
2. The contents or functions of reserved locations may change in future device revisions, in which case a
program that relies on one or more of these locations might not function properly.
3. External memory occupies the boot memory partition, FF2080–FF7FFH. After reset, the default chip-
select line (CS0#) is active; the first instruction fetch is from FF2080H.
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6.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This datasheet contains information on
new products in production. The specifications are
subject to change without notice. Verify with your
local Intel sales office that you have the latest
datasheet before finalizing a design.
Storage Temperature ................................... –60°C to +150°C
Supply Voltage with Respect to VSS............... –0.5 V to +7.0 V
Power Dissipation........................................................... 1.5 W
OPERATING CONDITIONS*
*WARNING: Stressing the device beyond the
“Absolute Maximum Ratings” may cause
permanent damage. These are stress ratings only.
Operation beyond the “Operating Conditions” is not
recommended and extended exposure beyond the
“Operating Conditions” may affect device reliability.
TA (Ambient Temperature Under Bias) ................0°C to +70°C
VCC (Digital Supply Voltage) ............................. 4.5 V to 5.5 V
FXTAL1 (Input frequency for VCC = 4.5 V – 5.5 V)
(Note 1, 2, 3)........................................ 16 MHz to 50 MHz
NOTES:
1. This device is static and should operate below
1 Hz, but has been tested only down to 16 MHz.
2. When the phase-locked loop (PLL) circuitry is
enabled, the minimum input frequency on XTAL1
is 8 MHz. The PLL cannot be run at frequencies
lower than 16 MHz.
3. Assumes an external clock. The maximum fre-
quency for an external crystal oscillator is 25
MHz.
6.1 DC Characteristics
Table 6. DC Characteristics Over Specified Operating Conditions
Typical
(Note 1)
Test
Conditions
Symbol
Parameter
Min
Max
Units
ICC
VCC Supply Current
90
45
150
mA
XTAL1 = 50 MHz
V
CC = 5.5 V
Device in Reset
IIDLE
Idle Mode Current
60
mA
XTAL1 = 50 MHz
V
CC = 5.5 V
NOTES:
1. Typical values are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature with VCC = 5.0 V.
2. For temperatures below 100°C, typical is 10 µA.
3. For all pins except P4.3:0, which have higher drive capability (see VOL1).
4. During normal (non-transient) conditions, the following maximum current limits apply for pin groups
and individual pins:
Group
I
OL (mA)
IOH (mA)
Individual IOL (mA)
IOH (mA)
P1.7:3, P4
P2
P1.2:0, P3
40
40
40
40
40
40
P1, P2, P3
P4
10
18
10
10
5. For all pins that were weakly pulled high during reset. This excludes ALE, INST, and NMI, which were
weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3).
6. Pin capacitance is not tested. This value is based on design simulations.
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Table 6. DC Characteristics Over Specified Operating Conditions (Continued)
Typical
(Note 1)
Test
Conditions
Symbol
Parameter
Min
Max
Units
IPD
Powerdown Mode Current
20
50
µA
VCC = 5.5 V
(Note 2)
ISTDBY
ILI
Standby Mode
8
15
mA
µA
VCC = 5.5 V
VSS < VIN < VCC
Input Leakage Current
(Standard Inputs)
±10
VIL
Input Low Voltage (all pins)
Input Low Voltage XTAL1
Input High Voltage
–0.5
–0.5
0.8
V
V
V
V
VIL1
VIH
0.3 VCC
VCC + 0.5
VCC + 0.5
0.2 VCC +1
0.7 VCC
VIH1
VOL
Input High Voltage XTAL1
Output Low Voltage (output
configured as complementary)
(Note 3, 4)
0.3
0.45
1.5
V
V
V
I
I
I
OL = 200 µA
OL = 3.2 mA
OL = 7.0 mA
VOL
Output Low Voltage on P4.3:0
(output configured as comple-
mentary) (Note 4)
0.45
0.6
V
V
IOL = 8 mA
OL = 15 mA
1
I
VOL
Output Low Voltage in Reset
on ALE, INST, and NMI
0.45
0.45
V
V
IOL = 3 µA
2
VOL
Output Low Voltage in Reset
on ONCE pin
IOL = 30 µA
3
VOL
Output Low Voltage on XTAL2
0.3
0.45
1.5
V
V
V
I
I
I
OL = 100 µA
OL = 700 µA
OL = 3 mA
4
VOH
Output High Voltage (output
configured as complementary)
(Note 4)
VCC – 0.5
V
V
V
I
I
I
OH = –200 µA
OH = –3.2 mA
OH = –7.0 mA
VCC – 0.9
CC – 1.5
V
VOH
Output High Voltage in Reset
(Note 5)
VCC – 0.7
V
IOH = –3 µA
1
NOTES:
1. Typical values are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature with VCC = 5.0 V.
2. For temperatures below 100°C, typical is 10 µA.
3. For all pins except P4.3:0, which have higher drive capability (see VOL1).
4. During normal (non-transient) conditions, the following maximum current limits apply for pin groups
and individual pins:
Group
IOL (mA)
IOH (mA)
Individual IOL (mA)
IOH (mA)
P1.7:3, P4
P2
P1.2:0, P3
40
40
40
40
40
40
P1, P2, P3
P4
10
18
10
10
5. For all pins that were weakly pulled high during reset. This excludes ALE, INST, and NMI, which were
weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3).
6. Pin capacitance is not tested. This value is based on design simulations.
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Table 6. DC Characteristics Over Specified Operating Conditions (Continued)
Typical
(Note 1)
Test
Conditions
Symbol
Parameter
Min
Max
Units
VOH2
Output High Voltage on XTAL2 VCC – 0.3
V
V
V
IOH = –100 µA
IOH = –700 µA
IOH = –3 mA
V
V
CC – 0.7
CC – 1.5
VOH3
Output High Voltage on
READY in Reset
VCC –1.1
V
VTH+
VTH–
–
Hysteresis voltage width on
RESET# pin
0.3
V
CS
Pin Capacitance (any pin to
VSS) (Note 6)
10
pF
kΩ
RRST
Reset Pull-up Resistor
50
150
VCC = 5.5 V,
VIN = 4.0 V
NOTES:
1. Typical values are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature with VCC = 5.0 V.
2. For temperatures below 100°C, typical is 10 µA.
3. For all pins except P4.3:0, which have higher drive capability (see VOL1).
4. During normal (non-transient) conditions, the following maximum current limits apply for pin groups
and individual pins:
Group
I
OL (mA)
IOH (mA)
Individual IOL (mA)
IOH (mA)
P1.7:3, P4
P2
P1.2:0, P3
40
40
40
40
40
40
P1, P2, P3
P4
10
18
10
10
5. For all pins that were weakly pulled high during reset. This excludes ALE, INST, and NMI, which were
weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3).
6. Pin capacitance is not tested. This value is based on design simulations.
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140
120
100
80
60
40
20
0
0
5
10
15
20
25
30
35
40
45
50
Frequency (MHz)
A4379-01
Figure 4. ICC versus Frequency in Reset
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2 AC Characteristics
6.2.1 RELATIONSHIP OF XTAL1 TO CLKOUT
TXHCH
XTAL1
(12.5 MHz)
f
PLLEN2:1=00
t = 80ns
CLKOUT
f
PLLEN2:1=01
t = 40ns
CLKOUT
f
PLLEN2:1=11
t = 20ns
CLKOUT
A3160-02
Figure 5. Effect of Clock Mode on CLKOUT
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6.2.2 EXPLANATION OF AC SYMBOLS
Each AC timing symbol is two pairs of letters prefixed by “T” for time. The characters in a pair indicate a signal
and its condition, respectively. Symbols represent the time between the two signal/condition points.
Table 7. AC Timing Symbol Definitions
Character
Signal(s)
A
B
AD15:0, A19:0
BHE#
BR
C
BREQ#
CLKOUT
D
AD15:0, AD7:0, RXD (SIO mode 0 input data)
H
HOLD#
HA
L
HLDA#
ALE
Q
R
AD15:0, AD7:0, RXD (SIO mode 0 output data)
RD#
S
CSx#
W
X
WR#, WRH#,WRL#
XTAL1, TXD (SIO clock)
READY
Y
Character
Condition
H
L
High
Low
V
X
Z
Valid
No Longer Valid
Floating (low impedance)
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80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.3 AC CHARACTERISTICS — MULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 8. AC Characteristics the 80C296SA Will Meet, Multiplexed Bus Mode
Symbol
Parameter
Frequency on XTAL1, PLL in 1x mode
Frequency on XTAL1, PLL in 2x mode
Frequency on XTAL1, PLL in 4x mode
Operating frequency, f = FXTAL1; PLL in 1x mode
Operating frequency, f = 2FXTAL1; PLL in 2x mode
Operating frequency, f = 4FXTAL1; PLL in 4x mode
Period, t = 1/f
Min
16
Max
50 (1)
25
Units
MHz
MHz
MHz
FXTAL1
8 (2)
8 (2)
12.5
f
16
50
MHz
t
20
3
62.5
50
ns
ns
TXHCH
TCLCL
TCHCL
TAVWL
TCLLH
TLLCH
TLHLH
TLHLL
TAVLL
TLLAX
TLLRL
TRLCL
TRLRH
TRHLH
TRLAZ
TLLWL
TQVWH
TCHWH
TWLWH
NOTES:
XTAL1 Rising Edge to CLKOUT High or Low
CLKOUT Cycle Time
2t
ns
CLKOUT High Period
t – 10
2t – 25
–13
t + 15
ns
Address Valid to WR# Falling Edge
CLKOUT Falling Edge to ALE Rising Edge
ALE Falling Edge to CLKOUT Rising Edge
ALE Cycle Time
ns
10
15
ns
–15
ns
4t
ns (3)
ns
ALE High Period
t – 10
t – 15
1
t + 10
Address Valid to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD# Falling Edge
RD# Low to CLKOUT Falling Edge
RD# Low Period
ns
ns
3
ns
–10
20
ns
2t – 25
t – 5
ns (3)
ns (4)
ns
RD# Rising Edge to ALE Rising Edge
RD# Low to Address Float
t + 15
5
ALE Falling Edge to WR# Falling Edge
Data Stable to WR# Rising Edge
CLKOUT High to WR# Rising Edge
WR# Low Period
4
ns
2t – 27
–15
ns (3)
ns
5
2t – 25
ns (3)
1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
3. If wait states are used, add 2t × n, where n = number of wait states.
4. Assuming back-to-back bus cycles.
5. 8-bit bus only.
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Table 8. AC Characteristics the 80C296SA Will Meet, Multiplexed Bus Mode (Continued)
Symbol
TWHQX
TWHLH
TWHBX
TWHAX
TRHBX
Parameter
Data Hold after WR# Rising Edge
Min
t – 7
t – 15
0
Max
Units
ns
WR# Rising Edge to ALE Rising Edge
BHE#, INST Hold after WR# Rising Edge
AD15:8 Hold after WR# Rising Edge
BHE#, INST Hold after RD# Rising Edge
AD15:8 Hold after RD# Rising Edge
A19:16, CS# Hold after WR# Rising Edge
A19:16, CS# Hold after RD# Rising Edge
t + 20
ns
ns
t – 4
0
ns (5)
ns
TRHAX
t – 4
0
ns (5)
ns
TW
HSH
TRHSH
0
ns
NOTES:
1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
3. If wait states are used, add 2t × n, where n = number of wait states.
4. Assuming back-to-back bus cycles.
5. 8-bit bus only.
Table 9. AC Characteristics the External Memory System Must Meet, Multiplexed Bus Mode
Symbol
TAVDV
Parameter
AD15:0 Valid to Input Data Valid
Min
Max
Units
ns (1, 2)
ns (1, 2)
ns (1, 2)
ns
3t – 32
2t – 40
4t – 28
2t – 25
t – 3
TRLDV
RD# Active to Input Data Valid
TSLDV
Chip Select Low to Data Valid
TCHDV
TRHDZ
TRXDX
TAVYV
CLKOUT High to Input Data Valid
End of RD# to Input Data Float
ns (2)
ns
Data Hold after RD# Inactive
0
AD15:0 Valid to READY (Inactive) Setup
First READY Hold (active) after CLKOUT High
Non-first READY Hold (active) after CLKOUT High
Non-READY (Inactive) Time
2t – 42
2t – 21
2t – 21
ns (3)
ns (4, 5)
ns (4)
TCH1YX
TCH2YX
TYLYH
t – 4
0
No Upper
Limit
2t
ns
NOTES:
1. If using the READY signal to insert wait states, you must program at least one wait state in the
BUSCONx register because the first falling edge of READY is not synchronized with a CLKOUT edge.
2. If using the BUSCONx register without the READY signal to insert wait states, add 2t × n, where n =
number of wait states.
3. If using the BUSCONx register to insert wait states, add 2t × (n–1), where n = number of wait states.
4. Exceeding the maximum specification causes additional wait states.
5. If you program two or more wait states in the BUSCONx register, the TCH1YX minimum does not apply.
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6.2.3.1
System Bus Timings, Multiplexed Bus
T
CLCL
T
t
CHDV
T
T
T
CHCL
CLLH
RLCL
CLKOUT
T
T
LLCH
RHLH
T
LHLH
T
LHLL
T
LLRL
ALE
RD#
T
RLRH
T
T
RLAZ
RHDZ
T
RLDV
T
LLAX
T
AVLL
T
AVDV
AD15:0
(read)
Address Out
Data In
T
CHWH
T
T
T
LLWL
WHLH
T
T
WLWH
WHQX
WR#
QVWH
AD15:0
(write)
Address Out
Data Out
Address Out
WHBX RHBX
T
, T
BHE#, INST
T
, T
WHAX RHAX
High Address Out
AD15:8
(8-bit mode)
A19:16
CSx#
Extended Address Out
T
, T
WHSH RHSH
A3251-01
Figure 6. System Bus Timings, Multiplexed Bus Mode
22
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.3.2
READY Timing, Multiplexed Bus
CH0
T
CH1
CH2
CH3
T
CH YX
1
t
t
t
t
t
t
CLKOUT
T
YLYH
AVYV
First
READY
T
CH YX
2
Non-first
READY
T
+ 2t
LHLH
ALE
RD#
T
+ 2t
RLRH
T
T
+ 2t
+ 2t
RLDV
AVDV
AD15:0
(read)
Addr Out
Addr Out
Data In
T
+ 2t
WLWH
T
WR#
+ 2t
QVWH
AD15:0
(write)
Data Out
BHE#,INST
A19:16
CS0#
A5330-01
Figure 7. Example READY Timings at 50 MHz, Multiplexed Bus, BUSCONx = 1 Wait State
PRELIMINARY
23
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.4 AC CHARACTERISTICS — DEMULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode
Symbol
Parameter
Frequency on XTAL1, PLL in 1x mode
Frequency on XTAL1, PLL in 2x mode
Frequency on XTAL1, PLL in 4x mode
Operating frequency, f = FXTAL1; PLL in 1x mode
Operating frequency, f = 2FXTAL1; PLL in 2x mode
Operating frequency, f = 4FXTAL1; PLL in 4x mode
Period, t = 1/f
Min
16
Max
50 (1)
25
Units
MHz
MHz
MHz
FXTAL1
8 (2)
8 (2)
12.5
f
16
50
MHz
t
20
t – 10
t – 10
t – 5
3
62.5
ns
ns
TAVWL
TAVRL
TRHRL
TXHCH
TCLCL
TCHCL
TCLLH
TLLCH
TLHLH
TLHLL
TRLCL
TRLRH
TRHLH
TWLCL
TQVWH
TCHWH
TWLWH
TWHQX
TWHLH
NOTES:
Address Valid to WR# Falling Edge
Address Valid to RD# Falling Edge
Read High to Next Read Low
ns
ns
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
50
ns
2t
ns
CLKOUT High Period
t – 10
–13
t + 15
10
ns
CLKOUT Falling Edge to ALE Rising Edge
ALE Falling Edge to CLKOUT Rising Edge
ALE Cycle Time
ns
–15
15
ns
4t
ns (3,4)
ns
ALE High Period
t – 10
–5
t + 10
11
RD# Low to CLKOUT Falling Edge
RD# Low Period
ns
3t – 18
t – 4
–8
ns (3)
ns (4)
ns
RD# Rising Edge to ALE Rising Edge
WR# Low to CLKOUT Falling Edge
Data Stable to WR# Rising Edge
CLKOUT High to WR# Rising Edge
WR# Low Period
t + 15
9
3t – 10
–11
ns (4)
ns
10
3t – 10
t – 5
t – 5
ns (3)
ns
Data Hold after WR# Rising Edge
WR# Rising Edge to ALE Rising Edge
t + 20
t + 10
ns (3)
1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
3. If using either READY or BUSCONx to insert wait states, add 2t × n, where n = number of wait states.
4. Assuming back-to-back bus cycles.
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PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 10. AC Characteristics the 80C296SA Will Meet, Demultiplexed Bus Mode (Continued)
Symbol
TWHBX
Parameter
Min
0
Max
Units
ns
BHE#, INST Hold after WR# Rising Edge
A19:0, CSx# Hold after WR# Rising Edge
BHE#, INST Hold after RD# Rising Edge
A19:0, CSx# Hold after RD# Rising Edge
TWHAX
0
ns
TRHBX
0
ns
TRHAX
0
ns
NOTES:
1. 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
3. If using either READY or BUSCONx to insert wait states, add 2t × n, where n = number of wait states.
4. Assuming back-to-back bus cycles.
Table 11. AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode
Symbol
TAVDV
Parameter
A19:0 Valid to Input Data Valid
Min
Max
4t – 28 ns (1, 2, 3)
3t – 25 ns (1, 2)
4t – 28 ns (1, 2, 3)
Units
TRLDV
RD# Active to Input Data Valid
TSLDV
Chip Select Low to Data Valid
TCHDV
TRHDZ
TRXDX
TAVYV
CLKOUT High to Input Data Valid
End of RD# to Input Data Float
2t – 25
t
ns
ns (2, 3)
ns
Data Hold after RD# Inactive
0
A19:0 Valid to READY Setup
3t – 45
2t – 21
2t – 21
ns (4)
ns (5, 6)
ns (5)
TCH1YX
TCH2YX
TYLYH
First READY Hold (active) after CLKOUT High
Non-first READY Hold (active) after CLKOUT High
Non READY (inactive) Time
t – 4
0
No Upper
Limit
2t
ns
NOTES:
1. If using the READY signal to insert wait states, you must program at least one wait state in the
BUSCONx register because the first falling edge of READY is not synchronized with a CLKOUT edge.
2. If using the BUSCONx register without the READY signal to insert wait states, add 2t × n, where n =
number of wait states.
3. If CSx# changes or if a write cycle follows a read cycle, add 2t (1 state).
4. If using the BUSCONx register to insert wait states, add (2t × n–1), where n = number of wait states.
5. Exceeding the maximum specification causes additional wait states.
6. If you program two or more wait states in the BUSCONx register, the TCH1YX minimum does not apply.
PRELIMINARY
25
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.4.1
System Bus Timings, Demultiplexed Bus
T
T
T
t
CHCL
CLCL
T
T
CLLH
CHWH
CLKOUT
ALE
T
LHLH
WHLH
T
T
LHLL
T
RHLH
LLCH
T
RHRL
T
RHDZ
T
RHAX
T
T
AVRL
RLRH
T
RD#
CHDV
T
RLDV
T
AVDV
T
SLDV
AD15:0
(read)
Data In
T
T
WHQX
WLCL
T
T
WHAX
AVWL
T
T
WLWH
WR#
QVWH
AD15:0
(write)
Data Out
T
, T
WHBX RHBX
BHE#, INST
A19:0
Address Out
CSx#
A3253-02
Figure 8. System Bus Timings, Demultiplexed Bus Mode
26
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.4.2
READY Timing, Demultiplexed Bus
CH0
T
CH1
CH2
CH3
t
t
t
t
t
t
CLKOUT
T
AVYV
CH YX
1
T
YLYH
First
READY
T
AVYV
T
CH YX
2
Non-first
READY
T
+ 2t
LHLH
ALE
RD#
T
+ 2t
RLRH
T
+ 2t
+ 2t
RLDV
T
AVDV
AD15:0
(read)
Data In
T
+ 2t
+ 2t
WLWH
QVWH
WR#
T
AD15:0
(write)
Data Out
BHE#,INST
A19:0
Address Out
CSx#
A3258-02
Figure 9. Example READY Timings at 50 MHz, Demultiplexed Bus, BUSCONx = 1 Wait State
PRELIMINARY
27
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.4.3
80296SA Deferred Bus Timing Mode
The deferred bus cycle mode is designed to reduce bus contention when using the 80296SA in demultiplexed
mode with slow memory devices. Unlike the 8XC196NU, in which this bus mode has to be enabled through
the CCR to take advantage of the feature, the 80296SA automatically invokes this mode whenever the
appropriate conditions occur. In the deferred mode, a delay of the WR# signal and the next bus cycle will
occur in the first bus cycle following a chip-select change and in the first write cycle following a read cycle.
This mode will work in parallel with wait states. Refer to Figure 11 to determine which control signals are
affected.
Cycle 1 is a normal 4t read cycle. Cycle 2 is a write cycle that follows a read cycle, so a 2t delay of the next
bus cycle is inserted. Notice that the chip-select change at the beginning of cycle 2 did not cause a double
delay (4t). The chip-select change in cycle 3, a read cycle, causes a 2t delay.
CLKOUT
T
+ 2t
LHLH
T
+ 2t
+ 2t
WHLH
ALE
RD#
T
+ 2t
RHLH
T
AVRL
T
+ 2t
AVDV
AD15:0
(read)
Data In
Data In
T
+ 2t
AVWL
WR#
AD15:0
(write)
Data Out
Data Out
Data Out
BHE#, INST
A19:0
Address Out
Valid
Valid
CSx#
A3247-02
Figure 10. Deferred Bus Mode Timing Diagram
28
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 12. HOLD#, HLDA# Timings
6.2.5 HOLD#, HLDA# TIMINGS
Symbol
Parameter
Min
30
Max
Units
ns
THVCH
HOLD# Setup time (to guarantee recognition at next clock)
CLKOUT Low to HLDA# Low
TCLHAL
TCLBRL
THALAZ
THALBZ
TCLHAH
TCLBRH
THAHAX
THAHBV
–15
–15
15
15
33
25
15
25
ns
CLKOUT Low to BREQ# Low
ns
HLDA# Low to Address Float
ns
HLDA# Low to BHE#, INST, RD#, WR# Weakly Driven
CLKOUT Low to HLDA# High
ns
–25
–25
–20
–20
ns
CLKOUT Low to BREQ# High
ns
HLDA# High to Address No Longer Float
HLDA# High to BHE#, INST, RD#, WR# Valid
ns
ns
CLKOUT
THVCH
THVCH
Hold Latency
HOLD#
HLDA#
BREQ#
TCLHAL
TCLHAH
TCLBRL
TCLBRH
THALAZ
THAHAX
A19:0, AD15:0
THALBZ
THAHBV
Weakly held inactive
TCLLH
CSx#, BHE#,
INST, RD#, WR#
WRL#, WRH#
ALE
Start of strongly driven ALE
A2460-03
Figure 11. HOLD#, HLDA# Timing Diagram
PRELIMINARY
29
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.2.6 AC CHARACTERISTICS — SERIAL PORT, SYNCHRONOUS MODE 0
Table 13. Serial Port Timing — Synchronous Mode 0
Symbol
TXLXL
Parameter
Serial Port Clock period†
Min
Max
Units
SP_BAUD ≥ x002H
SP_BAUD = x001H
6t
4t
ns
ns
TXLXH
Serial Port Clock falling edge to rising edge †
SP_BAUD ≥ x002H
SP_BAUD = x001H
4t – 15
2t – 15
4t + 15
2t + 15
ns
ns
TQVXH
Output data setup to clock high (see Note)
ns
SP_BAUD ≥ x002H
SP_BAUD = x001H
4t – 15
2t – 15
4t + 15
2t + 15
TXHQX
TXHQV
TDVXH
Output data hold after clock high
2t – 20
ns
ns
Next output data valid after clock high
2t + 20
Input data setup to clock high (see Note)
ns
SP_BAUD ≥ x002H
SP_BAUD = x001H
2t + 10
t + 10
TXHDX
Input data hold after clock high
Last clock high to output float
0
ns
ns
TXHQZ
2t + 15
†
The minimum baud-rate (SP_BAUD) register value is x002H for receptions and x001H for transmissions.
T
XLXL
TXD
T
T
XHQV
XLXH
T
T
XHQZ
T
XHQX
5
QVXH
RXD
0
T
1
2
7
4
6
3
(Out)
T
DVXH
XHDX
Valid
RXD
(In)
Valid
Valid
Valid
Valid
Valid
Valid
Valid
A2080-02
Figure 12. Serial Port Waveform — Synchronous Mode 0
30
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 14. External Clock Drive
6.2.7 EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
16
8
Max
50†
Units
MHz
MHz
MHz
ns
FXTAL1
External Input Frequency (1/TXLXL), PLL disabled
External Input Frequency (1/TXLXL), PLL in 2x mode
External Input Frequency (1/TXLXL), PLL in 4x mode
Oscillator Period (TXLXL), PLL disabled
Oscillator Period (TXLXL), PLL in 2x mode
Oscillator Period (TXLXL), PLL in 4x mode
High Time
25
8
12.5
62.5
125
125
TXTAL1
20
40
80
ns
ns
TXHXX
TXLXX
TXLXH
0.35TXTAL1 0.65TXTAL1
ns
Low Time
0.35TXTAL1 0.65TXTAL1
ns
Rise Time
10
10
ns
TXHXL
Fall Time
ns
†
Assumes an external clock; the maximum input frequency for an external crystal oscillator is 25 MHz.
TXHXL
TXHXX
TXLXH
0.7 VCC + 0.5 V
0.7 VCC + 0.5 V
0.3 VCC – 0.5 V
TXLXL
TXLXX
0.3 VCC – 0.5 V
XTAL1
A2119-03
Figure 13. External Clock Drive Waveforms
PRELIMINARY
31
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
3.5 V
2.0 V
0.8 V
2.0 V
0.8 V
Test Points
0.45 V
Note:
AC testing inputs are driven at 3.5 V for a logic “ 1” and 0.45 V for a logic
“ 0” . Timing measurements are made at 2.0 V for a logic “ 1” and 0.8 V for
a logic “ 0”.
A2120-04
Figure 14. AC Testing Input and Output Waveforms During 5.0 Volt Testing
VOH – 0.15 V
V
LOAD + 0.15 V
VLOAD
VLOAD – 0.15 V
Timing Reference
Points
V
OL + 0.15 V
Note:
For timing purposes, a port pin is no longer floating when a 150 mV change from load
voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL
level occurs with IOL/IOH ≤15 mA.
A2121-03
Figure 15. Float Waveforms During 5.0 Volt Testing
32
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
7.0 THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will
change depending on operating conditions and the application. The Intel Packaging Handbook (order number
240800) describes Intel’s thermal impedance test methodology. The Components Quality and Reliability
Handbook (order number 210997) provides quality and reliability information.
Table 15. Thermal Characteristics
Package Type
θJA
θJC
100-pin QFP
50°C/W
16°C/W
8.0 80296SA ERRATA
The 80296SA may contain design defects or errors known as errata. Characterized errata that may cause the
80296SA’s behavior to deviate from published specifications are documented in a specification update.
Specification updates can be obtained from your local Intel sales office or from the World Wide Web
(www.intel.com).
9.0 DATASHEET REVISION HISTORY
This datasheet is valid for devices with an “A” at the end of the topside tracking number. Datasheets are
changed as new device information becomes available. Verify with your local Intel sales office that you have
the latest version before finalizing a design or ordering devices.
This is the -003 version of the datasheet. The following changes were made in this version:
1. All references to SQFP package were deleted.
2. Reference to ROM option was removed from Table 1.
3. The speed designation for 40 MHz was changed from “no mark” to “40” in Table 1.
4. The TRXDX specification was changed to 0 ns (from 2 ns) in Table 11 and Table 13.
5. The TCHYX specification was replaced by TCH1YX and TCH2YX
.
6. The READY timing diagrams (Figures 8 and 10) were replaced by examples that reflect the new TCH1YX
and TCH2YX specifications.
This is the -002 version of the datasheet. The following changes were made in this version:
1. The “Intel Confidential” designation was removed for publication.
2. A heading was added for Section 1.0, “Product Overview,” and the remaining sections were renum-
bered.
3. The errata list was replaced with a reference to the specification update document.
The following changes were made in the -001 version of the datasheet:
1. Throughout the datasheet, the product name was changed to read “80296SA” instead of “80C296SA.”
2. The feature list was clarified.
3. A table of contents was added.
4. The block diagram was changed.
5. Several sections were rearranged and section numbers were assigned. “Thermal Characteristics” was
moved to Section 7.0; a section heading was added for “Nomenclature Overview,” Section 2.0; a section
heading was added for “Address Map” and it was moved to Section 5.0; a section heading was added
for “Pinout,” and it was moved to Section 3.0; the section heading “Pin Descriptions” was changed to
“Signals,” Section 4.0. The remaining sections were assigned section numbers: “Electrical Characteris-
PRELIMINARY
33
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
tics” is Section 6.0; “Errata” is Section 8.0, and “Datasheet Revision History” is Section 9.0.
6. Table 2 was changed to Table 1 and the “process information” was corrected to show that “no mark” sig-
nifies a CHMOS process.
7. Table 3 was changed to Table 7 and several clarifications were made.
8. Figure 3 was changed to correct the product name. Pin assignments did not change.
9. Table 4 was changed to Table 2 and pin 3 was changed from “no connection” to “tie to VCC.”
10. Figure 4 was changed to correct the product name. Pin assignments did not change.
11. Figure 5, “ICC versus Frequency in Reset,” was added. Remaining figure numbers were incremented.
12. Table 6 was changed to Table 4 and a note for handling the “no connection” pins was added.
13. Table 8 was changed to Table 6. The descriptions of BREQ#, HLDA#, and HOLD# were changed to
reflect their operation during hold. The description of the ONCE signal was changed to reflect the correct
states of READY, RESET#, and NMI during ONCE mode. The description of PLLEN2:1 was changed to
show the correct pin states to achieve each phase-locked loop (PLL) clock multiplier mode. The descrip-
tions of RPD and RESET# were changed to reflect system requirements when using the PLL.
14. Two notes were added to clarify the “Operating Conditions” in the “Electrical Characteristics” section.
15. Table 9 was changed to Table 8, the notes were re-ordered, and the following specifications were
changed:
•
•
•
I
CC max was changed to 150 mA
(from 120 mA).
OH min was changed to VCC–0.5 V
(from VCC–0.3 V) at IOH = –200µA.
OH min was changed to VCC–0.9 V
V
V
(from VCC–0.7V) at IOH = –3.2 mA.
•
•
•
Test condition for VOL1 max = 0.45 V was changed to IOL = 8 mA (from IOL = 10 mA).
R
RST min and max were changed to 50 kΩ and 150 kΩ (from 9 kΩ and 95 kΩ).
V
OH3 min specification was added.
16. Table 10 was divided into two tables: timing specifications that the microcontroller will meet (Table 10)
and those that the external memory system must meet (Table 11). Note 7 was deleted and the remain-
ing notes were re-ordered. The following specifications were changed or added in Table 10:
•
•
•
•
•
•
•
F
T
T
T
T
T
T
XTAL1 min for the PLL in 4x mode was changed to 8 MHz (from 4 MHz); a clarifying note was added.
XHCH min was changed to 3 ns (from TBD).
LLAX min was changed to 1 ns (from TBD).
LLRL min was changed to 3 ns (from TBD)
RHAX min was changed to t – 4 ns (from t).
AVWL min (2t – 25) was added to Table 10.
SLDV min (4t – 28) was added to Table 11.
17. Table 11 was divided into two tables: timing specifications that the microcontroller will meet (Table 12)
and those that the external memory system must meet (Table 13). Note 7 was deleted and the remain-
ing notes were re-ordered. The following specifications were changed:
•
•
F
T
XTAL1 min for the PLL in 4x mode was changed to 8 MHz (from 4 MHz); a clarifying note was added.
WHQX min was changed to t – 5 ns (from t – 2 ns).
18. Figure 6 was changed to show the correct PLLEN2:1 values to select the 2x clock multiplier mode.
19. Table 13 was changed to Table 15 and a note was added.
20. Table 14 was changed to Table 16, 1/TXLXL specifications for each phase-locked loop (PLL) mode were
added, and Note 2 was deleted.
34
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
PRELIMINARY
35
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
36
PRELIMINARY
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