S80C196MC [INTEL]
8XC196MC INDUSTRIAL MOTOR CONTROL MICROCONTROLLER; 8XC196MC工业电机控制用微控制器
| 型号： | S80C196MC |
| 厂家： | 
INTEL |
| 描述： | 8XC196MC INDUSTRIAL MOTOR CONTROL MICROCONTROLLER |
| 文件： | 总22页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8XC196MC
INDUSTRIAL MOTOR CONTROL
MICROCONTROLLER
87C196MC 16 Kbytes of On-Chip OTPROM*
87C196MC, ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM
80C196MC ROMless
Y
Y
Y
High-Performance CHMOS 16-Bit CPU
Two 16-Bit Timers with Quadrature
Decoder Input
16 Kbytes of On-Chip OTPROM/
Factory-Programmed OTPROM
Y
Y
3-Phase Complementary Waveform
Generator
Y
Y
Y
Y
488 bytes of On-Chip Register RAM
Register to Register Architecture
Up to 53 I/O Lines
13 Channel 8/10-Bit A/D with Sample/
Hold with Zero Offset Adjustment H/W
Y
Y
Y
Y
Y
14 Prioritized Interrupt Sources
Flexible 8-/16-Bit External Bus
1.75 ms 16 x 16 Multiply
Peripheral Transaction Server (PTS)
with 11 Prioritized Sources
Y
Event Processor Array (EPA)
Ð 4 High Speed Capture/Compare
Modules
3 ms 32/16 Divide
Idle and Power Down Modes
Ð 4 High Speed Compare Modules
Y
Extended Temperature Standard
The 8XC196MC is a 16-bit microcontroller designed primarily to control 3 phase AC induction and DC brush-
less motors. The 8XC196MC is based on Intel’s MCS 96 16-bit microcontroller architecture and is manufac-
tured with Intel’s CHMOS process.
É
The 8XC196MC has a three phase waveform generator specifically designed for use in ‘‘Inverter’’ motor
control applications. This peripheral allows for pulse width modulation, three phase sine wave generation with
minimal CPU intervention. It generates 3 complementary non-overlapping PWM pulses with resolutions of
0.125 ms (edge trigger) or 0.250 ms (centered).
The 8XC196MC has 16 Kbytes on-chip OTPROM/ROM and 488 bytes of on-chip RAM. It is available in three
packages; PLCC (84-L), SDIP (64-L) and EIAJ/QFP (80-L).
Note that the 64-L SDIP package does not include P1.4, P2.7, P5.1 and the CLKOUT pins.
b
a
Operational characteristics are guaranteed over the temperature range of 40 C to 85 C.
§
§
The 87C196MC contains 16 Kbytes on-chip OTPROM. The 83C196MC contains 16 Kbytes on-chip ROM. All
references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted.
*OTPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package
and cannot be erased. It is user programmable.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
April 1994
Order Number: 270946-005
8XC196MC
270946–1
NOTE:
Connections between the standard I/O ports and the bus are not shown.
Figure 1. 87C196MC Block Diagram
2
8XC196MC
Address
8XC196MC Memory Map
Description
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS
III-E process. Additional process and reliability infor-
External Memory or I/O
0FFFFH
06000H
®
mation is available in the Intel Quality
System Handbook.
Internal ROM/EPROM or External
Memory (Determined by EA)
5FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
205EH
PTS Vectors
205DH
2040H
Upper Interrupt Vectors
ROM/EPROM Security Key
203FH
2030H
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201CH
270946–16
EXAMPLE: N87C196MC is 84-Lead PLCC OTPROM,
16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
Reserved. Must Contain 20H
(Note 5)
201BH
CCB1
201AH
2019H
Reserved. Must Contain 20H
(Note 5)
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
CCB0
2018H
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Figure 3. The 8XC196MC Family Nomenclature
Thermal Characteristics
Package
Lower Interrupt Vectors
2013H
2000H
i
i
jc
ja
Type
PLCC
QFP
SFR’s
1FFFH
1F00H
35 C/W
§
13 C/W
§
56 C/W
12 C/W
External Memory
1EFFH
0200H
§
TBD
§
TBD
SDIP
488 Bytes Register RAM (Note 1)
CPU SFR’s (Notes 1, 3)
01FFH
0018H
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology.
0017H
0000H
NOTES:
1. Code executed in locations 0000H to 03FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KC for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
8XC196MC
270946–2
NOTE:
*The pin sequence is correct.
The 64-Lead SDIP package does not include the following pins: P1.4/ACH12, P2.7/COMPARE3, P5.1/INST,
CLKOUT.
Figure 2. 64-Lead Shrink DIP (SDIP) Package
4
8XC196MC
270946–3
NOTE:
NC means No Connect. Do not connect these pins.
Figure 3. 84-Lead PLCC Package
5
8XC196MC
270946–4
NOTE:
NC means No Connect. Do not connect these pins.
Figure 4. 80-Lead Shrink EIAJQFP (Quad Flat Pack)
6
8XC196MC
PIN DESCRIPTIONS (Alphabetically Ordered)
Symbol
Function
ACH0–ACH12
(P0.0–P0.7, P1.0–P1.4)
Analog inputs to the on-chip A/D converter. ACH0–7 share the input pins
with P0.0–7 and ACH8–12 share pins with P1.0–4. If the A/D is not used,
the port pins can be used as standard input ports.
ANGND
Reference ground for the A/D converter. Must be held at nominally the
.
same potential as V
SS
ALE/ADV(P5.0)
Address Latch Enable or Address Valid output, as selected by CCR. Both
options allow a latch to demultiplex the address/data bus on the signal’s
falling edge. When the pin is ADV, it goes inactive (high) at the end of the
bus cycle. ALE/ADV is active only during external memory accesses. Can be
used as standard I/O when not used as ALE/ADV.
BHE/WRH (P5.5)
BUSWIDTH (P5.7)
Byte High Enable or Write High output, as selected by the CCR. BHE will go
low for external writes to the high byte of the data bus. WRH will go low for
external writes where an odd byte is being written. BHE/WRH is activated
only during external memory writes.
e
Input for bus width selection. If CCR bits 1 and 2
1, this pin dynamically
controls the bus width of the bus cycle in progress. If BUSWIDTH is low, an
8-bit cycle occurs. If it is high, a 16-bit cycle occurs. This pin can be used as
standard I/O when not used as BUSWIDTH.
CAPCOMP0–CAPCOMP3
(P2.0–P2.3)
The EPA Capture/Compare pins. These pins share P2.0–P2.3. If not used
for the EPA, they can be configured as standard I/O pins.
CLKOUT
Output of the internal clock generator. The frequency is (/2 of the oscillator
frequency. It has a 50% duty cycle.
COMPARE0–COMPARE3
(P2.4–P2.7)
The EPA Compare pins. These pins share P2.4–P2.7. If not used for the
EPA, they can be configured as standard I/O pins.
e
EA
External Access enable pin. EA
e
0 causes all memory accesses to be
external to the chip. EA
to 5FFFH to be from the on-chip OTPROM/QROM. EA
1 causes memory accesses from location 2000H
e
execution to begin in the programming mode. EA is latched at reset.
12.5V causes
EXTINT
INST (P5.1)
NMI
A programmable input on this pin causes a maskable interrupt vector
through memory location 203CH. The input may be selected to be a
positive/negative edge or a high/low level using WG PROTECT (1FCEH).
Ð
INST is high during the instruction fetch from the external memory and
throughout the bus cycle. It is low otherwise. This pin can be configured as
standard I/O if not used as INST.
A positive transition on this pin causes a non-maskable interrupt which
vectors to memory location 203EH. If not used, it should be tied to V . May
be used by Intel Evaluation boards.
SS
PORT0
PORT1
PORT2
8-bit high impedance input-only port. Also used as A/D converter inputs.
Port0 pins should not be left floating. These pins also used to select
programming modes in the OTPROM devices.
5-bit high impedance input-only port. P1.0–P1.4 are also used as A/D
converter inputs. In addition, P1.2 and P1.3 can be used as Timer 1 clock
input and direction select respectively.
8-bit bidirectional I/O port. All of the Port2 pins are shared with the EPA I/O
pins (CAPCOMP0–3 and COMPARE0–3).
PORT3
PORT4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared
with the multiplexed address/data bus which uses strong internal pullups.
PORT5
8-bit bidirectional I/O port. 7 of the pins are shared with bus control signals
(ALE, INST, WR, RD, BHE, READY, BUSWIDTH). Can be used as standard
I/O.
7
8XC196MC
PIN DESCRIPTIONS (Alphabetically Ordered) (Continued)
Symbol
Function
PORT6
8-bit output port. P6.6 and P6.7 output PWM, the others are used as the Wave
Form Generator outputs. Can be used as standard output ports.
PWM0, PWM1
(P6.6, P6.7)
Programmable duty cycle, Programmable frequency Pulse Width Modulator
pins. The duty cycle has a resolution of 256 steps, and the frequency can vary
from 122 Hz to 31 KHz (16 MHz input clock). Pins may be configured as
standard output if PWM is not used.
RD (P5.3)
Read signal output to external memory. RD is low only during external memory
reads. Can be used as standard I/O when not used as RD.
e
0, the memory
READY (P5.6)
Ready input to lengthen external memory cycles. If READY
controller inserts wait states until the next positive transition of CLKOUT
e
occurs with READY
READY.
1. Can be used as standard I/O when not used as
RESET
Reset input to and open-drain output from the chip. Held low for at least 16
state times to reset the chip. Input high for normal operation. RESET has an
Ohmic internal pullup resistor.
T1CLK
(P1.2)
Timer 0 Clock input. This pin has two other alternate functions: ACH10 and
P1.2.
T1DIR
(P1.3)
Timer 0 Direction input. This pin has two other alternate functions: ACH11 and
P1.3.
V
The programming voltage is applied to this pin. It is also the timing pin for the
return from Power Down circuit. Connect this pin with a 1 mF capacitor to V
PP
SS
and a 1 MX resistor to V . If the Power Down feature is not used, connect
CC
the pin to V
.
CC
WG1–WG3/WG1–WG3
(P6.0–P6.5)
3 phase output signals and their complements used in motor control
applications. The pins can also be configured as standard output pins.
WR/WRL (P5.2)
Write and Write Low output to external memory. WR will go low every external
write. WRL will go low only for external writes to an even byte. Can be used as
standard I/O when not used as WR/WRL.
XTAL1
XTAL2
Input of the oscillator inverter and the internal clock generator. This pin should
be used when using an external clock source.
Output of the oscillator inverter.
PMODE
(P0.4–7)
Determines the EPROM programming mode.
PACT
(P2.5)
A low signal in Auto Programming mode indicates that programming is in
process. A high signal indicates programming is complete.
PALE
(P2.1)
A falling edge in Slave Programming Mode and Auto Configuration Byte
Programming Mode indicates that ports 3 and 4 contain valid programming
address/command information (input to slave).
PROG
(P2.2)
A falling edge in Slave Programming Mode begins programming. A rising edge
ends programming.
PVER
(P2.0)
A high signal in Slave Programming Mode and Auto Configuration Byte
Programming Mode indicates the byte programmed correctly.
CPVER
(P2.6)
Cumulative Program Verification. Pin is high if all locations since entering a
programming mode have programmed correctly.
AINC
(P2.4)
Auto Increment. Active low input enables the auto increment mode. Auto
increment will allow reading or writing of sequential EPROM locations without
address transactions across the PBUS for each read or write.
8
8XC196MC
ABSOLUTE MAXIMUM RATINGS
NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
tions are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
Ambient Temperature
Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 C to 85 C
b
a
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
§
§
b
a
§
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Voltage from EA or V
PP
to V or ANGNDÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13.00V
a
SS
Voltage on V or EQ
PP
to V or ANGND ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 13.0V
SS
b
Voltage on Any Other Pin
(1)
b
a
to V or ANGND ÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 7.0V
SS
(2)
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
NOTES:
1. This includes V and EA on ROM or CPU only devices.
PP
2. Power dissipation is based on package heat transfer lim-
itations, not device power consumption.
OPERATING CONDITIONS
Symbol
Description
Ambient Temperature Under Bias
Digital Supply Voltage
Min
Max
Units
b
a
85
T
A
40
C
§
V
CC
4.50
4.00
8
5.50
5.50
16
V
V
Analog Supply Voltage
Oscillator Frequency
V
REF
OSC
F
MHz
NOTE:
ANGND and V should be nominally at the same potential. Also V and V
must be at the same potential.
SS1
S
S
S
S
DC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions)
Symbol
Parameter
Input Low Voltage
Min
Max
0.3 V
Units
Test Conditions
b
V
V
V
0.5
V
V
IL
CC
a
0.5
Input High Voltage
0.7 V
V
CC
IH
OL
CC
e
e
e
Output Low Voltage
Port 2 and 5, P6.6, P6.7,
CLKOUT
0.3
0.45
1.5
V
V
V
I
I
I
200 mA
3.2 mA
7 mA
OL
OL
OL
e
e
V
V
Output Low Voltage on Port 3/4
1.0
V
V
I
I
15 mA
10 mA
OL1
OL2
OL
OL
Output Low Voltage on
Port 6.0–6.5
0.45
b
b
b
e b
e b
e b
V
V
Output High Voltage
V
V
V
0.3
0.7
1.5
V
V
V
I
I
I
200 mA
3.2 mA
7 mA
OH
CC
CC
CC
OH
OH
OH
–V
Hysteresis Voltage Width on
RESET
0.2
V
Typical
a
b
th
th
9
8XC196MC
DC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
Symbol
Parameter
Min Typ Max Units
Test Conditions
k
k
k
g
I
I
I
I
I
Input Leakage Current on All Input
Only Pins
10 mA 0V
V
V
V
–0.3V (in RESET)
CC
LI
IN
k
g
Input Leakage Current on Port0
and Port1
3
mA 0V
V
LI1
IL
IN
REF
b
e
0.3 V
Input Low Current on BD Ports
(Note 1)
70 mA
V
IN
CC
b
Input Low Current on P5.4 and
P2.6 during Reset
7
mA 0.2 V
mA 0.7 V
IL1
OH
CC
b
Output High Current on P5.4 and
P2.6 during Reset
2
CC
e
I
I
I
I
Active Mode Current in Reset
A/D Conversion Reference Current
Idle Mode Current
50
2
70
5
mA XTAL1
16 MHz,
e
CC
e
e
e
V
V
PP
V
5.5V
5.5V
CC
CC
REF
mA
mA
mA
X
REF
IDL
PD
15
5
30
50
65k
10
e
e
Power-Down Mode Current
RESET Pin Pullup Resistor
V
V
PP
V
REF
R
6k
RST
S
e
C
Pin Capacitance (Any Pin to V
)
SS
pF
F
1.0 MHz
TEST
NOTES:
1. BD (Bidirectional ports) include:
P2.0–P2.7, except P2.6
P3.0–P3.7
P4.0–P4.7
P5.0–P5.3
P5.5–P5.7
2. During normal (non-transient) conditions, the following total current limits apply:
P6.0–P6.5
P3
P4
P5, CLKOUT
P2, P6.6, P6.7
I
I
I
I
I
: 40 mA
: 90 mA
: 90 mA
: 35 mA
: 63 mA
I : 28 mA
OH
I : 42 mA
OH
I : 42 mA
OH
I : 35 mA
OH
I : 63 mA
OH
OL
OL
OL
OL
OL
10
8XC196MC
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H
L
Ð High
A
B
C
D
G
H
Ð Address
L
Ð ALE/ADV
Ð Low
Ð BHE
BR Ð BREQ
V
X
Z
Ð Valid
Ð CLKOUT
Ð DATA
R
W
X
Ð RD
Ð No Longer Valid
Ð Floating
Ð WR/WRH/WRL
Ð XTAL1
Ð Buswidth
Ð HOLD
Y
Ð READY
Ð Data Out
HA Ð HLDA
Q
AC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions)
e
e
e
16 MHz.
OSC
Test Conditions: Capacitive load on all pins
100 pF, Rise and fall times
10 ns, F
The system must meet the following specifications to work with the 87C196MC:
Symbol
Parameter
Min
8
Max
16
Units
MHz
ns
Notes
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Frequency on XTAL1
3
XTAL
OSC
1/F
62.5
125
XTAL
b
OSC
Address Valid to READY Setup
ALE Low to READY Setup
2 T
75
ns
AVYV
LLYV
YLYH
CLYX
LLYX
AVGV
LLGV
CLGX
AVDV
RLDV
CLDV
RHDZ
RXDX
b
T
70
ns
4
OSC
Not READY Time
No Upper Limit
ns
b
READY Hold after CLKOUT Low
READY Hold after ALE Low
Address Valid to BUSWIDTH Setup
ALE Low to BUSWIDTH Setup
Buswidth Hold after CLKOUT Low
Address Valid to Input Data Valid
RD Active to Input Data Valid
CLKOUT Low to Input Data Valid
End of RD to Input Data Float
Data Hold after RD Inactive
0
T
30
ns
1
1
OSC
b
b
T
15
2 T
2 T
40
75
ns
OSC
OSC
OSC
b
ns
b
T
60
ns
4
OSC
0
ns
b
3 T
55
ns
2
2
OSC
b
T
T
22
ns
OSC
OSC
b
50
ns
T
ns
OSC
0
ns
NOTES:
1. If Max is exceeded, additional wait states will occur.
e
3. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. If wait states are used, add 2 T
* N, where N
number of wait states.
OSC
b
4. These timings are included for compatibility with older 90 and BH products. They should not be used for newer high-
speed designs.
11
8XC196MC
AC ELECTRICAL CHARACTERISTICS (Continued)
e
e
e
16 MHz.
OSC
Test Conditions: Capacitive load on all pins
100 pF, Rise and fall times
10 ns, F
The 87C196MC will meet the following timing specifications:
Symbol
Parameter
Min
Max
110
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
XTAL1 to CLKOUT High or Low
CLKOUT Cycle Time
30
XHCH
CLCL
CHCL
CLLH
LLCH
LHLH
LHLL
2 T
OSC
T
b
a
OSC
CLKOUT High Period
T
10
15
10
OSC
b
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
5
15
15
b
20
4 T
3
OSC
T
b
b
b
b
a
OSC
ALE High Period
T
T
T
T
10
OSC
OSC
OSC
OSC
Address Setup to ALE Falling Edge
Address Hold after ALE Falling
ALE Falling Edge to RD Falling
RD Low to CLKOUT Falling Edge
RD Low Period
15
40
30
AVLL
LLAX
LLRL
4
30
RLCL
RLRH
RHLH
RLAZ
LLWL
CLWL
QVWH
CHWH
WLWH
WHQX
WHLH
WHBX
WHAX
RHBX
RHAX
b
a
T
5
T
T
25
25
3
1
OSC
OSC
OSC
a
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
T
OSC
5
b
ALE Falling Edge to WR Falling
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
T
T
10
23
OSC
0
25
15
b
OSC
b
10
b
b
b
b
b
b
b
T
T
T
T
T
T
T
30
25
10
10
30
10
30
3
1
2
2
OSC
OSC
OSC
OSC
OSC
OSC
OSC
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE, INST Hold after WR Rising
AD8–15 Hold after WR Rising
BHE, INST Hold after RD Rising
AD8–15 Hold after RD Rising
a
T
15
OSC
NOTES:
1. Assuming back to back cycles.
2. 8-bit bus only.
3. If wait states are used, add 2 T
e
number of wait states.
*N, where N
OSC
12
8XC196MC
SYSTEM BUS TIMINGS
270946–5
13
8XC196MC
READY TIMINGS (One Wait State)
270946–6
BUSWIDTH TIMINGS
270946–7
14
8XC196MC
EXTERNAL CLOCK DRIVE
Symbol
1/T
Parameter
Min
8
Max
16.0
125
Units
MHz
ns
Oscillator Frequency
Oscillator Period
High Time
XLXL
T
T
T
T
T
62.5
22
XLXL
ns
XHXX
XLXX
XLXH
XHXL
Low Time
22
ns
Rise Time
10
10
ns
Fall Time
ns
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
270946–14
270946–15
* Required if TTL driver used.
Not needed if CMOS driver is used.
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and V . When
SS
e
e
20 pF. When using
using crystals, C1
20 pF, C2
ceramic resonators, consult manufacturer for recom-
mended circuitry.
EXTERNAL CLOCK DRIVE WAVEFORMS
270946–8
An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the V and
IL
V
IH
specifications the capacitance will not exceed 20 pF.
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270946–9
AC Testing inputs are driven at 3.5V for a Logic ‘‘1’’ and 0.45V for
a Logic ‘‘0’’. Timing measurements are made at 2.0V for a Logic
‘‘1’’ and 0.8V for a Logic ‘‘0’’.
270946–10
For Timing Purposes a Port Pin is no Longer Floating when a
100 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded V /V Level occurs
OH OL
s
e
g
15 mA.
I
/I
OL OH
15
8XC196MC
e
T
F
B
B
Conversion time, ms
CONV
A TO D CHARACTERISTICS
e
Processor frequency, MHz
8 for 8-bit conversion
10 for 10-bit conversion
e
bits 0–5
OSC
e
e
The sample and conversion time of the A/D convert-
er in the 8-bit or 10-bit modes is programmed by
loading a byte into the AD TIME Special Function
CONV
Value loaded into AD TIME
Ð
Ð
Register. This allows optimizing the A/D operation
for specific applications. The AD TIME register is
Ð
functional for all possible values, but the accuracy of
the A/D converter is only guaranteed for the times
specificed in the operating conditions table.
CONV must be in the range 2 through 31.
The converter is ratiometric, so absolute accuracy is
dependent on the accuracy and stability of V
.
REF
must be close to V since it supplies both the
The value loaded into AD TIME bits 5, 6, 7 deter-
Ð
V
REF CC
mines the sample time, T
ing the following formula:
, and is calculated us-
resistor ladder and the analog portion of the convert-
er and input port pins. There is also an AD TEST
SAM
Ð
SFR that allows for conversion on ANGND and
c
b
2
(T
SAM
F
8
)
V as well as adjusting the zero offset. The abso-
REF
lute error listed is WITHOUT doing any adjustments.
OSC
e
SAM
A/D CONVERTER SPECIFICATION
e
e
T
F
SAM
Sample time, ms
Processor frequency, MHz
Value loaded into AD TIME
SAM
OSC
The specifications given assume adherence to the
operating conditions section of this data sheet. Test-
e
Ð
bits 5, 6, 7
e
ing is performed with V
5.12V and 16.0 MHz
REF
operating frequency. After a conversion is started,
the device is placed in the IDLE mode until the con-
version is complete.
SAM must be in the range 1 through 7.
The value loaded into AD TIME bits 0–5 deter-
Ð
mines the conversion time, T
using the following formula:
, and is calculated
CONV
c
b
3
(T
F
)
OSC
CONV
e
b
1
CONV
2B
16
8XC196MC
Units
10-BIT MODE A/D OPERATING CONDITIONS
Symbol
Description
Ambient Temperature
Digital Supply Voltage
Analog Supply Voltage
Sample Time
Min
Max
b
a
85
T
A
40
C
§
V
V
4.50
4.00
1.0
5.50
5.50
V
CC
(1)
V
REF
SAM
CONV
OSC
(2)
ms
T
T
F
(2)
ms
Conversion Time
10.0
8.0
20.0
16.0
Oscillator Frequency
MHz
NOTES:
ANGND and V should nominally be at the same potential.
SS
must be within 0.5V of V
1. V
.
CC
REF
2. The value of AD TIME is selected to meet these specifications.
Ð
10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
(1)
Parameter
Resolution
Typical
Min
Max
Units*
1024
10
1024
10
Levels
Bits
g
Absolute Error
0
4
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
g
0.25 0.5
Full Scale Error
g
0.25 0.5
Zero Offset Error
Non-Linearity
g
1.0 2.0
g
a
4
2
l
b
0
Differential Non-Linearity
Channel-to-Channel Matching
Repeatability
1
g
g
0.1
1.0
g
0.25
0
Temperature Coefficients:
Offset
Full Scale
0.009
0.009
0.009
LSB/C
LSB/C
LSB/C
Differential Non-Linearity
(2, 3)
dB
b
Off Isolation
Feedthrough
60
(2)
dB
b
b
60
60
(2)
dB
V
Power Supply Rejection
CC
(4)
Input Series Resistance
Voltage on Analog Input Pin
Sampling Capacitor
750
2K
X
(5, 6)
V
b
a
ANGND
0.5
V
0.5
REF
3
pF
g
g
DC Input Leakage
1
0
3.0
mA
NOTES:
*An ‘‘LSB’’, as used here has a value of approximately 5 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25 C but are not tested or guaranteed.
2. DC to 100 KHz.
§
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
g
5. These values may be exceeded if the pin current is limited to 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
7. All conversions performed with processor in IDLE mode.
17
8XC196MC
8-BIT MODE A/D OPERATING CONDITIONS
Symbol
Description
Ambient Temperature
Digital Supply Voltage
Analog Supply Voltage
Sample Time
Min
Max
Units
b
a
85
T
A
40
C
§
V
V
4.50
4.00
1.0
5.50
5.50
V
CC
(1)
V
REF
SAM
CONV
OSC
(2)
ms
T
T
F
(2)
ms
Conversion Time
7.0
20.0
16.0
Oscillator Frequency
8.0
MHz
NOTES:
ANGND and V should nominally be at the same potential.
SS
must be within 0.5V of V
1. V
.
CC
REF
2. The value of AD TIME is selected to meet these specifications.
Ð
8-BIT MODE A/D CHARACTERISTICS (Over the Above Operating Conditions)
(1)
Parameter
Resolution
Typical
Min
Max
Units*
256
8
256
8
Level
Bits
g
Absolute Error
0
1
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
g
g
Full Scale Error
0.5
0.5
Zero Offset Error
Non-Linearity
g
a
0
1
1
l
b
Differential Non-Linearity
Channel-to-Channel Matching
Repeatability
1
g
0
1.0
g
0.25
Temperature Coefficients:
Offset
Full Scale
0.003
0.003
0.003
LSB/C
LSB/C
LSB/C
Differential Non-Linearity
(2, 3)
dB
b
Off Isolation
Feedthrough
60
(2)
dB
b
b
60
60
(2)
dB
V
CC
Power Supply Rejection
(4)
Input Series Resistance
Voltage on Analog Input Pin
Sampling Capacitor
750
2K
X
(5, 6)
V
b
a
V
0.5
V
0.5
SS
REF
3
pF
g
g
DC Input Leakage
1
0
3.0
mA
NOTES:
*An ‘‘LSB’’ as used here, has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25 C but are not tested or guaranteed.
2. DC to 100 KHz.
§
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
g
5. These values may be exceeded if the pin current is limited to 2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
7. All conversions performed with processor in IDLE mode.
18
8XC196MC
EPROM SPECIFICATIONS
OPERATING CONDITIONS
Symbol
Description
Min
20
Max
30
Units
T
Ambient Temperature during Programming
Supply Voltage during Programming
Reference Supply Voltage during Programming
Programming Voltage
C
§
A
(1)
V
V
V
V
4.5
5.5
V
CC
(1)
V
4.5
5.5
REF
PP
(2)
V
12.25
12.25
6.0
12.75
12.75
8.0
(2)
V
EA Pin Voltage
EA
F
Oscillator Frequency during Auto
and Slave Mode Programming
MHz
OSC
T
Oscillator Frequency during
Run-Time Programming
6.0
12.0
MHz
OSC
NOTES:
1. V and V
2. V and V must never exceed the maximum specification, or the device may be damaged.
should nominally be at the same voltage during programming.
REF
CC
PP EA
3. V and ANGND should nominally be at the same potential (0V).
SS
e
4. Load capacitance during Auto and Slave Mode programming
150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Parameter
Reset High to First PALE Low
PALE Pulse Width
Min
1100
50
Max
Units
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
SHLL
LLLH
AVLL
LLAX
PLDV
PHDX
DVPL
PLDX
Address Setup Time
0
Address Hold Time
100
PROG Low to Word Dump Valid
Word Dump Data Hold
Data Setup Time
50
50
0
Data Hold Time
400
50
(1)
PROG Pulse Width
PLPH
PHLL
LHPL
PHPL
PHIL
ILIH
PROG High to Next PALE Low
PALE High to PROG Low
PROG High to Next PROG Low
PROG High to AINC Low
AINC Pulse Width
220
220
220
0
240
50
PVER Hold after AINC Low
AINC Low to PROG Low
PROG High to PVER Valid
ILVH
ILPL
170
220
PHVL
NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.
19
8XC196MC
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
I
V
Supply Current (When Programming)
PP
100
mA
PP
NOTE:
Do not apply V until V
PP
damaged.
is stable and within specifications and the oscillator/clock has stabilized or the device may be
CC
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
2709461–11
NOTE:
P3.0 must be high (‘‘1’’)
20
8XC196MC
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
270946–12
NOTE:
P3.0 must be low (‘‘0’’)
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM
WITH REPEATED PROG PULSE AND AUTO INCREMENT
270946–13
21
8XC196MC
3. EXTINT function description now includes
WG PROTECT (1FCEH) as the name and ad-
87C196MC DESIGN
CONSIDERATIONS
Ð
dress of the register used to select positive/neg-
ative or high/low detection for EXTINT.
When an indirect shift during divide occurs the upper
3 bits of the shift count are not masked completely.
If the shift count register has the value 32 n where n
e
1, 3, 5 or 7, the operand will be shifted 32 times.
This should have resulted in no shift taking place.
4. The memory range 01F00H–01FBFH was added
to the SFR map as RESERVED.
*
b
b
5. I changed from 60 mA to 70 mA.
IL
6. I
changed from 5 mA to 2 mA maximum and
the typical specification was removed.
REF
7. The READY description of the READY TIMINGS
(One Wait State) graphic was modified to denote
the shifting of the leading edge of READY versus
frequency. At 16 MHz the falling edge of READY
occurs before the falling edge of ALE.
DATA SHEET REVISION HISTORY
This data sheet (270946-004) is valid for devices
with a ‘‘B’’ at the end of the topside tracking number.
Data sheets are changed as new device information
becomes available. Verify with your local Intel sales
office that you have the latest version before finaliz-
ing a design or ordering devices.
8. AC Testing Input, Output Waveform was
changed to reflect inputs driven at 3.5V for a
Logic ‘‘1’’ and .45V for a Logic ‘‘0’’ and timing
measurements made at 2.0V for a Logic ‘‘1’’
and 0.8V for a Logic ‘‘0’’.
The following important differences exist between
this data sheet (270946-002) and the previous ver-
sion (270946-003):
e
9. Float Waveform was changed from I /I
s
OL OH
g
g
15 mA
15 mA to I /I
OL OH
1. The data sheet was reorganized to standard for-
mat.
10. AD TIME register for 10-bit conversions was
Ð
changed from 0C7H to 0D8H. The number of
sample time states was changed from 24 to 25
states, the conversion time states was changed
from 80 to 240 states, and the total conversion
2. Added 83C196MC device.
3. Added package thermal characteristics.
4. Added note on missing pins on SDIP package.
5. Removed SFR maps (now in user’s manual).
e
conversion time for AD TIME
time for AD TIME
Ð
D8H replaced the total
e
C7H.
Ð
11. The number of sample time states for an 8-bit
conversion was changed from 20 states to 21
states.
6. Added note on T
and T
specifications.
LLGV
LLYV
7. Changed 10-bit mode T
from 15.0 ms.
(MIN) to 10.0 ms
CONV
12. There is a single entry in the ERRATA section of
this version of the data sheet concerning the
results of an indirect shift during divide.
8. Changed 10-bit mode T
from 18.0 ms.
(MAX) to 20.0 ms
CONV
9. Changed VREF (MIN) in 8- and 10-bit mode to
4.0V from 4.5V.
The following important differences exist between
this data sheet (270946-002) and the previous ver-
sion (270946-001):
The following important differences exist between
data sheet 270946-003 and the previous version
(270946-002):
1. T
Ambient Temperature Under Bias Min
b
A
changed from 20 C to 40 C.
b
§
§
A/D Conversion Reference Current Max
1. The data sheet title was changed to better reflect
the purpose of the 87C196MC as an AC Inverter/
DC Brushless Motor Control Microcontroller.
2. I
REF
changed from 5 mA to 2 mA.
3. Testing levels changed from TTL values to
CMOS values.
2. The standard temperature range for this part now
b
a
covers 40 C to 85 C.
§
§
4. A/D Input Series Resistance Max changed from
1.2 KX to 2 KX.
22
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