SXT6282 [INTEL]
PCM Transceiver, 8-Func, PQFP144, LQFP-144;
| 型号： | SXT6282 |
| 厂家： | 
INTEL |
| 描述： | PCM Transceiver, 8-Func, PQFP144, LQFP-144 PC 电信 电信集成电路 |
| 文件： | 总56页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
SEPTEMBER, 1998
Revision 1.1
SXT6282
Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/Wander
Suppression
General Description
Features
SXT6282 is an eight-channel E1 digital interface. It inte-
grates an E1 dejitter phase locked loop, an E1 retiming
function and a CRC-4 monitor function for each E1 trans-
mitter and a CRC-4 monitoring function for each E1
receiver. It is optimized for SDH applications and can used
in conjunction with the SXT6251 (21 E1 mapper).
• Octal E1 transceiver digital interface
• Performs the jitter attenuation function on a gapped
clock supplied by a PDH or SDH multiplexer
• Performs CRC4 performance monitoring on both
transmit and receive sides
• Provides a retiming function on the transmit side for
SDH applications (demapped E1 tributaries)
Applications
• Built-in HDB3 encoder/decoder
• Compatible with SXT6251 for STM-0/1 applications
• SDH 21 or 63 E1 multiplexer
• STM-0 and STM1 SDH add/drop multiplexer
• PDH NxE1 multiplexer
• DCS
• Compatible with LXT334 and the Next Generation
octal LIU
• Microprocessor programmable
• Low power, 3.3 Volt operation, 5 V tolerant i/o
• IEEE 1149.1 (JTAG) compliant
• Microwave radio
• LQFP - 144 surface mount packaging
• Satellite
• Compatible with ITU G.703, G.704, G.706, G.707,
G.775 (Draft 1996), G.783 and G.742
• Test equipment
• Protection Switch
•Industrial temperature operating range -40°C to +85°C.
SXT6282
Block Diagram
Retiming 2 MHz
Clock
High Speed Reference Clock
SXT6282
CLOCK
REFERENCES
E1 TRANSMITTER #0
E1 TRANSMITTER #1
E1 TRANSMITTER #2
E1 TRANSMITTER #3
E1 TRANSMITTER #4
E1 TRANSMITTER #5
E1 TRANSMITTER #6
DEMUX
up to 8 x E1 Tributaries (Tx)
up to 8 x E1 Tributaries
E1
E1 TRANSMITTER #7
& Monitoring
SDH/PDH
MULDEX
up to
8 x
E1
L
I
U
(s)
(
SXT6051
& 6251
or
G703
E1 RECEIVER #0
& Monitoring
SXT6234)
E1 RECEIVER #1
E1 RECEIVER #2
up to 8 x E1 Tributaries
MUX
up to 8 x E1 Tributaries (Rx)
E1 RECEIVER #3
E1 RECEIVER #4
E1 RECEIVER #5
E1 RECEIVER #6
E1 RECEIVER #7
Test Pattern Generator
JTAG
SCAN
RESET&OEN 3Z
Microprocessor Parallel Interface
MICRO
INTERFACE
JTAG
Interrupt
ꢀ
SXT6282
CONTENTS
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS ....................................................................................6
GENERAL FUNCTIONAL DESCRIPTION....................................................................................................12
INTRODUCTION...............................................................................................................................12
TRANSMITTER DESCRIPTION.......................................................................................................12
RECEIVE DATA FLOW DESCRIPTION............................................................................................13
FUNCTIONAL DESCRIPTION PER E1 CHANNEL......................................................................................14
TRANSMITTER DEFAULT OPERATION ..........................................................................................14
Data Input Interface ....................................................................................................................14
Frame Alignment ........................................................................................................................14
CRC-4 Multiframe Alignment......................................................................................................14
AIS Detection..............................................................................................................................16
CRC-4 Multiframe Monitoring.....................................................................................................16
Retiming Elastic Store Operation ...............................................................................................16
De-jittering Circuitry....................................................................................................................18
AIS Signal Insertion....................................................................................................................18
Line Coding HDB3......................................................................................................................18
Line decoding HDB3...................................................................................................................19
AIS Detection..............................................................................................................................19
AIS Insert/LOS Alarm filtering ....................................................................................................19
Frame Alignment/Out Of Frame Alarm .......................................................................................19
CRC-4 Multiframe Alignment/Out of CRC Multiframe Alarm......................................................20
CRC-4 Multiframe Monitoring.....................................................................................................20
Test Pattern Generator for Autotesting/Maintenance..................................................................20
MICROCONTROLLER INTERFACE.................................................................................................20
Intel Interface ..............................................................................................................................20
Motorola Interface.......................................................................................................................21
IINTERRUPT HANDLING.................................................................................................................21
Interrupt Sources........................................................................................................................21
Interrupt Enables ........................................................................................................................21
Interrupt Clearing........................................................................................................................21
Status Registers Access.............................................................................................................22
Counter Reading ........................................................................................................................22
MICROPROCESSOR REGISTER DESCRIPTION.................................................................................23
GLOBAL REGISTERS......................................................................................................................24
GLOB_CONF0 - Global Operational Configuration 0 (0FH).......................................................25
BUFF_ALLCNT - Buffer All Counters (5FH)...............................................................................28
E1_RCV_AISTAT - E1 Receivers AIS Status (8FH) ...................................................................28
EI_XMT_AISTAT - E1 Transmitters AIS Status (9FH).................................................................28
TRANSMIT SIDE REGISTERS.........................................................................................................30
XMT_ALM_STAT - Transmitter Alarm Status (i3H).....................................................................33
XMT_ALM_INTE0 - Transmitter Alarm Interrupt Enable 0 (i4H).................................................33
2 of 56
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Contents
XMT_RMT_ERC - Transmitter Remote CRC-4 Block Errors Counter (iB - iAH)........................ 35
XMT_RTMBUF_STAT - Transmitter Retiming Buffer Status (iDH) ............................................. 36
RECEIVE SIDE REGISTERS........................................................................................................... 36
RCV_CONF- Receiver Configuration (jEH)................................................................................ 37
RCV_ALRM_INT0 - Receiver Alarm Interrupt 0 (j1H)................................................................ 38
RCV_ALRM_INT1 - Receiver Alarm Interrupt 1 (j2H)................................................................ 38
RCV_BLCK_ERC - Receiver CRC-4 Block Error Counter (j9 - j8H).......................................... 40
RCV_RMT_BLCK_ERC - Receiver Remote CRC-4 Block Error Counter (jB - jAH).................. 41
RCV_CD_ERC - Receiver Code Errors Counter (jDH).............................................................. 41
TEST SPECIFICATIONS............................................................................................................................... 42
TESTABILITY................................................................................................................................................ 48
IEEE 1149.1 BOUNDARY SCAN DESCRIPTION .................................................................................. 48
INSTRUCTION REGISTER AND DEFINITIONS ............................................................................. 49
EXTEST (‘b00)........................................................................................................................... 49
SAMPLE/PRELOAD (‘b01) ........................................................................................................ 49
BYPASS (‘b11)........................................................................................................................... 49
IDCODE (‘b10)........................................................................................................................... 49
BOUNDARY SCAN REGISTER ....................................................................................................... 49
GLOSSARY................................................................................................................................................... 54
PACKAGE INFORMATION ........................................................................................................................... 55
3 of 56
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SXT6282
Figure 1: SXT6282 Block Diagram
DRETCKREF
(external 2.048 MHz Retiming Clock)
E1( #i) TRANSMITTER
DTC(i)
7
Filtered
Clock
(2 M)
(
High speed 65.536 MHz ADPLL reference Clock)
DPLLCKREF
Jitter Attenuator
Phase
error
Config.
Retiming/
(second order ADPLL
)
Pass Through/
Dejitter/
2Hz loop bandwidth
Dejitter Fifo
DATA (Dejitter Mode)
E1DATA (Pass Through Mode)
TCLK(i)
(Transmit Clock)
DTC(i)
DTC(i)
DATAIN
[7..0]
(gapped Clock)
TPOSD(i)
(HDB3pos /NRZ data)
Retiming
Elastic Buffer
DATAOUT[7..0]
(Retiming Mode)
Frame
MultiFrame
Recovery
&
S
2
P
P
2
S
AIS
Insert
HDB3
Encoder
E1 DATA
DTD(i)
(Data)
Read
Enable
TNEGD(i)
(HDB3neg data)
TCLK(i)
Write
Write
Read
Addresses
(5..0)
Adresses
(5..0)
AIS
Detect
Enable
Config.
Dejitter/
Line CodeSelect
Insert Code Errors
Ais Force
En
Retiming elastic store Write
Control Logic
(Transmitter Timing gen.)
Retiming elastic store
Read Control Logic
CRC4
Pass THrough/
Retiming/
DTC(i)
TCLK(i)
DTC(i)
INIT
AIS defect, CRC4 errors, Remote End crc-4 Block Errors, Remote Alarm
Alarms (Out Of Frame, Loss Of Crc MultiFrame, errors in Frameword)
Configuration
Transmitter Monitoring Function
WRB, RDB
CSB, ASB
MCUTYPE
Transmit INTerrupt(i)
INTerrupt
INT
A[7..0]
Microcontroller Interface
Global Registers
Test Pattern Generator
DATA[7..0]
Test Pattern E1 data
DRETCKREF
Receive INTerrupt(i)
Alarms,
Frameword Errors
(Blue Clock)
LOS(i)
RLOS(i)
FILTER
Receiver Monitoring Function
(Los Of signal Alarm)
LOS alarm
Configurations
AIS
Detect
Line Code
Select
AIS force& Enable
Test Pattern Insert
Bpv
CRC4 errors, REBE, Remote Alarm
MTC(i)
(Clock)
MCLK(i)
DRETCKREF
(Blue Clock)
MCLK(i)
MCLK(i)
RCLKI(i)
AIS
or
Test
MCLK(i)
HDB3
Decoder
AIS
Detect
(Receive Clock)
CRC4
Monitoring
NRZ
DATA
E1DATA
MTD(i)
(Data)
RPOSD(i)
+
(HDB3/NRZ Data pos)
Pattern
Insert
RNEGD(i)
(HDB3 Data neg.)
Test Pattern E1 data
Enables
Alarms(Out Of Frame,
Loss Of Multiframe),
Frameword errors
MCLK(i)
&
Frame
MultiFrame recovery
SXT6282
Octal E1 Digital Interface
+ R
E1( #i) RECEIVER
(i= ..0)
Configurations
7
4 of 56
ꢀ
Contents
Figure 2: SXT6282 Block Diagram 2
DRETCKREF
DPLLCKREF
TCLK0
DTC0
DTD0
DTC1
E1 TRANSMITTER #0
E1 TRANSMITTER #1
E1 TRANSMITTER #2
E1 TRANSMITTER #3
E1 TRANSMITTER #4
E1 TRANSMITTER #5
TPOSD0, TNEGD0
TCLK1
TPOSD1, TNEGD1
TCLK2
DTD1
DTC2
TPOSD2, TNEGD2
DTD2
E1 DATA
&
TCLK3
DTC3
E1 HDB3
DATA
CLOCKS
RECEIVED
&
TPOSD3, TNEGD3
TCLK4
CLOCKS
SENT TO
FROM THE
DEMULTIPLEXER
DTD3
THE E1 LIU
(Bird Of Prey)
(SXT6251)
DTC4
TPOSD4, TNEGD4
TCLK5
DTD4
DTC5
TPOSD5, TNEGD5
TCLK6
DTD5
DTC6
DTD6
DTC7
DTD7
E1 TRANSMITTER #6
E1 TRANSMITTER #7
TPOSD6, TNEGD6
TCLK7
TPOSD7, TNEGD7
DATA[7..0]
AD[7..0]
INT
MICRO
INTERFACE
WRB/RWB, RDB/E, ASB
MCUTYPE, CSB
Test Pattern Generator
MTC0
MTD0
MTC1
RCLK0, RLOS0
E1 RECEIVER #0
E1 RECEIVER #1
E1 RECEIVER #2
E1 RECEIVER #3
E1 RECEIVER #4
E1 RECEIVER #5
E1 RECEIVER #6
E1 RECEIVER #7
RPOSD0, RNEGD0
RCLK1, RLOS1
MTD1
MTC2
RPOSD1, RNEGD1
RCLK2, RLOS2
MTD2
RPOSD2, RNEGD2
E1 HDB3
E1 DATA
&
CLOCKS
TRANSMITTED
TO THE
DATA
&
MTC3
CLOCKS
RECEIVED
FROM
THE E1 LIU
(Bird Of
Prey)
RCLK3, RLOS3
MTD3
RPOSD3, RNEGD3
RCLK4, RLOS54
MULTIPLEXER
SXT6251)
(
MTC4
MTD4
MTC5
MTD5
RPOSD4, RNEGD4
RCLK5, RLOS5
RPOSD5, RNEGD5
RCLK6, RLOS6
MTC6
MTD6
RPOSD6, RNEGD6
RCLK7, RLOS7
MTC7
MTD7
RPOSD7, RNEGD7
JTDO
JTCK, JTMS, JTRS, JTDI
JTAG
SCAN
SCANTEST, SCANEN
RSTB, OEN
SXT6282
(10/09/97)
RESET&OEN 3Z
VDD3, VSS3
5 of 56
ꢀ
SXT6282
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figure 3: SXT6282 Pin Assignment
GND_3
VCC_IO
NC
1
DATA7
DATA6
DATA5
DATA4
GND_IO
VCC_IO
DATA3
DATA2
DATA1
DATA0
GND_3
VCC_3
A7
108
107
106
105
104
103
102
101
100
99
2
3
OEN
4
JTCK
5
JTMS
6
JTRS
7
JTDI
8
JTD0
9
DRETCKREF
SCANTEST
SCANEN
VCC_3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
ꢀ
96
GND_3
MCUTYPE
DPLLCKREF
VCC_3
95
A6
94
A5
93
A4
92
A3
XXXX
XXXX
RLOS7
RNEGD7
RPOSD7
RCLK7
TNEGD7
TPOSD7
TCLK7
91
A2
90
A1
(Date Code)
(Trace Code)
89
A0
88
CSB
87
ASB
86
WRB/RWB
SXT6282QE
85
RDB/E
RSTB
INT
RLOS6
RNEGD6
RPOSD6
RCLK6
TNEGD6
TPOSD6
TCLK6
84
83
XXXXXX
VCC_3
GND_3
82
(Lot#)
81
RLOS0
80
RNEGD0
RPOSD0
RCLK0
79
78
RLOS4
RNEGD4
RPOSD4
RCLK4
VCC_IO
77
76
TNEGD0
TPOSD0
TCLK0
75
74
73
GND_IO
6 of 56
ꢀ
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Table 1: Signal Descriptions
Pin Name
Pin
PROP
I/O
Description
E1 Transmitters (receive side of demultiplexer)
E1 data and clocks transmitted to the LIU
TPOSD<7...0> 86
HiZ-4ma O
HiZ-4ma O
HiZ-8ma O
Positive HDB3 or NRZ Data Transmit outputs. Eight E1 data chan-
nel outputs (channel<i>, i=<7..0>) at 2.048 Mbit/s, in either NRZ or
HDB3 format.
79
62
69
50
59
43
34
TNEGD<7...0> 87
Negative HDB3 Data Transmit outputs. Eight E1 data channel out-
puts (channel<i>, i=<7..0>) at 2.048 Mbit/s when HDB3 coding is
used.
80
63
70
49
58
42
33
TCLK<7...0>
85
78
61
68
51
60
44
35
Transmit clock outputs. The 2.048 MHz clock output of each of the
eight independent transmitters (TCLK<i>, i=<7..0>) is to be used
with the corresponding E1 data (TPOSD<i> and TNEGD<i>) signals
when needed.
E1 data and clocks received from the demultiplexer
BUF-in
Demultiplexed NRZ data inputs. Eight E1 data channel inputs
DTD<7...0>
111
116
119
124
129
134
137
142
I
(transmitters, channel<i>, i=<7..0>) at 2.048 Mbit/s received from the
demultiplexer.
1. Buf-in = CMOS Input buffer with switching threshold at 3.3V / 2 (V / 2)
DD
2. i = <7...0> which corresponds to the E1 channel number
7 of 56
ꢀ
SXT6282
Table 1: Signal Descriptions
Pin Name
Pin
PROP
I/O
Description
DTC<7...0>
110
117
118
125
128
135
136
143
BUF-in
I
Demultiplexed Clock inputs. Eight E1 clock inputs (transmitters;
channel <i>, i=<7..0>) at 2.048 MHz received from the demultiplexer.
These clocks can be gapped due to the SDH frame structure and the
justification process.
External Clock References
DRETCKREF 99
BUF-in
BUF-in
I
Demultiplexer Re-timing Clock. This is an external 2.048 MHz ref-
erence clock input that can be used in each E1 transmitter to retime
the E1 data received from the demultiplexer (wander reduction if the
E1 transmitter # i is configured in retiming mode). This clock is also
used as a blue clock in each receiver to generate an AIS signal in case
of RLOS.
DPLLCKREF 93
I
High speed PLL clock reference. This is an external 65.536 MHz (+
/-50 ppm) reference clock that can be used in each E1 transmitter as
the Digital Phase Locked Loop Clock input reference. Only needed if
an E1 transmitter is configured in jitter attenuation mode.
E1 Receivers (Transmit side of multiplexer)
E1 Data and Clocks received from the LIU
RPOSD<7...0> 89
BUF-in
I
Positive HDB3 or NRZ Data Receive. Eight E1 data channel inputs
(channel <i>, i=<7..0>) at 2.048 Mbit/s supplied by the E1 line inter-
face unit(s), in either NRZ or HDB3 format.
82
65
75
47
56
40
31
RNEGD<7...0> 90
BUF-in
I
Positive HDB3 Data Receive. Eight E1 data channel inputs (chan-
nel<i>, i=<7..0>) at 2.048 Mbit/s supplied by the E1 line interface
unit(s), when HDB3 coding is used. If HDB3 coding is not used, these
inputs have to be grounded.
83
66
76
46
55
39
30
1. Buf-in = CMOS Input buffer with switching threshold at 3.3V / 2 (V / 2)
DD
2. i = <7...0> which corresponds to the E1 channel number
8 of 56
ꢀ
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Table 1: Signal Descriptions
Pin Name
Pin
PROP
I/O
Description
RLOS<7...0>
91
84
67
77
45
54
38
29
BUF-in
I
Loss of Signal from the external line interface unit(s). Eight input
alarms from the E1 line interface circuits (channel<i>, i=<7..0>).
RLOS alarm is active high.
RCLK<7...0>
88
81
64
74
48
57
41
32
BUF-in
I
Receive clock inputs. Eight receive E1 clocks at 2.048 MHz provided
by the E1 line interface unit(s).
E1 Data and Clocks transmitted to the Multiplexer
HiZ-4ma O
NRZ Data outputs. Eight E1 data channel outputs of the receivers
MTD<7...0>
112
115
120
123
130
133
138
141
(channel<i>, i=<7..0>) at 2.048 Mbit/s transmitted to the multiplexer.
MTC<7...0>
113
114
121
122
131
132
139
140
HiZ-8ma O
Clock outputs. Each one of these eight 2048 MHz clock outputs of
the receivers is to be used with the corresponding E1 data (MTD<i>,
i=<7..0>) signal transmitted to the multiplexer, if needed.
Microprocessor Bus
A<7..0>
13-20
BUF-in
I
Address Bus 8 bits. Eight-bit address port for data, command and sta-
tus addresses.
DATA<7..0>
1-4
BUF-in/ I/O Data Bus 8 bits. Eight bits I/O to read and write data, commands and
Hiz-
10ma
status to and from the device.
7-10
WRB/RWB
RDB/E
INT
23
24
26
BUF-in
BUF-in
Hiz-4ma
I
Write-Bar Intel; Read/Write Bar Motorola
Read-bar Intel; Enable Motorola
Interrupt request. Active low
I
O
1. Buf-in = CMOS Input buffer with switching threshold at 3.3V / 2 (V / 2)
DD
2. i = <7...0> which corresponds to the E1 channel number
9 of 56
ꢀ
SXT6282
Table 1: Signal Descriptions
Pin Name
CSB
Pin
PROP
I/O
Description
21
22
BUF-in
BUF-in
I
Chip Select. Active low
ASB
I
I
I
Address Strobe Enable. Indication that the address on the address
bus is valid. Active high.
MCUTYPE
RSTB
94
25
BUF-in
Motorola/Intel Interface mode select. A High indicates a Motorola
and a Low an Intel Microprocessor.
BUF-in
(60K
Chip Master Reset. A low will reset all registers to default values.
pull up)
OEN
105
BUF-in
(60K
I
Master chip output enable. Active high (a low will set all outputs
and bidirectionnal to 3Z)
pull up)
JTAG and SCAN test ports
JTCK
JTMS
104
103
BUF-in
I
I
JTAG Clock. Clock for all boundary scan circuitry.
BUF-in
(60K
JTAG Test Mode Select. Determine state of TAP controller.
pull up)
JTRS
JTDI
102
101
BUF-in
(60K
pull
I
I
JTAG Reset. Active low.
down)
BUF-in
(60K
JTAG Data Input. Input signal used to shift in instructions and data.
pull up)
JTDO
100
98
2mA
O
I
JTAG Data Output. Output signal used to shift out instructions and
data.
SCANTEST
BUF-in
(60K
Scan test mode (active low)
pull up)
SCANEN
97
BUF-in
(60K
I
Scan enable (active low)
pull up)
Power Supply
VCC_3
GND_3
12, 27, 52,
71, 92, 96,
109, 127
3.3 V Core supply. (8 pins)
11, 28, 53,
95, 108,
126
GND-Core. Ground for 3.3 V supply. (6 pins)
1. Buf-in = CMOS Input buffer with switching threshold at 3.3V / 2 (V / 2)
DD
2. i = <7...0> which corresponds to the E1 channel number
10 of 56
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PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Table 1: Signal Descriptions
Pin Name
VCC_IO
Pin
PROP
I/O
Description
6, 37, 73,
107, 144
3.3V I/O ring supply. (5 pins)
GND_IO
NC
5, 36, 72
106
GND-I/O Ring. Ground for I/O supply. (3 pins)
This pin should be left unconnected.
1. Buf-in = CMOS Input buffer with switching threshold at 3.3V / 2 (V / 2)
DD
2. i = <7...0> which corresponds to the E1 channel number
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SXT6282
GENERAL FUNCTIONAL DESCRIPTION
Dejitter Mode
In Dejitter mode, the transmitter filters jitter and elim-
inates gaps in the incoming E1 clock and data.
INTRODUCTION
The SXT6282 integrates eight E1 transmitters and eight E1
receivers that can operate independently. It performs jitter/
wander filtering, CRC-4 monitoring and HDB3 encoding/
decoding. It also includes a Motorola/Intel compatible
microcontroller interface for alarm and performance moni-
toring.
The incoming E1 data is fed into a 32-bit FIFO. The
write clock of the FIFO is the gapped input clock
(DTC), which is also fed to the jitter attenuator consist-
ing of a second order All Digital Phase Locked Loop
(ADPLL) having a 2.0 Hz loop bandwidth. The fil-
tered clock output of the ADPLL is the read clock of
the FIFO. The transmitter can be configured to insert
an AIS signal (data “all one” + blue clock) automati-
cally when the FIFO overflows, underflows or the PLL
is unlocked.
The following description follows the simplified block dia-
gram (refer to Figures 1 and 2).
TRANSMITTER DESCRIPTION
The eight fully independent E1 transmitter blocks can be
configured for different applications.
The degapped E1 output is emitted as NRZ data on
TPOSD, or as HDB3 encoded data on TPOSD and
TNEGD. The dejittered and degapped output clock of
each transmitter is emitted on TCLK at the same fre-
quency as the DTC input clock (TCLK clock is the
ADPLL output). This working mode is fully transpar-
ent - no data is lost or added in the transmission.
Each transmitter input interface accepts an NRZ encoded
E1 signal input (DTDx) and clock input (DTCx). The trans-
mission frame structure and the justification process allow
the incoming clock (DTCx) to be gapped and jittered. The
E1 signal (DTDx) may have a CRC-4 multiframe structure
according to recommendation ITU G.704 (refer to Table
2).
Retiming Mode
In the Retiming mode, the transmitter eliminates wan-
der and jitter in the incoming clock (DTC).
The DTDx data is fed to the frame/multiframe recovery
block. This block synchronizes the Transmitter Timing
Generator to the incoming E1 data frame and provides Out
Of Frame (OOF) and Loss Of Multiframe (LOMF) alarm
indications. Remote End Block Errors (REBE) are also
counted and stored in a set of microprocessor-accessible
counters. The Remote alarm is monitored (but not inserted)
for status changes.
Incoming E1 data is converted to a byte parallel format
and fed into a two frame-wide elastic buffer. The write
and read control logic of this elastic store are initial-
ized by the E1 frame acquisition process. The data is
read out of the elastic buffer using an external clock
reference input (DRETCKREF). DRETCKREF may
or may not be at the same frequency as the DTC clock
input. If the read and write frequencies are different,
the elastic store will periodically overflow or under-
flow. In either case, the read control logic will process
a controlled slip of one complete frame in order to re-
center the elastic buffer. This will result in the loss or
repetition of one complete E1 frame.
Once frame synchronization is achieved, any errors in the
frame word are detected, counted and stored in a set of
microprocessor-accessible counters. A CRC-4 calculation
is also performed over the multiframe and compared with
the incoming CRC-4 value. Again, any errors are counted
and stored in a set of microprocessor-accessible counters.
An AIS defect at the DTDx input is also detected and mon-
itored. All framing, multiframing and CRC-4 monitoring
functions can be bypassed if not needed.
The retiming FIFO may also operate on an un-framed
2.048 Mbit/s signal busy setting the transmitter to
“Retiming Test Mode.” In this case, the read and write
control logic of the elastic store is in full free running
mode and independent of the framing algorithm. As
the data is supposed to be un-framed in this test mode,
CRC-4 error monitoring is not valid.
The transmitter can be configured to operate in three differ-
ent modes:
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GENERAL FUNCTIONAL DESCRIPTION
The output from the elastic buffer is converted to a
serial format and emitted as NRZ data on TPOSD, or
output as HDB3 encoded data on TPOSD and
TNEGD, at the TCLK clock rate that is synchronous
with the DRETCKREF clock input.
detected, counted and stored in a set of microprocessor
accessible counters. Remote End Block Errors (REBE) are
also counted and stored in a set of microprocessor-accessi-
ble counters. The Remote alarm is monitored (but not
inserted) for status changes.
This working mode may be non-transparent. It can
handle a maximum of 26 time slots (208 UI) of wander
or low frequency jitter before a frame slip occurs. This
controlled frame slip assures that the time-slot assign-
ment is not lost at the output of the chip. All the jitter
and wander due to the multiplexing/demultiplexing
process in the transmission is eliminated.
A CRC-4 calculation is also performed over the multiframe
and compared to the incoming CRC-4 value. Again, any
errors are counted and stored in a set of microprocessor-
accessible counters.
The E1 signal is emitted as NRZ data on MTD and clock
on MTC.
All the AIS, framing, multiframing and CRC-4 monitoring
functions can be independently bypassed in each receiver if
not needed.
Pass-Through Mode
In the Pass-through mode no dejitter or retiming is per-
formed on the input data.
For testing and maintenance purposes, the receiver can be
set via the microprocessor as a sequence pattern generator
on MTD and MTC data and clock output pins (framed or
unframed PRBS sequence).
The input clock (DTC) is shunted to the output clock
(TCLK). CRC-4 monitoring and HDB3 encoding can
be performed if so configured.
RECEIVE DATA FLOW
DESCRIPTION
The Receiver consists in eight fully independent E1
receiver blocks.
Each receiver input interface includes an NRZ encoded E1
signal input on RPOSDx or HDB3 encoded data on
RPOSDx and RNEGDx, a serial clock RCLKx, and a Loss
Of Signal (RLOSx) alarm indication coming from the out-
put of an E1 Line Interface Unit Receiver. The E1 input
data RPOSD/RNEGD may have a CRC-4 multiframe
structure according to recommendation ITU G.704 (refer to
Figure 3). HDB3 code errors (Bipolar Violations) are
detected and stored in a set of microprocessor-accessible
counters.
An AIS defect is detected according to recommendation
ITU G.775 for the E1 incoming signal after HDB3 decod-
ing, and the corresponding alarm is accessible to the micro-
processor.
If the Loss Of Signal alarm is active, the receiver may
insert an AIS signal (all ones in the data), using the DRET-
CLK clock reference input as a blue clock.
Data is fed to the framing/multiframing block that synchro-
nizes the Receiver Timing Generator to the incoming E1
data frame, and provides Out Of Frame (OOF) and Out Of
Multiframe (OOMF) alarm indications. Once the frame
synchronization is acquired, frame word errors are
13 of 56
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SXT6282
FUNCTIONAL DESCRIPTION PER E1 CHANNEL
to four consecutive frame alignment signals received that
contain single or multiple errors, or four consecutive bit 2
of the non-frame alignment signal not one (if so config-
ured).
TRANSMITTER DEFAULT
OPERATION
Data Input Interface
The Out Of Frame (OOF) alarm status is accessible to the
microprocessor via the status registers.
The relative phase between E1 NRZ data (on DTDx pin)
and clock (on DTCx pin) inputs can be configured via
microprocessor (DTDx data input may be sampled in the
transmitter by the rising or falling edge of the input clock
DTCx: see global register AFH).
CRC-4 Multiframe Alignment
CRC-4 multiframe alignment is used for immunity against
false framing and also provides non-intrusive error moni-
toring capabilities for the E1 payload.
Frame Alignment
The framing method follows the rules set forth in CCITT/
ITU recommendations G.704 and G.706.
When CRC-4 is selected as the E1 framing option the trans-
mitter attempts to synchronize to a 16 frame multiframe
structure illustrated in Table 1.
The frame alignment circuit searches for the first frame
alignment signal (“0011011” frameword, bit 2-8 in time
slot 0) within the incoming E1 data (DTDx). Once
detected, the frame acquisition counter is set to check bit 2
in the non-frame alignment signal (time slot 0) of the next
frame. If bit 2 is one, a second un-errored frame alignment
signal is checked one frame later. Next, the timing genera-
tor counters are set and frame synchronization is declared.
If bit 2 in the non-frame alignment signal is not one, or the
frame alignment signal is not found in the third frame, then
a new search is initiated.
The multiframe consists of 16 basic E1 frames (eight dou-
ble frames), numbered 0-15, that are further divided into
two 8-frame sub-multiframes (SMF I and SMF II). Bit 1 of
each frame is used to transport the Cyclic Redundancy
Check bits, multiframe sync word and Remote End Block
Errors (REBE) in the following manner:
• In the four frames of each SMF that include the FAS
word, bit 1 contains the four CRC bits, numbered C1-
C4.
• In the eight frames of the entire multiframe that
include the NFAS word, bit 1 contains a 6-bit CRC-4
multiframe alignment signal as well as two REBE
indication bits.
If CRC-4 multiframing is configured (see paragraph below
and Figure 3-2), two correct multiframes within 8 ms are
used for immunity against false framing.
Once the E1 frame is synchronized, the framer will go out
of synchronization after three consecutive frame alignment
signals containing single or multiple errors are received. In
addition, it is possible to configure the framing algorithm
via register 0FH, so that the framer will also go out of syn-
chronization if three consecutive bit 2 of the non- frame
alignment signal are not one. A 12-bit microprocessor-
accessible counter can be configured (see global register
0FH) to count either the errored FAS, the errored NFAS, or
the FAS and the NFAS with single or multiple errors.
If the CRC-4 multiframing is not configured, it is possible
to strengthen the frame acquisition algorithm to five con-
secutive frames (three FAS and two NFAS with no error)
by programming global register 0FH. This will minimize
the probability of incorrect synchronization. In this case,
the frame desynchronization algorithm is also strengthened
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FUNCTIONAL DESCRIPTION PER E1 CHANNEL
Table 2: Multiframe TimeSlot 0 Signaling Description
Frame #
1
2
3
4
5
6
7
8
SMF I
0
1
2
3
4
5
6
7
C1
0
0
F
0
F
0
F
0
F
0
1
1
0
1
1
A
0
Sa4
1
Sa5
1
Sa6
0
Sa7
1
Sa8
1
C2
0
A
0
Sa4
1
Sa5
1
Sa6
0
Sa7
1
Sa8
1
C3
1
A
0
Sa4
1
Sa5
1
Sa6
0
Sa7
1
Sa8
1
C4
0
A
Sa4
Sa5
Sa6
Sa7
Sa8
Frame #
1
2
3
4
5
6
7
8
SMF II
8
C1
1
0
F
0
F
0
F
0
F
0
1
1
0
1
1
9
A
0
Sa4
1
Sa5
1
Sa6
0
Sa7
1
Sa8
1
10
11
12
13
14
15
C2
1
A
0
Sa4
1
Sa5
1
Sa6
0
Sa7
1
Sa8
1
C3
RE1
C4
RE2
A
0
Sa4
1
Sa5
1
Sa6
0
Sa7
1
Sa8
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
Legend:
RE: Remote End CRC-4 Block Error indicator bits (REBE)
Sa4-Sa8: Spare bits for national use
C1-C4: CRC-4 Bits
A: Remote Alarm Indication
F: NFAS Framing Bit (normally = 1 to avoid spurious frame sync)
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SXT6282
After FAS/NFAS frame synchronization is acquired, the
CRC-4 multiframe alignment is declared when two correct
CRC-4 MultiFrame Alignment signals are detected within
8 ms (one complete multiframe lasts two ms). If CRC-4
multiframe alignment is not achieved within 8 ms after
frame alignment, a new search will be initiated for valid
FAS/NFAS.
Retiming Elastic Store Operation
This block is used to eliminate the wander and the jitter in
the incoming clock and data (DTC and DTD). It may be
non-transparent for the incoming data (see frame slips,
below), but it keeps the time slot alignment in the E1 frame.
The incoming data is converted to a byte parallel format
and clocked into a 2 frame wide elastic buffer. The write
and read control logic of this elastic store are initialized by
the frame synchronization process. Once the frame is
acquired, the Elastic Store is centered and the data is read
out of the elastic buffer and re-converted to a serial format
using an external system clock reference input (DRETCK-
REF).
Once the CRC-4 Multiframe is acquired, a Loss Of CRC-4
Multiframe (LOMF) is declared when the frame synchroni-
zation is lost, or the CRC-4 error rate is greater or equal to
915 block/s. The Loss Of CRC-4 Multiframe alarm is
accessible to the microprocessor via the status registers.
AIS Detection
If the incoming clock DTC and the system clock
DRETCKREF are synchronous and phase-locked (i.e., in
the case of a synchronous network), the elastic buffer will
never overflow or underflow.
An AIS defect is detected in the DTDx input data when the
incoming signal has two or less ZEROs in each of two con-
secutive double frame periods (512 bits). This defect alarm
is cleared when each of two consecutive double frame peri-
ods contain three or more ZEROs or when the frame align-
ment signal has been found.
If these two clocks, (DRETCKREF and DTC) do not have
the same frequency, the elastic store will overflow or
underflow repetitively, depending on the frequency offset.
The AIS defect alarm status is accessible to the micropro-
cessor via the status registers.
If the read system clock (DRETCKREF) frequency is
higher than the write incoming clock (DTC) frequency,
then when the FIFO is close to underflowing, the read con-
trol logic will perform a slip of one complete frame. This
results in the repetition of the last received frame (“positive
slip”).
CRC-4 Multiframe Monitoring
CRC-4 Block Errors Calculation
When the CRC-4 multiframe is synchronized, the
CRC-4 bits are calculated internally based on a sub-
multiframe (as specified in recommendation ITU
G704) and compared to the incoming CRC-4 value in
the next sub-multiframe. The block errors are stored in
a 10-bit counter that can be read by the microproces-
sor. A maskable interrupt is provided for counter over-
flows.
If the read system clock (DRETCKREF) frequency is
lower than the write incoming clock (DTCx) frequency,
then when the FIFO is close to overflow, the read control
logic will perform a slip of one complete frame. This
results in the loss of the last received frame (“negative
slip”).
Positive and negative slips in the elastic store are indicated
via two maskable interrupts, and counted in two different
4-bit counters accessible via the microprocessor. A
maskable interrupt is provided to indicate counter over-
flows.
Remote End Block Errors
Two bits per multiframe (RE1 and RE2) are allocated
for the CRC-4 Remote End Block Errors (REBE) indi-
cation. These errors are counted and stored in a 10 bit
counter that can be read by the microprocessor. A
maskable interrupt is provided for counter overflows.
For FIFO and Wander monitoring, or delay calculation, the
relative difference between FIFO write and read pointers is
indicated in register iCH (6 bits used), accessible via the
microprocessor.
Remote Alarm
The Remote alarm bit (bit 3 in the NFAS) is used to tell
the transmit end that the receive end has detected a loss
of signal or loss of frame. The remote alarm is filtered
for three consecutive frames before being declared a
new value. Changes in its status is indicated to the
microprocessor via a maskable interrupt.
For testing and debugging, this two-frame-wide elastic
buffer may be reset via the microprocessor to its center
point (see register iEH).
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FUNCTIONAL DESCRIPTION PER E1 CHANNEL
Figure 4: Frame and Multiframe Acquisition
Frame Acquisition
Incorrect
FAS
Out Of
Frame
STate
(OOF)
incorrect
NFAS
correct FAS
=> Reset Frame Acquisition
Counter
incorrect
NFAS or
Desync CRC MF
ST1
(OOF)
incorrect
FAS or
Desync CRC MF
correct NFAS (bit 2)
ST6
(OOF)
4
consecutive
Correct FAS and
CRC MF Disabled
and StrgFA
incorrect NFAS
and
CnfFaOp[1,0]=11
3
consecutive
incorrect NFAS
and
CnfFaOp[1,0]=01
3
consecutive
4
consecutive
incorrect FAS
and
CnfFaOp[1,0]=0X
incorrect FAS
and
CnfFaOp[1,0]=1X
correct NFAS (bit 2)
ST2
(OOF)
Desync CRC MF
ST7
(OOF)
correct FAS and
(not StrgFA or CRC MF
Enbl)
IN FRAME
STate
correct FAS
=> /OOF
=> Reset Timing Generator Counter
=> Start TIME OUT DECOUNTER FOR MF Search(8 ms)
Note
:
.For CRC MF Enabled/Disabled Configuration Condition
see register definition.
OUT OF
MULTIFRAME
ST
.FAS
.NFAS
.CnfFaOp[1,0]
register (see global registers definition)
.Desync CRC MF Desynchronized CRC MultiFrame
initiates new frame search if CRC MF is enabled.
.OOF means Out Of Frame Alarm
.LOMF means Loss Of MultiFrame Alarm.
:
means Frame Alignment Signal
means Not Frame Alignment Signal
Configure Frame Acquisition Operation
:
:
(LOMF Alm)
MFAS Word found,
no OOF Alm.,
and Time Out decounter /=
:
0
a
=> Desync CRC MF
(if CRC MF is Enabled)
=> LOMF
:
:
Time out (>8ms)
or
CRC Block error rate
914 block/s
OOF Alm
CRC MF
ACQUISITION
STate
>
or
OOF Alm.
(LOMF Alm)
CRC-4 MultiFrame Acquisition
MFAS word found
IN CRC
MultiFrame
STate
=> /OOMF
Frame and CRC MultiFrame Recovery
(05/19/97)
17 of 56
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SXT6282
A maskable interrupt is also provided to indicate the inop-
erability of the elastic store. This alarm indicates that the
clock frequencies are so different that slippage is continual.
When the transmitter is configured to operate in dejitter
mode, an AIS signal may be automatically hardware
inserted when enabled (see registers iEH and AFH), if the
dejitter ADPLL is unlocked and the FIFO crashed. In this
case, the AIS blue clock is derived from the high-speed
PLL reference clock (+/- 50 ppm), and the transition from
non-AIS clock to AIS blue clock (and the inverse) is
always smooth. The AIS state is accessible to the micropro-
cessor via the global status register 9FH.
By setting a special configuration in register iEH, the trans-
mit retiming 2 frame-wide elastic store (512 bits) may be
used to retime an un-framed 2.048 Mbit/s signal for wander
elimination. In this case, the read and write pointer of the
FIFO are independent of the framing algorithm and operate
in complete free running mode, but the CRC-4, REBE and
remote alarm monitoring are un-valid, as the 2.048 Mbit/s
input signal is considered un-framed.
Line Coding HDB3
The serial E1 output is a HDB3 signal output on TPOSD
and TNEGD. The output clock is TCLK (2.048 MHz). For
testing, it is possible to insert (microprocessor config-
urable) BPV errors on TPOSD and TNEGD output data. A
single code error, one error every 1024 bits (BER 10-3),
one error every multiframe, or one error every second may
be inserted.
The retiming elastic store can be bypassed by using the
dejittering circuitry or configuring the data path in pass-
through mode (see register iEH).
De-jittering Circuitry
The de-jittering circuitry consists of the dejitter FIFO and a
jitter attenuator or phase lock loop. This function can be
bypassed by using the retiming function or configuring the
data path in pass-through mode (see register iEH).
If the HDB3 encoder is not used, TPOSD is used as an NRZ
output.
The relative phase between output data and clock can be
configured via microprocessor (TPOSDx/TNEGDx data
outputs emitted on rising or falling edge of the output clock
TCLKx: see global register AFH).
The dejitter FIFO is a 32-bit asynchronous FIFO, whose
write clock is the input gapped clock (DTCx) at 2.048MHz
+/- 50 ppm average frequency, and whose read clock is the
phase-locked and filtered output of the jitter attenuator (the
ADPLL).
Depending on the transmitter configuration, TCLK trans-
mit clock output may be provided by different sources:
The jitter attenuator is a second order All Digital Phase
Lock Loop with a 2.0 Hz loop bandwidth. The reference
and sample clock of the digital PLL is provided by the high
speed clock input pin DPLLCKREF at 65.536 MHz +/- 50
ppm. DPLLCKREF reference clock is provided by an
external crystal oscillator. When the de-jittering circuitry is
not selected in a transmitter, the high speed clock is shut
down in this specific transmitter to save power consump-
tion.
A maskable interrupt is provided to indicate dejitter FIFO
overflows.
AIS Signal Insertion
An AIS signal (unframed all ones signal) can be generated
using the external clock input DRETCKREF at 2.048 MHz
+/- 50 ppm (if the transmitter is configured to operate in
retiming or passed through mode) or using the high-speed
ADPLL reference clock at 65.536 MHz +/- 50 ppm divided
by 32 (if the transmitter is configured to operate in dejitter
mode), as a blue clock on the E1 transmitter output.
18 of 56
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FUNCTIONAL DESCRIPTION PER E1 CHANNEL
Table 3: Transmitter clock output scheme
TCLK clock sources
Synchronous with
Clock source
DRETCKREF
Retiming Mode (No AIS or AIS)
Dejitter Mode (No AIS)
DRETCKREF input
DTC input
ADPLL filtered output
DPLLCKREF/32
DTC
Dejitter Mode (AIS insert)
DPLLCKREF input/32
DTC input
Pass Through Mode (No AIS)
Pass Through Mode (AIS insert)
DRETCKREF input
DRETCKREF
AIS Detection
RECEIVER OPERATION
After HDB3 decoding, an AIS detection is performed
on the incoming data according to recommendation
ITU G.775.
Line decoding HDB3
The HDB3 decoder is microprocessor selectable.
When selected, this block accepts an HDB3 encoded
E1 signal via data inputs RPOSDx and RNEGDx and
clock RCLKx. A bipolar violation (or code error)
detector is implemented in the HDB3 decoder. The
Bipolar Violation (BPV) Errors Detector can be con-
figured for all the E1 HDB3 receivers via the micro-
processor. The detector can:
AIS defect alarm is declared when each of two consec-
utive double frame periods (512 bits) has two or less
ZEROs, and the alarm is cleared when three or more
ZEROs or when the Frame Alignment Signal has been
found in each of two consecutive double frame peri-
ods.
The AIS defect alarm status is accessible to the micro-
processor via the status registers.
• be disabled
• detect two consecutive ‘1’s’ with the same polar-
ity (except when it is used as part of a valid
HDB3 substitution)
AIS Insert/LOS Alarm filtering
This block includes a filter for Loss Of Signal Alarm
input on RLOS pin from the external LIU. The filter-
ing on the LOS can be integrated over 128 clock cycles
or disabled via microprocessor.
• detect BPV that do not alternate polarity (recom-
mendation ITU O161)
• detect two consecutive ‘1’ with the same polarity,
or BPV that do not alternate polarity, or four con-
secutive ‘0’ badly encoded.
An AIS signal (unframed all ones in the data) can be
inserted on the incoming data RPOSD and RNEGD
after decoding in case of LOS alarm. DRETCKREF
clock reference input (2.048 MHz +/- 50 ppm) may be
used as a blue clock for AIS generation, if the receiver
is so configured. The AIS insert can also be disabled or
forced via microprocessor (see configuration register
jEH). The AIS state for every receiver is reported in
the global status registers.
BPV errors are accumulated in a 16-bit counter that
can be read by the microprocessor. A maskable inter-
rupt is provided to indicate counter overflows.
If the HDB3 decoder is not used, the E1 NRZ data is
input on RPOSD. In this case, RNEGD input pin has
to be grounded, and the BPV error detection is invalid.
The relative phase between E1 data (on RPOSDx/
RNEGDx pins) and clock (on RCLKx pin) inputs can
be configured via microprocessor (RPOSDx/
RNEGDx data inputs may be sampled, in the transmit-
ter, by rising or falling edge of the input clock RCLKx:
see global register AFH).
Frame Alignment/Out Of Frame Alarm
The framing method follows the rules set forth in
CCITT/ITU recommendations G.704 and G.706 and is
the same as the one described in the transmitter. Refer
to Frame Alignment section on page 14 and Figure 1
on page 18.
Out Of Frame status changes are indicated via a
maskable interrupt, and errored FAS/NFAS (see glo-
19 of 56
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SXT6282
bal configuration register 0FH) are counted via a 13-
bit microprocessor-accessible counter.
Test Pattern Generator for Autotesting/
Maintenance
CRC-4 Multiframe Alignment/Out of
CRC Multiframe Alarm
The multiframe acquisition is the same as in the trans-
mitter. Refer to CRC-4 Multiframe Alignment on page
14.
CRC-4 E1 Framed Test Pattern
An internal E1 framed pattern generator may be
enabled via the microprocessor for autotesting and
maintenance purposes. The sequence consists of an E1
CRC-4 framed signal with the FAS, NFAS, MFAS
and CRC-4 bits in the time slots 0 and a PRBS 2E15-
1 sequence in the time slots 1 ->31.
Loss Of CRC-4 Multiframe status changes are indi-
cated via a maskable interrupt.
If enabled (see registers 1FH and jEH), the E1 framed
test pattern sequence is sent to the receiver input and
then emitted on MTD data output pin, with the associ-
ated DRETCKREF blue clock emitted on MTC clock
output pin. So, by looping back externally, the MTC/
MTD output signals to the DTC/DTD input signals,
the chip can be autotested without any external test
equipment.
CRC-4 Multiframe Monitoring
CRC-4 Block Errors Calculation
Once the CRC-4 multiframe is acquired, the CRC-4
bits are calculated internally based on a sub-multi-
frame (as specified in recommendation ITU G704) and
compared to the incoming CRC-4 value in the next
sub-multiframe. The block errors are accumulated in a
10-bit counter that can be read by the microprocessor.
A maskable interrupt is provided to indicate counter
overflows.
PRBS Unframed Test Pattern
If enabled (see registers 1FH and jEH), the internal test
pattern generator can also generate the standard
pseudo-random (2E15-1 sequence) unframed test sig-
nal used for E1 jitter analysis (Recommendation ITU-
T O171) emitted on MTD data output pin, with the
associated DRETCKREF blue clock emitted on MTC
clock output pin.
Remote End Block Errors
Two bits per multiframe (RE1 and RE2) are allocated
for the CRC-4 Remote End Block Error (REBE) indi-
cation. REBEs are accumulated in a 10-bit counter that
can be read by the microprocessor. A maskable inter-
rupt is provided to indicate counter overflows.
MICROCONTROLLER INTERFACE
This section contains a description of the asynchronous
microprocessor interface. A microprocessor should be con-
nected to the SXT6282 for reading and writing data via the
microprocessor interface pins.
Remote Alarm
The Remote alarm bit (bit 3 in the NFAS) is used to tell
the transmit end that the received end has detected a
loss of signal or loss of frame. The remote alarm is fil-
tered for three consecutive frames before being
declared a new value. A change in its status is indi-
cated to the microprocessor via a maskable interrupt.
The microprocessor interface is a generic asynchronous
interface, including an address bus (A [7..0]), data bus
(DATA [7..0]) and handshaking pins (WRB/RWB, RDB/
E, CSB, and ALE). The MCUTYPE input pin indicates the
type of microprocessor interface to be used – Intel or
Motorola. There is also an INT output pin that indicates sta-
tus changes to the microprocessor.
Output Interface
NRZ receive data and clock are emitted on MTDx and
MTCx pins. MTCx clock is synchronous with an
RCLKx input clock or DRETCKREF blue clock if
AIS is inserted in the receiver or if in Autotest Mode.
The relative phase between output data and clock can
be configured via the microprocessor (MTDx data out-
puts emitted on the rising or falling edge of the output
clock MTCx: see global register AFH).
This interface has the same features as SFT’s SXT6051 and
SXT6251 chips.
Intel Interface
The Intel interface is indicated by driving the MCU-
TYPE input pin HIGH. It uses the WRB/RWB input
pin as WRB and the RDB/E input pin as RDB.
20 of 56
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FUNCTIONAL DESCRIPTION PER E1 CHANNEL
A read cycle is indicated to the SXT6282 by the uP
forcing a LOW on the RDB pin with the WRB pin held
HIGH.
1) Status change of a monitoring process: For exam-
ple, the SXT6282 monitors the incoming E1 frame for
the correct framing pattern and updates the OofSt and
LofSt status bits to indicate presence or absence of Out
Of Frame and Loss Of Frame conditions. When the
value of these status bits change an interrupt is gener-
ated if enabled.
A write cycle is indicated to the SXT6282 by the uP
forcing a LOW on the WRB pin with the RDB pin held
HIGH.
Both cycles require the CSB pin to be LOW and the uP
to drive the A[7..0] address pins. In the case of the
write cycle, the uP is also required to drive the DATA
[7..0] data pins. In the case of the read cycle, the
SXT6282 drives the DATA [7..0] data pins.
2) Event Occurrence: For example, positive and nega-
tive slips as well as FIFO overflows are considered
“events” and can generate interrupts if enabled.
3) Counter overflows: For example, the SXT6282
monitors the E1 frame structure for framing errors.
These errors are recorded in a counter whose overflow
can cause an interrupt if enabled.
When a multiplexed data/address bus is used, the fall-
ing edge of the ALE input latches the address provided
on the muxed bus (the muxed bus will be connected to
both the A[7..0] and DATA[7..0]). If the address and
data are not multiplexed the ALE pin should be tied
HIGH.
Interrupt Enables
In order for an interrupt source to affect the state of the
INT output pin its associated interrupt enable bit must
be SET. The setting (whether it is 0 or 1) of the inter-
rupt enables does not affect the updating of the status
registers or counters.
Motorola Interface
The Motorola interface is indicated by driving the
MCUTYPE input pin LOW. It uses the WRB/RWB
input pin as RWB and the RDB/E input pin as E.
Assuming the interrupt enable for a particular interrupt
source is SET and the interrupt source is active, its
interrupt bit will be SET. The primary difference
between each interrupt type is the way its respective
interrupt bit is cleared.
A read cycle is indicated to the SXT6282 by the uP
forcing a HIGH on the RWB pin. A write cycle is indi-
cated to the SXT6282 by the uP forcing a LOW on the
RWR pin.
Interrupt Clearing
In the discussion below it is assumed that the example
interrupt sources have their interrupt enable bits SET.
A LOW on the E input initiates both cycles. The E
input is connected to the E output from the Motorola
uP and is typically a 50% duty cycle waveform with a
frequency derived from the uP clock.
Status change interrupt sources have their interrupt
bits cleared when their status is read. For example, say
the OofSt bit changes from zero to one (in frame to out
of frame). Its interrupt bit is SET by this event. When
the microprocessor reads the register containing the
OofSt bit its interrupt bit will be CLEARED. If the
OofSt bit subsequently changes from one to zero (out
of frame to in frame) again its interrupt bit is SET by
this event and then CLEARED when the status is read.
Both cycles require the CSB pin to be LOW and the uP
to drive the A[7..0] address pins. In the case of the
write cycle, the uP is also required to drive the DATA
[7..0] data pins. In the case of the read cycle, the
SXT6282 drives the DATA [7..0] data pins.
When a multiplexed data/address bus is used, the fall-
ing edge of the ALE input latches the address provided
on the muxed bus (the muxed bus will be connected to
both the A[7..0] and DATA[7..0]). If the address and
data are not multiplexed the ALE pin should be tied
HIGH.
The interrupt register can be read again only after three
interval clock cycles (1.47) have completed since it
has been cleared (by reading its associated status reg-
isters).
IINTERRUPT HANDLING
It should be noted that updates to status bits are not
affected by the interrupt bit state. For example, the
OofSt bit could change from a one to zero (generating
an interrupt) and then before the microprocessor reads
Interrupt Sources
There are three types of interrupt sources:
21 of 56
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SXT6282
OofSt it could change back to one. This would have no
affect on its interrupt bit since it would already be
SET. When the microprocessor reads the OofSt bit it
would read a one.
Both event interrupts and counter overflow interrupts
are cleared when the interrupt register containing these
bits is read (since event and counters do not have any
associated status registers).
Status Registers Access
Due to the asynchronous nature of the microprocessor
interface and timing differences during interrupt bit
updates, it is possible that a status bit change can fail
to SET its associated interrupt bit if the AlmUpdDsbl
bit is not SET during a read of the status registers by
the microprocessor. This situation is very difficult to
achieve however, it can happen.
For this reason we encourage programmers to SET the
AlmUpdDsbl bit before accessing the status registers
during alarm processing. This effectively locks out
internal processes that wish to access the status and
interrupt bits during the time that the microprocessor is
accessing these bits. After the microprocessor is done
accessing the status registers it should CLEAR the
AlmUpdDsbl bit so that internal processes may again
update the status and interrupt bits.
Counter Reading
Counters are read by first buffering their contents and
then reading the buffer. They can be individually buff-
ered or group buffered. They are group buffered by
writing to register BfrAllCntrs (5FH). They are indi-
vidually buffered by writing to the most significant
byte of a particular buffer. After buffering the counter,
the contents of the buffer are read at the address spec-
ified in the register definition.
For example, to read the contents of the transmitter #1
FrameWord counter a write to register 07H will buffer
only the contents of transmitter #1’s frame word
counter. A read of registers 06H and 07H will give the
counter value. Alternatively, all of the frame word
counters for all 8 transmitters and receivers can be
buffered by writing a 02H to register 5FH.
A counter can be read only after three interval clock
cycles (1.47) have completed since it has been buff-
ered (previous write operation. (JCC)
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MICROPROCESSOR REGISTER DESCRIPTION
MICROPROCESSOR REGISTER DESCRIPTION
The address mapping (8 address bits) is the following:
• addresses 0FH -> AFH: Global registers
• addresses i1H -> iEH: transmitter registers (i = {0 to 7} and i = E1 channel number)
• addresses j1H -> jEH: receiver registers (j = {8 to 15} and (j-8) = E1 channel number)
Page
#
Address
Mnemonic
Register Name
Type
Global Registers
0FH
0FH
2FH
3FH
4FH
5FH
8FH
9FH
AFH
GLOP_CONF0
Operational Configuration 0
Operational Configuration 1
Individual Transmit E1 Channel Interrupt
Individual Receive E1 Channel Interrupt
Chip ID Number
R/W
R/W
R
25
26
27
27
27
28
28
28
29
GLOP_CONF1
IND_TRNSE1_CHN
IND_RECE1_CHN
CHIP_ID_NMB
BUFF_ALLCNT
E1_REC_AISTAT
E1_TRNS_AISTAT
GLOP_CONF
R
R
Buffer All Counters
W
E1 Receivers AIS Status
R
E1 Transmitters AIS Status
Operational Configuration 3
R
R/W
Transmitter Alarm Status and Configuration Registers (E1 channel #i, i = {0 to 7})
iEH
TRAMS_CONF
Transmitter Configuration
R/W
R
31
32
32
33
33
34
34
34
35
35
i1H
TRAN_ALRMIN0
TRAN_ALRMIN1
TRAN_ALRM_STAT
TRAN_ALRM_INTE0
TRAN_ALRM_INTE1
TRAN_FRMWD_ERC
TRAN_BLCK_ECR
TRAN_RMT_ERC
TRAN-RETMBUF
Transmitter Alarm Interrupt 0
i2H
Transmitter Alarm Interrupt 1
R
i3H
Transmitter Alarm Status
R
i4H
Transmitter Alarm Interrupt Enable 0
Transmitter Alarm Interrupt Enable 1
Transmitter FrameWord Error Counter
Transmitter CRC-4 Block Errors Counter
Transmitter Remote CRC-4 Block Errors Counter
R/W
R/W
R
i5H
i7-i6H
i9-i8H
iB-iAH
iCH
R
R
Transmitter Retiming Buffer Pos. & Neg. Slip
Counters
R
iDH
TRAN_RTMBUF_STAT
Transmitter Retiming Buffer Status
R
36
Receivers Alarm Status and Configuration Registers (E1 channel #i = j - 8, j = {8 to 15})
jEH
j1H
REC_CONF
Receiver Configuration
R/W
R
37
38
REC_ALRMIN0
Receiver Alarm Interrupt 0
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SXT6282
Page
#
Address
Mnemonic
Register Name
Type
j2H
REC_ALRMIN1
REC_ALRMS
Receiver Alarm Interrupt 1
Receiver Alarm Status
R
R
38
39
39
40
40
40
41
41
j3H
j4H
REC_ALRM_INTEREG0 Receiver Alarm Interrupt Enable Register 0
REC_ALRM_INTEREG1 Receiver Alarm Interrupt Enable Register 1
R/W
R/W
R
j5H
j7-j6H
j9-j8H
jB-jAH
jD-jCH
REC_FRMWD_ERC
REC_BLCK_ERC
REC_RMT_BLCK_ERC
REC-CD_ERC
Receiver FrameWord Error Counter
Receiver CRC-4 Block Error Counter
Receiver Remote CRC-4 Block Error Counter
Receiver Code Errors Counter
R
R
R
GLOBAL REGISTERS
The registers described in this section are related to global configuration, tests and alarms.
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MICROPROCESSOR REGISTER DESCRIPTION
GLOB_CONF0 - Global Operational Configuration 0 (0FH)
Configures high level operational characteristics of the chip.
Bit Name Label
Type Default
0
Bit
CnfBpvIns[1..0] These bits configure the code errors (Bipolar Violation) inserted in all R/W
the E1 HDB3 transmitter outputs (TPOSD and TNEGD, to the LIU)
<7:6>
when the BpvInsert is enabled (see register iEH) - (used for testing)
00 - Insert a single code error
01 - Insert one code error per second (used for testing)
10 - Insert one code error per multiframe (used for testing)
11 - Insert one code error per 1000 bits (BER 10-3) (used for testing)
Bit
<5:4>
CnfBpvDet[1..0] These bits configure the Bipolar Violation Errors Detection in all the R/W
E1 HDB3 receivers (on RPOSD and RNEGD inputs, from the LIU).
1
00 - Disable Bpv Detection
01 - 2 consecutive ‘1’ with the same polarity
10 - BPV do not alternate polarity (recommendation ITU O161)
11 - two consecutive ‘1’ with the same polarity, BPV do not alternate
polarity, or four consecutive’0’ badly encoded
Bit
<3:2>
CnfFeCnt[1..0]
CnfFaOp[1..0]
These bits configure the FrameWord (FAS/NFAS) error counters in all R/W
the E1 transmitters and receivers.
0
0
00 - Disable FrameWord error counter
01 - Count only FAS with single or multiple errors
10 - Count only errored NFAS (bit 2)
11 - Count both errored FAS and NFAS
Bit
<1:0>
These bits configure the Frame Acquisition Algorithm in all transmit- R/W
ters and receivers. The robust acquisition modes are only relevant if
CRC-4 multiframing is disabled (see registers iEH and jEH). CRC-4
Multiframing selected always uses normal acquisition modes.
00 - Normal Acquisition: During acquisition, check three consecutive
frames with two correct FAS and one correct NFAS. De-synchroniza-
tion caused by three consecutive incorrect FAS.
01 - Normal Acquisition/de-synchronization using both FAS/NFAS:
During acquisition, check three consecutive frames with two correct
FAS and one correct NFAS. De-synchronization caused by three con-
secutive incorrect FAS or by three consecutive bit 2 of NFAS, not 1.
10 - Robust Acquisition: During acquisition, check five consecutive
frames with three correct FAS and two correct NFAS. De-synchroni-
zation caused by four consecutive incorrect FAS.
11 - Robust Acquisition/de-synchronization using both FAS/NFAS:
During acquisition, check five consecutive frames with three cor-
rect NFAS. De-synchronization caused by four consecutive incorrect
FAS or by four consecutive incorrect NFAS.
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SXT6282
GLOB_CONF1- Global Operational Configuration 1 (1FH)
Bit
Name
Label
Type
R/W
Default
Bit 7
AlmUpdDsbl This bit enables/disables updates to status registers.
0 - Enable status updates when alarm interrupt is active
1 - Disable status updates when alarm interrupt is active
0
0
Bit 6
MastIntEn
Enables/disables the chip interrupt pin.
R/W
0 - Disable
1 - Enable
Bit
Unused
<5:4>
Bit 3
TestTBR
Test Bit: has to be set to 0
0 - Normal operation
R/W
R/W
0
1
1 - Test Only - non-working mode
Bit 2
AutotestCnfg This bit configures the generation of the test pattern sequence as
framed or unframed (both test pattern sequences are described in
0.151)
0 - Unframed (PBRS2E15-1 sequence).
1 - CRC-4 framed sequence. The PRBS2E15-1 sequence is transmit-
ted in time slot 1 to 31 (and stopped during timeslot 0.)
Bit 1
Bit 0
ADPLLTest
CntrTest
This bit should always be set to 0 during normal operation. It allows R/W
faster testing of the eight digital PLLs during simulation.
0
0
0 - Normal operation
1 - Very fast tracking PLLs
This bit should always be set to 0 during normal operation. It allows R/W
faster testing of the overflow interrupt functionality during simula-
tion.
0 - Normal operation
1 - set overflow count: error counter 4; retiming slip counters: 2
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MICROPROCESSOR REGISTER DESCRIPTION
These next two registers (2FH and 3FH) indicate which channel (receiver or transmitter) has caused an interrupt.
For example, when a channel incurs a receive LOS alarm event, if the interrupt is enabled, the LosInt bit in the interrupt
register will be set and causing the device interrupt pin to become active. The microcontroller would then read the Receive
E1 Channel interrupt register 3FH to determine the channel in alarm. Next the Channel Interrupt Registers Receive j1H
would be read to identify the alarm. Finally, the status register j3H is read to determine the current alarm state. This last
read would also clear the corresponding interrupt register.
IND_XMTE1_CHN - Individual Transmit E1 Channel Interrupt (2FH)
Bit
Name
Label
Type
RO
Default
Bit
XmtChannel
This register indicates which E1 channel transmitter has
caused an interrupt.
0
<7:0> XMTINT <7:0>
IND_RCVE1_CHN - Individual Receive E1 Channel Interrupt (3FH)
Bit
Name
Label
Type
RO
Default
Bit
<7:0>
RcvChannel
RCVINT <7:0>
This register indicates which E1 channel receiver has
caused an interrupt.
0
CHIP_ID_NMB - Chip ID Number (4FH)
This register can only be read. It is used to identify the version of the chip.
Bit
Name
Label
Type
RO
Default
Bit
<7:0>
ChipID [7:0] This field contains the chip identification value
01H
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SXT6282
BUFF_ALLCNT - Buffer All Counters (5FH)
A write to this location causes all of the counters of the same type to be loaded into buffers and then cleared. This
operation assumes that those counters can be monitored in the same second. The contents of an individual counter
buffer can then be read at the addresses specified for the counters in this document. Counters can be individually buff-
ered by writing to the specified MSByt of the counter of interest.
Bit
Bit
Name
Unused
Label
Type
Default
<7:2>
Bit
<1:0>
BfrAllCntrs[1:0]
A write to these bits selects the counters to be loaded at the WO
same time.
0
00 - all CRC-4 Block Error counters both transmit and
receive (16 x 10-bit counters) plus all Positive and Negative
Frame Slip Counters (transmit side: 16 x 4-bit counters)
01 - all REBE Counters both transmit and receive (16x 10-
bit counters) plus all Retiming FIFO Status Bits (transmit
side: 8 x 6-bits, 8 registers iDH)
10 - all FrameWord Error Counters both receive and trans-
mit (16 x 13-bit counters)
11 - all Code Errors counters (receive side) (8 x 16-bit
counters)
E1_RCV_AISTAT - E1 Receivers AIS Status (8FH)
This register indicates the status of internal chip logic for AIS generation processes in each of the eight E1 receivers.
Bit
Bit
Name
Label
Type
RO
Default
GenRcvAISCh<7:0> Present status of E1 receiver #n (n= <7..0>) AIS generator.
0
<7:0>
0 - No AIS
1 - AIS
EI_XMT_AISTAT - E1 Transmitters AIS Status (9FH)
This register indicates the status of internal chip logic for AIS generation processes in each of the eight E1 transmitters.
Bit
Bit
Name
Label
Type
RO
Default
GenXmtAISCh<7:0> Present status of E1 transmitter #n (n=<7..0>) AIS genera-
tor.
0
<7:0>
0 - No AIS
1 - AIS
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MICROPROCESSOR REGISTER DESCRIPTION
GLOB_CONF - Global Operational Configuration 3 (AFH)
Bit
Name
Label
Type
Default
Bit 7 CnfTxClkIn
Clock Edges specification at the data interfaces:
R/W
0
This bit Configures the phase relation between clock and data
at the transmitter inputs (DTCx and DTDx input pins).
0 - DTDx input data is sampled in the chip by the falling edge
of DTCx clock.
1 - DTDx input data is sampled in the chip by the rising edge
of DTCx clock.
Bit 6 CnfTxClkOut
Bit 5 CnfRxClkIn
Bit 4 CnfRxClkOut
This bit configures the phase relation between clock and data R/W
at the transmitters outputs (TCLKx and TPOSDx/TNEGDx
output pins).
0
0
0 - TPOSDx/TNEGDx output data are sampled by the rising
edge of TCLKx clock.
1- TPOSDx/TNEGDx output data are sampled by the falling
edge of TCLKx clock.
This bit configures the phase relation between clock and data R/W
at the receivers inputs (RCLKx and RPOSDx/RNEGDx
input pins).
0 - RPOSDx/RNEGDx input data are sampled in the chip by
the rising edge of RCLKx clock.
1 - RPOSDx/RNEGDx input data is sampled in the chip by
the falling edge of RCLKx clock.
This bit configures the phase relation between clock and data R/W
at the receivers outputs (MTCx and MTDx output pins).
0
0
0 - MTDx output data are sampled by the falling edge of
MTCx clock.
1- MTDx output data are sampled by the rising edge of
MTCx clock.
Bit
DjtAisSetWinNum[3:0]
Consecutive windows for setting AIS in the transmitters
(dejitter mode):
R/W
<3:0>
These bits are only relevant in dejitter mode (Transmitter)
and are common for the eight transmitters when hardware
AIS is enabled (see register iEH).
Number of consecutive 200 ms windows that must detect
dejitter ADPLL unlocked and dejitter FIFO crash to insert
AIS and switch to the blue clock on the transmitter output.
(Detection time = DjtAisSetWinNum *200 ms.)
(Note: DjtAisSetWineNum = 0 => immediate insertion of
AIS after detection of dejitter FIFO crash alarm)
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SXT6282
TRANSMIT SIDE REGISTERS
The registers described in this section are related to the E1 transmitters alarm status and configuration.
There are eight E1 transmitters in the chip, and 14 registers per E1 transmitter. The 4 MSB bits of the register addresses
indicate the E1 channel number (from 0 to 7). The eight transmitters are each capable of generating 12 alarm types. Any
one of these alarms (if enabled) can cause the device interrupt pin to become active.
Each E1 transmitter alarm has three registers associated with it:
• Interrupt source: This register set will identify the alarm(s) that triggered the interrupt.
• Alarm status: This register contains the current status of the alarm. When this register is read, the corresponding inter-
rupt will be cleared.
• Interrupt Enable: This register contains the interrupt enable for all alarms.
Status alarms will generate an interrupt when the alarm changes from inactive to active or active to inactive. The event and
overflow alarms generate an interrupt when detected.
Updating the status register is controlled by the AlmUp-dateDsbl configuration bit in global register 0FH. When low, status
register are updated once every frame, regardless of the interrupt state. When high, status alarm memory updates will be
disabled. When accessing status alarm memory, the microprocessor should SET AlmUpdateDsbl so that the microproces-
sor will have uncontested access to this memory.
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MICROPROCESSOR REGISTER DESCRIPTION
XMT_CONF - Transmitter Configuration (iEH)
(i = [0 to 7] and corresponds to the eight different E1 channel numbers)
This register configures a particular E1 channel transmitter’s parameters.
Bit
Name
Label
Type Default
Bit 7
CenterRetFifo A transition from 0 to 1 in this bit sets the two frame-wide retiming elas- W
tic store to its center point (only relevant in retiming mode).
0
0
Bit 6
XmtDjtAisEn Enable/disable hardware AIS generation on the transmit data and clock R/W
outputs (to the LIU) via software (only relevant in dejitter mode). This
bit should be set to 0 before changing the mode from dejitter.
0 - Disable AIS generation because of unlocked PLL
1 - Enable AIS generation because of unlocked PLL
Bit 5
InsBpv
Inserts a code error (Bipolar Violation) in the transmitter HDB3 output
(TPOSD and TNEGD, to the LIU). See CnfBpvIns[1..0] configuration
bits in global register 0FH for the error repetition.
R/W
0
0 - Normal operation
1 - Insert Bpv errors (see register 0FH)
Bit 4
Bit 3
XmtAisFrc
Forces AIS generation on the transmit data and clock outputs (to the
LIU).
R/W
R/W
0
0
0 - Disable
1 - Enable
XmtCrc-4En
Enable/disable G704 CRC-4 monitoring and multiframing in the E1
transmitter (on DTD data input).
0 - Disable. In this case, the E1 transmitter checks the errors in the E1
frameword (every two frames) and counts them in the XmtErrCnt errors
counter. No CRC multiframing
1 - Enable. The chip performs a CRC-4 check on the incoming E1. The
blocks in error is counted in the XmtErrCnt errors counter
Bit
<2:1>
OpCnf <1..0> Each E1 Transmitter can be configured for the following operational
modes.
R/W
0
00 - Passed through mode: no dejitter, no retiming in the transmitter
01 - Dejitter mode
10 - Retiming mode: normal configuration (operates on an E1 framed
signal)
11 - Retiming mode: test configuration (operates on a 2.048 Mbit/s un-
framed signal; in this mode the CRC-4, REBE and remote alarm moni-
toring functions are irrelevant since the incoming data is supposed to be
un-framed.)
(Note: When not in dejitter mode, the High Speed ADPLL reference
Clock is shut down in the transmitter to save power consumption.)
Bit 0
XmtLnCode-
Sel
Line Interface coding (on TPOSD/TNEGD transmit data).
R/W
0
0 - HDB3
1 - NRZ
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SXT6282
XMT_ALRM_INTO - Transmitter Alarm Interrupt 0 (i1H)
(i = [0 to 7] and corresponds to the E1 channel number)
This register identifies the interrupt source for a particular E1 Channel Transmitter. Each of these bits can cause the
chip interrupt pin to become active if enabled via the bits in the Transmit Interrupt Enable Register 0 (i4H).
Bit
Bit
Name
Unused
Label
Type
Default
<7:5>
Bit 4
XmtRmtAlm This bit is set when there is a change in the XmtRmtAlmSt bit
(i3H). It is cleared when status register (i3H) is read.
RO
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
XmtLomf
This bit is set when there is a change in the XmtLomfSt bit (i3H). RO
It is cleared when status register (i3H) is read.
XmtOof
This bit is set when there is a change in the XmtOofSt bit (i3H). It RO
is cleared when status register (i3H) is read.
XmtAisDet
Unused
This bit is set when there is a change in the XmtAisDetSt bit
(i3H). It is cleared when status register (i3H) is read.
RO
XMT_ALRM_INT1 - Transmitter Alarm Interrupt 1(i2H)
(i = [0 to 7] and corresponds to the E1 channel number)
This register identifies the interrupt source for a particular E1 Channel Transmitter. Each of these bits can cause the
chip interrupt pin to become active if enabled via the bits in the Transmit Interrupt Enable Register 1 (i5H).
Bit
Name
Label
Type
RO
Default
Bit 7
XmtPosSlip
Indicates that a positive frame slip has occurred in the retiming
elastic buffer. It is cleared when this register is read.
0
Bit 6
Bit 5
XmtNegSlip
Indicates that a negative frame slip has occurred in the retiming
elastic buffer. It is cleared when this register is read.
RO
0
0
XmtFifofAlm
Indicates that the transmit FIFO has overflowed (depending on the RO
OpCnf bits setting, this can be either the dejitter FIFO, or the
retiming elastic buffer). It is cleared when register is read.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XmtRetNegOvrFlw This bit is set when the RetNegCnt[] retiming positive slip counter RO
rollover occurs. It is cleared when this register is read.
0
0
0
0
0
XmtRetPosOvrFlw This bit is set when the RetPosCnt[] retiming positive slip counter RO
rollover occurs. It is cleared when this register is read.
XmtRbeOvrFlw
This bit is set when the RbeCnt[] Remote Block error counter roll- RO
over occurs. It is cleared when this register is read.
XmtCrc4ErrOvrFlw This bit is set when the Crc4ErrCnt[] error counter rollover occurs. RO
It is cleared when this register is read.
XmtFasErrOvrFlw
This bit is set when the FasErrCnt[] Frame Alignment Signal error RO
counter rollover occurs. It is cleared when this register is read.
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MICROPROCESSOR REGISTER DESCRIPTION
XMT_ALM_STAT - Transmitter Alarm Status (i3H)
(i = [0 to 7] and corresponds to the E1 channel number)
This register gives the present status of each alarm source for a particular E1 channel transmitter.
These registers are associated with the interrupt source registers. Status the interrupt source bits have an associated
status bit. Generally, when an interrupt is being acknowledged, the status bit will be checked to see the present status
of the interrupt-generating source. Overflow event interrupt sources do not have status bits.
Bit
Bit
Name
Unused
Label
Type
Default
<7:5>
Bit 4
XmtRmAlmSt
Present status of Remote Alarm detect on DTDx input data.
0 - No Remote Alarm
RO
0
0
1 - Remote Alarm
Bit 3
XmtLomfSt
Present status of Out Of E1 CRC-4 MultiFrame detect on
DTDx input data.
RO
0 - No LOMF
1 - LOMF
Bit 2
Bit 1
Bit 0
XmtOofSt
XmtAisDetSt
Unused
Present status of Out Of E1 Frame detect on DTDx input data. RO
0
0
0 - No OOF
1 - OOF
Present status of AIS defect detect on DTDx input data.
0 - No AIS defect
RO
1 - AIS defect detected
XMT_ALM_INTE0 - Transmitter Alarm Interrupt Enable 0 (i4H)
(i = [0 to 7] and corresponds to the E1 channel number)
This register can be used to enable an interrupt source for a particular E1 channel interrupt source. The reset default is
disabled (‘0’). All of the interrupt registers in the above section are capable of activating the chip interrupt pin if their
corresponding interrupt enable bits are set to 1.
Bit
Name
Unused
Label
Type
Default
Bit 7:5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XmtRmtAlmIntEn
XmtLomfIntEn
XmtOofIntEn
XmtAisDetIntEn
Unused
R/W
0
0
0
0
R/W
R/W
R/W
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SXT6282
XMT_ALM_INTE1 - Transmitter Alarm Interrupt Enable 1 (i5H)
(i = [0 to 7] and corresponds to the E1 channel number)
This register can be used to enable an interrupt source for a particular E1 channel interrupt source. The reset default is
disabled (‘0’). All of the interrupt registers in the above section are capable of activating the chip interrupt pin if their
corresponding interrupt enable bits are set to 1.
Bit
Name
Label
Type
R/W
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XmtPosSlipEn
0
0
0
0
0
0
0
0
XmtNegSlipEn
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XmtFifofAlmIntEn
XmtRetNOvrFlwEn
XmtRetPOvrFlwEn
XmtRbeOvrFlwEn
XmtCrcErrOvrFlwEn
XmtFasErrOvrFlwEn
XMT_FRMWD_ERC - Transmitter FrameWord Error Counter (i7- i6H)
(i = [0 to 7] and corresponds to the E1 channel number)
(i7H = bits <15:8>, i6H = bits <7:0>
This counter increments each time an errored E1 frameword (FAS and/or NFAS: see global configuration register
0FH: bits CnfFeCnt[1..0]) is detected. A write to the MSByte of the counter (register i7H) causes the entire counter to
be buffered and then cleared. The contents of the buffer can then be read.
Bit
Bit
Name
Label
Type
Default
Unused
XmtFasErrCnt[12:0]
<15:13>
Bit
RO
00H
<12:0>
XMT_BLCK_ERC - Transmitter CRC-4 Block Errors Counter (i9H - i8H)
(i = [0 to 7] and corresponds to the E1 channel number)
(i9H = bits<15:8>, i6H = bits<7:0>
This counter increments each time a CRC-4 Block error is detected. A write to the MSByte of the counter (register
i9H) causes the entire counter to be buffered and then cleared. The contents of the buffer can then be read.
Bit
Name
Label
Type
Default
Bit
<15:10>
Unused
XmtCrc4ErrCnt[9:0]
Bit
RO
00H
<9:0>
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MICROPROCESSOR REGISTER DESCRIPTION
XMT_RMT_ERC - Transmitter Remote CRC-4 Block Errors Counter (iB - iAH)
(i = [0 to 7] and corresponds to the E1 channel number)
(iBH = bits<15:8>, iAH = bits<7:0>)
This counter increments each time a Remote CRC-4 Block error is detected. A write to the MSByte of the counter
(register iBH) causes the entire counter to be buffered and then cleared. The contents of the buffer can then be read.
Bit
Name
Label
Type
Default
Bit < 15:10> Unused
Bit <9:0>
XmtRbeCnt[9:0]
RO
0
XMT_RETMBUF - Transmitter Retiming Buffer Positive & Negative Slip Counters
(iCH)
(i = [0 to 7] and corresponds to the E1 channel number)
A write to the register (register iC) causes both counters to be buffered and then cleared. The contents of the buffer can
then be read.
Bit
Name
Label
Type
Default
Bit <7:4>
RetNegCnt[3:0]
The RetNegCnt[3..0] counter (4 MSB bits
of register iCH) counter increments each
time a negative slip is detected in the retim-
ing elastic buffer (one complete frame is
lost).
RO
0
0
Bit <3:0>
RetPosCnt[3:0]
The RetPosCnt[3..0] counter (4 LSB bits of RO
register iCH) increments each time a posi-
tive slip is detected in the retiming elastic
buffer (one complete frame is repeated).
35 of 56
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SXT6282
XMT_RTMBUF_STAT - Transmitter Retiming Buffer Status (iDH)
(i = [0 to 7] and corresponds to the E1 channel number)
A write to the register (register iDH) causes the Retiming elastic store status bits to be buffered. The contents of the
buffer can then be read.
Bit
Name
Label
Type
Default
Bit <7:6> Unused
Bit <5:0> RetFifoStatus<5:0>
The RetFifoStatus[5..0] bits make an indication
of the content of the Retiming 2 frame-wide elas-
tic store. This value, coded on 6 bits, corresponds
to the difference between the read and the write
pointer of the FIFO and may be used for wander
monitoring and delay calculation.
RO
<0, 1, 0, 1, 0,
0>
If WritePointerValue < ReadPointerValue then
RetFifoStatus[5..0] = 64 + WritePointerValue - ReadPointerValue
else
RetFifoStatus[5..0] = WritePointerValue - ReadPointerValue
RECEIVE SIDE REGISTERS
The registers described in this section are related to the E1 receivers alarm status and configuration.
There are eight E1 receivers in the chip, and 14 registers per E1 receiver. The 4 MSB bits of the register addresses indicate
the E1 channel number (4 MSB bits [from 8 to 15] minus 8 correspond to the E1 channel number: from 0 to 7)
The eight receivers are each capable of generating nine alarm types. Any one of these alarms (if enabled) can cause the
device interrupt pin to become active.
Each E1 receiver alarm has three registers associated with it:
• Interrupt source: This register set will identify the alarm(s) that triggered the interrupt
• Alarm status: This register contains the current status of the alarms. When this register is read, the corresponding
interrupts will be cleared
• Interrupt Enable: This register contains the interrupt enables for all alarms
Status alarms will generate an interrupt both when the alarm changes from inactive to active or active to inactive. The over-
flow alarms generate an interrupt when detected.
Updating the status register is controlled with the AlmUpdsbl bit in global register 0FH. When low, the status registers are
updated once every frame, regardless of the interrupt state. When high, status alarm memory updates will be disabled.
When accessing status alarm memory, the microprocessor should SET AlmUpdateDsbl so that the microprocessor will
have uncontested access to this memory.
36 of 56
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MICROPROCESSOR REGISTER DESCRIPTION
RCV_CONF- Receiver Configuration (jEH)
(j =[8 to F] and corresponds to the eight different E1 channel numbers)
This register configures a particular E1 channel receiver parameters.
Bit
Bit 7
Name
Unused
Label
Type
Default
Bit 6
Bit 5
Bit 4
AutoTestEn
RcvBclkEn
RcvCrc-4En
Enable/disable test pattern generator (the contents of the
sequence is configured in global register 1FH).
R/W
0
0
0
0 - Normal mode (disable autotest)
1 - Enable autotest
Enable/disable hardware switches to blue clock during Loss Of R/W
Signal condition.
0 - Disable hardware clock switch because of LOS
1 - Enable hardware clock switch because of LOS
Enable/disable CRC-4 monitoring and multiframing in the E1 R/W
receiver (on RPOSD/RNEGD data input from the LIU).
0 - Disable. In this case, the receiver checks the errors in the
receive E1 frameword (every two frames) and counts them in
the RxErrCnt error counter. CRC multiframing is also disabled
1 - Enable. The chip performs a CRC-4 check on the incoming
E1. The blocks in error are counted in the RxErrCnt errors
counter. CRC multiframing is also enabled.
Bit 3
Bit 2
RcvLosFlt
RcvAisFrc
Configure LOS alarm filtering (on RLOS input signal).
0 - No filtering
R/W
R/W
0
0
1 - LOS filtering. The LOS condition must be maintained for
128 clock cycles
Force AIS generation from the receive data and clock inputs
(from the LIU) to the receiver output (to the multiplexer) via
software.
0 - Disable
1 - Enable
Bit 1
Bit 0
RcvAisEn
Enable/disable hardware AIS generation from the receive data R/W
and clock inputs (from the LIU) to the receiver output (to the
PDH/SDH multiplexer).
0
0
0 - Disable AIS generation because of LOS
1 - Enable AIS generation because of LOS
RcvLnCodeSel Line interface coding (on RPOSD/RNEGD receive data)
R/W
0 - HDB3
1 - NRZ
37 of 56
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SXT6282
RCV_ALRM_INT0 - Receiver Alarm Interrupt 0 (j1H)
(j =[8 to F] and corresponds to the E1 channel number)
This register identifies the interrupt source for a particular E1 channel receiver. Each of these bits can cause the chip
interrupt pin to become active if enabled via the bits in the Receive Interrupt Enable Register j4H.
Bit
Bit
Name
Unused
Label
Type
Default
<7:5>
Bit 4
RcvRmtAlm This bit is set when there is a change in the RcvRmAlmSt Receive RO
0
Remote Alarm bit (j3H). It is cleared when status register (j3H) is
read.
Bit 3
Bit 2
Bit 1
Bit 0
RcvLomf
RcvOof
RcvAisDet
Los
This bit is set when there is a change in the RcvLomfSt bit (j3H). RO
It is cleared when status register (j3H) is read.
0
0
0
0
This bit is set when there is a change in the RcvOofSt bit (j3H). It RO
is cleared when status register (j3H) is read.
This bit is set when there is a change in the RcvAisDetSt bit (j3H). RO
It is cleared when status register (j3H) is read.
This bit is set when there is a change in the LosSt bit (j3H). It is
cleared when status register (i3H) is read.
RO
RCV_ALRM_INT1 - Receiver Alarm Interrupt 1 (j2H)
(j =[8 to F] and corresponds to the E1 channel number)
This register identifies the interrupt source for a particular E1 channel receiver. Each of these bits can cause the chip
interrupt pin to become active if enabled via the bits in the Receive Interrupt Enable Register j5H.
Bit
Bit
Name
Unused
Label
Type
Default
<7:4>
Bit 3
BpvOvrFlw
This bit is set when the BpvCnt[] Code error counter rollover
occurs. It is cleared when this register is read.
RO
RO
RO
0
0
0
Bit 2
Bit 1
RcvRbeOvrFlw
This bit is set when the RbeCnt[] Remote Block error counter
rollover occurs. It is cleared when this register is read.
RcvCrc4ErrOvrFlw This bit is set when the RcvCrc4ErrCnt[] Receive CRC-4 block
error counter rollover occurs. It is cleared when this register is
read.
Bit 0
RcvFasErrOvrFlw
This bit is set when the RcvFasErrCnt[] Receive Frame Align-
ment Signal error counter rollover occurs. It is cleared when this
register is read.
RO
0
38 of 56
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MICROPROCESSOR REGISTER DESCRIPTION
REC_ALRMS - Receiver Alarm Status (j3H)
(j =[8 to F] and corresponds to the E1 channel number)
This register gives the present status of each alarm source for a particular E1 channel receiver.
These registers are associated with the interrupt source registers. Status interrupt source bits have an associated status
bit. Generally, when an interrupt is being acknowledged, the status bit will be checked to see the present status of the
interrupt-generating source. Overflow interrupt sources do not have status bits associated with them since the counter
value fulfills this purpose.
Bit
Bit
Name
Unused
Label
Type
Default
<7:5>
Bit 4
RcvRmtAlmSt Present status of Receive Remote Alarm detect.
0 - No Remote Alarm
RO
0
0
0
0
1 - Remote Alarm
Bit 3
Bit 2
Bit 1
RcvLomfSt
RcvOofSt
Present status of Out Of E1 CRC-4 MultiFrame detect.
0 - No LOMF
1 - LOMF
RO
RO
RO
Present status of Out Of E1 Frame detect.
0 - No OOF
1 - OOF
RcvAisDetSt
Present status of AIS defect detect on the incoming E1 data
(ITU G.775).
0 - No AIS
1 - AIS defect detected
Bit 0
LosSt
Present status of Loss of Signal detect.
RO
0
0 - No LOS
1 - LOS
RCE_ALM_INTE0 - Receiver Alarm Interrupt Enable Register 0 (j4H)
(j =[8 to F] and corresponds to the E1 channel number)
This register can be used to enable an interrupt source for a particular E1 channel. The reset default is not enabled (‘0’).
All of the interrupt registers in the above section are capable of activating the chip interrupt pin if their corresponding
interrupt enable bits are set to 1.
Bit
Name
Label
Type
Default
Bit <7:5>
Bit 4
Unused
RcvRmtAlmEn
RcvLomfIntEn
RcvOofIntEn
RcvAisDetIntEn
LosIntEn
R/W
0
0
0
0
0
Bit 3
R/W
R/W
R/W
R/W
Bit 2
Bit 1
Bit 0
39 of 56
ꢀ
SXT6282
RCV_ALM_INTE1 - Receiver Alarm Interrupt Enable Register 1 (j5H)
(j =[8 to F] and corresponds to the E1 channel number)
This register can be used to enable an interrupt source for a particular E1 channel. The reset default is disabled (‘0’).
All of the interrupt registers in the above section are capable of activating the chip interrupt pin if their corresponding
interrupt enable bits are set to 1.
Bit
Bit
Name
Unused
Label
Type
Default
<7:4>
Bit 3
Bit 2
Bit 1
Bit 0
BpvOvrFlwIntEn
R/W
0
0
0
0
RcvRbeOvrFlwEn
RcvCrcOvrFlwIntEn
RcvFasErrOvrFlwEn
R/W
R/W
R/W
RCV_FRMWD_ERC - Receiver FrameWord Error Counter (j7 - j6H)
(j =[8 to F] and corresponds to the E1 channel number)
(j7H = bits <15:8>, j6H = bits <7:0>)
This counter increments each time an errored E1 frameword (FAS and/or NFAS: see global configuration register
0FH: bits CnfFeCnt[1..0]) is detected. A write to the MSByte of the counter (Register j7H) causes the entire counter
to be buffered and then cleared. The contents of the buffer can then be read.
Bit
Name
Label
Type
Default
Bit
<15:13>
Bit <12:0> RcvFasErrCnt[12:0]
Unused
RO
0
RCV_BLCK_ERC - Receiver CRC-4 Block Error Counter (j9 - j8H)
(j =[8 to F] and corresponds to the E1 channel number)
(j9H = bits<15:8>, j8H = bits <7:0>
This counter increments each time either a CRC Block error event is selected. A write to the MSByte of the counter
(Register j9H) causes the entire counter to be buffered and then cleared. The contents of the buffer can then be read.
Bit
Name
Label
Type
Default
Bit
<15:10>
Unused
RcvCrc4ErrCnt[9:0]
Bit <9:0>
RO
0
40 of 56
ꢀ
MICROPROCESSOR REGISTER DESCRIPTION
RCV_RMT_BLCK_ERC - Receiver Remote CRC-4 Block Error Counter (jB - jAH)
(j =[8 to F] and corresponds to the E1 channel number)
(jBH = bits<15:8>, jAH = bits<7:0>)
This counter increments each time a remote CRC-4 block error is detected. A write to the MSByte of the counter (Reg-
ister jBH) causes the entire counter to be buffered and then cleared. The contents of the buffer can then be read.
Bit
Name
Label
Type
Default
Bit <15:10> Unused
Bit <9:0>
RcvRbeCnt[9:0]
RO
0
RCV_CD_ERC - Receiver Code Errors Counter (jDH)
(j =[8 to F] and corresponds to the E1 channel number)
(jDH = bits <15:8>, jCH = bits<7:0>)
This counter increments each time a code error (Bipolar Violation) is detected, according to cnfBpvDet[1,0] configu-
ration bits in global register 0FH. A write to the MSByte of the counter (register jDH) causes the entire counter to be
buffered and then cleared. The contents of the buffer can then be read.
Bit
Name
Label
Type
Default
Bit <15:0> BpvCnt[15:0]
RO
0
41 of 56
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SXT6282
TEST SPECIFICATIONS
Table 4: Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Supply Voltage
VDD
VIN
3.6
5.5
V
V
DC Voltage on any pin1
-1.0
Ambient operating temperature
Storage temperature range
TOP
TST
-40
-65
+85
C
C
+150
1. Minimum voltage is -0.6V dc which may undershoot to -1.0 V for pulses of less than 20 ns
CAUTION
Exceeding these values may cause permanent damage.
Functional operation under these conditions is not implied
Exposure to maximum rating conditions for extended periods may affect device reliability
Table 5: Operating Conditions
Typ1
Parameter
Symbol
Min
Max
Unit
Recommended Operating Temperature
Supply Voltage - I/O Ring and Core
TOP
VDDr
IDDrja
-40
3.0
-
-
+85
3.6
-
C
V
3.3
65
Supply Current 3 (8 channels in jitter attenuation mode)
Supply Current - Core 3 (8 channels in retiming mode)
mA
IDDrret
-
15
-
mA
1. Typical values are at 25C and nominal voltage and are provided for design aid only; not guaranteed nor subject to production testing
2. Voltages with respect to ground unless otherwise specified
3. Core +I/O (outputs loaded with 30pF).
Table 6: 5 V Tolerant Digital I/O Characteristics
Parameter
Input Low Voltage
Symbol
Min
Typ
Max
Units
Test Conditions
VIL
VIH
VT
0.5
5.5
V
V
Input High Voltage
2.0
5.0
1.4
Switching Threshold
Input Leakage High
Output Low Voltage
Output High Voltage
Output Leakage (no pull up)
V
VDD=3.3V, 25C
VIN=VDD=3.6V
VDD=3.0V
IIH
5
uA
V
VOL
VOH
IOZ
0.4
VDD-0.6V
-10
V
10
uA
Vin=VDD or VSS, VDD=
3.6V, No pull up
1. All values applicable over recommended Voltage and Temperature operating range unless otherwise noted
42 of 56
ꢀ
TEST SPECIFICATIONS
Figure 5: E1 outputs, transmitted to the LIUs, Timing
DRETCKREF
tTCKOpd
tTCKOpd
TCLKi
tTDOpd
tTDOpd
TPOSDi
TNEGDi
DRAWING
1 - 10/21/98
Global Conf. Register @ 0xAF / bit #6 :
CnfTxClkOut = 1
CnfTxClkOut = 0
Table 7: E1 outputs, transmitted to the LIUs, Timing Parameters
Parameter
Symbol
Min
3
Typ
Max
11
Unit
ns
ns
2
DRETCKREF rising edge to TCLKi rising/falling edge
tTCKOpd
2
TCLKi rising/falling edge to TPOSDi and TNEGDi1
tTDOpd
1
8
1. i = [0 to 7] and corresponds to the eight different E1 channel numbers
2. Considering outputs with a 25pF load
Figure 6: E1 inputs, received from the LIUs, Timing
RCLKi
tRDIsu
tRDIh
tRDIsu
tRDIh
RPOSDi
RNEGDi
GIBRALTAR DS R
_ _ 1.0.FM - 6/15/98
Global Conf. Register @ AFH / bit #5 :
CnfRxClkIn = 1
CnfRxClkIn = 0
Table 8: E1 inputs, received from the LIUs,Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
RPOSDi and RNEGDi setup time
to RCLKi rising/falling edge
tRDIsu
1
ns
ns
RPOSDi and RNEGDi hold time
from RCLKi rising/falling edge
tRDIh
4
1. i = [0 to 7] and corresponds to the eight different E1 channel numbers
43 of 56
ꢀ
SXT6282
Figure 7: E1 inputs, received from the demultiplexer, Timing
DTCi
tRDIsu
tRDIh
tRDIsu
tRDIh
DTDi
AC_TRANSMIT _FMAP .VSD - 2/19/98
Global Conf. Register @ 0xAF / bit #7 :
CnfTxClkIn = 1
CnfTxClkIn = 0
Table 9: E1 inputs, received from the demultiplexer, Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
ns
ns
DTDi setup time to DTCi falling/rising edge
DTDi hold time from DTCi falling/rising edge
tRDIsu
tRDIh
1
3
1. i = [0 to 7] and corresponds to the eight different E1 channel numbers
2. Considering outputs with a 25pF load
Figure 8: E1 outputs, transmitted to the multiplexer, Timing
RCLKi (with CnfRxClkIn = 1
Conf. Register @ 0xAF / bit #5)
RCLKi (with CnfRxClkIn = 0
Conf. Register @ 0xAF /bit #5)
tRCKOpd
tRCKOpd
MTCi
MTDi
tRDOpd
tRDOpd
GIBRALTAR
DS R
_ _ 1.0.FM - 6/15/98
Global Conf. Register @ AFH / bit #4 :
CnfRxClkOut = 1
CnfRxClkOut = 0
Table 10: E1 outputs, transmitted to the multiplexer, Timing
Parameter
Symbol
Min
Typ
Max
Unit
RCLKi rising/falling edge to MTCi rising/falling edge
MTCi falling/rising edge to MTDi
tRCKOpd
tRDOpd
3
1
12
7
ns
ns
1. i = [0 to 7] and corresponds to the eight different E1 channel numbers
2. Considering outputs with a 25pF load
44 of 56
ꢀ
TEST SPECIFICATIONS
Figure 9: Microprocessor Read Timing
MicroProcessor Read Timing (Intel Mode)
MicroProcessor Read Timing (Motorola Mode)
tSAR
tSAR
A<7:0>
A<7:0>
tHAR
tHAR
tSALR
tSALR
tVL
tHALR
tHALR
tVL
ASB
ASB
tSCR
tHCR
tSLR
CSB
R W B
tSLR
tSRWB
tHRWB
tVRD
RDB
INT
CS
tINTH
tSCR
tHCR
E
tDDR
tZDR
tVRD
tINTH
INT
DATA<7:0>
tDDR
tZDR
tADR
tAAC
tAAC
tHDR
DATA<7:0>
tADR
tHDR
tAAC
tAAC
Table 11: Microprocessor Data Read Timing Parameters (considering outputs with a 50pF
load)
Parameter
Symbol
Min
Typ
Max
Unit
A<7:0> setup time to read cycle end
A<7:0> hold time from inactive read
tSAR
5
1
ns
ns
1
tHAR
2
A<7:0> setup time to latch
A<7:0> hold time from latch
Valid latch pulse width
4
2
5
6
ns
ns
ns
ns
tSALR
2
tHALR
2
tVL
2
AS rising edge to read cycle end setup
tSLR
RWB setup to active read
RWB hold from inactive read
CSB setup to active read
CSB hold from inactive read
tSRWB
tHRWB
tSCR
1
1
1
1
ns
ns
ns
ns
tHCR
1. For non-multiplexed Address and Data bus (ASB tied high)
2. For multiplexed Address and Data bus (ASB used as address latch enable)
3. T is the minimum cycle time of either DTCi, either, DRETCKREF, or MTCi (typically 488 ns for E1)
45 of 56
ꢀ
SXT6282
Table 11: Microprocessor Data Read Timing Parameters (considering outputs with a 50pF
load)
Parameter
Symbol
Min
Typ
Max
Unit
DATA<7:0> access time from valid address
(or ASB whichever comes last for muxed AD bus)
DATA<7:0> bus driven from active read
tAAC
20
ns
tDDR
tADR
tHDR
tZDR
tVRD
5
4
ns
ns
ns
ns
ns
ns
DATA<7:0> access time from active read
DATA<7:0> hold from inactive read
DATA<7:0> High impedance from inactive read
Valid read pulse width
15
13
20
3
Inactive read to inactive INT (due to reset on read
feature)
T + 6
2*T + 21
tINTH
1. For non-multiplexed Address and Data bus (ASB tied high)
2. For multiplexed Address and Data bus (ASB used as address latch enable)
3. T is the minimum cycle time of either DTCi, either, DRETCKREF, or MTCi (typically 488 ns for E1)
Figure 10: Microprocessor Write Timing
MicroProcessor Write Timing (Intel Mode)
MicroProcessor Write Timing (Motorola Mode)
tS A W
tS A W
A<7:0>
A<7:0>
tH A W
tH A W
tS A L W
tS A L W
tH A L W
tH A L W
tVL
tVL
ASB
CSB
ASB
tS C W
tH C W
tS L W
tH R W B
R W B
tS R W B
tS L W
tH C W
tS C W
W R B
INT
CSB
E
tINTH
tV W R
tV W R
tS D W
tINTH
tH D W
INT
DATA<7:0>
tS D W
tH D W
DATA<7:0>
46 of 56
ꢀ
TEST SPECIFICATIONS
Table 12: Microprocessor Data Write Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
A<7:0> setup time to write cycle end
A<7:0> hold time from inactive write
tSAW
6
2
ns
ns
1
tHAW
2
A<7:0> setup time to latch
4
2
5
7
ns
ns
ns
ns
tSALW
2
A<7:0> hold time from latch
Valid latch pulse width
tHALW
2
tVL
2
ASB rising edge to write cycle end setup
tSLW
RWB setup to active write
tSRWB
tHRWB
tSCW
0
ns
ns
ns
ns
ns
ns
ns
ns
RWB hold from inactive write
CSB setup to active write
1
1
CSB hold from inactive write
DATA<7:0> setup to inactive write
DATA<7:0> hold from inactive write
Valid write pulse width
tHCW
tSDW
tHDW
tVWR
1
2
2
20
T + 6
3
Inactive write to inactive INT (due to interrupt
masking)
2*T + 21
tVWR
1. For non-multiplexed Address and Data bus (AS tied high)
2. For multiplexed Address and Data bus (AS used as address latch enable)
3. T is the minimum cycle time of either DTCi, either, DRETCKREF, or MTCi (typically 488 ns for E1)
47 of 56
ꢀ
SXT6282
TESTABILITY
The SXT6282 provides a method for enhancing testability:
IEEE1149.1 Boundary Scan (JTAG) is used for testing of
the interconnect.
.
Table 13: JTAG Pin Description
Pin #
Name
I/O
Function
IEEE 1149.1 BOUNDARY SCAN
DESCRIPTION
103
JTMS_P
I
Test Mode Select:
Determines state of
TAP Controller. Pull
up 48k
The boundary scan circuitry allows the user to test the
interconnection between the SXT6282 and the circuit
board. The boundary scan port consists of 5 pins as shown
in Table 13. The heart of the scan circuitry is the Test
Access Port controller (TAP). The TAP controller is a 16
state machine that controls the function of the boundary
scan circuitry. Inputs of the TAP controller are the Test
Mode Select (JTMS) and the Test Clock (JTCK) signals.
Data and instructions are shifted into the SXT6282 through
the Test Data In pin (JTDI). Data and instructions are
shifted out through the Test Data Out pin (JTDO). An asyn-
chronous reset pin (JTRS) allows to reset the boundary
scan circuitry
104
102
JTCK_P
JTRS_P
I
I
Test Clock: Clock for
all boundary scan
circuitry
Test Reset: Active
low asynchronous
signal that causes
the TAP controller to
reset. Pull down 35k
101
100
JTDI_P
I
Test Data In: Input
signal used to shift in
instructions and
data. Pull up 48k
JTDO_P
O
Test data Out: Output
signal used to shift
out instructions and
data.
Figure 11: Test Access Port
Boundary Scan
Bypass Register
JTDI
Device ID Register
Instruction Register
JTDO
JTMS
JTCK
JTRS
Test Access Port Controller
48 of 56
ꢀ
TESTABILITY
shifts while this instruction is active. All BSR cells
capture data present at their inputs on the rising edge
of JTCK during the CAPTURE-DR state. No action is
taken during the UPDATE-DR state.
INSTRUCTION REGISTER AND
DEFINITIONS
The SXT6282 supports the following instructions
IEEE1149.1: EXTEST, SAMPLE/PRELOAD, BYPASS
and IDCODE. Instructions are shifted into the instruction
register during the SHIFT-IR state and become active upon
exiting the UPDATE-IR state. The instruction register def-
inition is shown in the following figure.
BYPASS (‘b11)
This instruction allows a device to be effectively
removed from the scan chain by inserting a one-bit
shift register stage between TDI and TDO during data
shifts. When the instruction is active, the test logic has
no impact upon the system logic performing its system
function. When selected, the shift-register is set to a
logic zero on the rising edge of the JTCK during the
CAPTURE-DR state.
TDI
TDO
IDCODE (‘b10)
MSB
LSB
This instruction allows the reading of component types
via the scan chain. During this instruction, the 32-bit
Device Identification Register (ID-Register) is placed
between TDI and TDO. The ID Register captures a
fixed value of (‘h 1188A0FD) on the rising edge of
JTCK during the CAPTURE-DR state. The Device
Identification Register contains the following informa-
tion: Manufacturer ID: ‘d126; Design Part Number: ‘d
SXT6282; Design Version Number: ‘d1.
EXTEST (‘b00)
This instruction allows the testing of circuitry external
to the package, typically the board interconnect, to be
tested. While the instruction is active, the boundary
scan register is connected between TDI and TDO for
any data shifts. Boundary scan cells at the output pins
are used to apply test stimuli, while those at input pins
capture test results. Signals present on input pins are
loaded into the BSR inputs cells on the rising edge of
JTCK during CAPTURE-DR state. BSR contains are
shifted one bit location on each rising edge of JTCK
during the SHIFT-DR state. BSR output cell contents
appear at output pins on the falling edge of JTCK dur-
ing the UPDATE-IR state.
BOUNDARY SCAN REGISTER
The Boundary Scan Register is a 126 bit shift register,
made of two types of 4 types of shift-register cells. Accord-
ing to the Boundary Scan Description Language (BSDL)
JTAG_BSRINBOTH,
JTAG_BSRCTL
JTAG_BSROUTBOTH
designated
and
TYPE2,
are
JTAG_BSRINCLKOBS are designated TYPE1.
Description
• Length: 126 BSR cells
One test cycle is:
• JTCK_P Jtag Test Clock
• JTDI_P Jtag Test Data Input
1. A test stimuli pattern is shifted into the BSR during
SHIFT-DR state
• JTDO_C Jtag Test Data Output Control enable
• JTDO_P Jtag Test Data Output
• JTMS_P Jtag Test Mode Select
• JTRS_P Jtag Test Reset
2. This pattern is applied to output pins during the
UPDATE-DR state
3. The response is loaded into input BSR cells during the
CAPTURE-DR state
4. The results are shifted out and next test stimuli shifted
in to the BSR
SAMPLE/PRELOAD (‘b01)
This instruction allows a snapshot of the normal oper-
ation of the SXT6282. The boundary scan register is
connected between the TDI and TDO for any data
49 of 56
ꢀ
SXT6282
Figure 12: Boundary Scan Cell
Data in
Data out
Scan out
Scan in
Shift dr
Clock dr
TYPE 1
Scan out
Data out
Data in
Scan in
Shift dr
Clock dr
Update dr
Mode
TYPE 2
Table 14: Boundary Scan Order
dpllckref
mcutype
scanen
scantest
dretckref
oen
Clock
Data
Data
Data
Clock
Data
Data
Data
Data
Data
Data
1
JTAG_BSRINCLKOBS
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINCLKOBS
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
2
3
4
5
6
dtc[7]
7
dtd[7]
8
mtd[7]
mtc[7]
mtc[6]
9
10
11
oen_c
oen_c
50 of 56
ꢀ
TESTABILITY
Table 14: Boundary Scan Order
mtd[6]
dtd[6]
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
oen_c
dtc[6]
dtc[5]
dtd[5]
mtd[5]
mtc[5]
mtc[4]
mtd[4]
dtd[4]
oen_c
oen_c
oen_c
oen_c
dtc[4]
dtc[3]
dtd[3]
mtd[3]
mtc[3]
mtc[2]
mtd[2]
dtd[2]
oen_c
oen_c
oen_c
oen_c
dtc[2]
dtc[1]
dtd[1]
mtd[1]
mtc[1]
mtc[0]
mtd[0]
dtd[0]
oen_c
oen_c
oen_c
oen_c
dtc[0]
data/i[7]
data/o[7]
data/i[6]
data/o[6]
data/i[5]
data/o[5]
data/i[4]
data/o[4]
data/i[3]
data/o[3]
rdb_c
rdb_c
rdb_c
rdb_c
rdb_c
51 of 56
ꢀ
SXT6282
Table 14: Boundary Scan Order
data/i[2]
data/o[2]
data/i[1]
data/o[1]
data/i[0]
data/o[0]
oen_c
rdb_c
a[7]
Data
Data
Data
Data
Data
Data
Enble
Enble
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Enble
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSRCTL
rdb_c
rdb_c
rdb_c
JTAG_BSRCTL
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRCTL
a[6]
a[5]
a[4]
a[3]
a[2]
a[1]
a[0]
csb
asb
wrb
rdb
reset
int
int
rlos[0]
rnegd[0]
rposd[0]
rclk[0]
tnegd[0]
tposd[0]
tclk[0]
rlos[1]
rnegd[1]
rposd[1]
rclk[1]
tnegd[1]
tposd[1]
tclk[1]
rlos[3]
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
oen_c
oen_c
oen_c
oen_c
oen_c
oen_c
52 of 56
ꢀ
TESTABILITY
Table 14: Boundary Scan Order
rnegd[3]
rposd[3]
rclk[3]
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
86
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
JTAG_BSROUTBOTH
87
88
tnegd[3]
tposd[3]
tclk[3]
89
oen_c
oen_c
oen_c
90
91
rlos[2]
92
rnegd[2]
rposd[2]
rclk[2]
93
94
95
tnegd[2]
tposd[2]
tclk[2]
96
oen_c
oen_c
oen_c
oen_c
oen_c
oen_c
97
98
tclk[5]
99
tposd[5]
tnegd[5]
rclk[5]
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
rposd[5]
rnegd[5]
rlos[5]
tclk[4]
oen_c
oen_c
oen_c
tposd[4]
tnegd[4]
rclk[4]
rposd[4]
rnegd[4]
rlos[4]
tclk[6]
oen_c
oen_c
oen_c
tposd[6]
tnegd[6]
rclk[6]
rposd[6]
rnegd[6]
rlos[6]
tclk[7]
oen_c
oen_c
oen_c
tposd[7]
tnegd[7]
53 of 56
ꢀ
SXT6282
Table 14: Boundary Scan Order
rclk[7]
Data
Data
Data
Data
123
124
125
126
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
JTAG_BSRINBOTH
rposd[7]
rnegd[7]
rlos[7]
GLOSSARY
AIS
Alarm Indication Signal
E-1 Frame Alignment Signal
First in/First Out Memory
FAS
FIFO
MFAS
NFAS
PDH
SDH
E1 CRC-4 Multiframe Alignment Signal
E1 Non-Frame Alignment Signal
Synchronous Digital Hierarchy
Synchronous Digital Hierarchy
54 of 56
ꢀ
PACKAGE INFORMATION
PACKAGE INFORMATION
D
NOTE: All dimensions in millimeters.
b
D/2
e
E/2
E1/2
e/2
E1
E
M
0
DEG. MIN.
A2
0.08
/ 0.20 R.
D1/2
A1
D1
0.08 R. MIN.
0.25
L
A
0
- 7 DEG.
1.00
REF.
144-pin L Quad Flat Pack package (1.40 mm body thickness)
Millimeters
Dimension1
Minimum
Nominal
Maximum
A
A1
A2
b
-
-
1.60
0.15
1.45
0.27
0.05
1.35
0.17
0.10
1.40
0.22
D
22.00 B.S.C.
20.00 B.S.C.
22.00 B.S.C.
20.00 B.S.C.
0.50 B.S.C.
0.60
D1
E
E1
e
L
0.45
0.14
0.75
-
M
-
1. See JEDEC Publication for additional specifications.
55 of 56
ꢀ
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Revision
Date
Status
0.0
1.0
1.1
03/98
06/98
09/98
Advance Information, limited distribution
Product Release
Remove 5V VDDP pin reference and associated DC characteristics, other minor changes
The products listed in this publication are covered by one or more of the following patents. Additional patents pending.
5,008,637; 5,028,888; 5,057,794; 5,059,924; 5,068,628; 5,077,529; 5,084,866; 5,148,427; 5,153,875; 5,157,690; 5,159,291; 5,162,746; 5,166,635; 5,181,228;
5,204,880; 5,249,183; 5,257,286; 5,267,269; 5,267,746; 5,461,661; 5,493,243; 5,534,863; 5,574,726; 5,581,585; 5,608,341; 5,671,249; 5,666,129; 5,701,099
Copyright © 1998 Level One Communications, Inc. Specifications subject to change without notice.
All rights reserved. Printed in the United States of America.
PDS-6282-R1.1-9/98
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