TE28F160C2TA100 [INTEL]
Flash, 1MX16, 100ns, PDSO48, 12 X 20 MM, TSOP-48;![TE28F160C2TA100](http://pdffile.icpdf.com/pdf2/p00243/img/icpdf/TE28F160C2TA_1471905_icpdf.jpg)
型号: | TE28F160C2TA100 |
厂家: | ![]() |
描述: | Flash, 1MX16, 100ns, PDSO48, 12 X 20 MM, TSOP-48 光电二极管 内存集成电路 闪存 |
文件: | 总56页 (文件大小:271K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
![](http://public.icpdf.com/style/img/ads.jpg)
PRELIMINARY
E
2.4 VOLT ADVANCED+ BOOT BLOCK
FLASH MEMORY
28F800C2, 28F160C2 (x16)
Flexible SmartVoltage Technology
Improved 12 V Production
Programming
2.4 V–3.0 V Read/Program/Erase
12 V for Fast Production
Programming
Faster Production Programming
No Additional System Logic
High Performance
128-bit Protection Register
64-bit Unique Device Identifier
64-bit User Programmable OTP
Cells
2.4 V–3.0 V: 100 ns Max Access
Time
2.7 V–3.0 V: 90 ns Max Access Time
Optimized Architecture for Code Plus
Data Storage
Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles
Eight 4- Kword Blocks,
Top or Bottom Locations
Supports Flash Data Integrator
Software
Up to Sixty-Three 32-Kword Blocks
Fast Program Suspend Capability
Fast Erase Suspend Capability
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., voice)
Flexible Block Locking
Lock/Unlock Any Block
Full Protection on Power-Up
WP# Pin for Hardware Block
Protection
Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
VPP = GND Option
VCC Lockout Voltage
Cross-Compatible Command Support
Intel Basic Command Set
Low Power Consumption
8 mA Typical Read Power
10 µA Typical Standby Power with
Automatic Power Savings Feature
Common Flash Interface
x16 I/O for Various Applications
48-Ball µBGA* Package
Extended Temperature Operation
–40 °C to +85 °C
48-Lead TSOP Package
0.25 µ ETOX™ VI Flash Technology
The 0.25 µm 2.4 Volt Advanced+ Boot Block flash memory, manufactured on Intel’s latest 0.25 µ technology,
represents a feature-rich solution for low power applications. These flash memory devices incorporate low
voltage capability (2.4 V read, program and erase) with high-speed, low-power operation. Flexible block
locking allows any block to be independently locked or unlocked. A 128-bit protection register enhances
customers’ ability to develop secure systems. Add to this the Intel-developed Flash Data Integrator (FDI)
software and you have a cost-effective, flexible, monolithic code plus data storage solution. 2.4 Volt
Advanced+ Boot Block products will be available in 48-lead TSOP and 48-ball µBGA* packages. All devices
have a 16-bit data bus. Additional information on this product family can be obtained by accessing Intel’s
Flash website: http://www.intel.com/design/flash.
June 1999
Order Number: 290647-002
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F800C2 and 28F160C2 may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s website at http:\\www.intel.com
COPYRIGHT © INTEL CORPORATION 1998, 1999
CG-041493
*Other brands and names are the property of their respective owners.
E
28F800C2, 28F160C2
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION..............................................5
3.4 128-Bit Protection Register........................ 20
3.4.1 Reading the Protection Register ......... 20
3.4.2 Programming the Protection Register . 20
3.4.3 Locking the Protection Register .......... 21
3.5 VPP Program and Erase Voltages.............. 21
1.1 2.4 Volt Advanced+ Boot Block Flash
Memory Enhancements...............................5
1.2 Product Overview.........................................6
2.0 PRODUCT DESCRIPTION..............................6
2.1 Package Pinouts ..........................................6
2.2 Block Organization .......................................9
2.2.1 Parameter Blocks ..................................9
2.2.2 Main Blocks...........................................9
3.5.1 Improved 12 V Operation for Production
Programming..................................... 21
3.5.2 VPP ≤ VPPLK for Complete Protection .. 21
3.6 Power Consumption .................................. 22
3.6.1 Active Power (Program/Erase/Read) .. 22
3.6.2 Automatic Power Savings (APS)......... 22
3.6.3 Standby Power ................................... 22
3.6.4 Deep Power-Down Mode.................... 23
3.7 Power-Up/Down Operation........................ 23
3.7.1 RP# Connected to System Reset ....... 23
3.7.2 VCC, VPP and RP# Transitions ............ 23
3.8 Power Supply Decoupling.......................... 23
3.0 PRINCIPLES OF OPERATION .....................10
3.1 Bus Operation ............................................10
3.1.1 Read....................................................10
3.1.2 Output Disable.....................................10
3.1.3 Standby ...............................................10
3.1.4 Reset...................................................11
3.1.5 Write....................................................11
3.2 Modes of Operation....................................11
3.2.1 Read Array ..........................................11
3.2.2 Read Configuration..............................12
3.2.3 Read Status Register...........................12
3.2.3.1 Clearing the Status Register .........12
3.2.4 Read Query.........................................12
3.2.5 Program Mode.....................................13
4.0 ELECTRICAL SPECIFICATIONS................. 24
4.1 Absolute Maximum Ratings....................... 24
4.2 Operating Conditions................................. 24
4.3 Capacitance .............................................. 25
4.4 DC Characteristics..................................... 25
4.5 AC Characteristics—Read Operations—
Extended Temperature............................. 29
3.2.5.1 Suspending and Resuming
Program.......................................13
4.6 AC Characteristics—Write Operations—
Extended Temperature............................. 31
3.2.6 Erase Mode.........................................13
3.2.6.1 Suspending and Resuming Erase.14
3.3 Flexible Block Locking................................18
3.3.1 Locking Operation ...............................18
3.3.2 Locked State .......................................18
3.3.3 Unlocked State ....................................18
3.3.4 Lock-Down State .................................18
3.3.5 Reading a Block’s Lock Status ............19
4.7 Erase and Program Timings...................... 32
4.8 Reset Operations....................................... 34
5.0 ORDERING INFORMATION......................... 35
6.0 ADDITIONAL INFORMATION...................... 36
APPENDIX A: WSM Current/Next States ......... 37
APPENDIX B: Program/Erase Flowcharts ....... 39
3.3.6 Locking Operations during Erase
Suspend.............................................19
APPENDIX C: Common Flash Interface Query
Structure..................................................... 45
3.3.7 Status Register Error Checking ...........19
3
PRELIMINARY
28F800C2, 28F160C2
E
APPENDIX D: Architecture Block Diagram ......52
APPENDIX F: Device ID Table .......................... 55
APPENDIX E: Word-Wide Memory Map
APPENDIX G: Protection Register
Diagrams .....................................................53
Addressing ................................................. 56
REVISION HISTORY
Date of
Revision
Version
Description
11/17/98
06/11/99
-001
-002
Original version
Removed all references to x8 configurations
Removed 32-Mbit offering
Appendix C, CFI Query Structure, tables updated
4
PRELIMINARY
E
28F800C2, 28F160C2
1.0 INTRODUCTION
1.1
2.4 Volt Advanced+ Boot Block
Flash Memory Enhancements
This document contains the specifications for the
2.4 Volt Advanced+ Boot Block flash memory
family. These flash memories add features which
can be used to enhance the security of systems:
instant block locking and a protection register.
The 2.4 Volt Advanced+ Boot Block flash memory
features:
•
•
•
Zero-latency, flexible block locking
128-bit Protection Register
Throughout this document, the term “2.4 V” refers
to the full voltage range 2.4 V–3.0 V (except where
noted otherwise) and “VPP = 12 V” refers to 12 V
±5%. Sections 1 and 2 provide an overview of the
flash memory family including applications, pinouts,
pin descriptions and memory organization. Section
3 describes the operation of these products. Finally,
Section 4 contains the operating specifications.
Simple system implementation for 12 V
production programming with 2.4
programming
V in-field
•
•
•
Ultra-low power operation at 2.4 V
Minimum 100,000 block erase cycles
Common Flash Interface for software query of
device specs and features
Table 1. 2.4 Volt Advanced+ Boot Block Feature Summary
Feature
VCC Operating Voltage
VPP Voltage
8 Mbit(1), 16 Mbit
Reference
Table 8
2.4 V – 3.0 V
Provides complete write protection with
optional 12 V Fast Programming
Table 8
VCCQ I/O Voltage
Bus Width
2.4 V– 3.0 V
16-bit
Table 2
Speed (ns)
8/16 Mbit: 100, 120 @ 2.4 V and 90, 110 @ 2.7 V
Section 4.4
Blocking (top or bottom)
8 x 4-Kword parameter
Section 2.2
Appendix E
8-Mb: 15 x 32-Kword main
16-Mb: 31 x 32-Kword main
Operating Temperature
Program/Erase Cycling
Packages
Extended: –40 °C to +85 °C
100,000 cycles
Table 8
Table 8
48-Lead TSOP
48-Ball µBGA* CSP(1)
Figures 1 and 2
Block Locking
Flexible locking of any block with zero latency
Section 3.3
Protection Register
64-bit unique device number, 64-bit user programmable Section 3.4
NOTE:
1. 8-Mbit density not available in µBGA* CSP.
5
PRELIMINARY
28F800C2, 28F160C2
E
The status register indicates the status of the WSM
by signifying block erase or word program
completion and status.
1.2
Product Overview
Intel provides secure low voltage memory solutions
with the Advanced Boot Block family of products. A
new block locking feature allows instant
locking/unlocking of any block with zero-latency. A
128-bit protection register allows unique flash
device identification.
Program and erase automation allows program and
erase operations to be executed using an industry-
standard two-write command sequence to the CUI.
Program operations are performed in word or byte
increments. Erase operations erase all locations
within a block simultaneously. Both program and
erase operations can be suspended by the system
software in order to read from any other block. In
addition, data can be programmed to another block
during an erase suspend.
Discrete supply pins provide single voltage read,
program, and erase capability at 2.4 V while also
allowing 12 V VPP for faster production
programming. Improved 12 V,
a new feature
designed to reduce external logic, simplifies board
designs when combining 12 V production
programming with 2.4 V in-field programming.
The 2.4 Volt Advanced+ Boot Block flash memories
offer two low power savings features: Automatic
Power Savings (APS) and standby mode. The
device automatically enters APS mode following the
completion of a read cycle. Standby mode is
initiated when the system deselects the device by
driving CE# inactive. Combined, these two power
savings features significantly reduce power
consumption.
The 2.4 Volt Advanced+ Boot Block flash memory
products are available in x16 packages in the
following densities: (see Section 6, Ordering
Information)
•
8-Mbit (8,388,608 bit) flash memories organized
as either 512 Kwords of 16 bits each.
•
16-Mbit (16,777,216 bit) flash memories
organized as either 1024 Kwords of 16 bits
each.
The device can be reset by lowering RP# to GND.
This provides CPU-memory reset synchronization
and additional protection against bus noise that
may occur during system reset and power-up/down
sequences (see Section 3.5 and 3.6).
Eight 4-Kword parameter blocks are located at
either the top (denoted by -T suffix) or the bottom (-
B
suffix) of the address map in order to
Refer to the DC Characteristics Section 4.3 for
complete current and voltage specifications. Refer
to the AC Characteristics Sections 4.4 and 4.5, for
read and write performance specifications. Program
and erase times and shown in Section 4.6.
accommodate different microprocessor protocols
for kernel code location. The remaining memory is
grouped into 64-Kbyte main blocks. (See Appendix
E.)
All blocks can be locked or unlocked instantly to
provide complete protection for code or data. (see
Section 3.3 for details).
2.0 PRODUCT DESCRIPTION
This section provides device pin descriptions and
package pinouts for the 2.4 Volt Advanced+ Boot
Block flash memory family which is available in 48-
lead TSOP (x16), and 48-ball µBGA packages
(Figures 1 and 2, respectively).
The Command User Interface (CUI) serves as the
interface
between
the
microprocessor
or
microcontroller and the internal operation of the
flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for program and erase
operations,
including
verification,
thereby
2.1
Package Pinouts
unburdening the microprocessor or microcontroller.
6
PRELIMINARY
E
28F800C2, 28F160C2
A16
VCCQ
GND
DQ15
DQ7
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DQ14
DQ6
DQ13
DQ5
DQ12
A8
NC
A20
48-Lead TSOP
12 mm x 20 mm
DQ
4
WE#
VCC
RP#
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
VPP
TOP VIEW
WP#
A19
16M
8M
A 18
A17
A7
A6
A5
A4
A3
A2
A1
DQ
0
OE#
GND
CE#
A0
NOTE:
Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pins 9 and 15.
Figure 1. 48-Lead TSOP Package for x16 Configurations
1
2
3
4
5
6
7
8
16M
A
B
C
D
E
F
A13
A11
A8
VPP
WP#
A19
A7
A4
A14
A10
A12
D14
D15
D7
WE#
A9
RP#
A18
A17
A5
A3
A2
A1
A15
A6
A16
D5
D11
D12
D4
D2
D3
D8
CE#
D0
A0
VCCQ
GND
D6
D9
GND
OE#
D13
VCC
D10
D1
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A19 is the upgrade address for the 16-Mbit device.
2. 8-Mbit not available on µBGA* CSP.
Figure 2. x16 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
7
PRELIMINARY
28F800C2, 28F160C2
E
Table 2. 2.4 Volt Advanced+ Boot Block Pin Descriptions
Name and Function
Symbol
Type
INPUT
ADDRESS INPUTS: Memory addresses are internally latched during a
program or erase cycle.
8-Mbit: A[0-18], 16-Mbit: A[0-19]
A0–A21
DQ0–DQ7
INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, configuration and status register data.
The data pins float to tri-state when the chip is de-selected or the outputs
are disabled.
DQ8–DQ15 INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched.
Outputs array and configuration data. The data pins float to tri-state when
the chip is de-selected.
CE#
INPUT
CHIP ENABLE: Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels.
OE#
WE#
INPUT
INPUT
OUTPUT ENABLE: Enables the device’s outputs through the data
buffers during a read operation. OE# is active low.
WRITE ENABLE: Controls writes to the command register and memory
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode, which drives the outputs to High-Z, resets the Write State
Machine, and minimizes current levels (ICCD).
When RP# is at logic high, the device is in standard operation.
When RP# transitions from logic-low to logic-high, the device resets all
blocks to locked and defaults to the read array mode.
WP#
INPUT
WRITE PROTECT: Controls the lock-down function of the flexible
Locking feature
When WP# is a logic low, the lock-down mechanism is enabled and
blocks marked lock-down cannot be unlocked through software.
When WP# is logic high, the lock-down mechanism is disabled and
blocks previously locked-down are now locked and can be unlocked and
locked through software. After WP# goes low, any blocks previously
marked lock-down revert to that state.
See Section 3.3 for details on block locking.
VCC
SUPPLY
DEVICE POWER SUPPLY: [2.4 V–3.0 V] Supplies power for device
operations.
8
PRELIMINARY
E
28F800C2, 28F160C2
Table 2. 2.4 Volt Advanced+ Boot Block Pin Descriptions (Continued)
Symbol
Type
Name and Function
I/O POWER SUPPLY: Supplies power for input/output buffers.
[2.4 V–3.0 V] This input should be tied directly to VCC
VCCQ
INPUT
.
VPP
INPUT/
SUPPLY
PROGRAM/ERASE POWER SUPPLY: [1.65 V–3.0 V or 11.4 V–12.6 V]
Operates as a input at logic levels to control complete device protection.
Supplies power for accelerated program and erase operations in 12 V ±
5% range. This pin cannot be left floating.
Lower VPP ≤ VPPLK, to protect all contents against Program and
Erase commands.
Set VPP = VCC for in-system read, program and erase operations. In
this configuration, VPP can drop as low as 1.65 V to allow for resistor or
diode drop from the system supply. Note that if VPP is driven by a logic
signal, VIH = 1.65. That is, VPP must remain above 1.65V to perform in-
system flash modifications.
Raise VPP to 12 V ± 5% for faster program and erase in a production
environment. Applying 12 V ± 5% to VPP can only be done for a
maximum of 1000 cycles on the main blocks and 2500 cycles on the
parameter blocks. VPP may be connected to 12 V for a total of 80 hours
maximum. See Section 3.4 for details on VPP voltage configurations.
GND
NC
SUPPLY
GROUND: For all internal circuitry. All ground inputs must be
connected.
NO CONNECT: Pin may be driven or left floating.
2.2.1
PARAMETER BLOCKS
2.2
Block Organization
The 2.4 Volt Advanced+ Boot Block flash memory
architecture includes parameter blocks to facilitate
storage of frequently updated small parameters
(i.e., data that would normally be stored in an
EEPROM). Each device contains eight parameter
blocks of 4-Kwords (4,096 words).
The 2.4 Volt Advanced+ Boot Block is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. Each block can be erased
independently of the others up to 100,000 times.
For the address locations of each block, see the
memory maps in Appendix E.
2.2.2
MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into 32-Kword (32,768 words) main
blocks for data or code storage. Each 8-Mbit or 16-
Mbit device contains 15 or 31 main blocks,
respectively.
9
PRELIMINARY
28F800C2, 28F160C2
E
CE# and OE# must be driven active to obtain data
at the outputs. CE# is the device selection control;
when active it enables the flash memory device.
OE# is the data output control and it drives the
selected memory data onto the I/O bus. For all read
modes, WE# and RP# must be at VIH. Figure 7
illustrates a read cycle.
the VPP voltage. The appropriate read mode
command must be issued to the CUI to enter the
corresponding mode. Upon initial device power-up
or after exit from reset, the device automatically
defaults to read array mode.
3.0 PRINCIPLES OF OPERATION
The 2.4 Volt Advanced+ Boot Block flash memory
family utilizes a CUI and automated algorithms to
simplify program and erase operations. The CUI
allows for 100% CMOS-level control inputs and
fixed power supplies during erasure and
programming.
The internal WSM completely automates program
and erase operations while the CUI signals the start
of an operation and the status register reports
status. The CUI handles the WE# interface to the
data and address latches, as well as system status
requests during WSM operation.
3.1.2
OUTPUT DISABLE
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins are placed in a
high-impedance state.
3.1
Bus Operation
The 2.4 Volt Advanced+ Boot Block flash memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations
are summarized in Table 3.
3.1.3
STANDBY
Deselecting the device by bringing CE# to a logic-
high level (VIH) places the device in standby mode,
which substantially reduces device power
consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operation, the
device continues to consume active power until the
program or erase operation is complete.
3.1.1
READ
The flash memory has four read modes available:
read array, read configuration, read status and read
query. These modes are accessible independent of
Table 3. Bus Operations(1)
RP# CE# OE#
VIH VIL
Mode
Note
WE#
DQ0–7
DQ8-15
Read (Array, Status,
2-4
VIL
VIH
DOUT
DOUT
Configuration, or Query)
Output Disable
Standby
Reset
2
2
VIH
VIH
VIL
VIH
VIL
VIH
X
VIH
X
VIH
X
High Z
High Z
High Z
DIN
High Z
High Z
High Z
DIN
2,7
2,5-7
X
X
Write
VIL
VIH
VIL
NOTES:
1. 8-bit devices use only DQ [0:7], 16-bit devices use DQ [0:15]
2. X must be VIL, VIH for control pins and addresses.
3. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, voltages.
4. Manufacturer and device codes may also be accessed in read configuration mode (A –A20 = 0). See Table 4.
1
5. Refer to Table 5 for valid DIN during a write operation.
6. To program or erase the lockable blocks, hold WP# at V .
IH
7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
10
PRELIMINARY
E
28F800C2, 28F160C2
3.1.4
RESET
addressable memory location. The address and
data buses are latched on the rising edge of the
second WE# or CE# pulse, whichever occurs first.
Figure 8 illustrates a program and erase operation.
The available commands are shown in Table 6, and
A provides detailed information on
moving between the different modes of operation
using CUI commands.
From read mode, RP# at VIL for time tPLPH
deselects the memory, places output drivers in a
high-impedance state, and turns off all internal
circuits. After return from reset, a time tPHQV is
required until the initial read access outputs are
valid. A delay (tPHWL or tPHEL) is required after
return from reset before a write can be initiated.
After this wake-up interval, normal operation is
restored. The CUI resets to read array mode, the
status register is set to 80H, and all blocks are
locked. This case is shown in Figure 9A.
Appendix
There are two commands that modify array data:
Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User
Interface (CUI) initiates a sequence of internally-
timed functions that culminate in the completion of
the requested task (unless that operation is aborted
by either RP# being driven to VIL for tPLRH or an
appropriate suspend command).
If RP# is taken low for time tPLPH during a program
or erase operation, the operation will be aborted
and the memory contents at the aborted location
(for a program) or block (for an erase) are no longer
valid, since the data may be partially erased or
written. The abort process goes through the
following sequence: When RP# goes low, the
device shuts down the operation in progress, a
process which takes time tPLRH to complete. After
this time tPLRH, the part will either reset to read
3.2
Modes of Operation
The flash memory has four read modes and two
write modes. The read modes are read array, read
configuration, read status, and read query. The
write modes are program and erase. Three
additional modes (erase suspend to program, erase
suspend to read and program suspend to read) are
available only during suspended operations. These
modes are reached using the commands
summarized in Tables 5 and 6. A comprehensive
chart showing the state transitions is in Appendix A.
array mode (if RP# has gone high during tPLRH
,
Figure 9B) or enter reset mode (if RP# is still logic
low after tPLRH, Figure 9C). In both cases, after
returning from an aborted operation, the relevant
time tPHQV or tPHWL/tPHEL must be waited before a
read or write operation is initiated, as discussed in
the previous paragraph. However, in this case,
these delays are referenced to the end of tPLRH
rather than when RP# goes high.
3.2.1
READ ARRAY
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, processor expects to read from
the flash memory. Automated flash memories
provide status information when read during
program or block erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
When RP# transitions from VIL (reset) to VIH, the
device defaults to read array mode and will respond
to the read control inputs (CE#, address inputs, and
OE#) without any additional CUI commands.
When the device is in read array mode, four control
signals control data output:
•
•
•
•
WE# must be logic high (VIH)
CE# must be logic low (VIL)
OE# must be logic low (VIL)
RP# must be logic high (VIH)
In addition, the address of the desired location must
be applied to the address pins. If the device is not
in read array mode, as would be the case after a
program or erase operation, the Read Array
command (FFH) must be written to the CUI before
array reads can take place.
3.1.5
WRITE
A write takes place when both CE# and WE# are
low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard
microprocessor write timings to control flash
operations. The CUI does not occupy an
11
PRELIMINARY
28F800C2, 28F160C2
E
3.2.2
READ CONFIGURATION
command causes subsequent reads to output data
from the status register until another command is
issued. To return to reading from the array, issue a
Read Array (FFH) command.
The read configuration mode outputs the
manufacturer/device identifier. The device is
switched to this mode by writing the read
configuration command (90H). Once in this mode,
read cycles from addresses shown in Table 4
retrieve the specified information. To return to read
array mode, write the Read Array command (FFH).
The status register bits are output on DQ0–DQ7.
The upper byte, DQ8–DQ15, outputs 00H during a
Read Status Register command.
The contents of the status register are latched on
the falling edge of OE# or CE#, whichever occurs
last. This prevents possible bus errors which might
occur if status register contents change while being
read. CE# or OE# must be toggled with each
subsequent status read, or the status register will
not indicate completion of a program or erase
operation.
The Read Configuration mode outputs three types
of information: the manufacturer/device identifier,
the block locking status, and the protection register.
The device is switched to this mode by writing the
Read Configuration command (90H). Once in this
mode, read cycles from addresses shown in Table
4 retrieve the specified information. To return to
read array mode, write the Read Array command
(FFH).
When the WSM is active, SR.7 will indicate the
status of the WSM; the remaining bits in the status
register indicate whether the WSM was successful
in performing the desired operation (see Table 7).
Table 4. Read Configuration Table
Item
Address
00000
Data
0089
ID
Manufacturer Code (x16)
Device ID (See Appendix F)
Block Lock Configuration2
• Block Is Unlocked
3.2.3.1
Clearing the Status Register
00001
XX002(1) LOCK
DQ0 = 0
The WSM sets status bits 1 through 7 to “1,” and
clears bits 2, 6 and 7 to “0,” but cannot clear status
bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and
5 indicate various error conditions, these bits can
only be cleared through the use of the Clear Status
Register (50H) command. By allowing the system
software to control the resetting of these bits,
several operations may be performed (such as
cumulatively programming several addresses or
erasing multiple blocks in sequence) before reading
the status register to determine if an error occurred
during that series. Clear the status register before
beginning another command or sequence. Note
that the Read Array command must be issued
before data can be read from the memory array.
Resetting the device also clears the status register.
• Block Is Locked
DQ0 = 1
• Block Is Locked-Down
Protection Register Lock3
DQ1 = 1
80
PR-LK
PR
Protection Register (x16)
81-88
NOTES:
1. “XX” specifies the block address of lock configuration
being read.
2. See Section 3.3.4 for valid lock status outputs.
3. See Section 3.4 for protection register information.
4. Other locations within the configuration address space
are reserved by Intel for future use.
3.2.4
READ QUERY
3.2.3
READ STATUS REGISTER
The read query mode outputs Common Flash
Interface (CFI) data when the device is read. This
can be accessed by writing the Read Query
Command (98H). The CFI data structure contains
information such as block size, density, command
set and electrical specifications. Once in this mode,
read cycles from addresses shown in Appendix C
retrieve the specified information. To return to read
array mode, write the Read Array command (FFH).
The status register indicates the status of device
operations, and the success/failure of that
operation. The Read Status Register (70H)
12
PRELIMINARY
E
28F800C2, 28F160C2
3.2.5
PROGRAM MODE
A Read Array command can now be written to the
CUI to read data from blocks other than that which
is suspended. The only other valid commands,
while program is suspended, are Read Status
Register, Read Configuration, Read Query, and
Program Resume. After the Program Resume
command is written to the flash memory, the WSM
will continue with the programming process and
status register bits SR.2 and SR.7 will automatically
be cleared. The device automatically outputs status
register data when read (see Figure 11 in Appendix
B, Program Suspend/Resume Flowchart) after the
Program Resume command is written. VPP must
remain at the same VPP level used for program
while in program suspend mode. RP# must also
remain at VIH.
Programming is executed using
a
two-write
sequence. The Program Setup command (40H) is
written to the CUI followed by a second write which
specifies the address and data to be programmed.
The WSM will execute a sequence of internally
timed events to program desired bits of the
addressed location, then verify the bits are
sufficiently programmed. Programming the memory
results in specific bits within an address location
being changed to a “0.” If the user attempts to
program “1”s, the memory cell contents do not
change and no error occurs.
The status register indicates programming status:
while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling
either CE# or OE#. While programming, the only
valid commands are Read Status Register,
Program Suspend, and Program Resume.
3.2.6
ERASE MODE
To erase a block, write the Erase Set-up and Erase
Confirm commands to the CUI, along with an
address identifying the block to be erased. This
address is latched internally when the Erase
Confirm command is issued. Block erasure results
in all bits within the block being set to “1.” Only one
block can be erased at a time. The WSM will
execute a sequence of internally timed events to
program all bits within the block to “0,” erase all bits
within the block to “1,” then verify that all bits within
the block are sufficiently erased. While the erase
executes, status bit 7 is a “0.”
When programming is complete, the program status
bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status
register is set to indicate a program failure. If SR.3
is set then VPP was not within acceptable limits, and
the WSM did not execute the program command. If
SR.1 is set, a program operation was attempted on
a locked block and the operation was aborted.
The status register should be cleared before
attempting the next operation. Any CUI instruction
can follow after programming is completed;
however, to prevent inadvertent status register
reads, be sure to reset the CUI to read array mode.
When the status register indicates that erasure is
complete, check the erase status bit to verify that
the erase operation was successful. If the Erase
operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase
failure. If VPP was not within acceptable limits after
the Erase Confirm command was issued, the WSM
will not execute the erase sequence; instead, SR.5
of the status register is set to indicate an erase
error, and SR.3 is set to a “1” to identify that VPP
supply voltage was not within acceptable limits.
3.2.5.1
Suspending and Resuming
Program
The Program Suspend command halts an in-
progress program operation so that data can be
read from other locations of memory. Once the
programming process starts, writing the Program
Suspend command to the CUI requests that the
WSM suspend the program sequence (at
predetermined points in the program algorithm).
The device continues to output status register data
after the Program Suspend command is written.
Polling status register bits SR.7 and SR.2 will
determine when the program operation has been
suspended (both will be set to “1”). tWHRH1/tEHRH1
specify the program suspend latency.
After an erase operation, clear the status register
(50H) before attempting the next operation. Any
CUI instruction can follow after erasure is
completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in
read array mode after the erase is complete.
13
PRELIMINARY
28F800C2, 28F160C2
E
3.2.6.1
Suspending and Resuming Erase
A Read Array/Program command can now be
written to the CUI to read/program data from/to
blocks other than that which is suspended. This
nested Program command can subsequently be
suspended to read yet another location. The only
valid commands while erase is suspended are
Read Status Register, Read Configuration, Read
Query, Program Setup, Program Resume, Erase
Resume, Lock Block, Unlock Block and Lock-Down
Block. During erase suspend mode, the chip can be
placed in a pseudo-standby mode by taking CE# to
VIH. This reduces active current consumption.
Since an erase operation requires on the order of
seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in
order to read data from or program data to another
block in memory. Once the erase sequence is
started, writing the Erase Suspend command to the
CUI suspends the erase sequence at
a
predetermined point in the erase algorithm. The
status register will indicate if/when the erase
operation has been suspended. Erase suspend
latency is specified by tWHRH2/tEHRH2
.
Erase Resume continues the erase sequence when
CE# = VIL. As with the end of a standard erase
operation, the status register must be read and
cleared before the next instruction is issued.
Table 5. Command Bus Definitions
First Bus Cycle
Second Bus Cycle
Command
Read Array
Notes
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Addr
X
Data
FFH
90H
Oper
Addr
Data
4
2, 4
2, 4
4
Read Configuration
Read Query
X
Read
Read
Read
IA
QA
X
ID
X
98H
QD
Read Status Register
Clear Status Register
Program
X
70H
SRD
4
X
50H
3,4
4
X
40H/10H
20H
Write
Write
PA
BA
PD
Block Erase/Confirm
Program/Erase Suspend
Program/Erase Resume
Lock Block
X
D0H
4
X
B0H
D0H
60H
4
X
4
X
Write
Write
Write
Write
BA
BA
BA
PA
01H
D0H
2FH
PD
Unlock Block
4
X
60H
Lock-Down Block
Protection Program
X = Don’t Care
4
X
60H
4
X
C0H
PA = Prog Addr BA = Block Addr IA = Identifier Addr. QA = Query Addr.
SRD = Status Reg. Data PD = Prog Data
ID = Identifier Data QD = Query Data
NOTES:
1. Bus operations are defined in Table 3.
2. Following the Read Configuration or Read Query commands, read operations output device configuration or CFI query
information, respectively. See Section 3.2.2 and 3.2.4.
3. Either 40H or 10H command is valid, but the Intel standard is 40H.
4. When writing commands, the upper data bus [DQ –DQ15] should be either VIL or VIH, to minimize current draw.
8
14
PRELIMINARY
E
28F800C2, 28F160C2
Table 6. Command Codes and Descriptions
Description
Code Device Mode
FF
Read Array
Places device in read array mode, such that array data will be output on the
data pins.
40
Program
Set-Up
This is a two-cycle command. The first cycle prepares the CUI for a program
operation. The second cycle latches addresses and data information and
initiates the WSM to execute the Program algorithm. The flash outputs status
register data when CE# or OE# is toggled. A Read Array command is required
after programming to read array data. See Section 3.2.5.
20
Erase
Set-Up
Prepares the CUI for the Erase Confirm command. If the next command is not
an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the
status register to a “1,” (b) place the device into the read status register mode,
and (c) wait for another command. See Section 3.2.6.
D0
Erase Confirm If the previous command was an Erase Set-Up command, then the CUI will
close the address and data latches, and begin erasing the block indicated on the
address pins. During program/erase, the device will respond only to the Read
Status Register, Program Suspend and Erase Suspend commands and will
output status register data when CE# or OE# is toggled.
Program/Erase If a program or erase operation was previously suspended, this command will
Resume
resume that operation.
If the previous command was Configuration Set-Up, the CUI will latch the
address and unlock the block indicated on the address pins. If the block had
been previously set to Lock-Down, this operation will have no effect. (Sect. 3.3)
Unlock Block
B0
Program
Suspend
Issuing this command will begin to suspend the currently executing
program/erase operation. The status register will indicate when the operation
has been successfully suspended by setting either the program suspend (SR.2)
or erase suspend (SR.6) and the WSM status bit (SR.7) to a “1” (ready). The
WSM will continue to idle in the SUSPEND state, regardless of the state of all
input control pins except RP#, which will immediately shut down the WSM and
the remainder of the chip if RP# is driven to VIL. See Sections 3.2.5.1 and
3.2.6.1.
Erase
Suspend
70
50
Read Status
Register
This command places the device into read status register mode. Reading the
device will output the contents of the status register, regardless of the address
presented to the device. The device automatically enters this mode after a
program or erase operation has been initiated. See Section 3.2.3.
Clear Status
Register
The WSM can set the block lock status (SR.1) , VPP Status (SR.3), program
status (SR.4), and erase status (SR.5) bits in the status register to “1,” but it
cannot clear them to “0.” Issuing this command clears those bits to “0.”
90
60
Read
Configuration
Puts the device into the read configuration mode, so that reading the device will
output the manufacturer/device codes or block lock status. Section 3.2.2.
Configuration
Set-Up
Prepares the CUI for changes to the device configuration, such as block locking
changes. If the next command is not Block Unlock, Block Lock, or Block Lock-
Down, then the CUI will set both the program and erase status register bits to
indicate a command sequence error. See Section 3.3.
01
Lock-Block
If the previous command was Configuration Set-Up, the CUI will latch the
address and lock the block indicated on the address pins. (Section 3.3)
15
PRELIMINARY
28F800C2, 28F160C2
Code Device Mode
E
Table 6. Command Codes and Descriptions (Continued)
Description
2F
Lock-Down
If the previous command was a Configuration Set-Up command, the CUI will
latch the address and lock-down the block indicated on the address pins.
(Section 3.3)
98
Read
Query
Puts the device into the read query mode, so that reading the device will output
Common Flash Interface information. See Section 3.2.4 and Appendix C.
C0
Protection
Program
Setup
This is a two-cycle command. The first cycle prepares the CUI for an program
operation to the protection register. The second cycle latches addresses and
data information and initiates the WSM to execute the Protection Program
algorithm to the protection register. The flash outputs status register data when
CE# or OE# is toggled. A Read Array command is required after programming
to read array data. See Section 3.4.
10
00
Alt. Prog Set-Up Operates the same as Program Set-up command. (See 40H/Program Set-Up)
Invalid/
Unassigned commands that should not be used. Intel reserves the right to
redefine these codes for future functions.
Reserved
NOTE:
See Appendix A for mode transition information.
16
PRELIMINARY
E
28F800C2, 28F160C2
Table 7. Status Register Bit Definition
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
R
0
NOTES:
SR.7 WRITE STATE MACHINE STATUS
Check Write State Machine bit first to determine
Word Program or Block Erase completion, before
checking Program or Erase Status bits.
1 = Ready
0 = Busy
(WSMS)
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to “1.”
ESS bit remains set to “1” until an Erase Resume
command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the
max. number of erase pulses to the block and is still
unable to verify successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
When this bit is set to “1,” WSM has attempted but
failed to program a word/byte.
0 = Successful Programming
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous
indication of VPP level. The WSM interrogates VPP
level only after the Program or Erase command
sequences have been entered, and informs the
system if VPP has not been switched on. The VPP is
also checked before the operation is verified by the
WSM. The VPP status bit is not guaranteed to report
accurate feedback between VPPLK and VPP1Min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts
execution and sets both WSMS and PSS bits to “1.”
PSS bit remains set to “1” until a Program Resume
command is issued.
SR.1 = BLOCK LOCK STATUS
1 = Prog/Erase attempted on a locked
block; Operation aborted.
If a program or erase operation is attempted to one
of the locked blocks, this bit is set by the WSM. The
operation specified is aborted and the device is
returned to read status mode.
0 = No operation to locked blocks
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
This bit is reserved for future use and should be
masked out when polling the status register.
NOTES:
1. A Command Sequence Error is indicated when both SR.4 , SR.5 and SR.7 are set.
17
PRELIMINARY
28F800C2, 28F160C2
E
3.3.2
LOCKED STATE
3.3
Flexible Block Locking
The Intel® 2.4 Volt Advanced+ Boot Block products
offer an instant, individual block locking scheme
that allows any block to be locked or unlocked with
no latency, enabling instant code and data
protection.
The default status of all blocks upon power-up or
reset is locked (states [001] or [101]). Locked
blocks are fully protected from alteration. Any
program or erase operations attempted on a locked
block will return an error on bit SR.1 of the status
register. The status of a locked block can be
changed to Unlocked or Lock-Down using the
appropriate software commands. An Unlocked
block can be locked by writing the Lock command
sequence, 60H followed by 01H.
This locking scheme offers two levels of protection.
The first level allows software-only control of block
locking (useful for data blocks that change
frequently), while the second level requires
hardware interaction before locking can be changed
(useful for code blocks that change infrequently).
3.3.3
UNLOCKED STATE
The following sections will discuss the operation of
the locking system. The term “state [XYZ]” will be
used to specify locking states; e.g., “state [001],”
where X = value of WP#, Y = bit DQ1 of the Block
Lock status register, and Z = bit DQ0 of the Block
Lock status register. Table 9 defines all of these
possible locking states.
Unlocked blocks (states [000], [100], [110]) can be
programmed or erased. All unlocked blocks return
to the Locked state when the device is reset or
powered down. The status of an unlocked block can
be changed to Locked or Locked-Down using the
appropriate software commands. A Locked block
can be unlocked by writing the Unlock command
sequence, 60H followed by D0H.
3.3.1
LOCKING OPERATION
3.3.4
LOCK-DOWN STATE
The following concisely summarizes the locking
functionality.
Blocks that are Locked-Down (state [011]) are
protected from program and erase operations (just
like Locked blocks), but their protection status
cannot be changed using software commands
alone. A Locked or Unlocked block can be Locked-
down by writing the Lock-Down command
sequence, 60H followed by 2FH. Locked-Down
blocks revert to the Locked state when the device is
reset or powered down.
•
All blocks power-up locked, then can be
unlocked or locked with the Unlock and Lock
commands.
•
The Lock-Down command locks a block and
prevents it from being unlocked when WP# = 0.
When WP# = 1, Lock-Down is overridden
and commands can unlock/lock locked-
down blocks.
The Lock-Down function is dependent on the WP#
input pin. When WP# = 0, blocks in Lock-Down
[011] are protected from program, erase, and lock
status changes. When WP# = 1, the Lock-Down
function is disabled ([111]) and locked-down blocks
can be individually unlocked by software command
to the [110] state, where they can be erased and
programmed. These blocks can then be relocked
[111] and unlocked [110] as desired while WP#
remains high. When WP# goes low, blocks that
were previously locked-down return to the
Lock-Down state [011] regardless of any changes
made while WP# was high. Device reset or power-
down resets all blocks, including those in Lock-
Down, to Locked state.
When WP# returns to 0, locked-down
blocks return to Lock-Down.
Lock-Down is cleared only when the device
is reset or powered-down.
The locking status of each block can set to Locked,
Unlocked, and Lock-Down, each of which will be
described
comprehensive state table for the locking functions
is shown in Table 9, and a flowchart for locking
operations is shown in Figure 14.
in
the
following
sections.
A
18
PRELIMINARY
E
28F800C2, 28F160C2
3.3.5
READING A BLOCK’S LOCK STATUS
the lock status will be changed. After completing
any desired lock, read, or program operations,
resume the erase operation with the Erase Resume
command (D0H).
The lock status of every block can be read in the
configuration read mode of the device. To enter this
mode, write 90H to the device. Subsequent reads at
Block Address + 00002 will output the lock status of
that block. The lock status is represented by the
lowest two output pins, DQ0 and DQ1. DQ0
indicates the Block Lock/Unlock status and is set by
the Lock command and cleared by the Unlock
command. It is also automatically set when entering
Lock-Down. DQ1 indicates Lock-Down status and is
set by the Lock-Down command. It cannot be
cleared by software, only by device reset or power-
down.
If a block is locked or locked-down during a
suspended erase of the same block, the locking
status bits will be changed immediately, but when
the erase is resumed, the erase operation will
complete.
Locking operations cannot be performed during a
program suspend. Refer to Appendix A for detailed
information on which commands are valid during
erase suspend.
Table 8. Block Lock Status
3.3.7
STATUS REGISTER ERROR
CHECKING
Item
Address
Data
Block Lock Configuration
• Block Is Unlocked
• Block Is Locked
XX002
LOCK
Using nested locking or program command
sequences during erase suspend can introduce
ambiguity into status register results.
DQ0 = 0
DQ0 = 1
DQ1 = 1
Since locking changes are performed using a two
cycle command sequence, e.g., 60H followed by
01H to lock a block, following the Configuration
Setup command (60H) with an invalid command will
produce a lock command error (SR.4 and SR.5 will
be set to 1) in the status register. If a lock
command error occurs during an erase suspend,
SR.4 and SR.5 will be set to 1, and will remain at 1
after the erase is resumed. When erase is
complete, any possible error during the erase
cannot be detected via the status register because
of the previous locking command error.
• Block Is Locked-Down
3.3.6
LOCKING OPERATIONS DURING
ERASE SUSPEND
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock, or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
A similar situation happens if an error occurs during
a program operation error nested within an erase
suspend.
To change block locking during an erase operation,
first write the erase suspend command (B0H), then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired lock command sequence to a block and
19
PRELIMINARY
28F800C2, 28F160C2
E
Table 9. Block Locking State Transitions
Erase/Prog Lock Command Input Result [Next State]
Current State
DQ0
WP# DQ1
Name
Allowed?
Yes
No
Lock
Unlock
Lock-Down
0
0
0
1
1
1
0
0
1
0
0
1
1
0
1
1
0
1
0
1
“Unlocked”
Goes To [001] No Change Goes To [011]
“Locked” (Default)
“Locked-Down”
“Unlocked”
No Change Goes To [000] Goes To [011]
No
No Change
No Change
No Change
Yes
No
Goes To [101] No Change Goes To [111]
No Change Goes To [100] Goes To [111]
Goes To [111] No Change Goes To [111]
No Change Goes To [110] No Change
“Locked”
Lock-Down Disabled
Lock-Down Disabled
Yes
No
1
NOTES:
1. In this table, the notation [XYZ] denotes the locking state of a block, where X= WP#, Y = DQ1, and Z = DQ0. The current
locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ , DQ1). DQ0 indicates if
0
a block is locked (1) or unlocked (0). DQ1 indicates if a block has been locked-down (1) or not (0).
2. At power-up or device reset, all blocks default to Locked state [001] (if WP#= 0). Holding WP# = 0 is the recommended
default.
3. The “Erase/Program Allowed?” column shows whether erase and program operations are enabled (Yes) or disabled (No)
in that block’s current locking state.
4. The “Lock Command Input Result [Next State]” column shows the result of writing the three locking commands (Lock,
Unlock, Lock-Down) in the current locking state. For example,“Goes To [001]” would mean that writing the command to a
block in the current locking state would change it to [001].
3.4.1
READING THE PROTECTION
REGISTER
3.4
128-Bit Protection Register
The Advanced+ Boot Block architecture includes a
128-bit protection register than can be used to
increase the security of a system design. For
example, the number contained in the protection
register can be used to “mate” the flash component
with other system components such as the CPU or
ASIC, preventing device substitution. Additional
application information can be found in Intel
application note AP-657 Designing with the
Advanced+ Boot Block Flash Memory Architecture.
The protection register is read in the configuration
read mode. The device is switched to this mode by
writing the Read Configuration command (90H).
Once in this mode, read cycles from addresses
shown in Appendix
G retrieve the specified
information. To return to read array mode, write the
Read Array command (FFH).
3.4.2
PROGRAMMING THE PROTECTION
REGISTER
The 128-bits of the protection register are divided
into two 64-bit segments. One of the segments is
programmed at the Intel factory with a unique 64-bit
number, which is unchangeable. The other segment
is left blank for customer designs to program as
desired. Once the customer segment is
programmed, it can be locked to prevent
reprogramming.
The protection register bits are programmed using
the two-cycle Protection Program command. The
64-bit number is programmed 16 bits at a time for
word-wide parts and eight bits at a time for byte-
wide parts. First write the Protection Program Setup
command, C0H. The next write to the device will
latch in address and data and program the specified
location. The allowable addresses are shown in
Appendix G. See Figure 15 for the Protection
Register Programming Flowchart.
20
PRELIMINARY
E
28F800C2, 28F160C2
Program and Erase
Attempts to address Protection Program commands
outside the defined protection register address
space should not be attempted. This space is
reserved for future use. Attempting to program to a
previously locked protection register segment will
result in a status register error (program error bit
SR.4 and lock error bit SR.1 will be set to 1).
3.5
V
PP
Voltages
Intel’s 2.4 Volt Advanced+ Boot Block products
provide in-system programming and erase in the
1.65 V–3.0 V
range.
For
fast
production
programming, it also includes a low-cost, backward-
compatible 12 V programming feature.
3.4.3
LOCKING THE PROTECTION
REGISTER
3.5.1
IMPROVED 12 V OPERATION FOR
PRODUCTION PROGRAMMING
The user-programmable segment of the protection
register is lockable by programming Bit 1 of the
PR-LOCK location to 0. Bit 0 of this location is
programmed to 0 at the Intel factory to protect the
unique device number. This bit is set using the
Protection Program command to program “FFFD” to
the PR-LOCK location. After these bits have been
programmed, no further changes can be made to
the values stored in the protection register.
Protection Program commands to a locked section
will result in a status register error (program error bit
SR.4 and Lock Error bit SR.1 will be set to 1).
Protection register lockout state is not reversible.
When VPP is between 1.65 V and 3.0 V, all program
and erase current is drawn through the VCC pin.
Note that if VPP is driven by a logic signal, VIH min =
1.65 V. That is, VPP must remain above 1.65 V to
perform in-system flash modifications. When VPP is
connected to a 12 V power supply, the device
draws program and erase current directly from the
VPP pin. This eliminates the need for an external
switching transistor to control the voltage VPP
.
Figure 4 shows examples of how the flash power
supplies can be configured for various usage
models.
The 12 V VPP mode enhances programming
performance during the short period of time typically
found in manufacturing processes; however, it is
not intended for extended use. 12 V may be applied
to VPP during program and erase operations for a
maximum of 1000 cycles on the main blocks and
2500 cycles on the parameter blocks. VPP may be
connected to 12 V for a total of 80 hours maximum.
Stressing the device beyond these limits may cause
permanent damage.
88H
4 Words
User Programmed
85H
84H
4 Words
Factory Programmed
81H
3.5.2
V
PP ≤ VPPLK FOR COMPLETE
PR-LOCK
80H
PROTECTION
0645_05
In addition to the flexible block locking, the VPP
programming voltage can be held low for absolute
hardware write protection of all blocks in the flash
device. When VPP is below VPPLK, any program or
erase operation will result in a error, prompting the
corresponding status register bit (SR.3) to be set.
Figure 3. Protection Register Memory Map
21
PRELIMINARY
28F800C2, 28F160C2
E
System Supply
System Supply
12 V Supply
VCC
VPP
VCC
VPP
Prot#
(Logic Signal)
10
≤ KΩ
12 V Fast Programming
Low-Voltage Programming
Absolute Write Protection With V PP
≤
VPPLK
Absolute Write Protection via Logic Signal
System Supply
(Note 1)
System Supply
VCC
VCC
VPP
VPP
12 V Supply
Low Voltage and 12 V Fast Programming
Low-Voltage Programming
0645_06
NOTE:
1. A resistor can be used if the V supply can sink adequate current based on resistor value. SeeAP-657 Designing with
CC
the Advanced+ Boot Block Flash Memory Architecture for details.
Figure 4. Example Power Supply Configurations
3.6.2
AUTOMATIC POWER SAVINGS (APS)
3.6
Power Consumption
Automatic Power Savings provides low-power
operation during read mode. After data is read from
the memory array and the address lines are
quiescent, APS circuitry places the device in a
Intel’s flash devices have a tiered approach to
power savings that can significantly reduce overall
system power consumption. The Automatic Power
Savings (APS) feature reduces power consumption
when the device is selected but idle. If the CE# is
deasserted, the flash enters its standby mode,
where current consumption is even lower. The
combination of these features can minimize
memory power consumption, and therefore, overall
system power consumption.
mode where typical current is comparable to ICCS
.
The flash stays in this static state with outputs valid
until a new location is read.
3.6.3
STANDBY POWER
With CE# at a logic-high level (VIH) and device in
read mode, the flash memory is in standby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
are placed in a high-impedance state independent
of the status of the OE# signal. If CE# transitions to
3.6.1
ACTIVE POWER
(Program/Erase/Read)
With CE# at a logic-low level and RP# at a logic-
high level, the device is in the active mode. Refer to
the DC Characteristic tables for ICC current values.
Active power is the largest contributor to overall
system power consumption. Minimizing the active
current could have a profound effect on system
power consumption, especially for battery-operated
devices.
a
logic-high level during erase or program
operations, the device will continue to perform the
operation and consume corresponding active power
until the operation is completed.
22
PRELIMINARY
E
28F800C2, 28F160C2
System engineers should analyze the breakdown of
standby time versus active time and quantify the
respective power consumption in each mode for
their specific application. This will provide a more
accurate measure of application-specific power and
energy requirements.
System designers must guard against spurious
writes when VCC voltages are above VLKO. Since
both WE# and CE# must be low for a command
write, driving either signal to VIH will inhibit writes to
the device. The CUI architecture provides additional
protection since alteration of memory contents can
only occur after successful completion of the two-
step command sequences. The device is also
disabled until RP# is brought to VIH, regardless of
the state of its control inputs. By holding the device
in reset (RP# connected to system PowerGood)
during power-up/down, invalid bus conditions during
power-up can be masked, providing yet another
level of memory protection.
3.6.4
DEEP POWER-DOWN MODE
The deep power-down mode is activated when
RP# = VIL (GND ± 0.2 V). During read modes, RP#
going low de-selects the memory and places the
outputs in a high impedance state. Recovery from
deep power-down requires a minimum time of tPHQV
for read operations and tPHWL/tPHEL for write
operations.
3.7.2
VCC, VPP AND RP# TRANSITIONS
During program or erase modes, RP# transitioning
low will abort the in-progress operation. The
memory contents of the address being programmed
or the block being erased are no longer valid as the
data integrity has been compromised by the abort.
During deep power-down, all internal circuits are
switched to a low power savings mode (RP#
transitioning to VIL or turning off power to the device
clears the status register).
The CUI latches commands as issued by system
software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from reset mode or after VCC
transitions above VLKO (Lockout voltage), is read
array mode.
After any program or block erase operation is
complete (even after VPP transitions down to
V
PPLK), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
3.7
Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since the
device is indifferent as to which power supply, VPP
or VCC, powers-up first.
3.8
Power Supply Decoupling
Flash memory’s power switching characteristics
require careful device decoupling. System
designers should consider three supply current
issues:
3.7.1
RP# CONNECTED TO SYSTEM
RESET
1. Standby current levels (ICCS
)
2. Read current levels (ICCR
)
The use of RP# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
3. Transient peaks produced by falling and rising
edges of CE#.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
without
a
flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Intel recommends connecting
RP# to the system CPU RESET# signal to allow
proper CPU/flash initialization following system
reset.
flash device should have
a 0.1 µF ceramic
capacitor connected between each VCC and GND,
and between its VPP and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
23
PRELIMINARY
28F800C2, 28F160C2
E
4.0 ELECTRICAL SPECIFICATIONS
NOTICE: This datasheet contains preliminary information on
new products in production. Do not finalize a design with
this information. Revised information will be published when
the product is available. Verify with your local Intel Sales
office that you have the latest datasheet before finalizing a
design.
4.1
Absolute Maximum Ratings*
Extended Operating Temperature
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.
During Read .......................... –40 °C to +85 °C
During Block Erase
and Program.......................... –40 °C to +85 °C
Temperature Under Bias........ –40 °C to +85 °C
Storage Temperature................. –65 °C to +125 °C
Voltage on Any Pin
NOTES:
(except VCC and VPP
)
1. Minimum DC voltage is –0.5 V on input/output pins.
During transitions, this level may undershoot to–2.0 V
for periods < 20 ns. Maximum DC voltage on
input/output pins is VCC + 0.5 V which, during
transitions, may overshoot to VCC + 2.0 V for periods
< 20 ns.
with Respect to GND .............–0.5 V to +3.7 V1
VPP Voltage (for Block
Erase and Program)
with Respect to GND .......–0.5 V to +13.5 V1,2,4
2. Maximum DC voltage on VPP may overshoot to +14.0 V
for periods < 20 ns.
VCC and VCCQ Supply Voltage
with Respect to GND .............–0.2 V to +3.0 V1
3. Output shorted for no more than one second.No more
than one output shorted at a time.
Output Short Circuit Current...................... 100 mA3
4.
VPP voltage is normally 1.65 V–3.0 V. Connection to
supply of 11.4 V–12.6 V can only be done for 1000
cycles on the main blocks and 2500 cycles on the
parameter blocks during program/erase. VPP may be
connected to 12 V for a total of 80 hours maximum.
See Section 3.5 for details.
4.2
Operating Conditions
Table 10. Temperature and Voltage Operating Conditions
Symbol
Parameter
Operating Temperature
VCC Supply Voltage
Notes
Min
–40
Max
+85
3.0
Units
°C
TA
VCC1
VCC2
VCCQ1
VPP1
VPP2
1
1
2.4
Volts
2.7
3.0
I/O Supply Voltage
Supply Voltage
1
2.4
3.0
Volts
Volts
1
1.65
11.4
100,000
3.0
1, 2
2
12.6
Volts
Cycling
Block Erase Cycling
Cycles
NOTES:
1.
VCC and VCCQ must share the same supply when they are in the VCC1 range.
2. Applying VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours maximum. See Section
PP
3.5 for details.
24
PRELIMINARY
E
28F800C2, 28F160C2
Conditions
4.3
Capacitance
TA = 25 °C, f = 1 MHz
Sym
Parameter
Input Capacitance
Notes
Typ
6
Max
8
Units
pF
CIN
1
1
VIN = 0 V
VOUT = 0 V
COUT Output Capacitance
10
12
pF
NOTE:
1. Sampled, not 100% tested.
4.4
DC Characteristics
VCC
2.4 V–3.0 V
VCCQ
Note
1,7
2.4 V–3.0 V
Sym
Parameter
Typ
Max
Unit
Test Conditions
CC = VCCMax
CCQ = VCCQMax
IN = VCCQ or GND
V
V
V
ILI
Input Load Current
± 1
± 10
25
µA
V
CC = VCCMax
VCCQ = VCCQMax
IN = VCCQ or GND
ILO
Output Leakage Current
VCC Standby Current
1,7
1
0.2
10
µA
µA
V
ICCS
VCC = VCCMax
CE# = RP# = VCCQ
WP# = VCCQ or GND
V
CC = VCCMax
VCCQ = VCCQMax
IN = VCCQ or GND
RP# = GND ± 0.2 V
ICCD
VCC Deep Power-Down
Current
1,7
7
8
20
12
µA
V
V
V
CC = VCCMax
CCQ = VCCQMax
ICCR
VCC Read Current
1,5,7
mA
OE# = VIH , CE# = VIL
f = 5 MHz, IOUT = 0 mA
Inputs = VIL or VIH
V
PP = VPP1
ICCW VCC Program Current
1,4
1,4
18
8
55
15
45
15
mA
mA
mA
mA
Program in Progress
V
PP = VPP2 (12 V)
Program in Progress
PP = VPP1
Erase in Progress
PP = VPP2 (12 V)
Erase in Progress
V
VCC Erase Current
16
8
ICCE
V
25
PRELIMINARY
28F800C2, 28F160C2
4.4 DC Characteristics (Continued)
E
VCC
VCCQ
Note
1,2,4
2.4 V–3.0 V
2.4 V–3.0 V
Sym
Parameter
Typ
10
Max
25
Unit
Test Conditions
ICCES VCC Erase Suspend
Current
µA
CE# = VIH, Erase Suspend in
Progress
ICCWS VCC Program Suspend
Current
1,2,4
1
10
25
5
µA
µA
CE# = VIH, Program
Suspend in Progress
IPPD
VPP Deep Power-Down
Current
0.2
RP# = GND ± 0.2 V
V
V
V
PP ≤ VCC
PP ≤ VCC
PP ≤ VCC
IPPS
IPPR
VPP Standby Current
VPP Read Current
1
0.2
2
5
µA
µA
µA
mA
1
±15
200
0.1
1,4
1,4
50
VPP > VCC
PP =VPP1
V
IPPW
VPP Program Current
VPP Erase Current
0.05
Program in Progress
PP = VPP2 (12 V)
Program in Progress
PP = VPP1
Program in Progress
PP = VPP2 (12 V)
V
8
0.05
8
22
0.1
22
5
mA
mA
mA
µA
V
IPPE
1,4
1,4
1,4
V
Program in Progress
VPP = VPP1
Erase Suspend in Progress
IPPES VPP Erase Suspend Current
IPPWS VPP Program Suspend Current
0.2
50
VPP = VPP2 (12 V)
Erase Suspend in Progress
200
5
µA
VPP = VPP1
Program Suspend in
Progress
0.2
µA
VPP = VPP2 (12 V)
Program Suspend in
Progress
50
200
µA
26
PRELIMINARY
E
28F800C2, 28F160C2
4.4
DC Characteristics (Continued)
VCC
VCCQ
Note
2.4 V–3.0 V
2.4 V–3.0 V
Sym
Parameter
Min
-0.4
Max
VCC
Unit
Test Conditions
VIL
Input Low Voltage
V
*0.22 V
2.0
VCCQ
+0.3 V
VIH
Input High Voltage
Output Low Voltage
V
V
VOL
7
7
-0.10
0.10
VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
VOH
Output High Voltage
VCCQ
-
V
0.1 V
VPPLK VPP Lock-Out Voltage
3
3
1.0
3.0
V
V
Complete Write Protection
VPP1
VPP2
VLKO
VLKO2
VPP during Program / Erase
Operations
1.65
11.4
1.5
3,6
12.6
VCC Prog/Erase Lock Voltage
V
V
VCCQ Prog/Erase Lock
Voltage
1.2
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 °C.
2.
I
I
CCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of
CCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR
.
3. Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPP1 and VPP2
.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
6. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours maximum. See Section
PP
3.4 for details.
7. The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ voltage
listed at the top of each column.
27
PRELIMINARY
28F800C2, 28F160C2
E
OUTPUT
VCCQ
VCCQ
2
VCCQ
2
TEST POINTS
INPUT
0.0
0645_07
Figure 5. Input/Output Reference Waveform
Test Configuration Component Values Table
Test Configuration
CL (pF) R1 (Ω) R2 (Ω)
50 22K 22K
VCCQ
2.4 V–3.0 V Standard
Test
R1
R2
NOTE:
Device
Under Test
CL includes jig capacitance.
Out
CL
0645_08
Figure 6. Test Configuration
28
PRELIMINARY
E
28F800C2, 28F160C2
(1,4)
4.5
AC Characteristics—Read Operations
—Extended Temperature
Density
Product
VCC
8/16 Mbit
–100
–120
2.7 V–3.0 V 2.4 V–3.0 V 2.7 V–3.0 V 2.4 V–3.0 V
#
Sym
Parameter
Read Cycle Time
Note
Min Max Min Max Min Max Min Max Unit
R1
R2
tAVAV
90
100
110
120
ns
ns
tAVQV Address to
Output Delay
90
90
100
100
30
110
110
30
120
120
30
R3
R4
R5
R6
R7
R8
R9
tELQV
CE# to Output
Delay
2
2
ns
ns
ns
ns
ns
ns
ns
ns
tGLQV OE# to Output
Delay
30
tPHQV RP# to Output
Delay
150
150
150
150
tELQX
CE# to Output in
Low Z
3
3
3
3
3
0
0
0
0
0
0
0
0
tGLQX OE# to Output in
Low Z
tEHQZ CE# to Output in
High Z
25
20
25
20
25
20
25
20
tGHQZ OE# to Output in
High Z
R10 tOH
Output Hold from
Address, CE#, or
OE# Change,
Whichever
0
0
0
0
Occurs First
NOTES:
1. See Figure 7: AC Waveform: Read Operations.
2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV
.
3. Sampled, but not 100% tested.
4. See Figure 5: Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.
29
PRELIMINARY
28F800C2, 28F160C2
E
Device and
Address Selection
Data
Valid
Standby
VIH
ADDRESSES (A)
VIL
Address Stable
R1
VIH
CE# (E)
VIL
R8
R9
VIH
OE# (G)
VIL
VIH
WE# (W)
R4
R3
Valid Output
R7
R10
VIL
VOH
DATA (D/Q)
VOL
R6
High Z
High Z
R2
VIH
RP#(P)
R5
VIL
Figure 7. AC Waveform: Read Operations
30
PRELIMINARY
E
28F800C2, 28F160C2
—Extended Temperature
(1,5,6)
4.6
AC Characteristics—Write Operations
Density
8/16 Mbit
Product
–100
–120
110
2.7 V – 3.0 V
2.4 V – 3.0 V
Note
90
100
Min
150
120
Min
150
#
Sym
W1 tPHWL
tPHEL
W2 tELWL
tWLEL
W3 tWLWH
tELEH
W4 tDVWH
tDVEH
W5 tAVWH
tAVEH
W6 tEHWH
tWHEH
W7 tWHDX
tEHDX
W8 tWHAX
Parameter
Min
Min
Unit
/
RP# High Recovery to WE# (CE#)
Going Low
150
150
ns
/
CE# (WE#) Setup to WE# (CE#)
Going Low
0
60
50
60
0
0
70
60
70
0
0
70
60
70
0
0
70
60
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
/
WE# (CE#) Pulse Width
4
2
2
/
Data Setup to WE# (CE#) Going
High
/
Address Setup to WE# (CE#) Going
High
/
CE# (WE#) Hold Time from WE#
(CE#) High
/
Data Hold Time from WE# (CE#)
High
2
2
4
3
0
0
0
0
/
Address Hold Time from WE# (CE#)
High
0
0
0
0
tEHAX
W9 tWHWL/
tEHEL
WE# (CE#) Pulse Width High
30
200
30
200
30
200
30
200
W10 tVPWH
/
VPP Setup to WE# (CE#) Going
High
tVPEH
W11 tQVVL
VPP Hold from Valid SRD
3
3
0
0
0
0
0
0
0
0
ns
ns
W12
tBHWH / WP# Setup to WE# (CE#) Going
High
tBHEH
W13
tQVBL
WP# Hold from Valid SRD
3
0
0
0
0
ns
31
PRELIMINARY
28F800C2, 28F160C2
E
NOTES:
1. Write timing characteristics during erase suspend are the same as during write-only operations.
2. Refer to Table 5 for valid AIN or DIN
.
3. Sampled, but not 100% tested.
4. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last)to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, Write pulse width high (tWPH) is defined
from CE# or WE# going high (whichever goes high first)to CE# or WE# going low (whichever goes low first). Hence,
tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
5. See Figure 5: Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.
6. See Figure 8: AC Waveform: Program and Erase Operations.
(1)
4.7
Erase and Program Timings
VPP
Note
2, 3
1.65 V–3.0 V
11.4 V–12.6 V
Symbol
tBWPB
Parameter
Typ(1)
Max
Typ(1)
Max
Unit
4-KW Parameter Block
Word Program Time
0.10
0.30
0.03
0.12
s
tBWMB
32-KW Main Block
Word Program Time
2, 3
0.8
2.4
0.24
1
s
tWHQV1 / tEHQV1
Word Program Time
2, 3
22
200
8
185
µs
s
tWHQV2 / tEHQV2
4-KW Parameter Block
Erase Time
2, 3
0.5
4
0.4
4
tWHQV3 / tEHQV3
32-KW Main Block
Erase Time
2, 3
1
5
0.6
5
s
tWHRH1 / tEHRH1
tWHRH2 / tEHRH2
Program Suspend Latency
Erase Suspend Latency
3
3
5
5
10
20
5
5
10
20
µs
µs
NOTES:
1. Typical values measured at TA = +25 °C and nominal voltages.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
32
PRELIMINARY
E
28F800C2, 28F160C2
A
B
C
D
E
F
VIH
VIL
ADDRESSES [A]
AIN
AIN
W5
W8
(Note 1)
VIH
CE# (WE#) [E(W)]
VIL
VIH
W2
W6
OE# [G]
VIL
W9
(Note 1)
VIH
VIL
WE# (CE) [W(E)]
W3
W4
W7
VIH
VIL
High Z
W1
Valid
SRD
DATA [D/Q]
DIN
DIN
DIN
VIH
VIL
RP# [P]
WP#
W12
W13
W11
VIH
VIL
W10
VPPH
2
1
VPPH
VPP [V]
VPPLK
VIL
NOTES:
1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register
Data.
A.
V
Power-Up and Standby.
CC
B. Write Program or Erase Setup Command.
C. Write Valid Address and Data (for Program) or Erase Confirm Command.
D. Automated Program or Erase Delay.
E. Read Status Register Data (SRD): reflects completed program/erase operation.
F. Write Read Array Command.
Figure 8. AC Waveform: Program and Erase Operations
33
PRELIMINARY
28F800C2, 28F160C2
4.8 Reset Operations
E
V
IH
RP# (P)
tPHQV
tPHWL
tPHEL
VIL
t PLPH
(A) Reset during Read Mode
Abort
Complete
t PLRH
tPHQV
tPHWL
tPHEL
VIH
VIL
RP# (P)
t PLPH
tPLPH
t PLRH
<
(B) Reset during Program or Block Erase,
Abort Deep
Complete Power-
tPHQV
tPHWL
tPHEL
Down
t PLRH
VIH
VIL
RP# (P)
t PLPH
(C) Reset Program or Block Erase,
>
t PLPH t PLRH
Figure 9. AC Waveform: Reset Operation
Table 11. Reset Specifications(1)
VCC 2.4 V–3.0 V
Symbol
Parameter
Notes
Min
100
Max
Unit
tPLPH
RP# Low to Reset during Read
(If RP# is tied to VCC, this specification is not
applicable)
2,4
ns
tPLRH1
RP# Low to Reset during Block Erase
3,4
22
µs
µs
tPLRH2
RP# Low to Reset during Program
3,4
12
NOTES:
1. See Section 3.1.4 for a full description of these conditions.
2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed.
3. If RP# is asserted while a block erase orword program operation is not executing, the reset will complete within 100 ns.
4. Sampled, but not 100% tested.
34
PRELIMINARY
E
28F800C2, 28F160C2
5.0 ORDERING INFORMATION
T E 2 8 F 1 6 0 C 2 T 1 0 0
Package
TE = 48-Lead TSOP
GT = 48-Ball µBGA* CSP
Access Speed (ns)
8/16 Mbit =100, 120
T = Top Blocking
B = Bottom Blocking
Product line designator
for all Intel® Flash products
Product Family
C2 = 2.4 V Advanced+ Boot Block
VCC = 2.4 V - 3.0 V
Device Density
160 = x16 (16 Mbit)
800 = x16 (8 Mbit)
VPP = 1.65 V - 3.0 V or 11.4 V - 12 V
VALID COMBINATIONS (All Extended Temperature)
Extended 16M TE28F160C2TA100
GT28F160C2TA100
TE28F160C2BA100
GT28F160C2BA100
TE28F160C2TA120
TE28F160C2BA120
GT28F160C2TA120
GT28F160C2BA120
Extended 8M
TE28F800C2TA100
TE28F800C2BA100
TE28F800C2TA120
TE28F800C2BA120
NOTE:
1.
The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the first
character signifies either “E” for engineering samples or “S” for silicon daisy chain samples. All other assembly codes
without an “E” or “S” as the first character are production units.
35
PRELIMINARY
28F800C2, 28F160C2
E
(1,2)
6.0 ADDITIONAL INFORMATION
Order Number
Document/Tool
298006
210830
297645
2.4 Volt Advanced+ Boot Block Flash Memory Specification Update
Flash Memory Databook
3 Volt Advanced+ Boot Block Flash Memory; 28F800C3, 28F160C3,
28F320C3 datasheet
292216
292215
AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory
AP-657 Designing with the Advanced+ Boot Block Flash Memory
Architecture
Contact your Intel
Representative
Flash Data Integrator (FDI) Software Developer’s Kit
297874
FDI Interactive: Play with Intel’s Flash Data Integrator on Your PC
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical documentation
and tools.
36
PRELIMINARY
E
28F800C2, 28F160C2
APPENDIX A
WSM CURRENT/NEXT STATES
Command Input (and Next State)
Current
State
SR.7 Data
Read
Array
(FFH)
Program
Setup
(10/40H)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0)
Read
Status
(70H)
Clear
Status
(50H)
When
Read
Read Array
“1”
“1”
“1”
“1”
“1”
“1”
“1”
“1”
“0”
“1”
Array Read Array Program Setup
Status Read Array Program Setup
Config Read Array Program Setup
Erase
Setup
Read Array
Read Array
Read Array
Read Array
Read
Status
Read
Array
Read Status
Erase
Setup
Read
Status
Read
Array
Read
Config.
Erase
Setup
Read
Status
Read
Array
Read Query
CFI
Read Array Program Setup
Lock Command Error
Erase
Setup
Read
Status
Read
Array
Lock Setup
Status
Lock
(Done)
Lock
Cmd. Error
Lock
(Done)
Lock Cmd. Error
Lock Cmd.
Error
Status Read Array Program Setup
Erase
Setup
Read Array
Read
Status
Read
Array
Lock Oper.
(Done)
Status Read Array Program Setup
Erase
Setup
Read Array
Read
Status
Read
Array
Prot. Prog.
Setup
Status
Protection Register Program
Prot. Prog.
(Not Done)
Status
Protection Register Program (Not Done)
Prot. Prog.
(Done)
Status Read Array Program Setup
Status
Erase
Setup
Read Array
Program
Read
Status
Read
Array
Prog. Setup
“1”
“0”
Program
(Not Done)
Status
Program (Not Done)
Prog. Sus.
Status
Program (Not Done)
Prog. Susp.
Status
“1”
“1”
“1”
“1”
“1”
Status Prog. Sus.
Read Array
Program Suspend
Read Array
Program
Prog. Sus.
Program
Prog. Sus. Prog. Sus.
Status Rd. Array
(Not Done) Rd. Array (Not Done)
Prog. Susp.
Read Array
Array
Prog. Sus.
Read Array
Program Suspend
Read Array
Program Prog. Sus. Program
Prog. Sus. Prog. Sus.
Status Rd. Array
(Not Done) Rd. Array (Not Done)
Program Prog. Sus. Program
Prog. Susp.
Read Config
Config Prog. Sus.
Read Array
Program Suspend
Read Array
Prog. Sus. Prog. Sus.
Status Rd. Array
(Not Done) Rd. Array (Not Done)
Prog. Susp.
Read Query
CFI
Prog. Sus.
Read Array
Program Suspend
Read Array
Program Prog. Sus. Program
Prog. Sus. Prog. Sus.
(Not Done) Rd. Array (Not Done)
Read Array
Status
Rd. Array
Status Read Array Program Setup
Erase
Setup
Read
Status
Read
Array
Program
(Done)
Erase Setup
“1”
“1”
“0”
“1”
“1”
“1”
“1”
“1”
Status
Status Read Array Program Setup
Status
Erase Command Error
Erase
Erase
Erase
Erase Command Error
(Not Done) Cmd. Error (Not Done)
Erase Cmd.
Error
Erase
Setup
Read Array
Read
Status
Read
Array
Erase
(Not Done)
Erase (Not Done)
Erase Sus.
Status
Erase (Not Done)
Ers. Susp.
Status
Status Erase Sus. Program Setup Ers. Sus.
Read Array Rd. Array
Erase
Erase
Erase
Erase
Ers. Sus.
Rd. Array
Erase
Erase
Erase
Erase
Erase Sus. Ers. Sus.
Status Rd. Array
Erase Susp.
Array
Array
Erase Sus. Program Setup Ers. Sus.
Read Array Rd. Array
Ers. Sus.
Rd. Array
Erase Sus. Ers. Sus.
Status Rd. Array
Ers. Susp.
Read Config
Config Erase Sus. Program Setup Ers. Sus.
Read Array Rd. Array
Ers. Sus.
Rd. Array
Erase Sus. Ers. Sus.
Status Rd. Array
Ers. Susp.
Read Query
CFI
Erase Sus. Program Setup Ers. Sus.
Ers. Sus.
Rd. Array
Erase Sus. Ers. Sus.
Read Array
Rd. Array
Status
Rd. Array
Erase
(Done)
Status Read Array Program Setup
Erase
Setup
Read Array
Read
Status
Read
Array
37
PRELIMINARY
28F800C2, 28F160C2
E
APPENDIX A
WSM CURRENT/NEXT STATES (Continued)
Command Input (and Next State)
Current State
Read Config
(90H)
Read Query
(98H)
Lock Setup
(60H)
Prot. Prog.
Setup (C0H)
Lock Confirm
(01H)
Lock Down
Confirm
(2FH)
Unlock
Confirm
(D0H)
Read Array
Read Status
Read Config.
Read Query
Read Config.
Read Config.
Read Config.
Read Config.
Read Query
Read Query
Read Query
Read Query
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Prot. Prog.
Setup
Read Array
Read Array
Read Array
Read Array
Prot. Prog.
Setup
Prot. Prog.
Setup
Prot. Prog.
Setup
Lock
Setup
Locking Command Error
Lock Operation (Done)
Read Array
Lock Cmd.
Error
Read Config.
Read Config.
Read Query
Read Query
Lock Setup
Lock Setup
Prot. Prog.
Setup
Lock Operation
(Done)
Prot. Prog.
Setup
Read Array
Prot. Prog.
Setup
Protection Register Program
Prot. Prog.
(Not Done)
Protection Register Program (Not Done)
Prot. Prog.
(Done)
Read Config.
Read Query
Lock Setup
Prot. Prog.
Setup
Read Array
Prog. Setup
Program
Program
Program (Not Done)
(Not Done)
Prog. Susp.
Status
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Program
(Not Done)
Prog. Susp.
Read Array
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program
(Not Done)
Prog. Susp.
Read Config.
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program
(Not Done)
Prog. Susp.
Read Query.
Prog. Susp.
Read Config.
Prog. Susp.
Read Query
Program
(Not Done)
Program
(Done)
Read Config.
Read Query
Lock Setup
Lock Setup
Prot. Prog.
Setup
Read Array
Read Array
Erase
Setup
Erase Command Error
Erase
(Not Done)
Erase Cmd.
Error
Read Config.
Read Query
Prot. Prog.
Setup
Erase
Erase (Not Done)
(Not Done)
Erase Suspend Erase Suspend Erase Suspend
Status Read Config. Read Query
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Lock Setup
Erase Suspend Read Array
Erase
(Not Done)
Erase Suspend Erase Suspend Erase Suspend
Array Read Config. Read Query
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Read Array
Erase
(Not Done)
Eras Sus. Read Erase Suspend Erase Suspend
Config Read Config. Read Query
Erase
(Not Done)
Eras Sus. Read Erase Suspend Erase Suspend
Erase
(Not Done)
Query
Read Config.
Read Query
Ers.(Done)
Read Config.
Read Query
Prot. Prog.
Setup
Read Array
38
PRELIMINARY
E
28F800C2, 28F160C2
APPENDIX B
PROGRAM/ERASE FLOWCHARTS
Start
Bus Operation
Write
Command
Program Setup
Program
Comments
Data = 40H
Write 40H
Data = Data to Program
Addr = Location to Program
Write
Program Address/Data
Read Status Register
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent programming operations.
No
SR.7 = 1?
Yes
SR Full Status Check can be done after each program or after a sequence of
program operations.
Write FFH after the last program operation to reset device to read array mode.
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
Standby
Command
Comments
Check SR.3
1
1 = VPP Low Detect
SR.3 =
VPP Range Error
Check SR.4
1 = VPP Program Error
Standby
0
SR.4 =
0
Check SR.1
1
1
1 = Attempted Program to
Locked Block - Program
Aborted
Standby
Programming Error
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
Attempted Program to
Locked Block - Aborted
SR.1 =
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases where multiple bytes are programmed before full status is checked.
0
If an error is detected, clear the status register before attempting retry or other
error recovery.
Program Successful
Figure 10. Automated Word Programming Flowchart
39
PRELIMINARY
28F800C2, 28F160C2
E
Bus
Operation
Command
Comments
Start
Program
Suspend
Data = B0H
Write
Write
Addr = X
Write B0H
Data=70H
Addr=X
Read Status
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Write 70H
Read
Addr = X
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
Read Status Register
Check SR.2
Standby
Write
1 = Program Suspended
0 = Program Completed
0
SR.7 =
SR.2 =
Data = FFH
Addr = X
Read Array
1
0
Read array data from block
other than the one being
programmed.
Program Completed
Read
1
Program
Resume
Data = D0H
Addr = X
Write
Write FFH
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Program Resumed
Read Array Data
Figure 11. Program Suspend/Resume Flowchart
40
PRELIMINARY
E
28F800C2, 28F160C2
Start
Bus Operation
Command
Comments
Data = 20H
Addr = Within Block to Be
Erased
Write
Erase Setup
Write 20H
Data = D0H
Write
Read
Erase Confirm
Addr = Within Block to Be
Erased
Write D0H and
Block Address
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read Status Register
Suspend
Erase Loop
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
No
0
Yes
SR.7 =
1
Suspend Erase
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase or after a sequence of
block erasures.
Full Status
Check if Desired
Write FFH after the last write operation to reset device to read array mode.
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
Command
Comments
Check SR.3
Standby
1
1 = VPP Low Detect
SR.3 =
VPP Range Error
Check SR.4,5
Standby
Standby
Standby
Both 1 = Command Sequence
Error
0
SR.4,5 =
0
1
1
1
Check SR.5
1 = Block Erase Error
Command Sequence
Error
Check SR.1
1 = Attempted Erase of
Locked Block - Erase Aborted
SR.5 =
0
Block Erase Error
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases
where multiple bytes are erased before full status is checked.
Attempted Erase of
Locked Block - Aborted
SR.1 =
0
If an error is detected, clear the status register before attempting retry or other
error recovery.
Block Erase
Successful
Figure 12. Automated Block Erase Flowchart
41
PRELIMINARY
28F800C2, 28F160C2
E
Bus
Operation
Command
Erase Suspend
Read Status
Comments
Start
Data = B0H
Write
Write
Addr = X
Write B0H
Data=70H
Addr=X
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Write 70H
Read
Addr = X
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
Read Status Register
Check SR.6
Standby
Write
1 = Erase Suspended
0 = Erase Completed
0
SR.7 =
SR.6 =
Data = FFH
Addr = X
Read Array
1
0
Read array data from block
other than the one being
erased.
Erase Completed
Read
1
Data = D0H
Addr = X
Write
Erase Resume
Write FFH
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Erase Resumed
Read Array Data
Figure 13. Erase Suspend/Resume Flowchart
42
PRELIMINARY
E
28F800C2, 28F160C2
Bus
Operation
Command
Comments
Start
Data = 60H
Addr = X
Write
Write
Config. Setup
Write 60H
(Configuration Setup)
Data= 01H (Lock Block)
D0H (Unlock Block)
2FH (Lockdown Block)
Addr=Within block to lock
Lock, Unlock,
or Lockdown
Write
01H, D0H, or 2FH
Write
Read
Data = 90H
(Optional)
Configuration Addr = X
Read
(Optional)
Block Lock
Status
Block Lock Status Data
Addr = Second addr of block
Write 90H
(Read Configuration)
Confirm Locking Change on
DQ1, DQ0. (See Block Locking
State Table for valid
Standby
(Optional)
combinations.)
Read Block Lock Status
Locking
Change
Confirmed?
No
Write FFh
(Read Array)
Locking Change
Complete
Figure 14. Locking Operations Flowchart
43
PRELIMINARY
28F800C2, 28F160C2
E
Start
Bus Operation
Write
Command
Comments
Protection Program
Setup
Data = C0H
Write C0H
(Protection Reg.
Program Setup)
Data = Data to Program
Addr = Location to Program
Write
Protection Program
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Write Protect. Register
Address/Data
Read
Check SR.7
Standby
1 = WSM Ready
0 = WSM Busy
Read Status Register
Protection Program operations can only be addressed within the protection
register address space. Addresses outside the defined space will return an
error.
No
SR.7 = 1?
Yes
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program or after a sequence of
program operations.
Full Status
Check if Desired
Write FFH after the last program operation to reset device to read array mode.
Program Complete
FULL STATUS CHECK PROCEDURE
Bus Operation
Standby
Command
Comments
SR.1 SR.3 SR.4
Read Status Register
Data (See Above)
0
1
1
VPP Low
1, 1
0
0
1
Prot. Reg.
Prog. Error
Standby
SR.3, SR.4 =
SR.1, SR.4 =
VPP Range Error
1
0
1
Register
Locked:
Aborted
0,1
1,1
Standby
Protection Register
Programming Error
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
Attempted Program to
Locked Register -
Aborted
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases of multiple protection register program operations before full status is
checked.
SR.1, SR.4 =
If an error is detected, clear the status register before attempting retry or other
error recovery.
Program Successful
Figure 15. Protection Register Programming Flowchart
44
PRELIMINARY
E
28F800C2, 28F160C2
APPENDIX C
COMMON FLASH INTERFACE QUERY STRUCTURE
This appendix defines the data structure or “database” returned by the Common Flash Interface (CFI) Query
command. System software should parse this structure to gain critical information such as block size, density,
x8/x16, and electrical specifications. Once this information has been obtained, the software will know which
command sets to use to enable flash writes, block erases, and otherwise control the flash component. The
Query is part of an overall specification for multiple command set and control interface descriptions called
Common Flash Interface, or CFI.
C.1
QUERY STRUCTURE OUTPUT
The Query “database” allows system software to gain information for controlling the flash component. This
section describes the device’s CFI-compliant interface that allows the host system to access Query data.
Query data are always presented on the lowest-order data outputs (DQ0-7) only. The numerical offset value is
the address relative to the maximum bus width supported by the device. On this family of devices, the Query
table device starting address is a 10h, which is a word address for x16 devices.
For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and ”R” in ASCII, appear on the
low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus,
the device outputs ASCII “Q” in the low byte (DQ0-7) and 00h in the high byte (DQ8-15).
At Query addresses containing two or more bytes of information, the least significant data byte is presented
at the lower address, and the most significant data byte is presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the “h” suffix
has been dropped. In addition, since the upper byte of word-wide devices is always “00h,” the leading “00”
has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can
be assumed to have 00h on the upper byte in this mode.
Table C1. Summary of Query Structure Output As a Function of Device and Mode
Device
Hex
Offset
Code ASCII
Value
Device Addresses
10:
11:
12:
51
52
59
“Q”
“R”
“Y”
45
PRELIMINARY
28F800C2, 28F160C2
E
Table C2. Example of Query Structure Output of x16 and x8 Devices
Word Addressing
Byte Addressing
Hex Code
Offset
Hex Code
Value
Offset
Value
A15–A0
D15–D0
A7–A0
D7–D0
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
...
0051
0052
0059
P_IDLO
P_IDHI
PLO
“Q”
“R”
“Y”
10h
11h
12h
13h
14h
15h
16h
17h
18h
...
51
52
59
P_IDLO
P_IDLO
P_IDHI
...
“Q”
“R”
“Y”
PrVendor
ID #
PrVendor
TblAdr
AltVendor
ID #
PrVendor
ID #
ID #
PHI
...
A_IDLO
A_IDHI
...
...
C.2
QUERY STRUCTURE OVERVIEW
The Query command causes the flash component to display the Common Flash Interface (CFI) Query
structure or “database.” The structure sub-sections and address locations are summarized below.
Table C3. Query Structure(1)
Offset
00h
Sub-Section Name
Description
Manufacturer Code
01h
Device Code
(BA+2)h(2)
04-0Fh
10h
Block Status Register
Block-Specific Information
Reserved
Reserved for Vendor-Specific Information
Command Set ID and Vendor Data Offset
Device Timing and Voltage Information
Flash Device Layout
CFI Query Identification String
System Interface Information
Device Geometry Definition
1Bh
27h
P(3)
Primary Intel-Specific Extended Query
Vendor-Defined Additional Information
Table
Specific to the Primary Vendor Algorithm
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of
device bus width and mode.
2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the block size is
32 Kword).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
46
PRELIMINARY
E
28F800C2, 28F160C2
C.3
BLOCK LOCK STATUS REGISTER
The Block Status Register indicates whether an erase operation completed successfully or whether a given
block is locked or can be accessed for flash program/erase operations
Block Erase Status (BSR.1) allows system software to determine the success of the last block erase
operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed
during an erase operation. This bit is only reset by issuing another erase operation to the block. The Block
Status Register is accessed from word address 02h within each block.
Table C4. Block Status Register
Offset
Length
Description
Block Lock Status Register
Add.
Value
(BA+2)h(1)
1
BA+2: --00 or --01
BA+2: (bit 0): 0 or 1
BSR.0 Block Lock Status
0 = Unlocked
1 = Locked
BSR.1 Block Lock-Down Status
0 = Not locked down
BA+2: (bit 1): 0 or 1
1 = Locked down
BSR 2–7: Reserved for future use
BA+2: (bit 2–7): 0
NOTES:
1. BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64KB block) beginning location in word mode).
C.4
CFI QUERY IDENTIFICATION STRING
The Identification String provides verification that the component supports the Common Flash Interface
specification. It also indicates the specification version and supported vendor-specified command set(s).
Table C5. CFI Identification
Offset
Length
Description
Query-unique ASCII string “QRY”
Add.
10h
3
10
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
13h
15h
17h
19h
2
2
2
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
47
PRELIMINARY
28F800C2, 28F160C2
C.5 SYSTEM INTERFACE INFORMATION
E
Table C6. System Interface Information
Offset Length
Description
Add.
Hex
Value
Code
1Bh
1
1
1
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1B:
--24
2.4 V
1Ch
1Dh
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1C:
1D:
--30
--B4
3.0 V
VPP [programming] supply minimum program/erase
voltage
11.4 V
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
1Eh
1
VPP [programming] supply maximum program/erase
1E:
--C6
12.6 V
voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
1Fh
20h
21h
22h
23h
1
1
1
1
1
“n” such that typical single word program time-out = 2n µs
“n” such that typical max. buffer write time-out = 2n µs
“n” such that typical block erase time-out = 2n ms
“n” such that typical full chip erase time-out = 2n ms
1F:
20:
21:
22:
23:
--05
--00
--0A
--00
--04
32 µs
NA
1 s
NA
“n” such that maximum word program time-out = 2n times
typical
512 µs
24h
25h
26h
1
1
1
“n” such that maximum buffer write time-out = 2n times
typical
24:
25:
26:
--00
--03
--00
NA
8 s
NA
“n” such that maximum block erase time-out = 2n times
typical
“n” such that maximum chip erase time-out = 2n times
typical
48
PRELIMINARY
E
28F800C2, 28F160C2
C.6
DEVICE GEOMETRY DEFINITION
Table C7. Device Geometry Definition
Description
Offset Length
Code See Table
below
27h
1
“n” such that device size = 2n in number of bytes
Flash device interface: x8 async x16 async x8/x16 async
28:00,29:00 28:01,29:00 28:02,29:00
27:
28h
2Ah
2Ch
2
28:
29:
2A:
2B:
2C:
--01
--00
--00
--00
--02
x16
0
2
1
“n” such that maximum number of bytes in write buffer = 2n
Number of erase block regions within device:
2
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions
with one or more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
2Dh
31h
4
4
Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2D:
2E:
2F:
30:
31:
32:
33:
34:
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Device Geometry Definition
Address
8 Mbit
16 Mbit
–B
–T
–B
–T
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
31:
32:
33:
34:
--14
--01
--00
--00
--00
--02
--07
--00
--20
--00
--0E
--00
--00
--01
--14
--01
--00
--00
--00
--02
--0E
--00
--00
--01
--07
--00
--20
--00
--15
--01
--00
--00
--00
--02
--07
--00
--20
--00
--1E
--00
--00
--01
--15
--01
--00
--00
--00
--02
--1E
--00
--00
--01
--07
--00
--20
--00
49
PRELIMINARY
28F800C2, 28F160C2
C.7 INTEL-SPECIFIC EXTENDED QUERY TABLE
E
Table C8. Primary-Vendor Specific Extended Query
Offset(1) Length
P = 35h
Description
(Optional flash features and commands)
Add.
Hex
Code
Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
3
Primary extended query table
Unique ASCII string “PRI”
35:
36:
37:
38:
39:
3A:
3B:
3C:
3D:
--50
--52
--49
--31
--30
--66
--00
--00
--00
“P”
“R”
“I”
1
1
4
Major version number, ASCII
“1”
“0”
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 9–31 are reserved; undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of optional features follows at
the end of the bit-30 field.
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 0 = 0
No
Yes
Yes
No
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 0
bit 8 = 0
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
No
Yes
Yes
No
bit 7 Page mode read supported
bit 8 Synchronous read supported
No
(P+9)h
1
2
Supported functions after suspend: Read Array, Status,
Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
3E:
--01
bit 0 Program supported after erase suspend
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
bit 0 = 1
Yes
(P+A)h
(P+B)h
3F:
40:
--03
--00
bit 0 = 1
bit 1 = 1
Yes
Yes
(P+C)h
1
VCC logic supply highest performance program/erase
voltage
41:
--30
3.0 V
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
(P+D)h
1
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
42:
--C0
12.0 V
bits 4–7 HEX value in volts
50
PRELIMINARY
E
28F800C2, 28F160C2
Table C9. Protection Register Information
Offset(1) Length
P = 35h
Description
(Optional flash features and commands)
Add.
Hex
Code
Value
(P+E)h
1
Number of Protection register fields in JEDEC ID space.
43:
--01
01
“00h,” indicates that 256 protection bytes are available
(P+F)h
(P+10)h
4
Protection Field 1: Protection Description
This field describes user-available One Time
Programmable
44:
45:
--80
--00
80h
00h
(P+11)h
(P+12)h
(OTP) Protection register bytes. Some are pre-
programmed
with device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register
Lock byte, the section’s first byte. The following bytes are
factory pre-programmed and user-programmable.
46:
47:
--03
--03
8 byte
8 byte
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed
bytes
bits 24–31 = “n” such that 2n = user programmable bytes
(P+13)h
Reserved for future use
48:
NOTES:
1. The variable P is a pointer which is defined at CFI offset 15h.
51
PRELIMINARY
28F800C2, 28F160C2
E
APPENDIX D
ARCHITECTURE BLOCK DIAGRAM
DQ0-DQ15
VCCQ
Output Buffer
Input Buffer
Identifier
Register
Status
Register
I/O Logic
CE#
WE#
OE#
RP#
Command
User
Interface
Power
Reduction
Control
Data
Comparator
WP#
A0-A19
Y-Decoder
Y-Gating/Sensing
Write State
Machine
Program/Erase
Voltage Switch
Input Buffer
VPP
Address
Latch
X-Decoder
VCC
GND
Address
Counter
52
PRELIMINARY
E
28F800C2, 28F160C2
APPENDIX E
WORD-WIDE MEMORY MAP DIAGRAMS
8-Mbit and 16-Mbit Word-Wide Memory Addressing
Top Boot
8M
Bottom Boot
8M
Size
(KW)
16M
Size
(KW)
16M
4
7F000-7FFFF
7E000-7EFFF
7D000-7DFFF
7C000-7CFFF
7B000-7BFFF
7A000-7AFFF
79000-79FFF
78000-78FFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
FF000-FFFFF
FE000-FEFFF
FD000-FDFFF
FC000-FCFFF
FB000-FBFFF
FA000-FAFFF
F9000-F9FFF
F8000-F8FFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
This column continues on next page
This column continues on next page
53
PRELIMINARY
28F800C2, 28F160C2
E
8-Mbit and 16-Mbit Word-Wide Memory Addressing (Continued)
Top Boot
8M
Bottom Boot
8M
Size
(KW)
16M
Size
(KW)
16M
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
4
4
4
4
4
4
4
54
PRELIMINARY
E
28F800C2, 28F160C2
APPENDIX F
DEVICE ID TABLE
Read Configuration Addresses and Data
Item
Manufacturer Code
Device Code
Address
Data
x16 00000
0089
8-Mbit x 16-T
x16 00001
x16 00001
x16 00001
x16 00001
88C0
88C1
88C2
88C3
8-Mbit x 16-B
16-Mbit x 16-T
16-Mbit x 16-B
NOTE: Other locations within the configuration address space are reserved by Intel for future use.
55
PRELIMINARY
28F800C2, 28F160C2
E
APPENDIX G
PROTECTION REGISTER ADDRESSING
Word-Wide Protection Register Addressing
Word
Use
Both
A7
1
A6
0
A5
0
A4
0
A3
0
A2
0
A1
A0
LOCK
0
0
1
1
0
0
1
1
0
0
0
1
2
3
4
5
6
7
Factory
Factory
Factory
Factory
User
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
User
1
0
0
0
0
1
0
User
1
0
0
0
0
1
1
User
1
0
0
0
1
0
0
NOTE:
1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A –A8 = 0.
21
56
PRELIMINARY
相关型号:
©2020 ICPDF网 联系我们和版权申明