TE28F640B3TC70 [INTEL]
Flash, 4MX16, 70ns, PDSO48, 12 X 20 MM, TSOP-48;
| 型号： | TE28F640B3TC70 |
| 厂家： | 
INTEL |
| 描述： | Flash, 4MX16, 70ns, PDSO48, 12 X 20 MM, TSOP-48 光电二极管 内存集成电路 |
| 文件： | 总71页 (文件大小：1145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® Advanced Boot Block Flash
Memory (B3)
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet
Product Features
• Flexible SmartVoltage Technology
—2.7 V – 3.6 V read/program/erase
• Intel® Flash Data Integrator Software
—Flash Memory Manager
—12 V V fast production programming
—System Interrupt Manager
PP
—Supports parameter storage, streaming
data (for example, voice)
• 1.65 V – .5 V or 2.7 V – 3.6 V I/O option
—Reduces overall system power
• Extended Cycling Capability
—Minimum 100,000 block erase cycles
• High Performance
—2.7 V – 3.6 V: 70 ns max access time
• Automatic Power Savings Feature
• Optimized Block Sizes
—Eight 8-KB blocks for data, top or
bottom locations
—Typical I
after bus inactivity
CCS
• Standard Surface Mount Packaging
—48-Ball CSP packages
—Up to 127 x 64-KB blocks for code
—40-Lead and 48-Lead TSOP packages
• Block Locking
—V -level control through Write Protect
• Density and Footprint Upgradeable for
common package
CC
WP#
—8-, 16-, 32-, and 64-Mbit densities
• Low Power Consumption
—9 mA typical read current
• ETOX™ VIII (0.13 µm) Flash
Technology
• Absolute Hardware-Protection
—16-Mbit and 32-Mbit densities
—V = GND option
PP
• ETOX™ VII (0.18 µm) Flash Technology
—V lockout voltage
CC
—16-, 32-, and 64-Mbit densities
• Extended Temperature Operation
—–40 °C to +85 °C
• ETOX ™ VI (0.25µm) Flash Technology
—8-, 16-, and 32-Mbit densities
• Automated Program and Block Erase
—Status registers
• Bo not use the x8 option for new designs
The Intel® Advanced Boot Block Flash Memory (B3) device, manufactured on the Intel 0.13 µm
and 0.18 µm technologies, is a feature-rich solution at a low system cost. The B3 device in x16 is
available in 48-lead TSOP and 48-ball CSP packages. The x8 option of this product family is
available only in 40-lead TSOP and 48-ball µBGA* packages. For additional information about
this product family, see the Intel website: http://www.intel.com/design/flash.
Notice: This specification is subject to change without notice. Verify with your local Intel sales
office that you have the latest datasheet before finalizing a design.
Order Number: 290580, Revision: 020
18 Aug 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel® Advanced Boot Block Flash Memory (B3) may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800
548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, the Intel logo, and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation.
18 Aug 2005
2
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Contents
1.0 Introduction ...............................................................................................................................7
1.1
1.2
Nomenclature .......................................................................................................................7
Conventions..........................................................................................................................8
2.0 Functional Overview ..............................................................................................................8
3.0 Functional Overview ..............................................................................................................9
3.1
3.2
Architecture Diagram..........................................................................................................10
Memory Maps and Block Organization...............................................................................11
3.2.1 Parameter Blocks ..................................................................................................11
3.2.2 Main Blocks ...........................................................................................................11
3.2.3 4-Mbit, 8-Mbit, 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Maps .............11
3.2.4 4-Mbit, 8-Mbit, and 16-Mbit Byte-Wide Memory Maps...........................................20
4.0 Package Information............................................................................................................24
4.1
4.2
4.3
mBGA* and Very Thin Profile Fine Pitch Ball Grid Array (VF BGA) Package ....................24
TSOP Package...................................................................................................................25
Easy BGA Package ............................................................................................................26
5.0 Pinout and Signal Descriptions.......................................................................................27
5.1
Signal Pinouts.....................................................................................................................27
5.1.1 40-Lead and 48-Lead TSOP Packages.................................................................27
Signal Descriptions .............................................................................................................30
5.2
6.0 Maximum Ratings and Operating Conditions ...........................................................32
6.1
6.2
Absolute Maximum Ratings................................................................................................32
Operating Conditions..........................................................................................................33
7.0 Electrical Specifications.....................................................................................................34
7.1
7.2
DC Current Characteristics.................................................................................................34
DC Voltage Characteristics.................................................................................................36
8.0 AC Characteristics................................................................................................................37
8.1
8.2
8.3
8.4
8.5
AC Read Characteristics ....................................................................................................37
AC Write Characteristics.....................................................................................................41
Erase and Program Timing.................................................................................................45
AC I/O Test Conditions.......................................................................................................46
Device Capacitance............................................................................................................46
9.0 Power and Reset Specifications .....................................................................................47
9.1
Power-Up/Down Characteristics.........................................................................................47
9.1.1 RP# Connected to System Reset ..........................................................................47
9.1.2
V
, V
and RP# Transitions..............................................................................47
CC
PP,
9.2
9.3
Reset Specifications ...........................................................................................................48
Power Supply Decoupling...................................................................................................49
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
3
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
9.4
Power Consumption ...........................................................................................................49
9.4.1 Active Power..........................................................................................................49
9.4.2 Automatic Power Savings (APS) ...........................................................................49
9.4.3 Standby Power ......................................................................................................49
9.4.4 Deep Power-Down Mode.......................................................................................50
10.0 Operations Overview ...........................................................................................................50
10.1 Bus Operations...................................................................................................................51
10.1.1 Read ......................................................................................................................51
10.1.2 Output Disable.......................................................................................................52
10.1.3 Standby..................................................................................................................52
10.1.4 Deep Power-Down / Reset....................................................................................52
10.1.5 Write ......................................................................................................................53
11.0 Operating Modes...................................................................................................................53
11.1 Read Array..........................................................................................................................54
11.2 Read Identifier ....................................................................................................................56
11.3 Read Status Register..........................................................................................................56
11.3.1 Clearing the Status Register..................................................................................57
11.4 Program Mode....................................................................................................................57
11.4.1 Suspending and Resuming Programming.............................................................58
11.5 Erase Mode ........................................................................................................................58
11.5.1 Suspending and Resuming Erase .........................................................................59
12.0 Block Locking.........................................................................................................................62
12.1 WP# = V for Block Locking...............................................................................................62
IL
12.2 WP# = V for Block Unlocking...........................................................................................62
IH
13.0 V Program and Erase Voltages...................................................................................63
PP
13.1
V
= V for Complete Protection......................................................................................63
PP IL
14.0 Additional Information ........................................................................................................63
Appendix A Write State Machine Current/Next States .................................................64
Appendix B Program and Erase Flowcharts ....................................................................66
Appendix C Ordering Information.........................................................................................70
18 Aug 2005
4
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision History
Revision
Number
Description
-001
Original version
Section 3.4, VPP Program and Erase Voltages, added
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
IPPR maximum specification change from ±25 µA to ±50 µA
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)
Minor wording changes
-002
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V VPP read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
-003
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A1–A20 = 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
V
CC and VCCQ absolute maximum specification = 3.7 V (Section 4.1)
Combined IPPW and ICCW into one specification (Section 4.4)
Combined IPPE and ICCE into one specification (Section 4.4)
Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7)
-004
Erase suspend time @ 12 V (tWHRH2 EHRH2) changed to 5 µs typical and 20 µs maximum
/t
(Section 4.7)
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
µBGA package diagrams corrected (Figures 3 and 4)
IPPD test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
-005
-006
µBGA package top side mark information added (Section 6)
VIH and VILSpecification change (Section 4.4)
I
CCS test conditions clarification (Section 4.4)
Added Command Sequence Error Note (Table 7)
Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
5
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision
Description
Number
Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions
-007
Corrected typographical error fixed in Ordering Information
4-Mbit packaging and addressing information corrected throughout document
Corrected 4-Mbit memory addressing tables in Appendices D and E
Max ICCD changed to 25 µA
-008
-009
-010
-011
VCCMax on 32 M (28F320B3) changed to 3.3 V
Added 64-Mbit density and faster speed offerings
Removed access time vs. capacitance load curve
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product
offering.
-012
Changed VccMax=3.3V reference to indicate the affected product is the 0.25µm 32Mbit
device.
Minor text edits throughout document.
Added New Pin-1 indicator information on 40 and 48Lead TSOP packages.
Minor text edits throughout document.
-013
-014
-015
Added specifications for 0.13 micron product offerings throughout document
Minor text edits throughout document.
Adjusted ordering information.
Adjusted specifications for 0.13 micron product offerings.
Revised and corrected DC Characteristics Table.
Adjusted package diagram information.
Minor text edits throughout document.
-016
-017
Updated ordering information.
Adjusted specifications for 0.13 micron product offerings.
Updated AC/DC Characteristics Table.
Added TSOP and µBGA* package diagram information.
Minor text edits throughout document.
-018
-019
-020
Updated the layout of the datasheet.
Added line items to Table 34 “Ordering Information: Valid Combinations” on page 70.
Removed all x8 products from ordering information, page 70
18 Aug 2005
6
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
1.0
Introduction
This datasheet describes the specifications for the Intel Advanced Boot Block Flash Memory (B3)
device (hereafter referred to as the B3 flash memory device).
The B3 flash memory device is optimized for portable, low-power, systems. This family of
products features 1.65 V to 2.5 V or 2.7 V to 3.6 V I/Os, and a low V /V operating range of
CC PP
2.7 V to 3.6 V for Read, Program, and Erase operations. The B3 device is also capable of fast
programming at 12 V.
Throughout this document:
• 2.7 V refers to the full voltage range 2.7 V to 3.6 V (except where noted otherwise).
• V = 12 V refers to 12 V ±5%.
PP
1.1
Nomenclature
Table 1.
Nomenclature
Term
Definition
Hexadecimal prefix
0x
0b
Binary prefix
Byte
Word
8 bits
16 bits
KW or Kword
Mword
Kb
1024 words
1,048,576 words
1024 bits
KB
1024 bytes
Mb
1,048,576 bits
MB
1,048,576 bytes
Automatic Power Savings
Chip Scale Package
Command User Interface
One Time Programmable
Protection Register
Protection Register Data
Protection Lock Register
Reserved for Future Use
Status Register
APS
CSP
CUI
OTP
PR
PRD
PLR
RFU
SR
SRD
WSM
Status Register Data
Write State Machine
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
7
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
1.2
Conventions
Table 2.
Conventions
Convention
Description
Used interchangeably to refer to the external signal connections on the
package.
Pin or signal
Note: For a chip scale package (CSP), the term ball is used in place of pin.
Square brackets designate group membership or define a group of signals
with similar function (for example, A[21:1], SR[4:1])
Group Membership Brackets
Set
When referring to registers, the term set means the bit is a logical 1.
When referring to registers, the term clear means the bit is a logical 0.
Clear:
A group of bits (or words) that erase simultaneously using one block erase
instruction.
Block
Main Block
A block that contains 32 Kwords.
A block that contains 4 Kwords.
Parameter Block
2.0
Functional Overview
The B3 flash memory device features the following:
• Enhanced blocking for easy segmentation of code and data or additional design flexibility.
• Program Suspend to Read command.
• V
input of 1.65 V to 2.5 V or 2.7 V to 3.6 V on all I/Os. See Figure 1 through Figure 4 for
CCQ
pinout diagrams and V
location.
CCQ
• Maximum program and erase time specification for improved data storage.
Table 3.
B3 Device Feature Summary (Sheet 1 of 2)
28F800B3, 28F160B3,
Feature
28F008B3, 28F016B3
Reference
28F320B3(3), 28F640B3
Section 6.2, Section
7.2
VCC Read Voltage
2.7 V– 3.6 V
V
CCQ I/O Voltage
1.65 V–2.5 V or 2.7 V– 3.6 V
2.7 V– 3.6 V or 11.4 V– 12.6 V
Section 4.2, 4.4
Section 4.2, 4.4
Table 27
VPP Program/Erase Voltage
Bus Width
8 bit
70 ns, 80 ns, 90 ns, 100 ns, 110 ns
512 Kbit x 16 (8 Mbit),
16 bit
Speed
Section 8.1
1024 Kbit x 16 (16 Mbit),
2048 Kbit x 16 (32 Mbit),
4096 Kbit x 16 (64 Mbit)
Memory Arrangement
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit)
Section 3.2
18 Aug 2005
8
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 3.
B3 Device Feature Summary (Sheet 2 of 2)
28F800B3, 28F160B3,
28F320B3(3), 28F640B3
Feature
28F008B3, 28F016B3
Reference
Eight 8-Kbyte parameter blocks and
Fifteen 64-Kbyte blocks (8 Mbit) or
Thirty-one 64-Kbyte main blocks (16 Mbit)
Section 3.2, “Memory
Maps and Block
Organization” on
page 11
Blocking (top or bottom)
Sixty-three 64-Kbyte main blocks (32 Mbit)
One hundred twenty-seven 64-Kbyte main blocks (64 Mbit)
WP# locks/unlocks parameter blocks
All other blocks protected using VPP
Section 12.0
Table 32
Locking
Section 6.2, Section
7.2
Operating Temperature
Program/Erase Cycling
Extended: –40 °C to +85 °C
Section 6.2, Section
7.2
100,000 cycles
48-Lead TSOP,
40-lead TSOP(1)
48-Ball µBGA* CSP(2)
,
Packages
48-Ball µBGA CSP(2)
,
Figure 8, Figure 9
48-Ball VF BGA
Notes:
1.
2.
3.
32-Mbit and 64-Mbit densities not available in 40-lead TSOP.
8-Mbit densities not available in µBGA* CSP.
VCCMax is 3.3 V on 0.25µm 32-Mbit devices.
3.0
Functional Overview
Intel provides the most flexible voltage solution in the flash industry, providing three discrete
voltage supply pins:
• V for Read operation
CC
• V
for output swing
CCQ
• V for Program and Erase operation.
PP
All B3 flash memory devices provide program/erase capability at 2.7 V or 12 V (for fast
production programming), and read with V at 2.7 V. Because many designs read from the flash
CC
memory a large percentage of the time, 2.7 V V operation can provide substantial power
CC
savings.
The B3 flash memory device family is available in either x8 or x16 packages in the following
densities (see Appendix C, “Ordering Information,” for availability):
• 8-Mbit (8, 388, 608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024
Kbytes of 8-bits each.
• 16-Mbit (16, 777, 216-bit) flash memory organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each.
• 32-Mbit (33, 554, 432-bit) flash memory organized as 2048 Kwords of 16 bits each.
• 64-Mbit (67, 108, 864-bit) flash memory organized as 4096 Kwords of 16 bits each.
The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix)
of the address map, to accommodate different microprocessor protocols for kernel code location.
The upper two (or lower two) parameter blocks can be locked to provide complete code security
for system initialization code. Locking and unlocking is controlled by Write Protect WP# (see
Section 12.0, “Block Locking” on page 62 for details).
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
9
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
• The Command User Interface (CUI) is the interface between the microprocessor or
microcontroller and the internal operation of the flash memory.
• The internal Write State Machine (WSM) automatically executes the algorithms and timings
necessary for Program and Erase operations (including verification), which unburdens the
microprocessor or microcontroller.
• To indicate the status of the WSM, the Status Register signifies block erase or word program
completion and status.
The B3 flash memory device also provides Automatic Power Savings (APS), which minimizes
system current drain and allows for very low power designs. This mode is entered following the
completion of a read cycle (approximately 300 ns later).
The RP# pin provides additional protection against unwanted command writes that might occur
during system reset and power-up/down sequences due to invalid system bus conditions (see
“Power and Reset Specifications” on page 47).
• Section 10.0, “Operations Overview” on page 50 explains the different modes of operation.
• Section 7.0, “Electrical Specifications” on page 34 and Section 8.0, “AC Characteristics” on
page 37 provide complete current and voltage specifications.
• Section 8.1, “AC Read Characteristics” on page 37 provides read, program, and erase
performance specifications.
3.1
Architecture Diagram
Figure 1.
B3 Architecture Block Diagram
DQ0-DQ15
VCCQ
Output Buffer
Input Buffer
Identifier
Register
Status
Register
I/O Logic
CE#
WE#
OE#
RP#
Command
User
Interface
Power
Reduction
Control
Data
Comparator
WP#
A0-A19
Y-Decoder
Y-Gating/Sensing
Write State
Machine
Program/Erase
Voltage Switch
Input Buffer
VPP
Address
Latch
X-Decoder
VCC
GND
Address
Counter
18 Aug 2005
10
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.2
Memory Maps and Block Organization
The B3 flash memory device uses an asymmetrically blocked architecture, enabling system
integration of code and data within a single flash memory device. Each block can be erased
independently of other blocks up to 100,000 times. For the address locations of each block, see the
following memory maps:
• Table 4 “16-Mbit and 32-Mbit Word-Wide Memory Addressing Map” on page 11
• Table 5 “4-Mbit and 8-Mbit Word-Wide Memory Addressing Map” on page 14
• Table 6 “16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map” on page 15
• Table 7 “8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map” on page 20
• Table 8 “4-Mbit Byte Wide Memory Addressing Map” on page 23
3.2.1
3.2.2
Parameter Blocks
The B3 flash memory device architecture includes parameter blocks to facilitate storing frequently
updated small parameters (such as data traditionally stored in an EEPROM). The word-rewrite
functionality of EEPROMs can be emulated using software techniques. Each flash memory device
contains eight parameter blocks of 8 Kbytes/4 Kwords (8192 bytes/4,096 words) each.
Main Blocks
After the parameter blocks, the remainder of the flash memory array is divided into equal-size main
blocks (65,536 bytes/32,768 words) for data or code storage.
• The 8-Mbit flash memory device contains 15 main blocks.
• The 16-Mbit flash memory device contains 31 main blocks.
• The 32-Mbit memory device contains 63 main blocks.
• The 64-Mbit memory device contains 127 main blocks.
3.2.3
4-Mbit, 8-Mbit, 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Maps
Table 4.
16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing
Top Boot
16 Mbit
Bottom Boot
16 Mbit
Size
(KW)
Size
(KW)
32 Mbit
8 Mbit
32 Mbit
4
4
FF000-FFFFF
FE000-FEFFF
1FF000-1FFFFF
1FE000-1FEFFF
32
32
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-
1EFFFF
4
4
FD000-FDFFF
FC000-FCFFF
1FD000-1FDFFF
1FC000-1FCFFF
32
32
1E0000-
1E7FFF
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
11
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 4.
16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 2 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
16 Mbit
Size
(KW)
Size
(KW)
16 Mbit
32 Mbit
8 Mbit
32 Mbit
1D8000-
1DFFFF
4
4
FB000-FBFFF
FA000-FAFFF
F9000-F9FFF
F8000-F8FFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
1FB000-1FBFFF
1FA000-1FAFFF
1F9000-1F9FFF
1F8000-1F8FFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
32
32
32
32
32
32
32
32
1D0000-
1D7FFF
1C8000-
1CFFFF
4
1C0000-
1C7FFF
4
1B8000-
1BFFFF
32
32
32
32
1B0000-
1B7FFF
1A8000-
1AFFFF
1A0000-
1A7FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
F8000-FFFFF 0F8000-0FFFFF
F0000-F7FFF
0F0000-0F7FFF
18 Aug 2005
12
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 4.
16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 3 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing
Top Boot
16 Mbit
Bottom Boot
16 Mbit
Size
(KW)
Size
(KW)
32 Mbit
8 Mbit
32 Mbit
0E8000-
0EFFFF
32
32
32
32
32
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
32
32
32
32
32
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
0E0000-
0E7FFF
0D8000-
0DFFFF
0D0000-
0D7FFF
0C8000-
0CFFFF
This column continues on next page
0F8000-0FFFFF
This column continues on next page
C0000-C7FFF
0C0000-
0C7FFF
32
32
32
32
32
32
32
32
32
32
0B8000-
0BFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
0B0000-
0B7FFF
0A8000-
0AFFFF
0A0000-
0A7FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
13
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
e 4.
16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 4 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing
Top Boot
16 Mbit
Bottom Boot
16 Mbit
e
W)
Size
(KW)
32 Mbit
8 Mbit
32 Mbit
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
4
4
4
4
4
4
4
4
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
Table 5.
4-Mbit and 8-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 2)
4-Mbit and 8-Mbit Word-Wide Memory Addressing
Top Boot
Bottom Boot
8 Mbit
Size
(KW)
Size
(KW)
4 Mbit
4 Mbit
3F000-3FFFF
3E000-3EFFF
3D000-3DFFF
3C000-3CFFF
3B000-3BFFF
3A000-3AFFF
39000-39FFF
38000-38FFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
7F000-7FFFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
78000-7FFFF
7E000-7EFFF
7D000-7DFFF
7C000-7CFFF
7B000-7BFFF
7A000-7AFFF
79000-79FFF
78000-78FFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
4
4
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
4
4
4
4
4
4
32
32
32
32
4
4
4
4
18 Aug 2005
14
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 5.
4-Mbit and 8-Mbit Word-Wide Memory Addressing Map (Sheet 2 of 2)
4-Mbit and 8-Mbit Word-Wide Memory Addressing
Bottom Boot
Top Boot
Size
(KW)
Size
(KW)
4 Mbit
4 Mbit
8 Mbit
32
32
32
10000-17FFF
4
4
4
02000-02FFF
01000-01FFF
00000-00FFF
02000-02FFF
01000-01FFF
00000-00FFF
08000-0FFFF
00000-07FFF
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot
32 Mbit
Bottom Boot
32 Mbit
Size
(KW)
Size
(KW)
16 Mbit
64 Mbit
16 Mbit
64 Mbit
1FF000-
1FFFFF
3F8000-
3FFFFF
4
4
FF000-FFFFF
FE000-FEFFF
FD000-FDFFF
FC000-FCFFF
FB000-FBFFF
FA000-FAFFF
F9000-F9FFF
F8000-F8FFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
3FF000-3FFFFF
3FE000-3FEFFF
3FD000-3FDFFF
3FC000-3FCFFF
3FB000-3FBFFF
3FA000-3FAFFF
3F9000-3F9FFF
3F8000-3F8FFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1FE000-
1FEFFF
3F0000-
3F7FFF
1FD000-
1FDFFF
3E8000-
3EFFFF
4
1FC000-
1FCFFF
3E0000-
3E7FFF
4
1FB000-
1FBFFF
3D8000-
3DFFFF
4
1FA000-
1FAFFF
3D0000-
3D7FFF
4
1F9000-
1F9FFF
3C8000-
3CFFFF
4
1F8000-
1F8FFF
3C0000-
3C7FFF
4
1F0000-
1F7FFF
3B8000-
3BFFFF
32
32
32
32
32
32
32
32
1E8000-
1EFFFF
3B0000-
3B7FFF
1E0000-
1E7FFF
3A8000-
3AFFFF
1D8000-
1DFFFF
3A0000-
3A7FFF
1D0000-
1D7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
1C8000-
1CFFFF
1C0000-
1C7FFF
1B8000-
1BFFFF
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
15
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 2 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
32 Mbit
Size
(KW)
Size
(KW)
16 Mbit
32 Mbit
64 Mbit
16 Mbit
64 Mbit
1B0000-
1B7FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
1A8000-
1AFFFF
1A0000-
1A7FFF
198000-
19FFFF
190000-
197FFF
188000-
18FFFF
180000-
187FFF
178000-
17FFFF
170000-
177FFF
168000-
16FFFF
160000-
167FFF
158000-
15FFFF
150000-
157FFF
148000-
14FFFF
140000-
147FFF
138000-
13FFFF
130000-
137FFF
2F8000-
2FFFFF
128000-
12FFFF
2F0000-
2F7FFF
120000-
127FFF
2E8000-
2EFFFF
2E0000-
2E7FFF
118000-11FFFF 318000-31FFFF
110000-117FFF 310000-317FFF
2D8000-
2DFFFF
18 Aug 2005
16
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 3 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot
32 Mbit
Bottom Boot
32 Mbit
Size
(KW)
Size
(KW)
16 Mbit
64 Mbit
16 Mbit
64 Mbit
108000-
10FFFF
2D0000-
2D7FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
08000-0FFFF
00000-07FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
100000-
107FFF
2C8000-
2CFFFF
0F8000-
0FFFFF
2C0000-
2C7FFF
0F0000-
0F7FFF
2B8000-
2BFFFF
0E8000-
0EFFFF
2B0000-
2B7FFF
0E0000-
0E7FFF
2A8000-
2AFFFF
0D8000-
0DFFFF
2A0000-
2A7FFF
0D0000-
0D7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
0C8000-
0CFFFF
0C0000-
0C7FFF
0B8000-
0BFFFF
0B0000-
0B7FFF
0A8000-
0AFFFF
0A0000-
0A7FFF
098000-
09FFFF
090000-
097FFF
088000-
08FFFF
080000-
087FFF
078000-
07FFFF
070000-
077FFF
068000-
06FFFF
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
17
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 4 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW)
Size
(KW)
16 Mbit
32 Mbit
64 Mbit
16 Mbit
32 Mbit
64 Mbit
060000-
067FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-21FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
058000-
05FFFF
050000-
057FFF
048000-
04FFFF
040000-
047FFF
038000-
03FFFF
030000-
037FFF
1F8000-
1FFFFF
1F8000-
1FFFFF
028000-
02FFFF
1F0000-
1F7FFF
1F0000-
1F7FFF
020000-
027FFF
1E8000-
1EFFFF
1E8000-
1EFFFF
018000-
01FFFF
1E0000-
1E7FFF
1E0000-
1E7FFF
010000-
017FFF
1D8000-
1DFFFF
1D8000-
1DFFFF
008000-
00FFFF
1D0000-
1D7FFF
1D0000-
1D7FFF
000000-
007FFF
1C8000-
1CFFFF
1C8000-
1CFFFF
1C0000-
1C7FFF
1C0000-
1C7FFF
1B8000-
1BFFFF
1B8000-
1BFFFF
1B0000-
1B7FFF
1B0000-
1B7FFF
1A8000-
1AFFFF
1A8000-
1AFFFF
1A0000-
1A7FFF
1A0000-
1A7FFF
32
32
32
32
32
32
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
32
32
32
32
32
32
198000-19FFFF 198000-19FFFF
190000-197FFF 190000-197FFF
188000-18FFFF 188000-18FFFF
180000-187FFF 180000-187FFF
178000-17FFFF 178000-17FFFF
170000-177FFF 170000-177FFF
18 Aug 2005
18
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 5 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot
32 Mbit
Bottom Boot
32 Mbit
Size
(KW)
Size
(KW)
16 Mbit
64 Mbit
16 Mbit
64 Mbit
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
168000-16FFFF 168000-16FFFF
160000-167FFF 160000-167FFF
158000-15FFFF 158000-15FFFF
150000-157FFF 150000-157FFF
148000-14FFFF 148000-14FFFF
140000-147FFF 140000-147FFF
138000-13FFFF 138000-13FFFF
130000-137FFF 130000-137FFF
128000-12FFFF 128000-12FFFF
120000-127FFF 120000-127FFF
118000-11FFFF 118000-11FFFF
110000-117FFF 110000-117FFF
108000-10FFFF 108000-10FFFF
100000-107FFF 100000-107FFF
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
F8000-FFFFF
F0000-F7FFF
E8000-EFFFF
E0000-E7FFF
D8000-DFFFF
D0000-D7FFF
C8000-CFFFF
C0000-C7FFF
B8000-BFFFF
B0000-B7FFF
A8000-AFFFF
A0000-A7FFF
98000-9FFFF
90000-97FFF
88000-8FFFF
80000-87FFF
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
19
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 6.
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 6 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
32 Mbit
Size
(KW)
Size
(KW)
16 Mbit
64 Mbit
16 Mbit
32 Mbit
64 Mbit
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
32
32
32
32
32
32
32
32
32
32
4
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
50000-57FFF
48000-4FFFF
40000-47FFF
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
4
4
4
4
4
4
4
3.2.4
4-Mbit, 8-Mbit, and 16-Mbit Byte-Wide Memory Maps
Table 7.
8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 1 of 3)
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing
Top Boot
8 Mbit
Bottom Boot
8 Mbit
Size (KB)
16 Mbit
Size (KB)
16 Mbit
8
8
8
8
8
8
8
8
FE000-FFFFF
FC000-FDFFF
FA000-FBFFF
F8000-F9FFF
F6000-F7FFF
F4000-F5FFF
F2000-F3FFF
F0000-F1FFF
1FE000-1FFFFF
1FC000-1FDFFF
1FA000-1FBFFF
1F8000-1F9FFF
1F6000-1F7FFF
1F4000-1F5FFF
1F2000-1F3FFF
1F0000-1F1FFF
64
64
64
64
64
64
64
64
18 Aug 2005
20
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 7.
8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 2 of 3)
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing
Top Boot Bottom Boot
8 Mbit
Size (KB)
8 Mbit
16 Mbit
Size (KB)
16 Mbit
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
E0000-EFFFF
D0000-DFFFF
C0000-CFFFF
B0000-BFFFF
A0000-AFFFF
90000-9FFFF
80000-8FFFF
70000-7FFFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
00000-0FFFF
1E0000-1EFFFF
1D0000-1DFFFF
1C0000-1CFFFF
1B0000-1BFFFF
1A0000-1AFFFF
190000-19FFFF
180000-18FFFF
170000-17FFFF
160000-16FFFF
150000-15FFFF
140000-14FFFF
130000-13FFFF
120000-12FFFF
110000-11FFFF
100000-10FFFF
0F0000-0FFFFF
0E0000-0EFFFF
0D0000-0DFFFF
0C0000-0CFFFF
0B0000-0BFFFF
0A0000-0AFFFF
090000-09FFFF
080000-08FFFF
070000-07FFFF
060000-06FFFF
050000-05FFFF
040000-04FFFF
030000-03FFFF
020000-02FFFF
010000-01FFFF
000000-00FFFF
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
1F0000-1FFFFF
1E0000-1EFFFF
1D0000-1DFFFF
1C0000-1CFFFF
1B0000-1BFFFF
1A0000-1AFFFF
190000-19FFFF
180000-18FFFF
170000-17FFFF
160000-16FFFF
150000-15FFFF
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
21
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 7.
8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 3 of 3)
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing
Top Boot Bottom Boot
8 Mbit 8 Mbit
Size (KB)
16 Mbit
Size (KB)
16 Mbit
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
8
140000-14FFFF
130000-13FFFF
120000-12FFFF
110000-11FFFF
100000-10FFFF
0F0000-0FFFFF
0E0000-0EFFFF
0D0000-0DFFFF
0C0000-0CFFFF
0B0000-0BFFFF
0A0000-0AFFFF
090000-09FFFF
080000-08FFFF
070000-07FFFF
060000-06FFFF
050000-05FFFF
040000-04FFFF
030000-03FFFF
020000-02FFFF
010000-01FFFF
00E000-00FFFF
00C000-00DFFF
00A000-00BFFF
008000-009FFF
006000-007FFF
004000-005FFF
002000-003FFF
000000-001FFF
F0000-FFFFF
E0000-EFFFF
D0000-DFFFF
C0000-CFFFF
B0000-BFFFF
A0000-AFFFF
90000-9FFFF
80000-8FFFF
70000-7FFFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
8
8
8
8
8
8
8
18 Aug 2005
22
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 8.
4-Mbit Byte Wide Memory Addressing Map
4-Mbit Byte-Wide Memory Addressing
Top Boot
Bottom Boot
Size
(KB)
Size
(KB)
4 Mbit
4 Mbit
8
8
7E000-7FFFF
7C000-7DFFF
7A000-7BFFF
78000-79FFF
76000-77FFF
74000-75FFF
72000-73FFF
70000-71FFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
00000-0FFFF
64
64
64
64
64
64
64
8
70000-7FFFF
60000-6FFFF
50000-5FFFF
40000-4FFFF
30000-3FFFF
20000-2FFFF
10000-1FFFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
8
8
8
8
8
8
64
64
64
64
64
64
64
8
8
8
8
8
8
8
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
23
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.0
Package Information
4.1
µBGA* and Very Thin Profile Fine Pitch Ball Grid Array
(VF BGA) Package
Figure 2.
µBGA* and VF BGA Package Drawing
Ball A1
Corner
Ball A1
Corner
D
S1
S2
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
B
C
D
A
B
C
E
D
E
F
e
E
F
b
Top View - Bump Side down
Bottom View -Bump side up
A
1
A2
A
Seating
Plan
Y
Side View
Note: Drawing not to scale
Millimeters
Nom
Inches
Nom
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length 8M (.25)
Package Body Length 16M (.25/.18/.13) 32M (.25/.18/.13)
Package Body Length 64M (.18)
Package Body Width 8M (.25)
Package Body Width 16M (.25/.18/.13) 32M (.18/.13)
Package Body Width 32M (.25)
Package Body Width 64M (.18)
Symbol
A
A1
A2
b
D
D
D
E
E
E
E
e
Min
Max
Min
Max
0.0394
1.000
0.150
0.0059
0.0128
0.665
0.375
7.910
7.286
7.700
6.500
6.964
10.850
9.000
0.750
46
0.0262
0.0148
0.325
7.810
7.186
7.600
6.400
6.864
0.425
8.010
7.386
7.800
6.600
7.064
10.860
9.100
0.0167
0.2829
0.2992
0.2520
0.2702
0.4232
0.3504
0.2868
0.3031
0.2559
0.2742
0.4272
0.3543
0.0295
46
0.2908
0.3071
0.2598
0.2781
0.4276
0.3583
10.750
8.900
Pitch
Ball (Lead) Count 8M, 16M
N
Ball (Lead) Count 32M
N
47
47
Ball (Lead) Count 64M
N
48
48
Seating Plane Coplanarity
Y
0.100
1.430
1.118
1.325
1.475
1.707
3.650
2.725
0.0039
0.0563
0.0440
0.0522
0.0581
0.0672
0.1437
0.1073
Corner to Ball A1 Distance Along D 8M (.25)
Corner to Ball A1 Distance Along D 16M (.25/.18/.13) 32M (.18/.13)
Corner to Ball A1 Distance Along D 64M (.18)
Corner to Ball A1 Distance Along E 8M (.25)
Corner to Ball A1 Distance Along E 16M (.25/.18/.13) 32M (.18/.13)
Corner to Ball A1 Distance Along E 32M (.25)
Corner to Ball A1 Distance Along E 64M (.18)
S1
S1
S1
S2
S2
S2
S2
1.230
0.918
1.125
1.275
1.507
3.450
2.525
1.330
1.018
1.225
1.375
1.607
3.550
2.625
0.0484
0.0361
0.0443
0.0502
0.0593
0.1358
0.0994
0.0524
0.0401
0.0482
0.0541
0.0633
0.1398
0.1033
18 Aug 2005
24
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.2
TSOP Package
Figure 3.
TSOP Package Drawing
Z
A
2
See Notes 1, 2, 3 and 4
Pin 1
e
See Detail B
E
Y
D
1
A
1
D
Seating
Plane
See Detail A
A
Detail A
Detail B
C
b
0
L
A5568-02
Dimensions
Family: Thin Small Ou-Lt ine Package
Symbol
Millimeters
Nom
Inches
Nom
Min
Max
1.200
Notes
Min
Max
Notes
Package Height
Standoff
A
A1
A2
b
0.047
0.050
0.002
Package Body Thickness
Lead Width
0.950 1.000 1.050
0.150 0.200 0.300
0.037 0.039 0.041
0.006 0.008 0.012
Lead Thickness
Plastic Body Length
Package Body Width
Lead Pitch
c
D1
E
0.100 0.150 0.200
18.200 18.400 18.600
11.800 12.000 12.200
0.500
0.004 0.006 0.008
0.717 0.724 0.732
0.465 0.472 0.480
0.0197
e
Terminal Dimension
Lead Tip Length
D
L
19.800 20.000 20.200
0.500 0.600 0.700
48
0.780 0.787 0.795
0.020 0.024 0.028
48
Lead Count
N
Ø
Y
Lead Tip Angle
0°
3°
5°
0°
3°
5°
Seating Plane Coplanarity
Lead to Package Offset
0.100
0.004
Z
0.150 0.250 0.350
0.006 0.010 0.014
Notes:
1.
2.
3.
One dimple on package denotes Pin 1.
If two dimples, then the larger dimple denotes Pin 1.
Pin 1 is in the upper left corner of the package, in reference to the product mark.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
25
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.3
Easy BGA Package
Figure 4.
Easy BGA Package Drawing
Ball A1
Corner
Ball A1
Corner
D
S1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
A
B
C
D
E
b
e
E
F
F
G
H
G
H
Top View - Ball side down
A1
Bottom View - Ball Side Up
A2
A
Seating
Plane
Y
Side View
Note: Drawing not to scale
Dimensions Table
Millimeters
Min
Inches
Min
Symbol
A
Nom
Max Notes
1.200
Nom
Max
Package Height
0.0472
Ball Height
A1
0.250
0.0098
2
Package Body Thickness
Ball (Lead) Width
Package Body Width
Package Body Length
Pitch
Ball (Lead) Count
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
A
0.780
0.430
10.000
13.000
1.000
64
0.0307
0.0169
0.3937
0.5118
0.0394
64
b
D
E
[e]
N
Y
S1
0.330
9.900
12.900
0.530
10.100
13.100
0.0130
0.3898
0.5079
0.0209
0.3976
0.5157
1
1
0.100
1.600
3.100
0.0039
0.0630
0.1220
1.400
2.900
1.500
3.000
1
1
0.0551
0.1142
0.0591
0.1181
2
S
Note: (1) Package dimensions are for reference only. These dimensions are estimates based
on die size, and are subject to change.
18 Aug 2005
26
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
5.0
Pinout and Signal Descriptions
This section explains the package pinout and signal descriptions.
5.1
Signal Pinouts
The B3 flash memory device is available in the following packages:
• 40-lead TSOP (x8, Figure 5).
• 48-lead TSOP (x16, Figure 6).
• 48-ball µBGA (x8 in Figure 8 and x16 in Figure 9).
• 48-ball VF BGA (x16, Figure 9).
5.1.1
40-Lead and 48-Lead TSOP Packages
Figure 5.
40-Lead TSOP Package for x8 Configurations
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
A20
A19
A10
16 M
8 M
DQ7
DQ6
DQ5
DQ4
VCCQ
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
GND
CE#
A0
A8
Advanced Boot Block
40-Lead TSOP
10 mm x 20 mm
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
TOP VIEW
4 M
A2
A1
Notes:
1.
2.
40-Lead TSOP available for 8-Mbit and 16-Mbit densities only.
Lower densities have NC on the upper address pins. For example, an 8-Mbit device has NC on Pin 38.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
27
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 6.
48-Lead TSOP Package for x16 Configurations
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
A8
64 M
32 M
A21
A20
WE#
RP#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
16 M
Figure 7.
New Mark for Pin-1 Indicator: 40-Lead 8/16 Mb TSOP and 48-Lead 8/16/32 Mb TSOP
New Mark:
Note:
The topside marking on 8-Mb, 16-Mb, and 32-Mb Intel Advanced Boot Block 40L and 48L
TSOP products changed to a white ink triangle as a Pin-1 indicator. Products without the white
triangle continue to use a dimple as a Pin-1 indicator. No other changes were made in package size,
materials, functionality, customer handling, or manufacturability. The product continues to meet
stringent Intel quality requirements. Table 9 lists the ordering codes of the affected products. See
also Table 34 “Ordering Information: Valid Combinations” on page 70.
18 Aug 2005
28
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 9.
B3 Flash Memory Device Ordering Information
Ordering Information Valid Combinations
40-Lead TSOP
48-Lead TSOP
Ext. Temp. 64
Mbit
TE28F640B3TC70
TE28F640B3BC70
TE28F320B3TD70
TE28F320B3TC70
TE28F320B3TC90
TE28F320B3TA100
TE28F320B3TA110
TE28F160B3TC70
TE28F160B3TC80
TE28F160B3TA90
TE28F160B3TA110
TE28F800B3TA90
TE28F800B3TA110
TE28F320B3BD70
TE28F320B3BC70
TE28F320B3BC90
TE28F320B3BA100
TE28F320B3BA110
TE28F160B3BC70
TE28F160B3BC80
TE28F160B3BA90
TE28F160B3BA110
TE28F800B3BA90
TE28F800B3BA110
Ext. Temp. 32
Mbit
Ext. Temp. 16
Mbit
TE28F016B3TA90
TE28F016B3BA90
TE28F016B3BA110
TE28F008B3BA90
TE28F008B3BA110
TE28F016B3TA110
TE28F008B3TA90
TE28F008B3TA110
Ext. Temp. 8
Mbit
Figure 8.
x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
1
2
3
4
5
6
7
8
16M
A
B
C
D
E
F
A14
A12
A8
VPP
WP#
A20
A7
A5
A4
A2
8M
A15
A16
A10
A13
NC
WE#
A9
RP#
A19
A18
A6
A3
A1
A17
D5
NC
NC
D4
D2
D3
NC
NC
NC
CE#
D0
A0
VCCQ
GND
A11
D7
D6
GND
OE#
NC
VCC
D1
Notes:
1.
A19 and A20 indicate the upgrade address connections. Lower density devices do not have the upper
address solder balls. Do not route is not done in this area. A20 is the upgrade address for the 16-Mbit
device.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
29
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 9.
x16 48-Ball VF BGA and µBGA* Chip Size Package (Top View, Ball Down)
1
2
3
4
5
6
7
8
16M
A
B
C
D
E
F
A13
A11
A8
VPP
WP#
A19
A7
A4
A14
A15
A16
VCCQ
Vss
A10
A12
D14
D15
D7
WE#
A9
RP#
A21
D11
D12
D4
A18
A20
D2
A17
A6
A5
A3
A2
A1
64M
32M
D5
D8
CE#
D0
A0
D6
D3
D9
Vss
OE#
D13
VCC
D10
D1
Notes:
1.
A19, A20, and A21 indicate the upgrade address connections. Lower density devices do not have the
upper address solder balls. Do not route in this area.
– A19 is the upgrade address for the 16-Mbit device.
– A20 is the upgrade address for the 32-Mbit device.
– A21 is the upgrade address for the 64-Mbit device.
2.
Table 10 “B3 Flash memory Device Signal Descriptions” on page 31 details the usage of each device
pin.
5.2
Signal Descriptions
Table 10 describes the active signals.
18 Aug 2005
30
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 10.
B3 Flash memory Device Signal Descriptions (Sheet 1 of 2)
Symbol
Type
Description
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or
erase cycle.
A0–A21
Input
28F008B3: A[0-19], 28F016B3: A[0-20],
28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20], 28F640B3: A[0-21]
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a
Program command.
Input/
Output
•
Inputs commands to the Command User Interface when CE# and WE# are active. Data is
internally latched.
DQ0–DQ7
•
Outputs array, identifier and Status Register data. The data pins float to tristate when the chip
is deselected or the outputs are disabled.
DATA INPUTS/OUTPUTS:
•
Inputs array data on the second CE# and WE# cycle during a Program command. Data is
internally latched.
Input/
Output
DQ8–DQ15
•
Outputs array and identifier data. The data pins float to tristate when the chip is de-selected.
Not included on x8 products.
CHIP ENABLE: Activates the internal control logic, input buffers, decoders, and sense amplifiers.
CE# is active low. CE# high de-selects the memory device and reduces power consumption to
standby levels.
CE#
Input
OUTPUT ENABLE: Enables the flash memory device outputs through the data buffers during a
Read operation. OE# is active low.
OE#
WE#
Input
Input
WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active
low. Addresses and data are latched on the rising edge of the second WE# pulse.
RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep power-
down mode.
•
When RP# is at logic low, the flash memory device is in reset/deep power-down mode,
which drives the outputs to High-Z, resets the Write State Machine, and minimizes current
levels (ICCD).
RP#
Input
Input
•
When RP# is at logic high, the flash memory device is in standard operation. When
RP# transitions from logic-low to logic-high, the flash memory device defaults to the read
array mode.
WRITE PROTECT: Locks and unlocks the two lockable parameter blocks.
•
When WP# is at logic low, the lockable blocks are locked, preventing Program and Erase
operations to those blocks. If a Program or Erase operation is attempted on a locked block,
SR.1 and either SR.4 [program] or SR.5 [erase] are set to indicate the operation failed.
WP#
•
When WP# is at logic high, the lockable blocks are unlocked and can be programmed or
erased.
See Section 12.0, “Block Locking” on page 62 for details on write protection.
OUTPUT VCC: Enables all outputs to be driven to 1.8 V to 2.5 V while the VCC is at 2.7 V to 3.3 V.
If the VCC is regulated to 2.7 V to 2.85 V, VCCQ can be driven at 1.65 V to 2.5 V to achieve lowest
power operation (see Section 7.2, “DC Voltage Characteristics” on page 36).
VCCQ
Input
This input can be tied directly to VCC (2.7 V to 3.6 V).
VCC
Power
DEVICE Power Supply: 2.7 V to 3.6 V
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
31
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 10.
B3 Flash memory Device Signal Descriptions (Sheet 2 of 2)
Symbol
Type
Description
PROGRAM/ERASE Power Supply: Supplies power for Program and Erase operations. VPP can
be the same as VCC (2.7 V to 3.6 V) for single supply voltage operation. For fast programming at
manufacturing, 11.4 V to 12.6 V can be supplied to VPP. This pin cannot be left floating. 11.4 V to
12.6 V can be applied to VPP only for a maximum of 1000 cycles on the main blocks and 2500
cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hours maximum
(see Section 13.0, “VPP Program and Erase Voltages” on page 63 for details).
VPP
Power
VPP < VPPLK protects memory contents against inadvertent or unintended program and erase
commands.
GND
NC
—
—
Ground: For all internal circuitry. All ground inputs must be connected.
No Connect: Pin can be driven or left floating.
6.0
Maximum Ratings and Operating Conditions
6.1
Absolute Maximum Ratings
Warning:
Stressing the flash memory device beyond the Absolute Maximum Ratings in Table 11 can cause
permanent damage. These ratings are stress ratings only.
NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest
datasheet before finalizing a design.
Table 11.
Absolute Maximum Ratings
Parameter
Extended Operating Temperature
Maximum Rating
Notes
During Read
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–65 °C to +125 °C
–0.5 V to +3.7 V
–0.5 V to +13.5 V
–0.2 V to +3.6 V
100 mA
During Block Erase and Program
Temperature under Bias
Storage Temperature
Voltage On Any Pin (except VCC and VPP) with Respect to GND
1
V
PP Voltage (for Block Erase and Program) with Respect to GND
CC and VCCQ Supply Voltage with Respect to GND
1,2,3
V
Output Short Circuit Current
4
Notes:
1.
Minimum DC voltage is –0.5 V on input/output pins. During transitions, this level might
undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is
VCC +0.5 V which, during transitions, might overshoot to VCC +2.0 V for periods <20 ns.
Maximum DC voltage on VPP might overshoot to +14.0 V for periods <20 ns.
VPP Program voltage is typically 1.65 V to 3.6 V. Connection to a 11.4 V to 12.6 V supply
can be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the
parameter blocks during program/erase. VPP can be connected to 12 V for a total of 80
hours maximum.
2.
3.
4.
Output shorted for no more than one second. No more than one output shorted at a time.
18 Aug 2005
32
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
6.2
Operating Conditions
Do not operate the flash memory device beyond the Operating Conditions in Table 12. Extended
exposure beyond the Operating Conditions can affect device reliability.
Table 12.
Temperature and Voltage Operating Conditions
Symbol
Parameter
Min
Max
Units
Notes
TA
Operating Temperature
VCC Supply Voltage
–40
2.7
+85
3.6
3.6
3.6
2.5
2.5
3.6
12.6
°C
VCC1
Volts
1, 2
1, 2
1
VCC2
3.0
VCCQ1
VCCQ2
VCCQ3
VPP1
2.7
I/O Supply Voltage
Supply Voltage
1.65
1.8
Volts
1.65
11.4
100,000
Volts
Volts
1
1, 3
3
VPP2
Cycling
Block Erase Cycling
Cycles
Notes:
1.
2.
3.
VCC and VCCQ must share the same supply when they are in the VCC1 range.
VCCMax = 3.3 V for 0.25µm 32-Mbit devices.
VPP = 11.4 V–12.6 V can be applied during a program/erase only for a maximum of
1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP can be
connected to 12 V for a total of 80 hours maximum.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
33
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
7.0
Electrical Specifications
7.1
DC Current Characteristics
Table 13.
DC Current Characteristics (Sheet 1 of 2)
VCC
2.7 V–3.6 V 2.7 V–2.85 V
2.7 V–3.3 V
1.8 V–2.5 V
Sym
Parameter
VCCQ 2.7 V–3.6 V 1.65 V–2.5 V
Unit
Test Conditions
Note
Typ Max
Typ
Max
Typ
Max
VCC = VCCMax
VCCQ = VCCQMax
ILI
Input Load Current
1,2
1
1
1
µA
VIN = VCCQ or GND
V
CC = VCCMax
ILO
Output Leakage Current
1,2
10
10
10
µA VCCQ = VCCQMax
VIN = VCCQ or GND
VCC Standby Current for
0.13 and 0.18 Micron
Product
V
CC = VCCMax
1
1
7
10
7
15
25
15
25
18
20
20
7
50
50
20
25
15
150
150
7
250
250
20
µA
µA
µA
µA
mA
CE# = RP# = VCCQ
or during Program/ Erase
Suspend
ICCS
ICCD
ICCR
V
CC Standby Current for
WP# = VCCQ or GND
0.25 Micron Product
VCC Power-Down Current
for 0.13 and 0.18 Micron
Product
VCC = VCCMax
1,2
1,2
1,2,3
VCCQ = VCCQMax
VIN = VCCQ or GND
RP# = GND ± 0.2 V
VCC Power-Down Current
for 0.25 Product
7
7
7
25
VCC Read Current for
0.13 and 0.18 Micron
Product
VCC = VCCMax
9
8
9
15
VCCQ = VCCQMax
OE# = VIH, CE# =VIL
f = 5 MHz, IOUT=0 mA
Inputs = VIL or VIH
VCC Read Current for
0.25 Micron Product
1,2,3
1
10
0.2
18
8
18
5
8
15
5
9
15
5
mA
µA
VPP Deep Power-Down
Current
RP# = GND ± 0.2 V
VPP ≤ VCC
IPPD
0.2
18
10
21
16
0.2
18
10
21
16
VPP =VPP1,
55
22
45
15
55
30
45
45
55
30
45
45
mA
mA
mA
mA
Program in Progress
ICCW
VCC Program Current
VCC Erase Current
1,4
1,4
VPP = VPP2 (12v)
Program in Progress
VPP = VPP1,
16
8
Erase in Progress
ICCE
VPP = VPP2 (12v) ,
Erase in Progress
VCC Erase Suspend
Current for 0.13 and 0.18
Micron Product
7
15
25
50
50
200
200
50
50
200
200
µA
µA
ICCES
ICCWS
/
CE# = VIH, Erase
Suspend in Progress
1,4,5
1,4
VCC Erase Suspend
Current for 0.25 Micron
Product
10
2
15
2
15
2
15
µA VPP ≤ VCC
IPPR
VPP Read Current
50
200
50
200
50
200
µA VPP > VCC
18 Aug 2005
34
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 13.
DC Current Characteristics (Sheet 2 of 2)
VCC
2.7 V–3.6 V 2.7 V–2.85 V
2.7 V–3.3 V
1.8 V–2.5 V
Sym
Parameter
VCCQ 2.7 V–3.6 V 1.65 V–2.5 V
Unit
Test Conditions
Note
Typ Max
Typ
Max
Typ
Max
V
PP =VPP1,
0.05
8
0.1
22
0.05
0.1
0.05
0.1
mA
mA
mA
mA
Program in Progress
IPPW
VPP Program Current
VPP Erase Current
1,4
VPP = VPP2 (12v)
8
22
0.1
45
8
22
0.1
45
Program in Progress
VPP = VPP1,
0.05
8
0.1
22
0.05
16
0.05
16
Erase in Progress
IPPE
1,4
1,4
VPP = VPP2 (12v) ,
Erase in Progress
VPP = VPP1,
0.2
50
5
0.2
50
5
0.2
50
5
µA Program or Erase
Suspend in Progress
IPPES
IPPWS Current
/
VCC Erase Suspend
VPP = VPP2 (12v) ,
200
200
200
µA Program or Erase
Suspend in Progress
Notes:
1.
2.
All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 °C.
The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ voltage
listed at the top of each column. VCCMax = 3.3 V for 0.25µm 32-Mbit devices.
Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
Sampled, not 100% tested.
3.
4.
5.
ICCES or ICCWS is specified with the flash memory device deselected.
– If the device is read while in erase suspend, the current draw is the sum of ICCES and ICCR
– If the device is read while in program suspend, the current draw is the sum of ICCWS and ICCR
.
.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
35
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
7.2
DC Voltage Characteristics
Table 14.
DC Voltage Characteristics
VCC
2.7 V–3.6 V
2.7 V–3.6 V
2.7 V–2.85 V
1.65 V–2.5 V
2.7 V–3.3 V
1.8 V–2.5 V
Symbol Parameter VCCQ
Note
Unit Test Conditions
Min
Max
Min
Max
Min
Max
Input Low
Voltage
VCC *
0.22 V
VIL
–0.4
2.0
–0.4
0.4
–0.4
0.4
V
V
Input High
Voltage
VCCQ
+0.3V
VCCQ
0.4V
–
–
VCCQ
+0.3V
VCCQ
0.4V
–
–
VCCQ
+0.3V
VIH
VCC = VCCMin
Output Low
Voltage
VOL
–0.1
0.1
-0.1
0.1
-0.1
0.1
V
V
VCCQ = VCCQMin
IOL = 100 µA
VCC = VCCMin
Output High
Voltage
VCCQ
–0.1V
VCCQ
0.1V
VCCQ
0.1V
VOH
VCCQ = VCCQMin
IOH = –100 µA
VPP Lock-
Out Voltage
Complete Write
Protection
VPPLK
VPP1
VPP2
1
1
1.0
3.6
1.0
3.6
1.0
3.6
V
V
VPP During
Program /
Erase
1.65
11.4
1.65
11.4
1.65
11.4
1,2
12.6
12.6
12.6
V
Operations
VCC Prog/
Erase
Lock
VLKO
1.5
1.2
1.5
1.2
1.5
1.2
V
Voltage
VCCQ Prog/
Erase
Lock
VLKO2
V
Voltage
Notes:
1.
2.
Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPP1 and VPP2
VPP = 11.4 V–12.6 V can be applied during program/erase only for a maximum of 1000 cycles on the main blocks and
2500 cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hours maximum.
.
18 Aug 2005
36
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
8.0
AC Characteristics
8.1
AC Read Characteristics
Read Operations—8-Mbit Density
Density
Table 15.
8 Mbit
Product
90 ns
3.0 V – 3.6 V 2.7 V – 3.6 V
110 ns
3.0 V – 3.6 V 2.7 V – 3.6 V
#
Sym
Parameter
Unit
VCC
Note
Min
Max
Min
Max
Min
Max
Min
Max
R1
tAVAV
Read Cycle Time
3,4
80
90
100
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
R2
R3
R4
R5
R6
R7
R8
R9
tAVQV Address to Output Delay
tELQV CE# to Output Delay
tGLQV OE# to Output Delay
tPHQV RP# to Output Delay
tELQX CE# to Output in Low Z
tGLQX OE# to Output in Low Z
tEHQZ CE# to Output in High Z
tGHQZ OE# to Output in High Z
Output Hold from
3,4
80
80
90
90
100
100
30
110
110
30
1,3,4
1,3,4
3,4
30
30
150
150
150
150
2,3,4
2,3,4
2,3,4
2,3,4
0
0
0
0
0
0
0
0
20
20
20
20
20
20
20
20
Address, CE#, or OE#
Change, Whichever
R10
tOH
2,3,4
0
0
0
0
ns
Occurs First
Notes:
1.
2.
3.
4.
OE# can be delayed up to tELQV– GLQV
Sampled, but not 100% tested.
See Figure 10 “Read Operation Waveform” on page 40.
See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing measurements and maximum allowable
input slew rate.
t
after the falling edge of CE# without impact on tELQV.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
37
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 16.
Read Operations—16-Mbit Density
Density
16 Mbit
90 ns
Product
VCC
70 ns
80 ns
110 ns
Param
eter
#
Sym
Unit Notes
2.7 V–3.6
V
2.7 V–3.6
V
3.0 V–3.6
2.7 V–3.6
V
3.0 V–
3.6V
2.7 V–3.6V
V
Min Max Min Max Min Max Min Max Min Max Min Max
R1
tAVAV Read Cycle Time
Address to Output
70
80
80
90
100
110
ns
ns
3,4
3,4
R2 tAVQV
R3 tELQV
R4 tGLQV
R5 tPHQV
R6 tELQX
R7 tGLQX
R8 tEHQZ
R9 tGHQZ
70
70
80
80
80
80
90
90
100
100
30
110
110
30
Delay
CE# to Output
Delay
ns
ns
ns
ns
ns
ns
ns
1,3,4
1,3,4
3,4
OE# to Output
Delay
20
20
30
30
RP# to Output
Delay
150
150
150
150
150
150
CE# to Output in
Low Z
0
0
0
0
0
0
0
0
0
0
0
0
2,3,4
2,3,4
2,3,4
2,3,4
OE# to Output in
Low Z
CE# to Output in
High Z
20
20
20
20
20
20
20
20
20
20
20
20
OE# to Output in
High Z
Output Hold from
Address, CE#, or
OE# Change,
Whichever Occurs
First
R10
tOH
0
0
0
0
0
0
ns
2,3,4
Notes:
1.
2.
3.
4.
OE# can be delayed up to tELQV– GLQV
Sampled, but not 100% tested.
See Figure 10 “Read Operation Waveform” on page 40.
See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing measurements and maximum allowable
input slew rate.
t
after the falling edge of CE# without impact on tELQV.
18 Aug 2005
38
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 17.
Read Operations—32-Mbit Density
Density
Product
32 Mbit
100 ns
70 ns
90 ns
110 ns
Param
eter
#
Sym
Unit Notes
2.7 V–3.6
V
2.7 V–3.6
V
3.0 V–3.3
2.7 V–3.3
V
3.0 V–3.3
2.7 V–3.3
V
VCC
V
V
Min Max Min Max Min Max Min Max Min Max Min Max
R1
tAVAV Read Cycle Time
Address to Output
70
90
90
100
100
110
ns
ns
3,4
3,4
R2 tAVQV
R3 tELQV
R4 tGLQV
R5 tPHQV
R6 tELQX
R7 tGLQX
R8 tEHQZ
R9 tGHQZ
70
70
90
90
90
90
100
100
30
100
100
30
110
110
30
Delay
CE# to Output
Delay
ns
ns
ns
ns
ns
ns
ns
1,3,4
1,3,4
3,4
OE# to Output
Delay
20
20
30
RP# to Output
Delay
150
150
150
150
150
150
CE# to Output in
Low Z
0
0
0
0
0
0
0
0
0
0
0
0
2,3,4
2,3,4
2,3,4
2,3,4
OE# to Output in
Low Z
CE# to Output in
High Z
20
20
20
20
20
20
20
20
20
20
20
20
OE# to Output in
High Z
Output Hold from
Address, CE#, or
OE# Change,
Whichever
R10
tOH
0
0
0
0
0
0
ns
2,3,4
Occurs First
Notes:
1.
2.
3.
4.
OE# can be delayed up to tELQV– GLQV
Sampled, but not 100% tested.
See Figure 10 “Read Operation Waveform” on page 40.
See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing measurements and maximum
allowable input slew rate.
t
after the falling edge of CE# without impact on tELQV.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
39
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 18.
Read Operations — 64-Mbit Density
Density
Product
VCC
64 Mbit
70 ns
2.7 V–3.6 V
80 ns
#
Sym
Parameter
Unit
2.7 V–3.6 V
Note
Min
Max
Min
Max
R1
R2
R3
R4
R5
R6
R7
R8
R9
tAVAV Read Cycle Time
3,4
70
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV Address to Output Delay
tELQV CE# to Output Delay
tGLQV OE# to Output Delay
tPHQV RP# to Output Delay
tELQX CE# to Output in Low Z
tGLQX OE# to Output in Low Z
tEHQZ CE# to Output in High Z
tGHQZ OE# to Output in High Z
3,4
70
70
80
80
1,3,4
1,3,4
3,4
20
20
150
150
2,3,4
2,3,4
2,3,4
2,3,4
0
0
0
0
20
20
20
20
Output Hold from Address, CE#, or OE#
Change, Whichever Occurs First
R10
tOH
2,3,4
0
0
ns
Notes:
1.
2.
3.
4.
OE# can be delayed up to tELQV– GLQV
Sampled, but not 100% tested.
See Figure 10 “Read Operation Waveform” on page 40.
See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing measurements and
maximum allowable input slew rate.
t
after the falling edge of CE# without impact on tELQV.
Figure 10.
Read Operation Waveform
R1
R2
R3
Address [A]
CE# [E]
R8
R4
R9
OE# [G]
WE# [W]
R7
R6
R10
Data [D/Q]
RST# [P]
R5
18 Aug 2005
40
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
8.2
AC Write Characteristics
Table 19.
Write Operations—8-Mbit Density
Density
Product
3.0 V – 3.6 V
2.7 V – 3.6 V
Note
4,5
8 Mbit
90 ns
110 ns
100
#
Sym
Parameter
80
Unit
VCC
90
110
Min
Min
Min
Min
tPHWL
/
W1
W2
W3
W4
W5
W6
W7
W8
W9
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
150
150
0
150
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHEL
tELWL
tWLEL
/
4,5
4,5
0
50
50
50
0
0
70
60
70
0
tWLWH
tELEH
/
60
50
60
0
70
60
70
0
tDVWH
tDVEH
/
/
/
/
/
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold Time from WE# (CE#) High
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
2,4,5
2,4,5
4,5
tAVWH
tAVEH
tWHEH
tEHWH
tWHDX
tEHDX
2,4,5
2,4,5
2,4,5
0
0
0
0
tWHAX
tEHAX
0
0
0
0
tWHWL /
tEHEL
30
30
30
30
tVPWH
tVPEH
/
W10
W11
W12
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3,4,5
3,4
200
0
200
0
200
0
200
0
ns
ns
ns
tQVVL
tBHWH
tBHEH
/
WP# Setup to WE# (CE#) Going High
3,4
0
0
0
0
W13
tQVBL
WP# Hold from Valid SRD
3,4
3,4
0
0
0
0
ns
ns
W14
tWHGL
WE# High to OE# Going Low
30
30
30
30
Notes:
1.
Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH
.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE#
going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL
.
2.
3.
4.
Refer to Table 27 “Bus Operations(1)” on page 51 for valid AIN or DIN
Sampled, but not 100% tested.
.
See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing measurements and maximum allowable
input slew rate.
5.
See Figure 11 “Write Operations Waveform” on page 45.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
41
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 20.
Write Operations—16-Mbit Density
Density
Product
16 Mbit
90 ns
80
70 ns
80 ns
110 ns
100
#
Sym
Parameter
3.0 V – 3.6 V
2.7 V – 3.6 V
Unit
VCC
70
80
90
110
Min
Note
Min
Min
Min Min
Min
tPHWL
tPHEL
/
RP# High Recovery to WE# (CE#) Going
Low
W1
W2
W3
W4
W5
W6
W7
W8
W9
4,5
150
0
150
0
150 150
150
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tELWL
tWLEL
/
CE# (WE#) Setup to WE# (CE#) Going Low 4,5
0
50
50
50
0
0
60
50
60
0
0
70
60
70
0
tWLWH
tELEH
/
WE# (CE#) Pulse Width
1,4,5
2,4,5
2,4,5
4,5
45
40
50
0
50
40
50
0
70
60
70
0
tDVWH
tDVEH
/
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
tAVWH
tAVEH
/
tWHEH
tEHWH
/
/
/
CE# (WE#) Hold Time from WE# (CE#)
High
tWHDX
tEHDX
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
2,4,5
2,4,5
1,4,5
0
0
0
0
0
0
tWHAX
tEHAX
0
0
0
0
0
0
tWHWL /
tEHEL
25
30
30
30
30
30
tVPWH
tVPEH
/
W10
W11
W12
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3,4,5
3,4
200
0
200
0
200 200
200
0
200
0
ns
ns
ns
tQVVL
0
0
0
0
tBHWH
tBHEH
/
WP# Setup to WE# (CE#) Going High
3,4
0
0
0
0
W13
W14
tQVBL
WP# Hold from Valid SRD
3,4
3,4
0
0
0
0
0
0
ns
ns
tWHGL
WE# High to OE# Going Low
30
30
30
30
30
30
Notes:
1.
Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH
.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or
WE# going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL
.
2.
3.
4.
Refer to Table 27 “Bus Operations(1)” on page 51 for valid AIN or DIN
Sampled, but not 100% tested.
.
See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing measurements and maximum allowable
input slew rate.
See Figure 11 “Write Operations Waveform” on page 45.
5.
18 Aug 2005
42
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 21.
Write Operations—32-Mbit Density
Density
32 Mbit
100 ns
Product
70 ns
90 ns
110 ns
100
#
Sym
Parameter
3.0 V – 3.6 V6
2.7 V – 3.6 V
Note
90
Unit
VCC
70
90
100
Min
110
Min
Min
Min
Min
Min
tPHWL
tPHEL
/
RP# High Recovery to WE# (CE#)
Going Low
W1
W2
4,5
4,5
150
0
150
0
150
150
0
150
150
0
ns
ns
tELWL
tWLEL
/
CE# (WE#) Setup to WE# (CE#)
Going Low
0
0
tWLWH
/
W3
WE# (CE#) Pulse Width
1,4,5
45
60
60
70
70
70
ns
tELEH
tDVWH
tDVEH
/
/
/
/
/
W4
W5
W6
W7
W8
W9
W10
Data Setup to WE# (CE#) Going High
2,4,5
2,4,5
4,5
40
50
0
40
60
0
50
60
0
60
70
0
60
70
0
60
70
0
ns
ns
ns
ns
ns
ns
tAVWH
tAVEH
Address Setup to WE# (CE#) Going
High
tWHEH
tEHWH
CE# (WE#) Hold Time from WE#
(CE#) High
tWHDX
tEHDX
Data Hold Time from WE# (CE#)
High
2,4,5
2,4,5
1,4,5
0
0
0
0
0
0
tWHAX
tEHAX
Address Hold Time from WE# (CE#)
High
0
0
0
0
0
0
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
25
30
30
30
30
30
tVPWH
tVPEH
/
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3,4,5
3,4
200
0
200
0
200
0
200
0
200
0
200
0
ns
ns
ns
W11 tQVVL
tBHWH
W12
/
WP# Setup to WE# (CE#) Going
High
3,4
0
0
0
0
0
0
tBHEH
W13 tQVBL
W14 tWHGL
Notes:
WP# Hold from Valid SRD
3,4
3,4
0
0
0
0
0
0
ns
ns
WE# High to OE# Going Low
30
30
30
30
30
30
1.
Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH
.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE#
going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL
.
2.
3.
4.
Refer to Table 27 “Bus Operations(1)” on page 51 for valid AIN or DIN
Sampled, but not 100% tested.
.
See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing measurements and maximum allowable
input slew rate.
5.
6.
See Figure 11 “Write Operations Waveform” on page 45.
VCCMax = 3.3 V for 32-Mbit 0.25 Micron product.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
43
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 22.
Write Operations—64-Mbit Density
Density
Product
64 Mbit
80 ns
Min
#
Symbol
Parameter
Unit
VCC
2.7 V – 3.6 V
Note
W1
W2
tPHWL / tPHEL
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
4,5
4,5
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
ELWL / tWLEL
WLWH / tELEH
DVWH / tDVEH
AVWH / tAVEH
WHEH / tEHWH
WHDX / tEHDX
WHAX / tEHAX
W3
t
1,4,5
2,4,5
2,4,5
4,5
60
40
60
0
W4
t
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold Time from WE# (CE#) High
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
W5
t
W6
t
W7
t
2,4,5
2,4,5
1,4,5
3,4,5
3,4
0
W8
t
0
W9
t
WHWL / tEHEL
VPWH / tVPEH
tQVVL
30
200
0
W10
W11
W12
W13
W14
Notes:
t
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
tBHWH / tBHEH
WP# Setup to WE# (CE#) Going High
WP# Hold from Valid SRD
3,4
0
tQVBL
3,4
0
tWHGL
WE# High to OE# Going Low
3,4
30
1.
Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH
.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or
WE# going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL
.
2.
3.
4.
Refer to Table 27 “Bus Operations(1)” on page 51 for valid AIN or DIN.
Sampled, but not 100% tested.
See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing measurements and maximum allowable
input slew rate.
5.
See Figure 11 “Write Operations Waveform” on page 45.
18 Aug 2005
44
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 11.
Write Operations Waveform
W5
W8
Address [A]
CE# [E]
W6
W3
W2
W9
WE# [W]
OE# [G]
W4
W7
Data [D/Q]
W1
RP# [P]
W10
Vpp [V]
8.3
Erase and Program Timing
Table 23.
Erase and Program Timing
VPP
1.65 V–3.6 V
11.4 V–12.6 V
Symbol
Parameter
Unit
Note
Typ
Max
Typ
Max
4-KW Parameter Block
Word Program Time
tBWPB
1, 2, 3
0.10
0.30
0.03
0.12
s
s
32-KW Main Block
Word Program Time
tBWMB
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
0.8
12
22
0.5
1
2.4
200
200
4
0.24
8
1
185
185
4
Word Program Time for 0.13
and 0.18 Micron Product
µs
µs
s
tWHQV1 / tEHQV1
Word Program Time for 0.25
Micron Product
8
4-KW Parameter Block
Erase Time
tWHQV2 / tEHQV2
0.4
0.6
32-KW Main Block
Erase Time
tWHQV3 / tEHQV3
5
5
s
t
WHRH1 / tEHRH1
WHRH2 / tEHRH2
Program Suspend Latency
Erase Suspend Latency
1,3
1,3
5
5
10
20
5
5
10
20
µs
µs
t
Notes:
1.
2.
3.
Typical values measured at TA= +25 °C and nominal voltages.
Excludes external system-level overhead.
Sampled, but not 100% tested.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
45
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
8.4
AC I/O Test Conditions
Figure 12.
AC Input/Output Reference Waveform
VCCQ
Test Points
Input
VCCQ/2
VCCQ/2
Output
0V
Note: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns.
Worst-case speed conditions are when VCC = VCCMin.
Figure 13.
Transient Equivalent Testing Load Circuit
VCCQ
R1
Device
Under Test
Out
CL
R2
Note: See Table 24 for component values.
Table 24.
Test Configuration Component Values for Worst Case Speed Conditions
Test Configuration
VCCQMin Standard Test
CL (pF)
R1 (kΩ)
R2 (kΩ)
50
25
25
Note: CL includes jig capacitance.
8.5
Device Capacitance
T = 25 °C, f = 1 MHz
A
Table 25.
Device Capacitance
Symbol
Parameter§
Typ
Max
Unit
Condition
CIN
COUT
Input Capacitance
Output Capacitance
6
8
8
pF
pF
VIN = 0.0 V
12
VOUT = 0.0 V
§Sampled, not 100% tested.
18 Aug 2005
46
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
9.0
Power and Reset Specifications
9.1
Power-Up/Down Characteristics
To prevent any condition that might result in a spurious write or erase operation, power-up V
CC
and V
together. Conversely, V and V
must power-down together.
CCQ
CC
CCQ
Also power-up V with or slightly after V . Conversely, V must power-down with or slightly
PP
CC
PP
before V
.
CC
If V
and/or VPP are not connected to the V supply, then V must attain V Min before
CC CC CC
CCQ
applying VCCQ and VPP. Device inputs must not be driven before supply voltage = VCCMin.
Power supply transitions must occur only when RP# is low.
9.1.1
RP# Connected to System Reset
Use RP# during system reset with automated program/erase devices, because the system expects to
read from the flash memory when the system exits reset. If a CPU reset occurs without a flash
memory reset, proper CPU initialization does not occur, because the flash memory might be
providing status information instead of array data. Connecting RP# to the system CPU RESET#
signal to allow proper CPU/flash initialization after a system reset.
System designers must guard against spurious writes when V voltages are above V
. Because
LKO
CC
both WE# and CE# must be low for a command write, driving either signal to V inhibits writes to
IH
the flash memory device. The CUI architecture provides additional protection, because memory
contents can be altered only after successful completion of the two-step command sequences. The
flash memory device is also disabled until RP# is brought to V , regardless of the state of its
IH
control inputs. By holding the device in reset (RP# connected to system POWERGOOD) during
power-up/down, invalid bus conditions during power-up can be masked, providing yet another
level of memory protection.
9.1.2
V
, V and RP# Transitions
CC PP,
The CUI latches commands as issued by system software, and is not altered by V or CE#
PP
transitions or WSM actions. The CUI default state upon power-up, after exit from reset mode or
after V transitions above V
(Lockout voltage), is read-array mode.
CC
LKO
After any program or Block-Erase operation is complete (even after V transitions down to
PP
V
), the CUI must be reset to read-array mode, using the Read Array command if access to the
PPLK
flash-memory array is required.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
47
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
9.2
Reset Specifications
Table 26.
Reset Specifications
VCC 2.7 V – 3.6 V
Symbol
Parameter
Unit
Notes
Min
Max
RP# Low to Reset during Read
(If RP# is tied to VCC, this specification is not
applicable)
tPLPH
100
ns
1, 2
tPLRH1
tPLRH2
RP# Low to Reset during Block Erase
RP# Low to Reset during Program
22
12
µs
µs
3
3
Notes:
1.
2.
If tPLPH is < 100 ns, the device can still reset, but reset is not guaranteed.
If RP# is asserted while a Block Erase or Word Program operation is not executing, the
reset completes within 100 ns.
3.
Sampled, but not 100% tested.
Figure 14.
Deep Power-Down/Reset Operations Waveforms
V
IH
RP# (P)
tPHQV
tPHWL
tPHEL
VIL
t PLPH
(A) Reset during Read Mode
Abort
Complete
t PLRH
tPHQV
tPHWL
tPHEL
VIH
VIL
RP# (P)
t PLPH
tPLPH
t PLRH
<
(B) Reset during Program or Block Erase,
Abort Deep
Complete Power-
tPHQV
tPHWL
tPHEL
Down
tPLRH
VIH
VIL
RP# (P)
t PLPH
(C) Reset Program or Block Erase, t PLPH > tPLRH
18 Aug 2005
48
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
9.3
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System
designers must consider the following three supply current issues:
1. Standby current levels (I
).
CCS
2. Read current levels (I
).
CCR
3. Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device output capacitive and inductive loading.
Two-line control and proper decoupling capacitor selection suppresses these transient voltage
peaks. Each flash device must have a 0.1 µF ceramic capacitor connected between each V and
CC
GND, and between its V and GND. These high-frequency, inherently low-inductance capacitors
PP
must be placed as close as possible to the package leads.
9.4
Power Consumption
Intel® flash memory devices use a tiered approach to power savings that can significantly reduce
overall system power consumption. The Automatic Power Savings (APS) feature reduces power
consumption when the flash memory device is selected but idle. If CE# is deasserted, the flash
memory device enters its standby mode, where current consumption is even lower. The
combination of these features can minimize memory power consumption, and therefore minimize
overall system power consumption.
9.4.1
9.4.2
9.4.3
Active Power
When CE# is at a logic-low level and RP# is at a logic-high level, the flash memory device is in the
active mode. Refer to the DC Characteristic tables for I current values. Active power is the
largest contributor to overall system power consumption. Minimizing the active current can
profoundly affect system power consumption, especially for battery-operated devices.
CC
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from
the flash memory array and the address lines are quiescent, APS circuitry places the flash memory
device in a mode where typical current is comparable to I
state with outputs valid until a new location is read.
. The flash memory stays in this static
CCS
Standby Power
When CE# is at a logic-high level (V ) and the flash memory device is in read mode, the flash
IH
memory is in standby mode. This mode disables much of the device circuitry, and substantially
reduces power consumption. Outputs are placed in a high-impedance state independent of the
status of the OE# signal. If CE# transitions to a logic-high level during Erase or Program
operations, the flash memory device continues to perform the operation and consume
corresponding active power until the operation is completed.
System engineers must analyze the breakdown of standby time versus active time and quantify the
respective power consumption in each mode for their specific application. This approach provides
a more accurate measure of application-specific power and energy requirements.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
49
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
9.4.4
Deep Power-Down Mode
The deep power-down mode is activated when RP# = V (GND 0.2 V). During read modes,
IL
RP# going low deselects the flash memory and places the outputs in a high-impedance state.
Recovery from deep power-down mode requires a minimum time of t
Characteristics” on page 37).
(see “AC Read
PHQV
During program or erase modes, RP# transitioning low aborts the in-progress operation. The
memory contents of the address being programmed or the block being erased are no longer valid,
because the abort compromises data integrity. During deep power-down, all internal circuits switch
to a low-power savings mode (RP# transitioning to V or turning off power to the flash memory
IL
device clears the Status Register).
10.0
Operations Overview
Flash memory combines EEPROM functionality with in-circuit electrical program-and-erase
capability. The B3 flash memory device family uses a Command User Interface (CUI) and
automated algorithms to simplify Program and Erase operations. The CUI allows for 100%
CMOS-level control inputs and fixed power supplies during erasure and programming.
When V < V
, the flash memory device executes only the following commands successfully:
PP
PPLK
• Read Array
• Read Status Register
• Clear Status Register
• Read Identifier
The flash memory device provides standard EEPROM read, standby, and Output-Disable
operations.
Manufacturer identification and device identification data can be accessed through the CUI.
All functions that alter memory contents (program and erase) are accessible through the CUI. The
internal Write State Machine (WSM) completely automates Program and Erase operations, while
the CUI signals the start of an operation and the Status Register reports status.
The CUI handles the WE# interface to the data and address latches, and system status requests
during WSM operation.
18 Aug 2005
50
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
10.1
Bus Operations
The B3 flash memory device performs read, program, and erase in-system operations through the
local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash memory
device:
• CE#
• OE#
• WE#
• RP#
Table 27 summarizes these bus operations.
Table 27.
Bus Operations(1)
Mode
Note
RP#
CE#
OE#
WE#
DQ0–7
DQ8–15
Read (Array, Status, or Identifier)
2–4
2
VIH
VIH
VIH
VIL
VIH
VIL
VIL
VIH
X
VIL
VIH
X
VIH
VIH
X
DOUT
High Z
High Z
High Z
DIN
DOUT
High Z
High Z
High Z
DIN
Output Disable
Standby
Reset
2
2, 7
2, 5–7
X
X
Write
VIL
VIH
VIL
Notes:
1.
8-bit devices use only DQ[0:7].
16-bit devices use DQ[0:15].
2.
3.
4.
5.
6.
7.
X must be VIL, VIH for control pins and addresses.
See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, VPP4 voltages.
Manufacturer and device codes can also be accessed in read identifier mode (A1–A21 = 0). See Table 29.
Refer to Table 30 for valid DIN during a Write operation.
To program or erase the lockable blocks, hold WP# at VIH
.
RP# must be at GND 0.2 V to meet the maximum deep power-down current specified.
10.1.1
Read
The B3 flash memory device provides four read modes:
• read array
• read identifier
• read status
• read query
These modes are accessible independently of the V voltage. Issue the appropriate Read Mode
PP
command to the CUI to enter the corresponding mode. Upon initial device power-up or after exit
from reset, the flash memory device automatically defaults to read-array mode.
CE# and OE# must be driven active to obtain data at the outputs.
• CE# is the device selection control. When active, CE# enables the flash memory device.
• OE# is the data output control, and drives the selected memory data onto the I/O bus.
For all read modes, WE# and RP# must be at V . Figure 10 on page 40 illustrates a read cycle.
IH
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10.1.2
10.1.3
Output Disable
When OE# is at a logic-high level (V ), the flash memory device outputs are disabled. Output pins
are placed in a high-impedance state.
IH
Standby
Deselecting the flash memory device by bringing CE# to a logic-high level (V ) places the device
IH
in standby mode. Standby mode substantially reduces device power consumption, without any
latency for subsequent read accesses. In standby mode, outputs are placed in a high-impedance
state independent of OE#. If deselected during Program or Erase operation, the flash memory
device continues to consume active power until the Program or Erase operation is complete.
10.1.4
Deep Power-Down / Reset
From read mode, RP# at V for time t
does the following:
IL
PLPH
• Deselects the flash memory.
• Places output drivers in a high-impedance state.
• Turns off all internal circuits.
• After a return from reset, a time t
is required until the initial read-access outputs are valid.
PHQV
• After a return from reset, a delay (t
or t
) is required before a write can be initiated.
PHEL
PHWL
After this wake-up interval, normal operation is restored. The CUI resets to read-array mode, and
the Status Register is set to 80H. Figure 14 “Deep Power-Down/Reset Operations Waveforms” on
page 48 (A) illustrates this case.
If RP# is taken low for time t
during a Program or Erase operation, the operation aborts. The
PLPH
memory contents at the aborted location (for a program) or block (for an erase) are no longer valid,
because the data might be partially erased or written.
The abort process uses the following sequence:
1. When RP# goes low, the flash memory device shuts down the operation in progress, a process
that takes time t
to complete.
PLRH
2. After this time t
, the flash memory device either resets to read-array mode (if RP# has
PLRH
gone high during t
, see Figure 14 “Deep Power-Down/Reset Operations Waveforms” on
PLRH
page 48 (B)), or enters reset mode (if RP# is still logic low after t
Power-Down/Reset Operations Waveforms” on page 48 (C)).
, see Figure 14 “Deep
PLRH
3. In both cases, after returning from an aborted operation, the relevant time t
or t
/
PHWL
PHQV
t
must elapse before initiating a Read or Write operation, as discussed in the previous
PHEL
paragraph. However, in this case, these delays are referenced to the end of t
when RP# goes high.
rather than
PLRH
As with any automated device, RP# must be asserted during system reset. When the system
finishes reset, the processor expects to read from the flash memory. Automated flash memories
provide status information when read during program or Block-Erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization cannot occur, because the flash
memory might be providing status information instead of array data.
Intel® Flash memories allow proper CPU initialization after a system reset, using the RP# input. In
this application, RP# is controlled by the same RESET# signal that resets the system CPU.
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10.1.5
Write
A write occurs when both CE# and WE# are low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard microprocessor write timings to control flash
memory operations. The CUI does not occupy an addressable memory location. The address and
data buses are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first.
Table 30 shows the available commands, and Appendix A provides detailed information about
moving between the different modes of operation using CUI commands.
Two commands modify array data:
• Program (40H).
• Erase (20H).
Writing either of these commands to the internal Command User Interface (CUI) initiates a
sequence of internally timed functions that culminate in the completion of the requested task
(unless that operation is aborted by either RP# being driven to V for t
or an appropriate
IL
PLRH
Suspend command).
11.0
Operating Modes
The flash memory device has four read modes:
• read array
• read identifier
• read status
• read query
See Figure 1 “B3 Architecture Block Diagram” on page 10).
The flash memory device also has two write modes:
• program
• block erase
Three additional modes are available only during suspended operations:
• erase suspend to program
• erase suspend to read
• program suspend to read
Table 28 “Command Codes and Descriptions” on page 54 summarizes the commands used to reach
these modes.
Appendix A, “Write State Machine Current/Next States,” is a comprehensive chart showing the
state transitions.
Datasheet
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11.1
Read Array
When RP# transitions from V (reset) to V , the flash memory device defaults to read-array
IL
IH
mode and responds to the read-control inputs (CE#, address inputs, and OE#) without any
additional CUI commands.
When the flash memory device is in read-array mode, four control signals control data output:
• WE# must be logic high (V
)
IH
• CE# must be logic low (V )
IL
• OE# must be logic low (V )
IL
• RP# must be logic high (V
)
IH
In addition, the address of the preferred location must be applied to the address pins. If the flash
memory device is not in read-array mode, such as after a Program or Erase operation, the Read
Array command (FFH) must be written to the CUI before array reads can occur.
Table 28.
Command Codes and Descriptions (Sheet 1 of 2)
Code
Device Mode
Description
00, 01,
60, 2F,
C0, 98
Invalid/
Reserved
Unassigned commands that must not be used. Intel reserves the right to redefine these codes
for future functions.
Places the flash memory device in read-array mode, so that array data is output on the data
pins.
FF
Read Array
A two-cycle command.
•
•
The first cycle prepares the CUI for a program operation.
The second cycle latches addresses and data information, and initiates the WSM to
execute the program algorithm.
40
Program Set-Up
The flash memory device outputs Status Register data when CE# or OE# is toggled. To read
array data, a Read Array command is required after programming. See Section 11.4.
Alternate
Program Set-Up
10
20
(See 40H/Program Set-Up)
Prepares the CUI for the Erase Confirm command. If the next command is not an Erase
Confirm command, then the CUI does the following:
1.
2.
3.
Sets both SR.4 and SR.5 of the Status Register to 1.
Places the flash memory device into the read-Status Register mode.
Waits for another command.
Erase Set-Up
Erase Confirm
See Section 11.5, “Erase Mode” on page 58.
If the previous command was an Erase Set-Up command, then the CUI closes the address and
data latches, and begins erasing the block indicated on the address pins.
During erase, the flash memory device responds only to the Read Status Register and Erase
Suspend commands. The device outputs Status Register data when CE# or OE# is toggled.
D0
Program / Erase
Resume
If a Program or Erase operation was previously suspended, this command resumes that
operation.
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Datasheet
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Table 28.
Command Codes and Descriptions (Sheet 2 of 2)
Code
Device Mode
Description
Issuing this command suspends the currently executing Program/Erase operation.
To indicate when the operation has been successfully suspended, the Status Register sets
either the program suspend (SR.2) or erase suspend (SR.6), and sets the WSM status bit
(SR.7) to 1 (ready).
Program / Erase
Suspend
B0
70
The WSM continues to idle in the SUSPEND state, regardless of the state of all input-control
pins except RP#, which immediately shuts down the WSM and the remainder of the device, if it
is driven to VIL.
See Section 11.4.1, “Suspending and Resuming Programming” on page 58 and Section 11.4.1,
“Suspending and Resuming Programming” on page 58.
This command places the flash memory device into Read-Status Register mode. Reading the
device outputs the contents of the Status Register, regardless of the address presented to the
device.
Read Status
Register
The flash memory device automatically enters this mode after a Program or Erase operation is
initiated. See Section 11.3, “Read Status Register” on page 56.
The WSM can set the block-lock status (SR.1), VPP status (SR.3), program status (SR.4), and
erase status (SR.5) bits in the Status Register to 1. However, the WSM cannot clear these bits
to 0. Issuing this command clears these bits to 0.
Clear Status
Register
50
90
Places the flash memory device into the intelligent-identifier-read mode, so that reading the
device outputs the manufacturer and device codes (A0 = 0 for manufacturer, A0 = 1 for the
device; all other address inputs must be 0). See Section 11.2, “Read Identifier” on page 56.
Read Identifier
Note: See Chapter 14.0, “Write State Machine Current/Next States,” for mode transition information.
Datasheet
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11.2
Read Identifier
To read the manufacturer and device codes, the flash memory device must be in read-identifier
mode, which can be reached by writing the Read Identifier command (90H).
As shown in Table 29, once in read-identifier mode:
• A = 0 outputs the manufacturer identification code.
0
• A = 1 outputs the device identifier.
0
Note:
A –A = 0.
1 21
To return to read-array mode, write the Read-Array command (FFH).
Table 29.
Read Identifier Table
Device Identifier
Size
Mfr. ID
-T (Top Boot)
-B (Bottom Boot)
28F004B3
28F400B3
28F008B3
28F800B3
28F016B3
28F160B3
28F320B3
28F640B3
D4H
8894H
D2H
D5H
8895H
D3H
0089H
0089H
0089H
8892H
D0H
8893H
D1H
8890H
8896H
8898H
8891H
8897H
8899H
11.3
Read Status Register
The flash memory device Status Register indicates when a Program or Erase operation is complete,
and the success or failure of that operation.
• To read the Status Register, issue the Read Status Register (70H) command to the CUI.
This command causes all subsequent Read operations to output data from the Status Register
until another command is written to the CUI.
• To return to reading from the array, issue the Read Array (FFH) command.
The Status Register bits are output on DQ –DQ . The upper byte, DQ –DQ , outputs 00H during
0
7
8
15
a Read Status Register command.
The contents of the Status Register are latched on the falling edge of OE# or CE#, which prevents
possible Bus errors that might occur if Status Register contents change while being read. CE# or
OE# must be toggled with each subsequent status read, or the Status Register does not indicate
completion of a Program or Erase operation.
When the WSM is active, SR.7 indicates the status of the WSM. The remaining bits in the Status
Register indicate whether the WSM was successful in performing the preferred operation (see
Table 31 on page 60).
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11.3.1
Clearing the Status Register
The WSM sets status bits 1 through 7 to 1, and clears bits 2, 6, and 7 to 0. However, the WSM
cannot clear status bits 1 or 3 through 5 to 0.
Because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through
the Clear Status Register (50H) command. By allowing the system software to control the resetting
of these bits, several operations can be performed (such as cumulatively programming several
addresses or erasing multiple blocks in sequence) before reading the Status Register to determine if
an error occurred during that series.
Clear the Status Register before beginning another command or sequence.
Note:
The Read Array command must be issued before data can be read from the flash memory array.
11.4
Program Mode
Programming is executed using a two-write sequence.
1. The Program Setup command (40H) is written to the CUI.
2. A second write specifies the address and data to program.
The WSM executes a sequence of internally timed events to program preferred bits of the
addressed location.
The WSM then verifies that the bits are sufficiently programmed.
Programming the memory changes specific bits within an address location to 0. If users attempt to
program 1 instead of 0, the memory cell contents do not change and no error occurs.
The Status Register indicates the programming status: while the program sequence executes, status
bit 7 is 0.
To poll the Status Register, toggle either CE# or OE#.
While programming, the only valid commands are:
• Read Status Register
• Program Suspend
• Program Resume
When programming is complete, the program-status bits must be checked.
• If the programming operation was unsuccessful, SR.4 is set, indicating a program failure.
• If SR.3 is set, then V was not within acceptable limits, and the WSM did not execute the
PP
program command.
• If SR.1 is set, a program operation was attempted on a locked block and the operation aborted.
Clear the Status Register before attempting the next operation. Any CUI instruction can follow
after programming is completed; however, to prevent inadvertent Status Register reads, be sure to
reset the CUI to read-array mode.
Datasheet
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11.4.1
Suspending and Resuming Programming
The Program Suspend command halts the in-progress program operation to read data from another
flash memory location.
1. After the programming process starts, writing the Program Suspend command to the CUI
requests that the WSM suspend the program sequence (at predetermined points in the program
algorithm).
2. The flash memory device continues to output Status Register data after the Program Suspend
command is written.
3. Polling SR.7 and SR.2 determines when the program operation has been suspended (both are
set to 1).
t
/t
specifies the program- suspend latency.
WHRH1 EHRH1
4. A Read Array command can now be written to the CUI to read data from blocks other than the
suspended block.
The only other valid commands while program is suspended are:
— Read Status Register
— Read Identifier
— Program Resume
5. After the Program Resume command is written to the flash memory, the WSM continues with
the program process, and Status Register bits SR.2 and SR.7 are automatically cleared.
6. After the Program Resume command is written, the flash memory device automatically
outputs Status Register data when read.
See Appendix B, “Program and Erase Flowcharts.”
Note:
V
must remain at the same V level used for program while in program-suspend mode. RP#
PP PP
must also remain at V
IH.
11.5
Erase Mode
To erase a block:
1. Write the Erase Set-up and Erase Confirm commands to the CUI, along with an address
identifying the block to be erased.
This address is latched internally when the Erase Confirm command is issued.
Block erasure sets all bits within the block to 1. Only one block can be erased at a time.
2. The WSM executes a sequence of internally timed events :
a. programs all bits within the block to 0.
b. Erases all bits within the block to 1.
c. Verifies that all bits within the block are sufficiently erased.
While the erase executes, status bit 7 is 0.
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3. When the Status Register indicates that erasure is complete, check the erase-status bit to verify
that the Erase operation was successful.
— If the Erase operation was unsuccessful, SR.5 of the Status Register is set to 1, indicating
an erase failure.
— If V was not within acceptable limits after the Erase Confirm command was issued, the
PP
WSM does not execute the erase sequence. Instead, SR.5 is set to indicate an Erase error,
and SR.3 is set to 1, indicating that the V supply voltage was not within acceptable
PP
limits.
4. After an Erase operation, clear the Status Register (50H) before attempting the next operation.
Any CUI instruction can follow after erasure is completed.
5. To prevent inadvertent status- register reads, place the flash memory device in read-array
mode after the erase is complete.
11.5.1
Suspending and Resuming Erase
Because an Erase operation requires on the order of seconds to complete, an Erase Suspend
command is provided. Erase Suspend interrupts an erase sequence to read data from—or program
data to— another block in memory.
After the erase sequence is started, writing the Erase Suspend command to the CUI requests that
the WSM pauses the erase sequence at a predetermined point in the erase algorithm.
Note:
The Status Register will indicates if/when the Erase operation has been suspended.
• A Read Array/Program command can now be written to the CUI, to read data from/ program
data to blocks other than the one currently suspended.
• The Program command can subsequently be suspended to read yet another array location.
The only valid commands while Erase is suspended are:
• Erase Resume
• Program
• Read Array
• Read Status Register
• Read Identifier
During erase-suspend mode, to place the flash memory device in a pseudo-standby mode, set CE#
to V , which reduces active current consumption.
IH
Erase Resume continues the erase sequence when CE# = V . As with the end of a standard Erase
IL
operation, the Status Register must be read and cleared before the next instruction is issued.
Datasheet
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
(1,4)
Table 30.
Command Bus Definitions
First Bus Cycle
Addr
Second Bus Cycle
Command
Read Array
Notes
Oper
Data
Oper
Addr
Data
Write
Write
Write
Write
X
X
X
X
FFH
90H
70H
50H
Read Identifier
2
3
Read
Read
IA
X
ID
Read Status Register
Clear Status Register
SRD
40H /
10H
Program
Write
X
Write
Write
PA
BA
PD
Block Erase/Confirm
Write
Write
Write
X
X
X
20H
B0H
D0H
D0H
Program/Erase Suspend
Program/Erase Resume
Notes:
PA: Program Address
IA: Identifier Address
PD: Program Data
ID: Identifier Data
BA: Block Address
SRD: Status Register Data
1.
2.
Bus operations are defined in Table 27.
Following the Intelligent Identifier command, two Read operations access manufacturer and device
codes.
– A 0 = 0 for manufacturer code.
– A0 = 1 for device code.
– A1–A21 = 0.
3.
4.
Either the 40H or 10H command is valid. The standard is 40H.
When writing commands to the flash memory device, the upper data bus [DQ 8–DQ15] must be either
VIL or VIH, to minimize current draw.
Table 31.
Status Register Bit Definition
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
R
0
Bits
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
Check Write State Machine bit first to determine word program
or block-erase completion, before checking program or erase-
status bits.
1 = Ready
0 = Busy
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
When erase suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to 1. ESS bit remains set at 1 until an
Erase Resume command is issued.
0 = Erase In Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to 1, WSM has applied the maximum
number of erase pulses to the block and is still unable to verify
successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Word Program
When this bit is set to 1, WSM has attempted but failed to
program a word.
0 = Successful Word Program
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Bits
NOTES:
The VPP status bit does not continuously indicate the VPP level.
The WSM interrogates the VPP level only after the Program or
Erase command sequences are entered, and informs the
system if VPP has not been switched on. The VPP is also
checked before the WSM verifies the operation. The VPP status
bit is not guaranteed to report accurate feedback between
VPPLK max and VPP1 min or between VPP1 max and VPP4 min.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
When program suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to 1. The PSS bit remains set to
1 until a Program Resume command is issued.
0 = Program in Progress/Completed
SR.1 = BLOCK LOCK STATUS
1 = Program/Erase attempted on locked block;
Operation aborted
If a Program or Erase operation is attempted to one of the
locked blocks, the WSM sets this bit. The operation specified is
aborted and the flash memory device returns to read status
mode.
0 = No operation to locked blocks
This bit is reserved for future use and must be masked out
when polling the Status Register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Note: A Command Sequence Error is indicated when SR.4, SR.5, and SR.7 are set.
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12.0
Block Locking
The B3 flash memory device architecture features two hardware-lockable parameter blocks.
12.1
WP# = VIL for Block Locking
The lockable blocks are locked when WP# = V ; any program or Erase operation to a locked
IL
block results in an error, which is reflected in the Status Register:
• For top configuration, the top two parameter blocks are lockable:
— blocks #133 and #134 for 64 Mbit
— blocks #69 and #70 for 32 Mbit
— blocks #37 and #38 for 16 Mbit
— blocks #21 and #22 for 8 Mbit
— blocks #13 and #14 for 4 Mbit
• For the bottom configuration, the bottom two parameter blocks are lockable. These are blocks
#0 and #1 for 4, 8 , 16, 32, and 64 Mbit.
Unlocked blocks can be programmed or erased normally (unless V is below V
).
PP
PPLK
12.2
WP# = VIH for Block Unlocking
WP# = V unlocks all lockable blocks. These blocks can now be programmed or erased.
IH
Note:
RP# does not override WP# locking for the B3 flash memory device, as in previous Boot Block
devices.
• WP# controls all block locking.
• V provides protection against spurious writes.
PP
Table 32 defines the write- protection methods.
Table 32.
Write-Protection Truth Table for the B3 Device Family
VPP
WP#
RP#
Write Protection Provided
X
X
X
VIL
VIH
VIH
VIH
All Blocks Locked
VIL
All Blocks Locked
≥ VPPLK
≥ VPPLK
VIL
VIH
Lockable Blocks Locked
All Blocks Unlocked
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13.0
V Program and Erase Voltages
PP
TheB3 flash memory device products provide in-system programming and erase at 2.7 V. For
customers requiring fast programming in their manufacturing environment, the B3 flash memory
device includes an additional low-cost 12-V programming feature.
The 12-V V mode enhances programming performance during the short period of time typically
PP
found in manufacturing processes. However, this mode is not intended for extended use. 12 V can
be applied to V during program and Erase operations for a maximum of 1000 cycles on the main
PP
blocks, and 2500 cycles on the parameter blocks. V can be connected to 12 V for a total of 80
PP
hours maximum.
Warning:
Stressing the flash memory device beyond these limits might cause permanent damage.
During Read operations or idle times, V can be tied to a 5-V supply. For Program and Erase
PP
operations, a 5-V supply is not permitted. The V must be supplied with either 2.7 V to 3.6 V or
PP
11.4 V to 12.6 V during Program and Erase operations.
13.1
VPP = VIL for Complete Protection
The V programming voltage can be held low for complete write protection of all blocks in the
PP
flash memory device. When V is below V
, any Program or Erase operation results in an
PP
PPLK
error, prompting the corresponding SR.3 to be set.
14.0
Additional Information
Order Number
Document/Tool
297948
292199
292200
Note 2
Intel Advanced Boot Block Flash Memory Family Specification Update
AP-641 Achieving Low Power with the 3 Volt Advanced Boot Block Flash Memory
AP-642 Designing for Upgrade to the 3 Volt Advanced Boot Block Flash Memory
3 Volt Advanced Boot Block Algorithms (‘C’ and assembly)
http://developer.intel.com/design/flash/swtools
Contact your Intel Representative
Intel® Flash Data Integrator (IFDI) Software Developer’s Kit
297874
IFDI Interactive: Play with Intel® Flash Data Integrator on Your PC
Notes:
1.
Call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers must contact
their local Intel or distribution sales office.
2.
3.
Visit the Intel home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools.
For the most current information about Intel Advanced Boot Block Flash memory and Intel Advanced+ Boot Block
Flash memory, visit http://developer.intel.com/design/flash/
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Appendix A Write State Machine Current/Next States
Table 33.
Write State Machine (Sheet 1 of 2)
Command Input (and Next State)
Data
When
Read
Read Program Erase
Array Setup Setup Confirm Suspend Resume
(FFH) (10/40H) (20H)
Erase
Prog/Ers Prog/Ers
Read
Clear
Read
Current
State
SR.7
Status Status Identifier.
(70H)
(D0H)
(B0H)
(D0H)
(50H)
(90H)
Read
Array
Program Erase
Setup Setup
Read
Status
Read
Array
Read
Identifier
Read Array
“1”
“1”
Array
Read Array
Read
Status
Read
Array
Program Erase
Setup Setup
Read
Status
Read
Array
Read
Identifier
Status
Read Array
Read Array
Read
Identifier
Read
Array
Program Erase
Read
Status
Read
Array
Read
Identifier
“1”
“1”
Identifier
Status
Setup
Setup
Prog. Setup
Program (Command Input = Data to be Programmed)
Prog.
Program
(continue)
Sysop. to
Rd.
Status
“0”
“1”
Status
Status
Program (continue)
Program (continue)
Prog.
Susp.
to
Read
Array
Prog.
Prog.
Program
Suspend to
Read
Program
Susp. to
Read
Prog.
Susp. to
Read
Program
(continue
)
Program
(continue
)
Susp.
to
Read
Array
Program Suspend
to Read Array
Susp.to
Read
Status
Status
Array
Identifier
Prog.
Susp.
to
Read
Array
Program
Susp. to
Read
Prog.
Susp.to Sus.to
Read
Status
Prog.
Prog.
Susp. to
Read
Program
Suspend to
Read Array
Program
(continue
)
Program
(continue
)
Program Suspend
to Read Array
“1”
“1”
Array
Read
Array
Array
Identifier
Prog.
Susp.
to
Read
Array
Program
Susp. to
Read
Prog.
Susp.to Sus.to
Read
Status
Prog.
Prog.
Susp. to
Read
Prog.Susp.
to Read
Identifier
Program
(continue
)
Program
(continue
)
Program Suspend
to Read Array
Identifier
Read
Array
Array
Identifier
Program
(complete)
Read
Array
Program Erase
Read
Status
Read
Array
Read
Identifier
“1”
“1”
“1”
Status
Status
Status
Read Array
Setup
Setup
Erase
(continue
)
Erase
Cant.
Error
Erase
(continue
)
Erase
Setup
Erase Command Error
Erase Command Error
EraseCant.
Error
Read
Array
Program Erase
Setup Setup
Read
Status
Read
Array
Read
Identifier
Read Array
Erase
Sus. to
Read
Erase
(continue)
“0”
Status
Erase (continue)
Erase (continue)
Status
18 Aug 2005
64
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 33.
Write State Machine (Sheet 2 of 2)
Command Input (and Next State)
Data
When
Read
Read Program Erase
Array Setup Setup Confirm Suspend Resume
(FFH) (10/40H) (20H)
Erase
Prog/Ers Prog/Ers
Read
Clear
Read
Current
State
SR.7
Status Status Identifier.
(70H)
(D0H)
(B0H)
(D0H)
(50H)
(90H)
Erase
Susp.
to
Read
Array
Erase
Susp.
to
Read
Array
Erase
Susp.
to
Read
Array
Erase
Susp. to
Read
Erase
Susp.to
Read
Ers.
Susp. to
Read
Erase
Suspend to
Status
Program
Setup
“1”
Status
Array
Erase
Erase
Array
Status
Identifier
Erase
Susp.
to
Read
Array
Erase
Susp.
to
Read
Array
Erase
Susp.
to
Read
Array
Erase
Susp. to
Read
Erase
Susp.to
Read
Ers.
Susp. to
Read
Erase
Susp. to
Read Array
Program
Setup
“1”
Erase
Erase
Erase
Erase
Array
Status
Identifier
Erase
Susp.
to
Read
Array
Erase
Susp.
to
Read
Array
Erase
Susp.
to
Read
Array
Erase
Susp. to
Read
Erase
Susp. to
Read
Erase
Susp.to
Read
Ers.
Susp. to
Read
Program
Setup
“1”
“1”
Identifier
Status
Identifier
Array
Status
Identifier
Erase
(complete)
Read
Array
Program Erase
Setup Setup
Read
Status
Read
Array
Read
Identifier
Read Array
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
65
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix B Program and Erase Flowcharts
Figure 15.
Program Flowchart
Start
Bus Operation
Write
Command
Program Setup
Program
Comments
Data = 40H
Write 40H
Data = Data to Program
Addr = Location to Program
Write
Program Address/Data
Read Status Register
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent programming operations.
No
SR.7 = 1?
Yes
SR Full Status Check can be done after each program or after a sequence of
program operations.
Write FFH after the last program operation to reset device to read array mode.
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
Standby
Command
Comments
Check SR.3
1
1 = VPP Low Detect
SR.3 =
VPP Range Error
Check SR.4
1 = VPP Program Error
Standby
0
SR.4 =
0
Check SR.1
1
1
1 = Attempted Program to
Locked Block - Program
Aborted
Standby
Programming Error
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
Attempted Program to
Locked Block - Aborted
SR.1 =
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases where multiple bytes are programmed before full status is checked.
0
If an error is detected, clear the status register before attempting retry or other
error recovery.
Program Successful
18 Aug 2005
66
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 16.
Program Suspend/Resume Flowchart
Bus
Operation
Command
Comments
Data = B0H
Start
Write B0H
Program
Suspend
Write
Write
Addr = X
Data = 70H
Addr = X
Read Status
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Write 70H
Read
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status Register
Standby
Check SR.2
1 = Program Suspended
0 = Program Completed
0
0
Standby
Write
SR.7 =
1
Data = FFH
Addr = X
Read Array
SR.2 =
Program Completed
Read array data from block
other than the one being
programmed.
Read
1
Program
Resume
Data = D0H
Addr = X
Write
Write FFH
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Program Resumed
Read Array Data
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
67
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 17.
Block Erase Flowchart
Start
Bus Operation
Command
Comments
Data = 20H
Write
Erase Setup
Addr = Within Block to Be
Erased
Write 20H
Data = D0H
Write
Read
Erase Confirm
Addr = Within Block to Be
Erased
Write D0H and
Block Address
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Read Status Register
Suspend
Erase Loop
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
No
0
Yes
SR.7 =
Suspend Erase
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase or after a sequence of
block erasures.
1
Full Status
Check if Desired
Write FFH after the last write operation to reset device to read array mode.
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
Bus Operation
Command
Comments
Check SR.3
Standby
1
1 = VPP Low Detect
SR.3 =
VPP Range Error
Check SR.4,5
Standby
Standby
Standby
Both 1 = Command Sequence
Error
0
SR.4,5 =
0
1
1
1
Check SR.5
1 = Block Erase Error
Command Sequence
Error
Check SR.1
1 = Attempted Erase of
Locked Block - Erase Aborted
SR.5 =
0
Block Erase Error
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases
where multiple bytes are erased before full status is checked.
Attempted Erase of
Locked Block - Aborted
SR.1 =
0
If an error is detected, clear the status register before attempting retry or other
error recovery.
Block Erase
Successful
18 Aug 2005
68
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 18.
Erase Suspend/Resume Flowchart
Bus Operation
Write
Command
Erase Suspend
Read Status
Comments
Data = B0H
Start
Write B0H
Addr = X
Data = 70H
Addr = X
Write
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Write 70H
Read
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status Register
Standby
Check SR.6
1 = Erase Suspended
0 = Erase Completed
0
Standby
Write
SR.7 =
1
Data = FFH
Addr = X
Read Array
0
SR.6 =
Erase Completed
Read array data from block
other than the one being
erased.
Read
1
Data = D0H
Addr = X
Write
Erase Resume
Write FFH
Read Array Data
No
Done
Reading
Yes
Write D0H
Write FFH
Erase Resumed
Read Array Data
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
69
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Appendix C Ordering Information
Figure 19.
Ordering Information
T E 2 8 F 3 2 0 B 3 T C 7 0
Package
TE = 48- Lead TSOP
Access Speed (ns)
GT = 48-Ball µBGA* CSP
GE = VF BGA CSP
(70, 80, 90, 100, 110)
RC = Easy BGA
Lithography
A = 0.25 µm
C = 0.18 µm
D = 0.13 µm
PC = Pb Free Easy BGA
PH = Pb Free VFBGA
JS = Pb Free TSOP
Product line designator
for all Inte®l Flash products
T = Top Blocking
B = Bottom Blocking
Device Density
640 = x16 (64 Mbit)
320 = x16 (32 Mbit)
160 = x16 (16 Mbit)
800 = x16 (8 Mbit)
Product Family
C3 = 3 Volt AdvancedBoot B
VCC = 2.7 V–3.6 V
VPP = 2.7 V–3.6 V or
11.4 V–12.6 V
Table 34.
Ordering Information: Valid Combinations (Sheet 1 of 2)
48-Ball µBGA CSP(1,2)
40-Lead TSOP
48-Lead TSOP
48-Ball VF BGA
Ext. Temp. 64 Mbit
Ext. Temp. 32 Mbit
TE28F640B3TC80
TE28F640B3BC80
GE28F640B3TC80
GE28F640B3BC80
TE28F320B3TD70
TE28F320B3BD70
TE28F320B3TC70
TE28F320B3BC70
TE28F320B3TC90
TE28F320B3BC90
TE28F320B3TA100
TE28F320B3BA100
TE28F320B3TA110
TE28F320B3BA110
JS28F320B3TD70
JS28F320B3BD70
GE28F320B3TD70
GE28F320B3BD70
GE28F320B3TC70
GE28F320B3BC70
GE28F320B3TC90
GE28F320B3BC90
PH28F320B3BD70
18 Aug 2005
70
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
Datasheet
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 34.
Ordering Information: Valid Combinations (Sheet 2 of 2)
48-Ball µBGA CSP(1,2)
40-Lead TSOP
48-Lead TSOP
48-Ball VF BGA
TE28F160B3TD70
TE28F160B3BD70
TE28F160B3TC70
TE28F160B3BC70
TE28F160B3TC80
TE28F160B3BC80
TE28F160B3TC90
TE28F160B3BC90
TE28F160B3TA90
TE28F160B3BA90
TE28F160B3TA110
TE28F160B3BA110
JS28F160B3TA70
JS28F160B3BD70
GE28F160B3TD70
GE28F160B3BD70
GE28F160B3TC70
GE28F160B3BC70
GE28F160B3TC80
GE28F160B3BC80
GE28F160B3TC90
GE28F160B3BC90
PH28F160B3TD70
PH28F160B3BD70
TE28F016B3TA90
TE28F016B3BA90
TE28F016B3TA110
TE28F016B3BA110
GT28F160B3TA90(3)
GT28F160B3BA90(3)
GT28F160B3TA110(3)
GT28F160B3BA110(3)
Ext. Temp. 16 Mbit
Ext. Temp. 8 Mbit
TE28F800B3TA90
TE28F800B3BA90
TE28F800B3TA110
TE28F800B3BA110
GE28F800B3TA70
GE28F800B3BA70
GE28F800B3TA90
GE28F800B3BA90
Notes:
1.
2.
3.
The 48-ball µBGA package top side mark reads F160B3. This mark is identical for both x8 and x16 products. All
product shipping boxes or trays provide the correct information regarding bus architecture. However, once the flash
memory devices are removed from the shipping media, differentiating based on the top side mark might be difficult. The
device identifier (accessible through the Device ID command: see Section 11.2, “Read Identifier” on page 56 for further
details) enables x8 and x16 µBGA package product differentiation.
The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the first
character signifies either:
– E for engineering samples, or
– S for silicon daisy-chain samples.
All other assembly codes without an E or an S as the first character are production units.
Intel recommends using.18 µm Intel Advanced Boot Block Products.
Datasheet
Intel® Advanced Boot Block Flash Memory (B3)
Order Number: 290580, Revision: 020
18 Aug 2005
71
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