TF28F020-90 [INTEL]
Flash, 256KX8, 90ns, PDSO32, 8 X 20 MM, REVERSE, TSOP-32;
| 型号： | TF28F020-90 |
| 厂家： | 
INTEL |
| 描述： | Flash, 256KX8, 90ns, PDSO32, 8 X 20 MM, REVERSE, TSOP-32 光电二极管 内存集成电路 |
| 文件： | 总29页 (文件大小：411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
28F020
2048K (256K x 8) CMOS FLASH MEMORY
Y
Y
Y
Flash Electrical Chip-Erase
Ð 2 Second Typical Chip-Erase
Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
Quick-Pulse Programming Algorithm
Ð 10 ms Typical Byte-Program
Ð 4 Second Chip-Program
Y
Y
Y
Noise Immunity Features
g
Ð Maximum Latch-Up Immunity
Ð
10% V
Tolerance
CC
Y
Y
Y
100,000 Erase/Program Cycles
through EPI Processing
g
12.0V 5% V
PP
ETOXTM Nonvolatile Flash Technology
Ð EPROM-Compatible Process Base
Ð High-Volume Manufacturing
Experience
High-Performance Read
Ð 70 ns Maximum Access Time
Y
CMOS Low Power Consumption
Ð 10 mA Typical Active Current
Ð 50 mA Typical Standby Current
Ð 0 Watts Data Retention Power
JEDEC-Standard Pinouts
Ð 32-Pin Plastic Dip
Ð 32-Lead PLCC
Ð 32-Lead TSOP
(See Packaging Spec., Order 231369)
Y
Integrated Program/Erase Stop Timer
Ý
Y
Extended Temperature Options
Intel’s 28F020 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F020 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on-
board during subassembly test; in-system during final test; and in-system after-sale. The 28F020 increases
memory flexibility, while contributing to time-and cost-savings.
The 28F020 is a 2048-kilobit nonvolatile memory organized as 262,144 bytes of 8 bits. Intel’s 28F020 is
offered in 32-pin plastic DIP, 32-lead PLCC, and 32-lead TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel’s ETOX (EPROM Tunnel Oxide) process
technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to
extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V V supply, the 28F020 performs
PP
100,000 erase and program cyclesÐwell within the time limits of the Quick-Pulse Programming and Quick-
Erase algorithms.
Intel’s 28F020 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 70 ns access time provides zero wait-state performance for a
wide range of microprocessors and microcontrollers. Maximum standby current of 100 mA translates into
power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved
through Intel’s unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on address
b
and data pins, from 1V to V
a
1V.
CC
With Intel’s ETOX process base, the 28F020 builds on years of EPROM experience to yield the highest levels
of quality, reliability, and cost-effectiveness.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
November 1995
Order Number: 290245-007
28F020
290245–1
Figure 1. 28F020 Block Diagram
Table 1. Pin Description
Symbol
A –A
Type
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
0
17
DQ –DQ
0
INPUT/OUTPUT
DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.
7
Ý
CE
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers,
Ý
Ý
decoders and sense amplifiers. CE is active low; CE high
deselects the memory device and reduces power consumption to
standby levels.
Ý
OE
INPUT
INPUT
OUTPUT ENABLE: Gates the devices output through the data buffers
Ý
during a read cycle. OE is active low.
Ý
WE
WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
Ý
and data is latched on the rising edge of the WE pulse.
s
Note: With V
6.5V, memory contents cannot be altered.
PP
V
PP
ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.
g
DEVICE POWER SUPPLY (5V 10%)
V
V
CC
GROUND
SS
2
28F020
290245–3
290245–2
290245–4
290245–5
Figure 2. 28F020 Pin Configurations
3
28F020
Material and labor costs associated with code
changes increases at higher levels of system inte-
gration Ð the most costly being code updates after
sale. Code ‘‘bugs’’, or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the re-
moval of EPROM components or entire boards. With
the 28F020, code updates are implemented locally
via an edge-connector, or remotely over a commun-
cations link.
APPLICATIONS
The 28F020 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These fea-
tures make the 28F020 an innovative alternative to
disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data-tables are
required, the 28F020’s reprogrammability and non-
volatility make it the obvious and ideal replacement
for EPROM.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory’s inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption Ð a consideration particularly impor-
tant in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and applica-
tion code. With updatable code, system manufactur-
ers can easily accommodate last-minute changes as
revisions are made.
Flash memory’s electrical chip erasure, byte pro-
grammability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a ‘‘blank slate’’ in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new ‘‘blank slate’’.
In diskless workstations and terminals, network traf-
fic reduces to a minimum and systems are instant-
on. Reliability exceeds that of electromechanical
media. Often in these environments, power interrup-
tions force extended re-boot periods for all net-
worked terminals. This mishap is no longer an issue
if boot code, operating systems, communication pro-
tocols and primary applications are flash-resident in
each terminal.
A high degree of on-chip feature integration simpli-
fies memory-to-processor interfacing. Figure 4 de-
picts two 28F020s tied to the 80C186 system bus.
The 28F020’s architecture minimizes interface cir-
cuitry needed for complete in-circuit updates of
memory contents.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F020 flash memory offers a solid
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. With stan-
dard and reverse pin configurations, TSOP reduces
the number of board layers and overall volume nec-
essary to layout multiple 28F020s. TSOP is particu-
larly suited for portable equipment and applications
requiring large amounts of flash memory. Figure 3
illustrates the TSOP Serpentine layout.
state alternative in
a minimal form factor. The
28F020 provides higher performance, lower power
consumption, instant-on capability, and allows an
‘‘execute in place’’ memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail.
With cost-effective in-system reprogramming, ex-
tended cycling capability, and true nonvolatility,
the 28F020 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today’s designs.
The need for code updates pervades all phases of a
system’s life Ð from prototyping to system manufac-
ture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F020 allows in-
circuit alterability; this eliminates unnecessary han-
dling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexi-
bility.
4
28F020
Figure 3. TSOP Serpentine Layout
5
28F020
290245–6
Figure 4. 28F020 in a 80C186 System
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or out-
put data for erase and program verification.
PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F020 introduces a command register to manage
this new functionality. The command register allows
for 100% TTL-level control inputs, fixed power sup-
plies during erasure and programming, and maxi-
mum EPROM compatibility.
Integrated Stop Timer
Successive command write cycles define the dura-
tions of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simpli-
fied timing control over these operations; thus elimi-
nating the need for maximum program/erase timing
specifications. Programming and erase pulse dura-
tions are minimums only. When the stop timer termi-
nates a program or erase operation, the device en-
ters an inactive state and remains inactive until re-
ceiving the appropriate verify or reset command.
In the absence of high voltage on the V pin, the
PP
28F020 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelli-
gent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is ap-
plied to the V pin. In addition, high voltage on V
PP
PP
enables erasure and programming of the device. All
functions associated with altering memory con-
tentsÐIntelligent Identifier, erase, erase verify, pro-
gram, and program verifyÐare accessed via the
command register.
Write Protection
The command register is only active when V is at
PP
high voltage. Depending upon the application, the
system designer may choose to make the V pow-
PP
er supply switchableÐavailable only when memory
Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming or erase operations. With
the appropriate command written to the register,
e
updates are desired. When V
V
, the con-
PPL
PP
tents of the register default to the read command,
making the 28F020 a read-only memory. In this
mode, the memory contents cannot be altered.
6
28F020
Table 2. 28F020 Bus Operations
(1)
Ý
Ý
Ý
WE
Mode
Read
Output Disable
READ-ONLY Standby
Intelligent Identifier (Mfr)
V
A
0
A
9
CE
OE
DQ –DQ
0
PP
7
V
A
A
V
V
V
V
V
Data Out
PPL
PPL
PPL
PPL
PPL
PPH
PPH
PPH
PPH
0
9
IL
IL
IH
V
V
V
V
X
X
V
Tri-State
Tri-State
IL
IH
IH
X
X
V
IH
X
X
(2)
(3)
e
e
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Data
Data
89H
IL
ID
ID
IL
IL
IL
IL
IH
IL
IL
IL
IH
IH
IH
IH
IH
(2)
(3)
Intelligent Identifier (Device)
Read
V
BDH
(4)
IH
V
V
V
V
A
A
Data Out
Tri-State
Tri-State
0
9
READ/WRITE Output Disable
X
X
V
(5)
Standby
Write
X
X
V
X
X
(6)
Data In
A
A
V
V
V
IL
0
9
IL
IH
NOTES:
1. Refer to DC Characteristics. When V
e
V
PPL
memory contents can be read but not written or erased.
PP
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All
other addresses low.
3.
V
4. Read operations with V
is the Intelligent Identifier high voltage. Refer to DC Characteristics.
e
ID
V
PPH
may access array data or the Intelligent Identifier codes.
PP
a
5. With V at high voltage, the standby current equals I
I
(standby).
PP
PP
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be V or V
CC
.
IH
IL
Or, the system designer may choose to ‘‘hardwire’’
, making the high voltage supply constantly
When V is high (V
PP
), the read operation can be
PPH
V
PP
used to access array data, to output the Intelligent
Identifier codes, and to access data for program/
erase verification. When V is low (V ), the read
available. In this case, all Command Register func-
tions are inhibited whenever V is below the write
lockout voltage V
CC
. (See Power Up/Down Protec-
PP
PPL
operation can only access the array data.
LKO
tion.) The 28F020 is designed to accommodate ei-
ther design practice, and to encourage optimization
of the processor-memory interface.
Output Disable
Ý
With OE at a logic-high level (V ), output from the
IH
The two step program/erase write sequence to the
Command Register provides additional software
write protection.
device is disabled. Output pins are placed in a high-
impedance state.
Standby
BUS OPERATIONS
Read
Ý
With CE at a logic-high level, the standby opera-
tion disables most of the 28F020’s circuitry and sub-
stantially reduces device power consumption. The
outputs are placed in a high-impedance state, inde-
The 28F020 has two control functions, both of which
must be logically active, to obtain data at the out-
Ý
pendent of the OE signal. If the 28F020 is dese-
Ý
puts. Chip-Enable (CE ) is the power control and
should be used for device selection. Output-Enable
lected during erasure, programming, or program/
erase verification, the device draws active current
until the operation is terminated.
Ý
(OE ) is the output control and should be used
to gate data from the output pins, independent of
device selection. Refer to AC read timing
waveforms.
7
28F020
The command register itself does not occupy an ad-
dressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manu-
facturer code (89H) and device code (BDH). Pro-
gramming equipment automatically matches the de-
vice with its proper erase and programming algo-
rithms.
Ý
The command register is written by bringing WE to
a logic-low level (V ), while CE is low. Addresses
Ý
IL
Ý
are latched on the falling edge of WE while data is
Ý
Ý
With CE and OE at a logic low level, raising A9
to high voltage V (see DC Characteristics) acti-
Ý
latched on the rising edge of the WE pulse. Stan-
dard microprocessor write timings are used.
ID
vates the operation. Data read from locations 0000H
and 0001H represent the manufacturer’s code and
the device code, respectively.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.
The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F020 is erased and reprogrammed in the tar-
get system. Following a write of 90H to the com-
mand register, a read from address location 0000H
outputs the manufacturer code (89H). A read from
address 0001H outputs the device code (BDH).
COMMAND DEFINITIONS
When low voltage is applied to the V pin, the con-
PP
tents of the command register default to 00H, en-
abling read-only operations.
Placing high voltage on the V pin enables read/
PP
write operations. Device operations are selected by
writing specific data patterns into the command reg-
Write
Device erasure and programming are accomplished
via the command register, when high voltage is ap-
ister. Table
commands.
3
defines these 28F020 register
plied to the V
pin. The contents of the register
PP
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.
Table 3. Command Definitions
Bus
First Bus Cycle
Second Bus Cycle
Command
Cycles
Req’d
(1)
(2)
Address
(3)
Data
(1)
(2)
Address
(3)
Data
Operation
Operation
Read Memory
1
3
2
2
2
2
2
Write
X
IA
X
00H
90H
20H
A0H
40H
C0H
FFH
(4)
Read Intelligent Identifier Codes
Write
Read
Write
Read
Write
Read
Write
IA
X
ID
(5)
Set-up Erase/Erase
Write
20H
EVD
PD
(5)
Erase Verify
Write
EA
X
X
(6)
Set-up Program/Program
Write
PA
X
(6)
Program Verify
Write
X
PVD
FFH
(7)
Reset
Write
X
X
NOTES:
1. Bus operations are defined in Table 2.
e
2. IA
EA
PA
Identifier address: 00H for manufacturer code, 01H for device code.
e
Erase Address: Address of memory location to be read during erase verify.
Program Address: Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
e
e
EVD
e
PD
PVD
e
e
89H, Device BDH).
3. ID
Identifier Address: Data read from location IA during device identification (Mfr
e
Erase Verify Data: Data read from location EA during erase verify.
Program Data: Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.
e
4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
5. Figure 6 illustrates the Quick-Erase Algorithm.
6. Figure 5 illustrates the Quick-Pulse Programming Algorithm.
7. The second bus cycle must be followed by the desired command register write.
8
28F020
of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.
Read Command
While V is high, for erasure and programming,
PP
memory contents can be accessed via the read
command. The read operation is initiated by writing
00H into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register con-
tents are altered.
Erase-Verify Command
The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing A0H into the command register. The address
for the byte to be verified must be supplied as it is
Ý
latched on the falling edge of the WE pulse. The
register write terminates the erase operation with the
Ý
rising edge of its WE pulse.
The default contents of the register upon V pow-
PP
er-up is 00H. This default value ensures that no spu-
rious alteration of memory contents occurs during
the V power transition. Where the V supply is
PP
PP
hard-wired to the 28F020, the device powers-up and
remains enabled for reads until the command-regis-
ter contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.
The 28F020 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
Intelligent Identifier Command
Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be ac-
cessible while the device resides in the target sys-
tem. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, mul-
tiplexing high voltage onto address lines is not a de-
sired system-design practice.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is com-
plete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 6, the Quick-Erase algorithm, illus-
trates how commands and bus operations are com-
bined to perform electrical erasure of the 28F020.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.
The 28F020 contains an Intelligent Identifier opera-
tion to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the com-
mand write, a read cycle from address 0000H re-
trieves the manufacturer code of 89H. A read cycle
from address 0001H returns the device code of
BDH. To terminate the operation, it is necessary to
write another valid command into the register.
Set-up Program/Program Commands
Set-up Erase/Erase Commands
Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.
Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.
Once the program set-up operation is performed,
Ý
the next WE pulse causes a transition to an active
programming operation. Addresses are internally
To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Ý
latched on the falling edge of the WE pulse. Data
Ý
WE pulse and terminates with the rising edge of
the next WE pulse (i.e., Erase-Verify Command).
Ý
is internally latched on the rising edge of the WE
Ý
Ý
pulse. The rising edge of WE also begins the pro-
gramming operation. The programming operation
Ý
This two-step sequence of set-up followed by execu-
tion ensures that memory contents are not acciden-
tally erased. Also, chip-erasure can only occur when
terminates with the next rising edge of WE used to
write the program-verify command. Refer to AC Pro-
gramming Characteristics and Waveforms for specif-
ic timing parameters.
high voltage is applied to the V pin. In the absence
PP
9
28F020
field greatly reduces oxide stress and the probability
of failure.
Program-Verify Command
The 28F020 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at ran-
dom. Following each programming operation, the
byte just programmed must be verified.
The 28F020 is capable of 100,000 program/erase
cycles. The device is programmed and erased using
Intel’s Quick-Pulse Programming and Quick-Erase
algorithms. Intel’s algorithmic approach uses a se-
ries of operations (pulses), along with byte verifica-
tion, to completely and reliably erase and program
the device.
The program-verify operation is initiated by writing
C0H into the command register. The register write
terminates the programming operation with the ris-
Ý
ing edge of its WE pulse. The program-verify oper-
ation stages the device for verification of the byte
last programmed. No new address information is
latched.
For further information, see Reliability Report RR-60.
QUICK-PULSE PROGRAMMING ALGORITHM
The 28F020 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 5,
the 28F020 Quick-Pulse Programming algorithm, il-
lustrates how commands are combined with bus op-
erations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.
The Quick-Pulse Programming algorithm uses pro-
gramming operations of 10 ms duration. Each opera-
tion is followed by a byte verification to determine
when the addressed byte has been successfully pro-
grammed. The algorithm allows for up to 25 pro-
gramming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with V at high voltage. Figure 5 illus-
PP
trates the Quick-Pulse Programming algorithm.
QUICK-ERASE ALGORITHM
Reset Command
Intel’s Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algo-
rithm employs a closed-loop flow, similar to the
Quick-Pulse Programming algorithm, to simulta-
neously remove charge from all bits in the array.
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.
Erasure begins with a read of memory contents. The
28F020 is erased when shipped from the factory.
Reading FFH data from the device would immedi-
ately be followed by device programming.
EXTENDED ERASE/PROGRAM CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some sup-
pliers have implemented redundancy schemes, re-
ducing cycling failures to insignificant levels. Howev-
er, redundancy requires that cell size be doubledÐ
an expensive solution.
For devices being erased and reprogrammed, uni-
form and reliable erasure is ensured by first pro-
gramming all bits in the device to their charged state
e
Quick-Pulse Programming algorithm, in approxi-
(Data
00H). This is accomplished, using the
mately four seconds.
Erase execution then continues with an initial erase
e
operation. Erase verification (data
FFH) begins at
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting im-
provements in cycling reliability come without in-
creasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carry-
ing ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probabili-
ty of oxide defects in the region. Finally, the peak
electric field during erasure is approximately
2 MV/cm lower than EEPROM. The lower electric
address 0000H and continues through the array to
the last address, or until data other than FFH is en-
countered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored ad-
dress location. Erasure typically occurs in two sec-
onds. Figure 6 illustrates the Quick-Erase algorithm.
10
28F020
Bus
Operation
Command
Comments
Standby
Wait for V Ramp to V (1)
PP PPH
Initialize Pulse-Count
e
40H
Write
Write
Set-up
Program
Data
Program
Valid Address/Data
Standby
Write
Duration of Program
)
Operation (t
WHWH1
(2)
e
Operation
Program
Verify
Data
C0H; Stops Program
(3)
Standby
Read
t
WHGL
Read Byte to Verify
Programming
Standby
Compare Data Output to Data
Expected
e
Data 00H, Resets the
Register for Read Operations
Write
Read
Standby
Wait for V Ramp to V (1)
PP PPL
290245–7
NOTES:
1. See DC Characteristics for the value of V
3. Refer to principles of operation.
and
PPH
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-
vice.
V
.
PPL
2. Program Verify is only performed after byte program-
ming. A final read/compare may be performed (option-
al) after the register is written with the Read command.
Figure 5. 28F020 Quick-Pulse Programming Algorithm
11
28F020
Bus
Operation
Command
Comments
e
Entire Memory Must
Before Erasure
00H
Use Quick-Pulse
Programming Algorithm
(Figure 5)
Standby
Wait for V Ramp to V (1)
PP PPH
Initialize Addresses and
Pulse-Count
e
e
Write
Write
Set-up
Erase
Data
Data
20H
20H
Erase
Standby
Write
Duration of Erase Operation
)
(t
WHWH2
(2)
e
e
Erase
Verify
Addr
Data
Byte to Verify;
A0H; Stops Erase
(3)
Operation
t
WHGL
Standby
Read
Read Byte to Verify Erasure
Standby
Compare Output to FFH
Increment Pulse-Count
e
Data 00H, Resets the
Register for Read Operations
Write
Read
Standby
Wait for V Ramp to V (1)
PP PPL
290245–8
1. See DC Characteristics for the value of V and
3. Refer to principles of operation.
PPH
V
.
PPL
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-
vice.
2. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
Figure 6. 28F020 Quick-Erase Algorithm
12
28F020
DESIGN CONSIDERATIONS
Two-Line Output Control
Power Up/Down Protection
The 28F020 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F020 is indifferent
Flash-memories are often used in larger memory ar-
rays. Intel provides two read-control inputs to ac-
commodate multiple memory connections. Two-line
control provides for:
as to which power supply, V or V , powers up
CC
PP
first. Power supply sequencing is not required.
Internal circuitry in the 28F020 ensures that the
command register is reset to the read mode on pow-
er up.
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
A system designer must guard against active writes
for V
voltages above V
when V
Since both WE and CE must be low for a com-
is active.
CC
LKO
PP
Ý
Ý
mand write, driving either to V will inhibit writes.
IH
To efficiently use these two control inputs, an ad-
dress-decoder output should drive chip-enable,
while the system’s read signal controls all flash-
memories and other parallel memories. This assures
that only enabled memory devices have active out-
puts, while deselected devices maintain the low
power standby condition.
The control register architecture provides an added
level of protection since alteration of memory con-
tents only occurs after successful completion of the
two-step command sequences.
28F020 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F020 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F020.
Power Supply Decoupling
Flash-memory power-switching characteristics re-
quire careful device decoupling. System designers
are interested in three supply current (I ) issuesÐ
standby, active, and transient current peaks pro-
duced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
CC
Table 4. 28F020 Typical
(4)
Update Power Dissipation
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 mF ceramic capacitor
Power Dissipation
Operation
Notes
(Watt-Seconds)
connected between V and V , and between V
SS
CC
PP
and V
.
Array Program/Program Verify
Array Erase/Erase Verify
One Complete Cycle
1
2
3
0.34
0.37
1.05
SS
Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 mF electrolytic capaci-
tor should be placed at the array’s power supply
connection, between V and V . The bulk capaci-
NOTES:
1. Formula to calculate typical Program/Program Verify
CC
SS
e
c
typical
typical
c
I
CC4
c
Bytes typical
[
I
c
Ý
Ý
typical)
Power
(t
V
Prog Pulse
tor will overcome voltage slumps caused by printed-
circuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.
PP
c
Bytes
a
c
a
]
[
V
t
I
WHWH1
PP2
WHGL
Ý
Prog Pulses (t
PP4
CC
typi-
c
cal
c
Ý
a
I
WHWH1
CC2
]
typical) .
t
WHGL
2. Formula to calculate typical Erase/Erase Verify Power
e
t
a
c
a
c
typical
[
WHGL
V
(I
PP PP3
typical
t
typical
I
ERASE
a
[
V (I
CC CC3
PP5
V
Trace on Printed Circuit Boards
c
c
typical t
ERASE
Ý
typical
]
Bytes)
typical
PP
c
c
Ý
WHGL
]
Bytes) .
I
t
CC5
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the V power sup-
ply trace. The V pin supplies the memory cell cur-
PP
rent for programming. Use similar trace widths and
e
a
Array Preprogram
3. One Complete Cycle
a
Array
Erase
Program.
4. ‘‘Typicals’’ are not guaranteed but based on a limited
number of samples from 28F020-150 production lots.
PP
layout considerations given the V
equate V
power bus. Ad-
supply traces and decoupling will de-
CC
PP
crease V voltage spikes and overshoots.
PP
13
28F020
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 C to 70 C
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
(1)
(1)
a
§
§
a
During Erase/Program ÀÀÀÀÀÀÀÀÀ0 C to 70 C
§
§
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 C to 85 C
(2)
(2)
b
a
§
§
b
a
During Erase/Program ÀÀÀÀÀÀ 40 C to 85 C
§
§
(1)
b
a
Temperature Under BiasÀÀÀÀÀÀÀ 10 C to 80 C
§
§
§
(2)
b
a
Temperature Under BiasÀÀÀÀÀÀÀ 50 C to 95 C
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 125 C
b
a
§
§
Voltage on Any Pin with
Respect to Ground ÀÀÀÀÀÀÀÀÀÀ 2.0V to 7.0V
Voltage on Pin A with
(2)
b
a
9
(2, 3)
b
a
Respect to Ground ÀÀÀÀÀÀÀ 2.0V to 13.5V
V
PP
Supply Voltage with
Respect to Ground
During Erase/ProgramÀÀÀÀ 2.0V to 14.0V
Supply Voltage with
(2, 3)
b
a
V
CC
(2)
b
a
Respect to Ground ÀÀÀÀÀÀÀÀÀÀ 2.0V to 7.0V
(4)
Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA
OPERATING CONDITIONS
Limits
Unit
Max
Symbol
Parameter
Min
(1)
T
A
Operating Temperature
Operating Temperature
0
70
C
C
§
§
(2)
b
a
85
T
A
40
(6)
V
V
V
Supply Voltage (10%)
4.50
4.75
5.50
5.25
V
CC
CC
CC
CC
(7)
V
Supply Voltage (5%)
V
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Operating temperature is for extended temperature product as defined by this specification.
b
b
3. Minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is V
a
a
0.5V, which may overshoot to V
2.0V for periods less than 20 ns.
CC
CC
a
4. Maximum DC voltage on A or V may overshoot to 14.0V for periods less than 20 ns.
PP
9
5. Output shorted for no more than one second. No more than one output shorted at a time.
6. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
7. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteris-
tics.
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐCommercial Products
Limits
Symbol
Parameter
Notes
Unit
Test Conditions
(4)
Min
Typ
Max
e
g
I
I
Input Leakage Current
1
1.0
mA
V
V
V
Max
CC
or V
SS
LI
CC
e
V
IN
CC
e
g
Output Leakage Current
1
10
mA
V
V
V
CC
Max
LO
CC
e
V
or V
SS
OUT
CC
14
28F020
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐCommercial
Products (Continued)
Limits
Symbol
Parameter
Notes
Unit
Test Conditions
(3)
Min Typ
Max
e
I
I
V
V
Standby Current
1
0.3
10
1.0
mA V
CC
CE
V
Max
CC
CCS
CC1
CC
CC
e
Ý
V
IH
e
6 MHz, I
e
V
e
0 mA
Ý
Active Read Current
1
30
mA V
f
V
Max, CE
CC
e
CC
IL
OUT
I
I
I
V
V
V
Programming Current
Erase Current
1, 2
1, 2
1, 2
1.0
5.0
5.0
10
15
15
mA Programming in Progress
mA Erasure in Progress
CC2
CC3
CC4
CC
CC
CC
e
V
PPH
Program Verify Current
mA V
PP
Program Verify in Progress
e
V
PPH
I
V
Erase Verify Current
1, 2
5.0
15
mA V
CC5
CC
PP
Erase Verify in Progress
s
g
I
I
V
V
Leakage Current
1
1
10
mA
mA
V
V
V
V
V
V
PPS
PP1
PP
PP
PP
PP
PP
PP
CC
CC
CC
l
s
e
Read Current, ID Current
90
8
200
or Standby Current
g
10
I
V
Programming Current
1, 2
30
mA V
V
PPH
PP2
PP
Programming in Progress
e
e
I
I
V
V
Erase Current
1, 2
1, 2
10
30
mA V
mA V
V
V
PP3
PP4
PP
PP
PP
PPH
Program Verify Current
2.0
5.0
PP
PPH
Program Verify in Progress
e
V
PPH
I
V
Erase Verify Current
1, 2
2.0
5.0
mA V
PP5
PP
PP
Erase Verify in Progress
b
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
0.8
V
V
V
IL
a
2.0
V
0.5
IH
OL
CC
e
e
0.45
V
V
5.8 mA
Min
CC
CC
I
OL
e
e b
V
V
Output High Voltage
2.4
V
V
V
V
Min
CC
2.5 mA
OH1
ID
CC
I
OH
A
Voltage
Intelligent Identifer
11.50
13.00
200
9
e
V
ID
I
A
Current
Intelligent Identifier
1, 2
90
mA
V
A
ID
9
9
V
V
V
V during Read-Only
PP
Operations
0.00
11.40
2.5
6.5
NOTE: Erase/Program are
PPL
PPH
LKO
e
V
PPL
Inhibited when V
PP
V during Read/Write
PP
Operations
12.60
V
V
Erase/Write Lock Voltage
V
CC
NOTES:
e
e
e
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
2. Not 100% tested: Characterization data available.
5.0V, V
PP
12.0V, T
25 C. These currents
§
CC
3. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.
15
28F020
DC CHARACTERISTICSÐCMOS COMPATIBLEÐCommercial Products
Limits
Symbol
Parameter
Notes
Unit
Test Conditions
(3)
Min
Typ
Max
e
g
I
I
I
I
Input Leakage Current
1
1.0
mA V
V
Max
LI
CC
IN
CC
e
V
V
or V
CC SS
e
g
Output Leakage Current
1
1
1
10
mA V
V
CC
Max
or V
CC SS
LO
CC
e
V
V
OUT
e
V
V
Standby Current
50
10
100
30
mA V
V
CC
Max
g
CCS
CC1
CC
CC
CC
e
Ý
CE
V
0.2V
CC
e
6 MHz, I
e
Ý
V
0 mA
Active Read Current
mA V
f
V
CC
Max, CE
e
CC
e
IL
OUT
I
I
I
V
V
V
Programming Current
Erase Current
1, 2
1, 2
1.0
5.0
5.0
10
15
15
mA Programming in Progress
mA Erasure in Progress
CC2
CC3
CC4
CC
CC
CC
e
V
PPH
Program Verify Current 1, 2
mA V
PP
Program Verify in Progress
e
V
PPH
I
V Erase Verify
CC
Current
1, 2
5.0
90
15
mA V
CC5
PP
Erase Verify in Progress
s
g
I
I
V
V
Leakage Current
Read Current,
1
1
10
mA V
mA V
V
V
CC
V
CC
V
CC
PPS
PP1
PP
PP
PP
PP
l
s
200
PP
ID Current or
Standby Current
g
10
e
Programming in Progress
I
I
I
I
V Programming
PP
Current
1, 2
1, 2
1, 2
1, 2
8
30
mA V
V
PPH
PP2
PP3
PP4
PP5
PP
e
V
PPH
V
Erase Current
10
2.0
2.0
30
5.0
5.0
mA V
PP
PP
Erasure in Progress
e
Program Verify in Progress
V
Program Verify
mA V
V
PPH
PP
PP
Current
Erase Verify
Current
e
V
PPH
V
mA V
PP
PP
Erase Verify in Progress
b
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
0.8
V
V
V
IL
a
0.7 V
V
CC
0.5
IH
OL
CC
e
e
0.45
V
V
Min
CC
CC
5.8 mA
I
OL
e
e b
V
V
V
V
I
V
Min
CC
2.5 mA
OH1
OH2
ID
CC
OH
0.85 V
CC
Output High Voltage
V
V
e
V
V Min
100 mA
CC
OH
CC
e b
b
V
CC
0.4
I
A
Voltage
Intelligent Identifer
11.50
13.00
200
9
e
V
ID
I
A
Current
Intelligent Identifier
1, 2
90
mA A
ID
9
9
V
PPL
V
PPH
V
LKO
V during Read-Only
PP
Operations
0.00
11.40
2.5
6.5
V
V
V
NOTE: Erase/Programs are
e
V
PPL
Inhibited when V
PP
V during Read/Write
PP
Operations
12.60
V Erase/Write Lock
CC
Voltage
16
28F020
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐExtended Temperature
Products
Limits
(3)
Symbol
Parameter
Notes
Unit
Test Conditions
Min Typ
Max
e
g
I
I
I
I
Input Leakage Current
Output Leakage Current
1
1.0
mA
V
V
V
Max
CC
or V
SS
LI
CC
IN
e
V
CC
e
g
1
1
1
10
mA
V
V
V
Max
CC
LO
CC
e
V
or V
SS
OUT
CC
e
V
V
Standby Current
0.3
10
1.0
mA V
CC
CE
V
Max
CC
CCS
CC1
CC
CC
e
Ý
V
IH
e
6 MHz, I
e
V
e
0 mA
Ý
Active Read Current
30
mA V
f
V
Max, CE
CC
e
CC
IL
OUT
I
I
I
V
V
V
Programming Current
Erase Current
1, 2
1, 2
1, 2
1.0
5.0
5.0
30
30
30
mA Programming in Progress
mA Erasure in Progress
CC2
CC3
CC4
CC
CC
CC
e
V
PPH
Program Verify Current
mA V
PP
Program Verify in Progress
e
V
PPH
I
V
Erase Verify Current
1, 2
5.0
30
mA V
CC5
CC
PP
Erase Verify in Progress
s
g
I
I
V
V
Leakage Current
1
1
10
mA
mA
V
V
V
V
V
V
PPS
PP1
PP
PP
PP
PP
PP
PP
CC
CC
CC
l
s
e
Read Current, ID Current
90
8
200
or Standby Current
g
10
I
V
Programming Current
1, 2
30
mA V
V
PPH
PP2
PP
Programming in Progress
e
e
I
I
V
V
Erase Current
1, 2
1, 2
10
30
mA V
mA V
V
V
PP3
PP4
PP
PP
PP
PPH
Program Verify Current
2.0
5.0
PP
PPH
Program Verify in Progress
e
V
PPH
I
V
Erase Verify Current
1, 2
2.0
5.0
mA V
PP5
PP
PP
Erase Verify in Progress
b
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
0.8
V
V
V
IL
a
2.0
V
0.5
IH
OL
CC
e
5.8 mA
0.45
I
OL
e
V
V
Min
CC
CC
e b
OH
V
V
Output High Voltage
2.4
V
V
I
2.5 mA
V Min
CC
OH1
ID
e
V
CC
A
Voltage
Intelligent Identifer
11.50
13.00
500
9
e
V
ID
I
A
Current
Intelligent Identifier
1, 2
90
mA
V
A
9
ID
9
V
V
V
V during Read-Only
PP
Operations
0.00
11.40
2.5
6.5
NOTE: Erase/Program are
PPL
PPH
LKO
e
V
PPL
Inhibited when V
PP
V during Read/Write
PP
Operations
12.60
V
V
Erase/Write Lock Voltage
V
CC
17
28F020
DC CHARACTERISTICSÐCMOS COMPATIBLEÐExtended Temperature
Products
Limits
Symbol
Parameter
Notes
Unit
Test Conditions
(3)
Min
Typ
Max
e
g
I
I
I
I
Input Leakage Current
1
1.0
mA V
V
Max
LI
CC
IN
CC
e
V
V
or V
CC SS
e
g
Output Leakage Current
1
1
1
10
mA V
V
CC
Max
or V
CC SS
LO
CC
e
V
V
OUT
e
V
V
Standby Current
50
10
100
50
mA V
V
CC
Max
g
CCS
CC1
CC
CC
CC
e
Ý
CE
V
0.2V
CC
e
6 MHz, I
e
Ý
V
0 mA
Active Read Current
mA V
f
V
CC
Max, CE
e
CC
e
IL
OUT
I
I
I
V
V
V
Programming Current
Erase Current
1, 2
1, 2
1.0
5.0
5.0
10
30
30
mA Programming in Progress
mA Erasure in Progress
CC2
CC3
CC4
CC
CC
CC
e
V
PPH
Program Verify Current 1, 2
mA V
PP
Program Verify in Progress
e
V
PPH
I
V Erase Verify
CC
Current
1, 2
5.0
90
30
mA V
CC5
PP
Erase Verify in Progress
s
g
I
I
V
V
Leakage Current
Read Current,
1
1
10
mA V
mA V
V
V
CC
V
CC
V
CC
PPS
PP1
PP
PP
PP
PP
l
s
200
PP
ID Current or
Standby Current
g
10
e
Programming in Progress
I
I
I
I
V Programming
PP
Current
1, 2
1, 2
1, 2
1, 2
8
30
mA V
V
PPH
PP2
PP3
PP4
PP5
PP
e
V
PPH
V
V
Erase Current
10
2.0
2.0
30
5.0
5.0
mA V
PP
PP
PP
Erasure in Progress
e
Program Verify in Progress
Program Verify
mA V
V
PPH
PP
Current
e
V
PPH
V Erase Verify
PP
Current
mA V
PP
Erase Verify in Progress
b
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
0.5
0.8
V
V
V
IL
a
0.7 V
V
CC
0.5
IH
OL
CC
e
e
0.45
V
V
Min
CC
CC
5.8 mA
I
OL
e
e b
V
V
V
V
I
V
Min
CC
2.5 mA
OH1
OH2
ID
CC
OH
0.85 V
CC
Output High Voltage
V
V
e
V
V Min
100 mA
CC
OH
CC
e b
b
V
CC
0.4
I
A
Voltage
Intelligent Identifer
11.50
13.00
500
9
e
V
ID
I
A
Current
Intelligent Identifier
1, 2
90
mA A
ID
9
9
V
PPL
V
PPH
V
LKO
V during Read-Only
PP
Operations
0.00
11.40
2.5
6.5
V
V
V
NOTE: Erase/Programs are
e
V
PPL
Inhibited when V
PP
V during Read/Write
PP
Operations
12.60
V Erase/Write Lock
CC
Voltage
18
28F020
NOTES:
e
e
e
1. All currents are in RMS unless otherwise noted. Typical values at V
are valid for all product versions (packages and speeds).
2. Not 100% tested: Characterization data available.
5.0V, V
PP
12.0V, T
25 C. These currents
§
CC
3. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.
e
e
CAPACITANCE T
25 C, f
§
1.0 MHz
A
Limits
Min Max
Symbol
Parameter
Notes
Unit
Conditions
e
C
C
Address/Control Capacitance
Output Capacitance
1
1
8
pF
pF
V
V
0V
IN
IN
e
12
0V
OUT
OUT
NOTE:
1. Sampled, not 100% tested.
(1)
TESTING INPUT/OUTPUT WAVEFORM
HIGH SPEED AC TESTING INPUT/OUTPUT
(2)
WAVEFORMS
290245–21
290245–22
AC test inputs are driven at V
(2.4 V
) for a Logic
TTL
) for a Logic ‘‘0’’. Input timing
OH
‘‘1’’ and V
(0.45 V
AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and
0.0V for a Logic ‘‘0’’. Input timing begins, and output
timing ends, at 1.5V. Input rise and fall times (10% to
OL
begins at V (2.0 V
ing ends at V and V . Input rise and fall times (10%
TTL
) and V (0.8 V
). Output tim-
IH
TTL IL TTL
IH IL
s
to 90%) 10 ns.
s
90%) 10 ns.
(1)
(2)
AC TESTING LOAD CIRCUIT
HIGH SPEED AC TESTING LOAD CIRCUIT
290245–23
290245–24
e
e
30 pF
includes Jig Capacitance
C
C
100 pF
includes Jig Capacitance
C
C
L
L
L
L
e
e
3.3 kX
R
L
3.3 kX
R
L
(1)
(2)
HIGH SPEED AC TEST CONDITIONS
AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%)ÀÀÀÀÀÀ10 ns
Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.45 and 2.4
Input Timing Reference Level ÀÀÀÀÀÀÀÀÀÀ0.8 and 2.0
Output Timing Reference LevelÀÀÀÀÀÀÀÀÀ0.8 and 2.0
Input Rise and Fall Times (10% to 90%)ÀÀÀÀÀÀ10 ns
Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.0 and 3.0
Input Timing Reference Level ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5
Output Timing Reference LevelÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5
Capacitive LoadC ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ100 pF
I
Capacitive Load C ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ30 pF
I
NOTES:
1. Testing characteristics for 28F020-70 in standard configuration, and 28F020-90 and 28F020-150.
2. Testing characteristics for 28F020-70 in high speed configuration.
19
28F020
20
28F020
Figure 7. AC Waveforms for Read Operations
21
28F020
22
28F020
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Notes
Unit
Min
Typ
2
Max
30
Chip Erase Time
1, 3, 4
1, 2, 4
Sec
Sec
Chip Program Time
4
25
NOTES:
1. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots. Data taken at 25 C, 12.0V
§
V
at 0 cycles.
PP
2. Minimum byte programming time excluding system overhead is 16 msec (10 msec program
a
6 msec write recovery),
while maximum is 400 msec/byte (16 msec x 25 loops allowed by algorithm). Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes 00H Programming prior to Erasure.
4. Excludes System-Level Overhead.
5. Refer to RR-60, 69 ‘‘ETOX Flash Memory Reliability Data Summaries’’ for typical cycling data and failure rate calculations.
23
28F020
290245–12
290245–13
Figure 8. 28F020 Typical Programming Capability
Figure 9. 28F020 Typical Program Time at 12V
290245–15
290245–14
NOTE:
Does not include Pre-Erase Program.
NOTE:
Does not include Pre-Erase Program.
Figure 11. 28F020 Typical Erase Time at 12.0V
Figure 10. 28F020 Typical Erase Capability
24
28F020
Figure 12. AC Waveforms for Programming Operations
25
28F020
Figure 13. AC Waveforms for Erase Operations
26
28F020
27
28F020
NOTE:
Alternative CE-Controlled Write Timings also apply to erase operations.
Figure 14. Alternate AC Waveforms for Programming Operations
28
28F020
ORDERING INFORMATION
290245–19
VALID COMBINATIONS:
P28F020-70
P28F020-90
P28F020-150
N28F020-70
N28F020-90
N28F020-150
TN28F020-90
E28F020-70
E28F020-90
E28F020-150
F28F020-70
F28F020-90
F28F020-150
TE28F020-90
TF28F020-90
ADDITIONAL INFORMATION
References
Order
Number
294005
ER-20
ER-24
ER-28
‘‘ETOXTM Flash Memory Technology’’
‘‘Intel Flash Memory’’
294008
294012
292046
292059
‘‘ETOXTM III Flash Memory Technology’’
AP-316 ‘‘Using Flash Memory for In-System Reprogrammable Nonvolatile Storage’’
AP-325 ‘‘Guide to Flash Memory Reprogramming’’
Revision History
Number
Description
-004
Removed Preliminary Classification. Clarified AC and DC test conditions. Added ‘‘dimple’’ to F
TSOP package. Corrected serpentine layout.
-005
-006
-007
Added -80V05, -90 ns speed grades. Added extended temperature devices. Corrected AC
Waveforms.
Ý
Added -70 ns speed. Deleted -80V05 speed. Revised symbols, i.e., CE, OE, etc. to CE , OE
etc.
Ý
,
Updated Command Def. Table. Updated 28F020 Quick-Erase Algorithm. Updated AC
Characteristics.
29
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