TN83C196MD_技术文档

8XC196MD

Table 2. 8XC196MD Memory Map

PROCESS INFORMATION

Description

Address

This device is manufactured on PX29.5, a CHMOS

III-E process. Additional process and reliability infor-

mation is available in the Intel Quality System

External Memory or I/O

0FFFFH

06000H

®

Handbook.

Internal ROM/EPROM or External

Memory (Determined by EA)

5FFFH

2080H

Reserved. Must contain FFH.

(Note 5)

207FH

205EH

PTS Vectors

205DH

2040H

Upper Interrupt Vectors

ROM/EPROM Security Key

203FH

2030H

x

202FH

2020H

272323–2

Reserved. Must contain FFH.

(Note 5)

201FH

201CH

Reserved. Must Contain 20H

(Note 5)

201BH

NOTE:

CCB1

201AH

2019H

EPROMs are available as One Time Programmable

(OTPROM) only.

Reserved. Must Contain 20H

(Note 5)

CCB0

2018H

Figure 2. The 8XC196MD Family Nomenclature

Reserved. Must contain FFH.

(Note 5)

2017H

2014H

Table 1. Thermal Characteristics

Package

Lower Interrupt Vectors

2013H

2000H

θ

jc

ja

Type

PLCC

QFP

35 C/W

13 C/W

°

SFR’s

1FFFH

1F00H

56 C/W

°

12 C/W

°

All thermal impedance data is approximate for static air

conditions at 1W of power dissipation. Values will change

depending on operation conditions and application. See

the Intel Packaging Handbook (order number 240800) for a

description of Intel’s thermal impedance test methodology.

External Memory

1EFFH

0200H

488 Bytes Register RAM (Note 1)

CPU SFR’s (Notes 1. 3)

01FFH

0018H

0017H

0000H

NOTES:

1. Code executed in locations 0000H to 01FFH will be

forced external.

2. Reserved memory locations must contain 0FFH unless

noted.

3. Reserved SFR bit locations must contain 0.

4. Refer to 8XC196MC for SFR descriptions.

5. WARNING: Reserved memory locations must not be

written or read. The contents and/or function of these lo-

cations may change with future revisions of the device.

Therefore, a program that relies on one or more of these

locations may not function properly.

3

8XC196MD

8XC196MC AND 8XC196MD

DIFFERENCES

PI MASK and PI PEND Registers

Ð Ð

The PI MASK/PI PEND registers contain the bits

Ð

for the Compare Module 5 (COMP5) Waveform Gen-

erator (WG), Timer 1 Overflow (TFI), and Timer 2

Overflow (TF2) mask/status flag. The diagram be-

low shows the registers. Notice that the COMP5 bit

is a reserved bit on the 8XC196MC. The 8XC196MC

User’s Manual should be referenced for details

about the Waveform Generator, Compare Modules,

and Timers.

INT MASK1/INT PEND1 Registers

Ð Ð

There are some differences between the

8XC196MC and 8XC196MD INT MASK1/

INT PEND1 registers. The 8XC196MD interrupt

Ð

mask and pending registers are shown below. No-

tice that the CAPCOM5, COMP4, and CAPCOM4

bits are reserved bits on the 8XC196MC. The PI bit

of the INT PEND1 register will be set when a

Ð

Waveform Generator or Compare Module 5 event

occurs and the corresponding bit in the PI MASK

PI MASK (1FBEH) and

Ð

PI PEND (1FBCH, Read Only)

Ð

register is set. The PI interrupt vector can be taken

Ð

7

6

5

4

3

2

1

0

when the PI bit in the INT MASK1 register is set.

Ð

The 8XC196MC User’s Manual should be refer-

enced for details about the interrupts.

RSV

COMP5*

RSV

WG

RSV

TF2

RSV

TF1

e

RSV

RESERVED BIT. MUST WRITE AS 0,

READ AS 1.

THIS BIT RESERVED ON 8XC196MC.

e

*

INT MASK1 (0031H)

Ð

and INT PEND1 (0012H)

Figure 5. Peripheral Interrupt Mask

and Status Registers

Ð

7

6

5

4

3

2

1

0

RSV EXTINT PI CAPCOM5* COMP4* CAPCOM4* COMP3 CAPCOM3

The PI bit in the INT PEND1 register is set if a

Ð

Waveform Generator event or Compare Module 5

event occurs and the corresponding PI MASK bit is

Ð

set. For either of these events to cause an interrupt,

e

RSV

e

RESERVED BIT. MUST WRITE AS 0

THIS BIT RESERVED ON 8XC196MC.

*

Figure 3. Interrupt Mask and Status Registers

the PI bit in the INT MASK1 register and the corre-

Ð

sponding event bit in the PI MASK register must be

Ð

set.

PTSSRV and PTSSEL Register

Similarly, the TOVF bit in the INT PEND register is

Ð

set if Timer 1 or Timer 2 overflow and the corre-

sponding bit in the PI MASK register is set. For ei-

Ð

ther of these two events to cause an interrupt, the

TOVF bit in the INT MASK register and the corre-

Ð

sponding event bit in the PI MASK must be set.

Ð

Similarly, there are differences between 8XC196MC

and 8XC196MD PTS registers. The 8XC196MD PTS

registers are shown below. Notice the CAPCOM5,

COMP4, and CAPCOM4 bits are reserved bits on

the 8XC196MC. The PI bit in the PTSSRV will be set

when a Waveform Generator or Compare Module 5

end of PTS interrupt occurs and the corresponding

Upon a PI and/or a TOVF interrupt, it may be neces-

sary to check if the Compare Module 5, the Wave-

form Generator, Timer 1, or Timer 2 event caused

the interrupt. The PI PEND will give this informa-

Ð

tion. However, it should be noted that reading the

bit in the PI MASK register is set. The PI PTS vec-

Ð

tor can be used when the PI bit in the PTSSEL regis-

ter is set. The 8XC196MC User’s Manual should be

referenced for details about the PTS.

PI PEND register will clear the register. So the indi-

Ð

vidual bits in the PI PEND register must be read by

Ð

PTSSEL (0004H) and PTSSRV (0006H)

10

loading PI PEND into another ‘‘shadow’’ register,

Ð

15

14

13

12

11

9

8

then checking the ‘‘shadow’’ register to see what

event occurred.

RSV EXTINT

PI

CAPCOM5* COMP4* CAPCOM4* COMP3 CAPCOM3

7

6

5

4

3

2

1

0

COMP2 CAPCOM2 COMP1 CAPCOM1 COMP0 CAPCOM0 AD DONE TOVF

Ð

e

RSV

e

RESERVED BIT. MUST WRITE AS 0

THIS BIT RESERVED ON 8XC196MC.

*

Figure 4. PTS Select and Service Registers

4

8XC196MD

Table 3. Interrupt Sources, Vectors and Priorities

Interrupt Service

PTS Service

Interrupt Source

Capture/Compare5

Compare4

Symbol

CAPCOMP5

COMP4

Name

INT12

INT11

INT10

Vector

2038H

2036H

2034H

Priority

12

Name

PTS12

PTS11

PTS10

Vector

2058H

2056H

2054H

Priority

27

11

26

Capture/Compare4

CAPCOMP4

10

25

Interrupt and PTS Vectors

Port 7

The 8XC196MD has three new interrupt and PTS

vectors which are Capture/Compare5, Compare 4,

and Capture/Compare4. Table 3 shows these inter-

rupt vectors and priorities. These are shown as re-

served vectors in the 8XC196MC User’s Manual.

Port 7 is an additional bidirectional port that was not

available on the 8XC196MC device. Port 7 can be

used as I/O or some of the pins have special func-

tions. The pins are listed below followed by their

special functions.

Table 4. Port 7 Special Function Pins

Frequency Generator

Special Function

CAPCOMP4

CAPCOMP5

CAPCOMP4

CAPCOMP5

The Frequency Generator (FG) Peripheral which

was not available on the 8XC196MC device, is avail-

able on the 8XC196MD device. The FG outputs a

programmable-frequency 50% duty cycle waveform

on the FREQOUT pin (P7.7). There are two 8-bit reg-

isters which control the FG peripheral:

P7.0

P7.1

P7.2

P7.3

P7.4

P7.5

P7.6

P7.7

Ð Frequency Generator Control Register

(FG CON) at 1FB8h

Ð

Ð Frequency Generator Period Count Register

(FG COUNT) at 1FBAh.

Ð

FREQOUT

The FG CON can be read or written. This register

Ð

is loaded with a value which determines the number

of counts necessary for toggling the output. The fol-

lowing equation should be used to calculate the

The special functions of the pins are selected in the

Port 7 SFRs. The Port 2 I/O Port section of the

8XC196MC User’s Manual can be referenced when

setting up the Port 7 SFRs. Port 7 SFRs are located

in the following locations:

FG CON value:

Ð

F

XTAL

e

b

1

FG CON value

Ð

16 * (FG Frequency)

Table 5. Port 7 Special Function Registers

where FG Frequency is from 4 kHz to 1 MHz.

SFR

Address

1FD1h

1FD3h

1FD5h

1FD7h

P7 MODE

Ð

The FG COUNT is loaded with the FG CON reg-

Ð Ð

ister value. The FG COUNT register is decrement-

Ð

ed every eighth state time. When it reaches 00h, the

P7 DIR

Ð

FG COUNT register will send a signal to toggle the

Ð

P7 REG

Ð

output pin and reload the FG COUNT register with

Ð

P7 PIN

Ð

the value in the FG CON register. The

Ð

FG COUNT can only be read, not written.

Ð

The FREQOUT pin (P7.7) must be configured for a

special function to use it for the Frequency Genera-

tor feature.

5

8XC196MD

Port 1

NOTE:

pin on the 8XC196MC device. If

P1.5 was a V

SS

P1.5 and P1.6 are not being used these pins can

remain connected to V

There are three additional Port 1 input pins (P1.5–

P1.7) that were not available on the 8XC196MC.

These pins are listed below followed by their func-

tion:

.

SS

Table 6. New 8XC196MD Port 1 Pins

Description

Digital or Analog Input

Digital Input

P1.5

P1.6

P1.7

Digital Input

6

8XC196MD

272323–3

NOTE:

NC means No Connect. Do not connect these pins.

Figure 6. 84-Lead PLCC Package

7

8XC196MD

272323–4

Figure 7. 80-Lead Shrink EIAJQFP (Quad Flat Pack)

8

8XC196MD

PIN DESCRIPTIONS (Alphabetically Ordered)

Symbol

Function

ACH0–ACH13

(P0.0–P0.7, P1.0–P1.5)

Analog inputs to the on-chip A/D converter. ACH0–7 share the input pins

with P0.0–7 and ACH8–13 share pins with P1.0–5. If the A/D is not used,

the port pins can be used as standard input ports.

ANGND

Reference ground for the A/D converter. Must be held at nominally the

.

same potential as V

SS

ALE/ADV(P5.0)

Address Latch Enable or Address Valid output, as selected by CCR. Both

options allow a latch to demultiplex the address/data bus on the signal’s

falling edge. When the pin is ADV, it goes inactive (high) at the end of the

bus cycle. ALE/ADV is active only during external memory accesses. Can be

used as standard I/O when not used as ALE/ADV.

BHE/WRH (P5.5)

BUSWIDTH (P5.7)

Byte High Enable or Write High output, as selected by the CCR. BHE will go

low for external writes to the high byte of the data bus. WRH will go low for

external writes where an odd byte is being written. BHE/WRH is activated

only during external memory writes.

e

Input for bus width selection. If CCR bits 1 and 2

1, this pin dynamically

controls the bus width of the bus cycle in progress. If BUSWIDTH is low, an

8-bit cycle occurs. If it is high, a 16-bit cycle occurs. This pin can be used as

standard I/O when not used as BUSWIDTH.

CAPCOMP0–CAPCOMP5

(P2.0–P2.3, P7.0–P7.1)

The EPA Capture/Compare pins. CAPCOMP0–3 share the pins with

P2.0–P2.3. CAPCOMP4–5 share the pins with P7.0–P7.1. If not used for the

EPA, they can be configured as standard I/O pins.

CLKOUT

Output of the internal clock generator. The frequency is (/2 of the oscillator

frequency. It has a 50% duty cycle.

COMPARE0–COMPARE5

(P2.4–P2.7, P7.2–P7.3)

The EPA Compare pins. COMPARE0–3 share the pins with P2.4–P2.7.

COMPARE4–5 share the pins with P7.2–P7.3. If not used for the EPA, they

can be configured as standard I/O pins.

e

EA

External Access enable pin. EA

e

0 causes all memory accesses to be

external to the chip. EA

to 5FFFH to be from the on-chip OTPROM/ROM. EA

1 causes memory accesses from location 2000H

e

12.5V causes

execution to begin in the programming mode. EA is latched at reset.

EXTINT

FREQOUT

INST (P5.1)

NMI

A programmable input on this pin causes a maskable interrupt vector

through memory location 203CH. The input may be selected to be a

positive/negative edge or a high/low level using WG PROTECT (1FCEH).

Ð

Programmable frequency output pin. The frequency can vary from 4 KHz to 1

MHz (16 MHz input clock). It has a 50% duty cycle. Pin may be configured as

standard I/O if FREQOUT is not used.

INST is high during the instruction fetch from the external memory and

throughout the bus cycle. It is low otherwise. This pin can be configured as

standard I/O if not used as INST.

A positive transition on this pin causes a non-maskable interrupt which

vectors to memory location 203EH. If not used, it should be tied to V . May

be used by Intel Evaluation boards.

SS

PORT0

8-bit high impedance input-only port. Also used as A/D converter inputs.

Port0 pins should not be left floating. These pins also used to select

programming modes in the OTPROM devices.

PORT1

8-bit high impedance input-only port. P1.0–P1.5 are also used as A/D

converter inputs. In addition, P1.2 and P1.3 can be used as Timer 1 clock

input and direction select respectively. P1.6–P1.7 can be used as input-only

pins.

9

8XC196MD

PIN DESCRIPTIONS (Alphabetically Ordered) (Continued)

Symbol

Function

PORT2

8-bit bidirectional I/O port. All of the Port2 pins are shared with the EPA I/O

pins (CAPCOMP0–3 and COMPARE0–3).

PORT3

PORT4

8-bit bidirectional I/O ports with open drain outputs. These pins are shared

with the multiplexed address/data bus which uses strong internal pullups.

PORT5

8-bit bidirectional I/O port. 7 of the pins are shared with bus control signals

(ALE, INST, WR, RD, BHE, READY, BUSWIDTH). Can be used as standard

I/O.

PORT6

PORT7

8-bit output port. P6.6 and P6.7 output PWM, the others are used as the Wave

Form Generator outputs. Can be used as standard output ports.

8-bit bidirectional I/O port. P7.0–P7.3 can be used as EPA I/O pins

(CAPCOMP4–5 and COMPARE4–5). P7.7 can be used as FREQOUT output

pin. P7.4–P7.6 are standard I/O pins.

PWM0, PWM1

(P6.6, P6.7)

Programmable duty cycle, Programmable frequency Pulse Width Modulator

pins. The duty cycle has a resolution of 256 steps, and the frequency can vary

from 122 Hz to 31 KHz (16 MHz input clock). Pins may be configured as

standard output if PWM is not used.

RD (P5.3)

Read signal output to external memory. RD is low only during external memory

reads. Can be used as standard I/O when not used as RD.

e

0, the memory

READY (P5.6)

Ready input to lengthen external memory cycles. If READY

controller inserts wait states until the next positive transition of CLKOUT

e

occurs with READY

READY.

1. Can be used as standard I/O when not used as

RESET

Reset input to and open-drain output from the chip. Held low for at least 16

state times to reset the chip. Input high for normal operation. RESET has an

Ohmic internal pullup resistor.

T1CLK

(P1.2)

Timer 1 Clock input. This pin has two other alternate functions: ACH10 and

P1.2.

T1DIR

(P1.3)

Timer 1 Direction input. This pin has two other alternate functions: ACH11 and

P1.3.

V

The programming voltage is applied to this pin. It is also the timing pin for the

return from Power Down circuit. Connect this pin with a 1 mF capacitor to V

PP

SS

and a 1 MX resistor to V . If the Power Down feature is not used, connect

CC

the pin to V

.

CC

WG1–WG3/WG1–WG3

(P6.0–P6.5)

3 phase output signals and their complements used in motor control

applications. The pins can also be configured as standard output pins.

WR/WRL (P5.2)

Write and Write Low output to external memory. WR will go low every external

write. WRL will go low only for external writes to an even byte. Can be used as

standard I/O when not used as WR/WRL.

XTAL1

XTAL2

Input of the oscillator inverter and the internal clock generator. This pin should

be used when using an external clock source.

Output of the oscillator inverter.

PMODE

(P0.4–7)

Determines the EPROM programming mode.

PACT

(P2.5)

A low signal in Auto Programming mode indicates that programming is in

process. A high signal indicates programming is complete.

10

8XC196MD

PIN DESCRIPTIONS (Alphabetically Ordered) (Continued)

Symbol

Function

PALE

(P2.1)

A falling edge in Slave Programming Mode and Auto Configuration Byte

Programming Mode indicates that ports 3 and 4 contain valid programming

address/command information (input to slave).

PROG

(P2.2)

A falling edge in Slave Programming Mode begins programming. A rising edge

ends programming.

PVER

(P2.0)

A high signal in Slave Programming Mode and Auto Configuration Byte

Programming Mode indicates the byte programmed correctly.

CPVER

(P2.6)

Cumulative Program Verification. Pin is high if all locations since entering a

programming mode have programmed correctly.

AINC

(P2.4)

Auto Increment. Active low input enables the auto increment mode. Auto

increment will allow reading or writing of sequential EPROM locations without

address transactions across the PBUS for each read or write.

11

8XC196MD

ABSOLUTE MAXIMUM RATINGS

NOTICE: This data sheet contains preliminary infor-

mation on new products in production. The specifica-

tions are subject to change without notice. Verify with

your local Intel Sales office that you have the latest

data sheet before finalizing a design.

Ambient Temperature

Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 C to 85 C

b

a

§

Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C

§

b

a

§

*WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

Voltage from EA or V

PP

b

a

to V or ANGNDÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 13.00V

SS

Voltage on Any Other Pin

(1)

b

a

to V or ANGND ÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 7.0V

SS

(2)

Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W

NOTES:

1. This includes V and EA on ROM or CPU only devices.

PP

2. Power dissipation is based on package heat transfer lim-

itations, not device power consumption.

OPERATING CONDITIONS

Symbol

Description

Ambient Temperature Under Bias

Digital Supply Voltage

Min

Max

Units

b

a

85

T

A

40

C

§

V

CC

4.50

4.00

8

5.50

16

V

Analog Supply Voltage

Oscillator Frequency

REF

OSC

F

MHz

NOTE:

ANGND and V should be nominally at the same potential. Also V and V

must be at the same potential.

SS1

S

DC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions)

Symbol

Parameter

Input Low Voltage

Min

Max

0.3 V

Units

Test Conditions

b

V

0.5

V

IL

CC

a

0.5

Input High Voltage

0.7 V

V

CC

IH

OL

CC

e

Output Low Voltage

Port 2, 5, and 7, P6.6, P6.7,

CLKOUT

0.3

0.45

1.5

V

I

200 mA

3.2 mA

7 mA

OL

e

V

Output Low Voltage on Port 3/4

1.0

V

I

15 mA

10 mA

OL1

OL2

OL

Output Low Voltage on

Port 6.0–6.5

0.45

b

e b

V

Output High Voltage

V

0.3

0.7

1.5

V

I

200 mA

3.2 mA

7 mA

OH

CC

OH

–V

Hysteresis Voltage Width on

RESET

0.2

V

Typical

a

b

th

12

8XC196MD

DC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions) (Continued)

Symbol

Parameter

Min Typ Max Units

Test Conditions

k

g

I

Input Leakage Current on All Input

Only Pins

10 mA 0V

V

–0.3V (in RESET)

CC

LI

IN

k

g

Input Leakage Current on Port0

and Port1

3

mA 0V

V

LI1

IL

IN

REF

b

e

0.3 V

Input Low Current on BD Ports

(Note 1)

70 mA

V

IN

CC

Input Low Current on P5.4 and

P2.6 during Reset (Note 3)

10 mA 0.2 V

mA 0.7 V

IL1

OH

CC

b

Output High Current on P5.4 and

P2.6 during Reset (Note 4)

2

CC

e

I

Active Mode Current in Reset

A/D Conversion Reference Current

Idle Mode Current

50

2

70

mA XTAL1

16 MHz,

e

CC

e

V

PP

V

5.5V

CC

REF

5

mA

X

REF

IDL

PD

15

5

30

50

65k

10

e

Power-Down Mode Current

RESET Pin Pullup Resistor

V

PP

V

REF

R

6k

RST

S

e

C

Pin Capacitance (Any Pin to V

)

SS

pF

F

1.0 MHz

TEST

NOTES:

1. BD (Bidirectional ports) include:

P2.0–P2.7, except P2.6

P3.0–P3.7

P4.0–P4.7

P5.0–P5.3

P5.5–P5.7

P7.0–P7.7

2. During normal (non-transient) conditions, the following total current limits apply:

P6.0–P6.5

P3

P4

P5, CLKOUT

P2, P6.6, P6.7, P7

I

:

40 mA

90 mA

35 mA

63 mA

I

:

28 mA

42 mA

35 mA

63 mA

OL

OH

3. Maximum current that must be sunk by external device to ensure test mode entry.

4. Do not exceed minimum current or device may enter test mode.

13

8XC196MD

EXPLANATION OF AC SYMBOLS

Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its

condition, respectively. Symbols represent the time between the two signal/condition points.

Conditions:

Signals:

H

L

Ð High

A

B

C

D

G

H

Ð Address

L

Ð ALE/ADV

Ð Low

Ð BHE

BR Ð BREQ

V

X

Z

Ð Valid

Ð CLKOUT

Ð DATA

R

W

X

Ð RD

Ð No Longer Valid

Ð Floating

Ð WR/WRH/WRL

Ð XTAL1

Ð Buswidth

Ð HOLD

Y

Ð READY

Ð Data Out

HA Ð HLDA

Q

AC ELECTRICAL CHARACTERISTICS (Over Specified Operating Conditions)

e

16 MHz.

OSC

Test Conditions: Capacitive load on all pins

100 pF, Rise and fall times

10 ns, F

The system must meet the following specifications to work with the 87C196MD:

Symbol

Parameter

Min

8

Max

16

Units

MHz

ns

Notes

F

T

Frequency on XTAL1

3

XTAL

OSC

1/F

62.5

125

XTAL

b

OSC

Address Valid to READY Setup

ALE Low to READY Setup

2 T

75

ns

AVYV

LLYV

YLYH

CLYX

LLYX

AVGV

LLGV

CLGX

AVDV

RLDV

CLDV

RHDZ

RXDX

b

T

70

ns

4

OSC

Not READY Time

No Upper Limit

ns

b

READY Hold after CLKOUT Low

READY Hold after ALE Low

Address Valid to BUSWIDTH Setup

ALE Low to BUSWIDTH Setup

Buswidth Hold after CLKOUT Low

Address Valid to Input Data Valid

RD Active to Input Data Valid

CLKOUT Low to Input Data Valid

End of RD to Input Data Float

Data Hold after RD Inactive

0

T

30

ns

1

OSC

b

T

15

2 T

40

75

ns

OSC

b

ns

b

T

60

ns

4

OSC

0

ns

b

3 T

55

ns

2

OSC

b

T

22

ns

OSC

b

50

ns

T

ns

OSC

0

ns

NOTES:

1. If Max is exceeded, additional wait states will occur.

e

3. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.

2. If wait states are used, add 2 T

* N, where N

number of wait states.

OSC

b

4. These timings are included for compatibility with older 90 and BH products. They should not be used for newer high-

speed designs.

14

8XC196MD

AC ELECTRICAL CHARACTERISTICS (Continued)

e

16 MHz.

OSC

Test Conditions: Capacitive load on all pins

100 pF, Rise and fall times

10 ns, F

The 87C196MD will meet the following timing specifications:

Symbol

Parameter

Min

Max

110

Units

ns

Notes

T

XTAL1 to CLKOUT High or Low

CLKOUT Cycle Time

30

XHCH

CLCL

CHCL

CLLH

LLCH

LHLH

LHLL

2 T

OSC

T

b

a

OSC

CLKOUT High Period

T

10

15

10

OSC

b

CLKOUT Falling Edge to ALE Rising

ALE Falling Edge to CLKOUT Rising

ALE Cycle Time

5

15

b

20

4 T

3

OSC

T

b

a

OSC

ALE High Period

T

10

OSC

Address Setup to ALE Falling Edge

Address Hold after ALE Falling

ALE Falling Edge to RD Falling

RD Low to CLKOUT Falling Edge

RD Low Period

15

40

30

AVLL

LLAX

LLRL

4

30

RLCL

RLRH

RHLH

RLAZ

LLWL

CLWL

QVWH

CHWH

WLWH

WHQX

WHLH

WHBX

WHAX

RHBX

RHAX

b

a

T

5

T

25

3

1

OSC

a

RD Rising Edge to ALE Rising Edge

RD Low to Address Float

T

OSC

5

b

ALE Falling Edge to WR Falling

CLKOUT Low to WR Falling Edge

Data Stable to WR Rising Edge

CLKOUT High to WR Rising Edge

WR Low Period

T

10

23

OSC

0

25

15

b

OSC

b

10

b

T

30

25

10

30

10

30

3

1

2

OSC

Data Hold after WR Rising Edge

WR Rising Edge to ALE Rising Edge

BHE, INST Hold after WR Rising

AD8–15 Hold after WR Rising

BHE, INST Hold after RD Rising

AD8–15 Hold after RD Rising

a

T

15

OSC

NOTES:

1. Assuming back to back cycles.

2. 8-bit bus only.

3. If wait states are used, add 2 T

e

number of wait states.

*N, where N

OSC

15

8XC196MD

SYSTEM BUS TIMINGS

272323–5

16

8XC196MD

READY TIMINGS (One Wait State)

272323–6

BUSWIDTH TIMINGS

272323–7

17

8XC196MD

EXTERNAL CLOCK DRIVE

Symbol

1/T

Parameter

Min

8

Max

16.0

125

Units

MHz

ns

Oscillator Frequency

Oscillator Period

High Time

XLXL

T

62.5

22

XLXL

ns

XHXX

XLXX

XLXH

XHXL

Low Time

22

ns

Rise Time

10

ns

Fall Time

ns

EXTERNAL CRYSTAL CONNECTIONS

EXTERNAL CLOCK CONNECTIONS

272323–8

272323–9

* Required if TTL driver used.

Not needed if CMOS driver is used.

NOTE:

Keep oscillator components close to chip and use

short, direct traces to XTAL1, XTAL2 and V . When

SS

e

20 pF. When using

e

using crystals, C1

20 pF, C2

ceramic resonators, consult manufacturer for recom-

mended circuitry.

EXTERNAL CLOCK DRIVE WAVEFORMS

272323–10

An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to

interaction between the amplifier and its feedback capacitance. Once the external signal meets the V and

IL

V

IH

specifications the capacitance will not exceed 20 pF.

AC TESTING INPUT, OUTPUT WAVEFORMS

FLOAT WAVEFORMS

272323–11

272323–12

AC Testing inputs are driven at 3.5V for a Logic ‘‘1’’ and 0.45V for

a Logic ‘‘0’’. Timing measurements are made at 2.0V for a Logic

‘‘1’’ and 0.8V for a Logic ‘‘0’’.

For Timing Purposes a Port Pin is no Longer Floating when a

100 mV change from Load Voltage Occurs and Begins to Float

when a 100 mV change from the Loaded V /V Level occurs

OH OL

e

g

15 mA.

I /I

OL OH

18

8XC196MD

e

T

F

B

Conversion time, ms

CONV

A TO D CHARACTERISTICS

e

Processor frequency, MHz

8 for 8-bit conversion

10 for 10-bit conversion

e

bits 0–5

OSC

e

The sample and conversion time of the A/D convert-

er in the 8-bit or 10-bit modes is programmed by

loading a byte into the AD TIME Special Function

CONV

Value loaded into AD TIME

Ð

Register. This allows optimizing the A/D operation

for specific applications. The AD TIME register is

Ð

functional for all possible values, but the accuracy of

the A/D converter is only guaranteed for the times

specificed in the operating conditions table.

CONV must be in the range 2 through 31.

The converter is ratiometric, so absolute accuracy is

dependent on the accuracy and stability of V

.

REF

must be close to V since it supplies both the

The value loaded into AD TIME bits 5, 6, 7 deter-

Ð

V

REF CC

mines the sample time, T

ing the following formula:

, and is calculated us-

resistor ladder and the analog portion of the convert-

er and input port pins. There is also an AD TEST

SAM

Ð

SFR that allows for conversion on ANGND and

c

b

2

(T

SAM

F

8

)

V as well as adjusting the zero offset. The abso-

REF

lute error listed is WITHOUT doing any adjustments.

OSC

e

SAM

A/D CONVERTER SPECIFICATION

e

T

F

SAM

Sample time, ms

Processor frequency, MHz

Value loaded into AD TIME

SAM

OSC

The specifications given assume adherence to the

operating conditions section of this data sheet. Test-

e

Ð

bits 5, 6, 7

e

ing is performed with V

5.12V and 16.0 MHz

REF

operating frequency. After a conversion is started,

the device is placed in the IDLE mode until the con-

version is complete.

SAM must be in the range 1 through 7.

The value loaded into AD TIME bits 0–5 deter-

Ð

mines the conversion time, T

using the following formula:

, and is calculated

CONV

c

b

3

(T

F

)

OSC

CONV

e

b

1

CONV

2B

19

8XC196MD

10-BIT MODE A/D OPERATING CONDITIONS

Symbol

Description

Ambient Temperature

Digital Supply Voltage

Analog Supply Voltage

Sample Time

Min

Max

Units

b

a

85

T

A

40

C

§

V

4.50

4.00

1.0

5.50

V

CC

(1)

V

REF

SAM

CONV

OSC

(2)

ms

T

F

(2)

ms

Conversion Time

10.0

8.0

20.0

16.0

Oscillator Frequency

MHz

NOTES:

ANGND and V should nominally be at the same potential.

SS

must be within 0.5V of V

1. V

.

CC

REF

2. The value of AD TIME is selected to meet these specifications.

Ð

10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)

(1)

Parameter

Resolution

Typical

Min

Max

Units*

1024

10

1024

10

Levels

Bits

g

Absolute Error

0

4

LSBs

g

0.25 0.5

Full Scale Error

g

0.25 0.5

Zero Offset Error

Non-Linearity

g

1.0 2.0

g

a

4

2

l

b

0

Differential Non-Linearity

Channel-to-Channel Matching

Repeatability

1

g

0.1

1.0

g

0.25

0

Temperature Coefficients:

Offset

Full Scale

0.009

LSB/C

Differential Non-Linearity

(2, 3)

dB

b

Off Isolation

Feedthrough

60

(2)

dB

b

60

(2)

dB

V

Power Supply Rejection

CC

(4)

Input Series Resistance

Voltage on Analog Input Pin

Sampling Capacitor

750

2K

X

(5, 6)

V

b

a

ANGND

0.5

V

0.5

REF

3

pF

g

DC Input Leakage

1

0

3.0

mA

NOTES:

*An ‘‘LSB’’, as used here has a value of approximately 5 mV. (See Embedded Microcontrollers and Processors Handbook

for A/D glossary of terms).

1. These values are expected for most parts at 25 C but are not tested or guaranteed.

2. DC to 100 KHz.

§

3. Multiplexer Break-Before-Make is guaranteed.

4. Resistance from device pin, through internal MUX, to sample capacitor.

g

5. These values may be exceeded if the pin current is limited to 2 mA.

6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.

7. All conversions performed with processor in IDLE mode.

20

8XC196MD

Units

8-BIT MODE A/D OPERATING CONDITIONS

Symbol

Description

Ambient Temperature

Digital Supply Voltage

Analog Supply Voltage

Sample Time

Min

Max

b

a

85

T

A

40

C

§

V

4.50

4.00

1.0

5.50

V

CC

(1)

V

REF

SAM

CONV

OSC

(2)

ms

T

F

(2)

ms

Conversion Time

7.0

20.0

16.0

Oscillator Frequency

8.0

MHz

NOTES:

ANGND and V should nominally be at the same potential.

SS

must be within 0.5V of V

1. V

.

CC

REF

2. The value of AD TIME is selected to meet these specifications.

Ð

8-BIT MODE A/D CHARACTERISTICS (Over the Above Operating Conditions)

(1)

Parameter

Resolution

Typical

Min

Max

Units*

256

8

256

8

Level

Bits

g

Absolute Error

0

1

LSBs

g

Full Scale Error

0.5

Zero Offset Error

Non-Linearity

g

a

0

1

l

b

Differential Non-Linearity

Channel-to-Channel Matching

Repeatability

1

g

0

1.0

g

0.25

Temperature Coefficients:

Offset

Full Scale

0.003

LSB/C

Differential Non-Linearity

(2, 3)

dB

b

Off Isolation

Feedthrough

60

(2)

dB

b

60

(2)

dB

V

CC

Power Supply Rejection

(4)

Input Series Resistance

Voltage on Analog Input Pin

Sampling Capacitor

750

2K

X

(5, 6)

V

b

a

V

0.5

V

0.5

SS

REF

3

pF

g

DC Input Leakage

1

0

3.0

mA

NOTES:

*An ‘‘LSB’’ as used here, has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook

for A/D glossary of terms).

1. These values are expected for most parts at 25 C but are not tested or guaranteed.

2. DC to 100 KHz.

§

3. Multiplexer Break-Before-Make is guaranteed.

4. Resistance from device pin, through internal MUX, to sample capacitor.

g

5. These values may be exceeded if the pin current is limited to 2 mA.

6. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.

7. All conversions performed with processor in IDLE mode.

21

8XC196MD

EPROM SPECIFICATIONS

OPERATING CONDITIONS DURING PROGRAMMING

Symbol

Description

Ambient Temperature during Programming

Supply Voltage during Programming

Reference Supply Voltage during Programming

Programming Voltage

Min

20

Max

30

Units

T

A

C

§

(1)

V

4.5

5.5

V

CC

(1)

V

4.5

5.5

REF

PP

(2)

V

12.25

6.0

12.75

8.0

(2)

V

EA Pin Voltage

EA

F

Oscillator Frequency during Auto

and Slave Mode Programming

MHz

OSC

T

Oscillator Frequency during

Run-Time Programming

6.0

12.0

MHz

OSC

NOTES:

1. V and V

2. V and V must never exceed the maximum specification, or the device may be damaged.

should nominally be at the same voltage during programming.

REF

CC

PP EA

3. V and ANGND should nominally be at the same potential (0V).

SS

e

4. Load capacitance during Auto and Slave Mode programming

150 pF.

AC EPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE)

Symbol

Parameter

Reset High to First PALE Low

PALE Pulse Width

Min

1100

50

Max

Units

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

T

OSC

SHLL

LLLH

AVLL

LLAX

PLDV

PHDX

DVPL

PLDX

Address Setup Time

0

Address Hold Time

100

PROG Low to Word Dump Valid

Word Dump Data Hold

Data Setup Time

50

0

Data Hold Time

400

50

(1)

PROG Pulse Width

PLPH

PHLL

LHPL

PHPL

PHIL

ILIH

PROG High to Next PALE Low

PALE High to PROG Low

PROG High to Next PROG Low

PROG High to AINC Low

AINC Pulse Width

220

0

240

50

PVER Hold after AINC Low

AINC Low to PROG Low

PROG High to PVER Valid

ILVH

ILPL

170

220

PHVL

NOTE:

1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.

22

8XC196MD

DC EPROM PROGRAMMING CHARACTERISTICS

Symbol

Parameter

Min

Max

Units

I

V

Supply Current (When Programming)

PP

100

mA

PP

NOTE:

Do not apply V until V

PP

damaged.

is stable and within specifications and the oscillator/clock has stabilized or the device may be

CC

SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE

2723231–13

NOTE:

P3.0 must be high (‘‘1’’)

23

8XC196MD

SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT

272323–14

NOTE:

P3.0 must be low (‘‘0’’)

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM

WITH REPEATED PROG PULSE AND AUTO INCREMENT

272323–15

24

8XC196MD

the 8XC196MD. Port 7 is a bidirectional port added

to the 8XC196MD. Port 1 has one additional analog

87C196MD DESIGN

CONSIDERATIONS

or digital input that was connected to V

on the

SS

8XC196MC. Port 1 also has two additional digital in-

puts. See 8XC196MC and 8XC196MD Differences

Section of this data sheet.

When an indirect shift during divide occurs the upper

3 bits of the shift count are not masked completely.

If the shift count register has the value 32 n where

*

e

n

1, 3, 5 or 7. the operand will be shifted 32 times.

This should have resulted in no shift taking place.

DATA SHEET REVISION HISTORY

Document 272323-003 was updated due to changes

required for the lead free initiative. To address the fact

that many of the package prefix variables have changed,

all package prefix variables in the document are now

indicated with an "x".

8XC196MC to 8XC196MD Design

Considerations

8XC196MC and 8XC196MD are pin compatible.

However, there were several pins that were not con-

nected (NC) on the 8XC196MC that are I/O pins on

25


型号：	TN83C196MD
厂家：	INTEL
描述：	INDUSTRIAL MOTOR CONTROL MICROCONTROLLER 工业电机控制用微控制器微控制器和处理器电动机控制电机
文件：	总25页 (文件大小：1063K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TN83C196MD [INTEL]

相关型号：

TN83C196MH

TN83C196TB12

TN83C198

TN83C198-16

TN83C251SA

TN83C251SA16

TN83C251SB

TN83C251SB16

TN83C251SP

TN83C251SP16

TN83C251SQ

TN83C251SQ16