TN87C51RB-20_技术文档

8XC51RA/RB/RC

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Commercial/Express

87C51RA/83C51RA/80C51RA/87C51RB/83C51RB/87C51RC/83C51RC

*See Table 1 for Proliferation Options

Y

High Performance CHMOS EPROM/

ROM/CPU

6 Interrupt Sources

Y

Programmable Serial Channel with:

Ð Framing Error Detection

Ð Automatic Address Recognition

Y

24 MHz Operation

512 Bytes of On-Chip Data RAM

TTL and CMOS Compatible Logic

Levels

Dedicated Hardware Watchdog Timer

(One-Time Enabled with Reset-Out)

Y

64K External Program Memory Space

64K External Data Memory Space

Y

Three 16-Bit Timer/Counters

Programmable Clock Out

MCS 51 Compatible Instruction Set

É

Power Saving Idle and Power Down

Modes

Up/Down Timer/Counter

Three Level Program Lock System

8K/16K/32K On-Chip Program Memory

Y

ONCE (On-Circuit Emulation) Mode

Four-Level Interrupt Priority

Improved Quick Pulse Programming

Algorithm

Extended Temperature Range

b

Y

Boolean Processor

a

40 C to 85 C)

(

§

32 Programmable I/O Lines

MEMORY ORGANIZATION

ROMless

Device

ROM

EPROM

ROM/EPROM

Bytes

RAM

Device

Version

87C51RA

87C51RB

87C51RC

Bytes

80C51RA

83C51RA

83C51RB

83C51RC

8K

16K

32K

512

These devices can address up to 64 Kbytes of external program/data memory.

The Intel 8XC51RA/8XC51RB/8XC51RC is a single-chip control-oriented microcontroller which is fabricated

on Intel’s reliable CHMOS III-E technology. Being a member of the MCS 51 family of controllers, the

8XC51RA/8XC51RB/8XC51RC uses the same powerful instruction set, has the same architecture, and is pin-

for-pin compatible with the existing MCS 51 family of products. The 8XC51RA/8XC51RB/8XC51RC is an

enhanced version of the 8XC52/8XC54/8XC58. The added features make it an even more powerful microcon-

troller for applications that require 512 bytes of on-chip data RAM and dedicated hardware WatchDog Timer

with reset-out features.

Throughout this document 8XC51RX will refer to the 8XC51RA, 8XC51RB and 8XC51RC unless information

applies to a specific device.

For a detailed description of 8XC51RA/RB/RC, refer to the 8XC51RA/RB/RC Hardware Description, order

number 272668.

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

©

COPYRIGHT

INTELCORPORATION, 2004

July 2004

Order Number: 272659-003

8XC51RA/RB/RC

Table 1. Proliferations Options

NOTES:

*1 3.5 MHz to 12 MHz; 5V 20%

*1

Standard

-1

X

-20

X

-24

X

g

-1 3.5 MHz to 16 MHz; 5V 20%

80C51RA

83C51RA

87C51RA

83C51RB

87C51RB

83C51RC

87C51RC

X

g

-20 3.5 MHz to 20 MHz; 5V 20%

X

g

-24 3.5 MHz to 24 MHz; 5V 10%

X

272659–4

Figure 1. 8XC51RX Block Diagram

2

8XC51RA/RB/RC

PROCESS INFORMATION

PACKAGES

Part

Package Type

This device is manufactured on P629.5, a CHMOS

III-E process. Additional process and reliability infor-

mation is available in the Intel Quality System

8XC51RX

40-Pin Plastic DIP (OTP)

44-Pin PLCC (OTP)

44-Pin QFP (OTP)

®

Handbook.

272659–2

PLCC

272659–1

DIP

272336-005

272659–3

*Do not connect reserved pins.

QFP

Figure 2. Pin Connections

3

8XC51RA/RB/RC

LS TTL inputs. Port 2 pins that have 1’s written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 2

pins that are externally pulled low will source current

(I , on the data sheet) because of the internal pull-

IL

ups.

PIN DESCRIPTIONS

V

: Supply voltage.

CC

: Circuit ground.

SS

: Secondary ground (not on DIP). Provided to

SS1

Port 2 emits the high-order address byte during

fetches from external Program Memory and during

accesses to external Data Memory that use 16-bit

reduce ground bounce and improve power supply

by-passing.

@

addresses (MOVX DPTR). In this application it

uses strong internal pullups when emitting 1’s. Dur-

ing accesses to external Data Memory that use 8-bit

NOTE:

This pin is not a substitute for the V pin (pin 22).

SS

(Connection not necessary for proper operation.)

@

addresses (MOVX Ri), Port 2 emits the contents of

the P2 Special Function Register.

Port 0: Port 0 is an 8-bit, open drain, bidirectional

I/O port. As an output port each pin can sink several

LS TTL inputs. Port 0 pins that have 1’s written to

them float, and in that state can be used as high-im-

pedance inputs.

Some Port 2 pins receive the high-order address bits

during EPROM programming and program verifica-

tion.

Port 3: Port 3 is an 8-bit bidirectional I/O port with

internal pullups. The Port 3 output buffers can drive

LS TTL inputs. Port 3 pins that have 1’s written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 3

pins that are externally pulled low will source current

Port 0 is also the multiplexed low-order address and

data bus during accesses to external Program and

Data Memory. In this application it uses strong inter-

nal pullups when emitting 1’s, and can source and

sink several LS TTL inputs.

(I , on the data sheet) because of the pullups.

IL

Port 0 also receives the code bytes during EPROM

programming, and outputs the code bytes during

program verification. External pullup resistors are re-

quired during program verification.

Port 3 also serves the functions of various special

features of the 8051 Family, as listed below:

Port Pin

Alternate Function

RXD (serial input port)

TXD (serial output port)

Port 1: Port 1 is an 8-bit bidirectional I/O port with

internal pullups. The Port 1 output buffers can drive

LS TTL inputs. Port 1 pins that have 1’s written to

them are pulled high by the internal pullups, and in

that state can be used as inputs. As inputs, Port 1

pins that are externally pulled low will source current

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

INT0 (external interrupt 0)

INT1 (external interrupt 1)

T0 (Timer 0 external input)

T1 (Timer 1 external input)

(I , on the data sheet) because of the internal pull-

IL

ups.

WR (external data memory write strobe)

RD (external data memory read strobe)

In addition, Port 1 serves the functions of the follow-

ing special features of the 8XC51RX:

RST: Reset I/O. A high on this pin for two machine

cycles while the oscillator is running resets the de-

vice. The port pins will be driven to their reset condi-

Port Pin

Alternate Function

P1.0

T2 (External Count Input to Timer/

Counter 2), Clock-Out

tion when a minimum V voltage is applied whether

IHI

the oscillator is running or not. An internal pulldown

resistor permits a power-on reset with only a capaci-

tor connected to V . After a WatchDog Timer over-

P1.1

T2EX (Timer/Counter 2 Capture/

Reload Trigger and Direction Control)

CC

flow, this RST pin will drive an output high pulse at a

duration while the in-

minimum V for 96 x T

ternal reset signal is active.

OH2

OSC

Port 1 receives the low-order address bytes during

EPROM programming and verifying.

ALE: Address Latch Enable output pulse for latching

the low byte of the address during accesses to ex-

Port 2: Port 2 is an 8-bit bidirectional I/O port with

internal pullups. The Port 2 output buffers can drive

4

8XC51RA/RB/RC

ternal memory. This pin (ALE/PROG) is also the

program pulse input during EPROM programming for

the 87C51RX.

ured for use as an on-chip oscillator, as shown in

Figure 3. Either a quartz crystal or ceramic resonator

may be used. More detailed information concerning

the use of the on-chip oscillator is available in Appli-

cation Note AP-155, ‘‘Oscillators for Microcontrol-

lers’’, Order No. 230659.

In normal operation ALE is emitted at a constant

rate of (/6 the oscillator frequency, and may be used

for external timing or clocking purposes. Note, how-

ever, that one ALE pulse is skipped during each ac-

cess to external Data Memory.

If desired, ALE operation can be disabled by setting

bit 0 of SFR location 8EH. With this bit set, the pin is

weakly pulled high. However, the ALE disable fea-

ture will be suspended during a MOVX or MOVC in-

struction, idle mode, power down mode and ICE

mode. The ALE disable feature will be terminated by

reset. When the ALE disable feature is suspended or

terminated, the ALE pin will no longer be pulled up

weakly. Setting the ALE-disable bit has no affect if

the microcontroller is in external execution mode.

272659–5

e

g

30 pF 10 pF for Crystals

C1, C2

For Ceramic Resonators, contact resonator manufac-

turer.

Figure 3. Oscillator Connections

To drive the device from an external clock source,

XTAL1 should be driven, while XTAL2 floats, as

shown in Figure 4. There are no requirements on the

duty cycle of the external clock signal, since the in-

put to the internal clocking circuitry is through a di-

vide-by-two flip-flop, but minimum and maximum

high and low times specified on the data sheet must

be observed.

Throughout the remainder of this data sheet, ALE

will refer to the signal coming out of the ALE/PROG

pin, and the pin will be referred to as the ALE/PROG

pin.

PSEN: Program Store Enable is the read strobe to

external Program Memory.

When the 8XC51RX is executing code from external

Program Memory, PSEN is activated twice each

machine cycle, except that two PSEN activations

are skipped during each access to external Data

Memory.

An external oscillator may encounter as much as a

100 pF load at XTAL1 when it starts up. This is due

to interaction between the amplifier and its feedback

capacitance. Once the external signal meets the V

IL

and V specifications the capacitance will not ex-

IH

ceed 20 pF.

EA/V

: External Access enable. EA must be

PP

strapped to VSS in order to enable the device to

fetch code from external Program Memory locations

0000H to 0FFFFH. Note, however, that if any of the

Lock bits are programmed, EA will be internally

latched on reset.

EA should be strapped to V

executions.

for internal program

CC

272659–6

This pin also receives the programming supply volt-

age (V ) during EPROM programming.

PP

Figure 4. External Clock Drive Configuration

XTAL1: Input to the inverting oscillator amplifier.

IDLE MODE

XTAL2: Output from the inverting oscillator amplifi-

er.

The user’s software can invoke the Idle Mode. When

the microcontroller is in this mode, power consump-

tion is reduced. The Special Function Registers and

the onboard RAM retain their values during Idle, but

the processor stops executing instructions. Idle

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respec-

tively, of a inverting amplifier which can be config-

5

8XC51RA/RB/RC

Mode

Table 2. Status of the External Pins during Idle and Power Down

Program

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Memory

Internal

External

Internal

External

Idle

1

0

1

0

Data

Float

Data

Float

Data

Address

Data

Idle

Power Down

Data

Mode will be exited if the chip is reset or if an en-

abled interrupt occurs.

ware upset. WDT is disabled upon power-up. To en-

able the WDT, user must write 1EH and E1H in se-

quence to WDTRST Special Function Register.

Once the WDT is enabled, the 14-bit counter will

increment every machine cycle. While the oscillator

is running, the WDT will be incrementing and cannot

be disabled. The counter is reset by writing 1EH and

E1H in sequence to the WDTRST. If the counter is

not reset before it reaches 3FFFH (16383D), the

chip will be forced into reset sequence and the WDT

will be disabled as upon power-up. During this reset,

the chip will drive an output Reset-High pulse for the

POWER DOWN MODE

To save even more power, a Power Down mode can

be invoked by software. In this mode, the oscillator

is stopped and the instruction that invoked Power

Down is the last instruction executed. The on-chip

RAM and Special Function Registers retain their val-

ues until the Power Down mode is terminated.

duration of 96 x T

OSC

of the Reset-High pulse works out to 6.00 ms

16 MHz.

at the RST pin. The duration

@

On the 8XC51RX either a hardware reset or an ex-

ternal interrupt can cause an exit from Power Down.

Reset redefines all the SFRs but does not change

the on-chip RAM. An external interrupt allows both

the SFRs and on-chip RAM to retain their values.

While in the Idle mode the WDT continues to count.

If the user does not wish to exit the Idle mode with a

reset, then the processor must periodically ‘‘woken

up’’ to service the WDT. In Power Down mode, the

WDT stops counting and holds its current value.

To properly terminate Power Down, the reset or ex-

ternal interrupt should not be executed before V is

CC

restored to its normal operating level, and must be

held active long enough for the oscillator to restart

and stabilize (normally less than 10 ms).

DESIGN CONSIDERATION

With an external interrupt, INT0 and INT1 must be

enabled and configured as level-sensitive. Holding

the pin low restarts the oscillator but bringing the pin

back high completes the exit. Once the interrupt is

serviced, the next instruction to be executed after

RETI will be the one following the instruction that put

the device into Power Down.

The window on the D87C51RX must be covered

#

by an opaque label. Otherwise, the DC and AC

characteristics may not be met, and the device

may be functionally impaired.

When the idle mode is terminated by a hardware

#

reset, the device normally resumes program exe-

cution, from where it left off, up to two machine

cycles before the internal reset algorithm takes

control. On-chip hardware inhibits access to inter-

nal RAM in this event, but access to the port pins

is not inhibited. To eliminate the possibility of an

unexpected write when Idle is terminated by re-

set, the instruction following the one that invokes

Idle should not be one that writes to a port pin or

to external memory.

DEDICATED HARDWARE WATCHDOG

TIMER (One-Time Enabled with

Reset-Out)

The 8XC51RX contains a dedicated WatchDog Tim-

er (WDT) to allow recovery from software or hard-

NOTE:

For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors

Handbook Volume I, (Order No. 270645) and Application Note AP-252 (Embedded Applications Handbook, Order No.

270648), ‘‘Designing with the 80C51BH.’’

6

8XC51RA/RB/RC

whose operating requirements exceed commercial

standards.

ONCE MODE

The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates

testing and debugging of systems using the

8XC51RX without the 8XC51RX having to be re-

moved from the circuit. The ONCE Mode is invoked

by:

The EXPRESS program includes the commercial

standard temperature range with burn-in and an ex-

tended temperature range with or without burn-in.

With the commercial standard temperature range,

operational characteristics are guaranteed over the

1) Pull ALE low while the device is in reset and

PSEN is high;

a

temperature range of 0 C to

70 C. With the ex-

°

2) Hold ALE low as RST is deactivated.

tended temperature range option, operational char-

acteristics are guaranteed over the range of 40 C

-

°

While the device is in ONCE Mode, the Port 0 pins

float and the other port pins and ALE and PSEN are

weakly pulled high. The oscillator circuit remains ac-

tive. While the 8XC51RX is in this mode, an emulator

or test CPU can be used to drive the circuit. Normal

operation is restored when a normal reset is applied.

+

to 85 C.

°

The optional burn-in is dynamic for a minimum time

=

±

of 168 hours at 125 C with V

6.9V 0.25V,

°

CC

following guidelines in MIL-STD-883, Method 1015.

For the extended temperature range option, this

data sheet specifies the parameters which deviate

from their commercial temperature range limits.

8XC51RX EXPRESS

The Intel EXPRESS system offers enhancements to

the operational specifications of the MCS 51 family

of microcontrollers. These EXPRESS products are

designed to meet the needs of those applications

7

8XC51RA/RB/RC

NOTICE: This data sheet contains information on

products in the sampling and initial production phases

of development. The specifications are subject to

change without notice. Verify with your local Intel

Sales office that you have the latest data sheet be-

fore finalizing a design.

ABSOLUTE MAXIMUM RATINGS*

-

Ambient Temperature Under Bias........ 40° C to +85°C

+

Storage Temperature ....................-65 C to

150°C

°

+

Voltage on EA/V

Pin to V ................0V to 13.0V

PP

SS

+

0.5V to 6.5V

Voltage on Any Other Pin to V

SS......-

Per I/O Pin..................................................15 mA

*WARNING: Stressing the device beyond the"Absolute

I

OL

Maximum Ratings " may cause permanent damage.

Power Dissipation.................................................1.5W

These are stress ratings only . Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

(based on PACKAGE heat transfer limitations, not

device power consumption)

tended exposure beyond the "Operating Conditions "

may affect devicereliability .

OPERATING CONDITIONS

Symbol

Description

Min

Max

Units

Ambient Temperature Under Bias

Commercial

Express

T

A

0

40

+70

+85

C

°

-

Supply Voltage

All Others

8XC51RX-24

V

CC

4.0

4.5

6.0

5.5

V

0scillator Frequency

8XC51RX

8XC51RX-1

8XC51RX-20

8XC51RX-24

f

OSC

3.5

12

16

20

24

MHz

DC CHARACTERISTICS (Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated.

Typ

(Note 4)

Symbol

Parameter

Min

Max

Unit

Test Conditions

-

V

IL

Input Low Voltage

0.5

0

0.2 V -0.1

V

CC

-

0.3

CC

V

IL1

Input Low Voltage EA

0.2 V

V

Input High Voltage

(Except XTAL1, RST)

Input High Voltage

(XTAL1, RST)

Output Low Voltage (Note 5)

(Ports 1, 2 and 3)

0.2 V

CC+

0.9

0.5

IH

CC+

V

0.7 V

V

CC+

0.5

IH1

OL

CC

V

=

0.3

I

100 μA (Note 1)

OL

=

0.45

1.0

V

I

1.6

3.5

200

mA (Note 1)

μA (Note 1)

mA (Note 1)

OL

I

OL

V

Output Low Voltage (Note 5)

0.3

I

OL

OL1

(Port 0, ALE, PSEN )

=

0.45

1.0

V

I

3.2

7.0

OL

IOL

I

-

=

0.3

-10

-30

-60

μA

Output High Voltage

V

OH

CC

OH

)

(Ports 1,2 and 3,ALE,PSEN

-

=

0.7

I

OH

CC

-1.5

=

I

OH

8

8XC51RA/RB/RC

Test Conditions

DC CHARACTERISTICS (Over Operating Conditions) (Continued)

All parameter values apply to all devices unless otherwise indicated.

Typ

(Note 4)

Symbol

Parameter

Min

Max

Unit

b

e b

V

Output High Voltage

(Port 0 in External Bus Mode)

V

0.3

0.7

1.5

V

I

200 mA

3.2 mA

7.0 mA

800 mA

300 mA

80 mA

OH1

OH2

CC

OH

V

Output High Voltage

(RST)

0.5 V

CC

0.75 V

CC

0.9 V

I

Logical 0 Input Current

(Ports 1, 2 and 3)

IL

b

g

e

50

10

mA

V

0.45V

V or V

IL

IN

I

Input leakage Current (Port 0)

LI

IH

Logical 1 to 0 Transition Current

(Ports 1, 2 and 3)

Commercial

TL

b

e

675

775

mA

V

2V

IN

Express

RRST

CIO

RST Pulldown Resistor

Pin Capacitance

40

225

KX

@

1 MHz, 25 C

10

15

pF

§

I

Power Supply Current:

Active Mode

(Note 3)

CC

at 12 MHz (Figure 5)

at 16 MHz

at 20 MHz

at 24 MHz

Idle Mode

30

38

47

56

mA

at 12 MHz (Figure 5)

at 16 MHz

at 20 MHz

at 24 MHz

Power Down Mode

5

7.5

9.5

11.5

13.5

75

mA

NOTES:

1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V s of ALE and

OL

Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins

change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed

0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Triggers, or CMOS-level input logic.

2. Capacitive loading on Ports 0 and 2 cause the V

address lines are stabilizing.

3. See Figures 6–9 for test conditions. Minimum V

on ALE and PSEN to drop below the 0.9 V specification when the

CC

OH

for Power Down is 2V.

CC

4. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature

and 5V.

5. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

OL

Maximum I per 8-bit portÐ

10mA

OL

Port 0:

Ports 1, 2 and 3:

Maximum total I for all output pins:

26 mA

15 mA

71 mA

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater

OL OL

than the listed test conditions.

9

8XC51RA/RB/RC

272659–7

I

Max at other frequencies is given by:

272659–8

CC

Active Mode

I

All other pins disconnected

e

5 ns

e

c

a

Max

2.2

0.5

Freq

3.1

1.5

CC

Idle Mode

Max

e

TCLCH

TCHCL

e

c

I

CC

Figure 6. I Test Condition, Active

CC

Mode

Where Freq is in MHz, I

Max is given in mA.

CC

Figure 5. I vs Frequency

CC

272659–9

272659–10

All other pins disconnected

e

All other pins disconnected

e

TCLCH

TCHCL

5 ns

Figure 8. I Test Condition, Power Down Mode

CC

Figure 7. I Test Condition Idle Mode

CC

e

V

2.0V to 6.0V

CC

272659–11

e

5 ns

Figure 9. Clock Signal Waveform for I Tests in Active and Idle Modes. TCLCH

CC

TCHCL

10

8XC51RA/RB/RC

L: Logic level LOW, or ALE

P: PSEN

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has 5 characters. The first char-

acter is always a ‘T’ (stands for time). The other

characters, depending on their positions, stand for

the name of a signal or the logical status of that

signal. The following is a list of all the characters and

what they stand for.

Q: Output Data

R: RD signal

T: Time

V: Valid

W: WR signal

A: Address

X: No longer a valid logic level

Z: Float

C: Clock

D: Input Data

For example,

H: Logic level HIGH

I: Instruction (program memory contents)

e

TAVLL

TLLPL

Time from Address Valid to ALE Low

Time from ALE Low to PSEN Low

AC CHARACTERISTICS (Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and

e

80 pF)

PSEN

100 pF, Load Capacitance for All Other Outputs

EXTERNAL MEMORY CHARACTERISTICS

All parameter values apply to all devices unless otherwise indicated. In this table, 8XC51RX refers to

8XC51RX and 8XC51RX-1. 8XC51RX-24 refers to 8XC51RX-20 and 8XC51RX-24.

12 MHz

20 MHz

24 MHz

Oscillator Oscillator Oscillator

Variable

Oscillator

Symbol

Description

Units

Min Max Min Max Min Max

Min

Max

1/TCLCL Oscillator Frequency

8XC51RX

8XC51RX-1

3.5

12

16

20

24

MHz

8XC51RX-20

8XC51RX-24

b

2 TCLCL 40

TLHLL

TAVLL

ALE Pulse Width

127

43

60

10

43

12

ns

b

TCLCL 40

Address Valid to

ALE Low

b

TCLCL 30

TLLAX

TLLIV

Address Hold After

ALE Low

53

20

12

ns

ALE Low to Valid

Instruction In

8XC51RX

b

234

4 TCLCL 100

b

4 TCLCL 75

ns

8XC51RX-24

125

91

b

TCLCL 30

TLLPL

ALE Low to PSEN

Low

53

20

12

80

ns

b

3 TCLCL 45

TPLPH

TPLIV

PSEN Pulse Width

205

105

ns

PSEN Low to Valid

Instruction In

8XC51RX

b

145

3 TCLCL 105

b

3 TCLCL 90

ns

8XC51RX-24

60

35

TPXIX

Input Instruction

Hold After PSEN

0

ns

11

8XC51RA/RB/RC

EXTERNAL MEMORY CHARACTERISTICS (Continued)

All parameter values apply to all devices unless otherwise indicated.

12 MHz

20 MHz

24 MHz

Variable

Oscillator Oscillator Oscillator

Oscillator

Symbol

Description

Units

Min Max Min Max Min Max

Min

Max

TPXIZ

Input Instruction Float After

PSEN

b

8XC51RX

59

TCLCL 25

ns

b

TCLCL 20

8XC51RX-24

30

21

b

5 TCLCL 105

TAVIV

Address to Valid Instruction

In

312

10

145

103

ns

TPLAZ

TRLRH

PSEN Low to Address Float

RD Pulse Width

10

ns

b

6 TCLCL 100

400

200

150

b

6 TCLCL 100

TWLWH WR Pulse Width

TRLDV

RD Low to Valid Data In

b

8XC51RX

252

5 TCLCL 165

ns

b

5 TCLCL 95

8XC51RX-24

155

40

113

23

TRHDX

TRHDZ

TLLDV

Data Hold After RD

Data Float After RD

0

ns

b

2 TCLCL 60

107

517

ALE Low to Valid Data In

8XC51RX

b

8 TCLCL 150

ns

b

8 TCLCL 90

8XC51RX-24

310

243

TAVDV

Address to Valid Data In

8XC51RX

b

585

9 TCLCL 165

ns

b

9 TCLCL 90

8XC51RX-24

360

285

175

b

3 TCLCL 50

a

3 TCLCL 50

TLLWL

TAVWL

ALE Low to RD or WR Low

200 300 100 200

75

77

ns

Address Valid to WR Low

8XC51RX

b

203

4 TCLCL 130

ns

b

4 TCLCL 90

8XC51RX-24

110

TQVWX Data Valid before WR

8XC51RX

b

33

TCLCL 50

ns

b

TCLCL 35

b

TCLCL 30

8XC51RX-20

15

8XC51RX-24

12

TWHQX Data Hold after WR

8XC51RX

b

33

TCLCL 50

ns

b

TCLCL 40

b

TCLCL 30

8XC51RX-20

10

8XC51RX-24

7

TQVWH Data Valid to WR High

8XC51RX

b

433

7 TCLCL 150

ns

b

7 TCLCL 70

8XC51RX-24

280

222

TRLAZ

RD Low to Address Float

0

ns

TWHLH RD or WR High to ALE High

8XC51RX

b

a

TCLCL 40

43

123

10

90

TCLCL 40

ns

b

TCLCL 30

a

TCLCL 30

8XC51RX-24

12

71

12

8XC51RA/RB/RC

EXTERNAL PROGRAM MEMORY READ CYCLE

272659–12

EXTERNAL DATA MEMORY READ CYCLE

272659–13

EXTERNAL DATA MEMORY WRITE CYCLE

272659–14

13

8XC51RA/RB/RC

SERIAL PORT TIMING - SHIFT REGISTER MODE

e

Test Conditions: Over Operating Conditions; Load Capacitance 80 pF

12 MHz

20 MHz

24 MHz

Variable

Oscillator Oscillator

Oscillator

Symbol

Parameter

Units

Min Max Min Max Min Max

Min

12 TCLCL

Max

TXLXL

Serial Port Clock

Cycle Time

1

0.600

0.500

ms

b

284 10 TCLCL 133

TQVXH Output Data

Setup to Clock

Rising Edge

700

367

ns

TXHQX Output Data

Hold after Clock

Rising Edge

b

8XC51RX

50

0

2 TCLCL 117

ns

b

2 TCLCL 50

8XC51RX-24

50

0

34

0

TXHDX Input Data Hold

After Clock

Rising Edge

0

ns

b

10 TCLCL 133

TXHDV Clock Rising

Edge to Input

Data Valid

700

367

284

ns

SHIFT REGISTER MODE TIMING WAVEFORMS

272659–15

14

8XC51RA/RB/RC

EXTERNAL CLOCK DRIVE

Symbol

Parameter

Min

Max

Units

1/TCLCL

Oscillator Frequency

8XC51RX

8XC51RX-1

3.5

12

16

20

24

MHz

8XC51RX-20

8XC51RX-24

TCHCX

TCLCX

TCLCH

High Time

Low Time

0.35 T

0.65 T

ns

OSC

Rise Time

8XC51RX

8XC51RX-24

20

10

ns

TCHCL

Fall Time20

8XC51RX

8XC51RX-24

ns

20

10

EXTERNAL CLOCK DRIVE WAVEFORM

272659–16

AC TESTING INPUT, OUTPUT WAVEFORMS

FLOAT WAVEFORMS

272659–18

port pin is no longer floating when

100 mV change from load voltage occurs, and begins to float

when a 100 mV change from the loaded V /V level occurs.

272659–17

For timing purposes

a

b

and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V

AC Inputs during testing are driven at V

0.5V for a Logic ‘‘1’’

CC

IH

OH OL

min for a Logic ‘‘1’’ and V max for a Logic ‘‘0’’.

IL

e

g

20 mA.

I

/I

OL OH

15

8XC51RA/RB/RC

PROGRAMMING THE EPROM

DEFINITION OF TERMS

The part must be running with a 4 MHz to 6 MHz

oscillator. The address of an EPROM location to be

programmed is applied to address lines while the

code byte to be programmed in that location is ap-

plied to data lines. Control and program signals must

be held at the levels indicated in Table 4. Normally

ADDRESS LINES: P1.0–P1.7, P2.0–P2.5 respec-

tively for A0–A13.

DATA LINES: P0.0–P0.7 for D0–D7.

CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,

P3.6, P3.7

EA/V is held at logic high until just before ALE/

PP

PROG is to be pulsed. The EA/V is raised to V

,

PP

is re-

PP

ALE/PROG is pulsed low and then EA/V

PROGRAM SIGNALS: ALE/PROG, EA/V

PP

turned to a high (also refer to timing diagrams).

NOTES:

Exceeding the V maximum for any amount of

#

PP

time could damage the device permanently. The

V source must be well regulated and free of

PP

glitches.

Table 4. EPROM Programming Modes

ALE/

EA/

Mode

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

PROG

V

PP

Program Code Data

Verify Code Data

H

L

ß

H

12.75V

H

L

H

L

H

L

H

L

H

Program Encryption

Array Address 0–3FH

ß

12.75V

H

Program Lock

Bits

Bit 1

Bit 2

Bit 3

H

L

ß

H

12.75V

H

L

H

L

H

L

H

L

H

L

H

L

Read Signature Byte

L

16

8XC51RA/RB/RC

272659–19

*See Table 4 for proper input on these pins

Figure 10. Programming the EPROM

Repeat 1 through 5 changing the address and data

for the entire array or until the end of the object file is

reached.

PROGRAMMING ALGORITHM

Refer to Table 4 and Figures 10 and 11 for address,

data, and control signals set up. To program the

87C51RX the following sequence must be exer-

cised.

PROGRAM VERIFY

1. Input the valid address on the address lines.

Program verify may be done after each byte or block

of bytes is programmed. In either case a complete

verify of the programmed array will ensure reliable

programming of the 87C51RX.

2. Input the appropriate data byte on the data

lines.

3. Activate the correct combination of control sig-

nals.

The lock bits cannot be directly verified. Verification

of the lock bits is done by observing that their fea-

tures are enabled.

g

to 12.75V 0.25V.

4. Raise EA/V from V

PP

CC

5. Pulse ALE/PROG 5 times for the EPROM ar-

ray, and 25 times for the encryption table and

the lock bits.

272659–20

Figure 11. Programming Signal’s Waveforms

17

8XC51RA/RB/RC

If any program lock bits were programmed, erasing

the EPROM will not erase the program lock bits and

programming of the EPROM is disabled.

ROM and EPROM Lock System

The program lock system, when programmed, pro-

tects the onboard program against software piracy.

The 83C51RX has a one-level program lock system

and a 64-byte encryption table. See line 2 of Table

5. If program protection is desired. the user submits

the encryption table with their code. and both the

lock-bit and encryption array are programmed by the

factory. The encryption array is not available without

the lock bit. For the lock bit to be programmed, the

user must submit an encryption table.

Reading the Signature Bytes

The 8XC51RX has 3 signature bytes in locations

30H, 31H, and 60H. To read these bytes follow the

procedure for EPROM verify, but activate the control

lines provided in Table 4 for Read Signature Byte.

Location

30H

Device

All

Contents

89H

The 87C51RX has a 3-level program lock system

and a 64-byte encryption array. Since this is an

EPROM device, all locations are user-programma-

ble. See Table 5.

31H

All

58H

60H

87C51RC

87C51RB

87C51RA

83C51RC

83C51RB

83C51RA

C2H

C1H

C0H

Encryption Array

42H/C2H

41H/C1H

40H/C0H

Within the EPROM array are 64 bytes of Encryption

Array that are initially unprogrammed (all 1’s). Every

time that a byte is addressed during a verify, 6 ad-

dress lines are used to select a byte of the Encryp-

tion Array. This byte is then exclusive-NOR’ed

(XNOR) with the code byte, creating an Encryption

Verify byte. The algorithm, with the array in the un-

programmed state (all 1’s), will return the code in its

original, unmodified form. For programming the En-

cryption Array, refer to Table 4 (Programming the

EPROM).

Erasure Characteristics

(Windowed Packages Only)

Erasure of the EPROM begins to occur when the

chip is exposed to light with wavelength shorter than

approximately 4,000 Angstroms. Since sunlight and

fluorescent lighting have wavelengths in this range,

exposure to these light sources over an extended

time (about 1 week in sunlight, or 3 years in room-

level fluorescent lighting) could cause inadvertent

erasure. If an application subjects the device to this

type of exposure, it is suggested that an opaque la-

bel be placed over the window.

When using the encryption array, one important fac-

tor needs to be considered. If a code byte has the

value 0FFH, verifying the byte will produce the en-

l

cryption byte value. If a large block ( 64 bytes) of

code is left unprogrammed, a verification routine will

display the contents of the encryption array. For this

reason all unused code bytes should be pro-

grammed with some value other than 0FFH, and not

all of them the same value. This will ensure maxi-

mum program protection.

The recommended erasure procedure is exposure

to ultraviolet light (at 2537 Angstroms) to an integrat-

2

ed dose of at least 15 W-sec/cm . Exposing the

2

EPROM to an ultraviolet lamp of 12,000 mW/cm

Program Lock Bits

rating for 30 minutes, at a distance of about 1 inch,

should be sufficient.

The 87C51RX has 3 programmable lock bits that

when programmed according to Table 5 will provide

different levels of protection for the on-chip code

and data.

Erasure leaves all the EPROM Cells in a 1’s state.

18

8XC51RA/RB/RC

Table 5. Program Lock Bits and the Features

Protection Type

Program Lock Bits

LB1

LB2

LB3

1

2

U

No Program Lock features enabled. (Code verify will still be encrypted by the

Encryption Array if programmed.)

P

U

MOVC instructions executed from external program memory are disabled from

fetching code bytes from internal memory, EA is sampled and latched on

Reset, and further programming of the EPROM is disabled.

3

4

P

U

P

Same as 2, also verify is disabled.

Same as 3, also external execution is disabled.

NOTE:

Any other combination of the lock bits is not defined.

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

e

0V)

SS

g

5V 20%; V

(T

A

21 C to 27 C; V

§

Symbol

§

CC

Parameter

Min

Max

13.0

75

Units

V

Programming Supply Voltage

Programming Supply Current

Oscillator Frequency

12.5

PP

I

mA

PP

1/TCLCL

TAVGL

TGHAX

TDVGL

TGHDX

TEHSH

TSHGL

TGHSL

TGLGH

TAVQV

TELQV

TEHQZ

TGHGL

4

6

MHz

Address Setup to PROG Low

Address Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

48TCLCL

10

(Enable) High to V

PP

V

Setup to PROG Low

ms

PP

Hold after PROG

10

PROG Width

90

110

Address to Data Valid

ENABLE Low to Data Valid

Data Float after ENABLE

PROG High to PROG Low

48TCLCL

0

10

ms

19

8XC51RA/RB/RC

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

272659–21

*5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.

Thermal Impedance

The following differences exist between datasheet

(272659-002) and the version

(272659-001).

All thermal impedance data is approximate for static

air conditions at 1W of power dissipation. Values will

change depending on operating conditions and ap-

plications. See the Intel Packaging Handbook (Order

Number 240800) for a description of Intel’s thermal

impedance test methodology.

1. ADVANCE INFORMATION datasheet replaces

PRODUCT PREVIEW datasheet.

-

2. I

(Commercial) changed from

675 µA.

650 µA to

TL

-

3. I

(Express) changed from

775 µA.

4. 8XC51RX-24, V

750 µA to

TL

DATA SHEET REVISION HISTORY

-

±

changed from 5V

20% to

Data sheets are changed as new device information

becomes available. Verify with your local Intel sales

office that you have the latest version before finaliz-

ing a design or ordering devices.

CC

±

5V 10%.

5. Remove all CERDIP package types (prefix D, TD,

LD).

The following differences exist between this data-

sheet (272659-003) and the previous version

(272659-002).

1. Product prefix variables are now indicated with an x.

INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080

INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000

INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511


型号：	TN87C51RB-20
厂家：	INTEL
描述：	Microcontroller, 8-Bit, OTPROM, 8051 CPU, 20MHz, CMOS, PQCC44, PLASTIC, LCC-44 可编程只读存储器时钟微控制器外围集成电路装置
文件：	总20页 (文件大小：1665K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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