TN87C54-20 [INTEL]
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM; CHMOS单片8位与16 KB的用户可编程EPROM微控制器
| 型号： | TN87C54-20 |
| 厂家： | 
INTEL |
| 描述： | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM |
| 文件： | 总20页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
87C54/87C54-20
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 16 KBYTES USER PROGRAMMABLE EPROM
Automotive
Y
Y
Extended Automotive Temperature
Programmable Serial Channel with:
Ð Framing Error Detection
Ð Automatic Address Recognition
b
a
Range ( 40 C to 125 C Ambient)
§
§
Y
Y
Y
High Performance CHMOS EPROM
Three 16-Bit Timer/Counters
Y
TTL and CMOS Compatible Logic
Levels
One-to-Three Level Program/Data Lock
System
Y
Y
Y
Y
64K External Program Memory Space
64K External Data Memory Space
Y
Y
Y
Y
Y
Y
16K On-Chip EPROM/ROM
256 Bytes of On-Chip Data RAM
Quick Pulse Programming Algorithm
Boolean Processor
MCS -51 Compatible Instruction Set
É
Power Saving Idle and Power Down
Modes
Y
Y
Y
ONCE (On-Circuit Emulation) Mode
RFI Reduction Mode
32 Programmable I/O Lines
7 Interrupt Sources
Available in 12 MHz, 16 MHz and
20 MHz Versions
Y
Available in PLCC and DIP Packages
Ý
(See Packaging Spec., Order 231369)
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 16 Kbytes of the program memory can reside in the on-chip EPROM. The device
can also address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C54 is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable
CHMOS EPROM technology. Being a member of the MCS-51 family, the 87C54 uses the same powerful
instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS-51 family of
products. The 87C54 is an enhanced version of the 87C51FB. Its added features of 16 Kbytes of program
memory make it an even more powerful microcontroller for applications that require High Speed I/O and
up/down counting capabilities such as brake and traction control.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
February 1994
Order Number: 270849-004
AUTOMOTIVE 87C54/87C54-20
270849–1
Figure 1. 87C54 Block Diagram
2
AUTOMOTIVE 87C54/87C54-20
characteristics are guaranteed over the temperature
87C54 PRODUCT OPTIONS
b
a
range of 40 C to 85 C ambient. For the automo-
tive temperature range option, operational charac-
§
§
Intel’s extended and automotive temperature range
products are designed to meet the needs of those
applications whose operating requirements exceed
commercial standards.
teristics are guaranteed over the temperature range
a
b
of 40 C to 125 C ambient. The automotive, ex-
§
§
tended, and commercial temperature versions of the
MCS-51 product families are available with or with-
out burn-in options.
With the commercial standard temperature range,
operational characteristics are guaranteed over the
a
temperature range of 0 C to 70 C ambient. With
the extended temperature range option, operational
As shown in Figure 2 temperature, burn-in, and
package options are identified by a one- or two-letter
prefix to the part number.
§
§
270849–4
*Example:
AN87C54 indicates an automotive temperature range version of the 87C54 in a PLCC package with 16 Kbyte EPROM program memory.
Figure 2. Package Options
Table 1. Temperature Options
Operating
Temperature
Classification
Temperature
Designation
Burn-In
Options
Temperature
C Ambient
§
b
b
a
Extended
T
L
40 to 85
Standard
Extended
a
40 to 85
b
b
a
Automotive
A
B
40 to 125
Standard
Extended
a
40 to 125
3
AUTOMOTIVE 87C54/87C54-20
PACKAGES
Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1’s written to them
float, and in that state can be used as high-imped-
ance inputs.
Part
Prefix
Package Type
87C54
87C54
AP
AN
40-Pin Plastic DIP
44-Pin PLCC
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong inter-
nal pullups when emitting1’s, and can source and
sink several LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are re-
quired during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(I , on the data sheet) because of the internal pull-
IL
ups.
270849–2
In addition, Port 1 serves the functions of the follow-
ing special features of the 87C54:
DIP (PDIP)
Port Pin
Alternate Function
P1.0
T2 (External Count Input to Timer/
Counter 2), Clock-Out
P1.1
T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
P1.2
P1.3
ECI (External Count Input to the PCA)
CEX0 (External I/O for Compare/
Capture Module 0)
P1.4
P1.5
P1.6
P1.7
CEX1 (External I/O for Compare/
Capture Module 1)
CEX2 (External I/O for Compare/
Capture Module 2)
270849–3
CEX3 (External I/O for Compare/
Capture Module 3)
*Do not connect reserved pins.
PAD (PLCC)
Figure 3. Pin Connections
CEX4 (External I/O for Compare/
Capture Module 4)
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
PIN DESCRIPTIONS
V
V
V
: Supply voltage.
CC
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
: Circuit ground.
SS
: Secondary ground (in PLCC only). Provided to
SS1
reduce ground bounce and improve power supply
by-passing.
(I , on the data sheet) because of the internal pull-
IL
ups.
NOTE:
This pin is not a substitute for the V pin (pin 22).
SS
4
AUTOMOTIVE 87C54/87C54-20
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
In normal operation ALE is emitted at a constant
rate of (/6 the oscillator frequency, and may be used
for external timing or clocking purposes. Note, how-
ever, that one ALE pulse is skipped during each ac-
cess to external Data Memory.
@
addresses (MOVX DPTR). In this application it
uses strong internal pullups when emitting 1’s. Dur-
ing accesses to external Data Memory that use 8-bit
@
addresses (MOVX Ri), Port 2 emits the contents of
the P2 Special Function Register.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verifica-
tion.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
When the 87C54 is executing code from external
Program Memory, PSEN is activated twice each
machine cycle, except that two PSEN activations
are skipped during each access to external Data
Memory.
(I , on the data sheet) because of the pullups.
IL
EA/V
: External Access enable. EA must be
PP
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFFH. Note, however, that if any of the
Lock bits are programmed, EA will be internally
latched on reset.
Port Pin
Alternate Function
RXD (serial input port)
TXD (serial output port)
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
EA should be strapped to V
executions.
for internal program
INT0 (external interrupt 0)
INT1 (external interrupt 1)
CC
T0 (Timer 0 external input)
T1 (Timer 1 external input)
This pin also receives the programming supply volt-
age (V ) during EPROM programming.
PP
WR (external data memory write strobe)
RD (external data memory read strobe)
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
In addition, some Port 3 pins receive the high-order
address bits and act as control signals during
EPROM programming and programming verification.
OSCILLATOR CHARACTERISTICS
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the de-
vice. The port pins will be driven to their reset condi-
XTAL1 and XTAL2 are the input and output, respec-
tively, of a inverting amplifier which can be config-
ured for use as an on-chip oscillator, as shown in
Figure 4. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155, ‘‘Oscillators for Microcontrol-
lers.’’
tion when a minimum V
is applied, whether the
IH1
oscillator is running or not. An internal pulldown re-
sistor permits a power-on reset with only a capacitor
connected to V
.
CC
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to ex-
ternal memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C54.
5
AUTOMOTIVE 87C54/87C54-20
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated.
270849–5
e
For Ceramic Resonators, contact resonator manufacturer.
g
30 pF 10 pF for Crystals
C1, C2
On the 87C54 either a hardware reset or an external
interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the on-
chip RAM. An external interrupt allows both the
SFRs and on-chip RAM to retain their values.
Figure 4. Oscillator Connections
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 5. There are no requirements on the
duty cycle of the external clock signal, since the in-
put to the internal clocking circuitry is through a di-
vide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
To properly terminate Power down the reset or ex-
ternal interrupt should not be executed before V is
CC
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
With an external interrupt, INT0 or INT1 must be en-
abled and configured as level-sensitive. Holding the
pin low restarts the oscillator but bringing the pin
back high completes the exit. (The oscillator must be
allowed time to stabilize after start up, before this pin
is released high.) Once the interrupt is serviced, the
next instruction to be executed after RETI will be the
one following the instruction that put the device into
Power Down.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the V
IL
and V specifications the capacitance will not ex-
IH
ceed 20 pF.
DESIGN CONSIDERATION
When the idle mode is terminated by a hardware
reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles
before the internal reset algorithm takes control. On-
chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To
eliminate the possibility of an unexpected write when
Idle is terminated by reset, the instruction following
the one that invokes Idle should not be one that
writes to a port pin or to external memory.
270849–6
Figure 5. External Clock Drive Configuration
IDLE MODE
The user’s software can invoke the Idle Mode. When
the microcontroller is in this mode, power consump-
tion is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs.
6
AUTOMOTIVE 87C54/87C54-20
ONCE MODE
RFI REDUCTION MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the 87C54
without the 87C54 having to be removed from the
circuit. The ONCE Mode is invoked by:
The RFI reduction feature can be used only if exter-
nal program memory is not required since this mode
disables the ALE pin during instruction code fetches.
By writing a logical one to the LSB of the Auxiliary
Register (address 08EH), the ALE is disabled for in-
struction code fetches and the output is weakly held
high. When a logical zero is written, the ALE pin is
enabled allowing it to generate the Address Latch
Enable signal. This bit is cleared by reset. Once dis-
abled, ALE remains disabled until it is reset by soft-
ware or until a hardware reset occurs.
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains ac-
tive. While the 87C54 is in this mode, an emulator or
test CPU can be used to drive the circuit. Normal
operation is restored when a normal reset is applied.
Table 2. Status of the External Pins during Idle and Power Down
Program
Memory
Mode
Idle
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Internal
External
Internal
External
1
1
0
0
1
1
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Idle
Power Down
Power Down
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Applications Handbook, and Applica-
tion Note AP-252, ‘‘Designing with the 80C51BH.’’
7
AUTOMOTIVE 87C54/87C54-20
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet be-
fore finalizing a design.
b
a
Ambient Temperature Under Bias 40 C to 125 C
§
§
b
a
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C
§
§
Voltage on EA/V Pin to V ÀÀÀÀÀÀÀ0V to 13.0V
a
PP
SS
b a
ÀÀ 0.5V to 6.5V
Voltage on Any Other Pin to V
SS
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
I
Per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA
OL
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
(Based on package heat transfer limitations, not
device power consumption)
a
Typical Junction Temperature ÀÀÀÀÀÀÀÀÀÀÀÀ 135 C
§
a
(Based on ambient temperature at 125 C)
§
Typical Thermal Resistance Junction-to-Ambient
(i ):
JA
PDIP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ45 C/W
§
PLCC ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46 C/W
§
ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION
e b
a
40 C to 125 C; V
e
e
SS
g
5V 20%; V
DC CHARACTERISTICS: (T
0V)
§
§
A
CC
Typ
(Note 4)
Symbol
Parameter
Input Low Voltage
Min
Max
Unit
Test Conditions
b
b
V
V
V
0.5
0.2 V
0.1
0.3
V
V
V
IL
CC
b
Input Low Voltage EA
0
0.2 V
IL1
IH
CC
a
a
Input High Voltage
(Except XTAL1, RST, EA)
0.2 V
0.9
V
0.5
CC
CC
a
CC
a
V
V
Input High Voltage (XTAL1, RST)
0.7 V
0.1V
V
0.5
V
V
IH1
CC
e
e
e
e
e
e
Output Low Voltage (Note 5)
(Ports 1, 2 and 3)
0.3
I
I
I
I
I
I
I
I
I
I
I
I
100 mA (Note 1)
1.6 mA (Note 1)
3.5 mA (Note 1, 4)
200 mA (Note 1)
3.2 mA (Note 1)
7.0 mA (Note 1, 4)
OL
OL
OL
OL
OL
OL
OL
OH
OH
OH
OH
OH
OH
0.45
1.0
V
V
V
V
V
Output Low Voltage (Note 5)
(Port 0, ALE, PSEN)
0.3
V
OL1
0.45
1.0
V
V
b
e b
e b
e b
e b
e b
e b
Output High Voltage
(Ports 1, 2 and 3)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
0.3
V
10 mA
OH
b
b
b
b
b
0.7
1.5
0.5
0.7
1.5
V
30 mA
V
60 mA
Output High Voltage
(Port 0 in External Bus Mode)
V
200 mA
3.2 mA (Note 4)
7.0 mA
OH1
V
V
b
g
e
0.45V
I
Logical 0 Input Current
(Ports 1, 2 and 3)
75
10
mA
V
IL
IN
k
k
V
I
I
Input leakage Current (Port 0)
mA
mA
V
V
MAX
V
IN
LI
IL
CC
b
e
2V
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
750
TL
IN
RRST RST Pulldown Resistor
40
225
KX
@
1 MHz, 25 C
CIO
Pin Capacitance
10
pF
§
I
Power Supply Current:
(Note 3)
CC
Running at 16/20 MHz (Figure 5)
Idle Mode at 16/20 MHz (Figure 5)
Power Down Mode
20/25
5
15
28/33
12/14
100
mA
mA
mA
8
AUTOMOTIVE 87C54/87C54-20
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the V s of ALE and Ports 1, 2 and
OL
3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE
signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch
with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports 0 and 2 cause the V
address lines are stabilizing.
3. See Figures 6–9 for test conditions. Minimum V
on ALE and PSEN to drop below the 0.9 V specification when the
CC
OH
for Power Down is 2V.
CC
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
OL
Maximum I per 8-bit portÐ
10mA
OL
Port 0:
Ports 1, 2 and 3:
Maximum total I for all output pins:
26 mA
15 mA
71 mA
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater
OL OL
than the listed test conditions.
270849–8
270849–7
All other pins disconnected
e
I
Max at other frequencies is given by:
CC
Active Mode
e
TCLCH
TCHCL
5 ns
e
c
a
Osc Freq) 8
I
Max
(1.25
CC
Idle Mode
Max
Figure 7. I Test Condition, Active Mode
CC
e
c
a
4
I
(0.5
Osc Freq)
is in mA.
CC
Where Osc Freq is in MHz, I
CC
Figure 6. I vs Frequency
CC
270849–10
270849–9
All other pins disconnected
All other pins disconnected
e
e
TCLCH
TCHCL
5 ns
Figure 9. I Test Condition, Power Down Mode.
CC
e
V
2.0V to 6.0V.
Figure 8. I Test Condition Idle Mode
CC
CC
270849–11
e
e
5 ns.
Figure 10. Clock Signal Waveform for I Tests in Active and Idle Modes. TCLCH
CC
TCHCL
9
AUTOMOTIVE 87C54/87C54-20
P: PSEN
EXPLANATION OF THE AC SYMBOLS
Q: Output Data
R: RD signal
T: Time
Each timing symbol has 5 characters. The first char-
acter is always a ‘T’ (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
A: Address
C: Clock
For example,
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
e
e
T
T
Time from Address Valid to ALE Low
Time from ALE Low to PSEN Low
AVLL
LLPL
e b
a
e
e
0V, Load Capacitance
SS
g
AC CHARACTERISTICS (T
for Port 0, ALE/PROG and PSEN
40 C to 125 C, V
§
5V
20%, V
§
A
e
CC
e
100 pF, Load Capacitance for All Other Outputs
80 pF)
ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION
EXTERNAL MEMORY CHARACTERISTICS
Variable Oscillator
12 MHz Oscillator
87C54/87C54-20
Symbol
Parameter
Units
Min
Max
Min
Max
1/T
Oscillator
Frequency
3.5
16/20
MHz
CLCL
b
T
T
ALE Pulse Width
127
43
2 T
40
ns
ns
LHLL
CLCL
b
40
Address Valid to
ALE Low
T
CLCL
AVLL
LLAX
LLIV
b
T
T
T
Address Hold After
ALE Low
53
T
CLCL
30
ns
ns
ns
b
b
ALE Low to Valid
Instruction In
234
145
4 T
4 T
100/
CLCL
75*
CLCL
b
ALE Low to PSEN
Low
53
T
CLCL
30
LLPL
b
CLCL
T
T
PSEN Pulse Width
205
3 T
45
ns
ns
PLPH
b
b
PSEN Low to Valid
Instruction In
3 T
105/
PLIV
CLCL
3 T
90*
CLCL
T
T
T
T
Input Instruction
Hold After PSEN
0
0
ns
ns
ns
ns
PXIX
b
b
Input Instruction
Float After PSEN
59
312
10
T
T
25/
PXIZ
CLCL
20*
CLCL
b
105
Address Valid to
Valid Instruction In
5 T
AVIV
CLCL
PSEN Low to
Address Float
10
PLAZ
10
AUTOMOTIVE 87C54/87C54-20
Variable Oscillator
EXTERNAL MEMORY CHARACTERISTICS (Continued)
12 MHz Oscillator
Symbol
Parameter
87C54/87C54-20
Min Max
Units
Min
400
400
Max
b
b
T
T
T
RD Pulse Width
WR Pulse Width
6 T
6 T
100
100
ns
ns
ns
RLRH
WLWH
RLDV
CLCL
CLCL
b
RD Low to Valid
Data In
252
5 T
165/
CLCL
5 T
95*
CLCL
T
T
T
T
T
T
T
T
T
T
T
Data Hold After RD
High
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RHDX
RHDZ
LLDV
b
60
Data Float After RD
High
107
517
585
300
2 T
CLCL
b
ALE Low to Valid
Data In
8 T
8 T
150/
CLCL
b
90*
CLCL
CLCL
b
Address Valid to
Valid Data In
9 T
9 T
165/
AVDV
b
90*
CLCL
b
a
50
ALE Low to RD or
WR Low
200
203
33
3 T
50
3 T
CLCL
LLWL
AVWL
CLCL
b
Address Valid to
WR Low
4 T
130/
CLCL
b
4 T
90*
CLCL
b
Data Valid before
WR Low
T
T
50/
QVWX
WHQX
QVWH
CLCL
b
35*
CLCL
b
b
Data Hold after WR
High
33
T
T
50/
CLCL
40*
CLCL
b
Data Valid to WR
High
433
7 T
150/
CLCL
b
7 T
70*
CLCL
RD Low to Address
Float
0
0
RLAZ
b
a
40
RD or WR High to
ALE High
43
123
T
40
T
CLCL
WHLH
CLCL
NOTE:
*Timings speicified for the 87C54-20 are valid at 20 MHz only. For timings below 20 MHz, use the 87C54 timings.
11
AUTOMOTIVE 87C54/87C54-20
EXTERNAL PROGRAM MEMORY READ CYCLE
270849–12
EXTERNAL DATA MEMORY READ CYCLE
270849–13
EXTERNAL DATA MEMORY WRITE CYCLE
270849–14
12
AUTOMOTIVE 87C54/87C54-20
SERIAL PORT TIMINGÐSHIFT REGISTER MODE
e b
a
40 C to 125 C; V
e
e
5V 20%; V
SS
e
0V; Load Capacitance 80 pF
g
Test Conditions: T
§
§
A
CC
12 MHz Oscillator
Variable Oscillator
Min Max
12T
Symbol
Parameter
Units
Min
1
Max
T
T
Serial Port Clock Cycle Time
ms
XLXL
CLCL
b
CLCL
Output Data Setup to Clock
Rising Edge
700
10T
133
ns
QVXH
b
T
T
T
Output Data Hold after
Clock Rising Edge
50
0
2T
117
ns
ns
ns
XHQX
XHDX
XHDV
CLCL
0
Input Data Hold After Clock
Rising Edge
b
133
Clock Rising Edge to Input
Data Valid
700
10T
CLCL
SHIFT REGISTER MODE TIMING WAVEFORMS
270849–15
EXTERNAL CLOCK DRIVE
Symbol
1/T
Parameter
Min
Max
Units
Oscillator Frequency
87C54
CLCL
3.5
20
20
16/20
MHz
ns
T
T
T
T
High Time
Low Time
Rise Time
Fall Time
CHCX
ns
CLCX
CLCH
CHCL
20
20
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270849–16
13
AUTOMOTIVE 87C54/87C54-20
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270849–18
port pin is no longer floating when
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded V /V level occurs.
270849–17
For timing purposes
a
a
b
and 0.45V for a Logic ‘‘0’’. Timing measurements are made at V
AC Inputs during testing are driven at V
0.5V for a Logic ‘‘1’’
CC
IH
OH OL
min for a Logic ‘‘1’’ and V max for a Logic ‘‘0’’.
IL
t
g
20 mA.
I
/I
OL OH
EPROM CHARACTERISTICS
Table 3 shows the logic levels for programming the Program Memory, the Encryption Table and the Lock Bits
and for reading the signature bytes.
Table 3. EPROM Programming Modes
ALE/
EA/
Mode
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
PROG
V
PP
Program Code Data
Verify Code Data
H
H
H
L
L
L
ß
H
12.75V
H
L
L
L
H
L
H
L
H
H
L
H
H
H
Program Encryption
Array Address 0–3FH
ß
12.75V
H
H
Program Lock
Bits
Bit 1
Bit 2
Bit 3
H
H
H
H
L
L
L
L
ß
ß
ß
H
12.75V
12.75V
12.75V
H
H
H
H
L
H
H
L
H
H
H
L
H
L
H
L
L
L
H
L
Read Signature Byte
L
DEFINITION OF TERMS
PROGRAMMING THE EPROM
ADDRESS LINES: P1.0–P1.7, P2.0–P2.5 respec-
tively for A0–A13.
To be programmed, the part must be running with a
4 MHz to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appro-
priate internal EPROM locations.) The address of an
EPROM location to be programmed is applied to
Port 1 and pins P2.0–P2.5 of Port 2, while the code
byte to be programmed into that location is applied
to Port 0. The other Port 2 and 3 pins, RST, PSEN,
DATA LINES: P0.0–P0.7 for D0–D7.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7
PROGRAM SIGNALS: ALE/PROG, EA/V
PP
and EA/V should be held at the ‘‘Program’’ levels
PP
indicated in Table 3. ALE/PROG is pulsed low to
program the code byte into the addressed EPROM
location. The setup is shown in Figure 11.
14
AUTOMOTIVE 87C54/87C54-20
Normally EA/V is held at logic high until just be-
PP
fore ALE/PROG is to be pulsed. Then EA/V
Note that the EA/V pin must not be allowed to go
PP
is
PP
raised to V , ALE/PROG is pulsed low, and then
above the maximum specified V
level for any
PP
amount of time. Even a narrow glitch above that volt-
age level can cause permanent damage to the de-
vice. The V source should be well regulated and
PP
EA/V is returned to a valid high voltage. The volt-
PP
age on the EA/V pin must be at the valid EA/V
PP
PP
PP
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later
sections of this data sheet.
free of glitches.
270849–19
*See Table 3 for proper input on these pins
Figure 11. Programming the EPROM
Quick Pulse Programming Algorithm
Program Verification
The 87C54 can be programmed using the Quick
Pulse Programming Algorithm for microcontrollers.
The features of the new programming method are a
If the Program Lock Bits have not been pro-
grammed, the on-chip Program Memory can be read
out for verification purposes, if desired, either during
or after the programming operation. The address of
the Program Memory location to be read is applied
to Port 1 and pins P2.0–P2.5. The other pins should
be held at the ‘‘Verify’’ levels indicated in Table 3.
The contents of the addressed locations will come
out on Port 0. External pullups are required on Port 0
for this operation.
lower V (12.75V as compared to 21V) and a short-
PP
er programming pulse. It is possible to program the
entire 16K bytes of EPROM memory in less than 50
seconds with this algorithm!
To program the part using the new algorithm, V
PP
g
must be 12.75V 0.25V. ALE/PROG is pulsed low
for 100 ms, 25 times as shown in Figure 12. Then,
the byte just programmed may be verified. After pro-
gramming, the entire array should be verified. The
Program Lock features are programmed using the
same method, but with the setup as shown in Table
3. The only difference in programming Program Lock
features is that the Program Lock features cannot be
directly verified. Instead, verification of programming
is by observing that their features are enabled.
If the Encryption Array in the EPROM has been pro-
grammed, the data present at Port 0 will be Code
Data XNOR Encryption Data. The user must know
the Encryption Array contents to manually ‘‘unen-
crypt’’ the data during verify.
The setup, which is shown in Figure 13, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active
low read strobe.
15
AUTOMOTIVE 87C54/87C54-20
270849–22
Figure 12. PROG Waveforms
270849–23
Figure 13. Verifying the EPROM
16
AUTOMOTIVE 87C54/87C54-20
PROGRAMMING ALGORITHM
PROGRAM VERIFY
Refer to Table 3 and Figures 11 and 14 for address,
data, and control signals set up. To program the
87C54 the following sequence must be exercised.
Program verify may be done after each byte or block
of bytes is programmed. In either case a complete
verify of programmed array will ensure reliable pro-
gramming of the 87C54.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their fea-
tures are enabled. Refer to the EPROM Program
Lock section in this data sheet.
3. Activate the correct combination of control sig-
nals.
g
to 12.75V 0.25V.
4. Raise EA/V from V
PP
CC
5. Pulse ALE/PROG 5 times for the EPROM ar-
ray, and 25 times for the encryption table and
the lock bits.
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
270849–25
5 Pulses
Figure 14. Programming Signal’s Waveforms
17
AUTOMOTIVE 87C54/87C54-20
EPROM Program Lock
dress lines are used to select a byte of the Encryp-
tion Array. This byte is then exclusive-NOR’ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the un-
programmed state (all 1’s), will return the code in it’s
original, unmodified form. For programming the En-
cryption Array, refer to Table 3 (EPROM Program-
ming Modes).
The 87C54 program lock system, when pro-
grammed, protect the onboard program against soft-
ware piracy.
The 87C54 has a 3-level program lock system and a
64-byte encryption array. Since this is an EPROM
device, all locations are user programmable. See
Table 4.
Reading the Signature Bytes
The 87C54 has 3 signature bytes in locations 30H,
31H and 60H. To read these bytes follow the proce-
dure for EPROM verify, but activate the control lines
provided in Table 3 for Read Signature Byte.
Program Lock Bits
The 87C54 has 3 programmable lock bits that when
programmed according to Table 4 will provide differ-
ent levels of protection for the on-chip code and
data. See Table 3.
Contents
Location
87C54
Erasing the EPROM also erases the encryption ar-
ray and the program lock bits, returning the part to
full functionality.
30H
31H
60H
89H
58H
54H
Encryption Array
Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1’s). Every
time that a byte is addressed during a verify, 6 ad-
Table 4. Program Lock Bits and the Features
Protection Type
Program Lock Bits
LB1
LB2
LB3
1
2
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
P
U
U
MOVC instructions executed from external program memory are disabled
from fetching code bytes from internal memory, EA is sampled and latched on
Reset, and further programming of the EPROM is disabled.
3
4
P
P
P
P
U
P
Same as 2, also verify is disabled.
Same as 3, also external execution is disabled.
Any other combination of the lock bits is not defined.
18
AUTOMOTIVE 87C54/87C54-20
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
e
e
e
0V)
SS
g
(T
A
21 C to 27 C; V
5V
20%; V
§
§
CC
ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION
Symbol
Parameter
Min
Max
13.0
75
Units
V
V
Programming Supply Voltage
Programming Supply Current
Oscillator Frequency
12.5
PP
I
mA
PP
1/T
4
6
MHz
CLCL
AVGL
GHAX
T
Address Setup to PROG Low
Address Hold after PROG
Data Setup to PROG Low
Data Hold after PROG
48T
CLCL
CLCL
CLCL
CLCL
CLCL
T
48T
48T
48T
48T
T
DVGL
GHDX
T
T
T
T
(Enable) High to V
PP
EHSH
SHGL
GHSL
GLGH
V
Setup to PROG Low
10
ms
ms
ms
PP
PP
V
Hold after PROG
10
90
T
PROG Width
110
T
Address to Data Valid
ENABLE Low to Data Valid
Data Float after ENABLE
PROG High to PROG Low
48T
AVQV
CLCL
CLCL
CLCL
T
48T
48T
ELQV
EHQZ
GHGL
T
T
0
10
ms
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
270849–26
19
AUTOMOTIVE 87C54/87C54-20
DATA SHEET REVISION HISTORY
The following are key differences between this data sheet and the -003 version of the data sheet.
1. The data sheet has been revised to include the 20 MHz 87C54. The title was changed from 87C54 to
87C54/87C54-20.
2. RST pin in Figure 3 has been changed to RESET pin.
3. Max I
has been corrected to reflect test program conditions.
CC
4. Figure 6, I
vs. Frequency, has been changed to reflect new I
specifications.
CC
CC
5. 87C54-20 A.C. Timings have been added to the External Memory Characteristics Table.
The following are key differences between this data sheet and the -002 version of the data sheet.
1. ‘‘NC’’ pin labels changed to ‘‘Reserved’’ in Figure 3.
2. Capacitor value for ceramic resonators deleted in Figure 4.
3. Replaced A0–A15 with P1.0–P1.7, P2.0–P2.5 (EPROM programming and verification waveforms).
4. Replaced D0–D7 with P0 (EPROM programming and verification waveforms).
The following are the key differences between the -001 and the -002 versions of this data sheet.
1. The RST description has been modified to clarify the reset operation when the oscillator is not running.
2. Figure 4 (Oscillator Connections) has been changed for Ceramic Resonators.
3. A description of RFI Reduction Mode has been added.
4. V , I , I and I
IL IL TL
DC Characteristics have been revised.
CC
g
5. AC and DC Characteristics are specified to 10% V
g
revised from 20% V
.
CC
CC
20
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