TS83C196KB [INTEL]
Microcontroller, 16-Bit, MROM, 12MHz, CMOS, PQFP80;
| 型号： | TS83C196KB |
| 厂家： | 
INTEL |
| 描述： | Microcontroller, 16-Bit, MROM, 12MHz, CMOS, PQFP80 微控制器 |
| 文件： | 总22页 (文件大小：1359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8XC196KB/8XC196KB16
COMMERCIAL/EXPRESS CHMOS MICROCONTROLLER
Y
Y
8 Kbytes of On-Chip ROM/OTP
Available
Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
232 Byte Register File
Full Duplex Serial Port
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
1.75 ms 16 x 16 Multiply (16 MHz)
3.0 ms 32/16 Divide (16 MHz)
Powerdown and Idle Modes
Five 8-Bit I/O Ports
High Speed I/O Subsystem
16-Bit Timer
16-Bit Up/Down Counter with Capture
Pulse-Width-Modulated Output
Four 16-Bit Software Timers
10-Bit A/D Converter with Sample/Hold
HOLD/HLDA Bus Protocol
16-Bit Watchdog Timer
12 MHz and 16 MHz Available
Dedicated 15-Bit Baud Rate Generator
Extended Temperature Available
The 8XC196KB is a 16-bit microcontroller available in three different memory varieties: ROMless (80C196KB),
8K ROM (83C196KB) and 8K OTP (One Time Programmable-87C196KB). The 8XC196KB is a high perform-
ance member of the MCS 96 microcontroller family. The 8XC196KB has the same peripheral set as the
É
8096BH and has a true superset of the 8096BH instructions. Intel's CHMOS process provides a high perform-
ance processor along with low power consumption. To further reduce power requirements, the processor can
be placed into Idle or Powerdown Mode.
Bit, byte, word and some 32-bit operations are available on the 80C196KB. With a 16 MHz oscillator a 16-bit
addition takes 0.50 ms, and the instruction times average 0.37 ms to 1.1 ms in typical applications.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter. Also provided on-chip are an
A/D converter, serial port, watchdog timer and a pulse-width-modulated output signal.
The 8XC196KB has a maximum guaranteed frequency of 12 MHz. The 8XC196KB16 has a maximum guaran-
teed frequency of 16 MHz. All references to the 80C196KB also refer to the 80C196KB16; 83C196KB, Rxxx;
87C196KB and 87C196KB16 unless otherwise noted. The ROM device does not have a speed indicator at the
end of the device name. Instead it has a ROM code number.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the tem-
a
perature range of 0 C to 70 C. With the extended temperature range option, operational characteristics are
§
§
b
a
guaranteed over the temperature range of 40 C to 85 C.
§
§
*Other brands and names are the property of their respective owners.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT
INTEL CORPORATION,2004
July 2004
Order Number: 270909-007
8XC196KB/8XC196KB16
270909±1
Figure 1. 8XC196KB Block Diagram
2
8XC196KB/8XC196KB16
Table 2. 8XC196KB Memory Map
PROCESS INFORMATION
Description
Address
This device is manufactured on P629.0 and 629.1, a
CHMOS III-E process. Additional process and reli-
ability information is available in the Intel Quality
System Handbook:
http://developer.intel.com/design/quality/quality.htm
0FFFFH
04000H
External Memory or I/O
®
Internal ROM/EPROM or External
Memory (Determined by EA)
3FFFH
2080H
Reserved. Must contain FFH.
(Note 5)
207FH
2040H
Upper Interrupt Vectors
203FH
2030H
ROM/EPROM Security Key
202FH
2020H
Reserved. Must contain FFH.
(Note 5)
201FH
201AH
Reserved. Must Contain 20H.
(Note 5)
2019H
270909–2
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
CCB
2018H
Reserved. Must contain FFH.
(Note 5)
2017H
2014H
Figure 2. The 8XC196KB Nomenclature
Lower Interrupt Vectors
2013H
2000H
Table 1. Thermal Characteristics
Port 3 and Port 4
1FFFH
1FFEH
Package
θ
θ
jc
ja
Type
PLCC
QFP
External Memory
1FFDH
0100H
35 C/W
°
13 C/W
°
70 C/W
°
4 C/W
°
232 Bytes Register RAM (Note 1)
CPU SFR’s (Notes 1, 3)
00FFH
0018H
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel Packaging Handbook (order number 240800) for a
description of Intel’s thermal impedance test methodology.
0017H
0000H
NOTES:
1. Code executed in locations 0000H to 00FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KB quick reference for SFR descrip-
tions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
8XC196KB/8XC196KB16
270909–3
Figure 3. 68-Pin Package (PLCC Top View)
NOTE:
The above pin out diagram applies to the OTP (87C196KB) device. The OTP device uses all of the programming pins shown
above. The ROM (83C196KB) device only uses programming pins: AINC, PALE, PMODE.n, and PROG. The ROMless
(80C196KB) doesn’t use any of the programming pins.
4
8XC196KB/8XC196KB16
270909–4
NOTE:
N.C. means No Connect (do not connect these pins).
Figure 4. 80-Pin QFP Package
NOTE:
The above pin out diagram applies to the OTP (87C196KB) device. The OTP device uses all of the programming pins shown
above. The ROM (83C196KB) device only uses programming pins: AINC, PALE, PMODE.n, and PROG. The ROMless
(80C196KB) doesn’t use any of the programming pins.
5
8XC196KB/8XC196KB16
PIN DESCRIPTIONS
Symbol
Name and Function
V
V
V
Main supply voltage (5V).
Digital circuit ground (0V). There are multiple V pins, all of them must be connected.
CC
SS
SS
Reference voltage for the A/D converter (5V). V
is also the supply voltage to the analog
REF
REF
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
ANGND
Reference ground for the A/D converter. Must be held at nominally the same potential as
V
SS
. Connect V and ANGND at chip to avoid noise problems.
SS
V
Programming voltage. Also timing pin for the return from power down circuit.
Input of the oscillator inverter and of the internal clock generator.
Output of the oscillator inverter.
PP
XTAL1
XTAL2
CLKOUT
Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
frequency. It has a 50% duty cycle.
RESET
Reset input to and open-drain output from the chip. Input low for at least 4 state times to reset
the chip. The subsequent low-to-high transition re-synchronizes CLKOUT and commences a
10-state-time RESET sequence.
BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI
A positive transition causes a vector through 203EH.
INST
Output high during an external memory read indicates the read is an instruction fetch and
output low indicates a data fetch. INST is valid throughout the bus cycle. INST is activated
only during external memory accesses.
EA
Input for memory select (External Access). EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/OTPR OM. EA equal to a
TTL-low causes accesses to these locations to be directed to off-chip memory.
ALE/ADV
Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide
a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory
accesses.
RD
Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL
Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.
BHE/WRH
READY
Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will
go low for external writes to the high byte of the data bus. WRH will go low for external writes
where an odd byte is being addressed. BHE/WRH is activated only during external memory
writes.
Ready input to lengthen external memory cycles. If the pin is low prior to the falling edge of
CLKOUT, the memory controller goes into a wait mode until the next positive transition in
CLKOUT occurs with READY high. When the external memory is not being used, READY has
no effect. Internal control of the number of wait states inserted into a bus cycle (held not
ready) is available in the CCR.
HSI
Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO
Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
HSO.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
6
8XC196KB/8XC196KB16
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
Port 0
8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1
Port 2
8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.
8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KB.
Pins P2.6 and P2.7 are quasi-bidirectional.
Ports 3 and 4
8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus, which has strong internal pullups.
HOLD
HLDA
BREQ
Bus Hold input requesting control of the bus. Enabled by setting WSR.7.
Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.
Bus Request output activated when the bus controller has a pending external memory
cycle. Enabled by setting WSR.7.
TxD
RxD
The TxD pin is used for serial port transmission in Modes 1, 2 and 3. In Mode 0 the pin is
used as the serial clock output.
Serial Port Receive pin used for serial port reception. In Mode 0 the pin functions as input or
output data.
EXTINT
T2CLK
T2RST
PWM
A rising edge on the EXTINT pin will generate an external interrupt.
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.
A rising edge on the T2RST pin will reset Timer2.
The pulse width modulator output.
T2UP-DN
The T2UPDN pin controls the direction of Timer2 as an up or down counter.
T2CAPTURE A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register.
PMODE
Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the part is
operating.
SID
Slave ID Number. Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement.
PALE
PROG
PACT
PVAL
PVER
AINC
Programming ALE Input. Accepted by the 87C196KB when it is in Slave Programming
Mode. Used to indicate that Ports 3 and 4 contain a command/address.
Programming. Falling edge indicates valid data on PBUS and the beginning of
programming. Rising edge indicates end of programming.
Programming Active. Used in the Auto Programming Mode to indicate when programming
activity is complete.
Program Valid. This signal indicates the success or failure of programming in the Auto
Programming Mode. A zero indicates successful programming.
Program Verification. Used in Slave Programming and Auto CLB Programming Modes.
Signal is low after rising edge of PROG if the programming was not successful.
Auto Increment. Active low signal indicates that the auto increment mode is enabled. Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
Ports 3
and 4
(Programming
Mode)
Address/Command/Data Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,
addresses and data to slaves. Also used in the Auto Programming Mode as a regular
system bus to access external memory. Should have pullups to V when used in slave
CC
programming mode.
7
8XC196KB/8XC196KB16
ELECTRICAL CHARACTERISTICS
NOTICE: This data sheet contains preliminary infor-
mation on new products in production. The specifica-
tions are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias................................. 55 C to 125 C
b
a
§
§
§
§C
b
a
Storage Temperature.................... 65 C to 150
*WARNING: Stressing the device beyond the ``Absolute
Maximum Ratings'' may cause permanent damage.
These are stress ratings only. Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability.
b
a
Voltage On Any Pin to V
SS................
0.5V to 7.0V
(1)..........................
Power Dissipation
1.5W
NOTE:
1. Power dissipation is based on package heat transfer lim-
itations, not device power consumption.
OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol
Description
Min
Max
Units
a
T
A
Ambient Temperature Under Bias
Digital Supply Voltage
0
70
C
§
V
V
4.50
4.50
3.5
5.50
5.50
12
V
CC
Analog Supply Voltage
V
REF
OSC
OSC
F
F
Oscillator Frequency 12 MHz
Oscillator Frequency 16 MHz
MHz
MHz
3.5
16
NOTE:
ANGND and V should be nominally at the same potential.
SS
DC CHARACTERISTICS
Symbol
Description
Min
Max
Units Test Conditions
b
V
V
Input Low Voltage
0.5
0.8
V
V
IL
a
a
Input High Voltage (All Pins except
XTAL1 and RESET)
0.2 V
0.9
V
0.5
IH
CC
CC
a
a
V
IH1
V
IH2
V
OL
Input High Voltage on XTAL 1
Input High Voltage on RESET
Output Low Voltage
0.7 V
V
V
0.5
0.5
V
V
CC
CC
2.6
CC
e
e
e
0.3
0.45
1.5
V
V
V
I
I
I
200 mA
3.2 mA
7 mA
OL
OL
OL
b
b
b
e b
e b
e b
V
OH
Output High Voltage
(Standard Outputs)
V
V
V
0.3
0.7
1.5
V
V
V
I
I
I
200 mA
3.2 mA
7 mA
CC
CC
CC
OH
OH
OH
(2)
b
b
b
e b
e b
e b
V
Output High Voltage
(Quasi-bidirectional Outputs)
V
CC
V
CC
V
CC
0.3
0.7
1.5
V
V
V
I
I
I
10 mA
30 mA
60 mA
OH1
OH
OH
OH
k
(1)
k
b
0.3V
g
I
LI
Input Leakage Current
10
mA
0
V
IN
V
CC
(3)
(Std. Inputs)
k
k
a
I
I
Input Leakage Current (Port 0)
1 to 0 Transition Current
(QBD Pins)
3
mA
mA
0
V
V
LI1
IN
REF
b
e
e
800
V
2.0V
TL
IN
(1)
(1)
b
I
IL
Logical 0 Input Current (QBD Pins)
50
mA
V
0.45V
IN
8
8XC196KB/8XC196KB16
DC CHARACTERISTICS (Continued)
Symbol Description
Min Typ(7) Max
Units Test Conditions
b
e
e
e
I
I
I
Logical 0 Input Current in Reset
BHE, WR, P2.0
850
mA
mA
mA
V
IN
V
IN
V
IN
0.45V
0.45V
2.0V
IL1
IL2
IH1
b
Logical 0 Input Current in Reset
ALE, RD, INST
7
Logical 1 Input Current
on NMI Pin
100
Hyst.
Hysteresis on RESET Pin
Active Mode Current in Reset
A/D Converter Reference Current
Idle Mode Current
300
mV
mA
mA
mA
mA
X
e
16 MHz
I
I
I
I
50
2
60
5
CC
e
e
e
V
PP
V
REF
5.5V
5.5V
REF
IDLE
PD
10
5
25
30
50K
10
e
Powerdown Mode Current
Reset Pullup Resistor
V
PP
V
REF
R
RST
6K
e
C
S
Pin Capacitance (Any Pin to V
)
SS
pF
F
1.0 MHz
TEST
NOTES: (Notes apply to all specifications)
1. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
2. Standard Outputs include AD0±15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The V specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
OH
3. Standard Inputs include HSI pins, EA, READY, BUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/
P2.4.
4. Maximum current per pin must be externally limited to the following values if V
is held above 0.45V or V is held
OL
OH
b
below V
CC
0.7V:
I
I
I
on Output pins: 10 mA
on quasi-bidirectional pins: self limiting
on Standard Output pins: 10 mA
OL
OH
OH
g
5. Maximum current per bus pin (data and control) during normal operation is 3.2 mA.
6. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
I
I
I
: 29 mA
: 29 mA
: 13 mA
I
I
I
is self limiting
: 26 mA
: 11 mA
OL
OL
OL
OH
OH
OH
HSO, P2.0, RXD, RESET
P2.5, P2.7, WR, BHE
AD0±AD15
I
: 52 mA
I
: 52 mA
OL
OH
RD, ALE, INST±CLKOUT
I : 13 mA
OL
I : 13 mA
OH
7. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
e
e
5V.
and V
V
CC
REF
e
Max
c
a
FREQ 8.43
I
I
Max
3.88
270909±5
CC
e
c
a
FREQ 2.2
1.65
IDLE
Figure 6. I and I
vs Frequency
IDLE
CC
9
8XC196KB/8XC196KB16
AC CHARACTERISTICS
Test Conditions: Capacitive load on all pins
e
e
e
12/16 MHz
OSC
100 pF, Rise and fall times
10 ns, F
The system must meet these specifications to work with the 87C196KB:
Symbol
Description
Min
Max
2 T
Units
ns
Notes
b
T
AVYV
T
YLYH
T
CLYX
T
LLYX
T
AVGV
T
CLGX
T
AVDV
T
RLDV
T
CLDV
T
RHDZ
T
RXDX
Address Valid to READY Setup
NonREADY Time
75
OSC
No upper limit
ns
b
READY Hold after CLKOUT Low
READY Hold after ALE Low
Address Valid to Buswidth Setup
Buswidth Hold after CLKOUT Low
Address Valid to Input Data Valid
RD Active to Input Data Valid
CLKOUT Low to Input Data Valid
End of RD to Input Data Float
Data Hold after RD Inactive
0
T
30
ns
(Note 1)
(Note 1)
OSC
b
b
b
T
OSC
15
2 T
40
75
ns
OSC
OSC
2 T
ns
0
ns
b
3 T
55
ns
(Note 2)
(Note 2)
OSC
b
T
OSC
T
OSC
T
OSC
23
ns
b
b
50
20
ns
ns
0
ns
NOTES:
1. If max is exceeded, additional wait states will occur.
c
e
number of wait states.
2. When using wait states, add 2 T
n where n
OSC
10
8XC196KB/8XC196KB16
AC CHARACTERISTICS (Continued)
Test Conditions: Capacitive load on all pins
e
e
e
12/16 MHz
OSC
100 pF, Rise and fall times
10 ns, F
The 87C196KB will meet these specifications:
Symbol
Description
Min
Max
Units
MHz
MHz
ns
Notes
F
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Frequency on XTAL1 12 MHz
Frequency on XTAL1 16 MHz
3.5
3.5
12.0
(Note 2)
(Note 2)
XTAL
XTAL
OSC
16.0
286
286
1/F
1/F
12 MHz
16 MHz
83.3
62.5
XTAL
XTAL
ns
OSC
a
a
110
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
20
ns
XHCH
CLCL
CHCL
CLLH
LLCH
LHLH
LHLL
2 T
ns
OSC
b
10
15
a
10
15
CLKOUT High Period
T
OSC
10
T
OSC
10
ns
b
a
a
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
ns
b
ns
4 T
ns
(Note 3)
OSC
b
b
b
b
a
ALE High Period
T
OSC
T
OSC
T
OSC
T
OSC
10
T
OSC
10
ns
Address Setup to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
RD Low to CLKOUT Falling Edge
RD Low Period
20
40
35
ns
AVLL
LLAX
LLRL
ns
ns
a
a
4
25
a
a
ns
RLCL
RLRH
RHLH
RLAZ
LLWL
CLWL
QVWH
CHWH
WLWH
WHQX
WHLH
WHBX
RHBX
WHAX
RHAX
b
T
OSC
5
T
T
25
25
ns
(Note 3)
(Note 1)
OSC
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
T
ns
OSC
OSC
a
5
ns
b
ALE Falling Edge to WR Falling Edge
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
T
OSC
10
23
ns
a
0
25
ns
b
T
OSC
ns
(Note 3)
(Note 3)
(Note 1)
b
a
5
15
ns
b
b
b
b
b
b
b
a
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
T
OSC
15
15
15
15
10
30
25
T
OSC
5
ns
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE, INST HOLD after WR Rising Edge
BHE, INST HOLD after RD Rising Edge
AD8±15 hold after WR Rising Edge
AD8±15 hold after RD Rising Edge
ns
a
T
OSC
10
ns
ns
ns
ns
ns
NOTES:
1. Assuming back-to-back bus cycles.
2. Testing performed at 3.5 MHz, however, the device is static by design and will typically operate below 1 Hz.
a
e
number of wait states.
3. When using wait states, all 2 T
n where n
OSC
11
8XC196KB/8XC196KB16
System Bus Timings
270909±6
12
8XC196KB/8XC196KB16
READY Timings (One Wait State)
270909±7
Buswidth Bus Timings
270909±8
13
8XC196KB/8XC196KB16
HOLD/HLDA Timings
Symbol
Description
Min
Max
Units
ns
Notes
T
T
T
T
T
T
T
T
T
T
T
T
HOLD Setup
55
(Note 1)
HVCH
CLKOUT Low to HLDA Low
CLKOUT Low to BREQ Low
HLDA Low to Address Float
HLDA Low to BHE, INST, RD, WR Float
CLKOUT Low to HLDA High
CLKOUT Low to BREQ High
HLDA High to Address No Longer Float
HLDA High to Address Valid
HLDA High to BHE, INST, RD, WR No Longer Float
HLDA High to BHE, INST, RD, WR Valid
CLKOUT Low to ALE High
15
15
10
10
15
15
ns
CLHAL
CLBRL
HALAZ
HALBZ
CLHAH
CLBRH
HAHAX
HAHAV
HAHBX
HAHBV
CLLH
ns
ns
ns
b
b
b
15
15
15
ns
ns
ns
0
ns
b
20
ns
0
ns
b
5
15
ns
NOTE:
1. To guarantee recognition at next clock.
Maximum Hold Latency
Bus Cycle Type
Internal Access
Latency
1.5 States
2.5 States
4.5 States
16-Bit External Execution
8-Bit External
270909±9
14
8XC196KB/8XC196KB16
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
12.0
Units
MHz
1/T
1/T
Oscillator Frequency 12 MHz
Oscillator Frequency 16 MHz
Oscillator Period 12 MHz
Oscillator Period 16 MHz
High Time
3.5
3.5
XLXL
XLXL
16
MHz
ns
T
T
T
T
T
T
83.3
62.5
286
286
XLXL
ns
XLXL
XHXX
XLXX
XLXH
XHXL
21.25
21.25
ns
Low Time
ns
Rise Time
10
10
ns
Fall Time
ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270909±10
An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the V and
IL
V
IH
specifications, the capacitance will not exceed 20 pF.
EXTERNAL CRYSTAL CONNECTIONS
EXTERNAL CLOCK CONNECTIONS
270909±11
NOTE:
270909±12
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and V . When
* Required if open-collector TTL driver used
Not needed if CMOS driver is used.
SS
e
e
20 pF. When using
using crystals, C1
20 pF, C2
ceramic resonators, consult manufacturer for recom-
mended circuitry.
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270909±13
AC Testing inputs are driven at 2.4V for a Logic ``1'' and 0.45V for
a Logic ``0'' Timing measurements are made at 2.0V for a Logic
``1'' and 0.8V for a Logic ``0''.
270909±14
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs and Begins to Float
when a 200 mV change from the Loaded V /V
Level occurs;
OH OL
e
g
15 mA.
I
/I
OL OH
15
8XC196KB/8XC196KB16
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ``T'' for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H
L
- High
A
B
- Address
- BHE
G
H
- Buswidth
- HOLD
R
W
X
- RD
- Low
- WR/WRH /WRL
- XTAL1
V
X
Z
- Valid
BR - BREQ
HA - HLDA
- No Longer Valid
- Floating
C
D
- CLKOUT
- DATA IN
L
- ALE/ADV
- DATA OUT
Y
- READY
Q
AC CHARACTERISTICS-SERIAL
PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE (MODE 0)
Symbol Parameter
Min
Max
Units
ns
t
T
T
T
T
T
T
T
T
T
T
Serial Port Clock Period (BRR 8002H)
6 T
XLXL
OSC
t
b
a
a
Serial Port Clock Falling Edge to Rising Edge (BRR 8002H) 4 T
50 4 T
50 ns
ns
XLXH
XLXL
OSC
OSC
e
Serial Port Clock Period (BRR
8001H)
4 T
OSC
e
b
Serial Port Clock Falling Edge to Rising Edge (BRR
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Next Output Data Valid after Clock Rising Edge
Input Data Setup to Clock Rising Edge
Input Data Hold after Clock Rising Edge
Last Clock Rising to Output Float
8001H) 2 T
50 2 T
50
50 ns
ns
XLXH
QVXH
XHQX
XHQV
DVXH
XHDX
XHQZ
OSC
OSC
b
b
2 T
OSC
OSC
2 T
50
ns
a
2 T
50
ns
ns
ns
ns
OSC
a
T
OSC
50
0
2 T
OSC
WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE (MODE 0)
270909±18
16
8XC196KB/8XC196KB16
State times are calculated as follows:
10-BIT A/D CHARACTERISTICS
2
At a clock speed of 6 MHz or less, the clock prescal-
er should be disabled. This is accomplished by set-
e
state time
XTAL1
e
ting IOC2.4
1.
The converter is ratiometric, so the absolute accura-
cy is directly dependent on the accuracy and stability
At higher frequencies (greater than 6 MHz) the clock
e
of V
. V
must be close to V since it supplies
prescaler should be enabled (IOC2.4
the comparator to settle.
0) to allow
REF REF CC
both the resistor ladder and the digital section of the
converter.
The table below shows two different clock speeds
and their corresponding A/D conversion and sample
times.
See the MCS-96 A/D Converter Quick Reference
for definition of A/D terms.
Example Sample and Conversion Times
Sample Time
at Clock
Conversion
Time at
Clock Speed
(ms)
Conversion
Time
(States)
A/D Clock
Prescaler
Clock Speed
(MHz)
Sample Time
(States)
Speed
(ms)
e
IOC2.4
IOC2.4
0
1
x
x
ON
16
6
15
8
1.875
2.667
156.5
89.5
19.6
29.8
e
OFF
A/D CONVERTER SPECIFICATIONS
Parameter
Typical(1)
Minimum
Maximum
Units *
Notes
Resolution
1024
10
1024
10
Levels
Bits
g
Absolute Error
0
3
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
g
0.25 0.50
Full Scale Error
g
0.25 0.50
Zero Offset Error
g
g
a
Non-Linearity Error
Differential Non-Linearity Error
Channel-to-Channel Matching
Repeatability
1.5 2.5
0
3
2
1
l
b
1
g
g
0.1
0
g
0.25
Temperature Coefficients:
Offset
Full Scale
0.009
0.009
0.009
LSB/ C
§
LSB/ C
§
Differential Non-Linearity
LSB/ C
§
b
Off Isolation
Feedthrough
60
dB
dB
dB
X
2, 3
b
b
60
60
2
2
4
V
CC
Power Supply Rejection
Input Series Resistance
DC Input Leakage
750
0
1.2K
g
3.0
mA
pF
Sampling Capacitor
3
NOTES:
*An ``LSB'', as used here, has a value of approximately 5 mV.
1. Typical values are expected for most devices at 25 C.
§
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make Guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
17
8XC196KB/8XC196KB16
OTPROM SPECIFICATIONS
OTPROM PROGRAMMING OPERATING CONDITIONS
Symbol
Parameter
Min
20
Max
30
Units
T
Ambient Temperature During Programming
Supply Voltages During Programming
Programming Mode Supply Voltage
EPROM Programming Supply Voltage
Digital and Analog Ground
C
A
(1)
V
V
V
V
, V , V
CC PD REF
4.5
5.5
V
(2)
V
12.50
12.50
0
13.0
13.0
0
EA
(2)
V
PP
(3)
, ANGND
V
SS
F
Oscillator Frequency 12 MHz
6.0
12.0
16.0
MHz
MHz
OSC
OSC
F
Oscillator Frequency 16 MHz
6.0
NOTES:
1. V , V and V
should nominally be at the same voltage during programming.
CC PD REF
2. V and V must never exceed the maximum voltage for any amount of time or the device may be damaged.
EA PP
3. V and ANGND should nominally be at the same voltage (0V) during programming.
SS
AC OTPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Reset High to First PALE Low
PALE Pulse Width
Min
Max
Units
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
1100
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SHLL
LLLH
AVLL
LLAX
LLVL
PLDV
PHDX
DVPL
PLDX
PLPH
PHLL
LHPL
PHPL
PHIL
ILIH
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
40
0
Address Setup Time
Address Hold Time
50
PALE Low to PVER Low
PROG Low to Word Dump Valid
Word Dump Data Hold
Data Setup Time
60
50
50
0
Data Hold Time
50
PROG Pulse Width
40
PROG High to Next PALE Low
PALE High to PROG Low
PROG High to Next PROG Low
PROG High to AINC Low
AINC Pulse Width
120
220
120
0
40
PVER Hold after AINC Low
AINC Low to PROG Low
PROG High to PVER Low
50
ILVH
ILPL
170
90
PHVL
18
8XC196KB/8XC196KB16
DC OTPROM PROGRAMMING CHARACTERISTICS
Symbol
Description
Min
Max
100
Units
mA
I
V
PP
Supply Current (When Programming)
PP
NOTE:
Do not apply V until V
is stable and within specifications and the oscillator/clock has stabilized or the device may be
PP
CC
damaged.
OTPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
270909±15
SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT
270909±16
19
8XC196KB/8XC196KB16
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT
270909±17
20
8XC196KB/8XC196KB16
The following differences exist between this data
sheet (270909-005) and (270909-004).
FUNCTIONAL DEVIATIONS
Devices marked with an ‘‘E’’, ‘‘F’’ or ‘‘G’’ have the
following errata.
–
1. I MAX was 650 μA (270909-004). Now I
TL
TL
–
MAX is 800 μA (270909-005).
2. I was named I (270909-004). Now I
IL2
is
IL2
IL1
1. Missed Interrupt on P0.7, EXTINT
correctly named (270909-005).
3. I was omitted (270909-004). I
MAX was
IL1
Interrupts occurring on P0.7 could be missed since
the INT_PEND EXTINT bit may not be set. See
techbit MC0893.
IL1
–
added. I MAX is 850 μA (270909-005).
IL1
4. T
and T
(270909-004) were removed.
LLGV
LLYV
These timings are not required in high-speed sys-
tem designs.
2. HSI_ MODE Divide-by-Eight
5. An errata was added to the known errata section.
There is a possibility to miss an external interrupt
on P0.7 EXTINT.
REVISION HISTORY
The following differences exist between this data
sheet (270909-004) and (270909-003).
This data sheet (270909-006) is valid for devices
with an ‘‘E’’, ‘‘F’’ or ‘‘G’’ at the end of the top side
tracking number. Data sheets are changed as new
device information becomes available. Verify with
your local Intel sales office that you have the latest
version before finalizing a design or ordering devic-
es.
1. The
ROM
(80C196KB),
and
ROMless
(83C196KB) were combined with this data sheet
resulting in no specification differences.
2. The description of the prescalar bit for the A/D
has been enhanced.
The following differences exist between this data
sheet (270909-007) and (270909-006).
–
3. T
T
MIN was
15 ns (270909-003). Now
HAHBV
HAHBV
–
MIN is 20 ns (270909-004).
1. Package prefix variables have changed.
4. T
T
MAX was 1 TOSC (270909-003). Now
XHQZ
MAX is 2 TOSC (270909-004). This should
XHQZ
These variables are now indicated by “x”.
have no impact on designs using synchronous
serial mode 0.
The following differences exist between data
sheet 270909-006 and 270909-005.
5. The change indicators for the 80C196KB are
‘‘E’’, ‘‘F’’ and ‘‘G’’. Previously there was only one
change indicator ‘‘E’’. The change indicator is
used for tracking purposes. The change indicator
is the last character in the FPO number. The FPO
number is the second line on the top side of the
device.
1. Removed ‘‘Word Addressable Only’’ from Port 3
and 4 in Table 2.
2. Removed ICC1, active mode current at 3.5 MHz.
This specification is not longer required.
3. Removed TLLYV and TLLGV from waveform dia-
grams.
4. The HSI errata and CMPL with R0 were removed
as this is now considered normal operation.
5. The HSI_MODE divide-by-eight errata was add-
ed to the known errata section.
21
8XC196KB/8XC196KB16
The following differences exist between (-003) and
version (-002).
Differences between the -002 and -001 data sheets.
1. The -001 version of this data sheet was valid for
devices marked with a ``C'' at the end of the top
side tracking number.
1. The 12 MHz and 16 MHz devices were com-
bined in this data sheet. The 87C196KB 12 MHz
only data sheet (272035-001) is now obsolete.
2. Added 64L SDIP and 80L QFP packages.
3. Added IIH1.
2. Changes were made to the format of the data
sheet and the SFR descriptions were removed.
b
a
b
a
4. Changed T
5. Changed T
Min from
Max from
10 ns to
10 ns to
5 ns.
CHWH
CHWH
3. The -002 version of this data sheet was valid for
devices marked with a ``B'' or a ``D'' at the end
of the top side tracking number.
15 ns.
b
6. Changed T
Min from T
Min from T
Min from T
Max from T
Min from T
20 ns to
10 ns to
10 ns to
15 ns to
10 ns to
WLWH
WHQX
WHLH
WHLH
WHBX
HVCH
OSC
b
T
OSC
15 ns.
4. The OSCILLATOR errata was removed.
b
7. Changed T
OSC
5. An errata was not documented in the -002 data
sheet for devices marked with a ``B'' or a ``D''.
This is the DIVIDE DURING HOLD/READY er-
rata. When HOLD or READY is active and DIV/
DIVB is the last instruction in the queue, the di-
vide result may be incorrect.
b
T
OSC
15 ns.
b
8. Changed T
OSC
b
T
OSC
15 ns.
a
9. Changed T
OSC
a
T
OSC
10 ns.
e
40 ns to Min
e
6. T
was changed from Min
XCH
b
10. Changed T
OSC
20 ns.
b
T
OSC
15 ns.
e
e
7. T
was changed from Min
5 ns to Min
RLCL
11. Changed T
12. Remove T
Min from 85 ns to 55 ns.
Max.
4 ns.
HVCH
e b
e
9. I was changed from Max
6 mA to Max
IL1
b
b
15 ns.
13. Changed T
14. Changed T
15. Changed T
16. Changed T
17. Changed T
Min from
10 ns to
CLHAL
CLHAL
CLBRL
CLBRL
HAHAX
b
7 mA.
Max from 20 ns to 15 ns.
e b
10. T
was changed from Min
15 ns.
10 ns to
HAHBV
e b
b
b
15 ns.
Min
Min from
10 ns to
Max from 20 ns to 15 ns.
b
b
15 ns.
Min from
10 ns to
18. Added HSI description to Functional Deviations.
19. Added Oscillator description to Functional Devi-
ations.
22
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