WJLXT972ALC.A4SE001 [INTEL]
Ethernet Transceiver, CMOS, PQFP64, LEAD FREE, LQFP-64;
| 型号： | WJLXT972ALC.A4SE001 |
| 厂家： | 
INTEL |
| 描述： | Ethernet Transceiver, CMOS, PQFP64, LEAD FREE, LQFP-64 |
| 文件： | 总100页 (文件大小：1046K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® LXT972A
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Datasheet
The LXT972A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs).
This document also supports the LXT972.
The LXT972A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition
can be set using auto-negotiation, parallel detection, or manual control.
The LXT972A is fabricated with an advanced CMOS process and requires only a single 3.3 V
power supply.
Applications
■ Combination 10BASE-T/100BASE-TX
■ 10/100 PCMCIA Cards
■ Cable Modems and Set-Top Boxes
Network Interface Cards (NICs)
Product Features
■ 3.3 V Operation.
■ Standard CSMA/CD or full-duplex
operation.
■ Low power consumption (300 mW
typical).
■ Configurable via MDIO serial port or
hardware control pins.
■ 10BASE-T and 100BASE-TX using a
single RJ-45 connection.
■ Integrated, programmable LED drivers.
■ Supports auto-negotiation and parallel
■ 64-pin Low-profile Quad Flat Package
detection.
(LQFP).
■ MII interface with extended register
—LXT972ALC - Commercial (0° to 70°C
capability.
ambient).
■ Robust baseline wander correction
performance.
■ Supports JTAG Boundary Scan
Order Number: 249186-003
August 2002
.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELÆ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S
TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY
EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition
and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT972A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized
errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2002
*Third-party brands and names are the property of their respective owners.
2
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Contents
1.0
2.0
3.0
Pin Assignments .............................................................................................................................10
Signal Descriptions ........................................................................................................................13
Functional Description ..................................................................................................................17
3.1
Introduction .......................................................................................................................17
3.1.1
3.1.2
Comprehensive Functionality .............................................................................17
OSP™ Architecture ............................................................................................17
3.2
Network Media / Protocol Support....................................................................................18
3.2.1
10/100 Network Interface ...................................................................................18
3.2.1.1 Twisted-Pair Interface ..........................................................................18
3.2.1.2 Fault Detection and Reporting..............................................................18
MII Data Interface...............................................................................................19
3.2.2.1 Increased MII Drive Strength...............................................................19
Configuration Management Interface .................................................................19
3.2.3.1 MDIO Management Interface ..............................................................19
3.2.3.2 MII Interrupts .......................................................................................20
3.2.3.3 Hardware Control Interface..................................................................20
3.2.2
3.2.3
3.3
3.4
Operating Requirements....................................................................................................21
3.3.1
3.3.2
Power Requirements ...........................................................................................21
Clock Requirements............................................................................................21
3.3.2.1 External Crystal/Oscillator ...................................................................21
3.3.2.2 MDIO Clock.........................................................................................21
Initialization.......................................................................................................................22
3.4.1
3.4.2
3.4.3
MDIO Control Mode ..........................................................................................22
Hardware Control Mode .....................................................................................22
Reduced Power Modes........................................................................................23
3.4.3.1 Hardware Power Down ........................................................................23
3.4.3.2 Software Power Down..........................................................................24
Reset....................................................................................................................24
Hardware Configuration Settings........................................................................24
3.4.4
3.4.5
3.5
3.6
Establishing Link...............................................................................................................25
3.5.1
Auto-Negotiation ................................................................................................25
3.5.1.1 Base Page Exchange.............................................................................25
3.5.1.2 Next Page Exchange.............................................................................25
3.5.1.3 Controlling Auto-Negotiation...............................................................26
Parallel Detection................................................................................................26
3.5.2
MII Operation....................................................................................................................26
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
MII Clocks ..........................................................................................................27
Transmit Enable ..................................................................................................27
Receive Data Valid .............................................................................................27
Carrier Sense.......................................................................................................27
Error Signals .......................................................................................................27
Collision..............................................................................................................27
Loopback.............................................................................................................29
3.6.7.1 Operational Loopback ..........................................................................29
3.6.7.2 Test Loopback ......................................................................................29
Datasheet
3
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.7
100 Mbps Operation ......................................................................................................... 30
3.7.1
3.7.2
3.7.3
100BASE-X Network Operations...................................................................... 30
Collision Indication............................................................................................ 32
100BASE-X Protocol Sublayer Operations ....................................................... 32
3.7.3.1 PCS Sublayer ....................................................................................... 33
3.7.3.2 PMA Sublayer...................................................................................... 35
3.7.3.3 Twisted-Pair PMD Sublayer................................................................ 36
3.8
10 Mbps Operation ........................................................................................................... 36
3.8.1
3.8.2
3.8.3
3.8.4
10BASE-T Preamble Handling.......................................................................... 37
10BASE-T Carrier Sense ................................................................................... 37
10BASE-T Dribble Bits ..................................................................................... 37
10BASE-T Link Integrity Test........................................................................... 37
3.8.4.1 Link Failure.......................................................................................... 37
10T SQE (Heartbeat).......................................................................................... 38
10T Jabber.......................................................................................................... 38
10T Polarity Correction...................................................................................... 38
3.8.5
3.8.6
3.8.7
3.9
Monitoring Operations ..................................................................................................... 38
3.9.1
3.9.2
Monitoring Auto-Negotiation ............................................................................ 38
3.9.1.1 Monitoring Next Page Exchange......................................................... 38
LED Functions ................................................................................................... 39
3.9.2.1 LED Pulse Stretching........................................................................... 39
3.10
Boundary Scan (JTAG1149.1) Functions ........................................................................ 40
3.10.1 Boundary Scan Interface .................................................................................... 40
3.10.2 State Machine.................................................................................................... 40
3.10.3 Instruction Register ............................................................................................ 40
3.10.4 Boundary Scan Register (BSR).......................................................................... 40
4.0
5.0
Application Information............................................................................................................... 42
4.1
4.2
Magnetics Information ..................................................................................................... 42
Typical Twisted-Pair Interface ......................................................................................... 42
Test Specifications......................................................................................................................... 45
5.1
5.2
Electrical Parameters ........................................................................................................ 45
Timing Diagrams.............................................................................................................. 49
6.0
7.0
8.0
Register Definitions....................................................................................................................... 57
Package Specification ................................................................................................................... 73
Product Ordering Information.................................................................................................... 74
4
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figures
1
LXT972A Block Diagram...................................................................................................9
LXT972A 64-Pin LQFP Assignments ..............................................................................10
Management Interface Read Frame Structure ..................................................................20
Management Interface Write Frame Structure .................................................................20
Interrupt Logic ..................................................................................................................21
Initialization Sequence .....................................................................................................23
Hardware Configuration Settings .....................................................................................24
Link Establishment Overview ..........................................................................................26
10BASE-T Clocking ........................................................................................................28
100BASE-X Clocking ......................................................................................................28
Link Down Clock Transition ............................................................................................28
Loopback Paths ................................................................................................................29
100BASE-X Frame Format ..............................................................................................30
100BASE-TX Data Path ...................................................................................................31
100BASE-TX Reception with no Errors ..........................................................................31
100BASE-TX Reception with Invalid Symbol ................................................................32
100BASE-TX Transmission with no Errors .....................................................................32
100BASE-TX Transmission with Collision .....................................................................32
Protocol Sublayers ............................................................................................................33
LED Pulse Stretching .......................................................................................................40
Typical Twisted-Pair Interface - Switch............................................................................43
Typical Twisted-Pair Interface - NIC ...............................................................................44
Typical MII Interface .......................................................................................................44
100BASE-TX Receive Timing - 4B Mode ......................................................................49
100BASE-TX Transmit Timing - 4B Mode .....................................................................50
10BASE-T Receive Timing .............................................................................................51
10BASE-T Transmit Timing ............................................................................................52
10BASE-T Jabber and Unjabber Timing .........................................................................53
10BASE-T SQE (Heartbeat) Timing ................................................................................53
Auto Negotiation and Fast Link Pulse Timing .................................................................54
Fast Link Pulse Timing ....................................................................................................54
MDIO Input Timing .........................................................................................................55
MDIO Output Timing .......................................................................................................55
Power-Up Timing .............................................................................................................56
RESET Pulse Width and Recovery Timing .....................................................................56
PHY Identifier Bit Mapping .............................................................................................62
LXT972A LQFP Package Specifications .........................................................................73
Ordering Information - Sample .........................................................................................74
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Tables
1
2
3
4
5
6
7
LQFP Numeric Pin List....................................................................................................11
LXT972A MII Signal Descriptions...................................................................................13
LXT972A Network Interface Signal Descriptions............................................................14
LXT972A Miscellaneous Signal Descriptions..................................................................14
LXT972A Power Supply Signal Descriptions ..................................................................15
LXT972A JTAG Test Signal Descriptions .......................................................................15
LXT972A LED Signal Descriptions .................................................................................16
Datasheet
5
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
8
LXT972A Pin Types and Modes...................................................................................... 16
9
Hardware Configuration Settings ..................................................................................... 25
Carrier Sense, Loopback, and Collision Conditions......................................................... 29
4B/5B Coding................................................................................................................... 34
BSR Mode of Operation................................................................................................... 41
Supported JTAG Instructions ........................................................................................... 41
Device ID Register ........................................................................................................... 41
Magnetics Requirements .................................................................................................. 42
RJ-45 Pin Comparison of NIC and Switch Twisted-Pair Interfaces ................................ 42
Absolute Maximum Ratings............................................................................................. 45
Operating Conditions........................................................................................................ 45
Digital I/O Characteristics1.............................................................................................. 46
Digital I/O Characteristics - MII Pins............................................................................... 46
I/O Characteristics - REFCLK/XI and XO Pins............................................................... 46
I/O Characteristics - LED/CFG Pins ................................................................................ 47
100BASE-TX Transceiver Characteristics....................................................................... 47
10BASE-T Transceiver Characteristics............................................................................ 47
10BASE-T Link Integrity Timing Characteristics ........................................................... 48
LXT972A Thermal Characteristics .................................................................................. 48
100BASE-TX Receive Timing Parameters - 4B Mode.................................................... 49
100BASE-TX Transmit Timing Parameters - 4B Mode.................................................. 50
10BASE-T Receive Timing Parameters........................................................................... 51
10BASE-T Transmit Timing Parameters ......................................................................... 52
10BASE-T Jabber and Unjabber Timing Parameters....................................................... 53
10BASE-T SQE Timing Parameters ................................................................................ 53
Auto Negotiation and Fast Link Pulse Timing Parameters .............................................. 54
MDIO Timing Parameters................................................................................................ 55
Power-Up Timing Parameters ......................................................................................... 56
RESET Pulse Width and Recovery Timing Parameters.................................................. 56
Register Set....................................................................................................................... 57
Register Bit Map............................................................................................................... 58
Control Register (Address 0)............................................................................................ 60
MII Status Register #1 (Address 1) .................................................................................. 61
PHY Identification Register 1 (Address 2)....................................................................... 62
PHY Identification Register 2 (Address 3)....................................................................... 62
Auto Negotiation Advertisement Register (Address 4).................................................... 63
Auto Negotiation Link Partner Base Page Ability Register (Address 5) ......................... 64
Auto Negotiation Expansion (Address 6)......................................................................... 65
Auto Negotiation Next Page Transmit Register (Address 7) ........................................... 65
Auto Negotiation Link Partner Next Page Receive Register (Address 8)........................ 66
Configuration Register (Address 16, Hex 10).................................................................. 66
Status Register #2 (Address 17) ....................................................................................... 67
Interrupt Enable Register (Address 18)............................................................................ 68
Interrupt Status Register (Address 19, Hex 13)................................................................ 68
LED Configuration Register (Address 20, Hex 14) ......................................................... 70
Digital Config Register (Address 26)............................................................................... 71
Transmit Control Register #2 (Address 30) ..................................................................... 72
Product Information.......................................................................................................... 74
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
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48
49
50
51
52
53
54
55
6
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Revision History
Revision 003
Revision Date: August 6, 2002
Page #
Description
1
Added “JTAG Boundary Scan” to Product Features on front page.
Modified Figure 2 “LXT972A 64-Pin LQFP Assignments” (replaced TEST1 and TEST0 with
GND).
10
11
13
Modified Table 1 “LQFP Numeric Pin List” (replaced TEST1 and TEST0 with GND).
Added note under Section 2.0, “Signal Descriptions”: “Intel recommends that all inputs and
multi-function pins be tied to the inactive states and all outputs be left floating, if unused.”
14
15
16
19
24
41
41
45
45
46
47
48
51
58
71
72
74
Modified Table 4 “LXT972A Miscellaneous Signal Descriptions”.
Modified Table 5 “LXT972A Power Supply Signal Descriptions”.
Added Table 8 “LXT972A Pin Types and Modes”.
Added Section 3.2.2.1, “Increased MII Drive Strength”.
Modified Figure 7 “Hardware Configuration Settings”.
Modified Table 13 “Supported JTAG Instructions”.
Modified Table 14 “Device ID Register”.
Modified Table 17 “Absolute Maximum Ratings”.
Modified Table 18 “Operating Conditions”: Added Typ values to Vcc current.
Modified Table 20 “Digital I/O Characteristics - MII Pins”.
Modified Table 22 “I/O Characteristics - LED/CFG Pins”.
Added Table 26 “LXT972A Thermal Characteristics”.
Modified Table 29 “10BASE-T Receive Timing Parameters”.
Modified Table 38 “Register Bit Map” (added Address 26 information).
Added Table 53 “Digital Config Register (Address 26)”.
Modified Table 54 “Transmit Control Register #2 (Address 30)”.
Added Section 8.0, “Product Ordering Information”.
Revision 002
Revision Date: January 2001
Page #
Description
N/A
Clock Requirements: Modified language under Clock Requirements heading.
I/O Characteristics REFCLK (table): Changed values for Input Clock Duty Cycle under Min from 40
to 35 and under Max from 60 to 65.
Datasheet
7
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
8
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 1. LXT972A Block Diagram
RESET
VCC
Pwr Supply
GND
Management /
Mode Select
Logic
ADDR0
MDIO
PWRDWN
Register Set
REFCLK
Clock
MDC
Generator
MDINT
TxSLEW<1:0>
MDDIS
+
-
Manchester
Encoder
TX_EN
TXD<3:0>
TX_ER
10
TP
OSP™
Driver
TPOP
TPON
Pulse
Parallel/Serial
Converter
Scrambler
& Encoder
100
Shaper
TP Out
JTAG
TX_CLK
Auto
Negotiation
TDI,
Register
Set
TDO,
TMS,
TCK,
TRST
LED/CFG<3:1>
COL
OSP™
Adaptive EQ with
Baseline Wander
Cancellation
Collision
Detect
+
-
Media
Select
Clock
100TX
10BT
Generator
RX_CLK
RXD<3:0>
RXDV
TPIP
TPIN
Manchester
Serial-to-
Parallel
TP In
10
Decoder
OSP™
Slicer
Converter
Decoder &
Carrier Sense
100
CRS
+
-
Descrambler
Data Valid
Error Detect
RX_ER
Datasheet
9
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
1.0
Pin Assignments
Figure 2. LXT972A 64-Pin LQFP Assignments
48 RXD0
1
2
3
4
5
6
7
8
REFCLK/XI
XO
MDDIS
RESET
TXSLEW0
TXSLEW1
GND
RXD1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RXD2
RXD3
N/C
MDC
MDIO
GND
VCCIO
N/C
N/C
GND
ADDR0
GND
Part # LXT972A XX
LOT # XXXXXX
FPO # XXXXXXXX
Rev #
VCCIO
PWRDWN
LED/CFG1
LED/CFG2
LED/CFG3
GND
9
10
11
12
13
14
15
16
GND
GND
GND
GND
PAUSE
Package Topside Markings
Marking
Definition
LXT972A is the unique identifier for this product family.
Part #
Identifies the particular silicon “stepping” (Refer to Specification Update for additional stepping
information.)
Rev #
Lot #
Identifies the batch.
FPO #
Identifies the Finish Process Order.
10
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 1.
LQFP Numeric Pin List
Reference for
Pin
Symbol
Type
Full Description
1
REFCLK/XI
XO
Input
Table 4 on page 14
Table 4 on page 14
Table 2 on page 13
Table 4 on page 14
Table 4 on page 14
Table 4 on page 14
Table 5 on page 15
Table 5 on page 15
Table 4 on page 14
Table 4 on page 14
Table 5 on page 15
Table 4 on page 14
Table 5 on page 15
Table 5 on page 15
Table 5 on page 15
Table 5 on page 15
2
Output
3
MDDIS
RESET
TxSLEW0
TxSLEW1
GND
Input
4
Input
5
Input
6
Input
7
–
8
VCCIO
N/C
–
9
–
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
N/C
–
GND
–
ADDR0
GND
Input
–
–
–
–
GND
GND
GND
RBIAS
GND
Analog Input Table 4 on page 14
–
Output
Output
–
Table 5 on page 15
Table 3 on page 14
Table 3 on page 14
Table 5 on page 15
Table 5 on page 15
Table 3 on page 14
Table 3 on page 14
Table 5 on page 15
Table 5 on page 15
Table 6 on page 15
Table 6 on page 15
Table 6 on page 15
Table 6 on page 15
Table 6 on page 15
Table 5 on page 15
Table 4 on page 14
Table 4 on page 14
Table 4 on page 14
Table 7 on page 16
TPOP
TPON
VCCA
VCCA
TPIP
–
Input
Input
–
TPIN
GND
GND
–
TDI
Input
Output
Input
Input
Input
–
TDO
TMS
TCK
TRST
GND
PAUSE
GND
Input
–
GND
–
LED/CFG3
I/O
Datasheet
11
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 1.
LQFP Numeric Pin List (Continued)
Reference for
Pin
Symbol
Type
Full Description
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
LED/CFG2
LED/CFG1
PWRDWN
VCCIO
GND
I/O
I/O
Table 7 on page 16
Table 7 on page 16
Table 4 on page 14
Table 5 on page 15
Table 5 on page 15
Table 2 on page 13
Table 2 on page 13
Table 4 on page 14
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Table 5 on page 15
Table 5 on page 15
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Table 5 on page 15
Table 2 on page 13
Table 2 on page 13
Table 2 on page 13
Input
–
–
MDIO
MDC
I/O
Input
–
N/C
RXD3
Output
Output
Output
Output
Output
–
RXD2
RXD1
RXD0
RX_DV
GND
VCCD
RX_CLK
RX_ER
TX_ER
TX_CLK
TX_EN
TXD0
–
Output
Output
Input
Output
Input
Input
Input
Input
Input
–
TXD1
TXD2
TXD3
GND
COL
Output
Output
Open Drain
CRS
MDINT
12
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
2.0
Signal Descriptions
Intel recommends that all inputs and multi-function pins be tied to the inactive states and all
outputs be left floating, if unused.
Table 2. LXT972A MII Signal Descriptions
LQFP
Symbol
Type1
Signal Description
Pin#
Data Interface Pins
60
59
58
57
TXD3
Transmit Data. TXD is a bundle of parallel data signals that are driven by the
MAC. TXD<3:0> shall transition synchronously with respect to the TX_CLK.
TXD<0> is the least significant bit.
TXD2
TXD1
TXD0
I
Transmit Enable. The MAC asserts this signal when it drives valid data on
56
55
TX_EN
I
TXD. This signal must be synchronized to TX_CLK.
Transmit Clock. TX_CLK is sourced by the PHY in both 10 and 100 Mbps
TX_CLK
O
operations. 2.5 MHz for 10 Mbps operation, 25 MHz for 100 Mbps operation.
45
46
47
48
RXD3
RXD2
RXD1
RXD0
Receive Data. RXD is a bundle of parallel signals that transition synchronously
O
with respect to the RX_CLK. RXD<0> is the least significant bit.
Receive Data Valid. The LXT972A asserts this signal when it drives valid data
49
53
54
RX_DV
RX_ER
TX_ER
O
O
I
on RXD. This output is synchronous to RX_CLK.
Receive Error. Signals a receive error condition has occurred. This output is
synchronous to RX_CLK.
Transmit Error. Signals a transmit error condition. This signal must be
synchronized to TX_CLK.
Receive Clock. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps
operation. Refer to “Clock Requirements” on page 21 in the Functional
Description section.
52
62
RX_CLK
COL
O
O
Collision Detected. The LXT972A asserts this output when a collision is
detected. This output remains High for the duration of the collision. This signal
is asynchronous and is inactive during full-duplex operation.
Carrier Sense. During half-duplex operation (bit 0.8 = 0), the LXT972A asserts
this output when either transmitting or receiving data packets. During full-
duplex operation (bit 0.8 = 1), CRS is asserted during receive. CRS assertion is
asynchronous with respect to RX_CLK. CRS is de-asserted on loss of carrier,
synchronous to RX_CLK.
63
CRS
O
MII Control Interface Pins
Management Disable. When MDDIS is High, the MDIO is disabled from read
and write operations.
When MDDIS is Low at power up or reset, the Hardware Control Interface pins
control only the initial or “default” values of their respective register bits. After
the power-up/reset cycle is complete, bit control reverts to the MDIO serial
channel.
3
MDDIS
I
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
Datasheet
13
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 2. LXT972A MII Signal Descriptions (Continued)
LQFP
Symbol
MDC
Type1
Signal Description
Pin#
Management Data Clock. Clock for the MDIO serial data channel. Maximum
43
I
frequency is 8 MHz.
Management Data Input/Output. Bidirectional serial data channel for PHY/
42
64
MDIO
I/O
OD
STA communication.
Management Data Interrupt. When bit 18.1 = 1, an active Low output on this
MDINT
pin indicates status change. Interrupt is cleared by reading Register 19.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
Table 3. LXT972A Network Interface Signal Descriptions
LQFP
Symbol
Type1
Signal Description
Pin#
Twisted-Pair Outputs, Positive & Negative.
19
20
TPOP
TPON
O
During 100BASE-TX or 10BASE-T operation, TPOP/N pins drive 802.3
compliant pulses onto the line.
Twisted-Pair Inputs, Positive & Negative.
23
24
TPIP
TPIN
I
During 100BASE-TX or 10BASE-T operation, TPIP/N pins receive
differential 100BASE-TX or 10BASE-T signals from the line.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
Table 4. LXT972A Miscellaneous Signal Descriptions
LQFP
Symbol
Type1
Signal Description
Pin#
Tx Output Slew Controls 0 and 1. These pins select the TX output slew
rate (rise and fall time) as follows:
TxSLEW1
TxSLEW0
Slew Rate (Rise and Fall Time)
5
6
TxSLEW0
TxSLEW1
0
0
1
1
0
1
0
1
3.0 ns
3.4 ns
3.9 ns
4.4 ns
I
Reset. This active Low input is OR’ed with the control register Reset bit
(0.15). The LXT972A reset cycle is extended to 258 µs (nominal) after
reset is deasserted.
4
RESET
I
12
17
ADDR0
RBIAS
I
Address0. Sets device address.
Bias. This pin provides bias current for the internal circuitry. Must be tied
to ground through a 22.1 kΩ, 1% resistor.
AI
Pause. When set High, the LXT972A advertises Pause capabilities during
33
PAUSE
I
auto negotiation.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 4. LXT972A Miscellaneous Signal Descriptions (Continued)
LQFP
Pin#
Symbol
Type1
Signal Description
Power Down. When set High, this pin puts the LXT972A in a power-
39
PWRDWN
I
down mode.
Crystal Input and Output. A 25 MHz crystal oscillator circuit can be
connected across XI and XO. A clock can also be used at XI. Refer to
Functional Description for detailed clock requirements.
1
2
REFCLK/XI
XO
I
O
9, 10,
44
N/C
-
No Connection. These pins are not used and should not be terminated.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
Table 5. LXT972A Power Supply Signal Descriptions
LQFP
Symbol
VCCD
Type
Signal Description
Pin#
51
-
Digital Power. Requires a 3.3 V power supply.
7, 11, 13,
14, 15, 16,
18, 25, 26, GND
32, 34, 35,
-
Ground.
41, 50, 61
MII Power. Requires either a 3.3 V or a 2.5 V supply. Must be supplied
8, 40
VCCIO
VCCA
-
-
from the same source used to power the MAC on the other side of the MII.
21, 22
Analog Power. Requires a 3.3 V power supply.
Table 6. LXT972A JTAG Test Signal Descriptions
LQFP
Symbol
TDI2
TDO2
TMS2
TCK2
TRST2
Type1
Signal Description
Pin#
27
28
29
30
31
I
O
I
Test Data Input. Test data sampled with respect to the rising edge of TCK.
Test Data Output. Test data driven with respect to the falling edge of TCK.
Test Mode Select.
I
Test Clock. Test clock input sourced by ATE.
I
Test Reset. Test reset input sourced by ATE.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
2. If JTAG port is not used, these pins do not need to be terminated.
Table 7. LXT972A LED Signal Descriptions
LQFP
Pin#
Symbol
Type1
Signal Description
LED Drivers 1 -3. These pins drive LED indicators. Each LED can
display one of several available status conditions as selected by the LED
Configuration Register (refer to Table 52 on page 70 for details).
38
37
36
LED/CFG1
LED/CFG2
LED/CFG3
I/O
Configuration Inputs 1-3. These pins also provide initial configuration
settings (refer to Table 9 on page 25 for details).
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 8. LXT972A Pin Types and Modes
Tx/Rx
RXER
COL
CRS
TXD 0-3
Input
TXEN
Input
TXER
Input
Modes
RXD 0-3
RXDV
CLKS
Output Output Output
Output
HWReset
DL
DL
DH
DL
DL
DL
DL
DL
DL
IPLD
IPLD
IPLD
SFTPWRDN DL
DL
Active
High Z
IPLD
IPLD
IPLD
HWPWRDN
High Z
High Z
High Z High Z High Z
High Z
High Z
High Z
HZ w/
IPLD
HZ w/
IPLD
HZ w/
IPLD
HZ w/
IPLD
HZ w/
IPLD
HZ w/
IPLD
ISOLATE
IPLD
IPLD
IPLD
1. A High Z (High impedance) or three state determines when the device is drawing a current of less than
20 nA. A High Z with PLD (High impedance with pull-down) state determines when the device is drawing a
current of less than 20 uA.
2. DL = Driven Low (Logic 0), DH = Driven High (Logic 1), IPLD = Internal Pull-Down (Weak)
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.0
Functional Description
3.1
Introduction
The LXT972A is a single-port Fast Ethernet 10/100 Transceiver that supports 10 Mbps and
100 Mbps networks. It complies with all applicable requirements of IEEE 802.3. The LXT972A
can directly drive either a 100BASE-TX line (up to 140 meters) or a 10BASE-T line (up to 185
meters).
3.1.1
Comprehensive Functionality
The LXT972A provides a standard Media Independent Interface (MII) for 10/100 MACs. The
LXT972A performs all functions of the Physical Coding Sublayer (PCS) and Physical Media
Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X standard. This device also
performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX
connections.
On power-up, the LXT972A reads its configuration pins to check for forced operation settings. If
not configured for forced operation, it uses auto-negotiation/parallel detection to automatically
determine line operating conditions. If the PHY device on the other side of the link supports auto-
negotiation, the LXT972A auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY
partner does not support auto-negotiation, the LXT972A automatically detects the presence of
either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions
accordingly.
The LXT972A provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.
3.1.2
OSP™ Architecture
Intel's LXT972A incorporates high-efficiency Optimal Signal Processing™ design techniques,
combining the best properties of digital and analog signal processing to produce a truly optimal
device.
The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by
as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques
in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results
in improved receiver noise and cross-talk performance.
The OSP signal processing scheme also requires substantially less computational logic than
traditional DSP-based designs. This lowers power consumption and also reduces the logic
switching noise generated by DSP engines. This logic switching noise can be a considerable source
of EMI generated on the device’s power supplies.
The OSP-based LXT972A provides improved data recovery, EMI performance and low power
consumption.
Datasheet
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.2
Network Media / Protocol Support
The LXT972A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair.
3.2.1
10/100 Network Interface
The network interface port consists of two differential signal pairs. Refer to Table 3 for specific pin
assignments.
The LXT972A output drivers generate either 100BASE-TX or 10BASE-T. When not transmitting
data, the LXT972A generates 802.3-compliant link pulses or idle code. Input signals are decoded
either as a 100BASE-TX or 10BASE-T input, depending on the mode selected. Auto-negotiation/
parallel detection or manual control is used to determine the speed of this interface.
3.2.1.1
Twisted-Pair Interface
The LXT972A supports either 100BASE-TX or 10BASE-T connections over 100 Ω, Category 5,
Unshielded Twisted Pair (UTP) cable. When operating at 100 Mbps, the LXT972A continuously
transmits and receives MLT3 symbols. When not transmitting data, the LXT972A generates
“IDLE” symbols.
During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being
exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link
up.
Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete
this interface. On the transmit side, the LXT972A has an active internal termination and does not
require external termination resistors. Intel's patented waveshaping technology shapes the outgoing
signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 4 on
page 14) allow the designer to match the output waveform to the magnetic characteristics. On the
receive side, the internal impedance is high enough that it has no practical effect on the external
termination circuit.
3.2.1.2
Fault Detection and Reporting
The LXT972A supports one fault detection and reporting mechanism. “Remote Fault” refers to a
MAC-to-MAC communication function that is essentially transparent to PHY layer devices. It is
used only during Auto-Negotiation, and therefore is applicable only to twisted-pair links. “Far-End
Fault” is an optional PMA-layer function that may be embedded within PHY devices. The
LXT972A supports only the Remote Fault Function, explained in the paragraph that follows.
Remote Fault
Register bit 4.13 in the Auto-Negotiation Advertisement Register is reserved for Remote Fault
indications. It is typically used when re-starting the auto-negotiation sequence to indicate to the
link partner that the link is down because the advertising device detected a fault.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
When the LXT972A receives a Remote Fault indication from its partner during auto-negotiation it
does the following:
• Sets Register bit 5.13 in the Link Partner Base Page Ability Register, and
• Sets the Remote Fault Register bit 1.4 in the MII Status Register to pass this information to the
local controller.
3.2.2
MII Data Interface
The LXT972A supports a standard Media Independent Interface (MII). The MII consists of a data
interface and a management interface. The MII Data Interface passes data between the LXT972A
and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and
receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set automatically,
once the operating conditions of the network link have been determined. Refer to “MII Operation”
on page 26 for additional details.
3.2.2.1
Increased MII Drive Strength
A higher Media Independent Interface (MII) drive strength may be desired in some designs to drive
signals over longer PCB trace lengths, or over high-capacitive loads, through multiple vias, or
through a connector. The MII drive strength in the LXT971A can be increased by setting Register
bit 26.11 through software control. Setting Register bit 26.11 = 1 through the MDC/MDIO
interface sets the MII pins (RXD[0:3], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a
higher drive strength.
3.2.3
Configuration Management Interface
The LXT972A provides both an MDIO interface and a Hardware Control Interface for device
configuration and management.
3.2.3.1
MDIO Management Interface
The LXT972A supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT972A. The MDIO interface consists of a physical
connection, a specific protocol that runs across the connection, and an internal set of addressable
registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard. The
LXT972A also supports additional registers for expanded functionality. The LXT972A supports
multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using
an “X.Y” notation, where X is the register number (0-31) and Y is the bit number (0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write
operations are disabled and the Hardware Control Interface provides primary configuration control.
When MDDIS is Low, the MDIO port is enabled for both read and write operations and the
Hardware Control Interface is not used.
Datasheet
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Document #: 249186
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Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
MDIO Addressing
The protocol allows one controller to communicate between two LXT972A chips. Pin ADDR0 is
set high or low to determine the chip address.
MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is
shown in Figure 3 and Figure 4 (read and write). MDIO Interface timing is shown in Table 34 on
page 55.
Figure 3. Management Interface Read Frame Structure
MDC
MDIO
(Read)
High Z
D0
A4
A3
A0
R4
R3
R0
D14
D15
D1
Z
0
32 "1"s
0
1
1
0
Turn
Around
Data
Read
Idle
Preamble
ST
Op Code
PHY Address
Register Address
Write
Figure 4. Management Interface Write Frame Structure
MDC
MDIO
A4
A3
A0
R4
R3
R0
D15
D14
D1
D0
32 "1"s
0
1
0
1
0
1
(Write)
Turn
Around
Idle
Preamble
ST
Op Code
PHY Address
Register Address
Data
Idle
Write
3.2.3.2
MII Interrupts
The LXT972A provides a single interrupt pin (MDINT). Interrupt logic is shown in Figure 5. The
LXT972A also provides two dedicated interrupt registers. Register 18 provides interrupt enable
and mask functions and Register 19 provides interrupt status. Setting bit 18.1 = 1, enables the
device to request interrupt via the MDINT pin. An active Low on this pin indicates a status change
on the LXT972A. Interrupts may be caused by four conditions:
• Auto-negotiation complete
• Speed status change
• Duplex status change
• Link status change
3.2.3.3
Hardware Control Interface
The LXT972A provides a Hardware Control Interface for applications where the MDIO is not
desired. The Hardware Control Interface uses the three LED driver pins to set device configuration.
Refer to Section 3.4.5, “Hardware Configuration Settings” on page 24 for additional details.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 5. Interrupt Logic
Event X Mask Reg
AND
Event X Status Reg
OR
Interrupt Pin (MDINT)
NAND
.
.
.
Per Event
Force Interrupt
Interrupt Enable
1. Interrupt (Event) Status Register is cleared on read.
3.3
Operating Requirements
3.3.1
Power Requirements
The LXT972A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and
analog circuits require 3.3 V supplies (VCCD and VCCA). These inputs may be supplied from a
single source. Each supply input must be decoupled to ground.
An additional supply may be used for the MII (VCCIO). The supply may be either +2.5 V or
+3.3 V. The inputs on the MII interface are tolerant to 5 V signals from the controller on the other
side of the MII interface. Refer to Table 20 on page 46 for MII I/O characteristics.
As a matter of good practice, these supplies should be as clean as possible.
3.3.2
Clock Requirements
3.3.2.1
External Crystal/Oscillator
The LXT972A requires a reference clock input that is used to generate transmit signals and recover
receive signals. It may be provided by either of two methods: by connecting a crystal across the
oscillator pins (XI and XO), or by connecting an external clock source to pin XI. The connection of
a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is
recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to the
LXT971A/972A Design and Layout Guide for a list of recommended clock sources.
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a
crystal, is frequently used in switch applications. Refer to Table 21 on page 46 for clock timing
requirements
3.3.2.2
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock
(MDC) speed is a maximum of 8 MHz. Refer to Table 34 on page 55 for details.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.4
Initialization
When the LXT972A is first powered on, reset, or encounters a link failure state, it checks the
MDIO register configuration bits to determine the line speed and operating conditions to use for
the network link. The configuration bits may be set by the Hardware Control or MDIO interface as
shown in Figure 6.
3.4.1
3.4.2
MDIO Control Mode
In the MDIO Control mode, the LXT972A reads the Hardware Control Interface pins to set the
initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to
the MDIO interface.
Hardware Control Mode
In the Hardware Control Mode, LXT972A disables direct write operations to the MDIO registers
via the MDIO Interface. On power-up or hardware reset the LXT972A reads the Hardware Control
Interface pins and sets the MDIO registers accordingly.
The following modes are available using either Hardware Control or MDIO Control:
• Force network link operation to:
100BASE-TX, Full-Duplex
100BASE-TX, Half-Duplex
10BASE-T, Full-Duplex
10BASE-T, Half-Duplex
• Allow auto-negotiation/parallel-detection
When the network link is forced to a specific configuration, the LXT972A immediately begins
operating the network interface as commanded. When auto-negotiation is enabled, the LXT972A
begins the auto-negotiation/parallel-detection operation.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 6. Initialization Sequence
Power-up or Reset
Read H/W Control
Interface
Initialize MDIO Registers
MDIO Control
Mode
Hardware Control
Mode
MDDIS Voltage
Level?
Low
High
MDIO Controlled Operation
(MDIO Writes Enabled)
Disable MDIO Read and
Write Operations
No
Software
Reset?
Yes
Reset MDIO Registers to
values read at H/W
Control Interface at last
Hardware Reset
3.4.3
Reduced Power Modes
The LXT972A offers two power-down modes.
3.4.3.1
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High,
the following conditions are true:
• The LXT972A network port and clock are shut down.
• All outputs are three-stated.
• All weak pad pull-up and pull-down resistors are disabled.
• The MDIO registers are not accessible.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.4.3.2
Software Power Down
Software power-down control is provided by bit 0.11 in the Control Register (refer to Table 39 on
page 60). During soft power-down, the following conditions are true:
• The network port is shut down.
• The MDIO registers remain accessible.
3.4.4
Reset
The LXT972A provides both hardware and software resets. Configuration control of auto-
negotiation, speed, and duplex mode selection is handled differently for each. During a hardware
reset, auto-negotiation and speed are read in from pins (refer to Table 9 on page 25 for pin settings
and to Table 39 on page 60 for register bit definitions).
During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back
to the values that were read in during the last hardware reset. Therefore, any changes to pin values
made since the last hardware reset are not detected during a software reset.
During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset.
During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be
polled to see when the part has completed reset (0.15 = 0).
3.4.5
Hardware Configuration Settings
The LXT972A provides a hardware option to set the initial device configuration. The hardware
option uses the three LED driver pins. This provides three control bits, as listed in Table 9. The
LED drivers can operate as either open-drain or open-source circuits as shown in Figure 7.
.
Figure 7. Hardware Configuration Settings
3.3 V
Configuration Bit = 1
Configuration Bit = 0
LED/CFG Pin
LED/CFG Pin
1. The LED/CFG pins automatically adjust their
polarity upon power-up or reset.
2. Unused LEDs may be implemented with pull-up/
pull-down resistors of 10 K.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 9. Hardware Configuration Settings
Resulting Register Bit Values
LED/CFGn
Desired Mode
Pin Settings1
Control Register
Auto-Neg Advertisement
Speed
AutoNeg
Speed
0.13
FD
0.8
100FD
4.8
100TX
4.7
10FD
4.6
10T
4.5
Auto-Neg
Duplex
1
2
3
(Mbps)
0.12
Half
Full
Half
Full
Half
Full
Low Low Low
Low Low High
Low High Low
Low High High
High Low Low
High Low High
0
1
0
1
0
1
0
10
0
1
N/A
Auto-Negotiation Advertisement
Disabled
0
100
0
1
0
1
1
1
0
0
0
0
0
1
100 Only
Enabled
1
1
Half Only High High Low
10/100
Full or
High High High
Half
1
1
1
1
1
1. Refer to Table 7 on page 16 for LED/CFG pin assignments.
3.5
Establishing Link
See Figure 8 for an overview of link establishment.
3.5.1
Auto-Negotiation
If not configured for forced operation, the LXT972A attempts to auto-negotiate with its link
partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of up to 33 link pulses spaced
62.5 µs apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may
be present or absent to indicate a “1” or a “0”. Each FLP burst exchanges 16 bits of data, which are
referred to as a “link code word”. All devices that support auto-negotiation must implement the
“Base Page” defined by IEEE 802.3 (registers 4 and 5). LXT972A also supports the optional “Next
Page” function as described in Table 46 and Table 47 (registers 7 and 8).
3.5.1.1
3.5.1.2
Base Page Exchange
By exchanging Base Pages, the LXT972A and its link partner communicate their capabilities to
each other. Both sides must receive at least three identical base pages for negotiation to continue.
Each side identifies the highest common capabilities that both sides support and configures itself
accordingly.
Next Page Exchange
Additional information, above that required by base page exchange, is also sent via “Next Pages”.
The LXT972A fully supports the IEEE 802.3ab method of negotiation via Next Page exchange.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.5.1.3
Controlling Auto-Negotiation
When auto-negotiation is controlled by software, the following steps are recommended:
• After power-up, power-down, or reset, the power-down recovery time, as specified in Table 36
on page 56, must be exhausted before proceeding.
• Set the Auto-Negotiation Advertise Register bits.
• Enable auto-negotiation (set MDIO Register bit 0.12 = 1).
3.5.2
Parallel Detection
For the parallel detection feature of auto-negotiation, the LXT972A also monitors for 10BASE-T
Normal Link Pulses (NLP) and 100BASE-TX Idle symbols. If either is detected, the device
automatically reverts to the corresponding operating mode. Parallel detection allows the LXT972A
to communicate with devices that do not support auto-negotiation.
Figure 8. Link Establishment Overview
Power-Up, Reset,
or Link Failure
Start
Disable
Enable
0.12 = 0
0.12 = 1
Auto-Negotiation
Auto-Neg/Parallel Detection
Check Value
0.12
Go To Forced
Settings
Attempt Auto-
Negotiation
Listen for 100TX
Idle Symbols
Listen for 10T
Link Pulses
YES
NO
Done
Link Up?
3.6
MII Operation
The LXT972A device implements the Media Independent Interface (MII) as defined in the IEEE
802.3 standard. Separate channels are provided for transmitting data from the MAC to the
LXT972A (TXD), and for passing data received from the line (RXD) to the MAC. Each channel
has its own clock, data bus, and control signals. Nine signals are used to pass received data to the
MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL, and CRS. Seven signals are used to transmit
data from the MAC: TXD<3:0>, TX_CLK, TX_EN, and TX_ER.
The LXT972A supplies both clock signals as well as separate outputs for carrier sense and
collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.6.1
MII Clocks
The LXT972A is the master clock source for data transmission and supplies both MII clocks
(RX_CLK and TX_CLK). It automatically sets the clock speeds to match link conditions. When
the link is operating at 100 Mbps, the clocks are set to 25 MHz. When the link is operating at
10 Mbps, the clocks are set to 2.5 MHz. Figure 9 through Figure 11 show the clock cycles for each
mode. The transmit data and control signals must always be synchronized to TX_CLK by the
MAC. The LXT972A samples these signals on the rising edge of TX_CLK.
3.6.2
3.6.3
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN
after the last bit of the packet.
Receive Data Valid
The LXT972A asserts RX_DV when it receives a valid packet. Timing changes depend on line
operating speed:
• For 100TX links, RX_DV is asserted from the first nibble of preamble to the last nibble of the
data packet.
• For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the
Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
3.6.4
Carrier Sense
Carrier sense (CRS) is an asynchronous output. It is always generated when a packet is received
from the line and in half-duplex when a packet is transmitted.
Carrier sense is not generated when a packet is transmitted and in full-duplex mode. Table 10
summarizes the conditions for assertion of carrier sense, collision, and data loopback signals.
3.6.5
3.6.6
Error Signals
When LXT972A is in 100 Mbps mode and receives an invalid symbol from the network, it asserts
RX_ER and drives “1110” on the RXD pins.
When the MAC asserts TX_ER, the LXT972A drives “H” symbols out on the TPOP/N pins.
Collision
The LXT972A asserts its collision signal, asynchronously to any clock, whenever the line state is
half-duplex and the transmitter and receiver are active at the same time. Table 10 summarizes the
conditions for assertion of carrier sense, collision, and data loopback signals.
Datasheet
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 9. 10BASE-T Clocking
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
TX_CLK
(Sourced by LXT972A)
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
RX_CLK
(Sourced by LXT972A)
Constant 25 MHz
XI
Figure 10. 100BASE-X Clocking
25 MHz once 100BASE-X
2.5 MHz during auto-negotiation
2.5 MHz during auto-negotiation
Link Established
TX_CLK
(Sourced by LXT972A)
25 MHz once 100BASE-X
Link Established
RX_CLK
(Sourced by LXT972A)
Constant 25 MHz
XI
Figure 11. Link Down Clock Transition
Link Down condition/Auto Negotiate Enabled
2.5MHz Clock
RX_CLK
TX_CLK
Any Clock
Clock transition time will not exceed 2X the
nominal clock period: (10 Mbps = 2.5 MHz;
100 Mbps = 25 MHz)
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.6.7
Loopback
The LXT972A provides two loopback functions, operational and test (see Table 10). Loopback
paths are shown in Figure 12.
3.6.7.1
Operational Loopback
Operational loopback is provided for 10 Mbps half-duplex links when bit 16.8 = 0. Data
transmitted by the MAC (TXData) is looped back on the receive side of the MII (RXData).
Operational loopback is not provided for 100 Mbps links, full-duplex links, or when 16.8 = 1.
3.6.7.2
Test Loopback
A test loopback function is provided for diagnostic testing of the LXT972A. During test loopback,
the twisted-pair interface is disabled. Data transmitted by the MAC is internally looped back by the
LXT972A and returned to the MAC.
Test loopback is available for both 100TX and 10T operation. Test loopback is enabled by setting
bits as follows:
• 0.14 = 1
• 0.8 = 1 (full-duplex)
• 0.12 = 0 (disable auto-negotiation).
Figure 12. Loopback Paths
LXT972A
10T
Loopback
Digital
Block
100X
Analog
Block
MII
TX Driver
Loopback
Table 10. Carrier Sense, Loopback, and Collision Conditions
Test1
Operational
Speed
Duplex Condition
Full-Duplex
Half-Duplex
Carrier Sense
Collision
Loopback
Loopback
Receive Only
Yes
No
None
100 Mbps
Transmit and
Receive
Transmit or Receive
No
No
1. Test Loopback is enabled when Register bit 0.14 = 1
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 10. Carrier Sense, Loopback, and Collision Conditions (Continued)
Test1
Operational
Loopback
Speed
Duplex Condition
Carrier Sense
Receive Only
Collision
None
Loopback
Full-Duplex
Yes
No
Half-Duplex,
Transmit and
Receive
Transmit or Receive
Transmit or Receive
Yes
No
Yes
10 Mbps
Register bit 16.8 = 0
Half-Duplex,
Transmit and
Receive
No
Register bit 16.8 = 1
1. Test Loopback is enabled when Register bit 0.14 = 1
3.7
100 Mbps Operation
3.7.1
100BASE-X Network Operations
During 100BASE-X operation, the LXT972A transmits and receives 5-bit symbols across the
network link. Figure 13 shows the structure of a standard frame packet. When the MAC is not
actively transmitting data, the LXT972A sends out Idle symbols on the line.
In 100TX mode, the LXT972A scrambles and transmits the data to the network using MLT-3 line
code (Figure 14 on page 31). MLT-3 signals received from the network are descrambled, decoded,
and sent across the MII to the MAC.
Figure 13. 100BASE-X Frame Format
64-Bit Preamble
Destination and Source
Address (6 Octets each)
Packet Length
(2 Octets)
Data Field
Frame Check Field InterFrame Gap / Idle Code
(8 Octets)
(Pad to minimum packet size)
(4 Octets)
(> 12 Octets)
CRC
IFG
SFD
P0 P1 P6
DA DA SA SA L1
L2
D0 D1 Dn
I0
Replaced by
Replaced by
Start-of-Frame
Delimiter (SFD)
/T/R/ code-groups
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
End-of-Stream Delimiter (ESD)
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
.
Figure 14. 100BASE-TX Data Path
Standard Data Flow
+1
Parallel
D0
to
0
0
0
Serial
D1
Scramble
-1
4B/5B
MLT3
D0 D1 D2 D3
S0 S1 S2 S3 S4
De-
D2
D3
Transition = 1.
Serial
to
Scramble
No Transition = 0.
All transitions must follow
Parallel
pattern: 0, +1, 0, -1, 0, +1...
Scrambler Bypass Data Flow
S0
+1
Parallel
to
S1
0
0
0
Serial
-1
MLT3
S2
S0 S1 S2 S3 S4
Transition = 1.
Serial
S3
to
No Transition = 0.
All transitions must follow
Parallel
S4
pattern: 0, +1, 0, -1, 0, +1...
As shown in Figure 13 on page 30, the MAC starts each transmission with a preamble pattern. As
soon as the LXT972A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,
symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the SFD, packet data, and CRC.
Once the packet ends, the LXT972A transmits the End-of Stream-Delimiter (ESD, symbols T and
R) and then returns to transmitting Idle symbols. 4B/5B coding is shown in Table 11 on page 34.
Figure 15 shows normal reception with no errors. When the LXT972A receives invalid symbols
from the line, it asserts RX_ER as shown in Figure 16.
Figure 15. 100BASE-TX Reception with no Errors
RX_CLK
RX_DV
preamble SFD SFD DA DA DA DA
CRC
CRC
CRC
CRC
RXD<3:0>
RX_ER
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 16. 100BASE-TX Reception with Invalid Symbol
RX_CLK
RX_DV
preamble SFD SFD DA DA XX XX XX XX XX XX XX XX XX XX
RXD<3:0>
RX_ER
3.7.2
Collision Indication
Figure 17 shows normal transmission. Upon detection of a collision, the COL output is asserted
and remains asserted for the duration of the collision as shown in Figure 18.
Figure 17. 100BASE-TX Transmission with no Errors
TX_CLK
TX_EN
TXD<3:0>
CRS
P
R
E
A
M
B
L
E
DA DA DA DA DA DA DA DA DA
COL
Figure 18. 100BASE-TX Transmission with Collision
TX_CLK
TX_EN
TXD<3:0>
CRS
P
R
E
A
M
B
L
E
JAM
JAM
JAM
JAM
COL
3.7.3
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT972A is a Physical Layer 1 (PHY)
device. The LXT972A implements the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u standard. The following paragraphs discuss LXT972A operation from
the reference model point of view.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.7.3.1
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function.
For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver
as long as TX_EN is de-asserted.
Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-of-
Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues
to encode the remaining MII data, following the coding in Table 11 on page 34, until TX_EN is de-
asserted. It then returns to supplying IDLE symbols to the line driver.
In the receive direction, the PCS layer performs the opposite function, substituting two preamble
nibbles for the SSD.
Dribble Bits
The LXT972A handles dribbles bits in all modes. If between one through four dribble bits are
received, the nibble is passed across the MII, padded with 1s if necessary. If between five through
seven dribble bits are received, the second nibble is not sent onto the MII bus.
Figure 19. Protocol Sublayers
MII Interface
LXT972A
PCS
Encoder/Decoder
Sublayer
Serializer/De-serializer
PMA
Link/Carrier Detect
Sublayer
Scrambler/
PMD
De-scrambler
Sublayer
100BASE-TX
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 11. 4B/5B Coding
4B Code
5B Code
4 3 2 1 0
Code Type
Name
Interpretation
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
undefined
0
1
1 1 1 1 0
0 1 0 0 1
1 0 1 0 0
1 0 1 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 1 0
0 1 1 1 1
1 0 0 1 0
1 0 0 1 1
1 0 1 1 0
1 0 1 1 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 11
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
2
3
4
5
6
DATA
7
8
9
A
B
C
D
E
F
I 1
IDLE
Idle. Used as inter-stream fill code
Start-of-Stream Delimiter (SSD), part 1
of 2
0 1 0 1
0 1 0 1
J 2
K 2
T 3
R 3
H 4
1 1 0 0 0
1 0 0 0 1
0 1 1 0 1
0 0 1 1 1
0 0 1 0 0
Start-of-Stream Delimiter (SSD), part 2
of 2
CONTROL
End-of-Stream Delimiter (ESD), part 1
of 2
undefined
undefined
undefined
End-of-Stream Delimiter (ESD), part 2
of 2
Transmit Error. Used to force signaling
errors
undefined
undefined
undefined
undefined
undefined
undefined
undefined
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
INVALID
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 11. 4B/5B Coding (Continued)
4B Code
Code Type
5B Code
Name
Interpretation
4 3 2 1 0
3 2 1 0
undefined
undefined
undefined
Invalid
Invalid
Invalid
0 1 1 0 0
1 0 0 0 0
1 1 0 0 1
Invalid
Invalid
Invalid
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
3.7.3.2
PMA Sublayer
Link
In 100 Mbps mode, the LXT972A establishes a link whenever the scrambler becomes locked and
remains locked for approximately 50 ms. Whenever the scrambler loses lock (receiving less than
12 consecutive idle symbols during a 2 ms window), the link are taken down. This provides a very
robust link, essentially filtering out any small noise hits that may otherwise disrupt the link.
Furthermore, 100 M idle patterns will not bring up a 10 Mbps link.
The LXT972A reports link failure via the MII status bits Register bits 1.2 and 17.10) and interrupt
functions. If auto-negotiation is enabled, link failure causes the LXT972A to re-negotiate.
Link Failure Override
The LXT972A normally transmits data packets only if it detects the link is up. Setting Register bit
16.14 = 1 overrides this function, allowing the LXT972A to transmit data packets even when the
link is down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be
disabled to transmit data packets in the absence of link. If auto-negotiation is enabled, the
LXT972A automatically transmits FLP bursts if the link is down.
Carrier Sense
For 100BASE-TX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes assertion of
carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-assertion of
CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R; however, in
this case RX_ER is asserted for one clock cycle when CRS is de-asserted.
Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons:
• De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to
appear somewhat shorter to the MAC than it actually is on the wire.
• CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-
duplex mode.
Receive Data Valid
The LXT972A asserts RX_DV to indicate that the received data maps to valid symbols. However,
RXD outputs zeros until the received data is decoded and available for transfer to the controller.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.7.3.3
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and
de-scrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10BASE-T), as well
as receiving polarity correction and baseline wander correction functions.
Scrambler/De-scrambler
The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using
an 11-bit, data-independent polynomial. The receiver automatically decodes the polynomial
whenever IDLE symbols are received.
Scrambler Seeding. Once the transmit data (or Idle symbols) are properly encoded, they are
scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed.
Five seed bits are determined by the PHY address, and the remaining bits are hard coded in the
design.
Scrambler Bypass. The scrambler/de-scrambler can be bypassed by setting Register bit 16.12 = 1.
Scrambler bypass is provided for diagnostic and test support.
Baseline Wander Correction
The LXT972A provides a baseline wander correction function which makes the device robust
under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by
definition “unbalanced”. This means that the average value of the signal voltage can “wander”
significantly over short time intervals (tenths of seconds). This wander can cause receiver errors at
long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are
completely data dependent.
The LXT972A baseline wander correction characteristics allow the device to recover error-free
data while receiving worst-case “killer” packets over all cable lengths.
Polarity Correction
The 100BASE-TX de-scrambler automatically detects and corrects for the condition where the
receive signal at TPIP and TPIN is inverted.
Programmable Slew Rate Control
The LXT972A device supports a slew rate mechanism whereby one of four pre-selected slew rates
can be used. This allows the designer to optimize the output waveform to match the characteristics
of the magnetics. The slew rate is determined by the TxSLEW pins as shown in Table 4 on page 14.
3.8
10 Mbps Operation
The LXT972A operates as a standard 10BASE-T transceiver. The LXT972A supports all the
standard 10 Mbps functions. During 10BASE-T (10T) operation, the LXT972A transmits and
receives Manchester-encoded data across the network link. When the MAC is not actively
transmitting data, the LXT972A drives link pulses onto the line.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded
signals received from the network are decoded by the LXT972A and sent across the MII to the
MAC.
3.8.1
10BASE-T Preamble Handling
The LXT972A offers two options for preamble handling, selected by bit 16.5. In 10T Mode when
Register bit 16.5 = 0, the LXT972A strips the entire preamble off of received packets. CRS is
asserted coincident with SFD. RX_DV is held Low for the duration of the preamble. When
RX_DV is asserted, the very first two nibbles driven by the LXT972A are the SFD “5D” hex
followed by the body of the packet.
In 10BASE-T mode when Register bit 16.5 = 1, the LXT972A passes the preamble through the
MII and asserts RX_DV and CRS simultaneously. In 10BASE-T loopback, the LXT972A loops
back whatever the MAC transmits to it, including the preamble.
3.8.2
3.8.3
3.8.4
10BASE-T Carrier Sense
For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on
reception of an end-of-frame (EOF) marker. Bit 16.7 allows CRS de-assertion to be synchronized
with RX_DV de-assertion. Refer to Table 48 on page 66.
10BASE-T Dribble Bits
The LXT972A device handles dribbles bits in all modes. If between one through four dribble bits
are received, the nibble is passed across the MII, padded with 1s if necessary. If between five
through seven dribble bits are received, the second nibble is not sent onto the MII bus.
10BASE-T Link Integrity Test
In 10BASE-T mode, the LXT972A always transmits link pulses. When the Link Integrity Test
function is enabled (the normal configuration), it monitors the connection for link pulses. Once link
pulses are detected, data transmission is enabled and remains enabled as long as either the link
pulses or data transmission continue. If the link pulses stop, the data transmission is disabled.
If the Link Integrity Test function is disabled, the LXT972A transmits to the connection regardless
of detected link pulses. The Link Integrity Test function can be disabled by setting Register bit
16.14 = 1.
3.8.4.1
Link Failure
Link failure occurs if Link Integrity Test is enabled and link pulses or packets stop being received.
If this condition occurs, the LXT972A returns to the auto-negotiation phase if auto-negotiation is
enabled. If the Link Integrity Test function is disabled by setting Register bit 16.14 = 1 in the
Configuration Register, the LXT972A transmits packets, regardless of link status.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.8.5
3.8.6
10T SQE (Heartbeat)
By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT972A. To
enable this function, set Register bit 16.9 = 1. When this function is enabled, the LXT972A asserts
its COL output for 5-15 BT after each packet. See Figure 29 on page 53 for SQE timing
parameters.
10T Jabber
If a transmission exceeds the jabber timer, the LXT972A disables the transmit and loopback
functions. See Figure 28 on page 53 for jabber timing parameters.
The LXT972A automatically exits jabber mode after the unjabber time has expired. This function
can be disabled by setting Register bit 16.10 = 1.
3.8.7
10T Polarity Correction
The LXT972A automatically detects and corrects for the condition where the receive signal (TPIP/
N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted end-of-
frame (EOF) markers, are received consecutively. If link pulses or data are not received by the
maximum receive time-out period (96-128 ms), the polarity state is reset to a non-inverted state.
3.9
Monitoring Operations
3.9.1
Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows:
• Register bit 17.7 is set to 1 once the Auto-Negotiation process is completed.
• Register bits 1.2 and 17.10 are set to 1 once the link is established.
• Register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and
duplex).
3.9.1.1
Monitoring Next Page Exchange
The LXT972A offers an Alternate Next Page mode to simplify the next page exchange process.
Normally, Register bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode
is enabled (Register bit 16.1 = 1), Register bit 6.1 is automatically cleared whenever a new
negotiation process takes place. This prevents the user from reading an old value in Register bit
6.1 and assuming that Registers 5 and 8 (Partner Ability) contain valid information. Additionally,
the LXT972A uses Register bit 6.5 to indicate when the current received page is the base page.
This information is useful for recognizing when next pages must be resent due to a new negotiation
process starting. Register bits 6.1 and 6.5 are cleared when read.
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.9.2
LED Functions
The LXT972A incorporates three direct LED drivers. On power up all the drivers are asserted for
approximately one second after reset de-asserts. Each LED driver can be programmed using the
LED Configuration Register (refer to Table 52 on page 70) to indicate one the following
conditions:
• Operating Speed
• Transmit Activity
• Receive Activity
• Collision Condition
• Link Status
• Duplex Mode
The LED drivers can also be programmed to display various combined status conditions. For
example, setting Register bits 20.15:12 = 1101 produces the following combination of Link and
Activity indications:
• If Link is down, LED is off.
• If Link is up, LED is on.
• If Link is up and activity is detected, the LED blinks at the stretch interval selected by Register
bits 20.3:2 and continues to blink as long as activity is present.
The LED driver pins also provide initial configuration settings. The LED pins are sensitive to
polarity and automatically pulls up or pulls down to configure for either open drain or open source
circuits (10 mA Max current rating) as required by the hardware configuration. Refer to the
discussion of “Hardware Configuration Settings” on page 24 for details.
3.9.2.1
LED Pulse Stretching
The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms.
If during this pulse stretch period the event occurs again, the pulse stretch time is further extended.
When an event such as receiving a packet occurs, it is edge detected and starts the stretch timer.
The LED driver remains asserted until the stretch timer expires. If another event occurs before the
stretch timer expires, the stretch timer is reset and the stretch time is extended.
When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer.
When the stretch timer expires the edge detector is reset so that a long event causes another pulse to
be generated from the edge detector, which resets the stretch timer and causes the LED driver to
remain asserted. Figure 20 shows how the stretch operation functions.
Datasheet
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 20. LED Pulse Stretching
Event
LED
stretch
stretch
stretch
Note: The direct drive LED outputs in this diagram are shown as active Low.
3.10
Boundary Scan (JTAG1149.1) Functions
LXT972A includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input,
output, and input/output pins are accessible. The BSDL file is available by contacting your local
sales office (see the back page) or by accessing the Intel web site (developer.intel.com/design/
network/).
3.10.1
3.10.2
3.10.3
3.10.4
Boundary Scan Interface
This interface consists of five pins (TMS, TDI, TDO, TRST, and TCK). It includes a state machine,
data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is
internally pulled down. TDO does not have an internal pull-up or pull-down.
State Machine
The TAP controller is a 16 state machine driven by the TCK and TMS pins. Upon reset the
TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are
high for five TCK periods.
Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The decode logic
ensures the correct data flow to the Data registers according to the current instruction. Valid
instructions are listed in Table 13.
Boundary Scan Register (BSR)
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the
serial shift stage and the parallel output stage. There are four modes of operation as listed in Table
12.
40
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 12. BSR Mode of Operation
Mode
Description
1
2
3
4
Capture
Shift
Update
System Function
Table 13. Supported JTAG Instructions
Name
EXTEST
Code
Description
External Test
Mode
Data Register
BSR
1111 1111 1110 1000
1111 1111 1111 1110
1111 1111 1111 1000
1111 1111 1100 1111
1111 1111 1110 1111
1111 1111 1111 1111
Test
IDCODE
SAMPLE
HIGHZ
ID Code Inspection
Sample Boundary
Force Float
Normal
Normal
Normal
Test
ID REG
BSR
Bypass
Bypass
Bypass
CLAMP
BYPASS
Control Boundary to 1/0
Bypass Scan
Normal
Table 14. Device ID Register
31:28
27:12
11:8
7:1
0
Version
Part ID (hex)
Jedec Continuation Characters
JEDEC ID1
Reserved
XXXX
03CB
0000
111 1110
1
1. The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC ID is FE (1111 1110) which
becomes 111 1110.
2. See the LXT971A/972A Specification Update (document number 249354) for the current version of the
Jedec continuation characters.
Datasheet
41
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
4.0
Application Information
4.1
Magnetics Information
The LXT972A requires a 1:1 ratio for both the receive and transmit transformers. The transformer
isolation voltage should be rated at 2kV to protect the circuitry from static voltages across the
connectors and cables. Refer to Table 15 for transformer requirements.
A cross-reference list of magnetic manufacturers and part numbers is available in Magnetic
Manufacturers for Networking Product Applications (document number 248991) and is found on
the Intel web site (www.Intel.com). Before committing to a specific component, designers should
contact the manufacturer for current product specifications, and validate the magnetics for the
specific application.
Table 15. Magnetics Requirements
Parameter
Min
Nom
Max
Units
Test Condition
Rx turns ratio
–
–
1 : 1
1 : 1
0.6
–
–
–
–
–
–
–
–
–
Tx turns ratio
–
Insertion loss
0.0
350
–
1.1
–
dB
µH
kV
dB
dB
dB
dB
Primary inductance
Transformer isolation
1.5
–
–
40
35
-16
-10
–
.1 to 60 MHz
60 to 100 MHz
30 MHz
Differential to common mode rejection
Return Loss
–
–
–
–
–
–
80 MHz
4.2
Typical Twisted-Pair Interface
Table 16 provides a comparison of the RJ-45 connections for NIC and switch applications in a
typical twisted-pair interface setting.
Table 16. RJ-45 Pin Comparison of NIC and Switch Twisted-Pair Interfaces
RJ-45
Symbol
Switch
NIC
TPIP
TPIN
TPOP
TPON
1
2
3
6
3
6
1
2
Figure 21 on page 43 shows a typical twisted-pair interface with the RJ-45 connections crossed
over for a switch configuration. Figure 22 on page 44 provides a typical twisted-pair interface with
the RJ-45 connections configured for a NIC application.
42
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 21. Typical Twisted-Pair Interface - Switch
270 pF 5%
TPIP
RJ-45
50Ω 1%
1:1
1
2
0.01 µF
50Ω 1%
3
3
TPIN
50 Ω
50 Ω
50 Ω
50 Ω
4
5
6
7
8
270 pF 5%
TPOP
1:1
LXT972A
2
50 Ω
50 Ω
0.1µF
TPON
1
* = 0.001 µF / 2.0 kV
*
*
4
VCCA
0.1µF
.01µF
GND
1. Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be
realized by supplying the center-tap from a 2.5 V current source. A separate ferrite bead (rated at 50
mA) should be used to supply center-tap current.
2. The 100 Ω transmit load termination resistor typically required is integrated in the LXT972A.
3. Magnetics without a receive pair center-tap do not require a 2 kV termination.
4. RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45 setup, see
Figure 22 on page 44.
Datasheet
43
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 22. Typical Twisted-Pair Interface - NIC
RJ-45
50 Ω
50 Ω
50 Ω
270 pF 5%
8
7
6
5
4
3
2
1
TPIN
50Ω 1%
1:1
1:1
50 Ω
50 Ω
0.01 µF
50Ω 1%
3
50 Ω
TPIP
270 pF 5%
TPON
LXT972A
2
0.1µF
4
TPOP
1
* = 0.001 µF / 2.0 kV
*
*
VCCA
0.1µF
.01µF
GND
1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by
supplying the center tap from a 2.5 V current source. A separate ferrite bead (rated at 50 mA) should be used to supply
center tap current.
2. The 100Ω transmit load termination resistor typically required is integrated in the LXT972A.
3. Magnetics without a receive pair center tap do not require a 2kV termination.
4. RJ-45 connections shown are for a standard NIC. Tx/Rx crossover may be required for repeater & switch applications.
Figure 23. Typical MII Interface
TX_EN
TX_ER
TXD<3:0>
TX_CLK
RX_CLK
X
F
MAC
LXT972A
RX_DV
RJ-45
RX_ER
M
R
RXD<3:0>
CRS
COL
44
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
5.0
Test Specifications
Note: Table 17 through Table 36 and Figure 24 through Figure 35 represent the target specifications of
the LXT972A. These specifications are guaranteed by test except where noted “by design.”
Minimum and maximum values listed in Table 19 through Table 36 apply over the recommended
operating conditions specified in Table 18.
5.1
Electrical Parameters
Table 17. Absolute Maximum Ratings
Parameter
Sym
Min
Max
Units
Supply voltage
VCC
TOPA
TST
-0.3
-15
-65
4.0
+85
V
Operating temperature
Storage temperature
ºC
ºC
+150
Caution: Exceeding these values may cause permanent damage.
Functional operation under these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device
reliability.
Table 18. Operating Conditions
1
Parameter
Sym
Min
0
Typ
–
Max
70
Units
ºC
Recommended operating
LXT972A_C
(Commercial)
TOPA
temperature
Analog & Digital
I/O
Vcca, Vccd
Vccio
ICC
3.14
3.3
–
3.45
3.45
110
82
V
Recommended supply voltage2
2.35
V
100BASE-TX
10BASE-T
–
–
–
–
–
92
66
–
mA
mA
mA
ICC
VCC current
Hard Power Down
Soft Power Down
Auto-Negotiation
ICC
1
Icc
51
90
–
ICC
110
mA
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Voltages with respect to ground unless otherwise specified.
Datasheet
45
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 19. Digital I/O Characteristics1
2
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Input Low voltage
Input High voltage
Input current
VIL
VIH
II
–
–
–
–
–
–
0.8
–
V
V
–
–
2.0
-10
–
10
0.4
–
µA
V
0.0 < VI < VCC
IOL = 4 mA
Output Low voltage
Output High voltage
VOL
VOH
2.4
V
IOH = -4 mA
1. Applies to all pins except MII, LED and XI/XO pins. Refer to Table 20 for MII I/O Characteristics, Table 21 for XI/
XO and Table 22 for LED Characteristics.
2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 20. Digital I/O Characteristics - MII Pins
1
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Input Low voltage
Input High voltage
Input current
VIL
VIH
II
–
2.0
-10
–
–
–
–
–
–
–
0.8
–
V
V
–
–
10
0.4
–
µA
V
0.0 < VI < VCCIO
Output Low voltage
VOL
VOH
VOH
IOL = 4 mA
2.2
2.0
–
V
IOH = -4 mA, VCCIO = 3.3 V
IOH = -4 mA, VCCIO = 2.5 V
VCCIO = 2.5 V
Output High voltage
–
V
2
RO
100
100
–
Ω
Ω
Driver output resistance
2
(Line driver output enabled)
RO
–
–
VCCIO = 3.3 V
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design; not subject to production testing.
Table 21. I/O Characteristics - REFCLK/XI and XO Pins
Parameter
Input Low Voltage
Sym
Min
Typ1
Max
Units
Test Conditions
VIL
VIH
∆f
–
2.0
–
–
–
0.8
–
V
V
–
–
–
–
–
Input High Voltage
Input Clock Frequency Tolerance2
Input Clock Duty Cycle2
Input Capacitance
–
±100
65
ppm
%
Tdc
CIN
35
–
–
3.0
–
pF
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design; not subject to production testing.
Table 22. I/O Characteristics - LED/CFG Pins
Parameter
Input Low Voltage
Input High Voltage
Symbol
Min
Typ
Max
Units
Test Conditions
VIL
VIH
–
–
–
0.8
–
V
V
–
–
2.0
46
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 22. I/O Characteristics - LED/CFG Pins (Continued)
Parameter
Input Current
Symbol
Min
Typ
Max
Units
Test Conditions
II
-10
–
–
–
–
10
0.4
–
µA
V
0 < VI < VCCIO
IOL = 10 mA
Output Low Voltage
Output High Voltage
VOL
VOH
2.0
V
IOH = -10 mA
Table 23. 100BASE-TX Transceiver Characteristics
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Peak differential output voltage
Signal amplitude symmetry
Signal rise/fall time
VP
Vss
0.95
98
–
–
–
–
1.05
102
5.0
V
%
ns
ns
Note 2
Note 2
Note 2
Note 2
TRF
TRFS
3.0
–
Rise/fall time symmetry
0.5
Offset from 16ns pulse
width at 50% of pulse
peak
Duty cycle distortion
DCD
35
50
65
%
Overshoot/Undershoot
VOS
–
–
–
–
–
5
%
ns
–
–
Jitter (measured differentially)
1.4
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Measured at the line side of the transformer, line replaced by 100Ω(+/-1%) resistor.
Table 24. 10BASE-T Transceiver Characteristics
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Transmitter
With transformer, line
replaced by 100 Ω
resistor
Peak differential output
voltage
VOP
-
2.2
0
2.5
2
2.8
11
V
After line model specified
by IEEE 802.3 for
Transition timing jitter added
by the MAU and PLS sections
ns
10BASE-T MAU
Receiver
-
Receive Input Impedance
ZIN
-
22
kΩ
Differential Squelch
Threshold
VDS
300
420
585
mV
Table 25. 10BASE-T Link Integrity Timing Characteristics
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Time Link Loss Receive
Link Pulse
TLL
TLP
50
2
–
–
–
150
7
ms
Link Pulses
ms
–
–
–
Link Min Receive Timer
TLR MIN
2
7
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
47
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 25. 10BASE-T Link Integrity Timing Characteristics
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Link Max Receive Timer
Link Transmit Period
Link Pulse Width
TLR MAX
Tlt
50
8
–
–
–
150
24
ms
ms
ns
–
–
–
Tlpw
60
150
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 26. LXT972A Thermal Characteristics
Parameter
LXT972ALC
Package
Theta-JA
Theta-JC
Psi - JT
10 x 10 x 1.4 64LQFP
58 C/W
27 C/W
3.4 C/W
48
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
5.2
Timing Diagrams
Figure 24. 100BASE-TX Receive Timing - 4B Mode
0 ns
250 ns
TPI
t4
t5
CRS
t3
RX_DV
t1
t2
RXD<3:0>
RX_CLK
t6
t7
COL
Table 27. 100BASE-TX Receive Timing Parameters - 4B Mode
1
Parameter
Sym
Min
Typ
Max
Units2
Test Conditions
RXD<3:0>, RX_DV, RX_ER setup
to RX_CLK High
t1
10
–
–
ns
–
RXD<3:0>, RX_DV, RX_ER hold
from RX_CLK High
t2
10
–
–
ns
–
CRS asserted to RXD<3:0>, RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
t3
t4
t5
t6
t7
3
–
–
–
–
–
5
BT
BT
BT
BT
BT
–
–
–
–
–
12
10
16
17
16
17
22
20
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit
time = 10-8 s or 10 ns.
Datasheet
49
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 25. 100BASE-TX Transmit Timing - 4B Mode
0ns
250ns
t1
TXCLK
TX_EN
t2
TXD<3:0>
t5
TPO
t3
t4
CRS
Table 28. 100BASE-TX Transmit Timing Parameters - 4B Mode
1
Parameter
Sym
Min
Typ
Max
Units2
Test Conditions
TXD<3:0>, TX_EN, TX_ER setup to TX_CLK
High
t1
12
–
–
–
ns
–
TXD<3:0>, TX_EN, TX_ER hold from TX_CLK
High
t2
0
–
ns
–
TX_EN sampled to CRS asserted
t3
t4
t5
20
24
–
–
–
24
28
BT
BT
BT
–
–
–
TX_EN sampled to CRS de-asserted
TX_EN sampled to TPO out (Tx latency)
5.3
5.7
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit
time = 10-8 s or 10 ns.
50
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 26. 10BASE-T Receive Timing
RX_CLK
t1 t2
t3
RXD,
RX_DV,
RX_ER
t5
t4
CRS
t6
t7
t9
TPI
t8
COL
Table 29. 10BASE-T Receive Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units2
Test Conditions
RXD, RX_DV, RX_ER Setup to RX_CLK
High
t1
10
–
–
ns
–
RXD, RX_DV, RX_ER Hold from
RX_CLK High
t2
t3
t4
10
4.2
5
–
–
–
–
ns
–
–
–
TPIP/N in to RXD out (Rx latency)
6.6
32
BT
BT
CRS asserted to RXD, RX_DV, RX_ER
asserted
RXD, RX_DV, RX_ER de-asserted to CRS
de-asserted
t5
0.3
–
0.5
BT
–
TPI in to CRS asserted
t6
t7
t8
t9
2
6
1
5
–
–
–
–
28
10
31
10
BT
BT
BT
BT
–
–
–
–
TPI quiet to CRS de-asserted
TPI in to COL asserted
TPI quiet to COL de-asserted
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit
time = 10-7 s or 100 ns.
Datasheet
51
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 27. 10BASE-T Transmit Timing
TX_CLK
t1
t2
TXD,
TX_EN,
TX_ER
t3
t4
CRS
t5
TPO
Table 30. 10BASE-T Transmit Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units2
Test Conditions
TXD, TX_EN, TX_ER setup to TX_CLK
High
t1
10
–
–
–
ns
–
TXD, TX_EN, TX_ER hold from TX_CLK
High
t2
0
–
ns
–
TX_EN sampled to CRS asserted
t3
t4
t5
–
–
–
2
1
–
–
–
BT
BT
BT
–
–
–
TX_EN sampled to CRS de-asserted
TX_EN sampled to TPO out (Tx latency)
72.5
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit
time = 10-7 s or 100 ns.
52
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 28. 10BASE-T Jabber and Unjabber Timing
TX_EN
t1
TXD
t2
COL
Table 31. 10BASE-T Jabber and Unjabber Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Maximum transmit time
Unjab time
t1
t2
20
–
–
150
750
ms
ms
–
–
250
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Figure 29. 10BASE-T SQE (Heartbeat) Timing
TX_CLK
TX_EN
COL
t1
t2
Table 32. 10BASE-T SQE Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
COL (SQE) Delay after TX_EN off
COL (SQE) Pulse duration
t1
t2
0.65
0.5
–
–
1.6
1.5
us
us
–
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
53
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 30. Auto Negotiation and Fast Link Pulse Timing
Clock Pulse
Data Pulse
Clock Pulse
TPO
t1
t1
t3
t2
Figure 31. Fast Link Pulse Timing
FLP Burst
FLP Burst
TPO
t4
t5
Table 33. Auto Negotiation and Fast Link Pulse Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Clock/Data pulse width
Clock pulse to Data pulse
Clock pulse to Clock pulse
FLP burst width
t1
t2
t3
t4
t5
–
–
55.5
123
–
100
–
–
63.8
127
–
ns
µs
µs
ms
ms
ea
–
–
–
–
–
–
–
2
FLP burst to FLP burst
Clock/Data pulses per burst
8
12
–
24
17
33
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
54
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 32. MDIO Input Timing
MDC
t2
t1
MDIO
Figure 33. MDIO Output Timing
t4
MDC
t3
MDIO
Table 34. MDIO Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
MDIO setup before MDC, sourced
by STA
t1
10
5
–
–
ns
–
MDIO hold after MDC, sourced by
STA
t2
–
–
ns
–
MDC to MDIO output delay, source
by PHY
t3
t4
–
–
–
150
–
ns
ns
–
MDC period
125
MDC = 8 MHz
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
55
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figure 34. Power-Up Timing
v1
t1
VCC
MDIO,etc
Table 35. Power-Up Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
Voltage threshold
Power Up delay2
v1
t1
–
–
2.9
–
–
V
–
–
300
µs
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Power Up Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the PHY
comes out of reset after a delay of No MORE Than 300 µs. System designers should consider this as a minimum
value - After threshold v1 is reached, the MAC should delay No LESS Than 300 µs before accessing the MDIO port.
Figure 35. RESET Pulse Width and Recovery Timing
t1
RESET
t2
MDIO,etc
Table 36. RESET Pulse Width and Recovery Timing Parameters
1
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
RESET pulse width
RESET recovery delay2
t1
t2
10
–
–
–
–
ns
–
–
300
µs
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY's guaranteed performance - the
PHY comes out of reset after a delay of No MORE Than 300 µs. System designers should consider this as a minimum
value - After de-asserting RESET*, the MAC should delay No LESS Than 300 µs before accessing the MDIO port.
56
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
6.0
Register Definitions
The LXT972A register set includes multiple 16-bit registers. Refer to Table 37 for a complete
register listing.
• Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and
Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-
Negotiation” sections of the IEEE 802.3 standard.
• Additional registers are defined in accordance with the IEEE 802.3 standard for adding unique
chip functions.
Table 37. Register Set
Address
Register Name
Bit Assignments
0
1
2
3
4
5
6
7
Control Register
Status Register #1
Refer to Table 39 on page 60
Refer to Table 40 on page 61
Refer to Table 41 on page 62
Refer to Table 42 on page 62
Refer to Table 43 on page 63
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Base Page Ability Register Refer to Table 44 on page 64
Auto-Negotiation Expansion Register
Refer to Table 45 on page 65
Refer to Table 46 on page 65
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Received Next Page
Register
8
Refer to Table 47 on page 66
9
10
1000BASE-T/100BASE-T2 Control Register
1000BASE-T/100BASE-T2 Status Register
Extended Status Register
Port Configuration Register
Status Register #2
Not Implemented
Not Implemented
15
Not Implemented
16
Refer to Table 48 on page 66
Refer to Table 49 on page 67
Refer to Table 50 on page 68
Refer to Table 51 on page 68
Refer to Table 52 on page 70
–
17
18
Interrupt Enable Register
Interrupt Status Register
19
20
LED Configuration Register
Reserved
21-25
26
27-30
Transmit Control Register
Refer to Table 54 on page 72
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
58
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Datasheet
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 39. Control Register (Address 0)
Bit
Name
Description
Type 1
Default
1 = PHY reset
0 = Normal operation
R/W
SC
0.15
Reset
0
1 = Enable loopback mode
0 = Disable loopback mode
0.14
0.13
Loopback
R/W
0
0.6
0.13
Speed Selected
1
1
0
0
1
0
1
0
Reserved
Speed Selection
R/W
Note 2
1000 Mbps (not supported)
100 Mbps
10 Mbps
Auto-Negotiation
Enable
1 = Enable Auto-Negotiation Process
0 = Disable Auto-Negotiation Process
0.12
0.11
0.10
R/W
R/W
R/W
Note 2
1 = Power-down
Power-Down
Isolate
0
0
0 = Normal operation
1 = Electrically isolate PHY from MII
0 = Normal operation
Restart
Auto-Negotiation
R/W
SC
1 = Restart Auto-Negotiation Process
0 = Normal operation
0.9
0
1 = Full Duplex
0 = Half Duplex
0.8
0.7
Duplex Mode
Collision Test
R/W
R/W
Note 2
0
1 = Enable COL signal test
0 = Disable COL signal test
0.6
0.13
Speed Selected
1
1
0
0
1
0
1
0
Reserved
0.6
Speed Selection
Reserved
R/W
R/W
0
1000 Mbps (not supported)
100 Mbps
10 Mbps
0.5:0
Write as 0, ignore on Read
00000
1. R/W = Read/Write
RO = Read Only
SC = Self Clearing
2. Default value of bits 0.12, 0.13 and 0.8 are determined by the LED/CFG pins (refer to Table 9 on page 25).
Table 40. MII Status Register #1 (Address 1)
Bit
Name
Description
Type 1
Default
100BASE-T4
Not Supported
1 = PHY able to perform 100BASE-T4
0 = PHY not able to perform 100BASE-T4
1.15
RO
0
100BASE-X Full-
Duplex
1 = PHY able to perform full-duplex 100BASE-X
0 = PHY not able to perform full-duplex 100BASE-X
1.14
1.13
RO
RO
1
1
100BASE-X Half-
Duplex
1 = PHY able to perform half-duplex 100BASE-X
0 = PHY not able to perform half-duplex 100BASE-X
1. RO = Read Only
LL = Latching Low
LH = Latching High
60
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 40. MII Status Register #1 (Address 1)
Bit
Name
Description
Type 1
Default
1 = PHY able to operate at 10 Mbps in full-duplex mode
0 = PHY not able to operate at 10 Mbps full-duplex
mode
1.12
10 Mbps Full-Duplex
RO
1
1 = PHY able to operate at 10 Mbps in half-duplex mode
0 = PHY not able to operate at 10 Mbps in half-duplex
1.11
1.10
10 Mbps Half-Duplex
RO
RO
1
0
100BASE-T2 Full-
Duplex
Not Supported
1 = PHY able to perform full-duplex 100BASE-T2
0 = PHY not able to perform full-duplex 100BASE-T2
100BASE-T2 Half-
Duplex
Not Supported
Extended Status
Reserved
1 = PHY able to perform half duplex 100BASE-T2
0 = PHY not able to perform half-duplex 100BASE-T2
1.9
RO
0
1 = Extended status information in register 15
0 = No extended status information in register 15
1.8
1.7
RO
RO
0
0
1 = ignore when read
1 = PHY accepts management frames with preamble
suppressed
MF Preamble
Suppression
1.6
RO
0
0 = PHY will not accept management frames with
preamble suppressed
Auto-Negotiation
Complete
1 = Auto-negotiation complete
1.5
1.4
1.3
1.2
1.1
1.0
RO
RO/LH
RO
0
0
1
0
0
1
0 = Auto-negotiation not complete
1 = Remote fault condition detected
0 = No remote fault condition detected
Remote Fault
Auto-Negotiation
Ability
1 = PHY is able to perform Auto-Negotiation
0 = PHY is not able to perform Auto-Negotiation
1 = Link is up
Link Status
RO/LL
RO/LH
RO
0 = Link is down
1 = Jabber condition detected
Jabber Detect
0 = Jabber condition not detected
1 = Extended register capabilities
0 = Basic register capabilities
Extended Capability
1. RO = Read Only
LL = Latching Low
LH = Latching High
Table 41. PHY Identification Register 1 (Address 2)
Bit
Name
Description
Type 1
RO
Default
The PHY identifier composed of bits 3 through 18 of the
OUI.
2.15:0
PHY ID Number
0013 hex
1. RO = Read Only
Datasheet
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Document #: 249186
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 42. PHY Identification Register 2 (Address 3)
Bit
Name
Description
Type 1
RO
Default
The PHY identifier composed of bits 19
through 24 of the OUI.
3.15:10
PHY ID number
011110
Manufacturer’s
model number
6 bits containing manufacturer’s part
number.
3.9:4
3.3:0
RO
RO
001110
xxxx
Manufacturer’s
revision number
4 bits containing manufacturer’s revision
number.
(See LXT971A/972A
Specification Update)
1. RO = Read Only
Figure 36. PHY Identifier Bit Mapping
a
b
c
Organizationally Unique Identifier
r
s
x
PHY ID Register #2 (Address 3)
PHY ID Register #1 (address 2) = 0013
15
0
0
1
15
0
10
0
9
0
4
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
1
1
1
0 0
00
20
7B
5
0
3
0
The Intel OUI is 00207B hex
Manufacturer’s
Model Number
Revision
Number
62
Datasheet
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 43. Auto Negotiation Advertisement Register (Address 4)
Bit
Name
Description
Type 1
Default
1 = Port has ability to send multiple pages.
0 = Port has no ability to send multiple pages.
4.15
Next Page
Reserved
R/W
RO
0
0
0
0
0
4.14
4.13
4.12
4.11
Ignore.
1 = Remote fault.
Remote Fault
Reserved
R/W
R/W
R/W
0 = No remote fault.
Ignore.
Asymmetric
Pause
Pause operation defined in Clause 40 and 27.
1 = Pause operation enabled for full-duplex links.
0 = Pause operation disabled.
4.10
Pause
R/W
Note 2
1 = 100BASE-T4 capability is available.
0 = 100BASE-T4 capability is not available.
(The LXT972A does not support 100BASE-T4 but allows this
bit to be set to advertise in the Auto-Negotiation sequence for
100BASE-T4 operation. An external 100BASE-T4 transceiver
could be switched in if this capability is desired.)
4.9
100BASE-T4
R/W
0
100BASE-TX
full-duplex
1 = Port is 100BASE-TX full-duplex capable.
0 = Port is not 100BASE-TX full-duplex capable.
4.8
4.7
R/W
R/W
Note 3
Note 3
1 = Port is 100BASE-TX capable.
100BASE-TX
0 = Port is not 100BASE-TX capable.
1 = Port is 10BASE-T full-duplex capable.
0 = Port is not 10BASE-T full-duplex capable.
10BASE-T
full-duplex
4.6
4.5
R/W
R/W
Note 3
Note 3
1 = Port is 10BASE-T capable.
0 = Port is not 10BASE-T capable.
10BASE-T
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future Auto-Negotiation
development.
Selector Field,
S<4:0>
4.4:0
R/W
00001
<11111> = Reserved for future Auto-Negotiation
development.
Unspecified or reserved combinations should not be
transmitted.
1. R/W = Read/Write
RO = Read Only
2. Default value of bit 4.10 is determined by pin 33/H8.
3. Default values of bits 4.5, 4.6, 4.7, and 4.8 are determined by LED/CFGn pins at reset. Refer to Table 9 for details.
Datasheet
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Document #: 249186
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 44. Auto Negotiation Link Partner Base Page Ability Register (Address 5)
Bit
Name
Description
Type 1
Default
1 = Link Partner has ability to send multiple pages.
0 = Link Partner has no ability to send multiple pages.
5.15
Next Page
RO
N/A
1 = Link Partner has received Link Code Word from
LXT972A.
5.14
Acknowledge
RO
N/A
0 = Link Partner has not received Link Code Word from the
LXT972A.
1 = Remote fault.
5.13
5.12
Remote Fault
Reserved
RO
RO
N/A
N/A
0 = No remote fault.
Ignore.
Pause operation defined in Clause 40 and 27.
Asymmetric
Pause
5.11
RO
N/A
1 = Link Partner is Pause capable.
0 = Link Partner is not Pause capable.
1 = Link Partner is Pause capable.
5.10
5.9
5.8
Pause
RO
RO
RO
RO
N/A
N/A
N/A
N/A
0 = Link Partner is not Pause capable.
1 = Link Partner is 100BASE-T4 capable.
0 = Link Partner is not 100BASE-T4 capable.
100BASE-T4
100BASE-TX
full-duplex
1 = Link Partner is 100BASE-TX full-duplex capable.
0 = Link Partner is not 100BASE-TX full-duplex capable.
1 = Link Partner is 100BASE-TX capable.
0 = Link Partner is not 100BASE-TX capable.
5.7
100BASE-TX
10BASE-T
full-duplex
1 = Link Partner is 10BASE-T full-duplex capable.
0 = Link Partner is not 10BASE-T full-duplex capable.
5.6
5.5
RO
RO
N/A
N/A
1 = Link Partner is 10BASE-T capable.
0 = Link Partner is not 10BASE-T capable.
10BASE-T
<00001> = IEEE 802.3.
<00010> = IEEE 802.9 ISLAN-16T.
<00000> = Reserved for future Auto-Negotiation
development.
Selector Field
S<4:0>
5.4:0
RO
N/A
<11111> = Reserved for future Auto-Negotiation
development.
Unspecified or reserved combinations shall not be
transmitted.
1. RO = Read Only
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 45. Auto Negotiation Expansion (Address 6)
Bit
Name
Reserved
Description
Type 1
Default
6.15:6
Ignore on read.
RO
0
This bit indicates the status of the Auto-Negotiation variable,
base page. It flags synchronization with the Auto-
Negotiation state diagram allowing detection of interrupted
links. This bit is only used if bit 16.1 (Alternate NP feature)
is set.
RO/
LH
6.5
Base Page
0
1 = basepage = true
0 = basepage = false
RO/
LH
Parallel
1 = Parallel detection fault has occurred.
0 = Parallel detection fault has not occurred.
6.4
0
Detection Fault
Link Partner
1 = Link partner is next page able.
6.3
6.2
RO
RO
0
1
Next Page Able
0 = Link partner is not next page able.
1 = Local device is next page able.
Next Page Able
0 = Local device is not next page able.
1 = Indicates that a new page has been received and the
received code word has been loaded into register 5 (base
pages) or register 8 (next pages) as specified in clause 28 of
802.3. This bit is cleared on read. If bit 16.1 is set, the Page
Received bit is also cleared when mr_page_rx = false or
transmit_disable = true.
RO
LH
6.1
6.0
Page Received
0
0
Link Partner A/N 1 = Link partner is auto-negotiation able.
Able 0 = Link partner is not auto-negotiation able.
RO
1. RO = Read Only LH = Latching High
Table 46. Auto Negotiation Next Page Transmit Register (Address 7)
Bit
Name
Description
Type 1
Default
Next Page
(NP)
1 = Additional next pages follow
0 = Last page
7.15
R/W
RO
0
0
1
7.14
7.13
Reserved
Write as 0, ignore on read
Message Page
(MP)
1 = Message page
0 = Unformatted page
R/W
Acknowledge 2
(ACK2)
1 = Complies with message
0 = Can not comply with message
7.12
R/W
0
0
1 = Previous value of the transmitted Link Code Word
equalled logic zero
Toggle
(T)
7.11
R/W
R/W
0 = Previous value of the transmitted Link Code Word
equalled logic one
Message/Unformatted
Code Field
000000000
01
7.10:0
1. RO = Read Only. R/W = Read/Write
Datasheet
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Document #: 249186
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 47. Auto Negotiation Link Partner Next Page Receive Register (Address 8)
Bit
Name
Description
Type 1
Default
Next Page
(NP)
1 = Link Partner has additional next pages to send
0 = Link Partner has no additional next pages to send
8.15
RO
0
1 = Link Partner has received Link Code Word from
LXT972A
Acknowledge
(ACK)
8.14
RO
0
0 = Link Partner has not received Link Code Word from
LXT972A
Message Page
(MP)
1 = Page sent by the Link Partner is a Message Page
0 = Page sent by the Link Partner is an Unformatted Page
8.13
8.12
RO
RO
0
0
Acknowledge 2
(ACK2)
1 = Link Partner complies with the message
0 = Link Partner can not comply with the message
1 = Previous value of the transmitted Link Code Word
equalled logic zero
Toggle
(T)
8.11
RO
RO
0
0
0 = Previous value of the transmitted Link Code Word
equalled logic one
Message/Unformatted
Code Field
8.10:0
User definable
1. RO = Read Only.
Table 48. Configuration Register (Address 16, Hex 10)
Bit
Name
Reserved
Description
Write as zero, ignore on read.
Type 1
Default
16.15
R/W
0
Force Link Pass
1 = Force Link pass
0 = Normal operation
16.14
16.13
R/W
R/W
0
0
1 = Disable Twisted Pair transmitter
0 = Normal Operation
Transmit Disable
Bypass Scrambler
(100BASE-TX)
1 = Bypass Scrambler and Descrambler
0 = Normal Operation
16.12
16.11
16.10
R/W
R/W
R/W
0
0
0
Reserved
Ignore
Jabber
1 = Disable Jabber Correction
0 = Normal operation
(10BASE-T)
SQE
1 = Enable Heart Beat
0 = Disable Heart Beat
16.9
16.8
R/W
R/W
0
0
(10BASE-T)
TP Loopback
(10BASE-T)
1 = Disable TP loopback during half-duplex operation
0 = Normal Operation
CRS Select
1 = CRS deassert extends to RX_DV deassert
0 = Normal Operation
16.7
16.6
R/W
R/W
1
0
(10BASE-T)
Reserved
PRE_EN
Reserved
Write as zero, ignore on read.
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when CRS is
asserted.
16.5
R/W
R/W
0
16.4:3
Write as zero, ignore on read.
00
1. R/W = Read /Write, LHR = Latches High on Reset
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 48. Configuration Register (Address 16, Hex 10) (Continued)
Bit
16.2
Name
Reserved
Description
Write as zero, ignore on read.
Type 1
Default
R/W
0
Alternate NP
feature
1 = Enable alternate auto negotiate next page feature.
0 = Disable alternate auto negotiate next page feature
16.1
16.0
R/W
R/W
0
0
Reserved
Write as zero, ignore on read.
1. R/W = Read /Write, LHR = Latches High on Reset
Table 49. Status Register #2 (Address 17)
Bit
17.15
Name
Reserved
Description
Type 1
Default
Always 0.
RO
0
1 = LXT972A is operating in 100BASE-TX mode.
0 = LXT972A is not operating 100BASE-TX mode.
17.14
17.13
17.12
17.11
17.10
17.9
10/100 Mode
Transmit Status
Receive Status
Collision Status
Link
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
1 = LXT972A is transmitting a packet.
0 = LXT972A is not transmitting a packet.
1 = LXT972A is receiving a packet.
0 = LXT972A is not receiving a packet.
1 = Collision is occurring.
0 = No collision.
1 = Link is up.
0 = Link is down.
1 = Full-duplex.
0 = Half-duplex.
Duplex Mode
Auto-Negotiation
1 = LXT972A is in Auto-Negotiation Mode.
0 = LXT972A is in manual mode.
17.8
1 = Auto-negotiation process completed.
0 = Auto-negotiation process not completed.
Auto-Negotiation
Complete
17.7
RO
0
This bit is only valid when auto negotiate is enabled, and
is equivalent to bit 1.5.
17.6
17.5
Reserved
Polarity
Reserved.
RO
RO
0
0
1 = Polarity is reversed.
0 = Polarity is not reversed.
1 = Device Pause capable.
17.4
17:3
Pause
Error
RO
RO
0
0
0 = Device Not Pause capable.
1 = Error Occurred (Remote Fault, X,Y,Z).
0 = No error occurred.
17:2
17:1
17.0
Reserved
Reserved
Reserved
Always 0.
Always 0.
Always 0.
RO
RO
RO
0
0
0
1. RO = Read Only. R/W = Read/Write
Datasheet
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 50. Interrupt Enable Register (Address 18)
Bit
Name
Reserved
Description
Write as 0; ignore on read.
Type 1
Default
18.15:9
18.8
R/W
R/W
N/A
0
Reserved
Write as 0; ignore on read.
Mask for Auto Negotiate Complete
18.7
18.6
18.5
18.4
ANMSK
R/W
R/W
R/W
R/W
0
0
0
0
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Speed Interrupt
SPEEDMSK
DUPLEXMSK
LINKMSK
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Duplex Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
Mask for Link Status Interrupt
1 = Enable event to cause interrupt.
0 = Do not allow event to cause interrupt.
18.3
18.2
Reserved
Reserved
Write as 0, ignore on read.
Write as 0, ignore on read.
R/W
R/W
0
0
1 = Enable interrupts.
0 = Disable interrupts.
18.1
18.0
INTEN
TINT
R/W
R/W
0
0
1 = Force interrupt on MDINT.
0 = Normal operation.
1. R/W = Read /Write
Table 51. Interrupt Status Register (Address 19, Hex 13)
Bit
Name
Reserved
Description
Type 1
Default
19.15:9
Ignore
RO
N/A
0
19.8
Reserved
Ignore
RO
Auto Negotiation Status
19.7
ANDONE
RO/SC
N/A
0
1 = Auto Negotiation has completed.
0 = Auto Negotiation has not completed.
Speed Change Status
1 = A Speed Change has occurred since last reading this
19.6
19.5
SPEEDCHG
register.
RO/SC
RO/SC
0 = A Speed Change has not occurred since last reading this
register.
Duplex Change Status
1 = A Duplex Change has occurred since last reading this
DUPLEXCHG
register.
0
0 = A Duplex Change has not occurred since last reading this
register.
1. R/W = Read/Write, SC = Self Clearing.
68
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 51. Interrupt Status Register (Address 19, Hex 13) (Continued)
Bit
Name
Description
Type 1
Default
Link Status Change Status
1 = A Link Change has occurred since last reading this
register.
19.4
LINKCHG
RO/SC
0
0
0 = A Link Change has not occurred since last reading this
register.
19.3
19.2
Reserved
MDINT
Ignore
RO
RO
1 = MII interrupt pending.
0 = No MII interrupt pending.
19.1
19.0
Reserved
Reserved
Ignore.
Ignore
RO
RO
N/A
0
1. R/W = Read/Write, SC = Self Clearing.
Table 52. LED Configuration Register (Address 20, Hex 14)
Bit
Name
Description
Type 1
Default
0000 = Display Speed Status (Continuous, Default)
0001 = Display Transmit Status (Stretched)
0010 = Display Receive Status (Stretched)
0011 = Display Collision Status (Stretched)
0100 = Display Link Status (Continuous)
0101 = Display Duplex Status (Continuous)
0110 = Unused
0111 = Display Receive or Transmit Activity (Stretched)
1000 = Test mode- turn LED on (Continuous)
1001 = Test mode- turn LED off (Continuous)
1010 = Test mode- blink LED fast (Continuous)
1011 = Test mode- blink LED slow (Continuous)
1100 = Display Link and Receive Status combined 2
(Stretched)3
LED1
20.15:12
R/W
0000
Programming
bits
1101 = Display Link and Activity Status combined 2
(Stretched)3
1110 = Display Duplex and Collision Status combined 4
(Stretched)3
1111 = Unused
1. R/W = Read /Write
RO = Read Only
LH = Latching High
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched
regardless of the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
5. Values are relative approximations. Not guaranteed or production tested.
Datasheet
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Document #: 249186
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LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 52. LED Configuration Register (Address 20, Hex 14) (Continued)
Bit
Name
Description
Type 1
Default
0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status
0011 = Display Collision Status
0100 = Display Link Status (Default)
0101 = Display Duplex Status
0110 = Unused
0111 = Display Receive or Transmit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined 2
(Stretched)3
LED2
20.11:8
R/W
0100
Programming
bits
1101 = Display Link and Activity Status combined 2
(Stretched)3
1110 = Display Duplex and Collision Status combined 4
(Stretched)3
1111 = Unused
0000 = Display Speed Status
0001 = Display Transmit Status
0010 = Display Receive Status (Default)
0011 = Display Collision Status
0100 = Display Link Status
0101 = Display Duplex Status
0110 = Unused
0111 = Display Receive or Transmit Activity
1000 = Test mode- turn LED on
1001 = Test mode- turn LED off
1010 = Test mode- blink LED fast
1011 = Test mode- blink LED slow
1100 = Display Link and Receive Status combined 2
(Stretched)3
LED3
20.7:4
R/W
0010
Programming
bits
1101 = Display Link and Activity Status combined 2
(Stretched)3
1110 = Display Duplex and Collision Status combined 4
(Stretched)3
1111 = Unused
00 = Stretch LED events to 30 ms.
01 = Stretch LED events to 60 ms.
10 = Stretch LED events to 100 ms.
11 = Reserved.
20.3:2
LEDFREQ5
R/W
00
PULSE-
0 = Disable pulse stretching of all LEDs.
1 = Enable pulse stretching of all LEDs.
20.1
20.0
R/W
R/W
1
STRETCH
Reserved
Ignore.
N/A
1. R/W = Read /Write
RO = Read Only
LH = Latching High
2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.
The secondary LED driver (Receive or Activity) causes the LED to change state (blink).
3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched
regardless of the value of 20.1.
4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.
Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
5. Values are relative approximations. Not guaranteed or production tested.
70
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
Table 53. Digital Config Register (Address 26)
Bit
Name
Reserved
Description
Type 1
RO
Default
26.15:12
Reserved
0
0
0
0
0
1 = Increased MII drive strength
0 = Normal MII drive strength
26.11
26.10
26.9
MII Drive Strength
Reserved
R/W
RO
Reserved
1 = Map Symbol Error Signal To RXER
0 = Normal RXER
Show Symbol Error
R/W
RO
26.8:0
Reserved
Reserved
1. R/W = Read /Write, RO = Read Only, LH = Latching High
Table 54. Transmit Control Register #2 (Address 30)
Bit
Name
Reserved
Description
Type2
Default
30.15:11
Ignore
R/W
0
1 = Forces the transmitter into low power mode. Also
forces a zero-differential transmission.
0 = Normal transmission.
30.12
Transmit Low Power
R/W
0
00 = 3.0 ns (default is pins TXSLEW<1:0>)
Port Rise Time
Control1
01 = 3.4 ns
10 = 3.9 ns
11 = 4.4 ns
30.11:10
30.9:0
R/W
R/W
N/A
0
Reserved
Ignore
1. Values are relative approximations. Not guaranteed or production tested.
2. R/W = Read/Write
Datasheet
71
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
7.0
Package Specification
Figure 37. LXT972A LQFP Package Specifications
64-Pin Low Profile Quad Flat Pack
• Part Number - LXT972ALC Commercial Temperature Range (0ºC to +70ºC)
D
D1
Millimeters
Dim
Min
Max
A
A1
A2
B
–
1.60
0.15
1.45
0.27
12.15
10.1
12.15
10.1
0.05
1.35
0.17
11.85
9.9
E1
E
D
D1
E
11.85
E1
e
9.9
0.50 BSC1
L
0.45
0.75
e
e
/
2
L1
θ3
θ
1.00 REF
11o
0o
13o
7o
1. Basic Spacing between Centers
θ3
L1
A2
A
θ
A1
B
θ3
L
72
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
8.0
Product Ordering Information
Table 55. Product Information
Number
DJLXT972ALC.A4
Revision
Qualification
Tray MM
Tape & Reel MM
A4
S
834109
834917
Figure 38. Ordering Information - Sample
DJ
LXT
972A
L
C
A4
S
E001
Build Format
= Tray
E000
E001
= Tape and reel
Qualification
= Pre-production material
= Production material
Q
S
Product Revision
= 2 Alphanumeric characters
xn
Temperature Range
= Ambient (0 - 55° C)
A
C
E
= Commercial (0 - 70° C)
= Extended (-40 - +85° C)
Internal Package Designator
= LQFP
L
= PLCC
P
N
Q
H
T
= DIP
= PQFP
= QFP with heat spreader
= TQFP
= BGA
B
C
E
K
= CBGA
= TBGA
= HSBGA (BGA with heat slug)
xxxx
= 3-5 Digit Alphanumeric Product Code
IXA Product Prefix
= PHY layer device
LXT
IXE
IXF
IXP
= Switching engine
= Formatting device (MAC)
= Network processor
Intel Package Designator
DJ
FA
FL
FW
HB
HD
HF
HG
S
= LQFP
= TQFP
= PBGA (<1.0 mm pitch)
= PBGA (1.27 mm pitch)
= QFP with heat spreader
= QFP with heat slug
= CBGA
= SOIC
= QFP
GC
N
= TBGA
= PLCC
Datasheet
73
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver
74
Datasheet
Document #: 249186
Revision #: 003
Rev. Date: August 7, 2002
®
Intel LXT971A, LXT972A,
LXT972M Single-Port 10/100
Mbps PHY Transceivers
Specification Update
January 2005
®
Notice: The Intel LXT971A, LXT972A, LXT972M Single-Port 10/100 Mbps PHY Transceivers
may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are documented in this specification
update.
Order Number: 249354-010
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® LXT971A, LXT972A, LXT972M Single-Port 10/100 Mbps PHY Transceivers may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation
®
2
Intel LXT971A, LXT972A, and LX972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Contents
Revision History......................................................................................... 5
Preface....................................................................................................... 8
Summary Table of Changes..................................................................... 10
Identification Information.......................................................................... 13
Errata ....................................................................................................... 16
Specification Changes ............................................................................. 22
Specification Clarifications ....................................................................... 23
Documentation Changes ......................................................................... 24
Sightings .................................................................................................. 26
®
Intel LXT971A, LXT972A, and LX972M Transceivers Specification Update
3
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
®
4
Intel LXT971A, LXT972A, and LX972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Revision History
Revision History
Revision Number: 010
Revision Date: January 13, 2005
Page #
Description
Revised Figure 1, “Example of Pb-Free LQFP Package for Intel® LXT971A, LX972A, and LXT972M
Transceivers” and descriptive text that references this figure.
13
14
Revised Figure 2, “Example of LQFP Package for Intel® LXT971A, LXT972A, and LXT972M
Transceivers” and descriptive text that references this figure.
24
25
Revised Table 2, “Product Information”.
Revised Figure 5, “Ordering Information - Sample”.
Revision Number: 009
Revision Date: September 17, 2004
Page #
Description
-
Added the LXT972M Single-Port 10/100 Mbps PHY Transceiver where appropriate.
Revised Erratum item 4. Clarified workaround.
17
18
19
19
19
26
Revised Erratum item 5. Moved previous Note to Errata table.
Revised Erratum item 9. Moved previous Note to Errata table.
Revised Erratum item 10. Moved previous Note to Errata table.
Revised Erratum item 11. Moved previous Note to Errata table.
Revised “Sightings” section.
Revision Number: 008
Revision Date: December 2, 2003
Page #
Description
10
10
12
17
17
18
Added Errata items 13 through 15 to “Errata” table.
Removed Item 1 in “Specification Clarifications” table.
Modified steppings table under “Identification Information” section (added JTAG ID information).
Added Erratum 13: “Changing Advertised Duplex While Link Is Up” to “Errata” section.
Added Erratum 14: “Far-End Fault Reporting” to “Errata” section.
Added Erratum 15: “Detection of Illegal Symbols After SSD” to “Errata” section.
Incorporated tables under “Specification Clarifications” into the LXT971A and LXT972A Datasheets
and removed from this document.
20
22
Incorporated “Item 3: Increased MII Drive Strength” under the “Addenda” section into the LXT971A
and LXT972A Datasheets and removed from this document.
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
5
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Revision History
Revision Number: 007
Revision Date: May 17, 2002
Page #
Description
4
8
Updated “Affected Documents” Table.
Updated “Codes Used in Summary Table”.
7
Updated “Errata” Listing.
12
16
Added Erratum: “Switching Clocks from 100 Mbps to 10 Mbps Prior to End of Packet”.
Added Addendum: ”Increased MII Drive Strength”.
Revision Number: 006
Revision Date: August 17, 2001
Page #
Description
7
Documentation Changes: Modified to reflect document rev numbers.
Modified Absolute Maximum Ratings table.
14
Revision Number: 005
Revision Date: June 27, 2001
Page #
Description
16
Addenda: Clarified Description 1.
Revision Number: 004
Revision Date: June 20, 2001
Page #
Description
15
Added Product Ordering Information
Revision Number: 003
Revision Date: May 9, 2001
Page #
Description
7
Errata 7, 9, 10, 11, 12 were fixed in Stepping 2. Removed “Xs” for correct status.
Revision Number: 002
Revision Date: March 20, 2001
Page #
Description
8
Updated “Markings” table with Manufacturer’s Revision Code information.
Replaced text with “None” for Workaround under Errata 9.
Added BSDL text to Workaround under Errata 11.
11
12
®
6
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Revision History
Date
Version
Page #
Description
January 15, 2001
August 24, 2000
June 27, 2000
001
2.11
2.01
1.n1
-
-
-
-
Converted to Intel format (no technical or material changes).
Added errata for Stepping 2.
Reformatted and added errata for Stepping 1.
Various versions covered silicon Stepping 0.
November 5, 1999
1. Level One document version number. As of 1/ 15,/01, this document replaces the Level One document.
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
7
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Preface
Preface
This document is an update to the specifications contained in the Affected Documents/Related
Documents table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system manufacturers and
software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification update and are
no longer published in other documents.
This document may also contain information that was not previously published.
Stepping 2 devices are labeled as LXT971A, LXT972A, and LXT972M Transceivers.
Affected Documents/Related Documents
Title
Order
Intel® LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Intel® LXT972A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
Intel® LXT971A/972A 3.3V PHY Transceivers Design and Layout Guide Application Note
Intel® LXT971A — LXT970A-to-LXT971A Migration Application Note
249185
249186
249016
249028
Intel® LXD971B Demo Board for 3.3V 10/100 Applications (Board Rev A1) Development Kit
Manual
249246
249247
Intel® LXD971L Demo Board for 3.3V 10/100 Applications (Board Rev B2) Development Kit
Manual
Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet
Intel® LXT972M Transceiver Demo Board (Board Rev A1)
302875
303125
®
8
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Preface
Nomenclature
Errata are design defects or errors. These may cause the behaviors of the following to deviate from
published specifications:
• LXT971/LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver (called hereafter the
LXT971A Transceiver)
• LXT972/LXT972A 3.3V Dual-Speed Fast Ethernet Transceiver (called hereafter the
LXT972A Transceiver)
• LXT972M Single-Port 10/100 Mbps PHY Transceiver (called hereafter the LXT972M
Transceiver).
Hardware and software designed to be used with any given stepping must assume that all errata
documented for that stepping are present on all devices.
Specification Changes are modifications to the current published specifications. These changes
will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation. These clarifications will be incorporated in
any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current published
specifications. These will be incorporated in any new release of the specification.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a particular
stepping is no longer commercially available. Under these circumstances, errata removed from the
specification update are archived and available upon request. Specification changes, specification
clarifications and documentation changes are removed from the specification update when the
appropriate changes are made to the appropriate product specification or user documentation
(datasheets, manuals, and so on).
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
9
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Summary Table of Changes
Summary Table of Changes
The following table indicates the errata, specification changes, or specification clarifications which
apply to the LXT971A, LXT972A, and LXT972M Transceivers. Intel may fix some of the errata in
a future stepping of the component, and account for the other outstanding issues through
documentation or specification changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X:
Errata that applies to this stepping.
(No mark) or (Blank box): This erratum is fixed in stepping indicated. Specification Change or
Specification Clarification does not apply to this stepping.
Page
(Page):
Page location of item in this document.
Status
Doc:
Document change or update will be implemented.
This erratum may be fixed in a future stepping of the product.
This erratum has been previously fixed.
Plan Fix:
Fixed:
No Fix:
There are no plans to fix this erratum.
Row
Change bar to left of table row indicates this erratum is either new or
modified from the previous version of the document.
®
10
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Summary Table of Changes
Errata
LXT971A/LXT972A
Transceiver
Steppings1,2,3
No.
Page
Status
ERRATA
0
1
2
“Incorrect Auto-Negotiation Link Partner Base Page
Ability Register”
1
X
13
Fixed
2
3
4
5
6
7
8
X
X
X
X
X
X
X
13
13
13
14
14
15
15
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
“Incorrect Auto-Negotiation Next Page”
“Incorrect Remote Fault”
“Incorrect Auto-Negotiation Duplex Status”
“Incorrect JTAG Revision Code”
“Incorrect Duplex - Collision LED Display”
“Incorrect Activity LED Display”
X
X
X
“MII Pins Not Three-Stateable”
“100 M External Loopback Using Short Cable
Length”
9
X
X
15
Fixed
10
11
X
X
X
X
16
16
Fixed
Fixed
“10BASE-T Data Inversion”
“Power Cycling and JTAG TRST Reset Pin”
“Switching Clocks from 100 Mbps to 10 Mbps Prior
to End-of-Packet”
12
X
X
16
Fixed
13
14
15
X
X
X
X
X
X
X
X
X
17
17
17
NoFix
NoFix
NoFix
“Changing Advertised Duplex While Link Is Up”
“Far-End Fault Reporting”
“Detection of Illegal Symbols After SSD”
1. Refer to “Markings” on page 12 for codes to identify various silicon steppings.
2. Devices with an A suffix (such as the LXT971A and LXT972A Transceiver) are Stepping 2.
3. The LXT972M Transceiver is available only as Stepping 2.
Specification Changes
Steppings
No.
Page
Status
SPECIFICATION CHANGES
#
#
#
None for this revision of this specification update.
Specification Clarifications
Steppings
No.
Page
Status
SPECIFICATION CLARIFICATIONS
None for this revision of this specification update.
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
11
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Summary Table of Changes
Documentation Changes
No.
Datasheet Revision
Page
Status
Documentation Changes
LXT971A - 002
LXT972A - 003
Table 1, “Product Information” and Figure 1, “Ordering
Information - Sample”
1
21
Doc
Sightings
LXT971A/LXT972A
Transceiver
Steppings1,2
No.
Page
Status
Sightings
0
1
2
1
2
X
X
X
X
13
13
Fixed
Fixed
Sighting 1, “100BASE-TX Receive Jitter Tolerance"
Sighting 2, “10BASE-T Jitter Tolerance"
1. Refer to “Markings” on page 12 for codes to identify various silicon steppings.
2. The LXT972M Transceiver is available only as Stepping 2.
®
12
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Identification Information
Identification Information
Markings
This section shows the markings for the LXT971A, LXT972A, and LXT972M Transceivers.
The LXT971A, LXT972A, and LXT972M Transceivers are available in both Low Profile Quad
Flat Pack (LQFP) and Pb-free LQFP packages. Figure 1 shows a sample Pb-free LQFP package for
the LXT971A, LXT972A, and LXT972M Transceivers.
®
Figure 1. Example of Pb-Free LQFP Package for Intel LXT971A, LX972A, and LXT972M
Transceivers
Part Number
W J 9 7 X X A 4
FPO Number
X X X X X X X X
( B L A N K
L I N E )
‘
e3
Y Y
Lead-Free
Indication
M C
Year
Pin 1
B3768-05
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
13
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Identification Information
Figure 2 shows a sample LQFP package for the LXT971A, LXT972A, and LXT972M
Transceivers.
Note: In contrast to the Pb-free LQFP package, the LQFP package does not have the “e3” symbol in the
last line of type on the package.
®
Figure 2. Example of LQFP Package for Intel LXT971A, LXT972A, and LXT972M Transceivers
Part Number
D J 9 7 X X A 4
FPO Number
X X X X X X X X
( B L A N K
L I N E )
‘
Y Y
M C
Year
Pin 1
B3771-03
®
14
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Identification Information
Figure 3 shows the LQFP package for previous revisions of the LXT971A and LXT972A
Transceivers.
®
Figure 3. Package for Previous Revision of Intel LXT971A and LXT972A Transceivers
Revision#
Part#
LOT#
FPO#
LXT97xAxx
xxxxxxxxxxxxxx
xxxxxxxxx
xx
Figure 4 shows the LQFP package for previous revisions of the LXT971A and LXT972A
Transceivers. (This figure is for reference only.).
Figure 4. Package for Level One LXT971A and LXT972A Transceivers (Reference Only)
ꢀ
Date Code
Trace Code
YYWW
xxxx
LXT97xAxx
xxxxxxxxx
Part#
LOT#
In the datasheets for the LXT971A, LXT972A, and LXT972M Transceivers, the silicon stepping is
referred to as “Manufacturer’s Revision Number.” Software can read the silicon stepping number
from Register bits 3.3:0. Table 1 lists the manufacturer’s revision number, trace codes, and JTAG
version IDs for LXT971A, LXT972A, and LXT972M Transceiver steppings.
Table 1. Revision Numbers, Trace Codes, and JTAG Versions IDs
Manufacturer’s
Stepping
Revision Number
Trace Codes1
JTAG Version ID3
Revision Number2
0
1
2
A1
A2
A4
xxAx
xxBx
xxDx
0000
0001
0010
0000
0001
0010
1. The letter “x” indicates an insignificant variable.
2. The value of the revision number is from register bits 3.3:0. For details, see the datasheets for the
LXT971A, LXT972A, and LXT972M Transceivers.
3. For details on the JTAG version ID, see the Device ID Register tables in the datasheets for the LXT971A,
LXT972A, and LXT972M Transceivers.
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
15
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Errata
Errata
1.
Incorrect Auto-Negotiation Link Partner Base Page Ability Register
Problem:
Upon completing the parallel detection function, the Auto-Negotiation Link Partner Base Page
Ability Register (Register 5) should be updated to reflect the link partner’s capability. Register 5 is
not updated correctly and always reads 0000h.
Workaround: The Status Register #2 (Register 17) is properly updated with the arbitrated link status information
and can be used to identify link speed and duplex status.
Status:
This erratum has been previously fixed.
2.
Incorrect Auto-Negotiation Next Page
Problem:
The Auto-Negotiation Next Page state machine functions incorrectly and does not support Next
Page operations.
Workaround: Bit 4.15 in the Auto-Negotiation Advertisement Register must be set to 0 (port has no ability to
send multiple pages).
Status:
This erratum has been previously fixed.
3.
Incorrect Remote Fault
Problem:
In fiber mode, the Remote Fault bit (Register bit 1.4) in MII Status Register #1 is used to report
receipt of the Far End Fault Indication (FEFI) code to the MAC. The Remote Fault bit fails to
indicate receipt of the FEFI code under certain conditions.
This occurs only when the following conditions are true:
• The device is operating in fiber mode, AND
• The device hardware configuration is set to enable auto-negotiation.
Workaround: Strap the LED/CFG1 pin to ground to disable auto-negotiation.
Status:
This erratum has been previously fixed.
®
16
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Errata
4.
Incorrect Auto-Negotiation Duplex Status
Problem:
The LXT971A and LXT972A Transceivers fail to update the initial control setting for full-duplex
or half-duplex operation (Register bit 0.8) after link is established. Under certain conditions, this
can cause incorrect reporting of duplex status and collision events. This problem occurs under the
following conditions:
• The LXT971A and LXT972A Transceivers are initially set for full-duplex operation, AND
• The LXT971A and LXT972A Transceivers establish a half-duplex link through auto-
negotiation or parallel detection
OR
• The LXT971A and LXT972A Transceivers is initially set for half-duplex operation, AND
• The LXT971A and LXT972A Transceivers establish a full-duplex link through auto-
negotiation or parallel detection.
Implication:
In the first case (half-duplex link established while control register is set for full-duplex), the
LXT971Aand LXT972A Transceivers do the following:
• Function as a full-duplex port
• Indicate full-duplex through LED and Register bit 0.8
• Indicate half-duplex through Register bit 17.9
• Do not indicate collision (through the LED, MII COL signal, or Register bit 17.11) when
transmitting and receiving concurrently
In the second case (full-duplex link established while control register is set for half-duplex), the
LXT971A and LXT972A Transceivers do the following:
• Function as a half-duplex port
• Indicate half-duplex through the LED
• Indicate full-duplex through Register bit 17.9
• Indicate collision (through LED, MII COL signal, and Register bit 17.11) when transmitting
and receiving concurrently
Workaround: Set Status Register #2 (Register bit 17.9) to update the duplex status in the Control Register
(Address 0). The Status Register #2 (Address 2) is updated with the correct duplex status when
auto-negotiation is completed. Each time link is established, the duplex status in Register bit 17.9
can be used to update the duplex mode in the Control Register (Register bit 0.8).
Status:
This erratum has been previously fixed.
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
17
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Errata
5.
Incorrect JTAG Revision Code
Problem:
LXT971A and LXT972A Transceivers (A2) JTAG Device ID is as follows - 0001 03CB 1110 111
1110 1
As per the standard, the Jedec Continuation Character (Register bit 11:8) for the Intel devices
should have been 0000 instead of 1110.
Implication:
JTAG boundary scan receives an incorrect JTAG ID for the LXT971A and LXT972A Trans-
ceivers.
Workaround: Use a continuation character of 1110 when addressing an LXT971A Transceiver Stepping 1.
Status:
This erratum has been previously fixed.
6.
Incorrect Duplex - Collision LED Display
Problem:
When the port LED is configured to indicate Duplex and Collision through the LED Configuration
Register (Address 20), the LED does not indicate Collision when transmitting and receiving in a
half-duplex link.
Workaround: Configure a separate LED for Collision only. A dedicated LED properly indicates a collision is
occurring.
Status:
This erratum has been previously fixed.
7.
Incorrect Activity LED Display
Problem:
With pulse stretching enabled, port activity is indicated with a slow blinking rate on the activity
LED when the port is in full-duplex and the port transmit and receive traffic has the same packet
size and inter-packet gap (IPG) for an extended period of time. A correct indication is for the
activity LED to remain active when continuously transmitting and receiving.
The activity LED resumes normal operation if either packet size or IPG is altered.
Implication:
The activity LED indication will not match the traffic rate at the port. Only the Activity LED
behavior is affected. Neither transmit nor receive status LED functionality are affected.
The activity LED operation has no impact on data reliability.
Workaround: Use the following steps for a possible workaround:
1. Use either transmit or receive status instead of activity as the LED indication.
2. Logically ‘OR’ transmit status and receive status to generate an activity indicator. This
workaround requires external hardware to complete the ‘OR’ function.
3. Add external pulse stretching through a PLD while disabling on-chip pulse stretching through
Register 20 (Register bit 20.1 = 0). This workaround requires external hardware and
manageability through the MDIO interface. Also, because pulse stretching is global to the
device, external logic must be added for any LED signal that requires stretching.
4. Display both transmit and receive status individually.
This erratum has been previously fixed.
Status:
®
18
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Errata
8.
MII Pins Not Three-Stateable
Problem:
In hardware power-down mode, the receive clock MDINT pins do not go into a high-impedance
state or are not three-stated.
Implication:
In hardware power-down mode, the receive clock (RxClk) and the MDINT pins are continuously
driven. The transmit clock will be in a true three-state condition. However, the LXT971A and
LXT972A Transceivers continue to source a receive clock.
Workaround: None.
Status:
This erratum has been previously fixed.
9.
100 M External Loopback Using Short Cable Length
Problem:
Link may not occur in applications requiring a short external looping plug (looping TPFO to TPFI)
with cable lengths typically less than 2 feet.
Implication:
During external loopback operations requiring a line-loop length less than two feet, the LXT971A
and LXT972A Transceivers input-receiver reference levels may incorrectly slice the twisted-pair
signal, causing a loss of link.
Workaround: None.
Status:
This erratum has been previously fixed.
10.
10BASE-T Data Inversion
Problem:
If jitter on the twisted-pair data occurs within a time window relative internally to the DPLL
Reference Clock and remains constant, inverted RxData can occur.
Implication:
When the receive twisted-pair data jitters, the LXT971A and LXT972A Transceivers may pass
errored data to the Reconciliation Sublayer. This errored data would be calculated as CRC errors at
the MAC and the RXER signal/bit would be active.
Workaround: None.
Status:
This erratum has been previously fixed.
11.
Power Cycling and JTAG TRST Reset Pin
Problem:
Power-on cycling may cause the LXT971A and LXT972A Transceivers to hang in an unknown
state due to the improper reset of some internal JTAG control flip-flops.
Implication:
Some internal JTAG flip-flops may not be reset properly, causing the input and output steering
muxes to be selected incorrectly. This incorrect selection may disable any of the digital, MII signal
outputs and inputs.
Workaround: Designs not using JTAG should tie the TRST pin directly to GND.
Designs using the 5-signal option should tie the TRST pin to GND through a resistor. The
suggested value for this resistor is 20 kΩ. A 20 kΩ resistor to GND is strong enough to pull down
the internal, weak pull-up to a logic 0 for normal operation. This pull down also allows a JTAG tap
controller to operate successfully and overcome the pull-up and pull-down resistors.
Designs using the 4-signal option and not using the TRST pin for reset should use a 20 kΩ pull-
down resistor from TRST to GND and control the JTAG TRST pin, accordingly.
Designs using the LXT971A or LXT972A Transceivers require a new BSDL file that may be
found on the Intel website (www.intel.com).
Status:
This erratum has been previously fixed.
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
19
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Errata
12.
Switching Clocks from 100 Mbps to 10 Mbps Prior to End-of-Packet
Problem:
Switching clocks from 100 Mbps to 10 Mbps prior to the End-of-Packet (EOP), as the PLL
transitions to its reset state, can cause the output to become random and unknown, and result in the
corruption of the last nibble of the CRC in the receive packet.
Implication:
A CRC error occurs randomly on a small percentage of devices and can result in an error rate up to
10 ppm.
Workaround: None.
Status:
This erratum has been previously fixed.
13.
Changing Advertised Duplex While Link Is Up
Problem:
Writing to Register bits 4.9:5, which control duplex mode advertisement while link is up and auto-
negotiation is enabled, immediately changes the PHY mode of operation to the new duplex mode.
When written, the values in this register are not intended to affect PHY operation until a new auto-
negotiation cycle is completed.
Implication:
A possible mixed-duplex operation will exist during the time between Register bits 4.9:5 writes
and the start of a new auto-negotiation process.
Workaround: Write Register bits 4.9:5 immediately before the start of a new auto-negotiation process.
Status:
There are no plans to fix this erratum.
14.
Far-End Fault Reporting
Problem:
If a link partner continuously sends successive Far-End Fault (FEF) codes (three sets of 84 1s
followed by a 0), the LXT971A/LXT972A Transceiver sets the Remote Fault bit High (Register bit
1.4 = 1) and drops link (Register bit 1.2 = 0). Register 1.4 is cleared after a Read and is not set High
again while the Far-End Fault signal is present.
Implication:
Implication: If the MAC reads Register bit 1.4 more than once under a continuous Far-End Fault
condition, a Far-End Fault is not indicated after the first Read.
Workaround: Once a remote fault has been indicated by Register bit 1.4 = 1, the following sequence can be used
to monitor the remote-fault status.
Managed Systems:
1. Write Register 0 = 0x6100. This forces the port to 100 Mbps full-duplex internal loopback,
link is up, Register bit 1.2 = 1, and Register bit 1.4 = 0.
2. Wait approximately 100 mS.
3. Write Register 0 = 0x2100. This forces the port into 100 Mbps full-duplex. If Far-End Fault is
present, Register bit 1.4 = 1 indicates Far-End Fault and Register bit 1.2 = 0 indicates link is
down.
Status:
There are no plans to fix this erratum.
®
20
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Errata
15.
Detection of Illegal Symbols After SSD
Problem:
An illegal symbol placed immediately after the SSD (preamble after JK) is not detected. However,
any subsequent corrupt symbol will be detected.
Standard Frame Contents:
Location of Symbol
/J/K/5/5/5/5/5/5/5/5/5/5/5/5/5/5/5/D/destination address, source address, . . . CRC/T/R/
SSD
Preamble
SOF
ESD
SSD – Start-of-Stream Delimiter
SOF – Start-of-Frame Delimiter
ESD – End-of-Stream Delimiter
Implication:
Implication: RXER does not assert if this symbol location is corrupted. However, an error in this
location does not affect packet integrity.
Workaround: Use the MAC layer protocol to detect corrupt symbols in the packet.
Status:
There are no plans to fix this erratum.
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
21
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Specification Changes
Specification Changes
There are no specification changes.
®
22
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Specification Clarifications
Specification Clarifications
There are no specification clarifications.
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
23
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Documentation Changes
Documentation Changes
Table 2. Product Information
Number
DJLXT971ALC.A4
Revision
Qualification
Tray MM
Tape and Reel MM
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
S
S
S
S
S
S
S
S
S
S
834105
835676
834103
834104
834109
864768
864115
857342
857343
857341
834916
835791
834926
835080
834917
864769
864101
857344
857346
857345
DJLXT971ALE.A4
FLLXT971ABC.A4
FLLXT971ABE.A4
DJLXT972ALC.A4
DJLXT972MLC.A4
WJLXT972MLC.A4 (Pb-free)
WJLXT971ALC.A4 (Pb-free)
WJLXT971ALE.A4 (Pb-free)
WJLXT972ALC.A4 (Pb-free)
®
24
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Documentation Changes
Figure 5 shows how to use the ordering information.
Figure 5. Ordering Information - Sample
DJ
LXT
971A
L
C
A4
S
E001
Build Format
E000 = Tray
E001 = Tape and reel
Qualification
Q
S
= Pre-production material
= Production material
Product Revision
= 2 Alphanumeric characters
xn
Temperature Range
= Ambient (0 - 55° C)
A
= Commercial (0 - 70° C)
= Extended (-40 - +85° C)
C
E
Internal Package Designator
= LQFP
L
= PLCC
= DIP
= PQFP
= QFP with heat spreader
P
N
Q
H
T
= TQFP
= BGA
= CBGA
= TBGA
= HSBGA (BGA with heat slug)
B
C
E
K
xxxx
= 3-5 Digit Alphanumeric Product Cod
IXA Product Prefix
= PHY layer device
LXT
= Switching engine
= Formatting device (MAC)
IXE
IXF
= Network processor
IXP
Intel Package Designator
DJ
WJ
FA
FL
FW
HB
HD
HF
HG
S
= LQFP
= LQFP (lead-free)
= TQFP
= PBGA (<1.0 mm pitch)
= PBGA (1.27 mm pitch)
= QFP with heat spreader
= QFP with heat slug
= CBGA
= SOIC
= QFP
= TBGA
= PLCC
GC
N
B3500-05
®
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
25
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
Sightings
Sightings
"Sightings" are descriptions of specific device behaviors or interaction behaviors with other
devices, originating from a variety of sources internal and external to Intel. Sightings are not device
errata, but specific behaviors that may be of interest to customers. Internal sources can include
product validation and product test. External sources can include product developers and
customers.
1.
100BASE-TX Receive Jitter Tolerance
Description:
If a receive-link partner operating in 100BASE-TX generates transmit jitter greater than the IEEE
standard, the LXT971A and LXT972A Transceivers may produce errors within the Reconciliation
Sublayer, which can result in a failure to link or to sustain a link. The LXT971A and LXT972A
Transceivers needed to be enhanced to allow greater margin to the IEEE standard. The identified
change would allow greater design flexibility.
Note: Customers are advised that reliance on such an out-of-margin performance is at their own risk.
Status:
Implemented in Stepping 2.
2.
10BASE-T Jitter Tolerance
Description:
In some 10BASE-T input jitter applications, the LXT971A and LXT972A Transceivers margin
may be close to the IEEE standard for input jitter tolerance. The LXT971A and LXT972A
Transceivers needed to be enhanced to be optimally centered for 10BASE-T input jitter tolerance.
The identified change would allow greater design flexibility; however, customers are advised that
reliance on such out-of-margin performance is at their own risk.
Status:
Implemented in Stepping 2.
®
26
Intel LXT971A, LXT972A, and LXT972M Transceivers Specification Update
Document Number: 249354
Revision Number: 010
Revision Date: January 13, 2005
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