5962-9859101NXB [INTERSIL]
14-Bit, 5 MSPS, Military A/D Converter; 14位， 5 MSPS ，军事A / D转换器
| 型号： | 5962-9859101NXB |
| 厂家： | 
Intersil |
| 描述： | 14-Bit, 5 MSPS, Military A/D Converter |
| 文件： | 总8页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5905N/QML
TM
Data Sheet
July 1999
File Number 4718.1
14-Bit, 5 MSPS, Military A/D Converter
Features
The HI5905N/QML is a monolithic, 14-bit, 5MSPS Analog-
to-Digital Converter fabricated in an advanced BiCMOS
process. It is designed for high speed, high resolution
applications where wide bandwidth, low power consumption
and excellent SINAD performance are essential. With a
100MHz full power input bandwidth and high frequency
accuracy, the converter is ideal for many Military types of
communication systems employing digital IF architectures.
• QML Compliant per SMD 5962-9859101NXB
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .5MSPS
• Low Power at 5MSPS. . . . . . . . . . . . . . . . . 400mW (Max)
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• SINAD at 1MHz . . . . . . . . . . . . . . . . . . . . . . >69dB (Min)
• Internal Voltage Reference
The HI5905N/QML is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold amplifier (S/H). Consuming 350mW (typ)
power at 5MSPS, the HI5905N/QML has excellent dynamic
performance over the full Military temperature range.
• TTL Compatible Clock Input
• CMOS Compatible Digital Data Outputs
Data output latches are provided which present valid data to
the output bus with a data latency of only 4 clock cycles.
Applications
• Digital Communication Systems
• Undersampling Digital IF
• Asymmetric Digital Subscriber Line (ADSL)
• Document Scanners
Specifications for QML devices are controlled by the
Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HI5905N/QML
are contained in SMD 5962-98591. That document may
be easily downloaded from our website.
• Reference Literature
http://www.Intersil.com/data/sm/index.htm
- AN9214, Using Intersil High Speed A/D Converters
- AN9785, Using the Intersil HI5905 EVAL2 Evaluation
Board
Pinout
HI5905 (MQFP) (MO-108AA-2 ISSUE A)
TOP VIEW
Ordering Information
ORDERING
NUMBER
INTERNAL INTERSIL
MKT. NUMBER
TEMP.
o
RANGE( C)
-55 to 125
25
5962-9859101NXB
HI5905EVAL2
HI5905N/QML
Low Frequency Platform
44 43 42 41 40 39 38 37 36 35 34
NC
NC
D3
D4
D5
D6
D7
NC
DV
1
33
32
31
30
29
2
3
4
5
6
7
8
9
D
GND1
NC
AV
A
CC
28
27
26
25
24
23
GND
NC
CC2
NC
D
GND2
D8
D9
NC
V
IN+
10
11
V
IN-
DC
V
12 13 14 15 16 17 18 19 20 21 22
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-724-7143 | Copyright © Intersil Corporation 1999
4-1
Functional Block Diagram
V
V
BIAS
DC
CLOCK
REF
CLK
-
IN
V
+
IN
V
V
ROUT
RIN
S/H
STAGE 1
DV
CC2
4-BIT
FLASH
4-BIT
DAC
+
D13 (MSB)
D12
D11
D10
D9
-
∑
X8
D8
STAGE 4
D7
D6
D5
4-BIT
FLASH
4-BIT
DAC
D4
+
D3
-
∑
D2
X8
D1
D0 (LSB)
STAGE 5
4-BIT
FLASH
D
GND2
AV
A
DV
D
GND1
CC
GND
CC1
Typical Application Schematic
(LSB) D0 (38)
D0
D1 (37)
(13)
D1
V
ROUT
D2 (36)
D3 (33)
D2
V
(14)
RIN
D3
A
(6)
GND
D4 (32)
D5 (31)
D6 (30)
D7 (29)
D8 (25)
D9 (24)
D10 (21)
D11 (20)
D12 (19)
D4
A
A
(15)
D
BNC
GND
GND
GND
D5
D
D
D
(3)
GND1
GND1
GND2
D6
(42)
(26)
D7
D8
V
+
-
V
+ (9)
IN
D9
IN
D10
D11
D12
D13
10µF AND 0.1µF CAPS ARE PLACED
AS CLOSE TO PART AS POSSIBLE
V
V
(11)
DC
- (10)
V
IN
IN
(MSB) D13 (18)
CLK (40)
CLOCK
DV
DV
(41)
(43)
(27)
CC1
AV
AV
(5)
CC
CC
CC1
CC2
(16)
DV
+5V
+5V
+
+
0.1µF
0.1µF
10µF
10µF
HI5905
4-2
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
S
H
S
H
S
H
S
H
S
H
S
H
S
H
S
H
N + 6 N + 6
N - 1
N - 1
N
N
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
N + 4
N + 4
N + 5
N + 5
INPUT
S/H
1ST
STAGE
B ,
B
B
B
B
B
B
1, N + 5
1
N - 1
1, N
1, N + 1
1, N + 2
1, N + 3
1, N + 4
2ND
STAGE
B ,
B ,
B ,
B ,
B ,
B ,
B ,
2 N + 4
2
N - 2
2
N - 1
2
N
2
N + 1
2
N + 2
2
N + 3
3RD
STAGE
B ,
B ,
B ,
B ,
B ,
B ,
B ,
3 N + 4
3
N - 2
3
N - 1
3
N
3
N + 1
3
N + 2
3
N + 3
4TH
STAGE
B ,
B ,
B ,
B ,
B ,
B ,
B ,
4 N + 3
4
N - 3
4
N - 2
4
N - 1
4
N
4
N + 1
4
N + 2
5TH
STAGE
B ,
B ,
B ,
B ,
B ,
B ,
B ,
5
5
N - 3
5
N - 2
5
N - 1
5
N
5
N + 1
5
N + 2
N + 3
DATA
OUTPUT
D
D
D
D
D
D
N + 1
D
N - 4
N - 3
N - 2
N - 1
N
N + 2
t
LAT
NOTES:
1. S : N-th sampling period.
3. B
: M-th stage digital output corresponding to N-th sampled input.
4. D : Final data output corresponding to N-th sampled input.
N
M, N
2. H : N-th holding period.
N
N
FIGURE 1. INTERNAL CIRCUIT TIMING
ANALOG
INPUT
t
AP
t
AJ
CLOCK
INPUT
1.5V
1.5V
t
OD
t
H
3.5V
1.5V
DATA
DATA N-1
DATA N
OUTPUT
FIGURE 2. INPUT-TO-OUTPUT TIMING
4-3
Detailed Description
Pin Descriptions
PIN #
NAME
DESCRIPTION
Theory of Operation
1
NC
No Connection
The HI5905 is a 14-bit fully differential sampling pipeline A/D
converter with digital error correction. Figure 3 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
2
NC
No Connection
3
D
Digital Ground
GND1
NC
4
No Connection
clock which is a non-overlapping two phase signal, φ and
1
5
AV
Analog Supply (5.0V)
Analog Ground
CC
φ , derived from the master clock. During the sampling
2
phase, φ , the input signal is applied to the sampling
6
A
GND
1
capacitors, C . At the same time the holding capacitors, C ,
S
H
7
NC
NC
No Connection
are discharged to analog ground. At the falling edge of φ
1
8
No Connection
the input signal is sampled on the bottom plates of the
9
V
+
Positive Analog Input
Negative Analog Input
DC Bias Voltage Output
No Connection
IN
sampling capacitors. In the next clock phase, φ , the two
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
V -
IN
bottom plates of the sampling capacitors are connected
together and the holding capacitors are switched to the op
amp output nodes. The charge then redistributes between
V
DC
NC
C
and C completing one sample-and-hold cycle. The
S
H
V
Reference Voltage Output
Reference Voltage Input
Analog Ground
ROUT
output is a fully-differential, sampled-data representation of
the analog input. The circuit not only performs the sample-
and-hold function but will also convert a single-ended input
to a fully-differential output for the converter core. During the
V
RIN
A
GND
AV
CC
Analog Supply (5.0V)
No Connection
sampling phase, the V pins see only the on-resistance of a
IN
NC
switch and C . The relatively small values of these
S
components result in a typical full power input bandwidth of
100MHz for the converter.
D13
D12
D11
D10
NC
Data Bit 11 Output (MSB)
Data Bit 11 Output
Data Bit 11 Output
Data Bit 10 Output
No Connection
φ1
φ1
C
H
φ1
φ2
φ1
C
C
S
S
V
+
IN
NC
No Connection
- +
+ -
V
+
-
OUT
D9
Data Bit 9 Output
Data Bit 8 Output
Digital Ground
V
OUT
V
-
IN
D8
D
C
GND2
H
φ1
φ1
DV
Digital Supply (5.0V)
No Connection
CC2
NC
FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD
D7
D6
D5
D4
D3
NC
NC
D2
D1
D0
NC
CLK
Data Bit 7 Output
Data Bit 6 Output
Data Bit 5 Output
Data Bit 4 Output
Data Bit 3 Output
No Connection
As illustrated in the functional block diagram and the timing
diagram in Figure 1, four identical pipeline subconverter
stages, each containing a four-bit flash converter, a four-bit
digital-to-analog converter and an amplifier with a voltage
gain of 8, follow the S/H circuit with the fifth stage being only
a 4-bit flash converter. Each converter stage in the pipeline
will be sampling in one phase and amplifying in the other
clock phase. Each individual sub-converter clock signal is
offset by 180 degrees from the previous stage clock signal,
with the result that alternate stages in the pipeline will
perform the same operation.
No Connection
Data Bit 2 Output
Data Bit 1 Output
Data Bit 0 Output (LSB)
No Connection
The output of each of the four-bit subconverter stages is a
four-bit digital word containing a supplementary bit to be
used by the digital error correction logic. The output of each
subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the four
Input Clock
DV
Digital Supply (5.0V)
Digital Ground
CC1
D
GND1
DV
Digital Supply (5.0V)
No Connection
CC1
NC
4-4
identical four-bit subconverter stages with the corresponding
output of the fifth stage flash converter before applying the
twenty bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final
fourteen bit digital data output of the converter.
common mode voltage range of 1.0V to 4.0V. The
performance of the ADC does not change significantly with
the value of the analog input common mode voltage.
V
+
V
IN
IN
HI5905
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 4th cycle of the clock after the analog
sample is taken. This time delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital output data is
synchronized to the external sampling clock with a latch. The
digital output data is available in two’s complement binary
format (see Table 1, A/D Code Table).
V
V
DC
-V
IN
-
IN
FIGURE 4. AC COUPLED DIFFERENTIAL INPUT
A 2.3V DC bias voltage source, V , half way between the
DC
top and bottom internal reference voltages, is made
available to the user to help simplify circuit design when
using a differential input. This low output impedance voltage
source is not designed to be a reference but makes an
excellent bias source and stays within the analog input
common mode voltage range over temperature.
Internal Reference Generator, V
and V
RIN
ROUT
The HI5905 has an internal reference generator, therefore, no
external reference voltage is required. V must be
ROUT
when using the internal reference voltage.
connected to V
RIN
The difference between the converter’s two internal voltage
references is 2V. For the AC coupled differential input, (Figure
The HI5905 can be used with an external reference. The
converter requires only one external reference voltage
4), if V is a 2V
sinewave with -V being 180 degrees out of
IN P-P
IN
connected to the V
pin with V
left open.
RIN
ROUT
, equal to 4.0V, connected
. Internal to the converter, two reference voltages of
phase with V , then V + is a 2V
IN IN P-P
sinewave riding on a DC
sinewave riding
The HI5905 is tested with V
ROUT
bias voltage equal to V and V - is a 2V
DC IN P-P
to V
on a DC bias voltage equal to V . Consequently, the converter
RIN
DC
1.3V and 3.3V are generated for a fully differential input
signal range of ±2V.
will be at positive full scale, resulting in a digital data output code
with D13 (MSB) equal to a logic “0” and D0-D12 equal to logic
“1” (see Table 1, A/D Code Table), when the V + input is at
IN
In order to minimize overall converter noise, it is
recommended that adequate high frequency decoupling be
V
+1V and the V - input is at VDC-1V (V + - V - = 2V).
DC IN IN IN
Conversely, the ADC will be at negative full scale, resulting in a
digital data output code with D13 (MSB) equal to a logic “1” and
D0-D12 equal to logic “0” (see Table 1, A/D Code Table), when
the V + input is equal to V -1V and V - is at V +1V
provided at the reference voltage input pin, V
.
RIN
Analog Input, Differential Connection
The analog input to the HI5905 can be configured in various
ways depending on the signal source and the required level
of performance. A fully differential connection (Figure 4) will
give the best performance for the converter.
IN
DC
IN
DC
(V +-V - = -2V). From this, the converter is seen to have a
IN IN
peak-to-peak differential analog input voltage range of 2V.
The analog input can be DC coupled (Figure 5) as long as
the inputs are within the analog input common mode voltage
range (1.0V ≤ VDC ≤ 4.0V).
Since the HI5905 is powered off a single +5V supply, the
analog input must be biased so it lies within the analog input
TABLE 1. A/D CODE TABLE
DIFFERENTIAL
INPUT VOLTAGE†
(USING INTERNAL
REFERENCE)
TWO’S COMPLEMENT BINARY OUTPUT CODE
LSB
CODE
CENTER
DESCRIPTION
MSB
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
+Full Scale
+1.99994V
0
1
1
1
1
1
1
1
1
1
1
1
1
1
(+FS) - 1/4 LSB
+FS - 1 1/4 LSB 1.99969V
0
0
1
1
1
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
1
0
+ 3/4 LSB
- 1/4 LSB
183.105µV
-61.035µV
-FS + 1 3/4 LSB -1.99957V
-Full Scale
-1.99982V
(-FS) + 3/4 LSB
† The voltages listed above represent the ideal center of each two’s complement binary output code shown.
4-5
The resistor, R, in Figure 7 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
V
IN
V
+
IN
VDC
VDC
connected from V + to V - will help filter any high frequency
IN IN
R
R
noise on the inputs, also improving performance. Values
around 20pF are sufficient and can be used on AC coupled
inputs as well. Note, however, that the value of capacitor C
chosen must take into account the highest frequency
component of the analog input signal.
HI5905
C
V
V
DC
-V
IN
-
IN
A single ended source will give better overall system
performance if it is first converted to differential before
driving the HI5905.
FIGURE 5. DC COUPLED DIFFERENTIAL INPUT
The resistors, R, in Figure 5 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
Digital I/O and Clock Requirements
connected from V + to V - will help filter any high
IN IN
The HI5905 provides a standard high-speed interface to
external TTL/CMOS logic families. The digital CMOS clock
input has TTL level thresholds. The low input bias current
allows the HI5905 to be driven by CMOS logic. The digital
CMOS outputs have a separate +5.0V digital supply input pin.
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
In order to ensure rated performance of the HI5905, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
Analog Input, Single-Ended Connection
The configuration shown in Figure 6 may be used with a
single ended AC coupled input. Sufficient headroom must
be provided such that the input voltage never goes above
Performance of the HI5905 will only be guaranteed at
conversion rates above 0.5MSPS. This ensures proper
performance of the internal dynamic circuits.
+5V or below A
.
GND
Supply and Ground Considerations
V
+
V
IN
IN
The HI5905 has separate analog and digital supply and ground
pins to keep digital noise out of the analog signal path. The part
should be mounted on a board that provides separate low
impedance connections for the analog and digital supplies and
grounds. For best performance, the supplies to the HI5905
should be driven by clean, linear regulated supplies. The board
should also have good high frequency decoupling capacitors
mounted as close as possible to the converter. If the part is
powered off a single supply then the analog supply and ground
pins should be isolated by ferrite beads from the digital supply
and ground pins.
HI5905
VDC
V
-
IN
FIGURE 6. AC COUPLED SINGLE ENDED INPUT
Again, the difference between the two internal voltage
references is 2V. If V is a 4V
sinewave, then V + is a
IN P-P
IN
4V
P-P
sinewave riding on a positive voltage equal to VDC. The
converter will be at positive full scale when V + is at VDC + 2V
(V + - V - = 2V) and will be at negative full scale when V +
IN IN IN
IN
Refer to the Application Note AN9214, “Using Intersil High
Speed A/D Converters” for additional considerations when
using high speed converters.
is equal to VDC - 2V (V + - V - = -2V). In this case, VDC
IN IN
could range between 2V and 3V without a significant change in
ADC performance. The simplest way to produce VDC is to use
Static Performance Definitions
the V
DC
bias voltage output of the HI5905.
Offset Error (V
)
OS
The single ended analog input can be DC coupled (Figure 7)
as long as the input is within the analog input common mode
voltage range.
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
V
IN
Full-Scale Error (FSE)
V
+
VDC
IN
The last code transition should occur for an analog input that
is 3/4 LSB below positive full-scale with the offset error
removed. Full-scale error is defined as the deviation of the
actual code transition from this point.
R
HI5905
-
C
VDC
V
IN
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
FIGURE 7. DC COUPLED SINGLE ENDED INPUT
4-6
present at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
calculation are (f + f ), (f - f ), (2f ), (2f ), (2f + f ), (2f - f ),
1
2
1
2
1
2
1
2
1
2
(f + 2f ), (f - 2f ). The ADC is tested with each tone 6dB
1
2
1
2
Power Supply Rejection Ratio (PSRR)
below full scale.
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and gain error (in LSBs) is noted.
Transient Response
Transient response is measured by providing a fullscale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
14-bit accuracy.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5905. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is -0.5dB down from full-scale for all these tests. SNR and
SINAD are quoted in dB. The distortion numbers are quoted in
dBc (decibels with respect to carrier) and DO NOT include any
correction factors for normalizing to full scale.
Over-Voltage Recovery
Over-voltage Recovery is measured by providing a fullscale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 14-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sinewave.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
The input sinewave has an amplitude which swings from -f
S
to +f . The bandwidth given is measured at the specified
S
sampling frequency.
Timing Definitions
Signal-to-Noise + Distortion Ratio (SINAD)
Refer to Figure 1, Internal Circuit Timing, and Figure 2,
Input-To-Output Timing, for these definitions.
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency,
f /2, excluding DC.
S
Aperture Delay (t
)
AP
Aperture delay is the time delay between the external
Effective Number Of Bits (ENOB)
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
The effective number of bits (ENOB) is calculated from the
SINAD data by:
ENOB = (SINAD + V
-1.76)/6.02
CORR
Aperture Jitter (t
)
AJ
where: V
= 0.5dB (Typical)
adjusts the ENOB for the amount the input is below
CORR
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
V
CORR
fullscale.
Data Hold Time (t )
H
Data hold time is the time to where the previous data (N - 1)
is still valid.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input signal.
Data Output Delay Time (t
)
OD
2nd and 3rd Harmonic Distortion
Data output delay time is the time to where the new data (N)
is valid.
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Data Latency (t
)
LAT
Spurious Free Dynamic Range (SFDR)
After the analog sample is taken, the digital data is output on
the bus at the third cycle of the clock. This is due to the
pipeline nature of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input sample by 4
clock cycles.
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component (excluding the first 5 harmonic components) in
the spectrum below f /2.
S
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f and f , are
1
2
4-7
HI5905N/QML
Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
D
Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
INCHES
MILLIMETERS
SYM-
BOL
MIN
MAX
MIN
-
MAX
2.35
NOTES
A
A1
A2
B
-
0.093
0.010
0.083
0.018
0.016
0.530
0.398
0.530
0.398
0.037
-
0.004
0.077
0.012
0.012
0.510
0.390
0.510
0.390
0.026
0.10
1.95
0.30
0.30
12.95
9.90
12.95
9.90
0.65
0.25
-
2.10
-
-A-
-B-
0.45
6
E
E1
B1
D
0.40
-
13.45
10.10
13.45
10.10
0.95
3
D1
E
4, 5
3
E1
L
4, 5
e
-
N
44
0.032 BSC
44
0.80 BSC
7
PIN 1
e
-
SEATING
PLANE
Rev. 1 1/94
-H-
A
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
0.10
0.004
o
o
-C-
5 -16
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
0.40
0.016
o
0.20
0.008
MIN
M
C
A-B S D S
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
0
MIN
B
A2
o
A1
o
o
B1
0 -7
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
0.13/0.17
0.005/0.007
6. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
o
5 -16
L
7. “N” is the number of terminal positions.
BASE METAL
WITH PLATING
0.13/0.23
0.005/0.009
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out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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TEL: (321) 724-7000
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4-8
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