80C883 [INTERSIL]
High Performance Microprocessor with Memory Management and Protection; 高性能微处理器与内存管理和保护
| 型号： | 80C883 |
| 厂家： | 
Intersil |
| 描述： | High Performance Microprocessor with Memory Management and Protection |
| 文件： | 总13页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
80C286/883
High Performance Microprocessor with Memory
Management and Protection
March 1997
Features
Description
• This Circuit is Processed in Accordance to MIL-STD- The Intersil 80C286/883 is a static CMOS version of the
883 and is Fully Conformant Under the Provisions of NMOS 80286 microprocessor. The 80C286/883 is an
Paragraph 1.2.1.
advanced, high-performance microprocessor with specially
optimized capabilities for multiple user and multi-tasking sys-
tems. The 80C286/883 has built-in memory protection that
supports operating system and task isolation as well as pro-
gram and data privacy within tasks. The 80C286/883
includes memory management capabilities that map 230
(one gigabyte) of virtual address space per task into 224
bytes (16 megabytes) of physical memory.
• Compatible with NMOS 80286/883
• Static CMOS Design for Low Power Operation
- ICCSB = 5mA Maximum
- ICCOP = 185mA Maximum (80C286-10/883)
- ICCOP = 220mA Maximum (80C286-12/883)
• Large Address Space
- 16 Megabytes Physical
- 1 Gigabyte Virtual per Task
The 80C286/883 is upwardly compatible with 80C86 and
80C88 software (the 80C286/883 instruction set is a super-
set of the 80C86/80C88 instruction set). Using the 80C286/
883 real address mode, the 80C286/883 is object code com-
patible with existing 80C86 and 80C88 software. In protected
virtual address mode, the 80C286/883 is source code com-
patible with 80C86 and 80C88 software but may require
upgrading to use virtual address as supported by the
80C286/883’s integrated memory management and protec-
tion mechanism. Both modes operate at full 80C286/883
performance and execute a superset of the 80C86 and
80C88 instructions.
• Integrated Memory Management, Four-Level Memory
Protection and Support for Virtual Memory and
Operating Systems
• Two 80C86 Upward Compatible Operating Modes
- 80C286/883 Real Address Mode
- Protected Virtual Address Mode
• Compatible with 80287 Numeric Data Co-Processor
The 80C286/883 provides special operations to support the
efficient implementation and execution of operating systems.
For example, one instruction can end execution of one task,
save its state, switch to a new task, load its state, and start
execution of the new task. The segment-not-present excep-
tion and restartable instructions.
Ordering Information
PACKAGE
TEMP. RANGE
10MHz
12.5MHz
CG80C286-12
IG80C286-12
16MHz
20MHz
25MHz
PKG. NO.
G68.B
o
o
68 Pin PGA
0 C to +70 C
-
CG80C286-16
CG80C286-20
-
-
-
-
o
o
-40 C to +85 C IG80C286-10
-
-
-
-
-
-
G68.B
o
o
-55 C to +125 C MG80C286-10/883 MG80C286-12/883
G68.B
5962-9067801MXC 5962-9067802MXC
G68.B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2948.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19939-128
80C286/883
Pinout
68 LEAD PGA, COMPONENT PAD VIEW
As viewed from underside of the component when mounted on the board.
35 37 39 41
34 36 38 40 42
32 33
43 45 47 49 51
A0
A2
D0
A1
ERROR
NC
NC
44 46 48 50 53 52
BUSY
NC
55 54
57 56
59 58
61 60
63 62
65 64
67 66
V
CLK
INTR
30 31
CC
A3
A5
RESET
A4
NMI
NC
28 29
PEREQ
READY
HLDA
M/IO
NC
V
26 27
SS
A7
A9
A6
V
24 25
CC
A8
22 23
HOLD
20 21
A11
A13
A10
A12
COD/INTA
LOCK
4
3
2
1
18 19 16 14 12
17 15 13 11
10
9
8
7
6
5
68
PIN 1 INDICATOR
P.C. BOARD VIEW
As viewed from the component side of the P.C. board.
51 49 47 45 43
41 39 37 35
42 40 38 36 34
33 32
NC ERROR
D0
A0
A2
V
52 53 50 48 46 44
BUSY
NC
NC
INTR
A1
54 55
56 57
58 59
60 61
62 63
64 65
66 67
CLK
31 30
CC
NC
NMI
RESET A3
29 28
V
PEREQ
READY
HLDA
M/IO
A4
A5
27 26
SS
V
A6
A7
25 24
CC
HOLD
COD/INTA
LOCK
23 22
A8
A9
21 20
A10
A12
A11
A13
2
1
4
3
68
6
5
8
7
10
9
12 14 16 19 18
11 13 15 17
NC
PIN 1 INDICATOR
3-129
80C286/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance (Typical)
Input, Output or I/O Voltage Applied. . . . . .GND -1.0V to V +1.0V PGA Package . . . . . . . . . . . . . . . . . . . . .
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22,500 Gates
θ
θ
JA
JC
o
o
35 C/W
6 C/W
CC
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C
o
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input RISE and FALL Time (From 0.8V to 2.0V
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
System Clock (CLK) RISE Time (From 1.0V to 3.6V . . . . 8ns (Max)
System Clock (CLK) FALL Time (from 3.6V to 1.0V) . . . . 8ns (Max)
80C286-10/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
80C286-12/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns (Max)
TABLE 1. 80C286/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
GROUP A
LIMITS
SUB-
PARAMETER
Input LOW Voltage
SYMBOL
CONDITIONS
= 4.5V
GROUPS
TEMPERATURE
MIN
-0.5
2.0
-0.5
3.6
-
MAX
0.8
+0.5
UNITS
o
o
V
V
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
V
V
IL
CC
CC
CC
CC
A
o
o
Input HIGH Voltage
CLK Input LOW Voltage
CLK Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
= 5.5V
-55 C ≤ T ≤ +125 C
V
V
IH
A
CC
o
o
V
= 4.5V
-55 C ≤ T ≤ +125 C
1.0
+0.5
V
ILC
A
o
o
V
= 5.5V
-55 C ≤ T ≤ +125 C
V
IHC
A
CC
o
o
V
I
I
I
= 2.0mA, V = 4.5V
-55 C ≤ T ≤ +125 C
0.4
-
V
OL
OL
OH
OH
CC
A
o
o
V
= -2.0mA, V = 4.5V
-55 C ≤ T ≤ +125 C
3.0
V
OH
CC
A
= -100µA, V = 4.5V
V
-0.4
CC
-
V
CC
o
o
Input Leakage Current
I
V
V
= GND or V
,
1, 2, 3
-55 C ≤ T ≤ +125 C
-10
10
µA
I
IN
CC
A
= 5.5V,
CC
Pins 29, 31, 57, 59, 61,
63-64
o
o
Input Sustaining Current
LOW
I
V
V
= 4.5V and 5.5V,
= 1.0V, Note 1
1, 2, 3
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
38
-50
-30
200
-400
-500
µA
µA
µA
BHL
CC
A
IN
o
o
Input Sustaining Current
HIGH
I
V
V
= 4.5V and 5.5V,
= 3.0V, Note 2
-55 C ≤ T ≤ +125 C
A
BHH
CC
IN
o
o
Input Sustaining Current
on BUSY and ERROR
Pins
I
V
V
= 4.5V and 5.5V
= GND, Note 5
-55 C ≤ T ≤ +125 C
A
SH
CC
IN
o
o
Output Leakage Current
I
V
V
= GND or V
1, 2, 3
-55 C ≤ T ≤ +125 C
-10
10
µA
O
O
CC
A
= 5.5V,
CC
Pins 1, 7-8, 10-28, 32-34
80C286-10/883, Note 4
80C286-12/883, Note 4
o
o
Active Power Supply
Current
I
1, 2, 3
1, 2, 3
-55 C ≤ T ≤ +125 C
-
-
-
185
220
5
mA
mA
mA
CCOP
A
o
o
Standby Power
Supply Current
I
V
= 5.5V, Note 3
-55 C ≤ T ≤ +125 C
A
CCSB
CC
NOTES:
2. I
3. I
4. I
5. I
should be measured after lowering V to GND and then raising to 1.0V on the following pins: 36-51, 66, 67.
IN
BHL
should be measured after raising V to V and then lowering to 3.0V on the following pins: 4-6, 36-51, 66-68.
BHH
IN
CC
should be tested with the clock stopped in phase two of the processor clock cycle. V = V or GND, V = 5.5V, outputs unloaded.
CCSB
CCOP
IN
CC
CC
measured at 10MHz for the 80C286-10/883 and 12.5MHz for the 80C286-12/883. V = 2.4V or 0.4V, V = 5.5V, outputs unloaded.
IN
CC
6. I should be measured after raising V to V and then lowering to 0V on pins 53 and 54.
SH
IN
CC
3-130
80C286/883
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
80C286/883
10MHz
12.5MHz
GROUP A
PARAMETER
System Clock
SYMBOL
CONDITIONS
SUBGROUPS
TEMPERATURE
MIN MAX MIN MAX UNITS
o
o
1
V
V
= 4.5V and 5.5V
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
50
12
16
20
-
-
-
-
40
11
13
15
-
-
-
-
ns
ns
ns
ns
CC
CC
A
(CLK) Period
o
o
System Clock
(CLK) Low Time
2
3
4
= 4.5V and 5.5V
-55 C ≤T ≤ +125 C
A
at 1.0V
o
o
System Clock (CLK)
High Time
V
= 4.5V and 5.5V
-55 C ≤ T ≤ +125 C
A
CC
at 3.6V
o
o
Asynchronous Inputs
SETUP Time
(Note 1)
V
= 4.5V
-55 C ≤ T ≤ +125 C
A
CC
and 5.5V
o
o
Asynchronous Inputs
HOLD Time
5
V
= 4.5V
9, 10, 11
-55 C ≤ T ≤ +125 C
20
-
15
-
ns
CC
A
and 5.5V
(Note 1)
o
o
RESET SETUP Time
RESET HOLD Time
6
7
V
= 4.5V
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
19
0
-
-
10
0
-
-
ns
ns
ns
ns
ns
ns
ns
CC
A
and 5.5V
o
o
V
= 4.5V
-55 C ≤ T ≤ +125 C
A
CC
and 5.5V
o
o
Read Data
SETUP Time
8
V
= 4.5V
-55 C ≤ T ≤ +125 C
8
-
5
-
CC
A
and 5.5V
o
o
Read Data
HOLD Time
9
V
= 4.5V
-55 C ≤ T ≤ +125 C
4
-
4
-
CC
A
and 5.5V
o
o
READY SETUP Time
READY HOLD Time
10
11
12A
V
= 4.5V
-55 C ≤ T ≤ +125 C
26
25
1
-
20
20
1
-
CC
A
and 5.5V
o
o
V
= 4.5V
-55 C ≤T ≤ +125 C
-
-
CC
A
and 5.5V
o
o
Status/PEACKActive
Delay, (Note 4)
V
= 4.5V and
-55 C ≤ T ≤ +125 C
22
21
CC
A
5.5V, C = 100pF
L
I = |2mA|
L
o
o
Status/PEACK
Inactive Delay
(Note 3)
12B
13
V
= 4.5V and
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
1
1
0
30
35
40
1
1
0
24
32
31
ns
ns
ns
CC
A
5.5V, C = 100pF
L
I = |2mA|
L
o
o
Address Valid
Delay (Note 2)
V
= 4.5V and
-55 C ≤ T ≤ +125 C
A
CC
5.5V, C = 100pF
L
I = |2mA|
L
o
o
Write Data
14
V
= 4.5V and
-55 C ≤ T ≤ +125 C
A
CC
Valid Delay, (Note 2)
5.5V, C = 100pF
L
I = |2mA|
L
3-131
80C286/883
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
80C286/883
10MHz
MIN MAX MIN MAX UNITS
47 25 ns
12.5MHz
GROUP A
SUBGROUPS
PARAMETER
SYMBOL
CONDITIONS
= 4.5V and
TEMPERATURE
o
o
HLDA Valid Delay
(Note 5)
15
V
9, 10, 11
-55 C ≤ T ≤ +125 C
0
0
CC
A
5.5V, C = 100pF
L
IL = |2mA|
NOTES:
1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure
recognition at a specific CLK edge.
2. Delay from 1.0V on the CLK to 0.8V or 2.0V.
3. Delay from 1.0V on the CLK to 0.8V for Min (HOLD time) and to 2.0V for Max (inactive delay).
4. Delay from 1.0V on the CLK to 2.0V for Min (HOLD time) and to 0.8V for Max (active delay).
5. Delay from 1.0V on the CLK to 2.0V.
TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
80C286/883
10MHz
12.5MHz
MIN MAX
PARAMETER
CLK Input Capacitance
Other Input Capacitance
I/O Capacitance
SYMBOL CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
10
UNITS
pF
o
C
FREQ = 1MHz
FREQ = 1MH
FREQ = 1MH
5
T = +25 C
-
-
-
-
10
10
10
32
CLK
A
o
C
5
5
T = +25 C
10
pF
IN
A
o
C
T = +25 C
-
10
-
pF
I/O
A
o
o
Address/Status/Data
Float Delay
15
1, 3, 4, 5
-55 C ≤ T ≤ +125 C
0
47
0
ns
A
o
o
Address Valid to Status
SETUP Time
19
I = |2.0mA|
1, 2, 5
-55 C ≤ T ≤ +125 C
27
-
20
-
ns
L
A
NOTES:
1. Output Load: C = 100pF.
L
2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching
2.0V.
3. Delay from 1.0V on the CLK to Float (no current drive) condition.
4. I = -6mA (V to Float), I = 8mA (V to Float).
L
OH
L
OL
5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
METHOD
100%/5004
100%/5004
100%
SUBGROUPS
-
Interim Test
PDA
1, 7, 9
1
Final Test
100%
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
Group A
-
Group C & D
Samples/5005
3-132
80C286/883
AC Electrical Specifications 82C284 and 82C288 Timing Specifications Are Given For Reference Only, And No Guarantee is
Implied.
82C284 Timing
10MHz
12.5MHz
MIN
SYMBOL
PARAMETER
MIN
MAX
MAX UNIT
TEST CONDITION
TIMING REQUIREMENTS
11
12
13
14
SRDY/SRDYEN Setup Time
15
2
-
-
-
-
15
2
-
ns
ns
ns
ns
SRDY/SRDYEN Hold Time
ARDY/ARDYEN Setup Time
ARDY/ARDYEN Hold Time
-
5
5
-
-
(Note 1)
(Note 1)
30
25
TIMING RESPONSES
19 PCLK Delay
0
20
0
16
ns
C = 75pF, I = 5mA,
L
OL
I
= -1mA
OH
NOTE:
1. These times are given for testing purposes to ensure a predetermined action.
82C288 Timing
10MHz
12.5MHz
MIN MAX
SYMBOL
PARAMETER
MIN
MAX
UNIT
TEST CONDITION
TIMING REQUIREMENTS
12
13
CMDLY Setup Time
CMDLY Hold Time
15
1
-
-
15
1
-
-
ns
ns
TIMING RESPONSES
ALE Active Delay
16
17
19
20
21
22
23
24
29
30
1
-
16
19
23
21
23
24
23
23
21
20
1
-
16
19
23
21
21
18
23
23
21
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE Inactive Delay
DT/R Read Active Delay
DEN Read Active Delay
-
-
C = 150pF
L
0
3
5
-
0
3
5
-
I
I
= 16mA Max
= -1mA Max
OL
DEN Read Inactive Delay
DT/R Read Inactive Delay
DEN Write Active Delay
OH
DEN Write Inactive Delay
Command Active Delay from CLK
Command Inactive Delay from CLK
3
3
3
3
3
3
C = 300pF
L
I
= 32mA Max
OL
3-133
80C286/883
AC Specifications
4.0V
3.6V
3.6V
CLK INPUT
0.45V
1.0V
1.0V
4.0V
3.6V
3.6V
CLK INPUT
1.0V
1.0V
0.45V
2.4V
tSETUP
tHOLD
2.0V
0.8V
2.0V
OTHER
DEVICE
INPUT
0.8V
0.4V
tDELAY (MAX)
tDELAY (MIN)
2.0V
0.8V
DEVICE
OUTPUT
NOTE:
1. For AC testing, input rise and fall times are driven at 1ns per volt.
FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT
3-134
80C286/883
Waveforms
READ CYCLE
ILLUSTRATED WITH ZERO
WAIT STATES
WRITE CYCLE
ILLUSTRATED WITH ONE
WAIT STATE
READ
(TI OR TS)
TI
TS
TC
TS
TC
TC
BUS CYCLE TYPE
3
1
VOH
φ2
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
CLK
2
12A
12B
VOL
S1 • S0
19
19
13
13
A
23 - A0
M/IO,
VALID ADDRESS
VALID ADDRESS
13
VALID IF TS
COD INTA
13
VALID CONTROL
9
VALID CONTROL
BHE, LOCK
14
15
8
VALID WRITE DATA
D15 - D0
VALID READ DATA
11
11
10
10
READY
12
11
SRDY +
SRDYEN
19
14
13
ARDY +
ARDYEN
19
16
19
17
20
PCLK
ALF
12
13
13
12
13
12
CMDLY
MWTC
29
30
29
19
30
(SEE NOTE 1)
MRDC
DT/R
24
22
23
20
21
DEN
NOTES:
1. The modified timing is due to the CMDLY signal being active.
2. 82C254 and 82C288 Timing Waveforms are shown for reference only, and no guarantee is inplied.
FIGURE 2. MAJOR CYCLE TIMING
3-135
80C286/883
Waveforms (Continued)
BUS CYCLE TYPE
VCH
VCH
TX
TX
φ2
φ1
φ2
φ2
φ1
φ1
CLK
CLK
VCL
VCL
19
19
7
(SEE NOTE 1)
6
PCLK
(SEE NOTE 1)
RESET
CLK
5
TX
φ2
4
VCH
φ1
φ2
INTR, NMI
HOLD, PEREQ
(SEE NOTE 2)
7
VCL
5
(SEE NOTE 1)
4
6
RESET
ERROR, BUSY
(SEE NOTE 2)
NOTES:
1. PCLK indicates which processor cycle phase will occur on the
next CLK. PCLK may not indicate the correct phase until the first
cycle is performed.
NOTE:
1. When RESET meets the setup time shown, the next CLK will
2. These inputs are asynchronous. The setup and hold times shown
assure recognition for testing purposes.
start or repeat φ1 of a processor cycle.
FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-
QUENT PROCESSOR CYCLE PHASE
FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL
TIMING
TH
TH OR TI
φ1
TI
TH
BUS CYCLE TYPE
VCH
φ1
φ2
φ2
φ1
φ2
φ1
φ2
CLK
VCL
16
16
15
HILDA
(SEE NOTE 4)
(NOTE 3)
12A
IF TS
(SEE NOTE 3)
S1 • S0
PEACK
12B
15
IF NPX TRANSFER
(SEE NOTE 1)
15
BHE, LOCK
A23 - A0,
13
(SEE NOTE 5)
VALID
14
M/IO,
COD/INTA
(SEE NOTE 2)
15
(SEE NOTE 6)
D15 - D0
PCLK
VALID IF WRITE
NOTES:
1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.
2. The data bus will be driven as shown if the last cycle before T in the diagram was a write T .
I
C
3. The 80C286/883 puts its status pins in a high impedance logic one state during T .
H
4. For HOLD request set up to HLDA, refer to Figure 8.
5. BHE and LOCK are driven at this time but will not become valid until T .
S
6. The data bus will remain in a high impedance state if a read cycle is performed.
FIGURE 5. EXITING AND ENTERING HOLD
3-136
80C286/883
Waveforms (Continued)
BUS CYCLE TYPE
TI
TS
TC
TS
TC
TI
VCH
φ2
φ1
φ2
φ2
φ1
φ2
φ1
φ2
φ1
1
CLK
VCL
I/0 READ IF PROC. EXT. TO MEMORY
MEMORY READ IF MEMORY TO PROC. EXT
MEMORY WRITE IF PROC. EXT. TO MEMORY
I/O WRITE IF MEMORY TO PROC. EXT.
S1 • S0
CLK
MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O
PORT ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER
A23 -A0
M/IO,
COD INTA
I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER
MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER
12A
12B
PEACK
(SEE NOTE 1)
5
(SEE NOTE 2)
4
PEREQ
NOTES:
1. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus operation
will be either a memory read at operand address or I/O read at port address 00FA(H).
1
2. To prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x
- 12A
-(4)
MAX MIN
(4)
(1)
1
The actual, configuration dependent, maximum time is: 3 x
- 12A
-
+N x 2 x . N is the number of extra T states added
MAX
MIN C
to either the first or second bus operation of the processor extension data operand transfer sequence.
FIGURE 6. 80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY
BUS CYCLE TYPE
TX
TX
TX
TI
VCH
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
CLK
VCL
6
(SEE NOTE 2)
6
7
(SEE NOTE 1)
RESET
AT LEAST
16 CLK PERIODS
12B
S1 • S0
PEACK
UNKNOWN
13
A23 - A0
BHE
UNKNOWN
UNKNOWN
13
M/IO
COD/INTA
13
LOCK
UNKNOWN
15
(SEE NOTE 3)
DATA
16
HILDA
UNKNOWN
NOTES:
1. Setup time for RESET ↑ may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later.
2. Setup and hold times for RESET ↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2.
3. The data bus is only guaranteed to be in a high impedance state at the time shown.
FIGURE 7. INITIAL 80C286/883 PIN STATE DURING RESET
3-137
80C286/883
Waveforms (Continued)
BUS HOLD
BUS HOLD ACKNOWLEDGE
TH TH TH
WRITE CYCLE
TC
ACKNOWLEDGE
BUS CYCLE TYPE
CLK
TS
TC
TC
TI
TH
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
(SEE NOTE 5)
(SEE NOTE 6)
(SEE NOTE 4)
HOLD
HLDA
(SEE NOTE 1)
(SEE NOTE 1)
S1 • S0
(SEE NOTE 2)
A23 - A0
M/IO,
VALID
COD/INTA
(SEE NOTE 3)
VALID
BHE, LOCK
VALID
D15 - D0
SRDY +
SRDYEN
NOT READY NOT READY (SEE NOTE 7)
ARDY +
ARDYEN
NOT READY NOT READY
DELAY ENABLE
READY
CMDLY
MWTC
(SEE NOTE 7)
VOH
DT/R
DEN
ALE
TS - STATUS CYCLE
CT - COMMAND CYCLE
NOTES:
1. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.
2. Address, M/IO and COD/lNTA may start floating during any T depending on when internal 80C286 bus arbiter decides to release bus to
C
external HOLD. The float starts in φ2 of T .
C
3. BHE and LOCK may start floating after the end of any T depending on when internal 80C286 bus arbiter decides to release bus to ex-
C
ternal HOLD. The float starts in φ1 of T .
C
4. The minimum HOLD to HLDA time is shown. Maximum is one T longer.
H
5. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
6. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,
Interrupts, Waits, Lock, etc.).
7. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state
is ignored after ready is signaled via the asynchronous input.
FIGURE 8. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD
3-138
80C286/883
Burn-In Circuit
R O
R O
R O
R O
R O
R O
R O
R O
R O
R O
R O
R O
R O
R O
R O
R O
NOTES:
8. Supply Voltage: V = 5.5V, V = 0.0V.
DD
SS
9. Input Voltage Limits: V (Maximum) = 0.8V, V (Minimum) = 2.0V
IL
IH
10. Component Values: RC = 1kΩ ±5%, RI = 10kΩ ±5%, RO = Two Series 2.7kΩ ±5%
11. Capacitor Values: C1 = 0.1 Microfarads
12. Oven Type and Frequency Requirements: Wakefield Oven Board f = 100kHz, f = 12.5kHz,
0
3
f = 6.25kHz, f = 3.125kHz, f = 781.25Hz.
4
5
7
13. Special Requirements: (a) ELECTROSTATIC DISCHARGE SENSITIVE. Proper Precautions Must be Used When Handling Units. (b) All Power Supplies
Must be at Zero Volts When the Boards are Inserted into the Ovens. (c) When Powering Up, the Inputs Must be Held Below the V Voltage. (d) If an
DD
Excessive Current is Indicated at Final Inspection, Check to See if a Part is Inserted Backwards or is Latched Up.
3-139
80C286/883
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
286 x 283 x 19 ±1mils
Type: Nitrox
Thickness: 10kÅ
WORST CASE CURRENT DENSITY: 2 X 105A/cm2
METALLIZATION:
Type: Si-Al
Thickness: 8kÅ
LEAD TEMPERATURE: (10s Soldering): ≤ 300oC
Metallization Mask Layout
80C286/883
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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Spec Number
3-140
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