82C88_05 [INTERSIL]
CMOS Bus Controller; CMOS总线控制器
| 型号： | 82C88_05 |
| 厂家： | 
Intersil |
| 描述： | CMOS Bus Controller |
| 文件： | 总11页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
82C88
®
Data Sheet
August 25, 2005
FN2979.2
CMOS Bus Controller
Features
• Compatible with Bipolar 8288
The Intersil 82C88 is a high performance CMOS Bus
Controller manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C88 provides the
control and command timing signals for 80C86, 80C88,
8086, 8088, 8089, 80186, and 80188 based systems. The
high output drive capability of the 82C88 eliminates the need
for additional bus drivers.
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
- 80186/80188. . . . . . . . . . . . . . . . . . . . . . . . . . (6/8MHz)
- 8086/8088. . . . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
- 8089
• Provides Advanced Commands for Multi-Master Busses
• Three-State Command Outputs
• Bipolar Drive Capability
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing equivalent products at a significant
power savings.
• Scaled SAJI IV CMOS Process
• Single 5V Power Supply
Pinouts
20 LD PDIP, CERDIP
• Low Power Operation
TOP VIEW
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 1mA/MHz (Max)
1
2
20
19
18
17
16
15
14
13
12
11
IOB
CLK
S1
V
CC
• Operating Temperature Ranges
S0
- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
- M82C88 . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
3
S2
4
DT/ R
ALE
AEN
MCE/PDEN
DEN
5
• Pb-Free Plus Anneal Available (RoHS Compliant)
6
CEN
Ordering Information
7
INTA
IORC
MRDC
AMWC
MWTC
GND
TEMP
8
PART
PART
RANGE
(°C)
PKG.
NUMBER
MARKING
PACKAGE
DWG. #
9
AIOWC
IOWC
CP82C88
CP82C88
20 Ld PDIP
0 to +70 E20.3
0 to +70 E20.3
10
CP82C88Z
(Note)
CP82C88Z 20 Ld PDIP
(Pb-free)
20 LD PLCC, CLCC
TOP VIEW
CP82C88-10 CP82C88-10 20 Ld PDIP
0 to +70 E20.3
-40 to +85 E20.3
0 to +70 N20.35
-40 to +85 N20.35
0 to +70 F20.3
-40 to +85 F20.3
-55 to +125 F20.3
F20.3
IP82C88
CS82C88
IS82C88
CD82C88
ID82C88
IP82C88
CS82C88
IS82C88
CD82C88
ID82C88
20 Ld PLCC
3
2
1
20 19
18
S2
4
DT/ R
ALE
20 Ld
CERDIP
17 MCE/PDEN
16 DEN
5
6
7
8
AEN
MD82C88/B MD82C88/B
8406901RA 8406901RA
15
14
CEN
MRDC
AMWC
SMD#
INTA
MR82C88/B MR82C88/B 20 Pad CLCC -55 to +125 J20.A
84069012A 84069012A SMD# J20.A
9
10 11 12 13
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
82C88
Functional Diagram
MRDC
MWTC
AMWC
IORC
S0
S1
S2
STATUS
DECODER
TM
MULTIBUS
COMMAND
SIGNAL
GENERATOR
COMMAND
SIGNALS
IOWC
AIOWC
INTA
DT/R
DEN
CLK
AEN
CEN
IOB
ADDRESS LATCH,
DATA TRANSCEIVER,
AND INTERRUPT
CONTROL
SIGNAL
GENERATOR
CONTROL
LOGIC
CONTROL
INPUT
MCE/PDEN
ALE
CONTROL SIGNALS
V
GND
CC
Pin Des cription
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
: The +5V power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling.
V
20
10
V
CC
CC
GND
GROUND.
S0, S1, S2 19, 3, 18
I
STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The
82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins
are not in use (passive), command outputs are held HIGH (See Table1).
CLK
ALE
2
5
I
CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock
generator and serves to establish when command/control signals are generated.
O
ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This signal is
active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use with transparent
D type latches, such as the 82C82 and 82C83H.
DEN
DT/R
AEN
16
4
O
O
I
DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus. This
signal is active HIGH.
DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers. A HIGH
on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from I/O or memory).
6
ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns (250ns
maximum) after it becomes active (LOW). AEN going inactive immediately three-states the command output
drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode (IOB tied HIGH).
CEN
IOB
15
1
I
I
COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN control
outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled.
INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus mode.
When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System Bus sections).
AIOWC
12
O
ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write Command earlier in the machine cycle to
give I/O devices an early indication of a write instruction. Its timing is the same as a read command signal.
AIOWC is active LOW.
IOWC
IORC
11
13
O
O
I/O WRITE COMMAND: This command line instructs an I/O device to read the data on the data bus. The signal
is active LOW.
I/O READ COMMAND: This command line instructs an I/O device to drive its data onto the data bus. This signal
is active LOW.
FN2979.2
2
August 25, 2005
82C88
Pin Des cription (Continued)
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
AMWC
8
O
ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory write command earlier in the machine
cycle to give memory devices an early indication of a write instruction. Its timing is the same as a read command
signal. AMWC is active LOW.
MWTC
MRDC
9
7
O
O
O
O
MEMORY WRITE COMMAND: This command line instructs the memory to record the data present on the data
bus. This signal is active LOW.
MEMORY READ COMMAND: This command line instructs the memory to drive its data onto the data bus. MRDC
is active LOW.
INTA
14
17
INTERRUPT ACKNOWLEDGE: This command line tells an interrupting device that its interrupt has been
acknowledged and that it should drive vectoring information onto the data bus. This signal is active LOW.
MCE/PDEN
This is a dual function pin. MCE (IOB IS TIED LOW) Master Cascade Enable occurs during an interrupt sequence
and serves to read a Cascade Address from a master 82C59A Priority Interrupt Controller onto the data bus. The
MCE signal is active HIGH. PDEN (IOB IS TIED HIGH): Peripheral Data Enable enables the data bus transceiver
for the I/O bus that DEN performs for the system bus. PDEN is active LOW.
Functional Des cription
The command logic decodes the three 80C86, 8086, 80C88,
8088, 80186, 80188 or 8089 status lines (S0, S1, S2) to
determine what command is to be issued (see Table 1).
IOB mode if I/O or peripherals dedicated to one processor
exist in a multi-processor system.
System Bus Mode
TABLE 1. COMMAND DECODE DEFINITION
The 82C88 is in the System Bus mode if the IOB pin is
strapped LOW. In this mode, no command is issued until a
specified time period after the AEN line is activated (LOW).
This mode assumes bus arbitration logic will inform the bus
controller (on the AEN line) when the bus is free for use.
Both memory and I/O commands wait for bus arbitration.
This mode is used when only one bus exists. Here, both I/O
and memory are shared by more than one processor.
82C88
S2
0
S1
0
S0
0
PROCESSOR STATE
COMMAND
Interrupt Acknowledge INTA
0
0
1
Read I/O Port
Write I/O Port
Halt
IORC
0
1
0
IOWC, AIOWC
None
0
1
1
Command Outputs
1
0
0
Code Access
Read Memory
Write Memory
Passive
MRDC
The advanced write commands are made available to initiate
write procedures early in the machine cycle. This signal can
be used to prevent the processor from entering an
unnecessary wait state.
1
0
1
MRDC
1
1
0
MWTC, AMWC
None
1
1
1
INTA (Interrupt Acknowledge) acts as an I/O read during an
interrupt cycle. Its purpose is to inform an interrupting device
that its interrupt is being acknowledged and that it should
place vectoring information onto the data bus.
I/O Bus Mode
The 82C88 is in the I/O Bus mode if the IOB pin is strapped
HIGH. In the I/O Bus mode, all I/O command lines IORC,
IOWC, AIOWC, INTA) are always enabled (i.e., not
dependent on AEN). When an I/O command is initiated by
the processor, the 82C88 immediately activates the
command lines using PDEN and DT/R to control the I/O bus
transceiver. The I/O command lines should not be used to
control the system bus in this configuration because no
arbitration is present. This mode allows one 82C88 Bus
Controller to handle two external busses. No waiting is
involved when the CPU wants to gain access to the I/O bus.
Normal memory access requires a “Bus Ready” signal (AEN
LOW) before it will proceed. It is advantageous to use the
The command outputs are:
MRDC - Memory Read Command
MWTC - Memory Write Command
IORC - I/O Read Command
IOWC - I/O Write Command
AMWC - Advanced Memory Write Command
AIOWC - Advanced I/O Write Command
INTA - Interrupt Acknowledge
FN2979.2
3
August 25, 2005
82C88
Control Outputs
Address Latch Enable and Halt
The control outputs of the 82C88 are Data Enable (DEN),
Data Transmit/Receive (DT/R) and Master Cascade Enable/
Peripheral Data Enable (MCE/PDEN). The DEN signal
determines when the external bus should be enabled onto
the local bus and the DT/R determines the direction of data
transfer. These two signals usually go to the chip select and
direction pins of a transceiver.
Address Latch Enable (ALE) occurs during each machine
cycle and serves to strobe the current address into the
82C82/82C83H address latches. ALE also serves to strobe
the status (S0, S1, S2) into a latch for halt state decoding.
Command Enable
The Command Enable (CEN) input acts as a command
qualifier for the 82C88. If the CEN pin is high, the 82C88
functions normally. If the CEN pin is pulled LOW, all
command lines are held in their inactive state (not three-
state). This feature can be used to implement memory
partitioning and to eliminate address conflicts between
system bus devices and resident bus devices.
The MCE/PDEN pin changes function with the two modes of
the 82C88. When the 82C88 is in the IOB mode (IOB HIGH),
the PDEN signal serves as a dedicated data enable signal
for the I/O or Peripheral System bus.
Interrupt Acknowledge and MCE
The MCE signal is used during an interrupt acknowledge
cycle if the 82C88 is in the System Bus mode (IOB LOW).
During any interrupt sequence, there are two interrupt
acknowledge cycles that occur back to back. During the first
interrupt cycle no data or address transfers take place. Logic
should be provided to mask off MCE during this cycle. Just
before the second cycle begins the MCE signal gates a
master Priority Interrupt Controller’s (PIC) cascade address
onto the processor’s local bus where ALE (Address Latch
Enable) strobes it into the address latches. On the leading
edge of the second interrupt cycle, the addressed slave PIC
gates an interrupt vector onto the system data bus where it is
read by the processor.
If the system contains only one PIC, the MCE signal is not
used. In this case, the second Interrupt Acknowledge signal
gates the interrupt vector onto the processor bus.
FN2979.2
4
August 25, 2005
82C88
Absolute Maximum Ratings
Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Thermal Resistance (Typical)
θ
(°C/W)
θ
(°C/W)
JC
JA
Input, Output or I/O Voltage. . . . . . . . . . . .GND -0.5V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
+0.5V
CC
CERDIP Package. . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . .
PLCC Package. . . . . . . . . . . . . . . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(PLCC - Lead Tips Only)
75
85
75
75
18
22
N/A
N/A
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
M82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
= 5.0V ± 10%;
CC
T
T
T
= 0°C to +70°C (C82C88);
= -40°C to +85°C (I82C88);
= -55°C to +125°C (M82C88)
A
A
A
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
C82C88, I82C88
M82C88
V
Logical One Input Voltage
2.0
2.2
-
-
V
V
IH
V
Logical Zero Input Voltage
-
0.8
-
V
V
V
IL
VIHC
VILC
CLK Logical One Input Voltage
CLK Logical Zero Input Voltage
V
-0.8
CC
-
0.8
-
V
Output High Voltage
Command Outputs
3.0
V
V
I
I
= -8.0mA
= -2.5mA
OH
OH
OH
V
V
-0.4
CC
3.0
-0.4
Output High Voltage
Control Outputs
-
V
V
I
I
= -4.0mA
= -2.5mA
OH
OH
CC
V
Output Low Voltage
Command Outputs
-
0.5
0.4
1.0
V
I
= +12.0mA
OL
OL
Output Low Voltage
Control Outputs
-
V
I
= +8.0mA
OL
I
Input Leakage Current
-1.0
µA
V
= GND or V , except S0, S1, S2,
CC
I
IN
DIP Pins 1-2, 6, 15
IBHH
IO
Input Leakage Current-Status Bus
Output Leakage Current
-50
-300
10.0
µA
µA
V
V
= 2.0V, S0, S1, S2 (See Note 1)
IN
O
-10.0
= GND or V , IOB = GND, AEN = V
CC
,
CC
DIP Pins 7-9, 11-14
ICCSB
ICCOP
Standby Power Supply
-
-
10
1
µA
V
V
= 5.5V, V = V
IN
or GND, Outputs Open
CC
CC
CC
= 5.5V, Outputs Open (See Note 2)
Operating Power Supply Current
mA/MHz
NOTES:
1. IBHH should be measured after raising the V on S0, S1, S2 to V
IN
and then lowering to valid input high level of 2.0V.
CC
2. ICCOP = 1mA/MHz of CLK cycle time (TCLCL)
Capacitance T = +25°C
A
SYMBOL
CIN
PARAMETER
Input Capacitance
TYPICAL
UNITS
pF
TEST CONDITIONS
10
17
FREQ = 1MHz, all measurements are
referenced to device GND
COUT
Output Capacitance
pF
FN2979.2
August 25, 2005
5
82C88
AC Electrical Specifications
V
T
T
T
= 5.0V ± 10%;
CC
= 0°C to +70°C (C82C88);
= -40°C to +85°C (I82C88);
= -55°C to +125°C (M82C88)
A
A
A
8MHz
10MHz
MAX
12MHz
MAX
TEST
SYMBOL
PARAMETER
MIN
MAX
MIN
MIN
UNITS CONDITIONS
TIMING REQUIREMENTS
(1) TCLCL
(2) TCLCH
(3) TCHCL
(4) TSVCH
(5) TCHSV
(6) TSHCL
(7) TCLSH
CLK Cycle Period
CLK Low Time
125
55
40
35
10
35
10
-
-
-
-
-
-
-
100
50
37
35
10
35
10
-
-
-
-
-
-
-
83
34
34
35
5
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
CLK High Time
Status Active Setup Time
Status Inactive Hold Time
Status Inactive Setup Time
Status Active Hold Time
35
5
TIMING RESPONSES
(8) TCVNV
(9) TCVNX
(10) TCLLH
Control Active Delay
5
10
-
45
45
20
25
20
30
18
35
35
50
30
40
40
5
10
-
45
45
20
23
20
23
18
35
35
50
30
40
40
5
10
-
45
35
20
23
20
23
18
35
35
50
30
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
2
2
1
1
3
4
Control Inactive Delay
ALE Active Delay (from CLK)
(11) TCLMCH MCE Active Delay (from CLK)
(12) TSVLH ALE Active Delay (from Status)
(13) TSVMCH MCE Active Delay (from Status)
-
-
-
-
-
-
-
-
-
(14) TCHLL
(15) TCLML
(16) TCLMH
(17) TCHDTL
ALE Inactive Delay
4
5
5
-
4
5
5
-
4
5
5
-
Command Active Delay
Command Inactive Delay
Direction Control Active Delay
(18) TCHDTH Direction Control Inactive Delay
-
-
-
(19) TAELCH
(20) TAEHCZ
Command Enable Time (Note 1)
-
-
-
Command Disable Time
(Note 2)
-
-
-
(21) TAELCV
(22) TAEVNV
Enable Delay Time
AEN to DEN
110
250
25
110
250
25
110
250
25
ns
ns
ns
ns
2
1
1
2
-
-
-
-
-
-
-
-
-
(23) TCEVNV CEN to DEN, PDEN
25
25
25
(24) TCELRH
(25) TLHLL
NOTES:
CEN to Command
TCLML
+10
TCLML
TCLML
ALE High Time
TCLCH -
10
-
TCLCH -
10
-
TCLCH -
10
n
ns
1
1. TAELCH measurement is between 1.5V and 2.5V.
2. TAEHCZ measured at 0.5V change in VOUT.
FN2979.2
August 25, 2005
6
82C88
AC Tes ting Input, Output Waveform
INPUT
OUTPUT
V
+0.4V
V
IH
OH
1.5V
-0.4V
1.5V
V
V
IL
OL
A.C. Testing: All input signals (other than CLK) must switch
between V -0.4V and V +0.4. CLK must switch between 0.4V
IL IH
-0.4V. Input rise and fall times are driven at 1ns/V.
and V
CC
A.C. Tes t Circuit
V1
R1
OUTPUT FROM
DEVICE
TEST
POINT
C1 (SEE NOTE)
UNDER TEST
NOTE:
INCLUDES STRAY AND JIG CAPACITANCE
TABLE 2. TEST CONDITION DEFINITION TABLE
TEST CONDITION
V1
R1
C1
1
2
3
4
2.13V
2.29V
1.5V
1.5V
220Ω
91Ω
80pF
300pF
300pF
50pF
187Ω
187Ω
FN2979.2
7
August 25, 2005
82C88
Timing Waveforms (Note 3)
T
T
T
T
T
4
STATE
4
1
2
3
TCLCL
(1)
TCLCH
(2)
CLK
TSHCL
(6)
TCHSV
(5)
TSVCH
(4)
TCHCL
(3)
TCLSH
(7)
S2, S1, S0
ADDRESS
VALID
WRITE
1
ADDRESS/DATA
ALE
DATA VALID
TCLLH
(10)
TCHLL (14)
TSVLH (12)
2
TCLMH
(16)
MRDC, IORC, INTA,
AMWC, AIOWC
TCLML
(15)
TCLML
(15)
MWTC, IOWC
TCVNV
(8)
DEN (READ)
(INTA)
TCVNX
(9)
PDEN (READ)
(INTA)
TCVNV
(8)
DEN (WRITE)
TCVNX
(9)
PDEN (WRITE)
TCHDTH
(18)
DT/R (READ)
(INTA)
TCHDTL
(17)
TCHDTH
(18)
2
MCE
TCLMCH
(11)
TCVNX
(9)
TSVMCH
(13)
NOTES:
1. Address/Data Bus is shown only for reference purposes.
2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last.
3. All timing measurements are made at 1.5V unless otherwise specified.
FIGURE 1.
FN2979.2
8
August 25, 2005
82C88
Timing Waveforms (Note 3) (Continued)
CEN
AEN
DEN
TAEVNV (22)
TCEVNV (23)
PDEN
FIGURE 2. DEN, PDEN QUALIFICATION TIMING
TAELCV
(21)
AEN
1.5V
1.5V
TAELCH (19)
TAEHCZ (20)
VOH
0.5V VOH
OUTPUT
COMMAND
TCELRH
(24)
CEN
TCELRH (24)
CEN MUST BE LOW OR INVALID PRIOR TO T2 TO PREVENT THE COMMAND FROM BEING GENERATED.
FIGURE 3. ADDRESS ENABLE (AEN) TIMING (THREE-STATE ENABLE/DISABLE)
NOTES:
1. Address/Data Bus is shown only for reference purposes.
2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last.
3. All timing measurements are made at 1.5V unless otherwise specified.
FN2979.2
9
August 25, 2005
82C88
Burn-In Circuits
MD82C88 CERDIP
R1
R1
R2
1
2
20
19
18
17
16
15
14
13
12
11
V
CC
F7
F0
F3
A
R2
R2
F4
3
F2
A
4
5
A
A
R1
R1
6
F5
A
F6
A
V
CC
7
R
3
3
8
A
A
A
A
A
9
R
10
V
A
CC
C1
MR82C88 CLCC
F3 F0 F7
V
F4
CC
R4 R1 R1
R4
3
2
1
20 19
R2
R4
R4
R1
R4
F2
18
4
5
6
7
8
V
V
/ 2
CC
R4
R4
R1
V
V
/ 2
17
16
15
14
CC
CC
/ 2
F5
/ 2
/ 2
CC
/ 2
F6
V
V
V
CC
R4
R4
/ 2
CC
CC
9
10 11 12 13
R4
R4
R4 R4
C1
V
CC
V
/ 2
V
/ 2
CC
CC
NOTES:
1. V
= 5.5V ± 0.5V
CC
GND = 0V
2. V = 4.5V ± 10%
IH
IL
V
= -0.2V to +0.4V
3. Component Values:
R1 = 47kΩ, 1/4W, 5%
R2 = 1.5kΩ, 1/4W, 5%
R3 = 10kΩ, 1/4W, 5%
R4 = 1.2kΩ, 1/4W, 5%
C1 = 0.01µF (Min)
F0 = 100kHz ± 10%
F1 = F0/2
F2 = F1/2 . . . F7 = F6/2
FN2979.2
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August 25, 2005
82C88
Die Characteris tics
DIE DIMENSIONS:
GLASSIVATION:
103.5 x 116.5 x 19 ± 1mils
Type: Nitrox
Thickness: 10kÅ
METALLIZATION:
Type: Si - Al
WORST CASE CURRENT DENSITY:
5
2
Thickness: 11kÅ ± 2kÅ
1.9 x 10 A/cm
Metallization Mas k Layout
82C88
S1
CLK
IOB
V
S0
S2
CC
DT/R
MCE/
PDEN
ALE
DEN
CEN
AEN
INTA
MRDC
AMWC
MWTC
GND
IOWC
AIOWC
IORC
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN2979.2
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August 25, 2005
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