ACS02K [INTERSIL]
Radiation Hardened Quad 2-Input NOR Gate; 抗辐射四2输入或非门
| 型号： | ACS02K |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened Quad 2-Input NOR Gate |
| 文件： | 总2页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACS02MS
Data Sheet
November 1998
File Number 4540
Radiation Hardened Quad 2-Input NOR Gate
Features
The Radiation Hardened ACS02MS is a Quad 2-Input NOR
Gate. For each gate, a HIGH level on either A or B input
results in a LOW level on the Y output. A LOW level on both
the A and B inputs results in a HIGH level on the Y output.
All inputs are buffered and the outputs are designed for
balanced propagation delay and transition times.
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-Up Free Under Any Conditions
5
- Total Dose. . . . . . . . . . . . . . . . . . . . . . . 3 x 10 RAD(Si)
-10
- SEU Immunity. . . . . . . . . . . . . <1 x 10
Errors/Bit/Day
2
The ACS02MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm )
• Input Logic Levels. . . . V = (0.3)(V ), V = (0.7)(V
IL CC IH
)
CC
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±8mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . 100µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .12ns (Max)
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Applications
Detailed Electrical Specifications for the ACS02MS are
contained in SMD 5962-98601. A “hot-link” is provided
on our homepage with instructions for downloading.
www.intersil.com/data/sm/index.asp
• High Speed Control Circuits
• Sensor Monitoring
• Low Power Designs
Ordering Information
INTERNAL MARKETING
o
ORDERING NUMBER
5962F9860101VCC
NUMBER
TEMP. RANGE ( C)
PACKAGE
14 Ld SBDIP
DESIGNATOR
CDIP2-T14
CDIP2-T14
CDFP4-F14
CDFP4-F14
N/A
ACS02DMSR-03
-55 to 125
ACS02D/SAMPLE-03
5962F9860101VXC
ACS02K/SAMPLE-03
5962F9860101V9A
ACS02D/SAMPLE-03
ACS02KMSR-03
25
-55 to 125
25
14 Ld SBDIP
14 Ld Flatpack
14 Ld Flatpack
Die
ACS02K/SAMPLE-03
ACS02HMSR-03
25
Pinouts
ACS02MS
ACS02MS
(SBDIP)
(FLATPACK)
TOP VIEW
TOP VIEW
1Y
1
2
3
4
5
6
7
14 V
CC
1Y
A1
1
2
3
4
5
6
7
14
13
12
11
10
9
V
CC
A1
B1
13 Y4
12 B4
11 A4
10 Y3
Y4
B4
A4
Y3
B3
A3
B1
Y2
Y2
A2
A2
B2
B2
9
8
B3
A3
GND
8
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
ACS02MS
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
SPECIAL INSTRUCTIONS
METALLIZATION: AI
Bond V
First
ADDITIONAL INFORMATION:
CC
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
5
2
Worst Case Current Density: <2.0 x 10 A/cm
Transistor Count: 108
SUBSTRATE POTENTIAL
Unbiased Insulator
Metallization Mask Layout
ACS02MS
V
(14)
A1
(2)
Y1
(1)
Y4
(13)
CC
B1 (3)
(12) B4
(11) A4
NC
Y2 (4)
NC
A2 (5)
(10) Y3
(6)
B2
(7)
GND
(8)
A3
(9)
B3
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