ACS05D [INTERSIL]
Radiation Hardened Hex Inverter with Open Drain Outputs; 抗辐射六角逆变器与漏极开路输出
| 型号： | ACS05D |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened Hex Inverter with Open Drain Outputs |
| 文件： | 总2页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACS05MS
Data Sheet
November 1998
File Number 4542
Radiation Hardened Hex Inverter with
Open Drain Outputs
Features
• QML Qualified Per MIL-PRF-38535 Requirements
• 1.25 Micron Radiation Hardened SOS CMOS
The Radiation Hardened ACS05MS is a Hex Inverter with
open drain outputs. This device inverts a HIGH level on each
input to a LOW level on the corresponding Y output. A LOW
level on the input causes the corresponding Y output to enter
a high impedance state, which can be pulled HIGH through a
• Radiation Environment
- Latch-Up Free Under any Conditions
5
- Total Dose. . . . . . . . . . . . . . . . . . . . . . 3 x 10 RAD (Si)
-10
resistor to V . All inputs are buffered and the outputs are
- SEU Immunity. . . . . . . . . . . . <1 x 10
Errors/Bit/Day
2
CC
designed for balanced propagation delay and transition times.
- SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm )
The ACS05MS is fabricated on a CMOS Silicon on Sapphire
(SOS) process, which provides an immunity to Single Event
Latch-up and the capability of highly reliable performance in
any radiation environment. These devices offer significant
power reduction and faster performance when compared to
ALSTTL types.
• Input Logic Levels. . . . V = (0.3)(V ), V = (0.7)(V
)
IL CC IH CC
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±8mA (Min)
• Quiescent Supply Current . . . . . . . . . . . . . . 100µA (Max)
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
Applications
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
• High Speed Control Circuits
• Sensor Monitoring
Detailed Electrical Specifications for the ACS05MS are
contained in SMD 5962-98602. A “hot-link” is provided
on our homepage with instructions for downloading.
www.intersil.com/data/sm/index.asp
• Low Power Designs
Ordering Information
o
ORDERING NUMBER
5962F9860201VCC
INTERNAL MKT. NUMBER
ACS05DMSR-03
TEMP. RANGE ( C)
PACKAGE
14 Ld SBDIP
DESIGNATOR
CDIP2-T14
CDIP2-T14
CDFP4-F14
CDFP4-F14
N/A
-55 to 125
ACS05D/SAMPLE-03
5962F9860201VXC
ACS05K/SAMPLE-03
5962F9860201V9A
ACS05D/SAMPLE-03
ACS05KMSR-03
25
-55 to 125
25
14 Ld SBDIP
14 Ld Flatpack
14 Ld Flatpack
Die
ACS05K/SAMPLE-03
ACS05HMSR-03
25
Pinouts
ACS05MS
ACS05MS
(SBDIP)
(FLATPACK)
TOP VIEW
TOP VIEW
A1
Y1
1
2
3
4
5
6
7
14
V
CC
A1
Y1
1
2
3
4
5
6
7
14 V
CC
13
12
11
10
9
A6
Y6
A5
Y5
A4
Y4
13 A6
12 Y6
11 A5
10 Y5
A2
A2
Y2
Y2
A3
Y3
A3
GND
8
Y3
9
8
A4
Y4
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
ACS05MS
PASSIVATION:
Die Characteristics
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
DIE DIMENSIONS:
Size: 2390µm x 2390µm (94 mils x 94 mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
SPECIAL INSTRUCTIONS:
Bond V
First
ADDITIONAL INFORMATION:
CC
METALLIZATION:
5
2
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
Worst Case Current Density: <2.0 x 10 A/cm
Transistor Count: 46
SUBSTRATE POTENTIAL
Unbiased Insulator
Metallization Mask Layout
ACS05MS
Y1
(2)
A1
(1)
V
(14)
A6
(13)
CC
A2 (3)
(12) Y6
(11) A5
NC
Y2 (4)
NC
A3 (5)
(10) Y5
(6)
Y3
(7)
GND
(8)
Y4
(9)
A4
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reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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