ACTS161MS [INTERSIL]
Radiation Hardened 4-Bit Synchronous Counter; 抗辐射4位同步计数器
| 型号： | ACTS161MS |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened 4-Bit Synchronous Counter |
| 文件： | 总4页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACTS161MS
Radiation Hardened
4-Bit Synchronous Counter
January 1996
Features
Pinouts
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96716 and Intersil’s QM Plan
LEAD FINISH C
TOP VIEW
• 1.25 Micron Radiation Hardened SOS CMOS
VCC
TC
MR
CP
P0
1
16
15
14
13
12
11
10
9
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
2
3
4
5
6
7
8
Q0
P1
Q1
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability. . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
P2
Q2
P3
Q3
TE
PE
SPE
GND
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
• Input Logic Levels
- VIL = 0.8V Max
TOP VIEW
- VIH = VCC/2 Min
• Input Current ≤ 1µA at VOL, VOH
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MR
CP
P0
VCC
TC
• Fast Propagation Delay . . . . . . . . . . . . . . . . 25ns (Max), 16ns (Typ)
Q0
Description
P1
Q1
The Intersil ACTS161MS is a Radiation Hardened 4-Bit Binary Synchronous
Counter, featuring asynchronous reset and load ahead carry logic. The MR is
an active low master reset. SPE is an active low Synchronous Parallel Enable
which disables counting and allows data at the preset inputs (P0 - P3) to load
the counter. CP is the positive edge clock. TC is the terminal count or carry
output. Both TE and PE must be high for counting to occur, but are irrelevant
to loading. TE low will keep TC low.
P2
Q2
P3
Q3
PE
TE
GND
SPE
The ACTS161MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACTS161MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9671601VEC
5962F9671601VXC
ACTS161D/Sample
ACTS161K/Sample
ACTS161HMSR
TEMPERATURE RANGE
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
PACKAGE
o
o
-55 C to +125 C
16 Lead SBDIP
o
o
-55 C to +125 C
16 Lead Ceramic Flatpack
16 Lead SBDIP
o
25 C
o
25 C
Sample
16 Lead Ceramic Flatpack
Die
o
25 C
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518893
File Number 4095
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
ACTS161MS
Functional Diagram
P0
P1
4
P2
P3
3
5
6
Q0 Q1
Q2 Q3
7
PE
10
TE
SPE
MR
TE
TE
9
1
P
D0
P
D1
P
D2
P
D3
Q3
Q0
Q1
Q2
T0
T1
T2
T3
MR
MR
MR
MR
GND
CP
CP
CP
CP
2
CP
14
13
12
11
15
Q0
Q1
Q2
Q3
TC
TRUTH TABLE
INPUTS
OUTPUTS
Q TC
N
OPERATING MODE
Reset (Clear)
MR
CP
PE
TE
SPE
P
N
L
X
X
X
X
X
h
X
I
X
L
L
Parallel Load
H
H
H
H
H
X
I
L
L
X
I
h
X
X
X
H
(Note 1)
(Note 1)
(Note 1)
L
Count
Inhibit
h
I (Note 2)
X
h (Note 3)
h (Note 3)
h (Note 3)
count
X
X
X
q
q
N
N
I (Note 2)
H = High Steady State, L = Low Steady State, h = High voltage level one setup time prior to the Low-to-High clock transition, I = Low volt-
age level one setup time prior to the Low-to-High clock transition, X = Don’t Care,q = Lower case letters indicate the state of the referenced
output prior to the Low-to-High clock transition,
NOTES:
= Low-to-High Transition.
1. The TC output is High when TE is High and the counter is at Terminal Count (HHHH).
2. The High-to-Low transition of PE or TE should only occur while CP is High for conventional operation.
3. The Low-to-High transition of SPE should only occur while CP is High for conventional operation.
Spec Number 518893
2
ACTS161MS
Die Characteristics
DIE DIMENSIONS:
88 mils x 88 mils
2240mm x 2240mm
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125kÅ ±1.125kÅ
Metal 2 Thickness: 9kÅ ±1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
< 2.0 x 105A/cm2
BOND PAD SIZE:
110µm x 110µm
4.3 mils x 4.3 mils
Metallization Mask Layout
ACTS161MS
CP
(2)
MR
(1)
VCC
(16)
TC
(15)
(14) Q0
(13) Q1
P0 (3)
P1 (4)
(12) Q2
(11) Q3
P2 (5)
P3 (6)
(7)
PE
(8)
(9)
(10)
TE
GND
SPE
Spec Number 518893
3
ACTS161MS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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FAX: (886) 2 2715 3029
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TEL: (321) 724-7000
FAX: (321) 724-7240
Spec Number
4
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