ACTS373D [INTERSIL]
Radiation Hardened Octal Transparent Latch, Three-State; 抗辐射八路透明锁存器,三态型号: | ACTS373D |
厂家: | Intersil |
描述: | Radiation Hardened Octal Transparent Latch, Three-State |
文件: | 总10页 (文件大小:93K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ACTS373MS
Radiation Hardened
Octal Transparent Latch, Three-State
April 1995
Features
• 1.25 Micron Radiation Hardened SOS CMOS
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C
TOP VIEW
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
<1 x 10-10 Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm2/mg
1
2
3
4
5
6
7
8
9
VCC
Q7
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
20
19
18 D7
17 D6
16 Q6
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
15
Q5
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
14 D5
13 D4
12
Q4
• Input Logic Levels
- VIL = 0.8V Max
GND 10
11 LE
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C
TOP VIEW
- VIH = VCC/2V Min
• Input Current ≤1µA at VOL, VOH
OE
Q0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
Description
The Intersil ACTS373MS is a radiation hardened octal transpar-
ent latch with three-state outputs. The outputs are transparent to
the inputs when the latch enable (LE) is high. When the LE goes
low, the data is latched. When the Output Enable (OE) is high,
the outputs are in the high impedance state. The latch operation
is independent of the state of the output enable.
D0
D1
Q1
Q2
D2
D3
The ACTS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
Q3
GND
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
PACKAGE
o
o
ACTS373DMSR
-55 C to +125 C
20 Lead SBDIP
o
o
ACTS373KMSR
-55 C to +125 C
20 Lead Ceramic Flatpack
20 Lead SBDIP
o
ACTS373D/Sample
ACTS373K/Sample
ACTS373HMSR
+25 C
o
+25 C
Sample
20 Lead Ceramic Flatpack
Die
o
+25 C
Die
Truth Table
Functional Diagram
1 OF 8
OE
LE
H
H
L
D
H
L
I
Q
H
L
(3, 4, 7, 8, 13,
14, 17, 18)
LATCH
L
OE
D
D
Q
Q
L
(2, 5, 6, 9, 12,
15, 16, 19)
COMMON
CONTROLS
LE
L
L
L
H
L
h
X
H
Z
LE
(11)
X
NOTE:
L
= Low Voltage Level
X = Don’t Care
Z = High Impedance State
OE
(1)
H = High Voltage Level
I
h
= Low voltage level one set-up time prior to the high to low latch enable transition
= High voltage level one set-up time prior to the high to low latch enable transition
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518800
File Number 4000
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Specifications ACTS373MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Impedance
DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flatpack. . . . . . . . . . . . . . . . . . . . . . . . . . 107 C/W 28 C/W
Maximum Package Power Dissipation at +125 C
DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7W
Flatpack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5W
Maximum Device Power Dissipation. . . . . . . . . . . . . . . . . . .(TBD)W
θ
θ
JA
JC
o
o
72 C/W
24 C/W
o
o
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
o
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +265 C
o
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Gates
(All Voltages Reference to VSS)
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . 10ns/V Max
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . VCC to VCC/2V
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V
o
o
Operating Temperature Range (T ) . . . . . . . . . . . . -55 C to +125 C
A
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
LIMITS
(NOTE 1)
PARAMETER
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MIN
MAX
UNITS
µA
o
Supply Current
ICC
VCC = 5.5V,
VIN = VCC or GND
1
+25 C
-
-
20
o
o
2, 3
1
+125 C, -55 C
400
µA
o
Output Current
(Source)
IOH
IOL
VCC = VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V, (Note 2)
+25 C
-12
-8
-
-
mA
o
o
2, 3
+125 C, -55 C
mA
o
Output Current
(Sink)
VCC = VIH = 4.5V,
VOUT = 0.4V, VIL = 0V,
(Note 2)
1
+25 C
12
8
-
-
mA
mA
o
o
2, 3
+125 C, -55 C
o
o
o
Output Voltage High
VOH
VCC = 5.5V, VIH = 2.75V
VIL = 0.8V, IOH = -50µA
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C
VCC -
0.1
-
V
V
V
V
o
o
o
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V, IOH = -50µA
+25 C, +125 C, -55 C
VCC -
0.1
-
o
o
o
Output Voltage Low
VOL
VCC = 5.5V, VIH = 2.75V
VIL = 0.8V, IOH = 50µA
+25 C, +125 C, -55 C
-
0.1
0.1
o
o
o
VCC = 4.5V, VIH = 2.25V,
+25 C, +125 C, -55 C
-
VIL = 0.8V, IOH = 50µA
o
Input Leakage
Current
IIN
IOZ
FN
VCC = 5.5V,
VIN = VCC or GND
1
2, 3
+25 C
-
-
-
-
-
±0.5
±1.0
±1
µA
µA
µA
µA
V
o
o
+125 C, -55 C
o
Three-State Output
Leakage Current
VCC = 5.5V,
Force Voltage = 0V or VCC
1
+25 C
o
o
2, 3
+125 C, -55 C
±35
-
o
o
o
Noise Immunity
Functional Test
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V, (Note 3)
7, 8A, 8B
+25 C, +125 C, -55 C
NOTE:
1. All voltages referenced to device GND.
2. Force/measure functions may be interchanged.
3. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”.
Spec Number 518800
2
Specifications ACTS373MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
LIMITS
MIN
(NOTES 1, 2)
A SUB-
PARAMETER
SYMBOL
CONDITIONS
GROUPS
TEMPERATURE
MAX
19
21
18
20
17
18
17
19
18
20
18
18
19
20
17
18
UNITS
ns
o
Propagation Delay
TPHL1
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
9
10, 11
9
+25 C
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
o
o
+125 C, -55 C
ns
o
TPLH1
TPHL2
TPLH2
TPZL1
TPLZ1
TPHZ1
TPZH1
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTE
TEMP
MIN
TYP
MAX
UNITS
pF
pF
pF
pF
pF
pF
ns
o
Capacitance Power
Dissipation
CPD
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
1
+25 C
-
-
17
21
-
-
-
o
+125 C
o
Input Capacitance
Output Capacitance
Pulse Width Time
Setup Time
CIN
COUT
TW
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
1
1
1
1
1
+25 C
-
10
10
20
20
-
o
+125 C
-
-
o
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
+25 C
-
-
o
+125 C
-
-
o
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
+25 C
7
7
5
5
3
3
-
o
+125 C
-
-
ns
o
TSU
TH
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
+25 C
-
-
ns
o
+125 C
-
-
ns
o
Hold Time
VCC = 4.5V, VIH = 4.5V,
VIL = 0V
+25 C
-
-
ns
o
+125 C
-
-
ns
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number 518800
3
Specifications ACTS373MS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
RAD LIMITS
(NOTE 1)
PARAMETER
Supply Current
SYMBOL
ICC
CONDITIONS
TEMP
MIN
-
MAX
400
-
UNITS
µA
o
VCC = 5.5V, VIN = VCC or GND
+25 C
o
Output Current (Source)
Output Current (Sink)
Output Voltage High
IOH
VCC = VIH = 4.5V,
VOUT = VCC -0.4V, VIL = 0
+25 C
-8
mA
o
IOL
VCC = VIH = 4.5V, VOUT = 0.4V,
VIL = 0
+25 C
8
-
-
mA
V
o
VOH
VCC = 5.5V, VIH = 2.75V,
+25 C
VCC -0.1
VIL = 0.8V, IOH = -50µA
o
VCC = 4.5V, VIH = 2.25V,
+25 C
VCC -0.1
-
V
VIL = 0.8V, IOH = -50µA
o
Output Voltage Low
VOL
VCC = 5.5V, VIH = 2.75V,
VIL = 0.8V, IOH = 50µA
+25 C
-
-
0.1
0.1
V
o
VCC = 4.5V, VIH = 2.25V,
+25 C
V
VIL = 0.8V, IOH = 50µA
o
Input Leakage Current
IIN
VCC = 5.5V, VIN = VCC or GND
+25 C
-
-
±1
µA
µA
o
Three-State Output
Leakage Current
IOZ
VCC = 5.5V,
Force Voltage = 0V or VCC
+25 C
±35
o
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V, (Note 2)
+25 C
-
-
V
o
Propagation Delay
TPHL1
TPLH1
TPHL2
TPLH2
TPZL1
TPLZ1
TPHZ1
TPZH1
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
+25 C
2
2
2
2
2
2
2
2
21
20
18
19
20
18
20
18
ns
ns
ns
ns
ns
ns
ns
ns
o
+25 C
o
+25 C
o
+25 C
o
+25 C
o
+25 C
o
+25 C
o
+25 C
NOTES:
1. All voltages referenced to device GND.
2. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”.
o
TABLE 5. DELTA PARAMETERS (+25 C)
(NOTE 1)
PARAMETER
Supply Current
SYMBOL
DELTA LIMIT
UNITS
ICC
±4.0
µA
nA
%
Three-State Leakage Current
Output Current
IOZ
±200
IOL/IOH
±15
NOTE:
1. All delta calculations are referenced to 0 hour readings or pre-life readings.
Spec Number 518800
4
Specifications ACTS373MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Initial Test (Preburn-In)
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
Sample/5005
Sample/5005
GROUP A SUBGROUPS
READ AND RECORD
ICC, IOL/H, IOZL/H
ICC, IOL/H, IOZL/H
ICC, IOL/H, IOZL/H
1, 7, 9
1, 7, 9
Interim Test 1 (Postburn-In)
Interim Test 2 (Postburn-In)
PDA
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
Interim Test 3 (Postburn-In)
PDA
ICC, IOL/H, IOZL/H
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Final Test
Group A (Note 1)
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Group D
NOTE:
1, 7, 9
1. Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method 5005.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
CONFORMANCE
GROUPS
Group E Subgroup 2
NOTE:
METHOD
PRE RAD
POST RAD
PRE RAD
1, 9
POST RAD
5005
1, 7, 9
Table 4
Table 4 (Note 1)
1. Except FN test which will be performed 100% Go/No-Go.
o
o
TABLE 8. BURN-IN TEST CONNECTIONS (+125 C < TA < 139 C)
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ±0.5V
VCC = 6V ±0.5V
50kHz
25kHz
STATIC BURN-IN 1 (Note 1)
-
1, 3, 4, 7, 8, 10, 11,
13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
20
-
-
STATIC BURN-IN 2 (Note 1)
-
10
2, 5, 6, 9, 12, 15, 16, 19
2, 5, 6, 9, 12, 15, 16, 19
1, 3, 4, 7, 8, 11, 13,
14, 17, 18, 20
-
-
DYNAMIC BURN-IN (Note 1)
-
1, 10
20
11
3, 4, 7, 8, 13,
14, 17, 18
NOTE:
1. Each pin except VCC and GND will have a series resistor of 500Ω ±5%.
o
o
TABLE 9. IRRADIATION TEST CONNECTIONS (TA = +25 C, ±5 C)
FUNCTION
OPEN
GROUND
VCC = 5V ±0.5V
1, 3, 4, 7, 8, 11, 13, 14, 17, 18, 20
Irradiation Circuit (Note 1)
2, 5, 6, 9, 12, 15, 16, 19
10
NOTE:
1. Each pin except VCC and GND will have a series resistor of 47kΩ ±5%. Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures.
Spec Number 518800
5
Specifications ACTS373MS
Intersil - Space Products MS Screening
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min
Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Interim Electrical Test 2 (Note 1)
100% Dynamic Burn-In Method 1015, 240 Hours at +125oC
100% Nondestructive Bond Pull Method 2023
100% Internal Visual Inspection Method 2010
or 180 Hours at +135oC
100% Interim Electrical Test 3 (Note 1)
100% Final Electrical Test
100% Temperature Cycling Method 1010 Condition C
(-65o to +150oC)
100% Fine and Gross Seal Method 1014
100% Radiographics Method 2012 (2 Views)
100% External Visual Method 2009
100% Constant Acceleration
100% PIND Testing
100% External Visual Inspection
100% Serialization
Group A (All Tests) Method 5005 (Class S)
Group B (Optional) Method 5005 (Class S) (Note 2)
Group D (Optional) Method 5005 (Class S) (Note 2)
CSI and/or GSI (Optional) (Note 2)
100% Initial Electrical Test
100% Static Burn-In 1 Method 1015, 24 Hours at +125oC Min
100% Interim Electrical Test 1 (Note 1)
Data Package Generation (Note 3)
NOTES:
1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures com-
bined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined,
PDA = 3% for subgroup 7 failures).
2. These steps are optional, and should be listed on the purchase order if required.
3. Data Package Contents:
Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity).
Certificate of Conformance (as found on shipper).
Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).
Variables Data (All Read, Record, and delta operations).
Group A Attributes Data Summary.
Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage.
X-Ray Report and Film, including penetrometer measurements.
GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose,
Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil.
Propagation Delay Timing Diagram and Load Circuit
DUT
TEST
POINT
VIH
RL
500Ω
CL
50pF
INPUT
VS
VSS
TPLH
TPHL
VOH
VOL
VS
OUTPUT
AC VOLTAGE LEVELS
PARAMETER
VCC
ACTS
4.50
3.00
1.30
0
UNITS
V
V
V
V
V
VIH
VS
VIL
GND
0
Spec Number 518800
6
Specifications ACTS373MS
Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger and AC Load Circuit
DUT
TEST
POINT
INPUT
VIH
TW
RL
500Ω
CL
50pF
VS
VIL
TH
TW
TSU
INPUT CP
VIH
PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS
VS
VIL
ACTS
4.50
3.00
1.30
0
PARAMETER
UNITS
VCC
V
V
V
V
V
VIH
VS
TH = HOLD TIME
TSU = SETUP TIME
TW = PULSE WIDTH
VIL
GND
0
Three-State High Timing Diagram and Load Circuit
DUT
TEST
POINT
VIH
INPUT
VS
RL
500Ω
CL
50pF
VSS
VOH
TPHZ
TPZH
VT
VW
OUTPUT
VOZ
PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS
PARAMETER
ACTS
4.50
3.00
1.30
1.30
3.60
0
UNITS
VCC
V
V
V
V
V
V
VIH
VS
VT
VW
GND
Three-State Low Timing Diagram and Load Circuit
VCC
VIH
INPUT
VS
RL
500Ω
VSS
VOZ
TPLZ
TEST
POINT
DUT
TPZL
VT
CL
50pF
VW
OUTPUT
VOL
PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS
PARAMETER
ACTS
4.50
3.00
1.30
1.30
0.90
0
UNITS
VCC
V
V
V
V
V
V
VIH
VS
VT
VW
GND
Spec Number 518800
7
ACTS373MS
Die Characteristics
DIE DIMENSIONS:
102 mils x 102 mils
2,600mm x 2,600mm
DIE ATTACH:
Material: Silver Glass or JM 7000 after 7/1/95
WORST CASE CURRENT DENSITY:
< 2.0 x 105A/cm2
METALLIZATION:
Type: AlSiCu
Metal 1 Thickness: 6.75kÅ (Min), 8.25kÅ (Max)
Metal 2 Thickness: 9kÅ (Min), 11kÅ (Max)
BOND PAD SIZE:
> 4.3 mils x 4.3 mils
> 110µm x 110µm
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
Metallization Mask Layout
ACTS373MS
D0
(3)
Q0
(2)
OE
(1)
VCC
(20)
Q7
(19)
D7
(18)
D1 (4)
Q1 (5)
NC
(17) D6
(16) Q6
NC
NC
NC
(15) Q5
Q2 (6)
D2 (7)
(14) D5
(8)
D3
(9)
Q3
(10)
GND
(11)
CP
(12)
Q4
(13)
D4
Spec Number 518800
8
ACTS373MS
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
D20.3 MIL-STD-1835 CDIP2-T20 (D-8, CONFIGURATION C)
20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
c1 LEAD FINISH
-A-
-D-
E
INCHES MILLIMETERS
MIN
BASE
METAL
(c)
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
1.060
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
26.92
7.87
NOTES
A
b
-
-
b1
M
M
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
(b)
b1
b2
b3
c
3
SECTION A-A
S
S
S
D
bbb
C
A - B
-
D
4
BASE
PLANE
S2
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
-
S1
b2
eA
A A
E
0.220
5.59
-
e
0.100 BSC
2.54 BSC
-
e
eA/2
C A - B
b
C A - B
c
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
aaa
D
S S
M
S
S
M
-
NOTES:
0.125
0.200
3.18
5.08
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.005
0.070
0.38
0.13
0.13
1.78
5
S1
S2
α
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
o
o
o
o
90
105
90
105
-
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
2
8
N
20
20
Rev. 0 4/94
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
Spec Number 518800
9
ACTS373MS
Ceramic Metal Seal Flatpack Packages (Flatpack)
K20.A MIL-STD-1835 CDFP4-F20 (F-9A, CONFIGURATION B)
20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
A
e
INCHES MILLIMETERS
MIN
PIN NO. 1
ID AREA
SYMBOL
MAX
0.115
0.022
0.019
0.009
0.006
0.540
0.300
0.330
-
MIN
1.14
0.38
0.38
0.10
0.10
-
MAX
2.92
0.56
0.48
0.23
0.15
13.72
7.62
8.38
-
NOTES
D
A
b
0.045
0.015
0.015
0.004
0.004
-
-
-
-A-
-B-
S1
b1
c
-
-
b
c1
D
-
E1
3
-
M
S
S
M
S
C
S
D
0.004
Q
H
A - B
D
0.036
H
A - B
E
0.245
-
6.22
-
E
E1
E2
E3
e
3
-
-D-
A
0.130
0.030
3.30
0.76
-H-
-C-
-
-
7
-
L
E2
L
E3
E3
0.050 BSC
1.27 BSC
SEATING AND
BASE PLANE
c1
LEAD FINISH
k
0.008
0.250
0.026
0.00
-
0.015
0.370
0.045
-
0.20
6.35
0.66
0.00
-
0.38
9.40
1.14
-
2
-
L
BASE
METAL
Q
S1
M
N
8
6
-
(c)
b1
M
0.0015
0.04
M
20
20
-
(b)
SECTION A-A
Rev. 0 5/18/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
3. This dimension allows for off-center lid, meniscus, and glass overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
Spec Number 518800
10
相关型号:
ACTS373K/SAMPLE-02
ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20, METAL SEALED, CERAMIC, FP-20
RENESAS
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