AD7541 [INTERSIL]
12-Bit, Multiplying D/A Converter; 12位乘法D / A转换器
| 型号： | AD7541 |
| 厂家： | 
Intersil |
| 描述： | 12-Bit, Multiplying D/A Converter |
| 文件： | 总8页 (文件大小：57K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AD7541
12-Bit, Multiplying D/A Converter
August 1997
Features
Description
• 12-Bit Linearity 0.01%
The AD7541 is a monolithic, low cost, high performance,
12-bit accurate, multiplying digital-to-analog converter
(DAC).
• Pretrimmed Gain
• Low Gain and Linearity Tempcos
• Full Temperature Range Operation
• Full Input Static Protection
• TTL/CMOS Compatible
Intersil’ wafer level laser-trimmed thin-film resistors on
CMOS circuitry provide true 12-bit linearity with TTL/CMOS
compatible operation.
Special tabbed-resistor geometries (improving time stability),
full input protection from damage due to static discharge by
diode clamps to V+ and ground, large I
lines (improving superposition errors) are some of the fea-
tures offered by Intersil AD7541.
and I
bus
• +5V to +15V Supply Range
• 20mW Low Power Dissipation
• Current Settling Time 1µs to 0.01% of FSR
• Four Quadrant Multiplication
OUT1
OUT2
Pin compatible with AD7521, this DAC provides accurate
four quadrant multiplication over the full military temperature
range.
Ordering Information
o
PART NUMBER
AD7541JN
NONLINEARITY
TEMP. RANGE ( C)
PACKAGE
18 Ld PDIP
PKG. NO.
E18.3
0.02% (11-Bit)
0.01% (12-Bit)
0 to 70
AD7541KN
AD7541LN
0 to 70
18 Ld PDIP
18 Ld PDIP
E18.3
E18.3
0.01% (12-Bit) Guaranteed
Monotonic
0 to 70
Pinout
Functional Block Diagram
AD7541
(PDIP)
TOP VIEW
V
10kΩ
10kΩ
10kΩ
10kΩ
REF IN
(17)
20kΩ
20kΩ
20kΩ
20kΩ
20kΩ
20kΩ
1
2
3
4
5
6
7
8
9
18
17
I
I
R
V
OUT1
FEEDBACK
(3)
OUT2
GND
REF IN
16 V+
SPDT
NMOS
SWITCHES
BIT 1 (MSB)
BIT 2
15 BIT 12 (LSB)
14 BIT 11
13 BIT 10
I
(2)
(1)
OUT2
I
OUT1
BIT 3
10kΩ
BIT 4
12
11
10
BIT 9
BIT 8
BIT 7
R
MSB
(4)
BIT 2
(5)
BIT 3
(6)
FEEDBACK
(18)
BIT 5
BIT 6
NOTE: Switches shown for digital inputs “High”.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number 3107.1
10-9
AD7541
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V Thermal Resistance (Typical, Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . .V+ to GND
θJA ( C/W)
V
REF
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
o
o
Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+
Maximum Storage Temperature . . . . . . . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
Operating Conditions
Temperature Range
JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 70 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications V+ = +15V, V
= +10V, V
OUT1
= V
= 0V, T = 25 C, Unless Otherwise Specified
A
REF
OUT2
o
T
= 25 C
T MIN-MAX
A
A
PARAMETER
SYSTEM PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
12
-
-
-
-
-
-
12
-
-
Bits
Nonlinearity
A, S, J
-10V ≤ V
≤ +10V
±0.024
±0.012
±0.012
±0.024
±0.012
±0.012
% of FSR
% of FSR
% of FSR
REF
= V
V
= 0V
OUT1
OUT2
B, T, K
L
-
-
See Figure 3
(Note 5)
-
-
Monotonicity
Gain Error
Guaranteed
±0.3
-10V ≤ V
REF
≤ +10V (Note 5)
-
-
-
-
-
-
±0.4
% of FSR
nA
Output Leakage Current
(Either Output)
V
= V
OUT2
= 0
±50
±200
OUT1
DYNAMIC CHARACTERISTICS
Power Supply Rejection
V+ = 14.5V to 15.5V
See Figure 5 (Note 5)
-
-
-
-
-
-
±0.005
-
-
-
±0.01 % of FSR/% of
∆V+
Output Current Settling Time
Feedthrough Error
To 0.1% of FSR
See Figure 9 (Note 6)
1
1
1
µs
V
= 20V , 10kHz
P-P
1
mV
P-P
REF
All Digital Inputs Low
See Figure 8 (Note 6)
REFERENCE INPUTS
Input Resistance
All Digital Inputs High
5
10
20
5
20
kΩ
I
at Ground
OUT1
ANALOG OUTPUT
Voltage Compliance
Both Outputs, See Maximum
Ratings (Note 7)
-100mV to V+
Output Capacitance
C
C
C
C
All Digital Inputs High
See Figure 7 (Note 6)
-
-
-
-
-
-
-
-
200
60
-
-
-
-
200
60
pF
pF
pF
pF
OUT1
OUT2
OUT1
OUT2
All Digital Inputs Low)
See Figure 7 (Note 6)
60
60
200
200
Output Noise (Both Outputs)
See Figure 6
(Notes 2, 6)
Equivalent to 10kΩ Johnson Noise
DIGITAL INPUTS
Low State Threshold, V
IL
-
-
-
0.8
-
-
0.8
-
V
V
High State Threshold, V
2.4
2.4
IH
10-10
AD7541
o
Electrical Specifications V+ = +15V, V
= +10V, V
OUT1
= V
= 0V, T = 25 C, Unless Otherwise Specified (Continued)
REF
OUT2
A
o
T
= 25 C
T MIN-MAX
A
A
PARAMETER
Input Current
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
V
= 0V or V+ (Note 6)
-
-
±1
-
±1
µA
IN
Input Coding
See Tables 1 and 2 (Note 6)
(Note 6)
Binary/Offset Binary
Input Capacitance
-
-
8
-
8
pF
POWER SUPPLY CHARACTERISTICS
Power Supply Voltage Range
Accuracy Is Not Guaranteed
+5 to +16
V
Over This Range
I+
All Digital Inputs High or Low
(Excluding Ladder Network)
-
-
-
2.0
-
-
-
2.5
-
mA
mW
Total Power Dissipation
NOTES:
(Including Ladder Network)
20
2. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy
electrostatic fields. Keep unused units in conductive foam at all times.
3. Do not apply voltages higher than V
or less than GND potential on any terminal except V
REF
and R
.
FEEDBACK
DD
4. Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes.
5. Using internal feedback resistor, R
.
FEEDBACK
6. Guaranteed by design or characterization and not production tested.
7. Accuracy not guaranteed unless outputs at ground potential.
Definition of Terms
Detailed Description
Nonlinearity: Error contributed by deviation of the DAC The AD7541 is a 12-bit, monolithic, multiplying D/A converter.
transfer function from a “best fit straight line” function. Nor- A highly stable thin film R-2R resistor ladder network and
mally expressed as a percentage of full scale range. For a NMOS SPDT switches form the basis of the converter circuit.
multiplying DAC, this should hold true over the entire V
range.
CMOS level shifters provide low power TTL/CMOS compati-
ble operation. An external voltage or current reference and an
operational amplifier are all that is required for most voltage
output applications. A simplified equivalent circuit of the DAC
is shown on page 1, (Functional Diagram). The NMOS SPDT
REF
Resolution: Value of the LSB. For example, a unipolar
-N
converter with n bits has a resolution of LSB = (V
REF
)/2 . A
bipolar converter of
n
bits has
a
resolution of
switches steer the ladder leg currents between I
and
buses which must be held at ground potential. This
-(N-1)
OUT1
LSB = (V
)/2
. Resolution in no way implies linearity.
REF
I
OUT2
configuration maintains a constant current in each ladder leg
independent of the input code. Converter errors are further
eliminated by using wider metal interconnections between the
major bits and the outputs. Use of high threshold switches
reduces the offset (leakage) errors to a negligible level.
Settling Time: Time required for the output function of the
1
DAC to settle to within
/
LSB for a given digital input
2
stimulus, i.e., 0 to Full Scale.
Gain Error: Ratio of the DAC’s operational amplifier output
voltage to the nominal input voltage value.
Each circuit is laser-trimmed, at the wafer level, to better than
12-bits linearity. For the first four bits of the ladder, special
trim-tabbed geometries are used to keep the body of the
resistors, carrying the majority of the output current, undis-
turbed. The resultant time stability of the trimmed circuits is
comparable to that of untrimmed units.
Feedthrough Error: Error caused by capacitive coupling
from V
to output with all switches OFF.
REF
Output Capacitance: Capacitance from I
, and I
OUT2
OUT1
terminals to ground.
Output Leakage Current: Current which appears on
, terminal when all digital inputs are LOW or on I
The level shifter circuits are comprised of three inverters with
a positive feedback from the output of the second to first
(Figure 1). This configuration results in TTL/COMS compati-
ble operation over the full military temperature range. With
the ladder SPDT switches driven by the level shifter, each
switch is binary weighted for an “ON” resistance proportional
to the respective ladder leg current. This assures a constant
voltage drop across each switch, creating equipotential ter-
minations for the 2R ladder resistor, resulting in accurate leg
currents.
I
OUT1
terminal when all inputs are HIGH.
OUT2
10-11
AD7541
V+
+15V
1 3
V
±10V
6
REF
4
TO LADDER
R
17
16
18
BIT 1 (MSB)
FEEDBACK
8
9
4
I
OUT1
5 AD7541 1
-
V
OUT
DIGITAL
INPUT
CR1
TTL/CMOS
INPUT
A
2
5
7
+
I
OUT2
15
2
3
BIT 12 (LSB)
I
I
OUT2 OUT1
GND
FIGURE 2. UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION)
FIGURE 1. CMOS SWITCH
Typical Applications
Zero Offset Adjustment
General Recommendations
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output
Static performance of the AD7541 depends on I
and
OUT1
(pin 1 and pin 2) potentials being exactly equal to
I
operational amplifier for 0V ±0.5mV (Max) at V
.
OUT2
GND (pin 3).
OUT
Gain Adjustment
The output amplifier should be selected to have a low input
bias current (typically less than 75nA), and a low drift
(depending on the temperature range). The voltage offset of
the amplifier should be nulled (typically less than ±200µV).
1. Connect all digital inputs to V
.
DD
12
1
2. Monitor V
OUT
for a -V
REF
(1 /
) reading.
2
3. To increase V
OUT
, connect a series resistor, (0Ω to
amplifier feedback loop.
The bias current compensation resistor in the amplifier’s
non-inverting input can cause a variable offset. Non-inverting
input should be connected to GND with a low resistance
wire.
250Ω), in the I
OUT1
4. To decrease V
OUT
, connect a series resistor, (0Ω to 250Ω),
between the reference voltage and the V
terminal.
REF
Ground-loops must be avoided by taking all pins going to
GND to a common point, using separate connections.
TABLE 1. CODE TABLE - UNIPOLAR BINARY OPERATION
DIGITAL INPUT
ANALOG OUTPUT
The V+ (pin 18) power supply should have a low noise level
and should not have any transients exceeding +17V.
1
12
111111111111
-V
-V
-V
(1 -
/
)
REF
REF
REF
2
Unused digital inputs must be connected to GND or V
proper operation.
for
DD
1
1
12
100000000001
( /
+
/
)
2
2
A high value resistor (~1MΩ) can be used to prevent static
charge accumulation, when the inputs are open-circuited for
any reason.
/2
100000000000
011111111111
000000000001
000000000000
1
1
12
-V
-V
0
( / - /
)
REF
REF
2
2
When gain adjustment is required, low tempco
1
12
o
( /
)
(approximately 50ppm/ C) resistors or trim-pots should be
2
selected.
Unipolar Binary Operation
The circuit configuration for operating the AD7541 in
unipolar mode is shown in Figure 2. With positive and
Bipolar (Offset Binary) Operation
negative V
values the circuit is capable of 2-Quadrant
REF
The circuit configuration for operating the AD7541 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage
values Four-Quadrant multiplication can be realized. The
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 2.
multiplication. The “Digital Input Code/Analog Output Value”
table for unipolar mode is given in Table 1. A Schottky diode
(HP5082-2811 or equivalent) prevents I
from negative
OUT1
excursions which could damage the device. This precaution
is only necessary with certain high speed amplifiers.
10-12
AD7541
A “Logic 1” input at any digital input forces the corresponding Gain Adjustment
ladder switch to steer the bit current to I
bus. A “Logic
OUT1
bus. For any code the
1. Connect all digital inputs to V
.
DD
1
0” input forces the bit current to I
OUT2
bus currents are complements of one
11
I
and I
2. Monitor V
OUT
for a -V
REF
(1 - /
) volts reading.
OUT1
another. The current amplifier at I
OUT2
2
changes the polarity
OUT2
current and the transconductance amplifier at
3. To increase V
OUT
, connect a series resistor, (0Ω to
amplifier feedback loop.
of I
OUT2
output sums the two currents. This configuration dou-
250Ω), in the I
OUT1
I
OUT1
bles the output range of the DAC. The difference current
resulting at zero offset binary code, (MSB = “Logic 1”, All
other bits = “Logic 0”), is corrected by using an external
4. To decrease V
OUT
, connect a series resistor, (0Ω to 250Ω),
between the reference voltage and the V
terminal.
REF
resistive divider, from V
to I
.
REF
OUT2
TABLE 2. CODE TABLE - BIPOLAR (OFFSET BINARY)
OPERATION
Offset Adjustment
1. Adjust V
to approximately +10V.
DIGITAL INPUT
ANALOG OUTPUT
REF
1
11
2. Set R4 to zero.
111111111111
-V
-V
0
(1 -
/
)
REF
REF
2
3. Connect all digital inputs to “Logic 1”.
1
11
100000000001
( /
)
2
4. Adjust I
amplifier offset zero adjust trimpot for 0V
amplifier output.
OUT1
±0.1mV at I
OUT2
100000000000
011111111111
000000000001
000000000000
5. Connect a short circuit across R2.
6. Connect all digital inputs to “Logic 0”.
1
( /
11
V
V
V
)
REF
REF
REF
2
1
11
(1 -
/
)
2
7. Adjust I
OUT2
amplifier offset zero adjust trimpot for 0V
amplifier output.
±0.1mV at I
OUT1
8. Remove short circuit across R2.
9. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.
10. Adjust R4 for 0V ±0.2mV at V
OUT
.
±10V
REF
V
+15V
16
17
BIT 1 (MSB)
4
18
I
OUT1
1
-
A1
V
OUT
+
DIGITAL
INPUT
AD7541
R1 10K
R2 10K
R5 10K
R3
390K
15
2
-
R4
500Ω
BIT 12 (LSB)
I
OUT2
3
A2
GND
+
NOTE: R1 and R2 should be 0.01%, low-TCR resistors.
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
10-13
AD7541
Test Circuits
+15V
V
REF
17
16
18
BIT 1 (MSB)
R
FEEDBACK
4
5
I
I
OUT1
12-BIT
BINARY
COUNTER
1
-
AD7541
HA2600
+
OUT2
10K
0.01%
15
2
3
1MΩ
BIT 12
(LSB)
GND
CLOCK
-
V
REF
HA2600
+
LINEARITY
ERROR X 100
BIT 1
10K 0.01%
(MSB)
BIT 12
BIT 13
BIT 14
14-BIT
REFERENCE
DAC
FIGURE 4. NONLINEARITY TEST CIRCUIT
+15V
UNGROUNDED
SINE WAVE
500K
GENERATION
40Hz 1.0V
P-P
+10V
V
REF
-
5K 0.01%
FEEDBACK
HA2600
+
17 16
BIT 1 (MSB)
R
5K 0.01%
V
X 100
ERROR
18
4
I
OUT1
OUT2
5
-
1
AD7541
HA2600
+
I
BIT 12
(LSB)
15
2
3
GND
FIGURE 5. POWER SUPPLY REJECTION TEST CIRCUIT
+11V (ADJUST FOR V
OUT
= 0V)
+15V
1K
100Ω
10K
F = 1KHz
BW = 1Hz
I
17
4
5
16
2
OUT2
15µF
QUAN
TECH
-
V
OUT
AD7541
MODEL
134D
101ALN
I
OUT1
15
1
WAVE
+
3
ANALYZER
50K
1K
-50V
0.1µF
FIGURE 6. NOISE TEST CIRCUIT
10-14
AD7541
Test Circuits (Continued)
+15V
NC
+15V
+15V
V
= 20V 10kHz SINE WAVE
P-P
REF
BIT 1 (MSB)
BIT 12 (LSB)
17
16
18
BIT 1 (MSB)
17
4
5
16
18
NC
1K
4
5
AD7541
AD7541
I
I
OUT1
3
1
2
1
2
6
OUT2
HA2600
15
17
100mV
1MHz
3
P-P
3
2
V
SCOPE
BIT 12 (LSB)
OUT
GND
FIGURE 7. OUTPUT CAPACITANCE TEST CIRCUIT
FIGURE 8. FEEDTHROUGH ERROR TEST CIRCUIT
+15V
V
REF
+10V
EXTRAPOLATE
3t: 5% SETTLING
9t: 0.01% SETTLING
BIT 1 (MSB)
17
4
16
+5V
0V
OSCILLOSCOPE
5
+100mV
AD7541
1
2
DIGITAL INPUT
I
OUT2
15
3
BIT 12 (LSB)
100Ω
GND
FIGURE 9. OUTPUT CURRENT SETTLING TIME TEST CIRCUIT
Dynamic Performance
The dynamic performance of the DAC, also depends on the code. These variations necessitate the use of compensation
output amplifier selection. For low speed or static applica- capacitors, when high speed amplifiers are used.
tions, AC specifications of the amplifier are not very critical.
A capacitor in parallel with the feedback resistor (as shown
For high-speed applications slew-rate, settling-time,
in Figure 10) provides the necessary phase compensation to
openloop gain and gain/phase-margin specifications of the
critically damp the output.
amplifier should be selected for the desired performance.
A small capacitor connected to the compensation pin of the
The output impedance of the AD7541 looking into I
OUT1
alone) and 5kΩ
in parallel with the ladder resistance).
amplifier may be required for unstable situations causing
oscillations. Careful PC board layout, minimizing parasitic
capacitances, is also vital.
varies between 10kΩ (R
FEEDBACK
(R
FEED-BACK
Similarly the output capacitance varies between the
minimum and the maximum values depending on the input
+15V
V
+10V
REF
R
FEEDBACK
17
4
16
18
BIT 1 (MSB)
BIT 2
5
C
C
I
I
AD7541
OUT1
OUT2
1
-
+
A
V
OUT
BIT 12 (LSB)
15
2
3
GND
FIGURE 10. GENERAL DAC CIRCUIT WITH COMPENSATION CAPACITOR, C
C
10-15
AD7541
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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10-16
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