CA3078 [INTERSIL]
2MHz, Micropower Operational Amplifier; 为2MHz ，微功耗运算放大器器
| 型号： | CA3078 |
| 厂家： | 
Intersil |
| 描述： | 2MHz, Micropower Operational Amplifier |
| 文件： | 总12页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CA3078, CA3078A
Data Sheet
December 1998
File Number 535.5
2MHz, Micropower Operational Amplifier
Features
The CA3078 and CA3078A are high gain monolithic
operational amplifiers which can deliver milliamperes of
current yet only consume microwatts of standby power. Their
operating points are externally adjustable and frequency
compensation may be accomplished with one external
capacitor. The CA3078 and CA3078A provide the designer
with the opportunity to tailor the frequency response and
improve the slew rate without sacrificing power. Operation
with a single 1.5V battery is a practical reality with these
devices.
• Low Standby Power . . . . . . . . . . . . . . . As Low As 700nW
• Wide Supply Voltage Range. . . . . . . . . . . ±0.75V to ±15V
• High Peak Output Current . . . . . . . . . . . . . . . 6.5mA (Min)
• Adjustable Quiescent Current
• Output Short Circuit Protection
Applications
• Portable Electronics
• Telemetry
• Intrusion Alarms
• Instrumentation
The CA3078A is a premium device having a supply voltage
range of V± = 0.75V to V± = 15V. The CA3078 has the same
lower supply voltage limit but the upper limit is V+ = +6V and
V- = -6V.
• Medical Electronics
Pinouts
CA3078 (PDIP, SOIC)
TOP VIEW
Ordering Information
COMP
1
2
3
4
8
7
6
5
PART NUMBER
(BRAND)
TEMP.
RANGE ( C)
PKG.
NO.
COMP
V+
o
PACKAGE
INV. INPUT
NON-INV.
INPUT
-
+
OUTPUT
CA3078AE
-55 to 125 8 Ld PDIP
-55 to 125 8 Ld SOIC
E8.3
V-
BIAS
CA3078AM
(3078A)
M8.15
CA3078 (METAL CAN)
CA3078AM96
(3078A)
-55 to 125 8 Ld SOIC Tape and Reel M8.15
TOP VIEW
V+
R
COMP
TAB
CA3078AT
CA3078E
-55 to 125 8 Pin Metal Can
T8.C
E8.3
8
V+
7
5
SET
1
3
0 to 70
0 to 70
8 Ld PDIP
8 Ld SOIC
INV.
INPUT
CA3078M
(3078)
M8.15
2
6
OUTPUT
+
NON-INV.
INPUT
CA3078T
0 to 70
8 Pin Metal Can
T8.C
BIAS
4
V-
NOTE: Case Voltage = Floating
Schematic Diagram
7
V+
50Ω
D
2
D
D
5
3
Q
12
Q
10
Q
18
Q
6
Q
OUTPUT
6
16
Q
4
Q
7
NON-
INVERTING
3
D
Q
9
11
Q
13
Q
D
3
Q
8
1
Q
15
Q
INVERTING
2
BIAS
5
8
Q
17
D
D
6
7
Q
9
Q
14
Q
Q
5
2
50Ω
D
1
D
4
V-
4
1
COMPENSATION
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
CA3078, CA3078A
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage (Between V+ and V- Terminal)
Thermal Resistance (Typical, Note 2)
θ
( C/W)
θ
( C/W)
JA
JC
CA3078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V
CA3078A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to V-
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1mA
Output Short Circuit Duration (Note 1). . . . . . . . . . . . . No Limitation
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
Metal Can Package . . . . . . . . . . . . . . .
Maximum Junction Temperature (Metal Can Package). . . . . . . .175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
130
165
175
N/A
N/A
100
o
o
o
o
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range
CA3078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
CA3078A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications For Equipment Design
CA3078 LIMITS
CA3078A LIMITS
= 5.1MΩ
TEST CONDITIONS
R
= 1MΩ
R
SET
SET
o
o
T
= 0 C to
T
= -55 C to
A
A
o
o
o
o
T
= 25 C
TYP
1.3
70 C
T
= 25 C
TYP
0.70
0.50
7
125 C
A
A
V+
R
R
L
S
PARAMETER
and V- (kΩ)
(kΩ)
MIN
MAX
MIN
MAX
MIN
MAX
3.5
2.5
12
-
MIN
MAX
4.5
5.0
50
-
UNITS
mV
nA
V
±6V
≤10
-
-
4.5
32
170
-
-
-
5
40
200
-
-
-
-
IO
I
-
-
-
6
-
IO
I
-
-
-
60
-
-
-
nA
IB
A
-
≥10
88
92
86
-
92
100
20
90
-
dB
OL
I
-
-
-
100
1200
±5.3
130
1560
-
150
1800
-
-
25
300
-
45
540
-
µA
µW
V
Q
P
-
-
-
≥10
-
-
±5.1
-
-
-
±5.1
-
240
±5.3
-
D
V
±5
±5
OM
V
≤10
-5.5 to
+5.8
-
-5 to
+5
-
-5.5 to
+5.8
-
-5 to
+5
-
V
ICR
CMRR
+ or I
≤10
-
-
-
-
-
80
-
110
12
-
-
-
-
-
6.5
-
-
30
-
80
-
115
12
-
-
-
-
-
-
30
-
dB
I
-
OM
6.5
mA
OM
∆V /∆V+
≤10
≤10
76
76
93
76
76
105
105
-
µV/V
µV/V
IO
∆V /∆V-
93
-
-
-
-
IO
R
= 13MΩ
SET
V
±15V
≤10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
92
-
1.4
100
20
3.5
-
-
4.5
-
mV
dB
µA
µW
V
IO
A
-
≥10
88
OL
I
-
-
30
750
-
-
50
1350
-
Q
P
-
-
-
600
-
D
V
-
≥10
±13.7 ±14.1
±13.5
OM
CMRR
≤10
-
-
-
80
-
106
7
-
-
-
-
-
dB
nA
nA
I
-
-
14
2.7
55
5.5
IB
I
-
0.50
IO
2
CA3078, CA3078A
o
Electrical Specifications T = 25 C, Typical Values Intended Only for Design Guidance
A
CA3078
CA3078A
V+ = +1.3V,
V- = -1.3V
V+ = +0.75V,
V- = -0.75V
V+ = +1.3V,
V- = -1.3V
V+ = +0.75V,
V- = -0.75V
PARAMETER
R
= 2MΩ
R
= 10MΩ
R
= 2MΩ
R = 10MΩ
SET
UNITS
mV
nA
SET
SET
SET
V
1.3
1.5
0.7
0.9
IO
I
1.7
9
0.5
0.3
3.7
84
0.054
0.45
65
IO
I
1.3
nA
IB
A
80
10
26
1.4
60
dB
OL
I
1
10
1
µA
Q
P
1.5
26
1.5
0.3
µW
V
D
V
0.3
1.4
OP-P
V
-0.8 to +1.1
-0.2 to +0.5
-0.8 to +1.1
-0.2 to +0.5
V
ICR
CMRR
100
12
90
0.5
50
100
12
90
0.5
50
dB
I
±
mA
µV/V
OM
∆V /∆V±
20
20
IO
o
Electrical Specifications T = 25 C and V
= ±6V, Typical Values Intended Only for Design Guidance
A
SUPPLY
CA3078
= 1MΩ
CA3078A
PARAMETER
∆V /∆T
TEST CONDITIONS
R
R
= 5.1MΩ
R = 1MΩ
SET
UNITS
SET
SET
o
R
R
≤10kΩ
≤10kΩ
6
5
6
µV/ C
IO
A
S
S
o
∆I /∆T
70
2
6.3
0.3
70
2
pA/ C
IO
A
GBWP
A
= 100, C = 10pF
MHz
V/µs
V/µs
µs
V
1
SR
See Figures 23, 24
0.04
1.5
2.5
0.87
0.8
25
0.027
0.5
3
0.04
1.5
2.5
1.7
0.8
-
t
10% to 90% Rise Time
R
R
-
-
7.4
1
MΩ
I
R
kΩ
O
e (10Hz)
R
R
= 0
40
nV/√Hz
pA/√Hz
N
S
S
i (10Hz)
= 1MΩ
1
0.25
-
N
3
CA3078, CA3078A
Test Circuits
V+
V+
100kΩ
100kΩ
V+
7
V+
7
R
R
SET
SET
0V
100kΩ
2
3
0V
2
3
V
5
8
5
8
IN
-
-
0V
R
C
R
2
CA3078
CA3078A
2
CA3078
CA3078A
6
V
6
10kΩ
V
OUT
OUT
0V
C
2
2
+
+
V
IN
10kΩ
C
100kΩ
1
C
1
L
L
51kΩ
4
4
V-
V-
R
C
1
R
1
C
1
1
R
OPTIONAL
- C COMP.
1
R
OPTIONAL
- C COMP.
1
R
2
2
R
2
2
FIGURE 1. TRANSIENT RESPONSE AND SLEW RATE, UNITY
GAIN (INVERTING) TEST CIRCUIT
FIGURE 2. SLEW RATE, UNITY GAIN (NON-INVERTING)
TEST CIRCUIT
NON-INVERTING
V+
INVERTING
R
F
R
INPUT
I
V+
7
3
INPUT
V+
R
I
+
7
2
3
OUTPUT
CA3078
CA3078A
-
V+
6
OUTPUT
CA3078
R
B
6
CA3078A
2
-
1M
R
B
4
+
1M
V-
V-
4
V-
R
F
V-
Value of R required to have a
B
null adjustment range of ±7.5mV
R
I
Value of R required to have a
B
R R V+
I
F
null adjustment range of ±7.5mV
R
≈
B
-3
(R + R ) 7.5 x 10
R V+
I
I
F
R
≈
B
-3
R R
7.5 x 10
I
F
assuming R > >
B
R + R
assuming R > > R
B I
I
F
FIGURE 3. OFFSET VOLTAGE NULL CIRCUITS
5.1MΩ
5.1MΩ
R
=
R
30MΩ
=
10MΩ
10MΩ
SET
30MΩ
SET
7
7
V
P-P
510kΩ
+
+
1.5V
“AA” CELL
1.5V
“AA” CELL
2
2
5
8
5
8
-
-
-
-
1µF
CA3078
CA3078A
CA3078
CA3078A
510kΩ
1µF
6
6
V
P-P
+
+
+
+
3
3
5µF
5µF
1
1
1µF
4
4
10MΩ
10MΩ
R
R
L
L
7pF
7pF
FIGURE 4. INVERTING 20dB AMPLIFIER CIRCUIT
FIGURE 5. NON-INVERTING 20dB AMPLIFIER CIRCUIT
4
CA3078, CA3078A
TABLE 1. UNITY GAIN SLEW RATE vs COMPENSATION - CA3078 AND CA3078A
V
= ±6V, Output Voltage (V ) = ±5V, Load Resistance (R ) = 10kΩ, Transient Response: 10% overshoot for an output voltage of 100mV,
SUPPLY
O
L
o
Ambient Temperature (T ) = 25 C
A
UNITY GAIN (INVERTING)
FIGURE 1
UNITY GAIN (NON-INVERTING)
FIGURE 2
R
C
R
C
SLEW RATE
R
C
R
C
2
SLEW RATE
1
1
2
2
1
1
2
COMPENSATION
TECHNIQUE
kΩ
pF
kΩ
µF
V/µs
kΩ
pF
kΩ
µF
V/µs
CA3078 - I = 100µA
Q
Single Capacitor
Resistor and Capacitor
Input
0
3.5
∞
750
350
0
0
0
0.0085
0.04
0
5.3
∞
1500
500
0
0
0
0.0095
0.024
0.67
∞
∞
∞
∞
0.25
0.306
0.67
0.311
0.45
CA3078A - I = 20µA
Q
Single Capacitor
Resistor and Capacitor
Input
0
14
∞
300
100
0
0
0
0.0095
0.027
0.29
0
34
∞
800
125
0
0
0
0.003
0.02
0.4
∞
∞
∞
∞
0.644
0.156
0.77
0.4
with input compensation, but this increases noise output.
Compensation can also be accomplished with a single
capacitor connected from Terminal 1 to Terminal 8, with speed
being sacrificed for simplicity. Table 1 gives an indication of
slew rates that can be obtained with various compensation
techniques at quiescent currents of 100µA and 20µA.
Application Information
Compensation Techniques
The CA3078A and CA3078 can be phase compensated with
one or two external components depending upon the closed
loop gain, power consumption, and speed desired. The
recommended compensation is a resistor in series with a
capacitor connected from Terminal 1 to Terminal 8. Values of
the resistor and capacitor required for compensation as a
function of closed loop gain are shown in Figures 25 and 26.
These curves represent the compensation necessary at
quiescent currents of 100µA and 20µA, respectively, for a
transient response with 10% overshoot. Figures 23 and 24
show the slew rates that can be obtained with the two different
compensation techniques. Higher speeds can be achieved
Single Supply Operation
The CA3078A and CA3078 can operate from a single supply
with a minimum total supply voltage of 1.5V. Figures 4 and 5
show the CA3078A or CA3078 in inverting and non-inverting
20dB amplifier configurations utilizing a 1.5V type “AA” cell
for a supply. The total consumption for either circuit is
approximately 675nW. The output voltage swing in this
configuration is 300mV
with a 20kΩ load.
P-P
Typical Performance Curves
V
= ±6
= 25 C
≤ 10kΩ
S
V
= ±6
= 25 C
o
S
T
A
o
T
A
R
S
10
1
CA3078
3.0
2.4
1.8
1.2
0.6
0
CA3078A
CA3078
0.1
0.01
CA3078A
1
10
100
1000
1
10
100
1000
10000
TOTAL QUIESCENT CURRENT (µA)
TOTAL QUIESCENT CURRENT (µA)
FIGURE 6. INPUT OFFSET VOLTAGE vs TOTAL QUIESCENT
CURRENT
FIGURE 7. INPUT OFFSET CURRENT vs TOTAL QUIESCENT
CURRENT
5
CA3078, CA3078A
Typical Performance Curves (Continued)
o
V
= ±6
= 25 C
S
T
= 25 C
A
o
T
A
100
10
1
126
108
CA3078
126
108
R
= 1MΩ
L
CA3078A
90
72
54
90
72
54
10kΩ
2kΩ
36
36
18
0
18
0
0.1
1
10
100
1000
10000
1
10
100
1000
TOTAL QUIESCENT CURRENT (µA)
TOTAL QUIESCENT CURRENT (µA)
FIGURE 8. INPUT BIAS CURRENT vs TOTAL QUIESCENT
CURRENT
FIGURE 9. OPEN LOOP VOLTAGE GAIN vs TOTAL
QUIESCENT CURRENT
1000
100
V
T
= ±6 TO V = ±15
= 25 C
S
S
o
V
= ±15
S
A
100
10
+6
-6
10
+3
-3
1
+1
-1
1
o
T
= 25 C
0.1
A
R
CONNECTED BETWEEN
SET
TERMINAL 5 AND V+
0.1
0.01
1000
100
10
1
0.1
0.01
0.001
1
10
100
1000
TOTAL QUIESCENT CURRENT (µA)
TOTAL QUIESCENT CURRENT (µA)
FIGURE 10. BIAS SETTING RESISTANCE vs TOTAL
QUIESCENT CURRENT
FIGURE 11. MAXIMUM OUTPUT CURRENT vs TOTAL
QUIESCENT CURRENT
V
T
= ±1.3V
V
I
= ±6
= 100µA
S
S
Q
o
120
100
80
= 25 C
R
= 50kΩ
A
L
1.5
1.0
C
= 0pF
1
0
C
C
= 10pF
= 30pF
1
1
100
200
300
400
100
300
1000
φ
60
40
10kΩ
5kΩ
2kΩ
1kΩ
500Ω
0.5
0
20
0
o
R
= 10kΩ, T = 25 C
L
A
C
BETWEEN TERMINALS 1 AND 8
1-
-20
0.1
1
2
3
4
5
6
0
0.5
1.0
1.5
2.0
1
10
10
10
10
10
10
TOTAL QUIESCENT CURRENT (µA)
FREQUENCY (Hz)
FIGURE 12. OUTPUT VOLTAGE SWING vs TOTAL QUIESCENT
CURRENT
FIGURE 13. OPEN LOOP VOLTAGE GAIN vs FREQUENCY
6
CA3078, CA3078A
Typical Performance Curves (Continued)
100
V
= ±6
= 20µA
S
I
= 20µA
Q
120
100
80
I
Q
o
T
= 25 C
A
0
C
= 0pF
1
C
= 10pF
= 30pF
1
100
200
300
400
C
1
10
φ
V
60
40
ICR
100
300
1000
V
OM
20
0
1
R
= 10kΩ
= 25 C
L
o
T
A
C - BETWEEN TERMINALS 1 AND 8
1
-20
1
2
3
4
5
6
0.1
1
10
10
10
10
10
10
0.1
FREQUENCY (Hz)
+1
-1
+10
-10
+100
-100
+0.1
-0.1
FIGURE 15. OPEN LOOP VOLTAGE GAIN vs FREQUENCY
1.75
SUPPLY VOLTS (V+, V-)
-0.1
V
= ±6
S
1.50
1.25
1.00
0.75
0.50
0.25
0
CA3078
I
= 100µA
Q
-1
-V
ICR
-V
OM
CA3078A
I
= 20µA
Q
-10
-75
-50
-25
0
25
50
75
100 125
o
TEMPERATURE ( C)
FIGURE 14. OUTPUT AND COMMON MODE VOLTAGE vs
SUPPLY VOLTAGE
FIGURE 16. INPUT OFFSET VOLTAGE vs TEMPERATURE
V
= ±6
S
V
= ±6
S
15.0
12.5
10.0
7.5
CA3078A
= 20µA
2.5
2.0
1.5
1.0
0.5
0
10
8
I
Q
100
75
CA3078
I
= 100µA
Q
6
CA3078A
50
I
= 20µA
4
5.0
CA3078
= 100µA
Q
I
Q
2
25
0
2.5
0
0
125
-75
-50
-25
0
25
50
o
75
100
125
-75
-50
-25
0
25
50
o
75
100
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 17. INPUT OFFSET CURRENT vs TEMPERATURE
FIGURE 18. INPUT BIAS CURRENT vs TEMPERATURE
7
CA3078, CA3078A
Typical Performance Curves (Continued)
V
= ±6
V
= ±6
S
S
110
105
100
95
50
40
30
20
10
0
CA3078A
= 20µA
I
200
150
100
50
Q
CA3078
= 100µA
I
Q
CA3078
CA3078A
90
85
0
125
80
-75
-50
-25
0
25
50
75
100 125
-75
-50
-25
0
25
50
o
75
100
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 19. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE
FIGURE 20. TOTAL QUIESCENT CURRENT vs TEMPERATURE
100
1
V
T
= ±6
= 25 C
V
T
= ±6
= 25 C
S
A
S
o
o
A
CA3078AT
CA3078AT
I
= 20µA
Q
I
= 100µA
Q
I
= 100µA
Q
10
0.1
I
= 20µA
Q
0
10
0.01
1
2
3
4
5
1
2
3
4
5
10
10
FREQUENCY (Hz)
10
10
10
10
10
FREQUENCY (Hz)
10
10
FIGURE 21. EQUIVALENT INPUT NOISE VOLTAGE vs
FREQUENCY
FIGURE 22. EQUIVALENT INPUT NOISE CURRENT vs
FREQUENCY
8
CA3078, CA3078A
Typical Performance Curves (Continued)
RESISTOR-CAPACITOR
COMPENSATION
1.5
1.25
1
0.6
0.5
0.4
0.3
0.2
0.1
0
RESISTOR-CAPACITOR
COMPENSATION
(R - C BETWEEN
1
1
(R - C BETWEEN
1
1
TERMINALS 1 AND 8)
TERMINALS 1 AND 8)
CAPACITOR
COMPENSATION
(BETWEEN
CAPACITOR
COMPENSATION
(BETWEEN
0.75
0.5
0.25
0
TERMINALS 1 AND 8)
TERMINALS 1 AND 8)
0
10
20
30
40
50
60
70
80
90
90
0
10
20
30
40
50
60
70
80
90
90
CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB)
CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB)
6
19.1 29.7 40 50 60 70 80
6
19.1 29.7 40 50 60 70 80
CLOSED LOOP INVERTING VOLTAGE GAIN (dB)
CLOSED LOOP INVERTING VOLTAGE GAIN (dB)
Supply Volts: V+ = +6, V- = -6
Quiescent Current (I ) = 100µA
Supply Volts: V+ = +6, V- = -6
Quiescent Current (I ) = 20µA
Q
Q
o
o
Ambient Temperature (T ) = 25 C
Ambient Temperature (T ) = 25 C
A
A
Load Impedance: R = 10kΩ, C = 100pF
Load Impedance: R = 10kΩ, C = 100pF
L L
L
L
Feedback Resistance (R ) = 0.1MΩ
Feedback Resistance (R ) = 0.1MΩ
F
F
Output Voltage (V
) = 10V
Output Voltage (V
) = 10V
determined for transient response with 10% overshoot on a
OP-P
OP-P
R
determined for transient response with 10% overshoot on a
R
1
1
-6
-6
100mV output signal (R x C = 2 x 10 )
100mV output signal (R x C = 2.5 x 10
)
1
1
1
1
FIGURE 23. SLEW RATE vs CLOSED LOOP GAIN FOR
IQ = 100mA - CA3078
FIGURE 24. SLEW RATE vs CLOSED LOOP GAIN FOR
IQ = 20mA - CA3078A
CAPACITOR
COMPENSATION
(BETWEEN
CAPACITOR
1000
1000
COMPENSATION
(BETWEEN
TERMINALS 1 AND 8)
TERMINALS 1 AND 8)
RESISTOR-CAPACITOR
COMPENSATION
(R - C BETWEEN
RESISTOR-CAPACITOR
COMPENSATION
100
10
1
100
1
1
(R - C BETWEEN
1
1
TERMINALS 1 AND 8)
TERMINALS 1 AND 8)
10
1
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB)
CLOSED LOOP NON-INVERTING VOLTAGE GAIN (dB)
6
19.1 29.7 40 50 60 70 80 90
6
19.1 29.7 40 50 60 70 80 90
CLOSED LOOP INVERTING VOLTAGE GAIN (dB)
CLOSED LOOP INVERTING VOLTAGE GAIN (dB)
Supply Volts: V+ = +6, V- = -6
Quiescent Current (I ) = 100µA
Supply Volts: V+ = +6, V- = -6
Quiescent Current (I ) = 20µA
Q
Q
o
o
Ambient Temperature (T ) = 25 C
Ambient Temperature (T ) = 25 C
A
A
Load Impedance: R = 10kΩ, C = 100pF
Load Impedance: R = 10kΩ, C = 100pF
L L
L
L
Feedback Resistance (R ) = 0.1MΩ
Feedback Resistance (R ) = 0.1MΩ
F
F
Output Voltage (V
) = 100mV
Output Voltage (V
) = 100mV
determined for transient response with 10% overshoot on a
OP-P
OP-P
R
determined for transient response with 10% overshoot on a
R
1
1
-6
-6
100mV output signal (R x C = 2 x 10 )
100mV output signal (R x C = 2.5 x 10
)
1
1
1
1
FIGURE 25. PHASE COMPENSATION CAPACITANCE vs
CLOSED LOOP GAIN - CA3078
FIGURE 26. PHASE COMPENSATION CAPACITANCE vs
CLOSED LOOP GAIN - CA3078A
9
CA3078, CA3078A
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INDEX
AREA
INCHES MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A1
A
D1
e
D
5
C
eC
B
eB
D1
E
5
0.010 (0.25)
C
B
S
M
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
e
6
A
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
10
CA3078, CA3078A
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
M
M
B
0.25(0.010)
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
D
h x 45
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
M
M
S
B
0.25(0.010)
C
A
L
6
NOTES:
N
α
8
8
7
11. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
o
o
o
o
0
8
0
8
-
Rev. 0 12/93
12. Dimensioning and tolerancing per ANSI Y14.5M-1982.
13. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
14. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
15. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
16. “L” is the length of terminal for soldering to a substrate.
17. “N” is the number of terminal positions.
18. Terminal numbers are shown for reference only.
19. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
20. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
11
CA3078, CA3078A
Metal Can Packages (Can)
REFERENCE PLANE
T8.C MIL-STD-1835 MACY1-X8 (A1)
8 LEAD METAL CAN PACKAGE
A
e1
L
INCHES
MILLIMETERS
L2
L1
SYMBOL
A
MIN
MAX
0.185
0.019
0.021
0.024
0.375
0.335
0.160
MIN
4.19
0.41
0.41
0.41
8.51
7.75
2.79
MAX
4.70
0.48
0.53
0.61
9.40
8.51
4.06
NOTES
ØD2
0.165
0.016
0.016
0.016
0.335
0.305
0.110
-
A
A
Øb
Øb1
Øb2
ØD
ØD1
ØD2
e
1
k1
1
Øe
ØD ØD1
2
-
N
1
-
-
Øb1
β
α
C
L
-
Øb
k
F
0.200 BSC
0.100 BSC
5.08 BSC
2.54 BSC
-
BASE AND
Q
e1
-
SEATING PLANE
F
-
0.040
0.034
0.045
0.750
0.050
-
-
1.02
0.86
1.14
19.05
1.27
-
-
BASE METAL
LEAD FINISH
Øb2
k
0.027
0.027
0.500
-
0.69
0.69
12.70
-
-
k1
2
Øb1
L
1
L1
1
SECTION A-A
L2
0.250
0.010
6.35
0.25
1
Q
0.045
1.14
-
NOTES:
o
o
45 BSC
45 BSC
3
α
β
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
o
o
45 BSC
45 BSC
3
4
N
8
8
2. Measured from maximum diameter of the product.
Rev. 0 5/18/94
3. α is the basic spacing from the centerline of the tab to terminal 1
and β is the basic spacing of each lead or lead position (N -1
places) from α, looking at the bottom of the package.
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
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12
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