CA3227M [INTERSIL]
High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz; 高频NPN晶体管阵列用于低功耗应用频率高达1.5GHz的
| 型号： | CA3227M |
| 厂家： | 
Intersil |
| 描述： | High-Frequency NPN Transistor Array For Low-Power Applications at Frequencies Up to 1.5GHz |
| 文件： | 总7页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CA3227
TM
Data Sheet
May 2000
File Number 1345.5
High-Frequency NPN Transistor Array For
Low-Power Applications at Frequencies
Up to 1.5GHz
Features
• Gain-Bandwidth Product (f ) . . . . . . . . . . . . . . . . . >3GHz
T
• Five Transistors on a Common Substrate
The CA3227 consists of five general purpose silicon NPN
transistors on a common monolithic substrate. Each of the
Applications
transistors exhibits a value of f in excess of 3GHz, making
T
• VHF Amplifiers
them useful from DC to 1.5GHz. The monolithic construction
of these devices provides close electrical and thermal
matching of the five transistors.
• VHF Mixers
• Multifunction Combinations - RF/Mixer/Oscillator
• IF Converter
Ordering Information
• IF Amplifiers
PART
NUMBER
(BRAND)
TEMP.
o
• Sense Amplifiers
RANGE ( C)
-55 to 125
-55 to 125
PACKAGE
16 Ld PDIP
16 Ld SOIC
PKG. NO.
E16.3
M16.15
• Synthesizers
CA3227E
• Synchronous Detectors
• Cascade Amplifiers
CA3227M
(3227)
CA3227M96
(3227)
-55 to 125
16 Ld SOIC Tape M16.15
and Reel
Pinout
CA3227
(PDIP, SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
1
Q
Q
2
3
Q
Q
5
4
SUBSTRATE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1
CA3227
Absolute Maximum Ratings
Thermal Information
o
Collector to Emitter Voltage (V
). . . . . . . . . . . . . . . . . . . . . . . 8V
Thermal Resistance (Typical, Note 2)
θJA ( C/W)
CEO
Collector to Base Voltage (V
Collector to Substrate Voltage (V
) . . . . . . . . . . . . . . . . . . . . . . . 12V
, Note 1) . . . . . . . . . . . . . . 20V
CIO
CBO
16 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Power Dissipation (Any One Transistor) . . . . . . . . 85mW
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . 175 C
Maximum Junction Temperature (Plastic Package). . . . . . . . 150 C
90
185
Collector Current (I ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
C
o
o
Operating Conditions
o
o
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
o
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of these devices is isolated from the substrate by an integral diode. The substrate (Terminal 5) must be connected
to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications T = 25 C
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS FOR EACH TRANSISTOR
Collector to Base Breakdown Voltage
Collector to Emitter Breakdown Voltage
Collector to Substrate Breakdown Voltage
Emitter Cutoff Current (Note 3)
Collector Cutoff Current
V
V
V
I
I
I
= 10µA, I = 0
12
20
10
-
-
V
V
(BR)CBO
(BR)CEO
(BR)CIO
EBO
C
E
= 1mA, I = 0
8
-
-
C
B
= 10µA, I = 0, I = 0
20
V
C1
B
E
I
I
I
V
V
V
V
= 4.5V, I = 0
-
-
10
1
µA
µA
nA
EB
CE
CB
CE
C
= 5V, I = 0
-
-
CEO
B
Collector Cutoff Current
= 8V, I = 0
E
-
-
100
-
CBO
DC Forward Current Transfer Ratio
h
= 6V
I
I
I
I
= 10mA
= 1mA
-
40
-
110
150
150
0.71
0.13
-
FE
C
C
C
C
-
= 0.1mA
= 1mA
-
Base to Emitter Voltage
Collector to Emitter Saturation Voltage
Base to Emitter Saturation Voltage
NOTE:
V
V
V
V
= 6V
0.62
-
0.82
0.50
0.94
V
V
V
BE
CE
I
I
= 10mA, I = 1mA
B
CE SAT
BE SAT
C
= 10mA, I = 1mA
0.74
C
B
3. On small-geometry, high-frequency transistors, it is very good practice never to take the Emitter Base Junction into reverse breakdown. To do
so may permanently degrade the h . Hence, the use of I rather than V . These devices are also susceptible to damage by
FE (BR)EBO
EBO
electrostatic discharge and transients in the circuits in which they are used. Moreover, CMOS handling procedures should be employed.
2
CA3227
o
Electrical Specifications T = 25 C, 200MHz, Common Emitter, Typical Values Intended Only for Design Guidance
A
TYPICAL
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR
Input Admittance
Y
Y
Y
Y
Y
Y
Y
Y
b
g
b
g
I
I
I
I
I
I
I
I
= 1mA, V
= 1mA, V
= 1mA, V
= 1mA, V
= 5V
= 5V
= 5V
= 5V
4
mS
mS
11
22
21
12
11
22
21
12
21
11
11
22
22
C
C
C
C
C
C
C
C
CE
CE
CE
CE
0.75
2.7
Output Admittance
mS
0.13
29.3
-33
0.38
-97
4.8
mS
Forward Transfer Admittance
Reverse Transfer Admittance
Input Admittance
Y
mS
21
21
θ
Degrees
mS
Y
12
12
11
11
22
22
θ
b
g
b
g
Degrees
mS
= 10mA, V
= 10mA, V
= 10mA, V
= 10mA, V
= 5V
CE
CE
CE
CE
2.85
2.75
0.9
mS
Output Admittance
= 5V
= 5V
= 5V
mS
mS
Forward Transfer Admittance
Reverse Transfer Admittance
Small Signal Forward Current Transfer Ratio
Y
95
mS
21
21
θ
-62
0.39
-97
7.1
Degrees
mS
Y
12
θ
Degrees
12
h
I
I
= 1mA, V = 5V
CE
C
= 10mA, V
= 5V
17
C
CE
TYPICAL CAPACITANCE AT 1MHz, THREE-TERMINAL MEASUREMENT
Collector to Base Capacitance
Collector to Substrate Capacitance
Collector to Emitter Capacitance
Emitter to Base Capacitance
C
V
V
V
V
= 6V
0.3
1.6
pF
pF
pF
pF
CB
CB
C
= 6V
CI
CE
EB
CI
C
C
= 6V
= 3V
0.4
CE
EB
0.75
Spice Model (Spice 2G.6)
.model NPN
+
+
+
+
+
+
+
+
BF = 2.610E + 02
RC = 1.000E + 01
IK = 1.000E - 01
ISC = 9.25E - 14
CJS = 1.800E - 12
CJC = 9.100E - 13
AF = 1.000E + 00
MJS = 3.530E - 01
BR = 4.401E + 00
RE = 7.396E - 01
ISE = 1.87E - 14
NC = 1.333E + 00
CJE = 1.010E - 12
PC = 3.850E - 01
EF = 1.000E + 00
RBM = 30.00
IS = 6.930E - 16
VA = 6.300E + 01
NE = 1.653E + 00
TF = 1.775E - 11
PE = 8.350E - 01
MC = 2.740E - 01
FC = 5.000E - 01
RBV = 100
RB = 130.0E + 00
VB = 2.208E + 00
IKR = 1.000E - 02
TR = 1.000E - 09
ME = 4.460E - 01
KF = 0.000E + 00
PJS = 5.410E - 01
IRB = 0.00
Please Note: No measurements have been made to model the reverse AC operation (tr is an estimation).
3
CA3227
Typical Performance Curves
160
150
140
130
120
110
100
90
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
o
V
= 5V, T = 25 C
A
CE
80
70
60
50
40
o
V
= 6V, T = 25 C
A
30
20
0.1
CE
1.0
10
100
0
5
10
15
I
(mA)
I
(mA)
C
C
FIGURE 1. h vs COLLECTOR CURRENT
FE
FIGURE 2. f vs COLLECTOR CURRENT
T
o
o
R
= 1kΩ, V
CE
= 6V, T = 25 C
R
= 500Ω, V
CE
= 6V, T = 25 C
SOURCE
A
SOURCE
A
30
20
10
30
FREQUENCY = 10Hz
FREQUENCY = 10Hz
100Hz
20
10
100Hz
1kHz
1kHz
10kHz
10kHz
100kHz
100kHz
10.0
0.01
0.1
1.0
10.0
0.01
0.1
1.0
I
(mA)
I (mA)
C
C
FIGURE 3. NOISE FIGURE vs COLLECTOR CURRENT
FIGURE 4. NOISE FIGURE vs COLLECTOR CURRENT
1.75
1.50
1.25
C
C
CI
1.00
0.75
0.50
EB
C
2
CB
0.25
0
0
1
3
4
5
6
7
8
9
10
BIAS VOLTAGE (V)
FIGURE 5. CAPACITANCE vs BIAS VOLTAGE
4
CA3227
Die Characteristics
DIE DIMENSIONS:
46 mils x 32 mils
Metallization Mask Layout
CA3227
(13)
(14)
(12)
(11)
(15)
(16)
(1)
(10)
(9)
(8)
(2)
(7)
(3)
(4)
(5)
(6)
SUBSTRATE
5
CA3227
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
INCHES
MILLIMETERS
1 2
3
N/2
AREA
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
A2
A
-
SEATING
PLANE
B1
C
8, 10
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
5
eC
C
B
D1
E
5
eB
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in JE-
N
16
16
DEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
6
CA3227
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
0.25(0.010)
M
B M
H
AREA
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
0.25
0.51
0.25
10.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
L
-
SEATING PLANE
A
9
-A-
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
16
16
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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7
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