CA3240A [INTERSIL]
Dual, 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output; 双通道， 4.5MHz ，采用BiMOS与MOSFET的输入运算放大器/双极性输出
| 型号： | CA3240A |
| 厂家： | 
Intersil |
| 描述： | Dual, 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output |
| 文件： | 总15页 (文件大小：604K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CA3240, CA3240A
Data Sheet
August 2001
File Number 1050.5
Dual, 4.5MHz, BiMOS Operational Amplifier
with MOSFET Input/Bipolar Output
Features
• Dual Version of CA3140
• Internally Compensated
• MOSFET Input Stage
The CA3240A and CA3240 are dual versions of the popular
CA3140 series integrated circuit operational amplifiers. They
combine the advantages of MOS and bipolar transistors on
the same monolithic chip. The gate-protected MOSFET
(PMOS) input transistors provide high input impedance and
a wide common-mode input voltage range (typically to 0.5V
below the negative supply rail). The bipolar output
transistors allow a wide output voltage swing and provide a
high output current capability.
- Very High Input Impedance (Z ) 1.5TΩ (Typ)
IN
- Very Low Input Current (I ) 10pA (Typ) at ± 15V
- Wide Common-Mode Input Voltage Range (V
Be Swung 0.5V Below Negative Supply Voltage Rail
I
): Can
ICR
• Directly Replaces Industry Type 741 in Most Applications
Applications
The CA3240A and CA3240 are compatible with the industry
standard 1458 operational amplifiers in similar packages.The
offset null feature is available only when these types are supplied
in the 14 lead PDIP package (E1 suffix).
• Ground Referenced Single Amplifiers in Automobile and
Portable Instrumentation
• Sample and Hold Amplifiers
Ordering Information
• Long Duration Timers/Multivibrators (Microseconds-
Minutes-Hours)
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
8 Ld PDIP
• Photocurrent Instrumentation
• Intrusion Alarm System
• Comparators
• Active Filters
CA3240AE
CA3240AE1
CA3240E
-40 to 85
-40 to 85
-40 to 85
E8.3
14 Ld PDIP
8 Ld PDIP
E14.3
E8.3
• Function Generators
• Power Supplies
• Instrumentation Amplifiers
Functional Diagram
Pinouts
CA3240, CA3240A (PDIP)
TOP VIEW
2mA
4mA
V+
OUTPUT (A)
1
2
3
4
8
7
6
5
V+
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
INV.
INPUT (A)
OUTPUT
INV.
INPUT (B)
NON-INV.
INPUT (B)
NON-INV.
INPUT (A)
200µA
1.6mA
200µA
2µA
2mA
V-
+
OUT-
PUT
IN-
PUT
A ≈ 10
A ≈ 10,000
A ≈ 1
CA3240A (PDIP)
-
C
1
TOP VIEW
12pF
V-
OFFSET
14
NULL (A)
INV.
INPUT (A)
NON-INV.
INPUT (A)
OFFSET
NULL (A)
1
2
3
4
5
6
7
13 V+†
12 OUTPUT (A)
11 NC
OFFSET NULL
V-
OFFSET
NULL (B)
NON - INV.
INPUT (B)
INV.
NOTE: Only available with 14 lead DIP (E1 Suffix).
10 OUTPUT (B)
9
8
V+†
OFFSET
NULL (B)
INPUT (B)
† Pins 9 and 13 internally connected through approximately 3Ω.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001
1
CA3240, CA3240A
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage (Between V+ and V-). . . . . . . . . . . . . . . . . . . . . 36V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 2)
θ
( C/W)
JA
8 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . .
14 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . .
100
100
o
Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C
o
o
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
Voltage Range . . . . . . . . . . . . . . . . . . . . . 4V to 36V or ± 2V to ± 18V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply. Temperatures and/or supply voltages must be limited to keep dissipation within max-
imum rating.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications For Equipment Design, V
= ± 15V, T = 25 C, Unless Otherwise Specified
SUPPLY
A
CA3240
CA3240A
TYP
2
PARAMETER
Input Offset Voltage
SYMBOL
MIN
-
TYP
5
MAX
15
30
50
-
MIN
-
MAX
5
UNITS
mV
pA
V
IO
Input Offset Current
Input Current
I
-
0.5
10
-
0.5
20
40
-
IO
I
-
-
10
pA
I
Large-Signal Voltage Gain
(See Figures 13, 28) (Note 3)
A
20
86
-
100
100
32
20
86
-
100
100
32
kV/V
dB
OL
-
-
Common Mode Rejection
Ratio (See Figure 18)
CMRR
320
-
320
-
µV/V
dB
70
-15
90
70
-15
90
Common Mode Input Voltage Range
(See Figure 25)
V
-15.5 to
+12.5
11
-15.5 to
+12.5
12
V
ICR
Power Supply Rejection Ratio
(See Figure 20)
PSRR
(∆V /∆V± ±
-
100
80
150
-
100
80
150
µV/V
dB
V
IO
76
12
-14
0.4
-
-
-
76
12
-14
0.4
-
-
-
Maximum Output Voltage (Note 4)
(See Figures 24, 25)
V
+
13
13
OM
V
-
-14.4
0.13
8
-
-14.4
0.13
8
-
V
OM
Maximum Output Voltage (Note 5)
V
-
-
V
OM-
I+
Total Supply Current
12
12
mA
(See Figure 16) For Both Amps
Total Device Dissipation
NOTES:
P
-
240
360
-
240
360
mW
D
3. At V = 26V
, +12V, -14V and R = 2kΩ.
L
O
P-P
4. At R = 2kΩ.
L
5. At V+ = 5V, V- = GND, I
SINK
= 200µA.
o
Electrical Specifications For Equipment Design, V
= ± 15V, T = 25 C, Unless Otherwise Specified
A
SUPPLY
TYPICAL VALUES
CA3240A CA3240 UNITS
PARAMETER
SYMBOL
TEST CONDITIONS
Typical Value of Resistor Between Terminals 4 and 3(5)
or Between 4 and 14(8) to Adjust Maximum V
Input Offset Voltage Adjustment Resistor (E1
Package Only)
18
4.7
kΩ
IO
Input Resistance
Input Capacitance
Output Resistance
R
C
1.5
4
1.5
4
TΩ
pF
Ω
I
I
R
60
48
60
48
O
N
Equivalent Wideband Input Noise Voltage
(See Figure 2)
e
BW = 140kHz, R = 1MΩ
µV
S
2
CA3240, CA3240A
o
Electrical Specifications For Equipment Design, V
= ± 15V, T = 25 C, Unless Otherwise Specified (Continued)
SUPPLY
A
TYPICAL VALUES
PARAMETER
SYMBOL
TEST CONDITIONS
f = 1kHz, R = 100Ω
CA3240A CA3240 UNITS
Equivalent Input Noise Voltage
(See Figure 19)
e
40
12
40
12
nV/√Hz
nV/√Hz
mA
N
S
f = 10kHz, R = 100Ω
S
Short-Circuit Current to Opposite Supply
I
+
Source
Sink
40
40
OM
I
-
11
11
mA
OM
Gain Bandwidth Product (See Figures 14, 28)
Slew Rate (See Figure 15)
f
4.5
9
4.5
9
MHz
V/µs
µs
T
SR
Transient Response (See Figure 1)
t
R
R
= 2kΩ, C = 100pF
Rise Time
Overshoot
To 1mV
0.08
10
0.08
10
r
L
L
L
OS
= 2kΩ, C = 100pF
%
L
Settling Time at 10V
(See Figure 26)
t
A
= +1, R = 2kΩ, C = 100pF,
4.5
1.4
120
4.5
1.4
120
µs
P-P
S
V
L
L
Voltage Follower
To 10mV
µs
Crosstalk (See Figure 23)
f = 1kHz
dB
o
Electrical Specifications For Equipment Design, at V
= ± 15V, T = -40 to 85 C, Unless Otherwise Specified
SUPPLY
A
TYPICAL VALUES
PARAMETER
Input Offset Voltage
SYMBOL
|V
CA3240A
CA3240
UNITS
|
3
32
10
32
mV
pA
IO
Input Offset Current (Note 8)
|I
|
IO
Input Current (Note 8)
I
640
63
640
63
pA
I
Large Signal Voltage Gain (See Figures 13, 28), (Note 6)
A
kV/V
dB
OL
96
96
Common Mode Rejection Ratio (See Figure 18)
CMRR
32
32
µV/V
dB
90
90
Common Mode Input Voltage Range (See Figure 25)
Power Supply Rejection Ratio (See Figure 20)
V
-15 to +12.3
150
76
-15 to +12.3
150
76
V
ICR
PSRR
(∆V /∆V± )
µV/V
dB
IO
Maximum Output Voltage (Note 7) (See Figures 24, 25)
V
+
12.4
-14.2
8.4
12.4
-14.2
8.4
V
OM
V
-
V
OM
I+
Supply Current (See Figure 16) Total For Both Amps
Total Device Dissipation
mA
mW
P
252
15
252
15
D
o
Temperature Coefficient of Input Offset Voltage
NOTES:
∆V /∆T
IO
µV/ C
6. At V = 26V
, +12V, -14V and R = 2kΩ.
L
O
P-P
7. At R = 2kΩ.
L
o
8. At T = 85 C.
A
o
Electrical Specifications For Equipment Design, at V+ = 5V, V- = 0V, T = 25 C, Unless Otherwise Specified
A
TYPICAL VALUES
PARAMETER
SYMBOL
|V
CA3240A
CA3240
UNITS
mV
Input Offset Voltage
Input Offset Current
Input Current
|
2
0.1
2
5
0.1
2
IO
|I
|
pA
IO
I
pA
I
Input Resistance
R
1
1
TΩ
IN
Large Signal Voltage Gain (See Figures 13, 28)
A
100
100
100
100
kV/V
dB
OL
3
CA3240, CA3240A
o
Electrical Specifications For Equipment Design, at V+ = 5V, V- = 0V, T = 25 C, Unless Otherwise Specified (Continued)
A
TYPICAL VALUES
PARAMETER
Common-Mode Rejection Ratio
SYMBOL
CA3240A
CA3240
32
UNITS
µV/V
dB
CMRR
32
90
-0.5
2.6
31.6
90
3
90
Common-Mode Input Voltage Range (See Figure 25)
Power Supply Rejection Ratio
V
-0.5
2.6
31.6
90
V
ICR
V
PSRR
µV/V
dB
Maximum Output Voltage (See Figures 24, 25)
Maximum Output Current
V
+
3
V
OM
V
-
0.3
20
1
0.3
20
V
OM
Source
Sink
I
+
mA
mA
V/µs
MHz
mA
mW
OM
I
-
1
OM
SR
Slew Rate (See Figure 15)
7
7
Gain Bandwidth Product (See Figure 14)
Supply Current (See Figure 16)
Device Dissipation
f
4.5
4
4.5
4
T
I+
P
20
20
D
Test Circuits and Waveforms
50mV/Div., 200ns/Div.
Top Trace: Input, Bottom Trace: Output
5V/Div., 1µs/Div.
Top Trace: Input, Bottom Trace: Output
FIGURE 1A. SMALL SIGNAL RESPONSE
FIGURE 1B. LARGE SIGNAL RESPONSE
+15V
0.1µF
10kΩ
SIMULATED
LOAD
+
CA3240
-
2kΩ
100pF
0.1µF
-15V
2kΩ
BW (-3dB) = 4.5MHz
SR = 9V/µs
0.05µF
FIGURE 1C. TEST CIRCUIT
FIGURE 1. SPLIT-SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS
4
CA3240, CA3240A
Test Circuits and Waveforms (Continued)
+15V
0.01µF
R
S
+
1MΩ
NOISE
VOLTAGE
OUTPUT
CA3240
-
30.1kΩ
0.01µF
-15V
1kΩ
BW (-3dB) = 140kHz
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT) = 48µV (TYP)
FIGURE 2. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENT
Schematic Diagram (One Amplifier of Two)
BIAS CIRCUIT
INPUT STAGE
SECOND STAGE
OUTPUT STAGE
DYNAMIC CURRENT SINK
V+
D
7
D
1
R
13
15K
R
50Ω
9
Q
Q
2
20
Q
3
Q
1
D
8
R
10
Q
19
1K
Q
R
14
20K
5
R
Q
Q
4
12
12K
6
R
11
20Ω
Q
7
Q
17
Q
21
R
1K
8
R
8K
1
Q
8
OUTPUT
Q
18
D
D
4
3
D
2
D
5
INVERTING
INPUT
-
Q
Q
10
C
1
9
12pF
NON-INVERTING
INPUT
+
R
500Ω
3
R
500Ω
2
Q
Q
14
Q
16
Q
13
15
D
Q
6
Q
11
12
R
50Ω
R
7
30Ω
6
R
500Ω
R
5
500Ω
4
OFFSET NULL (NOTE 9)
V-
NOTES:
9. Only available with 14 Lead DIP (E1 Suffix).
10. All resistance values are in ohms.
5
CA3240, CA3240A
Application Information
Circuit Description
Input Circuit Considerations
The schematic diagram details one amplifier section of the
CA3240. It consists of a differential amplifier stage using PMOS
As indicated by the typical VICR, this device will accept
inputs as low as 0.5V below V-. However, a series current-
limiting resistor is recommended to limit the maximum input
terminal current to less than 1mA to prevent damage to the
input protection circuitry.
transistors (Q and Q ) with gate-to-source protection against
9
10
static discharge damage provided by zener diodes D , D , and
3
4
D . Constant current bias is applied to the differential amplifier
5
from transistors Q and Q connected as a constant current
source. This assures a high common-mode rejection ratio. The
output of the differential amplifier is coupled to the base of gain
2
5
Moreover, some current-limiting resistance should be
provided between the inverting input and the output when
the CA3240 is used as a unity-gain voltage follower. This
resistance prevents the possibility of extremely large input-
signal transients from forcing a signal through the input-
protection network and directly driving the internal constant-
current source which could result in positive feedback via the
output terminal. A 3.9kΩ resistor is sufficient.
stage transistor Q by means of an NPN current mirror that
13
supplies the required differential-to-single-ended conversion.
Provision for offset null for types in the 14 lead plastic package
(E1 suffix) is provided through the use of this current mirror.
The gain stage transistor Q has a high impedance active
13
load (Q and Q ) to provide maximum open-loop gain. The
3
4
The typical input current is on the order of 10pA when the
inputs are centered at nominal device dissipation. As the
output supplies load current, device dissipation will increase,
rasing the chip temperature and resulting in increased input
current. Figure 4 shows typical input-terminal current versus
ambient temperature for the CA3240.
collector of Q directly drives the base of the compound
13
emitter-follower output stage. Pulldown for the output stage is
provided by two independent circuits: (1) constant-current-
connected transistors Q and Q and (2) dynamic current-
14 15
sink transistor Q and its associated circuitry. The level of
16
pulldown current is constant at about 1mA for Q and varies
15
from 0 to 18mA for Q depending on the magnitude of the
16
voltage between the output terminal and V+. The dynamic
current sink becomes active whenever the output terminal is
more negative than V+ by about 15V. When this condition
+HV
V+
LOAD
CA3240
exists, transistors Q and Q are turned on causing Q to
21 16 16
R
L
sink current from the output terminal to V-. This current always
flows when the output is in the linear region, either from the
load resistor or from the emitter of Q if no load resistor is
18
present. The purpose of this dynamic sink is to permit the
output to go within 0.2V (V
ground. When the load is returned to V+, it may be necessary
(sat)) of V- with a 2kΩ load to
CE
R
S
LOAD
to supplement the 1mA of current from Q in order to turn on
120V
AC
15
30V NO LOAD
the dynamic current sink (Q ). This may be accomplished by
placing a resistor (Approx. 2kΩ) between the output and V-.
16
MT
2
1
Output Circuit Considerations
CA3240
MT
Figure 24 shows output current-sinking capabilities of the
CA3240 at various supply voltages. Output voltage swing to
the negative supply rail permits this device to operate both
power transistors and thyristors directly without the need for
level-shifting circuitry usually associated with the 741 series
of operational amplifiers.
R
L
FIGURE 3. METHODS OF UTILIZING THE V
SINKING
CE (SAT)
CURRENT CAPABILITY OF THE CA3240 SERIES
Figure 3 shows some typical configurations. Note that a series
resistor, RL, is used in both cases to limit the drive available to
the driven device. Moreover, it is recommended that a series
diode and shunt diode be used at the thyristor input to prevent
large negative transient surges that can appear at the gate of
thyristors, from damaging the integrated circuit.
6
CA3240, CA3240A
shift in the output voltage (Terminal 7) of the CA3240E.
10K
These positive transitions are fed into the CA3059, which is
used as a latching circuit and zero-crossing TRIAC driver.
When a positive pulse occurs at Terminal 7 of the CA3240E,
the TRIAC is turned on and held on by the CA3059 and its
associated positive feedback circuitry (51kΩ resistor and
36kΩ/42kΩ voltage divider). When the positive pulse occurs
at Terminal 1 (CA3240E), the TRIAC is turned off and held
off in a similar manner. Note that power for the CA3240E is
supplied by the CA3059 internal power supply.
V
= ± 15V
S
1K
100
10
The advantage of using the CA3240E in this circuit is that it
can sense the small currents associated with skin
conduction while allowing sufficiently high circuit impedance
to provide protection against electrical shock.
-60
-40 -20
0
20
40
60
o
80 100 120 140
TEMPERATURE ( C)
Dual Level Detector (Window Comparator)
FIGURE 4. INPUT CURRENT vs TEMPERATURE
Figure 7 illustrates a simple dual liquid level detector using
the CA3240E as the sensing amplifier. This circuit operates
on the principle that most liquids contain enough ions in
solution to sustain a small amount of current flow between
two electrodes submersed in the liquid. The current, induced
by an 0.5V potential applied between two halves of a PC
board grid, is converted to a voltage level by the CA3240E in
a circuit similar to that of the on/off touch switch shown in
Figure 6. The changes in voltage for both the upper and
lower level sensors are processed by the CA3140 to activate
an LED whenever the liquid level is above the upper sensor
or below the lower sensor.
It is well known that MOSFET devices can exhibit slight
changes in characteristics (for example, small changes in
input offset voltage) due to the application of large
differential input voltages that are sustained over long
periods at elevated temperatures.
Both applied voltage and temperature accelerate these
changes. The process is reversible and offset voltage shifts
of the opposite polarity reverse the offset. In typical linear
applications, where the differential voltage is small and
symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational
amplifier employing a bipolar transistor input stage.
Constant-Voltage/Constant-Current Power Supply
The constant-voltage/constant-current power supply shown
in Figure 8 uses the CA3240E1 as a voltage-error and
current-sensing amplifier. The CA3240E1 is ideal for this
application because its input common-mode voltage range
includes ground, allowing the supply to adjust from 20mV to
25V without requiring a negative supply voltage. Also, the
ground reference capability of the CA3240E1 allows it to
sense the voltage across the 1Ω current-sensing resistor in
the negative output lead of the power supply. The CA3086
transistor array functions as a reference for both constant-
voltage and constant-current limiting. The 2N6385 power
Darlington is used as the pass element and may be required
to dissipate as much as 40W. Figure 9 shows the transient
response of the supply during a 100mA to 1A load transition.
Offset-Voltage Nulling
The input offset voltage of the CA3240AE1 and CA3240E1
can be nulled by connecting a 10kΩ potentiometer between
Terminals 3 and 14 or 5 and 8 and returning its wiper arm to
Terminal 4, see Figure 5A. This technique, however, gives
more adjustment range than required and therefore, a
considerable portion of the potentiometer rotation is not fully
utilized. Typical values of series resistors that may be placed
at either end of the potentiometer, see Figure 5B, to optimize
its utilization range are given in the table “Electrical
Specifications for Equipment Design” shown on third page of
this data sheetAn alternate system is shown in Figure 5C.
This circuit uses only one additional resistor of approximately
the value shown in the table. For potentiometers, in which the
resistance does not drop to 0Ω at either end of rotation, a
value of resistance 10% lower than the values shown in the
table should be used.
Precision Differential Amplifier
Figure 10 shows the CA3240E in the classical precision
differential amplifier circuit. The CA3240E is ideally suited for
biomedical applications because of its extremely high input
impedance. To insure patient safety, an extremely high
electrode series resistance is required to limit any current
that might result in patient discomfort in the event of a fault
condition. In this case, 10MΩ resistors have been used to
limit the current to less than 2µA without affecting the
performance of the circuit. Figure 11 shows a typical
electrocardiogram waveform obtained with this circuit.
Typical Applications
On/Off Touch Switch
The on/off touch switch shown in Figure 6 uses the
CA3240E to sense small currents flowing between two
contact points on a touch plate consisting of a PC board
metallization “grid”. When the “on” plate is touched, current
flows between the two halves of the grid causing a positive
7
CA3240, CA3240A
V+
13(9)
V+
1(7)
2(6)
CA3240
12(10)
CA3240
14(8)
4
3
(5)
R (NOTE 11)
R
10kΩ
(NOTE 11)
10kΩ
V-
V-
FIGURE 5B. IMPROVED RESOLUTION
FIGURE 5A. BASIC
V+
CA3240
10kΩ
(NOTE 11)
V-
FIGURE 5C. SIMPLER IMPROVED RESOLUTION
R
NOTE:
11. See Electrical Specification Table for value of R.
FIGURE 5. THREE OFFSET-VOLTAGE NULLING METHODS, (CA3240AE1 ONLY)
44M
+6V
10K (2W)
120V/220V
AC
60Hz/50Hz
+6V
R
(NOTE 12)
S
“ON”
51K
8
40W
120V LIGHT
1M
36K
5
12K
-
6
5
MT
2
1/2
CA3240
+
+6V
7
1
13
9
0.01µF
8
4
T2300B (NOTE 12)
1N914
42K
5.1M
CA3059
G
MT
1
10
11
1M
“OFF”
+
3
2
COMMON
7
1/2
CA3240
2
1N914
-
1M
+
0.01µF
+6V SOURCE
4
100µF (16V)
-
44M
NOTE:
12. At 220V operation, TRIAC should be T2300D, R = 18K, 5W.
S
FIGURE 6. ON/OFF TOUCH SWITCH
8
CA3240, CA3240A
12M
+15V
0.1µF
8
+15V
100K
-
2
3
1/2
1
CA3240
+
+15V
240K
0.1µF
7
33K
3
2
+
HIGH
LEVEL
160K
100K
CA3140
(0.5V)
6
-
680Ω
LED
8.2K
+
5
6
4
100K
1/2
7
CA3240
100K
-
4
LED ON WHEN
LIQUID OUTSIDE
OF LIMITS
LOW
LEVEL
12M
FIGURE 7. DUAL LEVEL DETECTER
V
O
I
V+
13
O
2N6385
2
10K
3
DARLINGTON
75Ω
3K
-
1
2
1/2
12
CA3240E1
180K
+
+
-
1
4
500
µF
100Ω
1N914
2.7K
V = 30V
I
100K
+
-
0.056µF
2000µF
50V
2.2K
82K
V+
10
2
1
+
-
5µF
16V
9
11
100K
-
7
6
1/2
14
13
10
CA3240E1
100K
9
8
7
CA3086E
+
12
3
5
TRANSISTOR
ARRAY
820Ω
680K
50K
1K
4
6
6.2K
1Ω
1W
100K
CHASSIS GROUND
RANGE = 20mV TO 25V
LOAD REGULATION:
VOLTAGE <0.08%
CURRENT <0.05%
V
OUTPUT HUM AND NOISE ≤ 150µV
RMS
O
(10MHz BANDWIDTH)
SINE REGULATION ≤ 0.1%/V
O
I
RANGE = 10mA - 1.3A
O
FIGURE 8. CONSTANT-VOLTAGE/CONSTANT-CURRENT POWER SUPPLY
9
CA3240, CA3240A
Top Trace: Output Voltage;
500mV/Div., 5µs/Div.
Bottom Trace: Collector Of Load Switching Transistor
Load = 100mA to 1A; 5V/Div., 5µs/Div.
FIGURE 9. TRANSIENT RESPONSE
+15V
0.1µF
8
100K 1%
2000pF
10M
+
1/2
3
2
1
CA3240
-
2000pF
+15V
0.1µF
1%
5.1K
GAIN
CONTROL
7
100K 1%
100K
3.9K
OUTPUT
2
3
CA3140
6
2K
100K 1%
2000pF
5.1K
1%
4
TWO COND.
SHIELDED
CABLE
0.1µF
-
-15V
6
5
1/2
7
CA3240
+
FREQUENCY RESPONSE (-3dB) DC TO 1MHz
SLEW RATE = 1.5V/µs
COMMON MODE REJ: 86dB
10M
4
GAIN RANGE: 35dB TO 60dB
0.1µF
-15V
FIGURE 10. PRECISION DIFFERENTIAL AMPLIFIER
10
CA3240, CA3240A
Vertical: 1.0mV/Div.
Amplifier Gain = 100X
Scope Sensitivity = 0.1V/Div.
Horizontal: >0.2s/Div. (Uncal)
FIGURE 11. TYPICAL ELECTROCARIOGRAM WAVEFORM
0.015µF
100K
+15V
+15V
8
2
-
+15V
1/2
7
1
7
CA3240E
2K
3
2
5.1K
C30809
PHOTO
DIODE
+
+
3
5
200K
1.3
K
OUTPUT
CA3140
6
-
+
1/2
CA3240E
13K
2K
4
6
-
-15V
4
C30809
PHOTO
DIODE
-15V
200k
100K
0.015µF
FIGURE 12. DIFFERENTIAL LIGHT DETECTOR
only the difference is amplified. In this manner, the circuit
can be used over a wide range of ambient light conditions
without circuit component adjustment. Also, when used with
a light source, the circuit will not be sensitive to changes in
light level as the source ages.
Differential Light Detector
In the circuit shown in Figure 12, the CA3240E converts the
current from two photo diodes to voltage, and applies 1V of
reverse bias to the diodes. The voltages from the CA3240E
outputs are subtracted in the second stage (CA3140) so that
11
CA3240, CA3240A
Typical Performance Curves
R
C
= 2kΩ
= 100pF
L
L
R
= 2kΩ
L
20
10
125
100
75
o
o
T
= -40 C
T
= -40 C
A
A
o
o
25 C
25 C
o
85 C
o
85 C
50
25
1
0
5
10
15
20
25
0
5
10
15
20
25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 13. OPEN LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE
FIGURE 14. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE
20
10
R
C
= 2kΩ
= 100pF
L
L
R
= ∞
L
9
8
7
6
5
4
3
2
o
25 C
o
15
10
T
= -40 C
A
o
25 C
o
85 C
o
T
= -40 C
A
o
85 C
5
0
0
5
10
15
20
25
0
5
10
15
20
25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 15. SLEW RATE vs SUPPLY VOLTAGE
FIGURE 16. QUIESCENTSUPPLY CURRENT vs SUPPLY VOLTAGE
120
SUPPLY VOLTAGE: V = ± 15V
A
S
SUPPLY VOLTAGE: V = ± 15V
o
S
T
= 25 C
o
T
= 25 C
A
25
100
80
60
40
20
0
20
15
10
5
0
1
2
3
4
5
6
7
10
10
10
10
10
10
10
10K
100K
1M
4M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 17. MAXIMUM OUTPUT VOLTAGE SWING vs
FREQUENCY
FIGURE 18. COMMON MODE REJECTION RATIO vs
FREQUENCY
12
CA3240, CA3240A
Typical Performance Curves (Continued)
1000
100
10
SUPPLY VOLTAGE: V = ± 15V
S
SUPPLY VOLTAGE: V = ± 15V
A
S
o
T
= 25 C
o
A
T
= 25 C
100
POWER SUPPLY
REJECTION RATIO = ∆V /∆
V
S
IO
R
= 100Ω
S
80
60
40
+PSRR
-PSRR
20
1
1
2
3
4
5
6
7
1
2
3
4
5
10
1
10
10
10
10
10
10
10
10
10
10
10
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. EQUIVALENT INPUT NOISE VOLTAGE vs
FREQUENCY
FIGURE 20. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
o
o
T
= 25 C
T
= 25 C
A
A
12
10
8
17.5
V
R
= ± 15V
= ∞
V
= ± 15V
S
L
S
15
ONE AMPLIFIER OPERATING
12.5
10
6
7.5
4
2
0
5
2.5
-15
-10
-5
0
5
10
15
-15
-10
-5
0
5
10
15
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
FIGURE 21. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE
FIGURE 22. SUPPLY CURRENT vs OUTPUT VOLTAGE
1000
V- = 0V
o
o
T
= 25 C
A
T
= 25 C
A
AMP A → AMP B
AMP B → AMP A
140
130
120
110
100
90
V
V
= ± 15V
S
O
= 5V
V+ = +5V
RMS
100
+15V
+30V
10
80
1.0
0.01
1
2
3
0.1
1
10
FREQUENCY (Hz)
10
10
0.1
1.0
10
LOAD (SINKING) CURRENT (mA)
FIGURE 23. CROSSTALK vs FREQUENCY
FIGURE 24. VOLTAGE ACROSS OUTPUT TRANSISTORS Q
15
AND Q vs LOAD CURRENT
16
13
CA3240, CA3240A
Typical Performance Curves (Continued)
R
= ∞
L
R
= ∞
L
0
-0.5
-1
1.5
1.0
OUTPUT VOLTAGE (+V
)
O
OUTPUT VOLTAGE (-V
COMMON MODE VOLTAGE (-V
)
O
COMMON MODE VOLTAGE (+V
ICR
)
)
ICR
o
0.5
0
T
= 25 C
A
o
o
T
= -40 C TO 85 C
A
o
= 85 C
-1.5
-2
o
T
A
T
= 85 C
A
o
T
= 85 C
A
-0.5
-1.0
-1.5
o
T
= -40 C
A
-2.5
-3
o
T
= 25 C
A
o
T
= 25 C
A
o
o
T
= -40 C
A
T
= -40 C
A
0
5
10
15
20
25
0
5
10
15
20
25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 25A.
FIGURE 25B.
FIGURE 25. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
SUPPLY VOLTAGE:
o
V
= ± 15V
S
T
= 25 C, R = 2kΩ, C = 100pF
A
L L
+15V
+
10
8
1mV
1mV
0.1µF
0.1µF
10mV
10mV
SIMULATED
LOAD
6
10kΩ
CA3240
4
-
2
2kΩ
100pF
FOLLOWER
INVERTING
0
-2
-4
-6
-8
-10
-15V
1mV
10mV
1mV
2kΩ
10mV
6
0.05µF
2
4
8
2
4
6
8
0.1
1.0
10
TIME (µs)
FIGURE 26A. SETTLING TIME vs INPUT VOLTAGE
FIGURE 26B. TEST CIRCUIT (FOLLOWER)
5kΩ
+15V
-
0.1µF
0.1µF
5kΩ
SIMULATED
LOAD
CA3240
+
200Ω
4.99kΩ
2kΩ
100pF
-15V
5.11kΩ
SETTLING POINT
1N914
D
D
2
1
1N914
FIGURE 26C. TEST CIRCUIT (INVERTING)
FIGURE 26. INPUT VOLTAGE vs SETTLING TIME
14
CA3240, CA3240A
Typical Performance Curves (Continued)
10K
-75
V
= ± 15V
= 25 C
S
V
= ± 15V
o
S
-90
T
A
R
C
= 2kΩ,
= 0pF
L
100
80
-105
L
PHASE
-120
-135
1K
R
C
= 2kΩ,
L
-150
= 100pF
L
60
100
GAIN
40
10
1
20
0
1
2
3
4
5
6
7
8
-60 -40 -20
0
20
40
60
80 100 120 140
10
10
10
10
10
10
10
10
o
TEMPERATURE ( C)
FREQUENCY (Hz)
FIGURE 27. INPUT CURRENT vs TEMPERATURE
FIGURE 28. OPEN LOOP VOLTAGE GAIN AND PHASE vs
FREQUENCY
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
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