CA3318_02 [INTERSIL]
CMOS Video Speed, 8-Bit, Flash A/D Converter; CMOS视频速度， 8位，闪存A / D转换器
| 型号： | CA3318_02 |
| 厂家： | 
Intersil |
| 描述： | CMOS Video Speed, 8-Bit, Flash A/D Converter |
| 文件： | 总12页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
CA3318
CMOS Video Speed,
November 2002
8-Bit, Flash A/D Converter
Features
Description
• CMOS Low Power with SOS Speed (Typ) . . . . . . . .150mW
The CA3318 is a CMOS parallel (FLASH) analog-to-digital
converter designed for applications demanding both low
power consumption and high speed digitization.
• Parallel Conversion Technique
• 15MHz Sampling Rate (Conversion Time). . . . . . . 67ns
• 8-Bit Latched Three-State Output with Overflow Bit
• Accuracy (Typ). . . . . . . . . . . . . . . . . . . . . . . . . . ±1 LSB
The CA3318 operates over a wide full scale input voltage
range of 4V up to 7.5V with maximum power consumption
depending upon the clock frequency selected. When
• Single Supply Voltage. . . . . . . . . . . . . . . . . . 4V to 7.5V operated from a 5V supply at a clock frequency of 15MHz,
the typical power consumption of the CA3318 is 150mW.
• 2 Units in Series Allow 9-Bit Output
The intrinsic high conversion rate makes the CA3318 ideally
suited for digitizing high speed signals. The overflow bit
makes possible the connection of two or more CA3318s in
series to increase the resolution of the conversion system. A
series connection of two CA3318s may be used to produce a
9-bit high speed converter. Operation of two CA3318s in
parallel doubles the conversion speed (i.e., increases the
sampling rate from 15MHz to 30MHz).
• 2 Units in Parallel Allow 30MHz Sampling Rate
Applications
• TV Video Digitizing (Industrial/Security/Broadcast)
• High Speed A/D Conversion
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• General-Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
256 paralleled auto balanced voltage comparators measure
the input voltage with respect to a known reference to
produce the parallel bit outputs in the CA3318.
255 comparators are required to quantize all input voltage
levels in this 8-bit converter, and the additional comparator is
required for the overflow bit.
• Motion Signature Analysis
• µP Data Acquisition Systems
Part Number Information
o
PART NUMBER LINEARITY (INL, DNL)
SAMPLING RATE
15MHz (67ns)
15MHz (67ns)
15MHz (67ns)
TEMP. RANGE ( C)
-40 to 85
PACKAGE
24 Ld PDIP
PKG. NO.
E24.6
CA3318CE
CA3318CM
CA3318CD
±1.5 LSB
±1.5 LSB
±1.5 LSB
-40 to 85
24 Ld SOIC
M24.3
D24.6
-40 to 85
24 Ld SBDIP
Pinout
CA3318
(PDIP, SBDIP, SOIC)
TOP VIEW
(LSB) B1
1
2
3
4
5
6
7
8
9
24
V
3
+ (ANA. SUP.)
AA
B2
23 / R
4
22
B3
B4
V
+
REF
IN
21 V
20 p
B5
B6
19 PHASE
18 CLK
B7
(MSB) B8
17 V - (ANA. GND)
AA
OVERFLOW
1
16 V
IN
15
/ R 10
V
-
REF
4
(DIG. GND) V
11
12
14 CE1
13 CE2
SS
DD
(DIG. SUP.) V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
FN3103.3
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
CA3318
Functional Block Diagram
V
V
+
DD
AA
24
ANALOG
SUPPLY
DIGITAL
SUPPLY
φ2 φ1
φ1
φ1
φ1
φ2
φ1
12
THREE-
STATE
V
IN
21
OUTPUT
REGISTER DRIVERS
OVER-
FLOW
COUNT
256
V
+
1
REF
22
/
R
2
9
D
Q
D
Q
D
Q
CAB
# 256
CLK
BIT 8
R = 2Ω
LATCH
256
LATCH
256
(MSB)
8
D
Q
ENCODER
LOGIC
ARRAY
CLK
COUNT
193
R
BIT 7
7
3
/
REF
D
Q
D
Q
4
D
Q
CAB
# 193
23
= 7Ω
CLK
LATCH
LATCH
BIT 6
6
R
R
D
Q
COUNT
129
CLK
D
Q
D
Q
1
/
REF
2
BIT 5
5
CAB
# 129
20
D
Q
= 30Ω
CLK
LATCH
LATCH
R
R
BIT 4
4
COUNT
65
D
Q
1
/
REF
D
Q
D
Q
4
CLK
CAB
# 65
10
= 4Ω
BIT 3
3
D
Q
LATCH
LATCH
R
V
IN
16
CLK
COUNT
1
BIT 2
2
D
Q
D
Q
R ≅ 2K
D
Q
V
-
CAB
REF
15
CLK
(NOTE 1)
BIT 1
(LSB)
COMPARATOR #1
1
LATCH
1
LATCH
11
/
R
2
D
Q
1
≅ 50K
CLK
φ1 (AUTO BALANCE)
CLOCK
18
PHASE
19
CE1
14
φ2 (SAMPLE UNKNOWN)
V
-
AA
17
CE2
13
ANALOG
GND
NOTE:
1. Cascaded Auto Balance (CAB).
V
SS
DIGITAL
GND
11
2
CA3318
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range (V
or V +). . . . . . . . . . -0.5V to +8V
AA
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
DD
JA
JC
(Referenced to V or V - Terminal, Whichever is More Negative)
Input Voltage Range
SBDIP Package. . . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
60
60
75
22
N/A
N/A
SS AA
CE2 and CE1 . . . . . . . . . . . . . . . . . . . . V - -0.5V to V
+ 0.5V
AA
DD
1
Clock, Phase, V
Clock, Phase, V
3
-,
-,
/
/
Ref. . . . . . . V - -0.5V to V + + 0.5V
Ref. . . . . . . . V - -0.5V to V
SS DD
REF
REF
REF
2
4
AA AA
1
o
+ 0.5V
o
V
,
/
REF, V
+ . . . . . . . . . . . . . .V - -0.5V to V - + 7.5V
IN
4
AA AA
o
o
Output Voltage Range,. . . . . . . . . . . . . . . V - 0.5V to V
+ 0.5V
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 265 C
SS
DD
o
Bits 1-8, Overflow (Outputs Off)
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
(SOIC - Lead Tips Only)
Clock, Phase, CE1, CE2, V , Bits 1-8, Overflow
IN
Operating Conditions
Operating Voltage Range (V
or V +) . . 4V (Min) to 7.5V (Max)
AA
DD
Recommended V + Operating Range. . . . . . . . . . . . . . . V
±1V
AA
DD
Recommended V - Operating Range . . . . . . . . . . . . . . . V ±1V
AA SS
o
o
Operating Temperature Range (T ). . . . . . . . . . . . . . -40 C to 85 C
A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications At 25 C, V + = V = 5V, V
+ = 6.4V, V - = V - = V , CLK = 15MHz,
REF AA SS
AA
DD
REF
All Reference Points Adjusted, Unless Otherwise Specified
PARAMETER
SYSTEM PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
8
-
-
-
Bits
LSB
LSB
LSB
Integral Linearity Error
Differential Linearity Error
Offset Error, Unadjusted
-
-
± 1.5
+1, -0.8
6.4
-
1
-0.5
4.5
V
V
= V
= V
- +
+ -
/
LSB
LSB
IN
IN
REF
REF
2
2
1
Gain Error Unadjusted
-1.5
0
1.5
LSB
/
DYNAMIC CHARACTERISTICS
Maximum Input Bandwidth
Maximum Conversion Speed
Signal to Noise Ratio (SNR)
(Note 1) CA3318
CLK = Square Wave
2.5
15
-
5.0
17
47
43
-
-
-
-
MHz
MSPS
dB
f
f
= 15MHz, f = 100kHz
IN
S
S
RMSSignal
=--------------------------------
RMSNoise
= 15MHz, f = 4MHz
IN
-
dB
Signal to Noise Ratio (SINAD)
f
f
= 15MHz, f = 100kHz
IN
-
-
45
35
-
-
dB
dB
S
S
RMSSignal
= 15MHz, f = 4MHz
IN
=-----------------------------------------------------------
RMSNoise+Distortion
Total Harmonic Distortion, THD
f
f
f
f
= 15MHz, f = 100kHz
IN
-
-
-
-
-
-
-46
-36
7.2
5.5
2
-
-
-
-
-
-
dBc
dBc
Bits
Bits
%
S
S
S
S
= 15MHz, f = 4MHz
IN
Effective Number of Bits (ENOB)
= 15MHz, f = 100kHz
IN
= 15MHz, f = 4MHz
IN
Differential Gain Error
Differential Phase Error
ANALOG INPUTS
Unadjusted
Unadjusted
1
%
Full Scale Range, V and (V
IN
+) - (V
-)
REF
Notes 2, 4
4
-
-
30
-
7
-
V
REF
Input Capacitance, V
pF
mA
IN
Input Current, V , (See Text)
IN
V
= 5V, V
+ = 5V
REF
-
3.5
IN
REFERENCE INPUTS
Ladder Impedance
270
500
800
Ω
3
CA3318
o
Electrical Specifications At 25 C, V + = V = 5V, V
+ = 6.4V, V - = V - = V , CLK = 15MHz,
REF AA SS
AA
DD
REF
All Reference Points Adjusted, Unless Otherwise Specified (Continued)
PARAMETER
DIGITAL INPUTS
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Low Level Input Voltage, V
CE1, CE2
OL
Note 4
Note 4
-
-
-
-
0.2V
V
V
DD
AA
Phase, CLK
0.2V
High Level Input Voltage, V
CE1, CE2
IN
Note 4
Note 4
Note 3
0.7V
-
-
-
-
V
V
DD
AA
Phase, CLK
0.7V
Input Leakage Current, I (Except CLK Input)
-
-
±0.2
3
±5
µA
pF
I
Input Capacitance, C
-
I
DIGITAL OUTPUTS
Output Low (Sink) Current
V
V
= 0.4V
4
-4
-
10
-6
-
-
mA
mA
µA
pF
O
O
Output High (Source) Current
= 4.5V
Three-State Output Off-State Leakage Current, I
±0.2
4
±5
-
OZ
Output Capacitance, C
-
O
TIMING CHARACTERISTICS
Auto Balance Time (φ1)
33
-
ns
∞
Sample Time (φ2)
Aperture Delay
Aperture Jitter
Note 4
25
-
-
500
ns
ns
ps
ns
ns
ns
ns
15
100
50
40
18
18
-
-
-
Data Valid Time, t
Note 4
Note 4
-
65
-
D
Data Hold Time, t
25
-
H
Output Enable Time, t
EN
-
Output Disable Time, t
DIS
POWER SUPPLY CHARACTERISTICS
-
-
Device Current (I
+ I ) (Excludes I )
REF
Continuous Conversion (Note 4)
-
-
30
30
60
60
mA
mA
DD
A
Auto Balance (φ1)
NOTES:
1. A full scale sine wave input of greater than f
/2 or the specified input bandwidth (whichever is less) may cause an erroneous code.
CLOCK
The -3dB bandwidth for frequency response purposes is greater than 30MHz.
2. V (Full Scale) or V + should not exceed V + + 1.5V for accuracy.
IN REF AA
3. The clock input is a CMOS inverter with a 50kΩ feedback resistor and may be AC coupled with 1V
minimum source.
P-P
4. Parameter not tested, but guaranteed by design or characterization.
Timing Waveforms
DECODED DATA IS SHIFTED
TO OUTPUT REGISTERS
COMPARATOR DATA IS LATCHED
CLOCK (PIN 18)
IF PHASE (PIN 19)
φ1
φ2
φ1
φ2
φ2
IS LOW
SAMPLE
N + 1
SAMPLE
N + 2
CLOCK IF
PHASE IS HIGH
SAMPLE
AUTO
BALANCE
AUTO
BALANCE
N
t
D
t
H
DATA
N - 2
DATA
N - 1
DATA
N
FIGURE 1. INPUT TO OUTPUT TIMING DIAGRAM
4
CA3318
Timing Waveforms (Continued)
CE1
CE2
t
t
EN
DIS
t
t
EN
DIS
BITS 1 - 8
OF
DATA
DATA
DATA
HIGH
HIGH
IMPEDANCE
IMPEDANCE
DATA
HIGH
IMPEDANCE
FIGURE 2. OUTPUT ENABLE TIMING DIAGRAM
AUTO
BALANCE
AUTO
BALANCE
SAMPLE
N
SAMPLE
N + 1
CLOCK
NO MAX
LIMIT
25ns
MIN
33ns
MIN
25ns
MIN
50ns
MIN
DATA
FIGURE 3A. STANDBY IN INDEFINITE AUTO BALANCE (SHOWN WITH PHASE = LOW)
AUTO
AUTO
BALANCE
BALANCE
SAMPLE
N
SAMPLE
N + 1
SAMPLE
N + 2
CLOCK
500ns
MAX
33ns
MIN
25ns
MIN
50ns
TYP
DATA
N - 1
DATA
N
DATA
FIGURE 3B. STANDBY IN SAMPLE (SHOWN WITH PHASE = LOW)
FIGURE 3. PULSE MODE OPERATION
5
CA3318
Typical Performance Curves
40
28
27
26
25
24
23
35
30
25
20
15
10
0
10
20
30
-50
-25
0
25
50
75
100
o
f
(MHz)
S
TEMPERATURE ( C)
FIGURE 4. DEVICE CURRENT vs SAMPLE FREQUENCY
FIGURE 5. DEVICE CURRENT vs TEMPERATURE
8.0
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0
f
= 15MHz
f
= 15MHz, f = 1MHz
I
S
S
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
INL
DNL
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 6. ENOB vs TEMPERATURE
FIGURE 7. NON-LINEARITY vs TEMPERATURE
1.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0
1.20
1.08
0.96
0.84
0.72
0.60
0.48
0.36
0.24
0.12
0
f
= 15MHz
S
INL
INL
DNL
DNL
0
1
2
3
4
5
6
7
0
5
10
15
20
25
V
(V)
REF
f
(MHz)
S
FIGURE 8. NON-LINEARITY vs SAMPLE FREQUENCY
FIGURE 9. NON-LINEARITY vs REFERENCE VOLTAGE
6
CA3318
Typical Performance Curves (Continued)
8.0
7.6
f
= 15MHz
7.2
6.8
6.4
6.0
5.6
5.2
4.8
S
4.4
4.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
f (MHz)
I
FIGURE 10. ENOB vs INPUT FREQUENCY
Pin Descriptions
CHIP ENABLE TRUTH TABLE
PIN
1
NAME
B1
DESCRIPTION
Output Data Bits
(High = True)
CE1
CE2
B1 - B8
Valid
OF
Valid
Bit 1 (LSB)
Bit 2
0
1
1
0
2
B2
1
X
Three-State
Three-State
Valid
3
B3
Bit 3
Three-State
4
B4
Bit 4
X = Don’t Care
5
B5
Bit 5
Theory of Operation
6
B6
Bit 6
A sequential parallel technique is used by the CA3318
converter to obtain its high speed operation. The sequence
consists of the “Auto-Balance” phase, φ1, and the “Sample
Unknown” phase, φ2. (Refer to the circuit diagram.) Each
conversion takes one clock cycle (see Note). With the phase
control (pin 19) high, the “Auto-Balance” (φ1) occurs during
the high period of the clock cycle, and the “Sample Unknown”
(φ2) occurs during the low period of the clock cycle.
7
B7
Bit 7
8
B8
Bit 8 (MSB)
Overflow
Reference Ladder
Digital Ground
9
OF
1
1
10
11
12
13
/
R
/ Point
4
4
V
V
SS
Digital Power Supply, +5V
DD
CE2
Three-State Output Enable Input,
Active Low, See Truth Table.
NOTE: The device requires only a single phase clock The terminology
of φ1 and φ2 refers to the high and low periods of the same clock.
14
CE1
Three-State Output Enable Input
Active High. See Truth Table.
During the “Auto-Balance” phase, a transmission switch is
used to connect each of the first set of 256 commutating
capacitors to their associated ladder reference tap. Those
tap voltages will be as follows:
15
16
17
18
19
V
-
Reference Voltage Negative Input
Analog Signal Input
Analog Ground
REF
V
IN
V
(N) = [(N/256) V
REF
] - (1/512) V ]
REF
V
-
TAP
AA
CLK
PHASE
= [(2N - 1)/512] V
,
Clock Input
REF
Where:
Sample clock phase control input.
When PHASE is low, “Sample
Unknown” occurs when the clock is
low and “Auto Balance” occurs when
the clock is high (see text).
V
V
(n) = reference ladder tap voltage at point n,
TAP
= voltage across V
- to V +,
REF
REF
REF
N
= tap number (1 through 256).
1
20
21
22
23
24
/
R
Reference Ladder Midpoint
Analog Signal Input
2
The other side of these capacitors are connected to single-
stage amplifiers whose outputs are shorted to their inputs by
switches. This balances the amplifiers at their intrinsic trip
V
IN
V
+
Reference Voltage Positive Input
3
REF
3
points, which is approximately (V + - V -)/2. The first set
AA AA
/
R
Reference Ladder / Point
4
4
of capacitors now charges to their associated tap voltages.
V
+
Analog Power Supply, +5V
AA
7
CA3318
At the same time a second set of commutating capacitors Pulse-Mode Operation
and amplifiers is also auto-balanced. The balancing of the
The CA3318 needs two of the same polarity clock edges to
second-stage amplifier at its intrinsic trip point removes any
tracking differences between the first and second amplifier
stages. The cascaded auto-balance (CAB) technique, used
here, increases comparator sensitivity and temperature
tracking.
complete a conversion cycle: If, for instance, a negative
going clock edge ends sample “N”, then data “N” will appear
after the next negative going edge. Because of this require-
ment, and because there is a maximum sample time of
500ns (due to capacitor droop), most pulse or intermittent
sample applications will require double clock pulsing.
In the “Sample Unknown” phase, all ladder tap switches and
comparator shorting switches are opened. At the same time
If an indefinite standby state is desired, standby should be in
auto-balance, and the operation would be as in Figure 3A.
V
is switched to the first set of commutating capacitors.
lN
Since the other end of the capacitors are now looking into an
effectively open circuit, any input voltage that differs from the
previous tap voltage will appear as a voltage shift at the
comparator amplifiers. All comparators that had tap voltages
If the standby state is known to last less than 500ns and
lowest average power is desired, then operation could be as
in Figure 3B.
greater than V will go to a “high” state at their outputs. All
lN
comparators that had tap voltages lower than V will go to a
lN
“low” state.
Increased Accuracy
In most cases the accuracy of the CA3318 should be
sufficient without any adjustments. In applications where
accuracy is of utmost importance, five adjustments can be
made to obtain better accuracy, i.e., offset trim; gain trim;
The status of all these comparator amplifiers is AC coupled
through the second-stage comparator and stored at the end
of this phase (φ2) by a latching amplifier stage. The latch
feeds a second latching stage, triggered at the end of φ1.
This delay allows comparators extra settling time. The status
1
1
3
and / , / and / point trim.
4
2
4
of the comparators is decoded by a 256 to 9-bit decoder Offset Trim
array, and the results are clocked into a storage register at
In general, offset correction can be done in the preamp
circuitry by introducing a DC shift to V or by the offset trim
the end of the next φ2.
lN
A 3-stage buffer is used at the output of the 9 storage regis- of the op amp. When this is not possible the V
- input can
REF
ters which are controlled by two chip-enable signals. CE1 be adjusted to produce an offset trim. The theoretical input
1
will independently disable B1 through B6 when it is in a high voltage to produce the first transition is / LSB. The equa-
2
state. CE2 will independently disable B1 through B8 and the tion is as follows:
OF buffers when it is in the low state.
1
1
V
(0 to 1 transition) = / LSB = / (V
/256)
lN
2
2
REF
To facilitate usage of this device, a phase control input is
provided which can effectively complement the clock as it
enters the chip.
= V
/512.
REF
If V for the first transition is less than the theoretical, then a
lN
single-turn 50Ω pot connected between V
- and ground
REF
will accomplish the adjustment. Set V to 1/2 LSB and trim
the pot until the 0-to-1 transition occurs.
lN
Continuous-Clock Operation
One complete conversion cycle can be traced through the
CA3318 via the following steps. (Refer to timing diagram.)
With the phase control in a “low” state, the rising edge of the
clock input will start a “sample” phase. During this entire
“high” state of the clock, the comparators will track the input
voltage and the first-stage latches will track the comparator
outputs. At the falling edge of the clock, all 256 comparator
outputs are captured by the 256 latches. This ends the “sam-
ple” phase and starts the “auto-balance” phase for the com-
parators. During this “low” state of the clock, the output of
the latches settles and is captured by a second row of
latches when the clock returns high. The second-stage latch
output propagates through the decode array, and a 9-bit
code appears at the D inputs of the output registers. On the
next falling edge of the clock, this 9-bit code is shifted into
If V for the first transition is greater than the theoretical,
lN
then the 50Ω pot should be connected between V
- and a
REF
negative voltage of about 2 LSBs. The trim procedure is as
stated previously.
Gain Trim
In general, the gain trim can also be done in the preamp
circuitry by introducing a gain adjustment for the op amp.
When this is not possible, then a gain adjustment circuit
should be made to adjust the reference voltage. To perform
this trim, V should be set to the 255 to overflow transition.
lN
1
That voltage is / LSB less than V
3
+ and is calculated as
REF
follows:
V
(255 to 256 transition) = V
= V
- V
/512
(511/512).
lN
REF
REF
REF
the output registers and appears with time delay t as valid
D
data at the output of the three-state drivers. This also marks
the end of the next “sample” phase, thereby repeating the
conversion process for this next cycle.
To perform the gain trim, first do the offset trim and then
apply the required V for the 255 to overflow transition. Now
lN
+ until that transition occurs on the outputs.
adjust V
REF
8
CA3318
The first step for connecting a 9-bit circuit is to totem-pole
+10V TO 30V
INPUT
+
the ladder networks, as illustrated in Figure 13. Since the
absolute resistance value of each ladder may vary, external
trim of the mid-reference voltage may be required.
3
18Ω
2
7
1
6
V
+
REF
(PIN 22)
8
CA3085E
(NOTE)
5K
The overflow output of the lower device now becomes the
ninth bit. When it goes high, all counts must come from the
upper device. When it goes low, all counts must come from
the lower device. This is done simply by connecting the lower
overtlow signal to the CE1 control of the lower A/D converter
and the CE2 control of the upper A/D converter. The three-
state outputs of the two devices (bits 1 through 8) are now
connected in parallel to complete the circuitry. The complete
circuit for a 9-bit A/D converter is shown in Figure 13.
4
+
IOT
CW
4.7µF,
TAN/IOV
10µF, TAN
(NOTE)
1.5K
NOTE: Bypass V
cap. Parts noted should have low temperature drift.
+ to analog GND near A/D with 0.1µF ceramic
REF
FIGURE 11. TYPICAL VOLTAGE REFERENCE SOURCE FOR
Grounding/Bypassing
DRIVING V
+ INPUT
REF
The analog and digital supply grounds of a system should be
kept separate and only connected at the A/D. This keeps
digital ground noise out of the analog data to be converted.
1
/ Point Trims
4
1
1
3
The / ,
/
and
/ points on the reference ladder are Reference drivers, input amps, reference taps, and the V
4
2
4
A
A
brought out for linearity adjusting or if the user wishes to supply should be bypassed at the A/D to the analog side of
1
create a nonlinear transfer function. The
/ points can be the ground. See Figure 15 for a block diagram of this con-
4
driven by the reference drivers shown (Figure 12) or by 2-K cept. All capacitors shown should be low impedance 0.1µF
1
pots connected between V
REF
+ and V -. The / (mid-) ceramics and should be mounted as close to the A/D as pos-
REF 2
point should be set first by applying an input of 257/512 x sible. If V + is derived from V , a small (10Ω resistor or
AA DD
(V
REF
) and adjusting for an output changing from 128 to inductor and additional filtering (4.7µF tantalum) may be
129. Similarly the / and / points can be set with inputs of used to keep digital noise out of the analog system.
1
3
4
4
129/512 and 385/512 x (V
) and adjusting for counts of
REF
Input Loading
192 to 193 and 64 to 65. (Note that the points are actually
1
1
3
/ , / and / of full scale +1 LSB.)
The CA3318 outputs a current pulse to the V terminal at
lN
4
2
4
the start of every sample period. This is due to capacitor
charging and switch feedthrough and varies with input volt-
age and sampling rate. The signal source must be capable
of recovering from the pulse before the end of the sample
period to guarantee a valid signal for the A/D to convert.
Suitable high speed amplifiers include the HA-5033,
HA-2542; and CA3450. Figure 16 is an example of an ampli-
fier which recovers fast enough for sampling at 15MHz.
+10V TO +30V
11
510Ω
V
+
4
REF
(PIN 22)
3
2
10Ω
1K
IOT
3
1
/
REF
+
4
CW
CW
-
(PIN 23)
5
6
10Ω
10Ω
1
1K
IOT
7
/
REF
+
2
(PIN 20)
-
Output Loading
10
9
1K
IOT
1
8
/
REF
+
4
The CMOS digital output stage, although capable of driving
large loads, will reflect these loads into the local ground. It is
CW
-
(PIN 10)
510Ω
recommended that
a
local QMOS buffer such as
CD74HC541 E be used to isolate capacitive loads.
NOTES:
Definitions
3
1. All Op Amps =
/ CA324E.
4
Dynamic Performance Definitions
2. Bypass all reference points to analog ground near A/D with 0.1µF
ceramic caps.
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the converter. A low distortion sine
wave is applied to the input, it is sampled, and the output is
stored in RAM. The data is then transformed into the frequency
domain with a 4096 point FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is -0.5dB down from fullscale for all these tests.
1
3
1
3. Adjust V
first, then / ,
3
/
and
/ points.
4
REF+
4
1
FIGURE 12. TYPICAL / POINT DRIVERS FOR ADJUSTING
4
LINEARITY (USE FOR MAXIMUM LINEARITY)
9-Bit Resolution
Signal-to-Noise (SNR)
To obtain 9-bit resolution, two CA3318s can be wired
together. Necessary ingredients include an open-ended lad-
der network, an overflow indicator, three-state outputs, and
chip-enable controls - all of which are available on the
CA3318.
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
9
CA3318
Signal-to-Noise + Distortion Ratio (SINAD)
Total Harmonic Distortion (THD)
SINAD is the measured RMS signal to RMS sum of all other THD is the ratio of the RMS sum of the first 5 harmonic
spectral components below the Nyquist frequency excluding DC. components to the RMS value of the measured input signal.
Effective Number of Bits (ENOB)
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
ENOB = (SINAD - 1.76 + V
)/6.02,
CORR
where:
V
= 0.5dB.
CORR
NC
V
V
V
+
OF
+6.4V REF
+5V
REF
+
-
V
DD
+5V
AA
AA
BIT 8
A
VIN1
0V TO 6.4V
V
V
BIT 1
CL
IN
IN
PH
CE2
CE1
MID-POINT
DRIVER
V
V
-
V
REF
REF
SS
6.4V REF
D
A
+5V
+
V
DD
CE2
V
V
CE1
OF
IN
IN
BIT 9
BIT 8
BIT 8
BIT 1
CL
BIT 1
CLOCK
V
+
-
+5V
AA
AA
V
V
PH
PHASE
-
V
SS
REF
A
A
D
FIGURE 13. USING TWO CA3318s FOR 9-BIT RESOLUTION
10
CA3318
4.7µF/10V TANTALUM
+
+5V (ANALOG SUPPLY)
A
V
3
+
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
OVF
AA
/
REF
4
+4V TO +6.5V
REFERENCE
V
+
REF
IN
V
1
DIGITAL
OUTPUT
/
REF
2
OPTIONAL CAP
(SEE TEXT)
0.01µF
PHASE
CLK
CLOCK
SOURCE
V
V
V
-
AA
INPUT SIGNAL
IN
1
/
REF
-
4
REF
AMPLIFIER/BUFFER
(SEE TEXT)
A
V
V
CE1
CE2
SS
A
D
D
DD
+
CA3318
4.7µF
TANTALUM/10V
+5V (DIGITAL SUPPLY)
FIGURE 14. TYPICAL CIRCUIT CONFIGURATION FOR THE CA3318 WITH NO LINEARITY ADJUST
V
V
IN
IN
AMP
TO
DIGITAL
SYSTEM
SIGNAL
SOURCE
OUTPUT
DRIVERS
REF
V
+
REF
SIGNAL
GROUND
REFERENCE
TAPS
V
+
V
DD
AA
V
-
REF
V
-
V
SS
AA
SYSTEM
DIGITAL
GROUND
-
+
V
V
DD
SUPPLY
ANALOG
SUPPLIES
AA
SUPPLY
FIGURE 15. TYPICAL SYSTEM GROUNDING/BYPASSING
+8V
75Ω
10Ω
1V
P-P
14
VIDEO
INPUT
7
0.001µF
0.001µF
75Ω
11
8
10Ω
16
21
6
A/D FLASH
INPUT
5pF
CA3450
9
3
13
12
5
390
4
10Ω
750
110
0V TO -10V
OFFSET SOURCE
< 10Ω
NOTE: Ground-planing and tight layout
are extremely important.
0.1
-4V
R
S
FIGURE 16. TYPICAL HIGH BANDWIDTH AMPLIFIER FOR DRIVING THE CA3318
11
CA3318
TABLE 1. OUTPUT CODE TABLE
(NOTE 1)
INPUT VOLTAGE
BINARY OUTPUT CODE
CODE
DESCRIPTION
V
V
MSB
B8
LSB
B1
DECIMAL
COUNT
REF
REF
6.40V (V) 5.12V (V)
OF
0
B7
0
B6
0
B5
0
B4
0
B3
0
B2
0
Zero
1 LSB
2 LSB
0.00
0.025
0.05
0.00
0.02
0.04
0
0
0
0
1
0
0
1
2
0
0
0
0
0
0
0
0
0
0
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
/
Full Scale
1.60
1.28
0
0
1
0
0
0
0
0
0
64
4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
/
Full Scale - 1 LSB
1
3.175
3.20
2.54
2.56
2.58
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
127
128
129
2
/
Full Scale
2
1
/
Full Scale + 1 LSB
3.225
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3
/
Full Scale
4.80
3.84
0
1
1
0
0
0
0
0
0
192
4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full Scale - 1 LSB
Full Scale
6.35
6.375
6.40
5.08
5.10
5.12
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
254
255
511
Over Flow
NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage.
Reducing Power
Clock Input
Most power is consumed while in the auto-balance state. The Clock and Phase inputs feed buffers referenced to
When operating at lower than 15MHz clock speed, power
V
+ and V -. Phase should be tied to one of these two
AA
AA
can be reduced by stretching the sample (φ2) time. The con- potentials, while the clock (if DC coupled) should be driven
straints are a minimum balance time (φ1) of 33ns, and a at least from 0.2 to 0.7 x (V + - V -). The clock may also
AA
AA
swing. This allows TTL
maximum sample time of 500ns. Longer sample times cause be AC coupled with at least a 1V
P-P
droop in the auto-balance capacitors. Power can also be drive levels or 5V QMOS levels when V + is greater than
AA
reduced in the reference string by switching the reference on 5V.
only during auto-balance.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
12
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