CD40208BMS [INTERSIL]
CMOS 4 x 4 Multiport Register; CMOS的4×4多端口寄存器
| 型号： | CD40208BMS |
| 厂家： | 
Intersil |
| 描述： | CMOS 4 x 4 Multiport Register |
| 文件： | 总11页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD40208BMS
CMOS 4 x 4 Multiport Register
December 1992
Features
Description
• High Voltage Types (20V Rating)
• One Input and Two Output Buses
• Unlimited Expansion in Bit and Word Directions
• Data Lines have Latched Inputs
• 3-State Outputs
The CD40208BMS is a 4 x 4 multiport register containing
four 4-bit registers, write address decoder, two separate
read address decoders, and two 3-state output buses.
When the ENABLE input is low, the corresponding output
bus is switched, independently of the clock, to a high imped-
ance state. The high impedance third state provides the out-
puts with the capability of being connected to the bus lines in
a bus organized system without the need for interface or
pull-up components.
• Separate Control of Each Bus, Allowing Simultaneous
Independent Reading of any of Four Registers on Bus
A and Bus B and Independent Writing Into any of the
Four Registers
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
When the WRITE ENABLE input is high, all data input lines
are latched on the positive transition of the CLOCK and the
data is entered into the word selected by the write address
lines. When WRITE ENABLE is low, the CLOCK is inhibited
and no new data is entered. In either case, the contents of
any word may be accessed via the read address lines inde-
pendent of the state of the CLOCK input.
• Maximum Input Current of 1µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
The CD40208BMS types are supplied in hermetic 24-lead
dual-in-line ceramic packages (D and F suffixes), 24-lead
dual-in-line plastic packages (E suffix), 24-lead ceramic flat
packages (K suffix), and in chip form (H suffix).
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Devices”
The CD40208BMS is supplied in these 24-lead outline pack-
ages:
Applications
Braze Seal DIP
Ceramic Flatpack
HNZ
H4P
• Scratch Pad Memories
• Arithmetic Units
• Data Storage
Functional Diagram
Pinout
CD40208BMS
TOP VIEW
WRITE
ENABLE
ENABLE A
15
3
4
Q3B
Q2B
1
2
3
4
5
6
7
8
9
24
VDD
20
D0
Q0
23 Q1B
19
5
6
7
D1
Q1
Q2
Q3
DATA
INPUTS
WORD A
OUTPUT
ENABLE A
Q0A
22 Q0B
18
D2
D3
21 ENABLE B
20 D0
17
Q1A
8
9
WRITE 0
WRITE 1
Q2A
19 D1
Q3A
18 D2
22
23
2
Q0
Q1
Q2
Q3
14
13
READ 1A
READ 0A
WRITE 0
WRITE 1
17 D3
WORD B
OUTPUT
16 CLOCK
15 WRITE ENABLE
14 READ 1A
13 READ 0A
1
11
10
READ 0B 10
READ 1B 11
VSS 12
READ 1B
READ 0B
16
CLOCK
21
VDD = 24
VSS = 12
ENABLE B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3396
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1431
Specifications CD40208BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance
Ceramic DIP and Frit Package . . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For T = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
A
o
o
For T = +100 C to +125 C (Package Type D, F, K). . . . . .Derate
A
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
For T = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
A
o
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
VIN = VDD or GND
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VIH
IOZL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
o
Tri-State Output
Leakage
VIN = VDD or GND
VOUT = 0V
VDD = 20V
1
2
3
1
2
3
+25 C
-0.4
-
-
µA
µA
µA
µA
µA
µA
o
+125 C
-12
o
VDD = 18V
VDD = 20V
-55 C
-0.4
-
o
Tri-State Output
Leakage
IOZH
VIN = VDD or GND
VOUT = VDD
+25 C
-
-
-
0.4
12
0.4
o
+125 C
o
VDD = 18V
-55 C
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/NoGo test with limits applied to inputs.
7-1432
Specifications CD40208BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
MAX
720
972
600
810
200
270
260
351
200
270
-
UNITS
ns
o
Propagation Delay
Clock or Write Enable to Q TPLH1 (Notes 1, 2)
TPHL1 VDD = 5V, VIN = VDD or GND
9
10, 11
9
+25 C
-
o
o
+125 C, -55 C
-
ns
o
Propagation Delay
Read or Write Enable to Q TPLH2 (Notes 1, 2)
TPHL2 VDD = 5V, VIN = VDD or GND
+25 C
-
ns
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Propagation Delay
3-State Disable Delay Time
TPZH, HZ VDD = 5V, VIN = VDD or GND
+25 C
-
ns
(Notes 2, 3)
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Propagation Delay
3-State Disable Delay Time
TPZL, LZ VDD = 5V, VIN = VDD or GND
(Notes 2, 3)
+25 C
-
ns
o
o
10, 11
9
+125 C, -55 C
-
-
ns
o
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Maximum Clock Input
Frequency
FCL
VDD = 5V, VIN = VDD or GND
+25 C
1.5
1.11
MHz
MHz
o
o
10, 11
+125 C, -55 C
-
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL4
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 4.5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
o
-55 C
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
+125 C
0.36
0.64
0.9
1.6
2.4
4.2
-
-
o
-55 C
-
o
+125 C
-
o
-55 C
-
o
+125 C
-
o
-55 C
-
o
IOH5A VDD = 5V, VOUT = 4.6V
+125 C
-0.36
-0.64
o
-55 C
-
7-1433
Specifications CD40208BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MAX
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
UNITS
mA
mA
mA
mA
mA
mA
V
o
Output Current (Source)
IOH5B VDD = 5V, VOUT = 2.5V
1, 2
+125 C
-
-
-
-
-
-
-
o
-55 C
o
Output Current (Source)
Output Current (Source)
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
1, 2
1, 2
+125 C
o
-55 C
o
+125 C
o
-55 C
o
o
Input Voltage Low
Input Voltage High
Propagation Delay
VIL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
1, 2
+25 C, +125 C,
o
-55 C
o
o
VIH
+25 C, +125 C,
+7
-
V
o
-55 C
o
TPHL1 VDD = 10V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
280
200
240
170
120
100
100
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock or Write Enable to Q TPLH1
o
VDD = 15V
TPHL2 VDD = 10V
+25 C
o
Propagation Delay
Read or Write Address to Q TPLH2
+25 C
o
VDD = 15V
+25 C
o
Propagation Delay
Output Disable to Output
TPZL, LZ VDD = 10V
VDD = 15V
+25 C
o
+25 C
o
Propagation Delay
Output Disable to Output
TPZH, HZ VDD = 10V
VDD = 15V
+25 C
o
+25 C
o
Minimum Write Enable to TS (WE) VDD = 5V
Clock Setup Time
+25 C
250
100
70
o
VDD = 10V
+25 C
o
VDD = 15V
+25 C
o
Minimum Data to Clock
Setup Time
TS (D)
VDD = 5V
VDD = 10V
VDD = 15V
+25 C
0
o
+25 C
0
o
+25 C
0
o
Minimum Write Address
to Clock Setup Time
TS (WA) VDD = 5V
VDD = 10V
+25 C
250
100
70
o
+25 C
o
VDD = 15V
+25 C
o
Minimum Write Enable to TH (WE) VDD = 5V
Clock Hold Time
+25 C
270
130
80
o
VDD = 10V
+25 C
o
VDD = 15V
+25 C
o
Minimum Data to Clock
Hold Time
TH (D)
VDD = 5V
VDD = 10V
VDD = 15V
+25 C
220
100
80
o
+25 C
o
+25 C
o
Minimum Write Address
to Clock Hold Time
TH (WA) VDD = 5V
VDD = 10V
+25 C
330
140
90
o
+25 C
o
VDD = 15V
+25 C
o
Minimum Clock Pulse
Width, Clock or Write En-
able
TW (CL) VDD = 5V
VDD = 10V
+25 C
350
130
90
o
+25 C
o
VDD = 15V
+25 C
o
Minimum Clock Pulse
Width, Write Address
TW (WA) VDD = 5V
VDD = 10V
+25 C
300
150
90
o
+25 C
o
VDD = 15V
+25 C
7-1434
Specifications CD40208BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
VDD = 10V
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
MIN
MAX
-
UNITS
MHz
MHz
µs
o
Maximum Clock Input
Frequency
FCL
+25 C
3.5
o
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
Any Input
+25 C
4.5
-
o
Clock Rise and Fall Time
tRCL
tFCL
+25 C
-
-
-
-
-
-
15
5
o
+25 C
µs
o
+25 C
5
µs
o
Transition Time
TTHL
TTLH
+25 C
100
80
7.5
ns
o
+25 C
ns
o
Input Capacitance
NOTES:
CIN
+25 C
pF
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K., Input TR, TF < 20ns
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
∆VNTH VDD = 10V, ISS= -10µA
1, 4
+25 C
V
o
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VPTH VSS = 0V, IDD = 10µA
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 3V, VIN = VDD or GND
VDD = 5V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
NOTES:
1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input tR, tF < 20ns.
o
3. See Table 2 for +25 C limit.
4. Read and Record.
o
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
7-1435
Specifications CD40208BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
1, 7, 9
READ AND RECORD
IDD, IOL5, IOH5A, RONDEL10
IDD, IOL5, IOH5A, RONDEL10
IDD, IOL5, IOH5A, RONDEL10
1, 7, 9
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A, RONDEL10
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
(Note 1)
1, 2, 4-7, 22, 23
3, 8-21
24
Static Burn-In 2
(Note 1)
1, 2, 4-7, 22, 23
1, 2, 4-7, 22, 23
12
12
12
3, 8-11, 13-21, 24
3, 15, 16, 21, 24
3, 8-11, 13-21, 24
Dynamic Burn-
In (Note 1)
1, 2, 4-7, 22, 23
8, 10, 14, 19, 20
9, 11, 13, 17, 18
Irradiation
(Note 2)
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Block Diagram
W0 W1 R0A R1A R0B R1B
CL
ENABLE A
DEC.
DEC.
DEC.
WE
Q0A
Q1A
Q2A
Q3A
WORD A
OUTPUT
D0
D1
D2
D3
DATA
INPUTS
4 X 4
MEMORY
Q0B
Q1B
Q2B
Q3B
WORD B
OUTPUT
ENABLE B
FIGURE 1.
7-1436
CD40208BMS
Logic Diagram
13 R0A
14 R1A
R0B 10
11 R1B
*
*
*
*
3-STATE
A ENABLE
3
C
C
*
16
CLOCK
*
15
4
Q0A
Q1A
WRITE
ENABLE
*
5
8
A
B
A
B
A
B
A
B
W0
QA
QB
QA
QB
QA
QB
QA
QB
*
D
D
D
D
W
W
W
W
9
6
7
Q2A
Q3A
W1
*
C
P
N
20
A
B
A
B
A
B
A
B
D0
*
QA
QB
W
QA
QB
W
QA
QB
W
QA
QB
W
C
D
D
D
D
C
C
P
N
22
23
Q0B
Q1B
C
P
N
19
D1
A
B
A
B
A
B
A
B
*
C
QA
QB
W
QA
QB
W
QA
QB
W
QA
QB
W
C
C
D
D
D
D
P
N
2
1
Q2B
Q3B
C
P
N
18
A
B
A
B
A
B
A
B
D2
QA
QB
W
QA
QB
W
QA
QB
W
QA
QB
W
*
C
D
D
D
D
C
C
P
N
C
P
N
B ENABLE
3-STATE
17
*
21
D3
*
C
C
P
N
A
P
N
P
N
QA
D
C
VDD
VDD = 24
VSS = 12
VDD
P
N
INPUT
OUTPUT
B
W
P
N
QB
VSS
VSS
*ALL INPUTS PROTECTED BY
COS/MOS PROTECTION
NETWORK
DETAIL OF
MEMORY CELL
DETAIL OF
3-STATE OUTPUTS
FIGURE 2.
7-1437
CD40208BMS
TRUTH TABLE
WRITE
CLOCK ENABLE
WRITE
1
WRITE
0
READ
1A
READ
READ
1B
READ ENABLE ENABLE
0A
S2
S2
X
0B
S2
S2
X
A
1
1
0
1
B
1
1
0
1
Dn
QnA
QnB
1
1
S1
S1
X
S2
S2
X
S1
S1
X
S1
S1
X
1
0
X
1
0
Z
1
0
Z
X
X
X
1
0
0
0
1
1
0
Dn to
Word 0
Word 1
Out
Word 2
Out
0
0
0
0
1
1
0
1
1
Word 0
Not
Word 1
Out
Word 2
Out
Altered
X
X
X
X
X
X
1
0
0
1
1
1
1
1
X
Word 2
Out
Word 1
Out
X
X
X
X
X
NC
NC
1 = High Level; 0 = Low Level; X = Don’t Care; Z = High Impedance
NOTE: S1 and S2 refer to input states of either 1 or 0.
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
7.5
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHAR-
ACTERISTICS
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHAR-
ACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
7-1438
CD40208BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
525
450
375
300
225
150
75
SUPPLY VOLTAGE (VDD) = 5V
200
150
100
50
SUPPLY VOLTAGE (VDD) = 5V
10V
5V
10V
15V
0
0
0
10
20
30
40
50
60
70
80
90 100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNC-
TION OF LOAD CAPACITANCE (CL OR WE TO Q)
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
106
SUPPLY VOLTAGE (VDD) = 15V
105
104
103
102
10V
5V
10V
CL = 50pF
CL = 15pF
AMBIENT TEMPERATURE (TA) = +25oC
102
103
104
1
10
INPUT FREQUENCY (fI) (kHz)
FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY
trCL
CL
tfCL
tW(CL)
tH(D)
tS(D)
Dn
tH(WE)
tS(WE)
WE
WA
tH(WA)
tS(WA)
tW(WA)
RA
Qn
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tTLH
tTHL
FIGURE 10. TIMING DIAGRAM
7-1439
CD40208BMS
0.1µF
500µF
VDD
ID
CL
(fI)
P.G. 1
P.G. 2
1
24
23
22
21
20
19
18
17
16
15
14
13
CL
CL
CL
2
3
CL
CL
CL
CL
4
5
6
P.G. 3
PULSE GEN. 2
7
Qn A, B
8
9
PULSE GEN. 1
10
11
12
REPETITIVE WAVEFORMS
PULSE GEN. 3
FIGURE 11. POWER-DISSIPATION TEST CIRCUIT AND WAVEFORMS
VDD
CL
P.G. 1
1
2
24
PULSE GEN. 2
23
ENABLE
VDD
P.G. 2
3
22
Q
ENABLE
INPUT
21
4
50%
50%
5
20
19
VSS
1kΩ
6
D
tPLZ
Q
tPZL
90%
7
18
17
16
15
14
13
TO ANY
OUTPUT
VDD
8
10%
90%
50pF
VOL
VOH
9
PULSE GEN. 1
OUTPUTS
10
11
12
10%
tPZH
VSS
TEST VOLTAGE
tPHZ
CHAR
tPHZ
tPZH
tPLZ
AT D
VDD
VDD
VSS
VSS
AT Q
VSS
VSS
VDD
VDD
tPZL
FIGURE 12. OUTPUT-ENABLE-DELAY-TIMES TEST CIRCUIT AND WAVEFORMS
7-1440
CD40208BMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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1441
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