CD4515BMS [INTERSIL]
CMOS 4-Bit Latch/4-to-16 Line Decoders; CMOS 4位锁存器/ 4至16线路解码器
| 型号： | CD4515BMS |
| 厂家： | 
Intersil |
| 描述： | CMOS 4-Bit Latch/4-to-16 Line Decoders |
| 文件： | 总10页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4514BMS
CD4515BMS
CMOS 4-Bit
Latch/4-to-16 Line Decoders
December 1992
Features
Pinout
CD4514BMS, CD4515BMS
• High-Voltage Types (20-Volt Rating)
• CD4514BMS Output “High” on Select
• CD4515BMS Output “Low” on Select
• Strobed Input Latch
TOP VIEW
1
2
3
4
5
6
7
8
9
24
VDD
STROBE
DATA 1
DATA 2
S7
23 INHIBIT
22 DATA 4
21 DATA 3
20 S10
• Inhibit Control
• 100% Tested for Quiescent Current at 20V
S6
19 S11
S5
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25oC
18 S8
S4
17 S9
S3
S2
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
16 S14
S1 10
S0 11
15 S15
- 2V at VDD = 10V
14 S12
- 2.5V at VDD = 15V
VSS 12
13 S13
• 5V, 10V, and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
Functional Diagram
VDD = 24
VSS = 12
Applications
11 S0
S1
10 S2
• Digital Multiplexing
• Address Decoding
9
8
7
6
5
4
S3
S4
S5
S6
S7
• Hexadecimal/BCD Decoding
• Program-counter Decoding
• Control Decoder
DATA 1
DATA 2
2
3
A
B
C
D
4 TO 16
DECODER
LATCH
DATA 3 21
DATA 4 22
18 S8
17 S9
20 S10
19 S11
14 S12
13 S13
16 S14
15 S15
Description
STROBE
1
CD4514BMS and CD4515BMS consist of a 4-bit strobed
latch and a 4-to-16-line decoder. The latches hold the last
input data presented prior to the strobe transition from 1 to 0.
Inhibit control allows all outputs to be placed at
0(CD4514BMS) or 1(CD4515BMS) regardless of the state of
the data or strobe inputs.
INHIBIT 23
The decode truth table indicates all combinations of data
inputs and appropriate selected outputs.
These devices are similar to industry types MC14514 and
MC14515.
The CD4514BMS and CD4515BMS are supplied in these 24
lead outline packages:
Braze Seal DIP
Frit Seal DIP
H4V
H1Z
H4P
Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3195
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1188
Specifications CD4514BMS, CD4515BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For T = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
A
o
o
For T = +100 C to +125 C (Package Type D, F, K). . . . . .Derate
A
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
For T = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
A
o
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VIH
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1189
Specifications CD4514BMS, CD4515BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS (NOTE 1, 2)
MAX
970
1310
500
675
200
270
UNITS
ns
o
Propagation Delay
Strobe or Data
TPHL1 VDD = 5V, VIN = VDD or GND
TPLH1
9
+25 C
-
-
-
-
-
-
o
o
10, 11
9
+125 C, -55 C
ns
o
Propagation Delay
Inhibit
TPHL2 VDD = 5V, VIN = VDD or GND
TPLH2
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Transition Time
NOTES:
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
o
-55 C
0.64
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
-
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
o
-55 C
o
+125 C
o
-55 C
o
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
+125 C
o
-55 C
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
1, 2
+25 C, +125 C,
o
-55 C
o
o
VIH
+25 C, +125 C,
+7
-
V
o
-55 C
7-1190
Specifications CD4514BMS, CD4515BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
MAX
370
270
220
170
100
80
UNITS
ns
o
Propagation Delay
Strobe or Datat
TPHL1 VDD = 10V
TPLH1
+25 C
-
-
-
-
-
-
-
-
-
-
-
-
-
o
VDD = 15V
+25 C
ns
o
Propagation Delay
Inhibit
TPHL2 VDD = 10V
TPLH2
+25 C
ns
o
VDD = 15V
+25 C
ns
o
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
+25 C
ns
o
+25 C
ns
o
Minimum Data Setup
Time
TS
TW
CIN
+25 C
150
70
ns
o
+25 C
ns
o
+25 C
40
ns
o
Minimum Strobe Pulse
Width
+25 C
250
100
75
ns
o
+25 C
ns
o
+25 C
ns
o
Input Capacitance
NOTES:
+25 C
7.5
pF
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
o
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
7-1191
Specifications CD4514BMS, CD4515BMS
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
25kHz
23
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
Static Burn-In 1
(Note 1)
4-11, 13-20
1-3, 12, 21-23
24
Static Burn-In 2
(Note 1)
4-11, 13-20
-
12
1-3, 21-24
21, 22, 24
Dynamic Burn-
In (Note 1)
2, 3, 12
4-11, 13-20
1
Irradiation
(Note 2)
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-1192
CD4514BMS, CD4515BMS
Logic Diagram
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
VDD
S0
S1
11
9
10
8
S2
S3
VSS
7
S4
S5
S6
S7
*
A
DATA 1
DATA 2
2
3
S
R
Q
Q
6
5
4
*
B
S
R
Q
Q
18 S8
*
DATA 3 21
C
D
S
R
Q
Q
S9
17
S10
S11
S12
20
19
14
*
DATA 4 22
S
R
Q
Q
*
STROBE
1
13 S13
16
*
A B C D
A B C D
INHIBIT 23
S14
15 S15
THESE INVENTERS USED ONLY ON CD4515BMS
* All inputs protected by CMOS protection network.
FIGURE 1. LOGIC DIAGRAM
TRUTH TABLE
DECODER INPUTS
SELECTED OUTPUT
CD4514BMS = LOGIC 1 (HIGH)
CD4515BMS = LOGIC 0 (LOW)
INHIBIT
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
All Outputs = 0, CD4514BMS
All Outputs = 1, CD4515BMS
1 = HIGH LEVEL
0 = LOW LEVEL
X = DON’T CARE
7-1193
CD4514BMS, CD4515BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
12.5
10.0
7.5
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
20
15
10V
10V
10
5
5.0
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
550
SUPPLY VOLTAGE (VDD) = 5V
500
AMBIENT TEMPERATURE (TA) = +25oC
350
300
450
400
SUPPLY VOLTAGE (VDD) = 5V
250
350
300
250
200
200
150
10V
100
10V
150
15V
50
15V
100
50
0
20
40
60
80
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL INHIBIT PROPAGATION DELAY TIME vs
LOAD CAPACITANCE
FIGURE 6. TYPICAL STROBE OR DATA PROPAGATION
DELAY TIME vs LOAD CAPACITANCE
7-1194
CD4514BMS, CD4515BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50pF
500
400
300
200
100
200
150
100
50
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
0
0
0
20
40
60
80
100
0
5
10
15
20
25
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL LOW-TO-HIGH TRANSITION TIME vs
LOAD CAPACITANCE
FIGURE 9. TYPICAL STROBE OR DATA PROPAGATION
DELAY TIME vs SUPPLY VOLTAGE
106
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE
(VDD) = 15V
105
104
103
10V
10V
5V
102
10
CL = 50pF
CL = 15pF
2
4 6 8
2
4
6 8
101
2
4
6 8
102
2
4
6 8
103
1
104
FREQUENCY (f) (kHz)
10. TYPICAL POWER DISSIPATION vs FREQUENCY
Waveforms
DATA
50%
tS
tr, tf = 20ns
50%
STROBE
tW
FIGURE 11. WAVEFORMS FOR SETUP TIME AND STROBE
PULSE WIDTH
7-1195
CD4514BMS, CD4515BMS
Chip Dimensions and Pad Layouts
112
0
10
20 30 40
50 60 70 80 90 100 110
74
70
60
50
40
30
71-79
(1.804-2.006)
20
10
0
4-10
(0.102-0.254)
109-117
(2.769-2.971)
Dimensions in parentheses are in milimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch.)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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