CD4520 [INTERSIL]
CMOS Dual Up Counters; CMOS双专柜
| 型号： | CD4520 |
| 厂家： | 
Intersil |
| 描述： | CMOS Dual Up Counters |
| 文件： | 总10页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4518BMS,
CD4520BMS
CMOS Dual Up Counters
December 1992
Features
Pinout
CD4518BMS, CD4520BMS
• High Voltage Types (20V Rating)
• CD4518BMS Dual BCD Up Counter
• CD4520BMS Dual Binary Up Counter
TOP VIEW
• Medium Speed Operation
CLOCK A
ENABLE A
Q1A
1
2
3
4
5
6
7
8
16 VDD
- 6MHz Typical Clock Frequency at 10V
15 RESET B
14 Q4B
• Positive or Negative Edge Triggering
• Synchronous Internal Carry Propagation
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
Q2A
13 Q3B
Q3A
12 Q2B
Q4A
11 Q1B
10 ENABLE B
• Maximum Input Current of 1µA at 18V Over Full Pack-
RESET A
VSS
age Temperature Range; 100nA at 18V and +25oC
9
CLOCK B
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Functional Diagram
Applications
3
4
5
6
Q1A
Q2A
Q3A
Q4A
• Multistage Synchronous Counting
• Multistage Ripple Counting
• Frequency Dividers
CLOCK A
1
÷10/÷16
ENABLE A
2
C
Description
R
RESET A
7
CD4518BMS Dual BCD Up Counter and CD4520BMS Dual
Binary Up Counter each consist of two identical, internally
synchronous 4-stage counters. The counter stages are
D-type flip-flops having interchangeable CLOCK and
ENABLE lines for incrementing on either the positive-going
or negative-going transition. For single unit operation the
ENABLE input is maintained high and the counter advances
on each positive-going transition of the CLOCK. The
counters are cleared by high levels on their RESET lines.
11
12
13
14
Q1B
Q2B
Q3B
Q4B
CLOCK B
9
÷10/÷16
ENABLE B
10
C
R
The counter can be cascaded in the ripple mode by connect-
ing Q4 to the enable input of the subsequent counter while
the CLOCK input of the latter is held low.
RESET B
15
The CD4518BMS and CD4520BMS are supplied in these
16-lead outline packages:
VSS = 8
VDD = 16
Braze Seal DIP
Frit Seal DIP
H4S
H1F
Ceramic Flatpack
*CD4518B Only
*H6P †H6W
†CD4520B Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3342
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1206
Specifications CD4518BMS, CD4520BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For T = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
A
o
o
For T = +100 C to +125 C (Package Type D, F, K). . . . . .Derate
A
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
For T = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
A
o
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
VIN = VDD or GND
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VIH
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1207
Specifications CD4518BMS, CD4520BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS (NOTE 1, 2)
MAX
560
756
650
878
200
270
-
UNITS
ns
o
Propagation Delay
Clock to Output
TPHL1 VDD = 5V, VIN = VDD or GND
TPLH1
9
10, 11
9
+25 C
-
o
o
+125 C, -55 C
-
ns
o
Propagation Delay
Reset to Ouput
TPHL2 VDD = 5V, VIN = VDD or GND
+25 C
-
ns
o
o
10, 11
9
+125 C, -55 C
-
-
ns
o
Transition Time
(Note 2)
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
+25 C
ns
o
o
10, 11
9
+125 C, -55 C
-
ns
o
Maximum Clock Input
Frequency
FCL
+25 C
1.5
1.11
MHz
MHz
o
o
10, 11
+125 C, -55 C
-
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
o
-55 C
0.64
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
-
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
o
-55 C
o
+125 C
o
-55 C
o
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
+125 C
o
-55 C
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
1, 2
+25 C, +125 C,
o
-55 C
o
o
VIH
+25 C, +125 C,
+7
-
V
o
-55 C
7-1208
Specifications CD4518BMS, CD4520BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
MAX
230
160
225
170
100
80
UNITS
ns
o
Propagation Delay
Clock to Output
TPHL1 VDD = 10V
TPLH1
+25 C
-
-
-
-
-
-
3
4
-
-
-
-
-
-
-
-
-
-
-
-
-
o
VDD = 15V
+25 C
ns
o
Propagation Delay
Reset to Output
TPHL2 VDD = 10V
VDD = 15V
+25 C
ns
o
+25 C
ns
o
Transition Time
TTHL
TTLH
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
+25 C
ns
o
+25 C
ns
o
Maximum Clock Input
Frequency
FCL
+25 C
-
MHz
MHz
µs
o
+25 C
-
o
Maximum Clock Rise and
Fall Time
TRCL
TFCL
+25 C
15
o
+25 C
5
µs
o
+25 C
5
µs
o
Minimum Enable Pulse
Width
TW
TW
TW
CIN
+25 C
400
200
140
250
110
80
ns
o
+25 C
ns
o
+25 C
ns
o
Minimum Reset Pulse
Width
+25 C
ns
o
+25 C
ns
o
+25 C
ns
o
Minimum Clock Pulse
Width
+25 C
200
100
70
ns
o
+25 C
ns
o
+25 C
ns
o
Input Capacitance
NOTES:
+25 C
7.5
pF
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
7-1209
Specifications CD4518BMS, CD4520BMS
o
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
Note 1
3-6, 11-14
1, 2, 7-10, 15
16
Static Burn-In 2
Note 1
3-6, 11-14
-
8
7, 8, 15
8
1, 2, 7, 9, 10,
15, 16
Dynamic Burn-
In Note 1
2, 10, 16
3-6, 11-14
1, 9
Irradiation
Note 2
3-6, 11-14
1, 2, 7, 9, 10,
15, 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
7-1210
CD4518BMS, CD4520BMS
Logic Diagrams
VDD
Q1
3/11
Q2
4/12
Q3
5/13
Q4
6/14
VSS
D
C
Q
Q
R
D
C
Q
Q
R
D
C
Q
Q
R
D
C
Q
Q
R
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
*
*
7/15
RESET
*
2/10
ENABLE
*
1/9
CLOCK
FIGURE 1. DECADE COUNTER (CD4518BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS
VDD
Q1
3/11
Q2
4/12
Q3
5/13
Q4
6/14
VSS
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
*
D
C
Q
Q
R
D
C
Q
Q
R
D
C
Q
Q
R
D
C
Q
Q
R
*
7/15
RESET
*
2/10
ENABLE
*
1/9
CLOCK
FIGURE 2. BINARY COUNTER (CD4520BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS
TRUTH TABLE
CLOCK
ENABLE
RESET
ACTION
Increment Counter
Increment Counter
No Change
1
0
0
0
0
0
0
1
0
X
0
X
No Change
No Change
1
No Change
X
X
Q1 thru Q4 = 0
X = Don’t Care 1 ≡ High State 0 ≡ Low State
7-1211
CD4518BMS, CD4520BMS
Typical Performance Curves
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
12.5
10.0
7.5
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
350
350
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
300
300
SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 5V
250
250
200
200
150
150
10V
10V
100
100
15V
15V
50
50
0
0
10
20
30
40
50
60
70
80 90 100 110
10
20
30
40
50
60
70
80
90
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL PROPAGATION DELAY vs LOAD CAPAC-
ITANCE, CLOCK OR ENABLE TO OUTPUT
FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE, RESET TO OUTPUT
7-1212
CD4518BMS, CD4520BMS
Typical Performance Curves
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50PF
15
10
5
200
SUPPLY VOLTAGE (VDD) = 5V
150
100
50
0
10V
15V
0
5
10
15
20
0
20
40
60
80
100
SUPPLY VOLTAGE (VDD) (V)
LOAD CAPACITANCE (CL) (pF)
FIGURE 9. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE
FIGURE 10. TYPICAL MAXIMUM CLOCK FREQUENCY vs
SUPPLY VOLTAGE
104
8
6
4
2
SUPPLY VOLTAGE (VDD) = 15V
103
102
8
6
4
2
8
6
4
10V
10V
5V
2
8
6
4
CL = 50pF
CL = 15pF
10
1
2
AMBIENT TEMPERATURE (TA) = +25oC
2
4 6 8
2
4 6 8
2
4 6 8
2
4 6 8
2
4 6 8
0.1
1
10
FREQUENCY (f) (kHz)
102
103
104
FIGURE 11. TYPICAL POWER DISSIPATION CHARACTERISTICS
Timing Diagrams
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17 18
CLOCK
ENABLE
RESET
0
1
2
3
4
5
6
0
7
8
9
0
Q1
Q2
CD4518BMS
Q3
Q4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
1
2
3
4
Q1
Q2
Q3
Q4
CD4520BMS
FIGURE 12. TIMING DIAGRAMS FOR CD4518BMS AND CD4520BMS
7-1213
CD4518BMS, CD4520BMS
CLOCK
INPUT
VDD
2
1
7
9
10
15
1
2
7
9
10
15
CLOCK ENABLE RESET
CLOCK ENABLE RESET
CLOCK ENABLE RESET
CLOCK ENABLE RESET
A
A
A
B
B
B
A
A
A
B
B
B
Q1A Q2A Q3A Q4A
Q1B Q2B Q3B Q4B
11 12 13 14
Q1A Q2A Q3A Q4A
Q1B Q2B Q3B Q4B
11 12 13 14
3
4
5
6
3
4
5
6
CD4518BMS/20BMS
CD4518BMS/20BMS
FIGURE 13. RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE EDGE TRIGGERING
CD4071
CD4071
CLOCK*
INPUT
1
2
3
9
10
15
1
2
3
9
10
15
CLOCK ENABLE RESET
CLOCK ENABLE RESET
CLOCK ENABLE RESET
CLOCK ENABLE RESET
A
A
A
B
B
B
A
A
A
B
B
B
Q1A Q2A Q3A Q4A
Q1B Q2B Q3B Q4B
Q1A Q2A Q3A Q4A
Q1B Q2B Q3B Q4B
11 12 13 14
3
4
5
6
11
12
13
14
3
4
5
6
CD4520BMS
CD4012A
CD4520BMS
CD4012A
CD4012A
CD4520BMS
* For synchronous cascading, the clock transition time should be made less than or equal to the sum of the fixed propagation delay at 15pF
and the transition time of the output driver stage for the estimated capacitive load.
FIGURE 14. SYNCHRONOUS CASCADING OF FOUR BINARY COUNTERS WITH NEGATIVE EDGE TRIGGERING
7-1214
CD4518BMS, CD4520BMS
Chip Dimensions and Pad Layouts
CD4518BMS
CD4520BMS
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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1215
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