CD54ACT1933A [INTERSIL]

Presettable Synchronous 4-Bit Binary Up/Down Counter with Reset; 可预置同步4位二进制加/减计数器复位
CD54ACT1933A
型号: CD54ACT1933A
厂家: Intersil    Intersil
描述:

Presettable Synchronous 4-Bit Binary Up/Down Counter with Reset
可预置同步4位二进制加/减计数器复位

计数器
文件: 总2页 (文件大小:19K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CD54AC193/3A  
CD54ACT193/3A  
S E M I C O N D U C T O R  
COMPLETE DATA SHEET  
COMING SOON!  
Presettable Synchronous  
4-Bit Binary Up/Down Counter with Reset  
June 1997  
Description  
Functional Diagram  
BINARY PRESET  
The CD54AC193/3A and CD54ACT193/3A are up/down  
binary counters with separate up/down clocks. These  
devices utilize the Harris Advanced CMOS Logic technology.  
Presetting the counter to the number on preset data inputs  
(P0-P3) is accomplished by a LOW asynchronous parallel  
load input (PL). The counter is incremented on the  
LOW-to-HIGH transition of the Clock-Up input (and a HIGH  
level on the Clock-Down input) and decremented on the  
LOW-to-HIGH transition of the Clock-Down input (and a  
HIGH level on the Clock-Up input). A HIGH level on the  
Reset input overrides any other input to clear the counter to  
its zero state. The TCU (carry) output goes LOW half a clock  
period before the zero count is reached and returns to a  
HIGH level at the zero count. The TCD (borrow) output in the  
count down mode likewise goes LOW half a clock period  
before the maximum count (15 counts) and returns to HIGH  
at the maximum count. Cascading is effected by connecting  
the TCU and TCD outputs of a less significant counter to the  
Clock-Up and Clock-Down inputs, respectively, of the next  
most significant counter.  
P0 P1 P2 P3  
15  
1
10  
9
ASYNC  
PARALLEL  
LOAD  
11  
3
2
6
7
Q0  
Q1  
Q2  
Q3  
PL  
ENABLE  
BINARY  
OUTPUTS  
MASTER 14  
RESET  
5
CLOCK UP  
12 TERMINAL  
COUNT UP  
4
13  
TERMINAL  
CLOCK DOWN  
COUNT DOWN  
ACT INPUT LOAD TABLE  
INPUT  
UNIT LOAD (NOTE 1)  
P0 - P3, PL  
0.75  
0.85  
The CD54AC193/3A and CD54ACT193/3A are supplied in  
16-lead dual-in-line ceramic packages (F suffix).s  
MR, CPU, CPD  
NOTE:  
1. Unit load is I limit specified in DC Electrical Specifications  
CC  
o
Table, e.g., 2.4mA Max at +25 C.  
Absolute Maximum Ratings  
DC Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6V  
Power Dissipation Per Package, P  
D
CC  
o
o
DC Input Diode Current, I  
T = -55 C to +100 C (Package F) . . . . . . . . . . . . . . . . . . 500mW  
IK  
A
o
o
For V < -0.5V or V > V + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA  
T = +100 C to +125 C (Package F) . . . . . . . . Derate Linearly at  
I
I
CC  
A
o
DC Output Diode Current, I  
8mW/ C to 300mW  
OK  
For V < -0.5V or V > V + 0.5V. . . . . . . . . . . . . . . . . . . . .±50mA Operating Temperature Range, T  
O
O
CC  
A
o
o
DC Output Source or Sink Current, Per Output Pin, I  
Package Type F. . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C  
O
o
o
For V > -0.5V or V < V + 0.5V. . . . . . . . . . . . . . . . . . . . .±50mA  
Storage Temperature, T  
. . . . . . . . . . . . . . . . . .-65 C to +150 C  
O
O
CC  
STG  
DC V or GND Current, I or I  
Lead Temperature (During Soldering)  
CC  
CC  
GND  
For Up to 4 Outputs Per Device, Add ±25mA For Each  
Additional Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±100mA  
At Distance 1/16in. ± 1/32in. (1.59mm ± 0.79mm)  
From Case For 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C  
Unit Inserted Into a PC Board (Min Thickness 1/16in., 1.59mm)  
o
o
With Solder Contacting Lead Tips Only. . . . . . . . . . . . . . . +300 C  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
Recommended Operating Conditions  
o
o
Supply Voltage Range, V  
Operating Temperature, T . . . . . . . . . . . . . . . . . . .-55 C to +125 C  
CC  
A
Unless Otherwise Specified, All Voltages Referenced to GND  
Input Rise and Fall Slew Rate, dt/dv  
T = Full Package Temperature Range  
CD54AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V  
CD54ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
at 1.5V to 3V (AC Types) . . . . . . . . . . . . . . . . . . . 0ns/V to 50ns/V  
at 3.6V to 5.5V (AC Types) . . . . . . . . . . . . . . . . . 0ns/V to 20ns/V  
at 4.5V to 5.5V (AC Types) . . . . . . . . . . . . . . . . . 0ns/V to 10ns/V  
A
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . . 0V to V  
CC  
I
O
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.  
File Number 3897  
Copyright © Harris Corporation 1994  
1
WWW.ALLDATASHEET.COM  
Copyright © Each Manufacturing Company.  
All Datasheets cannot be modified without permission.  
This datasheet has been download from :  
www.AllDataSheet.com  
100% Free DataSheet Search Site.  
Free Download.  
No Register.  
Fast Search System.  
www.AllDataSheet.com  

相关型号:

CD54ACT193F3A

Binary Counter, ACT Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, CDIP16
RENESAS

CD54ACT193H

ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, UUC, DIE
TI

CD54ACT193H

Binary Counter, ACT Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS,
GE

CD54ACT193HX

Binary Counter, ACT Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS,
GE

CD54ACT20

Dual 4-Input NAND Gate
TI

CD54ACT20E

Logic IC
ETC

CD54ACT20EN

Logic IC
ETC

CD54ACT20F

Logic IC
ETC

CD54ACT20F3A

Dual 4-Input NAND Gate
TI

CD54ACT20F3A

IC,LOGIC GATE,DUAL 4-INPUT NAND,ACT-CMOS,DIP,14PIN,CERAMIC
RENESAS

CD54ACT20HX

NAND Gate, ACT Series, 2-Func, 4-Input, CMOS,
GE

CD54ACT20M

Logic IC
ETC