CDP1805 [INTERSIL]
CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer; CMOS 8位微处理器与片上RAM和计数器/定时器
| 型号： | CDP1805 |
| 厂家： | 
Intersil |
| 描述： | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer |
| 文件： | 总30页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
CDP1805AC,
CDP1806AC
CMOS 8-Bit Microprocessor with On-Chip RAM†
March 1997
and Counter/Timer
Features
Description
o
o
• Instruction Time of 3.2µs, -40 C to +85 C
The CDP1805AC and CDP1806AC are functional and per-
formance enhancements of the CDP1802 CMOS 8-bit regis-
ter-oriented microprocessor series and are designed for use
in general-purpose applications.
• 123 Instructions - Upwards Software Compatible With
CDP1802
• BCD Arithmetic Instructions
The CDP1805AC hardware enhancements include a 64-
byte RAM and an 8-bit presettable down counter. The
Counter/Timer which generates an internal interrupt request,
can be programmed for use in timebase, event-counting,
and pulse-duration measurement applications. The
Counter/Timer underflow output can also be directed to the
Q output terminal. The CDP1806AC hardware enhance-
ments are identical to the CDP1805AC, except the
CDP1806AC contains no on-chip RAM.
• Low-Power IDLE Mode
• Pin Compatible With CDP1802 Except for Terminal 16
• 64K-Byte Memory Address Capability
• 64 Bytes of On-Chip RAM†
• 16 x 16 Matrix of On-Board Registers
• On-Chip Crystal or RC Controlled Oscillator
• 8-Bit Counter/Timer
The CDP1805AC and CDP1806AC software enhancements
include 32 more instructions than the CDP1802. The 32 new
software instructions add subroutine call and return capabil-
ity, enhanced data transfer manipulation, Counter/Timer con-
trol, improved interrupt handling, single-instruction loop
counting, and BCD arithmetic.
Upwards software and hardware compatibility is maintained
when substituting a CDP1805AC or CDP1806AC for other
CDP1800-series microprocessors. Pinout is identical except
for the replacement of V
with ME on the CDP1805AC and
CC
the replacement of V
with V
on the CDP1806AC.
CC
DD
n
Ordering Information
CDP1805AC
CDP1805ACE
CDP1806AC
CDP1806ACE
TEMPERATURE RANGE
PACKAGE
Plastic DIP
Burn-In
PLCC
SBDIP
Burn-In
PKG. NO.
o
o
-40 C to +85 C
E40.6
-
CDP1806ACEX
CDP1806ACQ
CDP1806ACD
-
o
o
CDP1805ACQ
CDP1805ACD
CDP1805ACDX
-40 C to +85 C
N44.65
D40.6
o
o
-40 C to +85 C
† CDP1805AC Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
File Number 1370.2
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
CDP1805AC, CDP1806AC
Pinouts
CDP1805AC, CDP1806AC
(PDIP, SBDIP)
CDP1805AC, CDP1806AC
(PLCC, PACKAGE TYPE Q)
TOP VIEW
TOP VIEW
CLOCK
1
2
3
4
5
6
7
8
9
40 V
DD
WAIT
CLEAR
Q
39 XTAL
38 DMA IN
37 DMA OUT
36 INTERRUPT
35 MWR
34 TPA
SC1
SC0
6
5 4 3 2 1 44 43 42 41 40
MRD
BUS 7
BUS 6
SC0
MRD
7
39
38
37
36
35
34
33
32
31
30
29
MWR
TPA
TPB
MA7
MA6
NC
33 TPB
8
32 MA7
31 MA6
30 MA5
29 MA4
28 MA3
27 MA2
26 MA1
25 MA0
24 EF1
BUS 7
BUS 6
BUS 5
NC
9
BUS 5 10
BUS 4 11
BUS 3 12
BUS 2 13
BUS 1 14
BUS 0 15
10
11
12
13
14
15
16
17
BUS 4
BUS 3
BUS 2
BUS 1
BUS 0
MA5
MA4
MA3
MA2
MA1
†
16
18 19 20 21 22 23 24 25 26 27 28
N2 17
N1 18
N0 19
23 EF2
22 EF3
V
20
21 EF4
SS
† ME for CDP1805AC
for CDP1806AC
V
DD
Schematic
ADDRESS BUS
MA0 - MA7
MA0 - MA7
MA0-MA4
MRD
MRD
IN
CDP1805AC WITH
RAM, COUNTER/TIMER
CDP1806AC WITH
CDP1824
32 BYTE RAM
(USED WITH
CDP1851
PIO
CDP1833
1K BYTE ROM
COUNTER/TIMER
CDP1806AC ONLY)
CONTROL
MWR
MWR
TPA
TPA
OUT
ME
CEO
CS
BUS0 - BUS7
BUS0-BUS4
BUS0 - BUS7
BUS0 - BUS7
(CDP1805AC ONLY)
8-BIT DATA BUS
FIGURE 1. TYPICAL CDP1805AC, CDP1806AC SMALL MICROPROCESSOR SYSTEM
2
CDP1805AC, CDP1806AC
FIGURE 2. BLOCK DIAGRAM FOR CDP1805AC AND CDP1806AC
3
CDP1805AC, CDP1806AC
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
)
Thermal Resistance (Typical, Note 2)
θ
( C/W)
θ
( C/W)
DD
JA
JC
(All Voltages Referenced to V
Terminal). . . . . . . . . -0.5V to +7V
SS
PDIP Package . . . . . . . . . . . . . . . . . . .
PLCC Package . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
Device Dissipation Per Output Transistor
50
46
55
N/A
N/A
15
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
+0.5V
DD
DC Input Current, any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
T
= Full Package Temperature Range . . . . . . . . . . . . . . 100mW
A
Operating Temperature Range (T )
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
Package Type E and Q . . . . . . . . . . . . . . . . . . . . .-40 C to +85 C
A
o
o
o
o
o
o
Storage Temperature Range (T
). . . . . . . . . . . .-65 C to +150 C
STG
Lead Temperature (During Soldering)
At Distance 1/16 ±1/32in (1.59 ± 0.79mm) from case for
o
10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C
Printed Circuit Board Mount: 57mm x 57mm Minimum Area x 1.6mm
Thick G10 Epoxy Glass, or Equivalent.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions T = Full-Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges.
CDP1805ACD, CDP1805ACE
CDP1806ACD, CDP1806ACE
TEST CONDITIONS
V
DD
PARAMETER
DC Operating Voltage Range
Input Voltage Range
(V)
MIN
MAX
UNITS
-
4
6.5
V
V
-
V
V
SS
DD
Minimum Instruction Time (Note 1)
5
3.2
-
µs
(f = 5MHz)
CL
Maximum DMA Transfer Rate
5
5
-
0.625
5
Mbyte/s
MHz
Maximum Clock Input Frequency,
DC
Load Capacitance (C ) = 50pF
L
Maximum External Counter/Timer Clock
Input Frequency to EF1, EF2
5
DC
2
MHz
NOTES:
1. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch, Long Skip, NOP, and “68” family
instructions, which are more than two cycles.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
o
Static Electrical Specifications at T = -40 C to +85 C, V ±5%, Except as Noted
A
DD
CDP1805ACD, CDP1805ACE
CDP1806ACD, CDP1806ACE
V
V
V
DD
(NOTE 3)
O
IN
PARAMETER
(V)
(V)
(V)
MIN
TYP
MAX
UNITS
Quiescent Device Current, I
DD
-
0, 5
0, 5
5
5
5
5
5
5
5
5
-
50
4
200
µA
mA
mA
mA
mA
V
Output Low Drive (Sink) Current, (Except XTAL), I
0.4
0.4
4.6
4.6
-
1.6
0.2
-1.6
-0.1
-
-
OL
XTAL Output, I
OL
0.4
-4
-
Output High Drive (Source) Current (Except XTAL, I
OH
0, 5
0
-
-
XTAL, I
OH
-0.2
0
Output Voltage Low Level, V
OL
0, 5
0, 5
0.1
-
Output Voltage High Level, V
OH
-
4.9
5
V
4
CDP1805AC, CDP1806AC
o
o
Static Electrical Specifications at T = -40 C to +85 C, V ±5%, Except as Noted (Continued)
A
DD
CDP1805ACD, CDP1805ACE
CDP1806ACD, CDP1806ACE
V
V
V
DD
(NOTE 3)
O
IN
PARAMETER
(V)
(V)
(V)
MIN
TYP
MAX
UNITS
Input Low Voltage (BUS0 - BUS7, ME), V
0.5, 4.5
0.5, 4.5
-
-
5
5
-
-
-
1.5
-
V
V
IL
Input High Voltage (BUS0 - BUS7, ME), V
3.5
IH
Schmitt Trigger Input Voltage (Except BUS0 - BUS7, ME)
Positive Trigger Threshold, V
0.5, 4.5
-
5
5
5
5
5
-
2.2
2.9
1.9
0.9
±0.1
±0.2
5
3.6
2.8
1.6
±5
V
V
P
Negative Trigger Threshold, V
0.5, 4.5
-
0.9
N
Hysteresis, V
0.5, 4.5
-
0, 5
0, 5
-
0.3
V
H
Input Leakage Current, I
IN
-
-
-
-
-
µA
µA
pF
pF
Three-State Output Leakage Current, I
0, 5
±5
OUT
Input Capacitance, C
-
-
7.5
15
IN
Output Capacitance, C
-
-
10
OUT
Total Power Dissipation (Note 4)
Run
-
-
-
-
5
5
-
-
-
-
35
12
2
50
18
mW
mW
V
Idle “00” at M (0000)
Minimum Data Retention Voltage, V
V
= V
DD DR
2.4
100
DR
Data Retention Current, I
NOTES:
V
= 2.4
DD
25
µA
DR
o
3. Typical values are for T = +25 C and nominal V
.
A
DD
4. External clock: f = 5MHz, t , t = 10ns; C = 50pF.
R
F
L
o
o
Dynamic Electrical Specifications at T = -40 to +85 C; C = 50pF; Input t , t = 10ns; Input Pulse Levels = 0.1V to
A
L
R
F
V
-0.1V; V
= 5V, ±5%.
DD
DD
CDP1805AC CDP1806AC
(NOTE 5)
PARAMETER
TYP
MAX
UNITS
Propagation Delay Times
Clock to TPA, TPB, t
, t
150
325
275
200
150
375
225
250
250
420
275
550
450
325
275
625
400
425
425
650
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH PHL
Clock-to-Memory High-Address Byte, t
Clock-to-Memory Low-Address Byte, t
, t
PLH PHL
, t
PLH PHL
Clock to MRD, t
, t
PLH PHL
Clock to MWR, t
, t
PLH PHL
(See Note 5)
Clock to (CPU DATA to BUS), t
, t
PLH PHL
Clock to State Code, t
, t
PLH PHL
Clock to Q, t
Clock to N, t
, t
PLH PHL
, t
PLH PHL
Clock to Internal RAM Data to BUS, t
, t
PLH PHL
5
CDP1805AC, CDP1806AC
o
o
Dynamic Electrical Specifications at T = -40 to +85 C; C = 50pF; Input t , t = 10ns; Input Pulse Levels = 0.1V to
A
L
R
F
V
-0.1V; V
= 5V, ±5%. (Continued)
DD
DD
CDP1805AC CDP1806AC
(NOTE 5)
PARAMETER
TYP
MAX
UNITS
Minimum Set-Up And Hold Times (Note 2)
Data Bus Input Set-Up, t
-100
125
-75
0
225
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SU
Data Bus Input Hold, t
H
DMA Set-Up, t
SU
DMA Hold, t
100
125
0
175
320
50
0
H
ME Set-Up, t
SU
ME Hold, t
H
Interrupt Set-Up, t
-100
100
20
SU
Interrupt Hold, t
175
50
0
H
WAIT Set-Up, t
SU
EF1-4 Set-Up, t
-125
175
SU
EF1 -4 Hold, t
300
H
Minimum Pulse Width Times (Note 6)
CLEAR Pulse Width, t
100
75
175
100
ns
ns
WL
CLOCK Pulse Width, t
W
NOTES:
5. Typical values are for T = 25 C and nominal V
o
A
DD
.
6. Maximum limits of minimum characteristics are the values above which all devices function.
o
1
Timing Specifications as a function of T (T = /f
) at T = -40 to +85 C, V
= 5V, ±15%
DD
CLOCK
A
CDP1805AC, CDP1806AC
(NOTE 7)
PARAMETER
TYP
MAX
UNITS
High-Order Memory-Address Byte
Set-Up to TPA
MRD to TPA
Time, t
SU
2T-275
2T -175
T/2 -75
ns
ns
Time, t
T/2 -100
SU
High-Order Memory-Address Byte
Hold after TPA Time, t
T/2 +75
T +180
T/2 +100
T +240
ns
ns
ns
ns
H
Low-Order Memory-Address Byte
Hold after WR Time, t
CPU Data to Bus
H
Hold after WR Time, t
T +110
T +150
H
Required Memory Access Time, t
Address to Data
ACC
o
4.5T -440
4.5T -330
NOTE:
7. Typical values are for T = +25 C and nominal V
.
DD
A
6
CDP1805AC, CDP1806AC
Timing Waveforms For Possible Operating Modes
INTERNAL RAM READ CYCLE
INTERNAL RAM WRITE CYCLE
00
10
20
30
40
50
60
70
00
10
20
30
40
50
60
70
CLOCK
01
11
21
31
41
51
61
71
01
11
21
31
41
51
61
71
TPA
TPB
MEMORY
ADDRESS
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
MRD
MWR
†ME
IN
VALID DATA FROM MEMORY
DATA
BUS
VALID DATA FROM CPU
NOTE:
8. ME has a minimum setup and hold time with respect to the beginning of clock 70. For a memory read operation, RAM data will appear on
the data bus during the time ME is active after clock 31. The time shown can be longer, if for instance, a DMA out operation is performed
on internal RAM data, to allow data enough time to be latched into an external device. The internal RAM is automatically deselected at
the end of clock 71 independent of ME.
† For CDP1805AC only.
FIGURE 3. INTERNAL MEMORY OPERATION TIMING WAVEFORMS
EXTERNAL MEMORY READ CYCLE
10 20 30 40 50 60
EXTERNAL MEMORY WRITE CYCLE
10 20 30 40 50 60 70
00
70
00
CLOCK
TPA
01
11
21
31
41
51
61
71
01
11
21
31
41
51
61
71
TPB
MEMORY
ADDRESS
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
MRD
MWR
†ME IN
(HIGH)
DATA
BUS
DATA LATCHED IN CPU
VALID DATA FROM CPU
NOTE:
† For CDP1805AC only.
FIGURE 4. EXTERNAL MEMORY OPERATION TIMING WAVEFORMS
7
CDP1805AC, CDP1806AC
0
1
2
3
4
5
6
7
0
t
W
CLOCK
00 01
10 11
20
21
30
31 40
41 50
51
60
61 70 71
00
01
t
t
PHL
PLH
TPA
TPB
t
t
PLH
PHL
t
t
PLH, PHL
t
t
H
SU
t
MEMORY
ADDRESS
HIGH ORDER
ADDRESS BYTE
LOW ORDER
ADDRESS BYTE
H
t
t
PLH, PHL
t
t
PHL
SU
MRD
(MEMORY
READ CYCLE)
t
PLH
t
PHL
t
PLH
MWR
(MEMORY
WRITE CYCLE)
t
PHL
t
SU
t
H
† ME
(MEMORY
ENABLE)
t
IS ALLOWABLE
INTERNAL RAM
ACCESS TIME
SU
t
PLH
†† EMS
(EXTERNAL
MEMORY
t
PHL
SELECT)
t
H
t
t
PLH,
PHL
DATA FROM
CPU TO BUS
t
t
PLH
PHL
t
t
PLH, PLH
DATA FROM
INTERNAL MEMORY
t
t
PLH,
PHL
TO BUS (ME = LOW)
STATE CODES
Q
t
t
PLH, PHL
t
t
PLH, PHL
t
PHL
t
N0, N1, N2
(I/O EXECUTION
CYCLE)
PLH
DATA LATCHED
IN CPU
t
SU
t
DATA FROM
BUS TO CPU
H
DMA SAMPLED (S1, S2, S3)
DMA REQUEST
t
t
H
SU
INTERRUPT
SAMPLED (S1, S2)
INTERRUPT
REQUEST
t
t
SU
H
FLAG LINES
SAMPLED END OF S0
EF1 - EF4
t
t
H
SU
t
t
t
t
H
SU
H
SU
WAIT
t
WL
CLEAR
NOTES:
† This Timing Diagram is used to show signal relationships only, and does not represent any specific machine cycle.
† All measurements are referenced to 50% point of the wave forms.
† Shaded areas indicate “don’t care” or undefined state. Multiple transitions may occur during this period.
† For the run (RAM only) mode only.
†† For the run (RAM/ROM) mode only.
FIGURE 5. TIMING WAVEFORMS
8
CDP1805AC, CDP1806AC
MRD = V : Input data from I/O to CPU and memory.
DD
Enhanced CDP1805AC and CDP1806AC
Operation
MRD = V : Output data from Memory to I/O.
SS
Timing
EF1 to EF4 (4 Flags)
Timing for the CDP1805AC and CDP1806AC is the same as These inputs enable the I/O controllers to transfer status
the CDP1802 microprocessor series, with the following information to the processor. The levels can be tested by the
exceptions:
conditional branch instructions. They can be used in con-
junction with the INTERRUPT request line to establish inter-
rupt priorities. The flag(s) are sampled at the end of every S0
cycle. EF1 and EF2 are also used for event counting and
pulse width measurement in conjunction with the
Counter/Timer.
• 4.5 Clock Cycles Are Provided for Memory Access Instead
of 5.
• Q Changes 1/2 Clock Cycle Earlier During the SEQ and
REQ Instructions.
• Flag Lines (EF1-EF4) Are Sampled at the End of the S0
Cycle Instead of at the Beginning of the S1 Cycle.
INTERRUPT, DMA-IN, DMA-OUT (3 I/O Requests)
DMA-lN and DMA-OUT are sampled during TPB every S1,
S2, and S3 cycle. INTERRUPT is sampled during TPB every
S1 and S2 cycle.
• Pause Can Only Occur on the Low-To-High Transition of
Either TPA or TPB, Instead of any Negative Clock Transi-
tion.
Interrupt Action - X and P are stored in T after executing
current instruction; designator X is set to 2; designator P is
set to 1; interrupt enable (MIE) is reset to 0 (inhibit); and
instruction execution is resumed. The interrupt action
requires one machine cycle (S3).
Special Features
Schmitt triggers are provided on all inputs, except ME and
BUS 0-BUS 7, for maximum immunity from noise and slow
signal transitions. A Schmitt Trigger in the oscillator section
allows operation with an RC or crystal.
DMA Action - Finish executing current instruction; R(0)
points to memory area for data transfer; data is loaded into
or read out of memory; and R(0) is incremented.
The CDP1802 Series LOAD mode is not retained. This
mode (WAIT, CLEAR = 0) is not allowed on the CDP1805AC
and CDP1806AC.
NOTE: In the event of concurrent DMA and INTERRUPT requests,
DMA-IN has priority followed by DMA-OUT and then INTERRUPT.
(The interrupt request is not internally latched and must be held true
after DMA).
A low power mode is provided, which is initiated via the IDLE
instruction. In this mode all external signals, except the oscil-
lator, are stopped on the low-to-high transition of TPB. All
outputs remain in their previous states, MRD is set to a logic
“1”, and the data bus floats. The IDLE mode is exited by a
DMA or INT condition. The INT includes both external inter-
rupts and interrupts generated by the Counter/Timer. The
only restrictions are that the Timer mode, which uses the
TPA ÷ 32 clock source, and the underflow condition of the
Pulse Width Measurement modes are not available to exit
the IDLE mode.
SC0, SC1, (2 State Code Lines)
These outputs indicate that the CPU is: 1) fetching an
instruction, or 2) executing an instruction, or 3) processing a
DMA request, or 4) acknowledging an interrupt request. The
levels of state code are tabulated below. All states are valid
at TPA.
STATE CODE LINES
STATE TYPE
S0 (Fetch)
SC1
L
SC0
L
Signal Descriptions
Bus 0 to Bus 7 (Data Bus)
S1 (Execute)
S2 (DMA)
L
H
8-Bit bidirectional DATA BUS lines. These lines are used for
transferring data between the memory, the microprocessor,
and I/O devices.
H
L
S3 (Interrupt)
H
H
N0 to N2 (I/O) Lines
NOTE: H = V , L = V
DD
SS.
Activated by an I/O instruction to signal the I/O control logic
of a data transfer between memory and I/O interface. These
lines can be used to issue command codes or device selec-
tion codes to the I/O devices. The N-bits are low at all times
except when an I/O instruction is being executed. During this
time their state is the same as the corresponding bits in the
N Register. The direction of data flow is defined in the I/O
instruction by bit N3 (internally) and is indicated by the level
of the MRD Signal:
TPA, TPB (2 Timing Pulses)
Positive pulses that occurrence in each machine cycle (TPB
follows TPA). They are used by I/O controllers to interpret
codes and to time interaction with the data bus. The trailing
edge of TPA is used by the memory system to latch the high-
order byte of the multiplexed 16-bit memory address.
9
CDP1805AC, CDP1806AC
MA0 to MA7 (8 Memory Address Lines)
ME (Memory Enable CDP1805AC Only)
In each cycle, the higher-order byte of a 16-bit memory This active low input is used to select or deselect the internal
address appears on the memory address lines MA0-7 first. RAM. It must be active prior to clock 70 for an internal RAM
Those bits required by the memory system can be strobed access to take place. Internal RAM data will appear on the
into external address latches by timing pulse TPA. The low- data bus during the time that ME is active (after clock 31).
order byte of the 16-bit address appears on the address Thus, if this data is to be latched into an external device (i.e.,
lines 1/2 clock after the termination of TPA.
during an OUTPUT instruction or DMA OUT cycle), ME
should be wide enough to provide enough time for valid data
to be latched. The internal RAM is automatically deselected
after clock 71. ME is ineffective when MRD • MWR = 1.
MWR (Write Pulse)
A negative pulse appearing in a memory-write cycle, after
the address lines have stabilized.
The internal RAM is not internally mask-decoded. Decoding
of the starting address is performed externally, and may
reside in any 64-byte block of memory.
MRD (Read Level)
A low level on MRD indicates a memory read cycle. It can be
used to control three-state outputs from the addressed mem-
ory and to indicate the direction of data transfer during an I/O
instruction.
V
(CDP1806AC Only)
DD
This input replaces the ME signal of the CDP1805AC and
must be connected to the positive power supply.
Q
V
, V , (Power Levels)
DD SS
Single bit output from the CPU which can be set or reset,
under program control. During SEQ and REQ instruction
execution, Q is set or reset between the trailing edge of TPA
and the leading edge of TPB. The Q line can also be con-
trolled by the Counter/Timer underflow via the Enable Toggle
Q instruction.
V
is the most negative supply voltage terminal and is nor-
SS
mally connected to ground. V
age terminal. All outputs swing from V
SS
recommended input voltage swing is from V to V
is the positive supply volt-
to V . The
DD
DD
.
SS
DD
Architecture
The Enable Toggle Q command connects the Q-line flip-flop
to the output of the counter, such that each time the counter
decrements from 01 to its next value, the Q line changes
state. This command is cleared by a LOAD COUNTER
(LDC) instruction with the Counter/Timer stopped, a CPU
reset, or a BRANCH COUNTER INTERRUPT (BCl) instruc-
tion with the counter interrupt flip-flop set.
Figure 2 shows a block diagram of the CDP1805AC and
CDP1806AC. The principal feature of this system is a regis-
ter array (R) consisting of sixteen 16-bit scratchpad regis-
ters. Individual registers in the array (R) are designated
(selected) by a 4-bit binary code from one of the 4-bit regis-
ters labeled N, P, and X. The contents of any register can be
directed to any one of the following paths:
Clock
1. The external memory (multiplexed, higher-order byte first
on to 8 memory address lines).
Input for externally generated single-phase clock. The maxi-
mum clock frequency is 5MHz at V
counted down internally to 8 clock pulses per machine cycle.
= 5V. The clock is
DD
2. The D register (either of the two bytes can be gated to D).
3. The increment/decrement circuit where it is increased or
decreased by one and stored back in the selected 16-bit
register.
XTAL
Connection to be used with clock input terminal, for an exter-
nal crystal, if the on-chip oscillator is utilized.
4. To any other 16-bit scratch pad register in the array.
The four paths, depending on the nature of the instruction,
may operate independently or in various combinations in the
same machine cycle.
WAIT, CLEAR (2 Control Lines)
Provide four control modes as listed in the following truth
table:
Most instructions consist of two 8-clock-pulse machine
cycles. The first cycle is the fetch cycle, and the second, and
more if necessary, are execute cycles. During the fetch cycle
the four bits in the P designator select one of the 16 registers
R(P) as the current program counter. The selected register
R(P) contains the address of the memory location from
which the instruction is to be fetched. When the instruction is
read out from the memory, the higher order 4 bits of the
instruction byte are loaded into the register and the lower
order 4 bits into the N register. The content of the program
counter is automatically incremented by one so that R(P) is
now “pointing” to the next byte in the memory.
CLEAR
WAIT
MODE
Not Allowed
Reset
L
L
L
H
L
H
H
Pause
H
Run
10
CDP1805AC, CDP1806AC
The X designator selects one of the 16 registers R(X) to Another important use of R as a data pointer supports the
“point” to the memory for an operand (or data) in certain ALU built-in Direct-Memory-Access (DMA) function. When a
or I/O operations.
DMA-ln or DMA-Out request is received, one machine cycle
is “stolen”. This operation occurs at the end of the execute
machine cycle in the current instruction. Register R(0) is
always used as the data pointer during the DMA operation.
The data is read from (DMA-Out) or written into (DMA-ln) the
memory location pointed to by the R(0) register. At the end
of the transfer, R(0) is incremented by one so that the pro-
cessor is ready to act upon the next DMA byte transfer
request. This feature in the CDP1805AC and CDP1806AC
architecture saves a substantial amount of logic when fast
exchanges of blocks of data are required, such as with mag-
netic discs or during CRT-display-refresh cycles.
The N designator can perform the following five functions
depending on the type of instruction fetched:
1. Designate one of the 16 registers in R to be acted upon
during register operations.
2. Indicate to the I/O devices a command code or device-
selection code for peripherals.
3. Indicate the specific operation to be executed during the
ALU instructions, types of tests to be performed during
the Branch instructions, or the specific operation required
in a class of miscellaneous instructions.
Data Registers
4. Indicate the value to be loaded into P to designate a new
register to be used as the program counter R(P).
When registers in R are used to store bytes of data, instruc-
tions are provided which allow D to receive from or write into
either the higher-order- or lower-order-byte portions of the
register designated by N. By this mechanism (together with
loading by data immediate) program pointer and data pointer
designations are initialized. Also, this technique allows
scratchpad registers in R to be used to hold general data. By
employing increment or decrement instructions, such regis-
ters may be used as loop counters. The new RLDl, RLXA,
RSXD, and RNX instructions also allow loading, storing, and
exchanging the full 16-Bit contents of the R registers without
affecting the D register. The new DBNZ instruction allows
decrementing and branching-on-not-zero of any 16-Bit R
register also without affecting the D register.
5. Indicate the value to be loaded into X to designate a new
register to be used as data pointer R(X).
The registers in R can be assigned by a programmer in three
different ways as program counters, as data pointers, or as
scratchpad locations (data registers) to hold two bytes of
data.
Program Counters
Any register can be the main program counter; the address
of the selected register is held in the P designator. Other reg-
isters in R can be used as subroutine program counters. By
a single instruction the contents of the P register can be
changed to effect a “call” to subroutine. When interrupts are The Q Flip-Flop
being serviced, register R(1) is used as the program counter
An internal flip-flop, Q, can be set or reset by instruction and
for the user's interrupt servicing routine. After reset, and dur-
ing a DMA operation, R(0) is used as the program counter.
At all other times the register designated as program counter
is at the discretion of the user.
can be sensed by conditional branch instructions. It can also
be driven by the underflow output of the counter/timer The
output of Q is also available as a microprocessor output.
REGISTER SUMMARY
Data Pointers
D
DF
B
8 Bits Data Register (Accumulator)
1-Bit Data Flag (ALU Carry)
The registers in R may be used as data pointers to indicate a
location in memory. The register designated by X (i.e., R(X))
points to memory for the following instructions (see Table 1):
8 Bits Auxiliary Holding Register
R
16 Bits 1 of 16 Scratch and Registers
1. ALU operations.
P
4 Bits Designates which Register is Program
Counter
2. Output instructions.
3. Input instructions.
X
N
4 Bits Designates which Register is Data Pointer
4 Bits Holds Low-Order Instr. Digit
4 Bits Holds High-Order Instr. Digit
8 Bits Holds old X, P after Interrupt (X is high nibble)
1-Bit Output Flip-Flop
4. Register to memory transfer.
5. Memory to register transfer.
6. Interrupt and subroutine handling.
I
T
Q
The register designated by N (i.e., R(N)) points to memory
for the “load D from memory” instructions ON and 4N and
the “Store D” instruction 5N. The register designated by P
(i.e., the program counter) is used as the data pointer for
ALU instructions F8-FD, FF, 7C, 7D, 7F, and the RLDl
instruction 68CN. During these instruction executions, the
operation is referred to as “data immediate”.
CNTR
CH
MIE
ClE
XlE
ClL
8-Bits Counter/Timer
8 Bits Holds Counter Jam Value
1-Bit
Master Interrupt Enable
1-Bit Counter Interrupt Enable
1-Bit
1-Bit
External Interrupt Enable
Counter Interrupt Latch
11
CDP1805AC, CDP1806AC
Interrupt Servicing
latched counter interrupt request signal will be reset when
the branch is taken, when the CPU is reset, or with a LDC
instruction with the Counter stopped. Note, that exiting a
counter-initiated interrupt routine without resetting the
counter-interrupt latch will result in immediately reentering
the interrupt routine.
Register R(1) is always used as the program counter when-
ever interrupt servicing is initialized. When an interrupt
request occurs and the interrupt is allowed by the program
(again, nothing takes place until the completion of the cur-
rent instruction), the contents of the X and P registers are
stored in the temporary Register T, and X and P are set to
new values; hex digit 2 in X and hex digit 1 in P. Master Inter-
rupt Enable is automatically deactivated to inhibit further
interrupts. The user’s interrupt routine is now in control; the
contents of T may be saved by means of a single SAV
instruction (78) in the memory location pointed to by R(X) or
the contents of T, D, and DF may be saved using a single
DSAV instruction (6876). At the conclusion of the interrupt,
the user's routine may restore the pre-interrupted value of X
and P with either a RET instruction (70) which permits fur-
ther interrupts, or a DlS instruction (71), which disables fur-
ther interrupts.
Counter/Timer and Controls (See Figure 7)
This logic consists of a presettable 8-Bit down-counter (Mod-
ulo N type), and a conditional divide-by-32 prescaler. After
counting down to (01) the counter returns to its initial value
16
at the next count and sets the Counter Interrupt Latch. It will
continue decrementing on subsequent counts. If the counter
is preset to (00) full 256 counts will occur.
16
During a Load Counter instruction (LDC) if the counter was
stopped with a STPC Instruction, the counter and its holding
register (CH) are loaded with the value in the D Register and
any previous counter interrupt is cleared. If the LDC is exe-
cuted when the counter is running, the contents of the D
Register are loaded into the holding register (CH) only and
Interrupt Generation and Arbitration (See Figure 6)
Interrupt requests can be generated from the following any previous counter interrupt is not cleared. (LDC RESETS
sources:
the Counter Interrupt Latch only when the Counter is
stopped). After counting down to (01) the next count will
load the new initial value into the counter, set the Counter
Interrupt Latch, and operation will continue.
16
1. Externally through the interrupt input (request not
latched).
2. Internally due to Counter/Timer response (request is
latched).
a. On the transition from count (01)
(counter underflow).
to its next value
16
b. On the
mode 1.
transition of EF1 in pulse measurement
transition of EF2 in pulse measurement
c. On the
mode 2.
For an interrupt to be serviced by the CPU, the appropriate
Interrupt Enable flip-flops must be set. Thus, the External
Interrupt Enable flip-flop must be set to service an external
interrupt request, and the Counter Interrupt Enable flip-flop
must be set to service an internal Counter/Timer interrupt
request. In addition, the Master interrupt Enable flip-flop (as
used in the CDP1802) must be set to service either type of
request. All 3 flip-flops are initially enabled with the applica-
tion of a hardware reset, and, can be selectively enabled or
disabled with software: ClE, ClD instructions for the ClE flip-
flop; XlE, XlD instructions for the XIE flip-flop; RET, DIS
instructions for the MIE flip flop.
Short branch instructions on Counter Interrupt (BCI) and
External Interrupt (BXl) can be placed in the user's interrupt
service routine to provide a means of identifying and priori-
tizing the interrupt source. Note, however, that since the
External Interrupt request is not latched, it must remain
active until the short branch is executed if this priority arbitra-
tion scheme is used.
Interrupt requests can also be polled if automatic interrupt
service is not desired (MlE = 0). With the Counter Interrupt
and External Interrupt short branch instructions, the branch
will be taken if an interrupt request is pending, regardless of
the state of any of the 3 Interrupt Enable flip-flops. The
12
CDP1805AC, CDP1806AC
RET
MIE
MASTER
INTERRUPT
ENABLE
FF
S
R
Q
RESET
S3
COUNTER
UNDERFLOW
TO BRANCH
LOGIC (BCI)
(MIE)
S
R
Q
PULSE MODE EF1
PULSE MODE EF2
DIS
COUNTER
INTERRUPT
LATCH
CI
BCI
(CIL)
CIE
RESET
COUNTER
INTERRUPT
ENABLE
FF
S
R
LDC • COUNTER
RESET
CID
STOPPED
Q
Q
(CIE)
INTERRUPT
REQUESTS
XI
EXTERNAL INT
TO BRANCH
LOGIC (BXI)
EXTERNAL
INTERRUPT
ENABLE
FF
XIE
S
R
RESET
XID
(XIE)
FIGURE 6. INTERRUPT LOGIC CONTROL DIAGRAM
The Counter/Timer has the following five programmable The modes can be changed without affecting the stored
modes: count.
1. Event Counter 1: Input to counter is connected to the EF1 Those modes which use EF1 and EF2 terminals as inputs do
terminal. The high-to-low transition decrements the not exclude testing these flags for branch instructions.
counter.
The Stop Counter (STPC) instruction clears the counter
2. Event Counter 2: Input to counter is connected to the EF2 mode and stops counting. The STPC instruction should be
terminal. The high-to-low transition decrements the executed prior to a GEC instruction, if the counter is in the
counter.
Event Counter Mode 1 or 2.
3. Timer: Input to counter is from the divide by 32 prescaler In addition to the five programmable modes, the Decrement
clocked by TPA. The prescaler is decremented on the Counter instruction (DTC) enables the user to count in soft-
low-to-high transition of TPA. The divide by 32 prescaler ware. In order to avoid conflict with counting done in the
is reset when the counter is in a mode other than the other modes, the instruction should be used only after the
Timer mode, system RESET, or stopped by a STPC.
mode has been cleared by a Stop Counter instruction.
4. Pulse Duration Measurement 1: Input to counter con- The Enable Toggle Q instruction (ETQ) connects the Q-line
nected to TPA. Each low-to-high transition of TPA decre- flip-flop to the output of the counter, such that each time the
ments the counter if the input signal at EF1 terminal (gate counter decrements from 01 to its next value, the Q output
input) is low. On the transition of EF1 to the positive state, changes state. This action is independent of the counter
the count is stopped, the mode is cleared, and the inter- mode and the Interrupt Enable flip-flops. The Enable Toggle
rupt request latched. If the counter underflows while the Q condition is cleared by an LDC with the Counter/Timer
input is low, interrupt will also be set, but counting will stopped, system Reset, or a BCl with Cl = 1.
continue.
NOTE: SEQ and REQ instructions are independent of ETQ, they
can SET or RESET Q while the Counter is running.
5. Pulse Duration Measurement 2: Operation is identical to
Pulse Duration Measurement 1, except EF2 is used as
the gate input.
On-Board Clock (See Figure 8, Figure 9 and Figure 10)
Clock circuits may use either an external crystal or an RC
network.
A typical crystal oscillator circuit is shown in Figure 8. The
crystal is connected between terminals 1 and 39 (CLOCK
and XTAL) in parallel with a resistance, RF (1mΩ typ). Fre-
quency trimming capacitors, C and C
, may be required
IN OUT
at terminals 1 and 39. For additional information on crystal
oscillators, see lCAN-6565.
13
CDP1805AC, CDP1806AC
STPC
STM
R
÷ 32
TO INTERRUPT LATCH
TPA
EF1
COUNTER
INH
UNDERFLOW
Q OUTPUT
SPMI
OUT
C
D
Q
Q
8-BIT
DOWN
COUNTER
ETQ
LDC
Q FF
SCMI
LOAD
READ
EF2
SPM2
SCM2
DTC
GEC
FIGURE 7. TIMER/COUNTER DIAGRAM
Because of the Schmitt Trigger input, an RC oscillator can
be used as shown in Figure 9. The frequency is approxi-
mately 1/RC (see Figure 10).
o
V
= 5V AT 25 C
DD
10M
1M
RF
1MΩ
100K
10K
CLOCK†
1
39 XTAL †
XTAL
5MHz PARALLEL
RESONANT
CRYSTAL
C
15pF
C
27pF
IN
OUT
1
10
100
1K
10K
100K
1M
FREQUENCY (Hz)
FIGURE 10. NOMINAL COMPONENT VALUES AS A FUNCTION
OF FREQUENCY FOR THE RC OSCILLATOR
†Pin numbers refer to 40 pin DIP.
FIGURE 8. TYPICAL 5MHz CRYSTAL OSCILLATOR
CONTROL MODES
R
CLEAR
WAIT
MODE
Not Allowed
Reset
L
L
L
H
L
CLOCK†
1
39 XTAL †
H
H
Pause
H
Run
C
†Pin numbers refer to 40 pin DIP.
FIGURE 9. RC NETWORK FOR OSCILLATOR
14
CDP1805AC, CDP1806AC
The function of the modes are defined as follows:
Power-up Reset/Run Circuit
Power-up Reset/Run can be realized with the circuit shown
in Figure 11.
Reset
V
The levels on the CDP1805A and CDP1806A external signal
lines will asynchronously be forced by RESET to the follow-
ing states:
DD
THE RC TIME CONSTANT
CDP1805AC
CDP1806AC
SHOULD BE GREATER THAN
THE OSCILLATOR START-UP
TIME (TYPICALLY 20ms)
WAIT
R
R
P
X
Q = 0
MRD = 1
TPB = 0
SC1, SC0 = 0,1
(EXECUTE)
N0, N1, N2 = 0, 0, 0 TPA = 0
MWR = 1
BUS 0-7 = 0
MA0-7 = RO.1
CLEAR
Internal Changes Caused By RESET are:
C
X
l, N Instruction Register is cleared to 00. XlE and CIE are set
to allow interrupts following initialize. ClL is cleared (any
pending counter interrupt is cleared), counter is stopped, the
counter mode is cleared, and ETQ is disabled.
FIGURE 11. RESET/RUN DIAGRAM
Initialization Cycle
Pause
The first machine cycle following termination of RESET is an
initialization cycle which requires 9 clock pulses. During this
cycle the CPU remains in S1 and the following additional
changes occur:
Pause is a low power mode which stops the internal CPU
timing generator and freezes the state of the processor. The
CPU may be held in the Pause mode indefinitely. Hardware
pause can occur at two points in a machine cycle, on the
low-to-high transition of either TPA or TPB. A TPB pause can
also be initiated by software with the execution of an IDLE
instruction. In the pause mode, the oscillator continues to run
but subsequent clock transitions are ignored. TPA and TPB
remain at their previous state (see Figure 12).
1 → MlE
X, P → T (The old value of X, P will be put into T. This
only has meaning following an orderly Reset with power
applied).
X, P, RO ← 0 (X, P, and RO are cleared).
Pause is entered from RUN by dropping WAIT low. Appropri-
ate Setup and Hold times must be met.
Interrupt and DMA servicing is suppressed during the initial-
ization cycle. The next cycle is an S0 or an S2 but never an
S1 or S3.The use of a 71 instruction followed by 00 at mem-
ory locations 0000 and 0001, may be used to reset MIE so
as to preclude interrupts until ready for them.
If Pause is entered while in the event counter mode, the
appropriate Flag transition will continue to decrement the
counter.
Hardware-initiated pause is exited to RUN by raising the
Wait line high. Pause entered with an IDLE instruction
requires DMA, INTERRUPT or RESET to resume execution.
Reset and Initialize Do Not Affect:
D (Accumulator)
DF
Run
R1, R2, R3, R4, R5, R6, R7, R8, R9, FA, RB, RC, RD, RE, RF
CH (Counter Holding Register)
May be initiated from the Pause or Reset mode functions. If
initiated from Pause, the CPU resumes operation at the
point it left off. If paused at TPA, it will resume on the next
high-to-low clock transition, while if paused at TPB, it will
resume on the next low-to-high clock transition (see Figure
12). When initiated from the Reset operation, the first
machine cycle following Reset is always the initialization
cycle. The initialization cycle is then followed by a DMA (S2)
cycle or fetch (S0) from location 0000 in memory.
Counter (the counter is stopped but the value is unaffected)
Schmitt Trigger Inputs
All inputs except BUS 0-BUS 7 and ME contain a Schmitt
Trigger circuit, which is especially useful on the CLEAR input
as a power-up RESET (see Figure 11) and the CLOCK input
(see Figure 8 and Figure 9).
15
CDP1805AC, CDP1806AC
State Transitions
The CDP1805A and CDP1806A state transitions are shown which requires 9 clock pulses. Reset is asynchronous and
in Figure 13. Each machine cycle requires the same period can be forced at any time.
of time, 8 clock pulses, except the initialization cycle (INlT)
ENTER RESUME
ENTER RESUME
PAUSE
RUN
PAUSE
RUN
PAUSE
PAUSE
50 51 60
61 70 71 00 01 10
CLOCK
TPB
CLOCK
70 71 00 01
10 11 20 21 30
PAUSE
PAUSE
t
t
PHL
PLH
t
t
PHL
PLH
TPA
WAIT
WAIT
t
SU
t
SU
t
t
H
SU
t
t
H
SU
NOTE:
9. Pause (in clock waveform) while represented here as one clock
cycle in duration, could be infinitely long.
FIGURE 12A. TPA PAUSE TIMING
FIGURE 12B. TPB PAUSE TIMING
FIGURE 12. PAUSE MODE TIMING WAVEFORMS
RESET
PAUSE
INT • DMA • RESET
IDLE • DMA • INT
FORCE S1
S1 RESET
DMA + INT
(LONG BRANCH,
LONG SKIP, NOP, RSXD, ETC)
DMA • FORCE S1
S1 EXECUTE
S1 INIT
DMA
DMA • IDLE • INT
• FORCE S1
INT • DMA • FORCE S1
DMA
DMA
FORCE S0
PRIORITY: RESET
FORCE S0, S1
DMA IN
DMA OUT
INT
S2 DMA
DMA
SO FETCH
S3 INT
DMA • INT
“68”
FORCE S0
DMA
INT • DMA
FIGURE 13. STATE TRANSITION DIAGRAM
16
CDP1805AC, CDP1806AC
Instruction Set
The CDP1805AC and CDP1806AC instruction summary is
given in Table 1. Hexadecimal notation is used to refer to the
4-bit binary codes.
R(W).0: Lower-order byte of R(W)
R(W).1: Higher-order byte of R(W)
Operation Notation
In all registers, bits are numbered from the least significant
bit (LSB) to the most significant bit (MSB) starting with 0.
M (R(N)) → D; R(N) + 1 → R(N)
R(W): Register designated by W, where
W = N or X, or P
This notation means: The memory byte pointed to by R(N) is
loaded into D, and R(N) is incremented by 1.
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES)
NO. OF
MACHINE
CYCLES
INSTRUCTION
MEMORY REFERENCE
LOAD IMMEDIATE
MNEMONIC
OP CODE
OPERATION
2
5
LDI
F8
M(R(P)) → D; R(P) + 1 → R(P)
REGISTER LOAD IMMEDIATE
RLDI
68CN
M(R(P)) → R(N).1; M(R(P)) + 1 →
(Note 10) R(N).0; R(P) + 2 → R(P)
LOAD VIA N
2
2
2
2
5
LDN
LDA
0N
4N
M(R(N)) → D; FOR N NOT 0
M(R(N)) → D; R(N) + 1 → R(N)
M(R(X)) → D
LOAD ADVANCE
LOAD VIA X
LDX
F0
LOAD VIA X AND ADVANCE
LDXA
RLXA
72
M(R(X)) → D; R(X) + 1 → R(X)
M(R(X)) → R(N).1; M(R(X) + 1) →
REGISTER LOAD VIA X AND
ADVANCE
686N
(Note 10) R(N).0; R(X)) + 2 → R(X)
STORE VIA N
2
2
5
STR
STXD
RSXD
5N
73
D → M(RN))
STORE VIA X AND DECREMENT
D → M(R(X)); R(X) - 1 → R(X)
REGISTER STORE VIA X AND
DECREMENT
68AN
R(N).0 → M(R(X)); R(N).1 →
(Note 10) M(R)(X) - 1); R(X) - 2 → R (X)
REGISTER OPERATIONS
INCREMENT REG N
2
2
5
INC
DEC
1N
2N
R(N) + 1 → R(N)
R(N) - 1 → R(N)
DECREMENT REG N
DECREMENT REG N AND LONG
BRANCH IF NOT EQUAL 0
DBNZ
682N
R(N) - 1 → R(N); IF R(N) NOT 0,
M(R(P)) → R(P).1, M(R(P) + 1) →
R(P).0, ELSE R(P) + 2 → R(P)
INCREMENT REG X
GET LOW REG N
PUT LOW REG N
GET HIGH REG N
PUT HIGH REG N
2
2
2
2
2
4
IRX
GLO
PLO
GHI
PHI
60
8N
AN
9N
BN
R(X) + 1 → R(X)
R(N).0 → D
D → R(N).0
R(N).1 → D
D → R(N).1
R(N) → R(X)
REGISTER N TO REGISTER X
COPY
RNX
68BN
(Note 10)
LOGIC OPERATIONS (Note 19)
OR
2
2
2
2
OR
ORI
XOR
XRI
F1
F9
F3
FB
M(R(X)) OR D → D
OR IMMEDIATE
M(R(P)) OR D → D; R(P) + 1 → R(P)
M(R(X)) XOR D → D
EXCLUSIVE OR
EXCLUSIVE OR IMMEDIATE
M(R(P)) XOR D → D;
R(P) + 1 → R(P)
AND
2
AND
F2
M(R(X)) AND D → D
17
CDP1805AC, CDP1806AC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
NO. OF
MACHINE
INSTRUCTION
AND IMMEDIATE
CYCLES
MNEMONIC
ANI
OP CODE
OPERATION
2
2
2
FA
F6
M(R(P)) AND D → D; R(P) + 1 → R(P)
Shift D Right, LSB(D) → DF, 0 → MSB(D)
Shift D Right, LSB(D) → DF, DF → MSB(D)
SHIFT RIGHT
SHR
SHIFT RIGHT WITH CARRY
SHRC
76
(Note 11)
RING SHIFT RIGHT
2
RSHR
76
SHIFT D RIGHT, LSB(D) → DF, DF → MSB(D)
(Note 11)
SHIFT LEFT
2
2
SHL
FE
SHIFT D LEFT, MSB(D) → DF, 0 → LSB(D)
SHIFT D LEFT, MSB(D) → DF, DF → LSB(D)
SHIFT LEFT WITH CARRY
SHLC
7E
(Note 11)
RING SHIFT LEFT
2
RSHL
7E
SHIFT D LEFT, MSB(D) → DF, DF → LSB(D)
(Note 11)
ARITHMETIC OPERATIONS (Note 3)
ADD
2
4
2
4
ADD
DADD
ADI
F4
68F4
FC
M(R(X)) + D → DF, D
DECIMAL ADD
M(R(X)) + D → DF, D DECIMAL ADJUST → DF, D
M(R(P)) + D → DF, D; R(P) + 1 → R(P)
ADD IMMEDIATE
DECIMAL ADD IMMEDIATE
DADI
68FC
M(R(P)) + D → DF, D; R(P) + 1 → R(P)
DECIMAL ADJUST → DF, D
ADD WITH CARRY
2
4
ADC
74
M(R(X)) + D + DF → DF, D
DECIMAL ADD WITH CARRY
DADC
6874
M(R(X)) + D + DF → DF, D
DECIMAL ADJUST → DF, D
ADD WITH CARRY, IMMEDIATE
2
4
ADCI
DACI
7C
M(R(P)) + D + DF → DF, D;
R(P) + 1 → R(P)
DECIMAL ADD WITH CARRY,
IMMEDIATE
687C
M(R(P)) + D + DF → DF, D;
R(P) + 1 → R(P),
DECIMAL ADJUST → DF, D
SUBTRACT D
2
2
SD
F5
M(R(X)) - D → DF, D
SUBTRACT D IMMEDIATE
SDI
FD
M(R(P)) - D → DF, D;
R(P) + 1 → R(P)
SUBTRACT D WITH BORROW
2
2
SDB
75
M(R(X)) - D - (NOT DF) → DF, D
SUBTRACT D WITH BORROW,
IMMEDIATE
SDBI
7D
M(R(P)) - D - (NOT DF) → DF, D;
R(P) + 1 → R(P)
SUBTRACT MEMORY
2
4
2
4
SM
DSM
SMI
F7
68F7
FF
D - M(R(X)) → DF, D
DECIMAL SUBTRACT MEMORY
SUBTRACT MEMORY IMMEDIATE
D - M(R(X)) → DF, D; DECIMAL ADJUST → DF, D
D - M(R(P)) → DF, D; R(P) + 1 → R(P)
DECIMAL SUBTRACT MEMORY,
IMMEDIATE
DSMI
68FF
D - M(R(P)) → DF, D;
R(P) + 1 → R(P),
DECIMAL ADJUST → DF, D
SUBTRACT MEMORY WITH
BORROW
2
4
2
SMB
DSMB
SMBI
77
6877
7F
D - M(R(X)) - (NOT DF) → DF, D
DECIMAL SUBTRACT MEMORY
WITH BORROW
D - M(R(X)) - (NOT DF) → DF, D;
DECIMAL ADJUST → DF, D
SUBTRACT MEMORY WITH
BORROW, IMMEDIATE
D - M(R(P)) - (NOT DF) → DF, D;
R(P) + 1 → R(P)
18
CDP1805AC, CDP1806AC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
NO. OF
MACHINE
INSTRUCTION
CYCLES
MNEMONIC
OP CODE
OPERATION
DECIMAL SUBTRACT MEMORY
WITH BORROW, IMMEDIATE
4
DSBI
687F
D - M(R(P)) - (NOT DF) → DF, D
R(P) + 1 → R(P)
DECIMAL ADJUST → DF, D
BRANCH INSTRUCTIONS - SHORT BRANCH
SHORT BRANCH
2
2
BR
30
M(R(P)) → R(P).0
R(P) + 1 → R(P)
NO SHORT BRANCH (See SKP)
NBR
38
(Note 11)
SHORT BRANCH IF D = 0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
BZ
BNZ
BDF
BPZ
BGE
BNF
BM
32
3A
33
IF D = 0, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
SHORT BRANCH IF D NOT 0
SHORT BRANCH IF DF = 1
SHORT BRANCH IF POS OR ZERO
IF D NOT 0, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
IF DF = 1, M(R(P)) → R(P).0
(Note 11) ELSE R(P) + 1 → R(P)
33 IF DF = 1, M(R(P)) → R(P).0
(Note 11) ELSE R(P) + 1 → R(P)
33 IF DF = 1, M(R(P)) → R(P).0,
SHORT BRANCH IF EQUAL OR
GREATER
(Note 11) ELSE R(P) + 1 → R(P)
SHORT BRANCH IF DF = 0
SHORT BRANCH IF MINUS
SHORT BRANCH IF LESS
SHORT BRANCH IF Q = 1
SHORT BRANCH IF Q = 0
SHORT BRANCH IF EF1 = 1
3B IF D = 0, M(R(P)) → R(P).0,
(Note 11) ELSE R(P) + 1 → R(P)
3B IF D = 0, M(R(P)) → R(P).0,
(Note 11) ELSE R(P) + 1 → R(P)
BL
3B IF D = 0, M(R(P)) → R(P).0,
(Note 11) ELSE R(P) + 1 → R(P)
BQ
31
IF Q = 1, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
BNQ
B1
39
IF Q = 0, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
34
IF EF1 = 1, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
(EF1 = V
)
SS
SHORT BRANCH IF EF1 = 0
(EF1 = V
BN1
B2
3C
35
IF EF1 = 0, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
)
DD
SHORT BRANCH IF EF2 = 1
(EF2 = V
IF EF2 = 1, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
)
SS
SHORT BRANCH IF EF2 = 0
(EF2 = V
BN2
B3
3D
36
IF EF2 = 0, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
)
DD
SHORT BRANCH IF EF3 = 1
(EF3 = V
IF EF3 = 1, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
)
SS
SHORT BRANCH IF EF3 = 0
(EF3 = V
BN3
B4
3E
37
IF EF3 = 0, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
)
DD
SHORT BRANCH IF EF4 = 1
(EF4 = V
IF EF4 = 1, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
)
SS
SHORT BRANCH IF EF4 = 0
(EF4 = V
BN4
BCI
BXI
3F
IF EF4 = 0, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
)
DD
SHORT BRANCH ON COUNTER
INTERRUPT
683E
IF CI = 1, M(R(P)) → R(P).0; 0 → CI
(Note 12) ELSE R(P) + 1 → R(P)
SHORT BRANCH ON EXTERNAL
INTERRUPT
683F
IF XI = 1, M(R(P)) → R(P).0
ELSE R(P) + 1 → R(P)
19
CDP1805AC, CDP1806AC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
NO. OF
MACHINE
INSTRUCTION
CYCLES
MNEMONIC
OP CODE
OPERATION
BRANCH INSTRUCTIONS - LONG BRANCH
LONG BRANCH
3
3
LBR
C0
M(R(P)) → R(P).1, M(R(P) + 1) → R(P).0
R(P) + 2 → R(P)
NO LONG BRANCH (See LSKP)
NLBR
C8
(Note 11)
LONG BRANCH IF D = 0
LONG BRANCH IF D NOT 0
LONG BRANCH IF DF = 1
LONG BRANCH IF DF = 0
LONG BRANCH IF Q = 1
LONG BRANCH IF Q = 0
3
3
3
3
3
3
LBZ
LBNZ
LBDF
LBNF
LBQ
C2
CA
C3
CB
C1
C9
IF D = 0, M(R(P)) → R(P).1
M(R(P) + 1) → R(P).0
ELSE R(P) + 2 → R(P)
IF D NOT 0, M(R(P)) → R(P).1
M(R(P) + 1) → R(P).0
ELSE R(P) + 2 → R(P)
IF DF = 1, M(R(P)) → R(P).1
M(R(P) + 1) → R(P).0
ELSE R(P) + 2 → R(P)
IF DF = 0, M(R(P)) → R(P).1
M(R(P) + 1) → R(P).0
ELSE R(P) + 2 → R(P)
IF Q = 1, M(R(P)) → R(P).1
M(R(P) + 1) → R(P).0
ELSE R(P) + 2 → R(P)
LBNQ
IF Q = 0, M(R(P)) → R(P).1
M(R(P) + 1) → R(P).0
ELSE R(P) + 2 → R(P)
SKIP INSTRUCTIONS
SHORT SKIP (See NBR)
2
3
3
3
3
3
3
3
3
SKP
LSKP
LSZ
38
(Note 11)
R(P) + 1 → R(P)
R(P) + 2 → R(P)
LONG SKIP (See NLBR)
LONG SKIP IF D = 0
LONG SKIP IF D NOT 0
LONG SKIP IF DF = 1
LONG SKIP IF DF = 0
LONG SKIP IF Q = 1
LONG SKIP IF Q = 0
LONG SKIP IF MIE = 1
C8
(Note 11)
CE
C6
CF
C7
CD
C5
CC
IF D = 0, R(P) + 2 → R(P)
ELSE CONTINUE
LSNZ
LSDF
LSNF
LSQ
IF D NOT 0, R(P) + 2 → R(P)
ELSE CONTINUE
IF DF = 1, R(P) + 2 → R(P)
ELSE CONTINUE
IF DF = 0, R(P) + 2 → R(P)
ELSE CONTINUE
IF Q = 1, R(P) + 2 → R(P)
ELSE CONTINUE
LSNQ
LSIE
IF Q = 0, R(P) + 2 → R(P)
ELSE CONTINUE
IF MIE = 1, R(P) + 2 → R(P)
ELSE CONTINUE
CONTROL INSTRUCTIONS
IDLE
2
IDL
00
STOP ON TPB; WAIT FOR DMA OR INTERRUPT;
(Note 14) BUS FLOATS
NO OPERATION
SET P
3
2
2
NOP
SEP
SEX
C4
DN
EN
CONTINUE
N → P
SET X
N → X
20
CDP1805AC, CDP1806AC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
NO. OF
MACHINE
INSTRUCTION
CYCLES
MNEMONIC
SEQ
OP CODE
OPERATION
SET Q
2
2
2
7B
7A
79
1 → Q
0 → Q
RESET Q
REQ
PUSH X, P TO STACK
MARK
(X, P) → T; (X, P) → M(R(2)),
THEN P → X; R(2) → 1→ R(2)
TIMER/COUNTER INSTRUCTIONS
LOAD COUNTER
3
LDC
6806
CNTR STOPPED: D → CH, CNTR;
(Note 15) 0 → CI. CNTR RUNNING; D → CH
GET COUNTER
STOP COUNTER
3
3
GEC
6808
6800
CNTR → D
STPC
STOP CNTR CLOCK;
0 → ÷ 32 PRESCALER
DECREMENT TIMER/COUNTER
SET TIMER MODE AND START
3
3
3
DTC
STM
6801
6807
6805
CNTR - 1 → CNTR
TPA ÷ 32 → CNTR
EF1 → CNTR CLOCK
SET COUNTER MODE 1 AND
START
SCM1
SET COUNTER MODE 2 AND
START
3
3
3
3
SCM2
SPM1
SPM2
ETQ
6803
6804
6802
EF2 → CNTR CLOCK
SET PULSE WIDTH MODE 1 AND
START
TPA.EF1 → CNTR CLOCK;
EF1
STOPS COUNT
SET PULSE WIDTH MODE 2 AND
START
TPA.EF2 → CNTR CLOCK;
EF2 STOPS COUNT
ENABLE TOGGLE Q
6809
IF CNTR = 01 • NEXT CNTR CLOCK
; Q → Q
(Note 15)
INTERRUPT CONTROL
EXTERNAL INTERRUPT ENABLE
EXTERNAL INTERRUPT DISABLE
COUNTER INTERRUPT ENABLE
COUNTER INTERRUPT DISABLE
RETURN
3
3
3
3
2
2
2
6
XIE
XID
680A
680B
680C
680D
70
1 → XIE
0 → XIE
CIE
l → CIE
CID
0 → CIE
RET
DIS
M(R(X)) → X, P; R(X) + 1 → R(X); 1 → MIE
M(R(X) → X, P; R(X) + 1 → R(X); 0 → MIE
T → M(R(X))
DISABLE
71
SAVE
SAV
DSAV
78
SAVE T, D, DF
6876
R(X) - 1 → R(X), T → M(R(X)),
(Note 10) R(X) - 1 → R(X), D → M (R(X)),
R(X) - 1 → R(X), SHIFT D
RIGHT WITH CARRY, D → M(R(X))
INPUT-OUTPUT BYTE TRANSFER
OUTPUT 1
2
2
2
2
2
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
61
62
63
64
65
M(R(X)) → BUS; R(X) + 1 → R(X)
N LINES = 1
OUTPUT 2
OUTPUT 3
OUTPUT 4
OUTPUT 5
M(R(X)) → BUS; R(X) + 1 → R(X)
N LINES = 2
M(R(X)) → BUS; R(X) + 1 → R(X)
N LINES = 3
M(R(X)) → BUS; R(X) + 1 → R(X)
N LINES = 4
M(R(X)) → BUS; R(X) + 1 → R(X)
N LINES = 5
21
CDP1805AC, CDP1806AC
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
NO. OF
MACHINE
INSTRUCTION
CYCLES
MNEMONIC
OP CODE
OPERATION
OUTPUT 6
OUTPUT 7
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT 5
INPUT 6
INPUT 7
2
OUT 6
66
M(R(X)) → BUS; R(X) + 1 → R(X)
N LINES = 6
2
2
2
2
2
2
2
2
OUT 7
INP 1
INP 2
INP 3
INP 4
INP 5
INP 6
INP 7
67
69
6A
6B
6C
6D
6E
6F
M(R(X)) → BUS; R(X) + 1 → R(X)
N LINES = 7
BUS → M(R(X)); BUS → D
N LINES = 1
BUS → M(R(X)); BUS → D
N LINES = 2
BUS → M(R(X)); BUS → D
N LINES = 3
BUS → M(R(X)); BUS → D
N LINES = 4
BUS → M(R(X)); BUS → D
N LINES = 5
BUS → M(R(X)); BUS → D
N LINES = 6
BUS → M(R(X)); BUS → D
N LINES = 7
CALL AND RETURN
STANDARD CALL
10
SCAL
SRET
688N
R(N).0 → M(R(X));
(Note 10) R(N).1 → M(R(X) - 1);
R(X) - 2 → R(X); R(P) → R(N);
THEN M(R(N)) → R(P).1;
M(R(N) + 1) → R(P).0;
R(N) + 2 → R(N)
STANDARD RETURN
NOTES:
8
689N
R(N) → R(P);
(Note 10) M(R(X) + 1) → R(N).1;
M(R(X) + 2) → R(N).0; R(X) + 2 → R(X)
10. Previous contents of T register are destroyed during instruction execution.
11. This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
12. ETQ cleared by LDC with the Counter/Timer stopped, reset of CPU, or BCl • (Cl = 1).
13. Cl = Counter Interrupt, Xl = External Interrupt.
14. An IDLE instruction initiates an S1 cycle. All external signals, except the oscillator, are stopped on the low-to-high transition of TPB. All
outputs remain in their previous states, MRD, MWR, are set to a logic ‘1’ and the data bus floats. The processor will continue to IDLE
until an I/O request (INTERRUPT, DMA-IN, or DMA-OUT) is activated. When the request is acknowledged, the IDLE cycle is terminated
and the I/O request is serviced, and the normal operation is resumed. (To respond to an lNTERRUPT during an IDLE, MlE and either
ClE or XlE must be enabled).
15. Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch + 2 execute).
Long-Branch instructions are three bytes long. The first byte specifies the condition to be tested; and the second and third byte, the
branching address.
The long branch instruction can:
a. Branch unconditionally
b. Test for D = 0 or D ≠ 0
c. Test for DF = 0 or DF = 1
d. Test for Q = 0 or Q = 1
e. Effect an unconditional no branch
If the tested condition is met, then branching takes place; the branching address bytes are loaded in the high-and-low-order bytes of the
current program counter, respectively. This operation effects a branch to any memory location.
If the tested condition is not met, the branching address bytes are skipped over, and the next instruction in sequence is fetched and exe-
cuted. This operation is taken for the case of unconditional no branch (NLBR).
22
CDP1805AC, CDP1806AC
16. The short-branch instructions are two or three bytes long. The first byte specifies the condition to be tested, and the second specifies the
branching address, except for the branches on interrupt. For those, the first two bytes specify the condition to be tested and the third byte
specifies the branching address.
The short branch instruction can:
a. Branch unconditionally
b. Test for D = 0 or D ≠ 0
c. Test for DF = 0 or DF = 1
d. Test for Q = 0 or Q = 1
e. Test the status (1 or 0) of the four EF flags
f. Effect an unconditional no branch
g. Test for counter or external interrupts (BCI, BXI)
If the tested condition is met, then branching takes place; the branching address byte is loaded into the low-order byte position of the
current program counter. This effects a branch within the current 256-byte page of the memory, i.e., the page which holds the branching
address. If the tested condition is not met, the branching address byte is skipped over, and the next instruction in sequence is fetched
and executed. This same action is taken in the case of unconditional no branch (NBR).
17. The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP) and eight Long-Skip instructions.
The Unconditional Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute). Its action is to skip over the byte following it.
Then the next instruction in sequence is fetched and executed. This SKP instruction is identical to the unconditional No-Branch Instruc-
tion (NBR) except that the skipped-over byte is not considered part of the program.
The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute).
They can:
a. Skip unconditionally
b. Test for D = 0 or D ≠ 0
c. Test for DF = 0 or DF = 1
d. Test for Q = 0 or Q = 1
e. Test for MIE = 1
If the tested condition is met, then Long Skip takes place; the current program counter is incremented twice. Thus, two bytes are
skipped over and the next instruction in sequence is fetched and executed. If the tested condition is not met, then no action is taken.
Execution is continued by fetching the next instruction in sequence.
18. Instruction 6800 through 68FF take a minimum of 3 machine cycles and up to a maximum of 10 machine cycles. In all cases, the first two
cycles are fetches and subsequent cycles are executes. The first byte (68) of these two-byte op codes is used to generate the second
fetch, the second byte is then interpreted differently than the same code without the 68 prefix. DMA and INT requests are not serviced
until the end of the last execute cycle.
19. Arithmetic Operations:
The arithmetic and shift operations are the only instructions that can alter the content of DF. The syntax ‘(NOT DF)’ denotes the subtrac-
tion of the borrow.
Binary Operations:
After an ADD instruction
DF = 1 denotes a carry has occurred. Result is greater than FF
DF = 0 denotes a carry has not occurred.
After a SUBTRACT instruction
.
16
DF = 1 denotes no borrow. D is a true positive number.
DF = 0 denotes a borrow. D is in two's complement form.
Binary Coded Decimal Operations:
After a BCD ADD instruction
DF = 1 denotes a carry has occurred. Result is greater than 99
DF = 0 denotes a carry has not occurred.
.
10
After a BCD SUBTRACT instruction
DF = 1 denotes no borrow. D is a true positive decimal number.
Example
99
-88
11
D
M(R(X))
D
DF = 1
DF = 0 denotes a borrow. D is in ten's complement form.
Example
88
-99
89
D
M(R(X))
D
DF = 0
89 is the ten's complement of 11, which is the correct answer (with a minus value denoted by DF = 0).
23
CDP1805AC, CDP1806AC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES
DATA
BUS
MEMORY
ADDRESS MRD MWR LINES
N
STATE
I
N
MNEMONIC
OPERATION
S1
RESET
0 → Q, I, N, COUNTER,
PRESCALER, CIL;
1 → CIE, XIE
00
UNDE-
FINED
1
1
1
1
0
0
S1
INITIALIZE, NOT PROGRAMMER AC- X, P → T THEN
00
(Note 20)
UNDE-
FINED
CESSIBLE
FETCH
0
0 → X, P; 1 → MIE, 0000 → R0
S0
S1
MRP → I, N; RP + 1 → RP
MRP
RP
RO
0
1
1
1
0
0
0
IDL
STOP AT TPB
HIGH Z
WAIT FOR DMA OR INT
S1
S1
S1
S1
0
1
2
3
1-F
0-F
0-F
0-F
LDN
INC
MRN → D
MRN
HIGH Z
HIGH Z
MRP
RN
RN
RN
RP
0
1
1
0
1
1
1
1
0
0
0
0
RN + 1 → RN
RN - 1 → RN
DEC
SHORT
TAKEN: MRP → RP.0
BRANCH
NOT TAKEN: RP + 1 → RP
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
4
5
6
6
6
6
6
6
6
6
6
0-F
0-F
0
LDA
STR
MRN → D; RN + 1 → RN
D → MRN
MRN
D
RN
RN
RX
RX
RX
RX
RX
RX
RX
RX
RX
0
1
1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
1
2
3
4
5
6
7
1
IRX
RX + 1 → RX
MRX
MRX
MRX
MRX
MRX
MRX
MRX
MRX
1
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
INP 1
MRX → BUS; RX + 1 → RX
MRX → BUS; RX + 1 → RX
MRX → BUS; RX + 1 → RX
MRX → BUS; RX + 1 → RX
MRX → BUS; RX + 1 → RX
MRX → BUS; RX + 1 → RX
MRX → BUS; RX + 1 → RX
BUS → MRX, D
2
3
4
5
6
7
9
DATA
FROM
I/O
DEVICE
S1
S1
S1
S1
6
6
6
6
A
B
C
D
INP 2
INP 3
INP 4
INP 5
BUS → MRX, D
BUS → MRX, D
BUS → MRX, D
BUS → MRX, D
DATA
FROM
I/O
RX
RX
RX
RX
1
1
1
1
0
0
0
0
2
3
4
5
DEVICE
DATA
FROM
I/O
DEVICE
DATA
FROM
I/O
DEVICE
DATA
FROM
I/O
DEVICE
24
CDP1805AC, CDP1806AC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)
DATA
BUS
MEMORY
ADDRESS MRD MWR LINES
N
STATE
I
N
MNEMONIC
OPERATION
BUS → MRX, D
S1
6
E
INP 6
DATA
FROM
I/O
RX
RX
1
1
0
0
6
DEVICE
S1
6
F
INP 7
BUS → MRX, D
DATA
FROM
I/O
7
DEVICE
S1
S1
7
7
0
1
RET
DIS
MRX → X, P; RX + 1 → RX
1 → MIE
MRX
RX
RX
0
0
1
1
0
0
MRX → X, P; RX + 1 → RX
0 → MIE
MRX
S1
S1
S1
S1
S1
S1
S1
S1
7
7
7
7
7
7
7
7
2
3
4
5
6
7
8
9
LDXA
STXD
ADC
MRX → D; RX + 1 → RX
D → MRX; RX - 1 → RX
MRX + D + DF → DF, D
MRX - D - DFN → DF, D
LSB(D) → DF; DF → MSB(D)
D - MRX - DFN → DF, D
T → MRX
MRX
D
RX
RX
RX
RX
RX
RX
RX
R2
0
1
0
0
1
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
MRX
MRX
HIGH Z
MRX
T
SDB
SHRC
SMB
SAV
MARK
X, P → T, MR2; P → X
R2 - 1 → R2
T
S1
S1
7
7
7
7
7
7
8
9
A
B
C
A
B
REQ
SEQ
ADCI
SDBI
SHLC
SMBI
GLO
GHI
0 → Q
HIGH Z
HIGH Z
MRP
MRP
HIGH Z
MRP
RN.0
RN.1
D
RP
RP
RP
RP
RP
RP
RN
RN
RN
RN
RP
1
1
0
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1 → Q
S1
C
MRP + D + DF → DF, D; RP + 1
MRP - D - DFN → DF, D; RP + 1
MSB(D) → DF; DF → LSB D
D - MRP - DFN → DF, D; RP + 1
RN.0 → D
S1
D
S1
E
S1
F
S1
0-F
0-F
0-F
0-F
S1
RN.1 → D
S1
PLO
PHI
D → RN.0
S1
D → RN.1
D
S1#1
0-3,
8-B
LONG
BRANCH
TAKEN: MRP → B; RP + 1 → RP
MRP
#2
S1#1
#2
C
C
C
C
C
0-3,
8-B
LONG
BRANCH
TAKEN: B → RP.1; MRP →
RP.0
M(RP + 1)
MRP
RP + 1
RP
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0-3,
8-B
LONG
BRANCH
NOT TAKEN RP + 1 → RP
NOT TAKEN RP + 1 → RP
TAKEN: RP + 1 → RP
0-3,
8-B
LONG
BRANCH
M(RP + 1)
MRP
RP + 1
RP
S1#1
#2
5
LONG
SKIP
6
LONG
SKIP
TAKEN: RP + 1 → RP
M(RP + 1)
RP + 1
25
CDP1805AC, CDP1806AC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)
DATA
BUS
MEMORY
ADDRESS MRD MWR LINES
N
STATE
I
N
MNEMONIC
OPERATION
#2
C
7
LONG
SKIP
TAKEN: RP + 1 → RP
M(RP + 1)
RP + 1
RP
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
S1#1
S1#1
#2
C
C
C
C
C
D
E
F
LONG
SKIP
NOT TAKEN: NO OPERATION
NOT TAKEN: NO OPERATION
NOT TAKEN: NO OPERATION
NOT TAKEN: NO OPERATION
MRP
LONG
SKIP
MRP
RP
LONG
SKIP
M(RP + 1)
M(RP + 1)
RP + 1
RP + 1
S1#1
LONG
SKIP
S1#1
#2
C
4
NOP
NOP
SEP
SEX
LDX
OR
NO OPERATION
MRP
M(RP + 1)
NN
RP
RP + 1
RN
RN
RX
RX
RX
RX
RX
RX
RX
RX
RP
RP
RP
RP
RP
RP
RP
RP
R0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
4
NO OPERATION
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S2
D
0-F
N → P
E
0-F
N → X
NN
F
0
MRX → D
MRX
MRX
MRX
MRX
MRX
MRX
MRX
HIGH Z
MRP
MRP
MRP
MRP
MRP
MRP
MRP
HIGH Z
F
1
MRX OR D → D
F
2
AND
XOR
ADD
SD
MRX AND D → D
F
3
MRX XOR D → D
F
4
MRX + D → DF, D
F
5
MRX - D → DF, D
F
7
SM
D - MRX → DF; D
F
6
SHR
LDI
LSB(D) → DF; 0 → MSB(D)
MRP → D; RP + 1 → RP
MRP OR D → D; RP + 1 → RP
MRP AND D → D; RP + 1 → RP
MRP XOR D → D; RP + 1 → RP
MRP + D → DF, D; RP + 1 → RP
MRP - D → DF, D; RP + 1 → RP
D - MRP → DF, D; RP + 1 → RP
MSB(D) → DF; 0 → LSB(D)
BUS → MR0; R0 + 1 → R0
F
8
F
9
ORI
ANI
F
A
F
B
XRI
F
C
ADI
F
D
SDI
F
F
F
E
SMI
SHL
DMA IN
DMA IN
DMA IN
DATA
FROM I/O
DEVICE
S2
S3
DMA OUT
DMA
OUT
DMA OUT
MRO → BUS; R0 + 1 → R0
MR0
R0
0
1
1
1
0
0
INTER-
RUPT
INTER-
RUPT
INTERRUPT X, P → T; 0 → MIE
1 → P; 2 → X
HIGH Z
RN
THE FOLLOWING ARE ALL LINKED INSTRUCTIONS “68” PRECEEDS ALL OP CODES, SO THERE IS A DUPLICATE FETCH
S1
0
0
STPC
STOP COUNTER CLOCK;
0 → ÷ 32 PRESCALER
HIGH Z
R0
1
1
0
0
S1
0
1
DTC
CNTR - 1 → CNTR
HIGH Z
R1
1
1
26
CDP1805AC, CDP1806AC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)
DATA
BUS
MEMORY
ADDRESS MRD MWR LINES
N
STATE
S1
I
N
2
3
4
5
6
MNEMONIC
SPM2
OPERATION
0
0
0
0
0
CNTR - 1 ON EF2 AND TPA
CNTR - 1 ON EF2 0 TO 1
CNTR - 1 ON EF1 AND TPA
CNTR - 1 ON EF1 0 TO 1
HIGH Z
HIGH Z
HIGH Z
HIGH Z
D
R2
R3
R4
R5
R6
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
S1
SCM2
S1
SPM1
S1
SCM1
S1
LDC
CNTR STOPPED: D → CH,
CNTR; 0 → CI
CNTR RUNNING: D → CH
S1
S1
0
0
0
0
0
0
0
2
2
2
7
8
STM
GEC
ETQ
XIE
CNTR - 1 ON TPA ÷ 32
CNTR → D
HIGH Z
CNTR
R7
R8
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
S1
9
IF CNTR THRU 0: Q → Q
1 → XIE
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
MRP
R9
S1
A
RA
S1
B
XID
0 → XIE
RB
S1
C
CIE
1 → CIE
RC
S1
D
CID
0 → CIE
RD
S1#1
#2
0-F
0-F
0-F
DBNZ
DBNZ
DBNZ
RN - 1 → RN
RN
MRP → B; RP + 1 → RP
RP
#3
TAKEN: B → RP.1, MRP →
RP.0
M(RP + 1)
RP + 1
NOT TAKEN: RP + 1 → RP
S1
S1
3
3
E
F
BCI
BXI
TAKEN: MRP → RP.0;
0 → CI
NOT TAKEN: RP + 1 → RP
MRP
RP
RP
0
0
1
1
0
0
TAKEN: MRP → RP.0
NOT TAKEN: RP + 1 → RP
MRP
MRX
S1#1
#2
6
6
6
7
7
7
7
7
0-F
0-F
0-F
4
RLXA
RLXA
RLXA
DADC
DADC
DSAV
DSAV
DSAV
MRX → B, RX + 1 → RX
RX
RX + 1
RN
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
0
B → T; MRX → B; RX + 1 → RX M(RX + 1)
#3
B, T → RN.0, RN.1
HIGH Z
MRX
HIGH Z
HIGH Z
T
S1#1
#2
MRX + D + DF → DF, D
DECIMAL ADJUST → DF, D
RX - 1 → RX
RX
4
RD
S1#1
#2
6
RP
6
T → MRX; RX - 1 → RX
RX - 1
RX - 2
#3
6
D → MRX; RX - 1 → RX
D
SHIFT D RIGHT WITH CARRY
#4
S1#1
#2
7
7
7
7
6
7
DSAV
DSMB
DSMB
DACI
D → MRX
D
RX - 3
RX
1
0
1
0
0
1
1
1
0
0
0
0
D - MRX - (NOT DF) → DF, D
DECIMAL ADJUST → DF, D
MRX
7
HIGH Z
MRP
RP
S1#1
C
MRP + D + DF → DF, D;
RP + 1 → RP
RP
#2
7
7
C
F
DACI
DSBI
DECIMAL ADJUST → DF, D
HIGH Z
MRP
RP + 1
RP
1
0
1
1
0
0
S1#1
D - MRP - (NOT DF) → DF, D;
RP + 1 → RP
27
CDP1805AC, CDP1806AC
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)
DATA
BUS
MEMORY
ADDRESS MRD MWR LINES
N
STATE
#2
I
N
MNEMONIC
DSBI
OPERATION
DECIMAL ADJUST → DF, D
RN.0, RN.1 → T, B
7
8
8
8
8
8
8
8
8
9
9
9
9
9
9
A
A
A
B
B
C
C
C
F
HIGH Z
HIGH Z
RN.0
RP + 1
RN
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S1#1
#2
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
0-F
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SRET
SRET
SRET
SRET
SRET
SRET
RSXD
RSXD
RSXD
RNX
T→ MRX RX - 1 → RX
B → MRX RX - 1 → RX
RP.0, RP.1 → T, B
RX
#3
RN.1
RX - 1
RP
#4
HIGH Z
HIGH Z
MRP
#5
B, T → RN.1, RN.0
RN
#6
MRN → B; RN + 1 → RN
RP
#7
B → T; MRN → B; RN + 1 → RN M(RP + 1)
RP + 1
RP
#8
B, T → RP.0, RP.1
RN.0, RN.1 → T, B
RX + 1 → RX
HIGH Z
HIGH Z
HIGH Z
HIGH Z
M(RX + 1)
M(RX + 1
HIGH Z
HIGH Z
RN.0
S1#1
#2
RN
RX
#3
B, T → RP.1, RP.0
MRX → B; RX + 1 → RX
B → T; MRX → B
RP
#4
RX + 1
RX + 2
RN
#5
#6
B, T → RN.0, RN.1
RN.0, RN.1 → T, B
T → MRX; RX - 1 → RX
B → MRX; RX - 1 → RX
RN.0, RN.1 → T, B
B, T → RX.1, RX.0
MRP → B; RP + 1 → RP
S1#1
#2
RN
RX
#3
RN.1
RX - 1
RN
S1#1
#2
HIGH Z
HIGH Z
MRP
RNX
RX
S1#1
#2
RLDI
RP
RLDI
B → T; MRP → B; RP + 1 → RP M(RP + 1)
RP + 1
RN
#3
RLDI
B, T → RN.0, RN.1;`
RP + 1 → RP
HIGH Z
S1#1
#2
F
F
F
F
F
4
4
7
7
C
DADD
DADD
DSM
MRX + D → DF; D
MRX
HIGH Z
MRX
RX
RP
RX
RP
RP
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
DECIMAL ADJUST → DF, D
D - MRX → DF, D
S1#1
#2
DSM
DECIMAL ADJUST → DF, D
HIGH Z
MRP
S1#1
DADI
MRP + D → DF, D;
RP + 1 → RP
#2
F
F
C
F
DADI
DSMI
DECIMAL ADJUST → DF, D
HIGH Z
MRP
RP + 1
RP
1
0
1
1
0
0
S1#1
D - MRP → DF, D
RP + 1 → RP
#2
F
F
DSMI
DECIMAL ADJUST → DF, D
HIGH Z
RP + 1
1
1
0
NOTE:
20. Data bus floats for first 2-1/2 clocks of the nine clock initialization cycle; all zeros for remainder of cycle.
28
CDP1805AC, CDP1806AC
INSTRUCTION SUMMARY
N
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IDL
LDN
INC
DEC
SKP
LDA
STR
†
BR
BQ
DIS
BZ
BDF
B1
B2
B3
B4
BNQ
BNZ
BNF
BN1
INP
BN2
BN3
BN4
IRX
OUT
RET
LDXA STXD ADC
SDB SHRC SMB
SAV MARK REQ SEQ ADCI SDBI SHLC SMBI
GLO
GHI
PLO
PHI
LBR
LDX
LBQ
OR
LBZ LBDF NOP LSNQ LSNZ LSNF LSKP LBNQ LBNZ LBNF LSIE
LSQ
LSZ LSDF
SEP
SEX
AND
XOR
ADD
SD
SHR
SM
LDI
ORI
ANI
XRI
ADI
CIE
-
SDI
SHL
SMI
-
‘68’ LINKED OPCODES (DOUBLE FETCH)
0
2
3
6
7
8
9
A
B
C
F
STPC DTC SPM2 SCM2 SPM1 SCM1 LDC
STM
-
GEC
DBNZ
-
ETQ
XIE
XID
CID
-
BCI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BXI
DSBI
RLXA
-
DADC
DSAV DSMB
DACI
SCAL
SRET
RSXD
RNX
RLDI
-
-
-
-
-
DADD
-
-
DSM
-
-
-
DADI
-
-
DSMI
†‘68’ is used as a linking OPCODE for the double fetch instructions.
29
CDP1805AC, CDP1806AC
Operating and Handling Considerations
Handling
Input Signals
All inputs and outputs of Intersil CMOS devices have a net- To prevent damage to the input protection circuit, input sig-
work for electrostatic protection during handling.
Operating
nals should never be greater than V
Input currents must not exceed 10mA even when the power
supply is off.
nor less than V .
SS
DD
Operating Voltage
Unused Inputs
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
A connection must be provided at every input terminal. All
unused input terminals must be connected to either V
or
DD
V
, whichever is appropriate.
SS
ground noise; any of these conditions must not cause V
-
DD
V
to exceed the absolute maximum rating.
Output Short Circuits
SS
Shorting of outputs to V
or V may damage CMOS
SS
DD
devices by exceeding the maximum device dissipation.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
30
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