CDP18243 [INTERSIL]
High-Reliability CMOS 32-Word x 8-Bit Static Random-Access Memory; 高可靠性的CMOS 32字×8位的静态随机存取存储器
| 型号： | CDP18243 |
| 厂家： | 
Intersil |
| 描述： | High-Reliability CMOS 32-Word x 8-Bit Static Random-Access Memory |
| 文件： | 总5页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
CDP1824/3,
CDP1824C/3
High-Reliability CMOS 32-Word x 8-Bit
Static Random-Access Memory
March 1997
Features
Description
• Access Time
- 610ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . at V
The CDP1824/3 and CDP1824C/3 types are high-reliability
CMOS 32-word x 8-bit fully static random-access memories
for use in CDP1800-series microprocessor systems. These
parts are compatible with the CDP1802 microprocessor and
will interface directly without additional components.
= 5V
DD
= 10V
- 320ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . at V
DD
• No Precharge or Clock Required
The CDP1824/3 is fully decoded and does not require a pre-
charge or clocking signal for proper operation. It has com-
mon input and output and is operated from a single voltage
supply. The MRD signal (output disable control) enables the
three-state output drivers, and overrides the MWR signal. A
CS input is provided for memory expansion.
Ordering Information
PACK-
PKG.
NO.
5V
10V
AGE
TEMP. RANGE
o
CDP1824CD3 CDP1824D3 SBDIP
-55 C to
D18.3
o
+125 C
The CDP1824C/3 is functionally identical to the CDP1824/3.
The CDP1824/3 has a recommended operating voltage
range of 4V to 10.5V, and the CDP1824C/3 has an operating
voltage range of 4V to 6.5V.
Pinout
Functional Diagram
CDP1824/3, CDP1824C/3 (SBDIP)
MA4
MA3
TOP VIEW
2
1
3
MA2
MA4
MA3
1
2
3
4
5
6
7
8
9
18 V
DD
32 X 8-BIT
ARRAY
ADDRESS
DECODER
4
MA1
17 MWR
16 MRD
15 CS
5
MA0
MA2
MA1
SENSE
AMPL
MA0
14 BUS0
13 BUS1
12 BUS2
11 BUS3
10 BUS4
BUS7
BUS6
BUS5
16
17
MRD
MWR
V
SS
I/O BUFFERS
15
CS
6
7
8
10 11 12 13 14
V
= 18
= 9
DD
V
SS
BUS BUS BUS BUS BUS BUS BUS BUS
7
6
5
4
3
2
1
0
OPERATIONAL MODES
FUNCTION
READ
CS
0
MRD
MWR
DATA PINS STATUS
Output: High/Low Dependent on Data
Input: Output Disabled
0
1
X
1
X
0
X
1
WRITE
0
Not Selected
Standby
1
Output Disabled: High-Impedance State
Output Disabled: High-Impedance State
0
Logic 1 = High Logic 0 = Low X = Don’t Care
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
File Number 1717.2
Copyright © Intersil Americas Inc. 2001. All Rights Reserved
42
CDP1824/3, CDP1824C/3
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
(All Voltages Referenced to V Terminal)
CDP1824/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1824C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
)
Thermal Resistance (Typical, Note 1)
SBDIP Package. . . . . . . . . . . . . . . . . .
Device Dissipation Per Output Transistor
θ
( C/W)
θ
( C/W)
DD
JA
JC
75
20
SS
T
= Full Package Temperature Range
A
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
+0.5V
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
DD
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range (T )
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
A
o
o
o
o
Storage Temperature Range (T
) . . . . . . . . . . .-65 C to +150 C
STG
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
o
from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C
T = Full Package-Temperature Range. For maximum reliability, nominal operating
A
Recommended Operating Conditions
conditions should be selected so that operation is always within the following ranges:
LIMITS
CDP1824/3
CDP1824C/3
MIN MAX
6.5
PARAMETER
DC Operating Voltage Range
Input Voltage Range
MIN
MAX
UNITS
4
10.5
4
V
V
V
V
V
V
DD
SS
DD
SS
Static Electrical Specifications
CONDITIONS
LIMITS
o
o
o
-55 C, +25 C
+125 C
MAX
V
(V)
V
(V)
V
DD
(V)
O
IN
PARAMETER
SYMBOL
MIN
MAX
MIN
UNITS
µA
µA
V
Quiescent Device Current
(Note 1)
I
-
0, 5
5
-
50
500
0.1
0.1
-
-
500
1000
0.2
0.2
-
DD
-
0, 10
0, 5
10
5
-
-
Output Voltage Low-Level
(Note 2)
V
-
-
-
-
OL
10
5
-
-
V
Output Voltage High-Level
(Note 2)
V
-
0, 5
-
4.9
4.8
V
OH
-
10
5
9.9
-
4.8
-
V
Input Low Voltage
V
0.5, 4.5
1, 9
0.5, 4.5
1, 9
0.4
0.5
4.6
9.5
-
-
-
1.5
3
-
1.5
-
V
IL
-
10
5
-
V
Input High Voltage
V
-
3.5
7
4
4
-
-
3.5
-
V
IH
-
10
5
-
7
-
V
Output Low Drive (Sink)
Current
I
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
(Note 2)
(Note 2)
-
1.5
-
mA
mA
mA
mA
µA
µA
µA
µA
pF
pF
OL
10
5
-
2.9
-
Output High Drive (Source)
Current
I
-1
-2
±1
±1
±2
±2
10
15
-
-
-
-
-
-
-
-
-0.75
-1.5
±5
±5
±5
±5
10
15
OH
10
5
-
Input Current
I
Any
Input
-
IN
10
5
-
Three-State Output
Leakage Current
I
0, 5
-
OUT
0, 10
10
-
Input Capacitance
Output Capacitance
NOTES:
C
-
IN
C
-
OUT
1. The CDP1824C/3 meets all 5V Static Electrical Characteristics of the CDP1824/3 except Quiescent Device Current for which the limits
o
o
o
are I
= 200µA at +25 C/-55 C; I = 1000µA at +125 C.
DD
DD
2. Guaranteed, but not tested.
43
CDP1824/3, CDP1824C/3
Read Cycle Dynamic Electrical Specifications Input t , t ≤ 15ns, C = 50pF
R
F
L
LIMITS
TEST
CONDITIONS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
SYMBOL
(V)
MIN
MAX
MIN
MAX
UNITS
ns
Access Time From Address Change
t
5
-
-
-
-
-
-
610
320
610
320
610
320
-
-
-
-
-
-
825
375
825
375
825
375
AA
10
5
ns
Access Time From Chip Select
Output Active From MRD
t
ns
DOA
10
5
ns
t
ns
AM
10
ns
t
AM
(NOTE 1)
MRD
MA
t
AA
CS
t
DOA
(NOTE 1)
DATA OUT
HIGH IMPEDANCE
NOTE:
1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.
FIGURE 1. READ CYCLE TIMING DIAGRAM
44
CDP1824/3, CDP1824C/3
Write Cycle Dynamic Electrical Specifications Input t , t ≤ 15ns, C = 50pF
R
F
L
LIMITS
TEST
CONDITIONS
o
o
o
-55 C, +25 C
+125 C
V
(NOTE 1)
(NOTE 1)
DD
PARAMETER
Write Pulse Width
SYMBOL
(V)
MIN
350
180
400
190
70
MAX
MIN
475
220
560
260
90
MAX
UNITS
ns
t
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WRW
10
5
ns
Data Setup Time
Data Hold Time
Chip Select Setup Time
Address Setup Time
NOTE:
t
ns
DS
DH
10
5
ns
t
ns
10
5
35
45
ns
t
550
340
550
340
775
475
775
475
ns
CS
AS
10
5
ns
t
ns
10
ns
1. Time required by a device to allow for the indicated function.
MA
CS
t
AS
t
CS
t
WRW
MWR
BUS
t
t
DH
DS
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
45
CDP1824/3, CDP1824C/3
o
Data Retention Specifications At T = +25 C
A
LIMITS
TEST
CONDITIONS
CDP1824/3
CDP1824C/3
V
DR
(V)
V
DD
(V)
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
V
Data Retention Voltage
V
-
-
-
2.5
-
-
10
-
2.5
-
40
-
DR
Data Retention Quiescent Current
Chip Deselect to Data Retention Time
I
2.5
2.5
2.5
2.5
2.5
-
600
-
µA
ns
DD
t
5
600
300
600
300
CDR
10
5
-
-
ns
Recovery to Normal Operation Time
t
-
600
-
-
ns
RC
10
-
-
ns
DATA RETENTION
MODE
0.95 V
DD
0.95 V
F
V
DD
DD
V
DD
t
CDR
t
t
t
RC
F
(NOTE 1)
(NOTE 1)
V
V
IH
IH
CS
V
V
IL
IL
NOTE: t , t > 1µs.
r
f
FIGURE 3. LOW V
DATA RETENTION WAVEFORMS AND TIMING DIAGRAM
DD
Static Burn-In Circuit
V
DD
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
DD
V
SS
V
SS
All Resistors 47kΩ (±±20%)
TYPE
V
TEMPERATURE
TIME
DD
o
CDP1824
11V
7V
+125 C
160 Hrs., Min.
160 Hrs., Min.
o
CDP1824C
+125 C
46
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