CDP1853C [INTERSIL]
High-Reliability CMOS N-Bit 1 of 8 Decoder; 高可靠性的CMOS N位的8解码器1
| 型号： | CDP1853C |
| 厂家： | 
Intersil |
| 描述： | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| 文件： | 总7页 (文件大小：39K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDP1853C/3
High-Reliability CMOS N-Bit 1 of 8 Decoder
March 1997
Features
Description
• Provides Direct Control of Up to 7 Input and 7 Output The CDP1853/3 and CDP1853C/3 are high-reliability 1 of 8
Devices When used with a CDP1800-Series Micropro- decoders designed for use in general purpose microproces-
cessor
sor systems. These devices, which are functionally identical,
are specifically designed for use as gated N-bit decoders
and interface directly with the 1800-Series microprocessors
without additional components. The CDP1853/3 has a rec-
ommended operating voltage range of 4V to 10.5V, and the
CDP1853C/3 has a recommended operating voltage range
of 4V to 6.5V.
• CHIP ENABLE (CE) Allows Easy Expansion for Multi-
level I/O Systems
Ordering Information
When CHIP ENABLE (CE) is high, the selected output will be
true (high) from the trailing edge of CLOCK A (high-to-low
transition) to the trailing edge of CLOCK B (high-to-low
transition). All outputs will be low when the device is not
selected (CE = 0) and during conditions of CLOCK A and
CLOCK B as shown in Figure 2. The CDP1853/3 inputs N0,
N1, N2, CLOCK A, and CLOCK B are connected to 1800-
series microprocessor outputs N0, N1, N2, TPA, and TPB
respectively, when used to decode I/O commands as shown
in Figure 5. The CHIP ENABLE (CE) input provides the capa-
bility for multiple levels of decoding as shown in Figure 6.
PKG.
NO.
PACKAGE TEMP. RANGE
5V
10V
o
o
SBDIP
-55 C to +125 C CDP1853CD3
-
D16.3
The CDP1853/3 can also be used as a general purpose 1 of
8 decoder for I/O and memory system applications as shown
in Figure 4.
Pinout
16 LEAD SBDIP
TOP VIEW
CLK A
N0
1
16 V
DD
2
3
4
5
6
7
8
15 CLK B
14 N2
N1
OUT 0
OUT 1
OUT 2
OUT 3
13 CE
12 OUT 4
11 OUT 5
10 OUT 6
9
OUT 7
V
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1713.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-40
CDP1853/3, CDP1853C/3
TRUTH TABLE
CDP1853/3 Functional Diagram
CE
CL A
CL B
EN
4
OUT 0
1
0
0
1
1
X
0
1
0
1
X
Qn-1(Note 2)
2
5
N0
OUT 1
1
1
1
0
1
0
1
0
6
7
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
3
1 OF 8
N1
12
11
10
9
DECODER
14
N2
EN
N2
0
N1
0
N0
0
EN
1
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
2
0
0
1
0
0
0
0
0
0
3
0
0
0
1
0
0
0
0
0
4
0
0
0
0
1
0
0
0
0
5
0
0
0
0
0
1
0
0
0
6
0
0
0
0
0
0
1
0
0
7
0
0
0
0
0
0
0
1
0
13
CE
1
0
0
1
1
0
1
0
1
QN
0
1
1
1
CLOCK
A
(TPA)
1
0
0
1
1
0
1
1
1
1
0
1
15
1
1
1
1
CLOCK
B
X
X
X
0
(TPB)
NOTES:
FIGURE 1.
1. 1 = High level, 0 = Low level, X = Don’t care.
2. Qn-1 = Enable remains in previous state.
4-41
CDP1853/3, CDP1853C/3
Static Electrical Specifications
CONDITIONS
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
V
V
DD
O
IN
PARAMETER
SYMBOL
(V)
(V)
(V)
MIN
MAX
MIN
-100
MAX
UNITS
µA
µA
mA
mA
mA
mA
V
Quiescent Device
Current
I
-
0, 5
5
-50
-
-
SS
(Note 1)
-
0, 10
10
5
-500
-
-
-1000
-
-
Output Low Drive
(Sink) Current
I
0.4
-
2.3
1.6
OL
0.5
-
10
5
3.7
-
2.6
-
Output High Drive
(Source) Current
I
4.6
-
-
-
-1.7
-3.7
0.1
0.1
-
-
-
-1.2
-2.6
0.2
0.2
-
OH
9.5
-
10
5
Output Voltage
Low-Level
V
-
0, 5
-
-
OL
(Note 2)
-
0, 10
10
5
-
-
V
Output Voltage
High-Level
V
-
0, 5
4.9
9.9
-
4.8
9.8
-
V
OH
(Note 2)
-
0, 10
10
5
-
-
V
Input Low Voltage
Input High Voltage
Input Leakage Low
Input Leakage High
V
0.8, 4.2
-
-
1.5
3
1.5
3
V
IL
IH
IL
1, 9
10
5
-
-
V
V
0.8, 4.2
-
3.5
7
-
3.5
7
-
V
1, 9
-
10
5
-
-
V
I
-
-
-
-
-
-
0
0
5
10
-
-1
-1
-
-
-5
-5
-
-
µA
µA
µA
µA
pF
pF
10
5
-
-
I
1
5
IH
10
-
-
1
-
5
Input Capacitance
Output Capacitance
NOTES:
C
(Note 2)
-
10
15
-
10
15
IN
C
(Note 2)
-
-
-
-
OUT
1. The CDP1853C meets all 5V static electrical characteristics of the CDP1853 except quiescent device current for which the limits are:
o
o
o
I
= -500µA at -55 C and +25 C and I = -1000µA at +125 C.
SS
SS
2. Guaranteed but not tested.
Dynamic Electrical Specifications See Figure 2, C = 100pF, t , t = 15ns
L
R F
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
Propagation Delay Time:
Chip Enable (CE) to Output High
SYMBOL
(V)
MIN
MAX
MIN
MAX
UNITS
ns
t
5
-
-
175
90
-
-
275
150
EOH
10
ns
4-42
CDP1853/3, CDP1853C/3
Dynamic Electrical Specifications See Figure 2, C = 100pF, t , t = 15ns
L
R F
LIMITS
o
o
o
-55 C, +25 C
+125 C
V
DD
PARAMETER
Disable to Output Low
SYMBOL
(V)
MIN
MAX
MIN
MAX
UNITS
ns
t
5
-
-
295
200
225
120
210
110
295
200
-
-
-
400
250
315
165
300
150
400
250
-
EOL
10
5
ns
N Input to Output
t
-
-
ns
NO
10
5
-
-
ns
Clock A to Output Low
Clock B to Output Low
t
t
-
-
ns
AO
BO
10
5
-
-
ns
-
-
ns
10
5
-
-
ns
Pulse Width:
t
t
50
25
50
25
75
50
75
50
ns
CACA
CBCB
Clock A
Clock B
10
5
-
-
ns
-
-
ns
10
-
-
ns
Recommended Operating Conditions At T = Full Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges:
LIMITS
CDP1853/3
CDP1853C/3
PARAMETER
DC Operating Voltage Range
Input voltage Range
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
V
V
V
V
V
DD
SS
DD
SS
4-43
CDP1853/3, CDP1853C/3
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
DD
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
(All Voltages Referenced to V Terminal)
CDP1853/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1853C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
SBDIP Package. . . . . . . . . . . . . . . . . .
Device Dissipation Per Output Transistor
85
22
SS
T = Full Package Temperature Range
A
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
+0.5V
(All Package Types). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
DD
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . ±10mA
Operating Temperature Range (T )
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
A
o
o
o
o
Storage Temperature Range (T
). . . . . . . . . . . .-65 C to +150 C
STG
Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 C
o
Timing Diagrams
CE
N0 - N2
OUTPUT 0 - 7
OUTPUT 0 - 7
T
T
T
EOH
EOL
N0
FIGURE 2A. N - INPUTS TO OUTPUTS DELAY TIME
FIGURE 2B. CE TO OUTPUT DELAY TIME
MIN. CLOCK A
T
CACA
PULSE WIDTH
MIN. CLOCK B
PULSE WIDTH
T
CBCB
CLOCK A
OUTPUT 0 - 7
CLOCK B
T
AO
OUTPUT 0 - 7
(SEE NOTE 1)
NOTE:
T
BO
1. To measure T , Clock B must be tied low.
AO
FIGURE 2D. CLOCK A TO OUTPUT DELAY TIME
FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS
FIGURE 2C. CLOCK B TO OUTPUT DELAY TIME
TPA
OUT 0
OUT 1
OUT 2
OUT 3
OUT 4
A
N0
N1
N2
CE
TPB
CE
B
C
EN
(NOTE 1)
CHIP ENABLE
OUTPUT
V
CLK B OUT 5
CLK A OUT 6
OUT 7
DD
NOTE:
1. Output enabled when EN = high. Internal signal shown for refer-
ence only (see Figure 1).
FIGURE 3. TIMING DIAGRAM
FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER
4-44
CDP1853/3, CDP1853C/3
CDP1802 CPU
TPA
TPB
N0 N1 N2 TPB MRD
V
DD
N0
CLOCK B CE
CDP1853
N2
N1
CLOCK A
0
1
2 - 6 7
READ VIA
6F INSTRUCTION
CS1 CS2
CS1 CS2
CDP1852
INPUT
PORT 7
CDP1852
OUTPUT
PORT 7
LOAD VIA
67 INSTRUCTION
DATA
DATA
DATA
AVAILABLE
SR
MODE TPB
MODE
STROBE
V
DD
CLOCK
5 CDP1852 INPUT AND OUTPUT PORTS
READ VIA
69 INSTRUCTION
CS2 CS1
CS1 CS2
CDP1852
OUTPUT
PORT 1
CDP1852
INPUT
PORT 1
LOAD VIA
61 INSTRUCTION
DATA
AVAILABLE
SR
MODE
STROBE
MODE TPB
V
DD
CLOCK
7 INPUT PORTS
7 OUTPUT PORTS
FIGURE 5. N-BIT DECODER IN A ONE LEVEL I/O SYSTEM
4-45
CDP1853/3, CDP1853C/3
CDP1800 SERIES
N0 N1 N2
TPA TPB
MRD BUS
DATA BUS
CL CS1
CDP1852
CS2
TPA
CDP1853
1
DECODED
“61” INSTRUCTION
CLOCK A
CLOCK B
CE
I/O
7 INPUT,
6 OUTPUT
PORTS
NO, N1, N2
CDP1853
“62 - 6F”
INST.
CLOCK A
CLOCK B
CE
I/O
7 INPUT,
6 OUTPUT
PORTS
NO, N1, N2
CDP1853
“62 - 6F”
INST.
SECTIONS 3 - 7
CLOCK A
CLOCK B
CE
I/O
7 INPUT,
6 OUTPUT
PORTS
NO, N1, N2
CDP1853
“62 - 6F”
INST.
NOTE:
1. System shown will select up to 56 input and 48 output ports. With additional decoding, the total number of input and output ports can be
further expanded.
FIGURE 6. TWO LEVEL I/O USING CDP1853 AND CDP1852
Bias/Static Burn-In Circuit
TYPE
V
TEMPERATURE
TIME
DD
V
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DD
o
CDP1853C
7V
+125 C
160 Hrs.
V
V
SS
DD
V
SS
NOTE:
1. All resistors are 47kΩ ±20%.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-46
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